WO2021208868A1 - 确定时钟的方法和相关装置 - Google Patents

确定时钟的方法和相关装置 Download PDF

Info

Publication number
WO2021208868A1
WO2021208868A1 PCT/CN2021/086705 CN2021086705W WO2021208868A1 WO 2021208868 A1 WO2021208868 A1 WO 2021208868A1 CN 2021086705 W CN2021086705 W CN 2021086705W WO 2021208868 A1 WO2021208868 A1 WO 2021208868A1
Authority
WO
WIPO (PCT)
Prior art keywords
clock
time
delay
network device
virtual clock
Prior art date
Application number
PCT/CN2021/086705
Other languages
English (en)
French (fr)
Inventor
石兴建
何涛
李�浩
曾晓意
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202010586995.XA external-priority patent/CN113541838A/zh
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP21789450.0A priority Critical patent/EP4123955A4/en
Publication of WO2021208868A1 publication Critical patent/WO2021208868A1/zh
Priority to US17/964,619 priority patent/US20230050042A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852—Delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/10—Active monitoring, e.g. heartbeat, ping or trace-route
    • H04L43/106—Active monitoring, e.g. heartbeat, ping or trace-route using time related information in packets, e.g. by adding timestamps

Definitions

  • This application relates to the field of communication technology, and more specifically, to a method and related device for determining a clock.
  • the time between the access network device 5G network required tolerances of less than 3 microseconds ([mu] S), synchronization accuracy of the network device and a network server clock time required is less than 1.5 ⁇ s.
  • the assisted partial timing support (APTS) function uses the global navigation satellite system (GNSS) to provide synchronization accuracy.
  • GNSS global navigation satellite system
  • the APTS solution is to deploy GNSS devices (such as global positioning system (GPS) receivers, Beidou receivers, etc.) in network equipment.
  • GPS global positioning system
  • Beidou receivers etc.
  • the network equipment tracks the clock time information of the GNSS device.
  • the clock time is synchronized to the ground communication network, for example, through the Precision Time Protocol (PTP) message method Realize frequency or phase synchronization; for example, synchronize to a clock source device upstream of the network by means of adaptive clock recovery (ACR)/adaptive time recovery (ATR).
  • PTP Precision Time Protocol
  • ACR adaptive clock recovery
  • ATR adaptive time recovery
  • This application provides a method and related device for determining a clock, which can simulate the clock of a network device.
  • an embodiment of the present application provides a method for determining a clock, which includes: in a case where the second network device and the first network device are synchronized with a reference clock, obtaining the difference between the second network device and the first network device Time delay information and frequency information of the clock of the second network device; determine the second virtual clock according to the frequency information; adjust the second virtual clock according to the delay information, wherein the adjusted second The virtual clock is synchronized with the first virtual clock, and the first virtual clock is used to simulate the clock of the first network device.
  • the above technical solution can simulate the clock of the second network device so as to use the simulated clock to perform subsequent operations.
  • the simulated clock can be used to estimate the synchronization performance of the PTP message of the second network device. Therefore, the PTP message synchronization performance of the second network device can be pre-judged before the GNSS failure occurs, and the network operation and maintenance activities can be guided.
  • the delay information includes N delays, and the N delays are N delays from the second network device to the first network device, or N delays from the first network device
  • the delay to the second network device, N is a positive integer greater than or equal to 2
  • the method further includes: obtaining N first time stamps generated by the first virtual clock
  • the adjustment of the second virtual clock includes: obtaining N second time stamps generated by the second virtual clock according to the N time delays and the N first time stamps, the N second time stamps and the N time time stamps Delay one-to-one correspondence; according to the N second time stamps and the N first time stamps, the frequency of the second virtual clock is adjusted.
  • the delay information includes forward delay and reverse delay, where the forward delay is the delay from the first network device to the second network device, and the reverse delay Is the time delay from the second network device to the first network device, the method further includes: obtaining a third time stamp and a sixth time stamp generated by the first virtual clock; obtaining a fourth time stamp and a fourth time stamp generated by the second virtual clock; The fifth time stamp; the adjusting the second virtual clock according to the time delay information includes: determining the first time delay according to the forward time delay, the third time stamp, and the fourth time stamp; The second time delay is determined by the reverse time delay, the fifth time stamp, and the sixth time stamp; and the phase of the second virtual clock is adjusted according to the first time delay and the second time delay.
  • the phase of the simulated clock of the second network device can be synchronized with the phase of the virtual clock of the first network device.
  • determining the first delay according to the forward delay, the third timestamp, and the fourth timestamp includes: determining the first delay according to the following formula:
  • D 1 is the first time delay
  • D f is the forward time delay
  • T 3 is the third time stamp
  • T 4 is the fourth time stamp
  • the determining the second delay according to the reverse delay, the fifth timestamp, and the sixth timestamp includes: determining the second delay according to the following formula:
  • D 2 is the second time delay
  • D b is the reverse time delay
  • T 5 is the fifth time stamp
  • T 6 is the sixth time stamp.
  • the time delay information includes a seventh time stamp, an eighth time stamp, a ninth time stamp, and a tenth time stamp;
  • the adjustment of the second virtual clock according to the time delay information includes : Adjust the eighth time stamp and the ninth time stamp according to the frequency information; according to the seventh time stamp, the adjusted eighth time stamp, the adjusted ninth time stamp and the tenth time Stamp, adjust the phase of the second virtual clock.
  • the method further includes: determining clock performance evaluation information according to the first virtual clock and the adjusted second virtual clock, where the clock performance evaluation information is used to indicate the clock time of the second virtual clock Recovery performance.
  • the second virtual clock can be used to obtain information for evaluating the clock time recovery performance of the second virtual clock, so that the obtained information can be used to evaluate the clock time recovery performance of the second virtual clock to guide network operation and maintenance activities.
  • the determining clock performance evaluation information according to the first virtual clock and the adjusted second virtual clock includes: determining the frequency F v1 of the first virtual clock and the adjusted second virtual clock.
  • the frequency of the clock F v2 ; according to F v1 and F v2 , the time interval error TIE is determined.
  • the determining clock performance evaluation information according to the first virtual clock and the adjusted second virtual clock includes: determining the generation timestamps T v1 and T v4 of the first virtual clock, and determining the adjustment The subsequent time stamps T v2 and T v3 generated by the second virtual clock; the time error TE is determined according to T v1 , T v2 , T v3 and T v4.
  • the above technical solution can obtain the phase recovery performance of the second virtual clock.
  • an embodiment of the present application provides an electronic device, which includes a unit for implementing the first aspect or any one of the possible designs of the first aspect.
  • an embodiment of the present application provides an electronic device, including: a processor, configured to be coupled with a memory, read and execute instructions and/or program codes in the memory, to execute such as the first aspect or the first aspect On the one hand, any possible design method.
  • an embodiment of the present application provides a chip system, including: a logic circuit configured to couple with an input/output interface, and transmit data through the input/output interface to execute the first aspect or the first aspect Any possible design method
  • the embodiments of the present application provide a computer-readable storage medium, the computer-readable medium stores program code, and when the computer program code runs on a computer, the computer executes the first aspect or the first aspect. Any possible design method.
  • Figure 1 is a schematic diagram of a system applying the technical solution of the present application.
  • Figure 2 is a schematic diagram of the principle of message time synchronization.
  • Figure 3 is a schematic diagram of the frequency synchronization process.
  • Fig. 4 is a schematic flowchart of a method for determining a clock according to an embodiment of the present application.
  • Fig. 5 is a schematic diagram of determining the frequency control word through two forward time delays.
  • Fig. 6 is a schematic flowchart of adjusting the phase of the virtual clock T-TSC according to an embodiment of the present application.
  • FIG. 7 is another schematic flowchart of adjusting the phase of the virtual clock T-TSC according to an embodiment of the present application.
  • Fig. 8 is a schematic flowchart of a method for determining a clock provided according to the present application.
  • Fig. 9 is a schematic structural block diagram of an electronic device according to an embodiment of the present application.
  • GSM Global System of Mobile Communication
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GSM Global System of Mobile Communication
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • UMTS Universal Mobile Telecommunication System
  • WiMAX Worldwide Interoperability for Microwave Access
  • 5G 5th Generation
  • 5NR New Radio
  • Clock synchronization includes two concepts: phase synchronization and frequency synchronization.
  • Frequency synchronization can also be called clock (clock) synchronization, which means that the frequency or phase between signals maintains a certain strict and specific relationship, and the signals appear at the same average rate at their corresponding effective instants to maintain All devices in the communication network operate at the same rate, that is, a constant phase difference between the signals is maintained.
  • clock clock
  • Phase synchronization can also be called time (time) synchronization, which means that the frequency and phase between the signals are kept consistent, that is, the phase difference between the signals is constant to zero.
  • the 1588v1 version was released in 2002 and is mainly used in the fields of industrial automation and test and measurement; in the field of telecommunications, with the development of Internet Protocol (IP) and the rise of the third generation (3 rd Generation, 3G) communication technology , The demand for time synchronization in telecommunication networks is becoming stronger and stronger.
  • IP Internet Protocol
  • 3G Third Generation
  • the IEEE organization revises 1588v1.
  • the first draft of IEEE 1588v2 was output in June 2006, and the revision was completed in 2007.
  • the IEEE 1588v2 standard was officially released at the end of 2008.
  • 1588v2 is called Precision Clock Synchronization Protocol for Networked Measurement and Control Systems (Precision Clock Synchronization Protocol for Networked Measurement and Control Systems), which is referred to as Precision Time Protocol (PTP) for short.
  • PTP Precision Time Protocol
  • 1588v2 was originally only used for high-precision time synchronization between devices, but it can also be used to achieve clock synchronization or time synchronization between devices.
  • the International Telecommunication Union Telecommunication Standardization Sector (ITU-T) defines the precision time protocol telecom profile for phase/time synchronization with full timing support from the network.
  • the ITU-T G.8275.1 protocol defines three basic clock node types: telecom grandmaster (T-GM), telecom boundary clock (T-BC), and telecom slave clock (telecom). time slave clock, T-TSC).
  • T-GM can only be a master device and provide a synchronized clock source.
  • the T-BC can have multiple clock ports.
  • the slave port can be synchronized with the clock information of the upstream device, and the master port can send clock information to the downstream device.
  • T-TSC can only be used as a slave device to synchronize the clock information of the upstream device.
  • a time synchronization network can be regarded as a spanning tree, and the master clock is the root node of the tree. The time of all nodes in the network is synchronized with the master clock.
  • the upstream node that sends the synchronization time is called the master device, and the downstream node that receives the synchronization time is called the slave device.
  • the network equipment referred to in the embodiments of the present application is a network equipment capable of providing clocks for access network equipment, baseband control unit (BBU), and remote radio unit (RRU).
  • BBU baseband control unit
  • RRU remote radio unit
  • it can be T-GM, T-BC, T-TSC, etc.
  • the 1588ACR network architecture mainly consists of three parts: 1588ACR master device, that is, packet master clock; 1588ACR slave device, that is packet slave clock; and the middle packet network, that is packet network (packet network).
  • the 1588ACR master device transmits the clock (frequency) signal to the 1588ACR slave device through the intermediate network through the 1588 message, and the 1588ACR slave device recovers the frequency of the 1588ACR master device according to the timestamp carried in the message.
  • the clock source of the 1588ACR master device can come from GNSS, or from the building integrated timing supply system (BITS) of the communication building, or even other synchronous digital hierarchy (SDH) synchronous networks or synchronous Ethernet. Network (synchronization Ethernet, SyncE).
  • the 1588ACR slave device recovers the clock of the 1588ACR master device according to the 1588v2 message to achieve frequency synchronization with the 1588ACR master device. Since the intermediate network will bring a certain delay and delay jitter when forwarding 1588v2 packets of the 1588ACR master device, it is equivalent to superimposing a certain amount on the time stamp of the 1588ACR master device when the 1588ACR slave device receives the packet. Noise, therefore, will affect the performance of the clock recovered from the 1588ACR slave device. The noise caused by different network loads and different forwarding paths is different, and the performance of 1588ACR recovery from the device is generally different.
  • the 1588ATR is an adaptive time synchronization solution mainly used in scenarios where 1588V2 hop-by-hop time synchronization is not supported across intermediate networks.
  • frequency synchronization can be SyncE frequency synchronization or 1588ACR frequency synchronization
  • the 1588ATR slave device calculates the time deviation between the master and slave devices according to the timestamp carried in the message, and adjusts the real-time clock of the slave device (Real-time clock, RTC), realizes the time synchronization of the slave device with the time of the master device; the time synchronization performance is affected by the traffic load of the network traversing in the middle, the packet delay variation (PDV) introduced by factors such as the forwarding path, etc. Influence.
  • PDV packet delay variation
  • the access network device in the embodiment of the application may be a device used to communicate with terminal devices, and the access network device may be a global system of mobile communication (GSM) system or a code division multiple access (Code Division Multiple) system.
  • the base station (Base Transceiver Station, BTS) in Access, CDMA can also be the base station (NodeB, NB) in the Wideband Code Division Multiple Access (WCDMA) system, or the evolution of the LTE system Type base station (Evolutional NodeB, eNB or eNodeB), it can also be a wireless controller in Cloud Radio Access Network (CRAN) scenarios, or the access network device can be a relay station, access point, or vehicle-mounted device , Wearable devices, network devices in the future 5G network or network devices in the future evolved PLMN network, etc., which are not limited in the embodiment of the present application.
  • CRAN Cloud Radio Access Network
  • Figure 1 is a schematic diagram of a system applying the technical solution of the present application.
  • the system shown in Figure 1 includes T-GM 101, T-BC 102 and T-TSC 103.
  • the reference clock of T-GM 101 is a reference time reference clock (primary reference time clock, PRTC) 111.
  • PRTC primary reference time clock
  • the reference clock of the T-TSC 103 is the clock obtained by the GNSS device 112.
  • the T-TSC 103 is synchronized with the clock obtained by the GNSS device 112.
  • the T-TSC 103 can provide a clock for the access network device 132 and the RRU 133.
  • the reference clock of the T-BC 102 is the clock obtained by the GNSS device 113.
  • the T-BC 102 is synchronized with the clock obtained by the GNSS device 113.
  • the clock from GNSS 113 obtained by T-BC 102 is obtained through RRU 135.
  • the clock time information collected by the GNSS device 113 may be sent to the T-BC 102 through the RRU 135.
  • the T-BC 102 can provide a clock for the BBU 134.
  • the clock time information from the GNSS device 133 received by the RRU 135 may be used as the clock of the access network device 131.
  • the GNSS device 132 and the GNSS device 133 may be based on clock time information collected by different GNSS.
  • the GNSS device 132 uses clock time information collected by Beidou
  • the GNSS device 133 uses clock time information collected by GPS.
  • the GNSS device 132 uses the clock time information collected by GPS
  • the GNSS device 133 uses the clock time information collected by the Galileo satellite navigation system.
  • the GNSS device 133 and the GNSS device 132 may also collect clock time information based on the same GNSS.
  • both the GNSS device 132 and the GNSS device 132 can use the clock time information collected by Beidou.
  • both the GNSS device 132 and the GNSS device 133 can use the clock time information collected by GPS.
  • each network device in Figure 1 only provides a clock for one access network device, one BBU, or one RRU. However, each network device can provide clocks for multiple access network devices, multiple BBUs, and/or multiple RRUs.
  • FIG 2 is a schematic diagram of the principle of message time synchronization. As shown in Figure 2, the master device sends a synchronization message (Sync message) to the slave device at time t1. The synchronization message carries a t1 timestamp.
  • Sync message a synchronization message
  • the synchronization message carries a t1 timestamp.
  • the slave device receives the synchronization message at t2 and generates a time stamp t2 locally. In other words, when the slave device receives the synchronization message, it locally generates the time stamp t2. The slave device also extracts the t1 timestamp from the synchronization message.
  • the slave device sends a delay request (Delay_Request, Delay_Req) message to the master device at t3, and generates a t3 time stamp locally.
  • the master device receives the delay request message at time t4, generates a t4 timestamp locally, and then carries the t4 timestamp in a delay response (Delay_Response, Delay_Resp) message and sends it to the slave device.
  • Delay_Response Delay_Resp
  • the slave device After receiving the delayed response message, the slave device extracts the t4 timestamp from the delayed response message.
  • the slave device can use the four timestamps t1, t2, t3, and t4 to calculate the time deviation between the slave device and the master device, thereby adjusting its time to synchronize with the master device.
  • D S1 the path delay of the message from the master device to the slave device
  • D S2 the path delay of the message from the slave device to the master device
  • Offset the time deviation between the slave device and the master device
  • t2-t1 can be called forward delay
  • t4-t3 can be called reverse delay
  • Figure 3 is a schematic diagram of the frequency synchronization process. As shown in Figure 3, the master device and the slave device achieve frequency synchronization through synchronization messages.
  • the master device periodically sends synchronization messages to the slave device.
  • the synchronization message carries the time stamp of the sending time.
  • the slave device After receiving the synchronization message, the slave device generates a local time stamp and extracts the time stamp in the synchronization message.
  • the master device sends a synchronization message 0 to the slave device at time t1 0.
  • the slave device receives the synchronization message 0 at time t2 0 , generates a local time stamp t2 0 , and extracts the time stamp t1 0 from the synchronization message 0.
  • the master device sends a synchronization message 1 to the slave device at time t11.
  • Device 1 at time T2 receives a synchronization packet, generating a local time stamp T2, and from the synchronization message extracted from a time stamp T1 1, and so on.
  • the master device periodically sends synchronization messages to the slave device, regardless of the path delay change. If the frequency of the slave device and the frequency of the master device are synchronized, then in the same time interval, the master device and the slave device accumulate The time deviation is the same, namely:
  • t2 1 -t2 0 t1 1- t1 0
  • t2 2- t2 1 t1 2- t1 1
  • t2 n -t2 0 is greater than t1 n -t1 0 , it means that the frequency of the slave device is higher than that of the master device, and the frequency of the slave device needs to be lowered; otherwise, the frequency of the slave device needs to be increased.
  • the specific adjustment method can be adjusted using the proportional-integral-derivative (PID) control principle.
  • Frequency synchronization can also be implemented using t3 and t4.
  • the principle is the same as t1 and t2 described here. For brevity, it will not be repeated here.
  • T-GM and T-BC can be used as master devices, and T-BC and T-TSC can be used as slave devices.
  • the slave device can be T-BC or T-TSC.
  • the slave device can be T-TSC.
  • Fig. 4 is a schematic flowchart of a method for determining a clock according to an embodiment of the present application.
  • the method shown in FIG. 4 can be executed by a network device as a slave device, and can also be implemented by a device (for example, a chip, or a circuit, etc.) in the network device as a slave device.
  • a device for example, a chip, or a circuit, etc.
  • the T-GM is the network device as the master device
  • T-TSC is the network device as the slave device.
  • the T-TSC obtains the time delay information between the T-TSC and the T-GM when the T-GM and the T-TSC are synchronized with the reference clock.
  • the T-TSC adjusts the virtual clock T-TSC in the T-TSC according to the collected delay information, so that the virtual clock T-TSC is synchronized with the virtual clock T-GM.
  • the virtual clock T-GM is a clock used to simulate T-GM.
  • the delay information acquired by the T-TSC may include forward delay and reverse delay.
  • T-TSC can track 1588 messages between T-GM and T-TSC (for example, synchronization messages, delayed request messages, and delayed response messages shown in Figure 2 and Figure 3, which can also be referred to as PTP message), obtain the timestamp, and determine the forward delay (that is, the delay between T-GM to T-TSC) and the reverse delay (that is, T-TSC to T-GM) according to the acquired timestamp Time delay between).
  • the delay information recorded by the T-TSC may include multiple sets of information, and each set of information may include a forward delay and a reverse delay.
  • Table 1 shows multiple sets of information in the delay information collected by T-TSC.
  • T-TSC executes the process shown in Figure 2 N times in total, and collects N groups of information in the delay information.
  • the first group of information in the delay information collected by T-TSC includes forward delay 1 and reverse delay 1
  • the second group of information in the delay information includes forward delay 2 and reverse delay 2. And so on.
  • the manner of collecting the forward delay and the reverse delay of the T-TSC can refer to the process shown in FIG.
  • the information collected by T-TSC includes frequency information in addition to time delay information.
  • the frequency information is T-TSC clock frequency information. The specific function of this frequency information will be introduced later.
  • the T-TSC may use the acquired timestamp as the delay information.
  • Table 2 shows multiple sets of information in the delay information collected by T-TSC.
  • T-TSC executes the process shown in Figure 2 N times in total, and collects N groups of information in the delay information.
  • a second set of information includes delay information T1 2, T2 2, T3 2, and T4 2. And so on.
  • the manner of collecting the forward delay and the reverse delay of the T-TSC can refer to the process shown in FIG.
  • the clock of T-TSC is synchronized with GNSS.
  • the clock required for the operation of the T-TSC is referred to as the actual clock below.
  • the actual clock of T-TSC is synchronized with GNSS. Because it needs to be synchronized with GNSS, T-TSC needs a frequency control word to adjust the frequency of the actual clock so that the actual clock is synchronized with the GNSS.
  • the frequency information collected by T-TSC may be a frequency control word.
  • the frequency information collected by the T-TSC may also be clock source noise. Since the actual clock has clock source noise, the frequency control word needs to be used to adjust the frequency of the actual clock so that the actual clock is synchronized with the GNSS. Therefore, the frequency control word and clock source noise can be corresponding.
  • a set of information collected by T-TSC may include delay information and frequency information.
  • T-TSC can collect frequency information in this time period when collecting time delay information.
  • T-TSC There can be two virtual clocks in the T-TSC, namely the virtual clock T-TSC and the virtual clock T-GM.
  • the virtual clock may include a virtual direct digital synthesizer (DDS) and a virtual real time clock (RTC).
  • the virtual DDS generates a clock signal
  • the virtual RTC uses the clock signal generated by the virtual DDS as a working clock to generate time information (time stamp).
  • the format of the time information generated by the virtual RTC is 48 bit (bit) seconds (second, s) and 32 bit nanosecond (nanosecond, ns).
  • the time information can be converted into year, month, day, hour, minute, and second.
  • the time information generated by the virtual RTC is represented by year, month, day, hour, minute, and second in the following.
  • the virtual clock T-GM is the actual clock used for the virtual T-GM.
  • the clock of T-GM is synchronized with PRTC. Therefore, it can be considered that the actual clock of T-GM is an ideal clock. Therefore, the clock signal generated by the virtual clock T-GM can be an ideal clock signal.
  • the clock signal generated by the virtual clock T-TSC is determined according to the collected frequency information and the ideal clock signal.
  • the clock signal generated by the virtual clock T-TSC is the ideal clock signal superimposed on the clock source noise. Therefore, as described above, if the frequency information collected by the T-TSC is clock source noise, the T-TSC can directly use the clock source noise to determine the clock signal generated by the virtual clock T-TSC. If the frequency information collected by the T-TSC is a frequency control word, then the frequency control word needs to be converted into clock source noise, and then the clock signal generated by the virtual T-TSC is determined according to the clock source noise.
  • T-TSC can use the collected delay information, the time stamp generated by the virtual clock T-GM, and the time stamp generated by the virtual clock T-TSC to adjust the virtual clock T-TSC, so that the virtual clock T-TSC and the virtual The clock is synchronized with T-GM.
  • Fig. 5 is a schematic flowchart of adjusting the frequency of the virtual clock T-TSC according to an embodiment of the present application.
  • Step 501 Obtain the time stamp T1 1 generated by the virtual clock T-GM.
  • step 502 after the forward time delay 1 has elapsed with T1 1 as the starting time, the current time stamp of the virtual clock T-TSC is recorded as T2 1 .
  • Step 503 Obtain the time stamp T1 2 generated by the virtual clock T-GM.
  • Step 504 Tl 2 in order to delay the starting time over the forward 2, when recording the current virtual clock timestamp T-TSC as T2 2.
  • Step 505 Adjust the frequency of the virtual clock T-TSC according to T1 1 , T1 2 , T2 1 and T2 2.
  • T2 2 -T2 1 is greater than T1 2 -T1 1 , slow down the frequency of the virtual clock T-TSC. If T2 2 -T2 1 is less than T1 2 -T1 1 , the frequency of the virtual clock T-TSC is increased.
  • the method for determining the frequency adjustment can be determined by the PID control method. For example, the PID control can be used to determine the frequency control word F 2_1 , and the frequency control word is used to adjust the frequency of the virtual clock T-TSC. The specific process of determining the frequency control word will not be repeated here.
  • Fig. 5 is a schematic diagram of determining the frequency control word through two forward time delays.
  • two reverse time delays can also be used to determine the frequency control word.
  • the determination process is opposite to that shown in Figure 5.
  • the time stamp of the virtual clock T-TSC is obtained as T3 1
  • the reverse time delay 1 starts with T3 1 as the starting time
  • the current time stamp of the virtual clock T-GM is recorded as T4 1
  • the virtual clock T-TSC is obtained 2 as a time stamp T3, T3 and then to 2 over the reverse time starting after delay 2, the recording current virtual clock timestamp T-GM 2 as T4; according T3 1, T3 2, T4 1 and 2 T4, generated Frequency control word.
  • the manner of determining the frequency control word may also be determined by using more than two forward delays or more than two reverse delays.
  • the specific determination method is similar to the method of using two forward delays or two reverse delays. For brevity, details are omitted here.
  • the time delay information collected by T-TSC can be forward time delay and reverse time delay.
  • the collected forward time delay or reverse time delay can be directly used to determine the frequency control word. If a group of information in the delay information collected by T-TSC is four timestamps, you can first determine the forward delay or the reverse delay according to the four timestamps collected, and then use the determined delay Determine the frequency control word.
  • Fig. 6 is a schematic flowchart of adjusting the phase of the virtual clock T-TSC according to an embodiment of the present application.
  • Step 601 Obtain time stamps T1, T2, T3, and T4.
  • the time stamps T1 and T4 are generated by the virtual clock T-GM, and the time stamps T2 and T3 are generated by the virtual clock T-TSC.
  • the time stamp T1 generated by the virtual clock T-GM is obtained, and then after one packet transmission interval has elapsed, the time stamp T2 generated by the virtual clock T-TSC is recorded.
  • the time stamp T3 generated by the virtual clock T-TSC is recorded, and then after a packet transmission interval has elapsed, the time stamp T4 generated by the virtual clock T-GM is recorded.
  • the virtual clock T-GM can generate time stamps T1, T2', T3', and T4, and then superimpose the collected clock source noise on T2' and T3' to obtain time stamps T2 and T3.
  • Step 602 Determine the first delay according to the forward delay, the time stamp T1 and the time stamp T2; and determine the second delay according to the reverse delay, the time stamp T3 and the time stamp T4.
  • the first delay can be determined according to the following formula:
  • D 1 is the first time delay
  • D f is the forward time delay
  • T 1 is the time stamp T1
  • T 2 is the time stamp T2.
  • the forward and reverse delays in formula 6.1 and formula 6.2 may be the forward and reverse delays included in the delay information.
  • the delay information collected by T-TSC is the forward and reverse delay.
  • the forward and reverse delays in Formula 6.1 and Formula 6.2 are calculated based on the four time stamps collected by T-TSC.
  • the second delay can be determined according to the following formula:
  • D 2 is the second time delay
  • D b is the reverse time delay
  • T 3 is the time stamp T3
  • T 4 is the time stamp T4.
  • Step 603 Adjust the phase of the virtual clock T-TSC according to the first time delay and the second time delay.
  • phase adjustment parameters can be determined according to the following formula:
  • T Offset represents the phase adjustment parameter
  • D 1 represents the first time delay
  • D 2 represents the second time delay
  • FIG. 7 is another schematic flowchart of adjusting the phase of the virtual clock T-TSC according to an embodiment of the present application.
  • the time delay information collected by the T-TSC is four timestamps instead of forward and reverse delays.
  • Step 701 Obtain time stamps T1, T2, T3, and T4 included in the time delay information.
  • Step 702 Adjust the time stamps T2 and T3 according to the frequency information to obtain the time stamp T2' and the time stamp T3'.
  • adjusting the time stamps T2 and T3 may include: superimposing the clock source noise corresponding to the frequency information on the basis of the time stamp T2 to obtain the time stamp T2'; superimposing on the basis of the time stamp T3 corresponds to The clock source noise of the frequency information obtains the time stamp T3'.
  • Step 703 Determine the third delay according to the forward delay, the time stamp T1 and the time stamp T2'; and determine the fourth delay according to the reverse delay, the time stamp T3' and the time stamp T4.
  • the third delay can be determined according to the following formula:
  • D 3 is the third period
  • T 1 is the time stamp T1
  • the fourth delay can be determined according to the following formula:
  • D 4 second time delay, T 3 'timestamp T3', T 4 is a time stamp T4.
  • Step 704 Adjust the phase of the virtual clock T-TSC according to the third time delay and the fourth time delay.
  • phase adjustment parameters can be determined according to the following formula:
  • T Offset represents the phase adjustment parameter
  • D 3 represents the third time delay
  • D 4 represents the fourth time delay.
  • the third time delay and the fourth time delay need to be determined according to T1, T2', T3', and T4, and then the phase adjustment parameter is determined.
  • the phase adjustment parameter can be determined directly based on T1, T2', T3', and T4.
  • the phase adjustment parameter can be determined according to formula 7.4:
  • phase adjustment parameters can be determined according to the following formula:
  • T Offset [(T 2 ' -T 1) - (T 4 -T 3')] / 2, ( Equation 7.3)
  • T 1 is the time stamp T1
  • T 2 ' is the timestamp T2'
  • T 4 is a time stamp T4.
  • the delay information used for adjusting the phase in FIG. 6 and FIG. 7 is a forward delay, a reverse delay, or a time stamp included in the same set of delay information.
  • the clock performance evaluation information can be determined according to the virtual clock T-GM and the adjusted virtual clock T-TSC.
  • the clock information evaluation information is used to indicate the clock time recovery of the virtual clock T-TSC performance.
  • the clock performance evaluation information may include one or more of time interval error (TIE) and time error (TE).
  • the clock performance evaluation information may also include one or more of maximum time interval error (MTIE), time deviation (TDEV), and maximum absolute time error (max
  • TIE time interval error
  • TE time error
  • MTIE maximum time interval error
  • TDEV time deviation
  • maximum absolute time error
  • the frequency F v1 of the virtual clock T-GM and the adjusted frequency F v2 of the virtual clock T-TSC can be determined; and the TIE is determined according to F v1 and F v2.
  • the generation timestamps T v1 and T v4 of the virtual clock T-GM can be determined, and the timestamps T v2 and T v3 generated by the adjusted virtual clock T-TSC can be determined; according to T v1 , T v2 , T v3 and T v4 , confirm TE.
  • T v1 , T v2 , T v3 and T v4 can be obtained in the following ways: obtain the timestamp T v1 generated by the virtual clock T-GM, and then after 1 packet transmission interval (1 is a positive integer greater than or equal to 1), record The time stamp T v2 generated by the virtual clock T-TSC. After a preset time interval has elapsed, the time stamp T v3 generated by the virtual clock T-TSC is recorded, and then after 1 packet transmission interval, the time stamp T v4 generated by the virtual clock T-GM is recorded.
  • can be determined based on TE and TIE statistics obtained over a period of time.
  • MTIE is the maximum value of TIE obtained by statistics in a period of time
  • is the maximum value of TE obtained by statistics in a period of time.
  • the determined clock performance evaluation information can be sent to the computer device.
  • the administrator can obtain the clock performance evaluation information through the computer device.
  • the embodiment of the present application can collect the delay information and the clock source noise of the T-TSC device when the reference clock is working normally, and use the collected delay information and the clock source noise to simulate the T-TSC clock.
  • the PTP message synchronization performance of the T-TSC can be estimated by using the simulated T-TSC clock. Therefore, it is possible to prejudge the synchronization performance of the PTP messages of the T-TSC before the failure of the GNSS, and guide the network operation and maintenance activities.
  • time delay information of several days can be collected, and the collected time delay information can be used to evaluate the clock time recovery performance of the T-TSC in a short time (for example, a few minutes). The entire process can automatically output the evaluation results without exporting the collected data, reducing the participation of operation and maintenance personnel, and the evaluation cost is lower.
  • the embodiment of the present application does not limit the type of the clock source.
  • the type of the clock source may be a crystal oscillator, a rubidium clock, or other types of oscillators.
  • the message synchronization performance evaluation of T-TSC is realized by using a virtual clock, and the generated clock signal is used to evaluate the message synchronization performance of T-TSC, so it will not affect the normal operation of T-TSC.
  • the methods shown in FIGS. 4 to 7 can be implemented by a network device as a slave device (for example, T-TSC or T-BC as a slave device) or components in the network device, and can also be implemented by other computer devices.
  • a network device for example, T-TSC or T-BC as a slave device
  • it may be implemented by other computer equipment (for example, a computer equipment (which may be a personal computer or a server, etc.) as a management equipment) or a component in a computer equipment.
  • the network device of the slave device collects the delay information and the frequency information of the actual clock of the slave device, and sends the collected information to the computer device.
  • the computer device determines the virtual clock T-TSC and the virtual clock T-GM according to the acquired information, and uses The determined virtual clock T-TSC is used to evaluate the clock time recovery performance of the slave device.
  • Fig. 8 is a schematic flowchart of a method for determining a clock provided according to the present application.
  • the method shown in FIG. 8 can be executed by a network device as a slave device or a component (such as a chip, circuit, etc.) in a network device, or a computer device (such as a computer device as a management device) or a component in a computer device ( (For example, chip, circuit, etc.) execution.
  • the second network device and the first network device are synchronized with the reference clock, obtain the time delay information between the second network device and the first network device and the frequency information of the clock of the second network device .
  • the second network device may be a network device that executes the method shown in FIG. 8.
  • the delay information includes N delays, and the N delays are N delays from the second network device to the first network device, or N delays from the first network device to the second network device.
  • N is a positive integer greater than or equal to 2; the method further includes: obtaining N first timestamps generated by the first virtual clock; and performing processing on the second virtual clock according to the delay information
  • the adjustment includes: obtaining N second time stamps generated by the second virtual clock according to the N time delays and the N first time stamps, and the N second time stamps and the N time delays correspond one-to-one ; According to the N second time stamps and the N first time stamps, the frequency of the second virtual clock is adjusted.
  • the delay information includes a forward delay and a reverse delay, where the forward delay is the delay from the first network device to the second network device, and the reverse delay is the second network device.
  • the method further includes: obtaining a third time stamp and a sixth time stamp generated by the first virtual clock; and obtaining a fourth time stamp and a fifth time stamp generated by the second virtual clock.
  • the adjustment of the second virtual clock according to the delay information includes: determining the first delay according to the forward delay, the third time stamp, and the fourth time stamp; according to the reverse time delay , The fifth time stamp and the sixth time stamp, determine the second time delay; according to the first time delay and the second time delay, adjust the phase of the second virtual clock.
  • the time delay information includes a seventh time stamp, an eighth time stamp, a ninth time stamp, and a tenth time stamp;
  • the adjusting the second virtual clock according to the time delay information includes: according to the frequency Information, the eighth time stamp and the ninth time stamp are adjusted; according to the seventh time stamp, the adjusted eighth time stamp, the adjusted ninth time stamp, and the tenth time stamp, the The phase of the second virtual clock is adjusted.
  • the method further includes: determining clock performance evaluation information according to the first virtual clock and the adjusted second virtual clock, where the clock performance evaluation information is used to indicate the clock time recovery performance of the second virtual clock.
  • the determining clock performance evaluation information according to the first virtual clock and the adjusted second virtual clock includes: determining the frequency F v1 of the first virtual clock and the adjusted frequency F of the second virtual clock v2 ; Determine the time interval error TIE according to F v1 and F v2.
  • the determining clock performance evaluation information according to the first virtual clock and the adjusted second virtual clock includes: determining the generation timestamps T v1 and T v4 of the first virtual clock, and determining the adjusted second virtual clock Two timestamps T v2 and T v3 generated by the virtual clock; determine the time error TE according to T v1 , T v2 , T v3 and T v4.
  • Fig. 9 is a schematic structural block diagram of an electronic device according to an embodiment of the present application.
  • the electronic device 900 shown in FIG. 9 includes an acquiring unit 901 and a processing unit 902.
  • the electronic device 900 can execute each step of the foregoing method embodiment.
  • the electronic device 900 may be a network device or a computer device.
  • the obtaining unit 901 is configured to obtain the time delay information between the second network device and the first network device and the time delay information of the second network device when the second network device and the first network device are synchronized with the reference clock. Clock frequency information.
  • the processing unit 902 may be configured to determine the second virtual clock according to the frequency information.
  • the processing unit 902 is further configured to adjust the second virtual clock according to the delay information, wherein the adjusted second virtual clock is synchronized with the first virtual clock, and the first virtual clock is used to simulate the first network The clock of the device.
  • the delay information includes N delays, and the N delays are N delays from the second network device to the first network device, or N delays from the first network device to the first network device.
  • the time delay of the second network device, N is a positive integer greater than or equal to 2;
  • the obtaining unit 901 is also configured to obtain N first time stamps generated by the first virtual clock;
  • the processing unit 902 is specifically configured to obtain N first time stamps according to the N Time delays and the N first time stamps, obtain N second time stamps generated by the second virtual clock, and the N second time stamps correspond to the N time delays one-to-one; according to the N second time stamps
  • the time stamp and the N first time stamps adjust the frequency of the second virtual clock.
  • the delay information includes forward delay and reverse delay, where the forward delay is the delay from the first network device to the second network device, and the reverse delay is the The time delay from the second network device to the first network device, the obtaining unit 901, is further configured to obtain the third time stamp and the sixth time stamp generated by the first virtual clock; and obtain the fourth time stamp and the sixth time stamp generated by the second virtual clock.
  • the fifth time stamp; the processing unit 902 is specifically configured to determine the first time delay according to the forward time delay, the third time stamp, and the fourth time stamp; according to the reverse time delay, the fifth time stamp, and the The sixth time stamp determines the second time delay; according to the first time delay and the second time delay, the phase of the second virtual clock is adjusted.
  • the time delay information includes a seventh time stamp, an eighth time stamp, a ninth time stamp, and a tenth time stamp;
  • the ninth time stamp is adjusted; the phase of the second virtual clock is adjusted according to the seventh time stamp, the adjusted eighth time stamp, the adjusted ninth time stamp, and the tenth time stamp.
  • the processing unit 902 is further configured to determine clock performance evaluation information according to the first virtual clock and the adjusted second virtual clock, where the clock performance evaluation information is used to indicate the clock time of the second virtual clock Recovery performance.
  • the processing unit 902 is specifically configured to determine the frequency F v1 of the first virtual clock and the adjusted frequency F v2 of the second virtual clock; and determine the time interval error TIE according to F v1 and F v2.
  • the processing unit 902 is specifically configured to determine the generation timestamps T v1 and T v4 of the first virtual clock, and determine the adjusted timestamps T v2 and T v3 generated by the second virtual clock; v1 , T v2 , T v3 and T v4 , determine the time error TE.
  • the acquiring unit 901 may be a communication interface in the network device, and the processing unit 902 may be a processor of the network device.
  • the acquiring unit 901 may be a receiver, and the receiver may be used to receive related information (for example, delay information, frequency information, etc.) from the second network device.
  • the processing unit 902 may be a processor of a computer device.
  • the above electronic device 900 may also be a chip.
  • the electronic device may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), or It is a central processor unit (CPU), a network processor (NP), a digital signal processing circuit (digital signal processor, DSP), or a microcontroller (microcontroller unit).
  • MCU programmable logic device
  • PLD programmable logic device
  • the acquiring unit 901 may be an input/output circuit or a communication interface
  • the processing unit 902 may be a processor or an integrated circuit integrated on the chip.
  • An embodiment of the present application also provides an electronic device, the electronic device includes a processor, and the processor is configured to be coupled with a memory to read and execute instructions and/or program codes in the memory to execute any one of the implementations in the foregoing embodiments. The method described in the example.
  • the embodiment of the present application also provides a chip system, the chip system includes a logic circuit, the logic circuit is configured to be coupled with an input/output interface, through the input/output interface to transmit data, so as to implement any of the above embodiments The method described.
  • each step of the above method can be completed by an integrated logic circuit of hardware in the processor or instructions or program codes in the form of software.
  • the steps of the method disclosed in combination with the embodiments of the present application may be directly embodied as being executed and completed by a hardware processor, or executed and completed by a combination of hardware and software modules in the processor.
  • the software module can be located in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, registers.
  • the storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware. To avoid repetition, it will not be described in detail here.
  • the processor in the embodiment of the present application may be an integrated circuit chip with signal processing capability.
  • the steps of the foregoing method embodiments may be completed by an integrated logic circuit of hardware in a processor or instructions or program codes in the form of software.
  • the general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed and completed by a hardware decoding processor, or executed and completed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, registers.
  • the storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.
  • the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory can be read-only memory (ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), and electrically available Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • the volatile memory may be random access memory (RAM), which is used as an external cache.
  • RAM random access memory
  • static random access memory static random access memory
  • dynamic RAM dynamic RAM
  • DRAM dynamic random access memory
  • synchronous dynamic random access memory synchronous DRAM, SDRAM
  • double data rate synchronous dynamic random access memory double data rate SDRAM, DDR SDRAM
  • enhanced synchronous dynamic random access memory enhanced SDRAM, ESDRAM
  • synchronous connection dynamic random access memory serial DRAM, SLDRAM
  • direct rambus RAM direct rambus RAM
  • the present application also provides a computer program product, the computer program product includes: computer program code, when the computer program code runs on a computer, the computer executes any one of the above embodiments Example method.
  • the present application also provides a computer-readable medium that stores program code, and when the program code runs on a computer, the computer executes any one of the above-mentioned embodiments. Example method.
  • the present application also provides a system, which includes the aforementioned second network device and the first network device.
  • the disclosed system, device, and method can be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of the present application essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions or program codes are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program code .

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Environmental & Geological Engineering (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

本申请提供一种确定时钟的方法和相关装置, 该方法包括: 在第二网络设备和第一网络设备均同步于基准时钟的情况下, 利用该第二网络设备和该第一网络设备之间的时延信息以及该第二网络设备的时钟的频率信息, 模拟出与第一虚拟时钟同步的第二虚拟时钟, 该第一虚拟时钟用于模拟该第一网络设备的时钟。上述技术方案可以模拟出第二网络设备的时钟, 以便利用模拟出的时钟进行后续操作, 例如可以利用模拟出的时钟对第二网络设备的PTP报文同步性能进行预估。从而可以在GNSS发生失效之前就可以对第二网络设备的PTP报文同步性能进行预先判断, 指导网络运维活动。

Description

确定时钟的方法和相关装置
本申请要求于2020年04月13日提交中国专利局、申请号为202010286753.9、申请名称为“评估网络报文同步性的方法及相关设备”,以及于2020年06月24日提交中国专利局、申请号为202010586995.X、申请名称为“确定时钟的方法和相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，更具体地，涉及确定时钟的方法和相关装置。
背景技术
在现代通信网络中，大多数电信业务的正常运行要求全网设备之间的频率或时间差异保持在合理的误差水平内，即网络时钟同步。不同网络设备之间的频率必须同步在一定精度之内，否则会导致接入网设备，或终端设备处理业务时会出现业务异常，例如滑码，掉线等等。而某些无线制式同时要求频率同步，和相位同步。
以第五代(5 th Generation，5G)通信网络为例，5G网络中的接入网设备之间的时间误差需要小于3微秒(μs)，网络设备与网络时钟时间服务器的同步精度需要小于1.5μs。
辅助部分定时(assisted partial timing support，APTS)功能借助全球卫星定位***(global navigation satellite system，GNSS)提供同步精度。APTS解决方案是在网络设备中部署GNSS装置(例如全球卫星定位***(global positioning system，GPS)接收器、北斗接收器等)。在GNSS装置正常时，网络设备跟踪GNSS装置的时钟时间信息。当GNSS装置出现问题(例如GNSS装置物理故障、GNSS信号受到干扰、欺骗或者丢失等)时，将时钟时间同步切换到地面通信网络，例如通过精密时间协议(Precision Time Protocol，PTP)报文的方式实现频率或相位同步；例如通过自适应时钟恢复(adaptive clock recovery，ACR)/自适应时间恢复(adaptive time recovery，ATR)的方式同步至网络上游的时钟源设备。
目前评估报文同步性能的方式包括通过下载设备采集的正反向时延数据进行同步性能的仿真分析，或将正反向时延数据导入到测试仪表的进行性能测试。这两种方式需要投入运维人员或者专业技术人员和专用测试仪表，并且无法快速获取评估结果，人力、物力、时间成本较高。
发明内容
本申请提供一种确定时钟的方法和相关装置，可以模拟网络设备的时钟。
第一方面，本申请实施例提供一种确定时钟的方法，包括：在第二网络设备和第一网络设备均同步于基准时钟的情况下，获取该第二网络设备和该第一网络设备之间的时延信息以及该第二网络设备的时钟的频率信息；根据该频率信息，确定第二虚拟时钟；根据该时延信息，对该第二虚拟时钟进行调整，其中调整后的该第二虚拟时钟与第一虚拟时钟同步，该第一虚拟时钟用于模拟该第一网络设备的时钟。上述技术方案可以模拟出第二网络 设备的时钟，以便利用模拟出的时钟进行后续操作，例如可以利用模拟出的时钟对第二网络设备的PTP报文同步性能进行预估。从而可以在GNSS发生失效之前就可以对第二网络设备的PTP报文同步性能进行预先判断，指导网络运维活动。
在一种可能的设计中，该时延信息包括N个时延，该N个时延为N个该第二网络设备到该第一网络设备的时延，或者，N个该第一网络设备到该第二网络设备的时延，N为大于或等于2的正整数；该方法还包括：获取该第一虚拟时钟产生的N个第一时间戳；该根据该时延信息，对该第二虚拟时钟进行调整，包括：根据该N个时延和该N个第一时间戳，获取该第二虚拟时钟产生的N个第二时间戳，该N个第二时间戳和该N个时延一一对应；根据该N个第二时间戳和该N个第一时间戳，对该第二虚拟时钟的频率进行调整。利用上述技术方案，可以使得模拟出的第二网络设备的时钟的频率同步于第一网络设备的虚拟时钟的频率。
在一种可能的设计中，根据该N个时延和该N个第一时间戳，获取该第二虚拟时钟产生的N个第二时间戳，包括：以该N个第一时间戳中的第n个时间戳为起始时刻，经过该N个时延中的第n个时延后，确定该第二虚拟时钟的时间戳为该N个第二时间戳中的第n个第二时间戳，n＝1,…,N。
在一种可能的设计中，该时延信息包括正向时延和反向时延，其中该正向时延为该第一网络设备到该第二网络设备的时延，该反向时延为该第二网络设备到该第一网络设备的时延，该方法还包括：获取第一虚拟时钟产生的第三时间戳和第六时间戳；获取第二虚拟时钟产生的第四时间戳和第五时间戳；该根据该时延信息，对该第二虚拟时钟进行调整，包括：根据该正向时延、该第三时间戳和该第四时间戳，确定第一时延；根据该反向时延、该第五时间戳和该第六时间戳，确定第二时延；根据该第一时延和该第二时延，对该第二虚拟时钟的相位进行调整。利用上述技术方案，可以使得模拟出的第二网络设备的时钟的相位同步于第一网络设备的虚拟时钟的相位。
在一种可能的设计中，根据该正向时延、该第三时间戳和该第四时间戳，确定第一时延，包括：根据以下公式确定该第一时延：
D 1＝D f+(T 4-T 3)，
其中，D 1为该第一时延，D f为该正向时延，T 3为该第三时间戳，T 4为该第四时间戳；
该根据该反向时延、该第五时间戳和该第六时间戳，确定第二时延，包括：根据以下公式确定该第二时延：
D 2＝D b+(T 6-T 5)，
其中，D 2为该第二时延，D b为该反向时延，T 5为该第五时间戳，T 6为该第六时间戳。
在一种可能的设计中，该时延信息包括第七时间戳、第八时间戳、第九时间戳和第十时间戳；该根据该时延信息，对该第二虚拟时钟进行调整，包括：根据该频率信息，对该第八时间戳和该第九时间戳进行调整；根据该第七时间戳、调整后的该第八时间戳、调整后的该第九时间戳和该第十时间戳，对该第二虚拟时钟的相位进行调整。利用上述技术方案，可以使得模拟出的第二网络设备的时钟的相位同步于第一网络设备的虚拟时钟的相位。
在一种可能的设计中，该方法还包括：根据该第一虚拟时钟和调整后的该第二虚拟时钟确定时钟性能评估信息，该时钟性能评估信息用于指示该第二虚拟时钟的时钟时间恢复 性能。上述技术方案利用第二虚拟时钟可以得到用于评估该第二虚拟时钟的时钟时间恢复性能的信息，从而可以利用得到的信息评估第二虚拟时钟的时钟时间恢复性能，以指导网络运维活动。
在一种可能的设计中，该根据该第一虚拟时钟和调整后的该第二虚拟时钟确定时钟性能评估信息，包括：确定该第一虚拟时钟的频率F v1和调整后的该第二虚拟时钟的频率F v2；根据F v1和F v2，确定时间间隔误差TIE。上述技术方案可以得到第二虚拟时钟的频率恢复性能。
在一种可能的设计中，该根据该第一虚拟时钟和调整后的该第二虚拟时钟确定时钟性能评估信息，包括：确定该第一虚拟时钟的产生时间戳T v1和T v4，确定调整后的该第二虚拟时钟产生的时间戳T v2和T v3；根据T v1、T v2、T v3和T v4，确定时间误差TE。上述技术方案可以得到第二虚拟时钟的相位恢复性能。
第二方面，本申请实施例提供一种电子设备，该电子设备包括用于实现第一方面或第一方面任一种可能的设计的单元。
第三方面，本申请实施例提供一种电子设备，包括：处理器，该处理器用于与存储器耦合，读取并执行该存储器中的指令和/或程序代码，以执行如第一方面或第一方面任一种可能的设计的方法。
第四方面，本申请实施例提供一种芯片***，包括：逻辑电路，该逻辑电路用于与输入/输出接口耦合，通过该输入/输出接口传输数据，以执行如第一方面或第一方面任一种可能的设计的方法
第五方面，本申请实施例提供一种计算机可读存储介质，该计算机可读介质存储有程序代码，当该计算机程序代码在计算机上运行时，使得计算机执行如第一方面或第一方面的任一种可能的设计的方法。
附图说明
图1是应用本申请技术方案的***的示意图。
图2是报文时间同步原理的示意图。
图3是频率同步过程的示意图。
图4是根据本申请实施例提供的确定时钟的方法的示意性流程图。
图5在是通过两个正向时延确定频率控制字的示意图。
图6是根据本申请实施例调整虚拟时钟T-TSC的相位的示意性流程图。
图7是根据本申请实施例另一调整虚拟时钟T-TSC的相位的示意性流程图。
图8是根据本申请所述提供的一种确定时钟的方法的示意性流程图。
图9是根据本申请实施例提供的一种电子设备的示意性结构框图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请实施例的技术方案可以应用于各种通信***，例如：全球移动通讯(Global System of Mobile communication，GSM)***、码分多址(Code Division Multiple Access，CDMA)***、宽带码分多址(Wideband Code Division Multiple Access，WCDMA)***、通用分组无线业务(General Packet Radio Service，GPRS)、长期演进(Long Term Evolution，LTE)***、LTE频分双工(Frequency Division Duplex，FDD)***、LTE时分双工(Time  Division Duplex，TDD)、通用移动通信***(Universal Mobile Telecommunication System，UMTS)、全球互联微波接入(Worldwide Interoperability for Microwave Access，WiMAX)通信***、未来的第五代(5th Generation，5G)***或新无线(New Radio，NR)等。
为了便于本领域技术人员更好地理解本申请技术方案，首先对本申请技术方案涉及到的一些概念进行简单介绍。
1，时钟同步
时钟同步包括相位同步和频率同步两个概念。
频率同步(frequency synchronization)也可以称为时钟(clock)同步，是指信号之间的频率或相位上保持某种严格的特定关系，信号在其相对应的有效瞬间以同一平均速率出现，以维持通信网络中所有的设备以相同的速率运行，即信号之间保持恒定相位差。
相位同步(phase synchronization)也可以称为时间(time)同步，是指信号之间的频率和相位都保持一致，即信号之间相位差恒定为零。
2，1588
1588是由电气和电子工程师协会(Institute of Electrical and Electronics Engineers，IEEE)定义的。
1588v1版本于2002年发布，主要应用于工业自动化和测试测量领域；在电信领域，随着网络互联网协议(Internet Protocol，IP)化的发展以及第三代(3 rd Generation，3G)通信技术的兴起，电信网络对时间同步的需求越来越强烈。IEEE组织对1588v1进行重新修订。在2006年6月输出了IEEE 1588v2初稿，2007年完成修订，2008年年底正式发布IEEE 1588v2标准。
1588v2的全称为网络测量和控制***的精密时钟同步协议(Precision Clock Synchronization Protocol for Networked Measurement and Control Systems)，简称精密时间协议(Precision Time Protocol，PTP)。1588v2本来只是用于设备之间的高精度时间同步，但也可以用来实现设备之间的时钟同步或时间同步。
3，ITU-T G.8275.1
国际电信联盟电信标准分局(International Telecommunication Union Telecommunication Standardization Sector，ITU-T)定义了电信级全网精确时间同步协议(Precision time protocol telecom profile for phase/time synchronization with full timing support from the network)。
ITU-T G.8275.1协议定义了三种基本的时钟节点类型：电信级主时钟(telecom grandmaster，T-GM)、电信级边界时钟(telecom boundary clock，T-BC)、电信级从时钟(telecom time slave clock，T-TSC)。
T-GM只能做主(master)设备，提供同步的时钟源。
T-BC可以有多个时钟端口，其中从(slave)端口可以同步于上游设备的时钟信息，主(master)端口可以向下游设备发送时钟信息。
T-TSC只能做从(slave)设备，同步上游设备的时钟信息。
4，主时钟(grandmaster)，主(master)设备/从(slave)设备
时间同步网络可以被看成是一棵生成树，而主时钟是树的根节点，网络中所有节点的时间都与主时钟保持同步。
对于进行时间同步的一对节点，发送同步时间的上游节点被称之为主设备，而接收同步时间的下游节点被称之为从设备。
本申请实施例中所称的网络设备是能够为接入网设备、基带控制单元(baseband control unit，BBU)和射频拉远单元(remote radio unit，RRU)提供时钟的网络设备。例如，可以是T-GM、T-BC、T-TSC等。
5，1588ACR(PTP ACR)
1588ACR网络架构主要包含3部分：1588ACR主(master)设备，即分组主时钟(packet master clock)；1588ACR从(slave)设备，即分组从时钟(packet slave clocker)；中间的包网络，即分组网络(packet network)。1588ACR主设备将时钟(频率)信号通过1588报文经过中间网络传递给1588ACR从设备，1588ACR从设备根据报文中携带的时间戳恢复出1588ACR主设备的频率。1588ACR主设备的时钟源可以来自于GNSS，也可以来自于通信楼综合定时供给***(building integrated timing supply system，BITS)，甚至是其他的同步数字体系(synchronous digital hierarchy，SDH)同步网或者同步以太网(synchronization Ethernet，SyncE)。1588ACR从设备根据1588v2报文恢复出1588ACR主设备的时钟，实现和1588ACR主设备之间的频率同步。由于中间网络在转发1588ACR主设备的1588v2报文时，会带来一定的延时和延时抖动，相当于1588ACR从设备在收到报文时，在1588ACR主设备的时间戳上叠加了一定的噪声，因此会影响1588ACR从设备恢复的时钟性能。不同的网络负载、不同的转发路径带来的噪声都不一样，1588ACR从设备恢复的性能一般来说也有所差别。
6，1588ATR(PTP ATR)
1588ATR是主要应用于穿越中间网络不支持1588V2逐跳时间同步的场景的自适应时间同步方案。在频率同步的前提下(频率同步可以是SyncE频率同步，或1588ACR频率同步)，1588ATR从设备根据报文中携带的时间戳，计算主，从设备之间的时间偏差，调整从设备的实时时钟(real-time clock，RTC)，实现从设备的时间同步于主设备的时间；时间同步性能受中间穿越的网络的流量负载，转发路径等因素引入的包时延变化(packet delay variation，PDV)影响。
本申请实施例中的接入网设备可以是用于与终端设备通信的设备，该接入网设备可以是全球移动通讯(Global System of Mobile communication，GSM)***或码分多址(Code Division Multiple Access，CDMA)中的基站(Base Transceiver Station，BTS)，也可以是宽带码分多址(Wideband Code Division Multiple Access，WCDMA)***中的基站(NodeB，NB)，还可以是LTE***中的演进型基站(Evolutional NodeB，eNB或eNodeB)，还可以是云无线接入网络(Cloud Radio Access Network，CRAN)场景下的无线控制器，或者该接入网设备可以为中继站、接入点、车载设备、可穿戴设备以及未来5G网络中的网络设备或者未来演进的PLMN网络中的网络设备等，本申请实施例并不限定。
图1是应用本申请技术方案的***的示意图。如图1所示的***中包括T-GM 101，T-BC 102和T-TSC 103。
T-GM 101的基准时钟是基准定时参考时钟(primary reference time clock，PRTC)111。换句话说，T-GM 101与PRTC 111是同步的。
T-TSC 103的基准时钟是GNSS装置112获取到的时钟。T-TSC 103是与GNSS装置 112获取到的时钟是同步的。T-TSC 103可以为接入网设备132和RRU 133提供时钟。
T-BC 102的基准时钟是GNSS装置113获取到的时钟。T-BC 102是与GNSS装置113获取到的时钟是同步的。T-BC 102获取的来自于GNSS 113的时钟是通过RRU 135获取的。GNSS装置113采集到的时钟时间信息可以通过RRU 135发送至T-BC 102。T-BC 102可以为BBU 134提供时钟。
RRU 135接收到的来自于GNSS装置133的时钟时间信息可以作为接入网设备131的时钟。
GNSS装置132和GNSS装置133可以是基于不同的GNSS采集的时钟时间信息。例如GNSS装置132是利用北斗采集的时钟时间信息，GNSS装置133是利用GPS采集的时钟时间信息。又如，GNSS装置132是利用GPS采集的时钟时间信息，GNSS装置133是利用伽利略(Galileo)卫星导航***采集的时钟时间信息。
当然，GNSS装置133和GNSS装置132也可以基于相同的GNSS采集时钟时间信息。例如，GNSS装置132和GNSS装置132都可以利用北斗采集的时钟时间信息。又如，GNSS装置132和GNSS装置133都可以利用GPS采集的时钟时间信息。
为了便于描述，图1中的每个网络设备只为一个接入网设备、一个BBU或一个RRU提供时钟。但是，每个网络设备可以为多个接入网设备、多个BBU和/或多个RRU提供时钟。
图2是报文时间同步原理的示意图。如图2所示，主设备在t1时刻向从设备发送同步报文(Sync message)。该同步报文中携带t1时间戳。
从设备在t2时刻接收到该同步报文，并在本地产生时间戳t2。换句话说，从设备在接收到该同步报文的时刻，在本地产生时间戳t2。从设备还从该同步报文中提取t1时间戳。
从设备在t3时刻向主设备发送延迟请求(Delay_Request，Delay_Req)报文，并在本地产生t3时间戳。
主设备在t4时刻接收到该延迟请求报文，并在本地产生t4时间戳，然后将t4时间戳携带在延迟响应(Delay_Response，Delay_Resp)报文中发送给从设备。
从设备在接收到该延迟响应报文后，从该延迟响应报文中提取t4时间戳。
从设备可以利用t1、t2、t3和t4四个时间戳计算出从设备和主设备之间的时间偏差，从而调整自身的时间以实现和主设备时间同步。
具体地，假设报文从主设备到从设备的路径时延记为D S1，报文从从设备到主设备的路径时延记为D S2，从设备和主设备之间的时间偏差记为Offset。那么，D S1，D S2，Offset，t1，t2，t3和t4有如下关系：
t2-t1＝D S1+Offset，(公式2.1)
t4-t3＝D S2-Offset，(公式2.2)
根据1588V2协议可知，可以假设D S1＝D S2，那么Offset可以通过以下公式计算：
Offset＝[(t2-t1)-(t4-t3)]/2，(公式2.3)。
t2-t1可以称为正向时延，t4-t3可以称为反向时延。
图3是频率同步过程的示意图。如图3所示，主设备和从设备之间通过同步报文来实现频率同步。
如图3所示，主设备周期性的向从设备发送同步报文。同步报文中携带有发送时间的时间戳。从设备在接收到同步报文后，产生本地时间戳并提取同步报文中的时间戳。
例如，主设备在时刻t1 0向从设备发送同步报文0。从设备在时刻t2 0接收到同步报文0，产生本地时间戳t2 0，并从同步报文0中提取时间戳t1 0。主设备在时刻t1 1向从设备发送同步报文1。从设备在时刻t2 1接收到同步报文1，产生本地时间戳t2 1，并从同步报文1中提取时间戳t1 1，以此类推。
主设备周期性地给从设备发送同步报文，不考虑路径延时的变化，如果从设备的频率和主设备的频率是同步的，那么在相同的时间间隔内，主设备和从设备累计的时间偏差是相同的，即：
t2 1-t2 0＝t1 1-t1 0，t2 2-t2 1＝t1 2-t1 1，t2 3-t2 2＝t1 3-t1 2….依此类推，t2 n-t2 0＝t1 n-t1 0。
如果t2 n-t2 0大于t1 n-t1 0，说明从设备的频率比主设备高，则需要调低从设备的频率；反之则需要调高从设备的频率。具体调整的方式可以利用比例积分微分(proportional-integral-derivative，PID)控制原理进行调节。
频率同步也可以用t3，t4来实现，原理与此处描述的t1，t2相同，为了简洁，在此就不再赘述。
如上所述T-GM和T-BC可以作为主设备，T-BC和T-TSC可以作为从设备。例如，如果主设备为T-GM，那么从设备可以是T-BC或者T-TSC。如果主设备为T-BC那么从设备可以是T-TSC。
图4是根据本申请实施例提供的确定时钟的方法的示意性流程图。图4所示的方法可以由作为从设备的网络设备执行，也可以由作为从设备的网络设备内的装置(例如芯片、或电路等)实现。为了便于描述，以下实施例中假设T-GM是作为主设备的网络设备，T-TSC是作为从设备的网络设备。为了便于描述，以下以T-TSC作为执行主体对本申请方案进行介绍。
步骤401，T-TSC在T-GM和T-TSC都同步于基准时钟的情况下，获取T-TSC和T-GM之间的时延信息。
步骤402，T-TSC根据采集到的时延信息，对T-TSC中的虚拟时钟T-TSC进行调整，以使得虚拟时钟T-TSC同步于虚拟时钟T-GM。虚拟时钟T-GM是用于模拟T-GM的时钟。
下面对上述步骤401和步骤402进行详细介绍。
可选的，在一些实施例中，T-TSC获取的时延信息可以包括正向时延和反向时延。具体地，T-TSC可以跟踪T-GM和T-TSC之间的1588报文(例如图2和图3中所示的同步报文、延迟请求报文和延迟响应报文，也可以称为PTP报文)，获取时间戳，并根据获取到的时间戳确定正向时延(即T-GM到T-TSC之间的时延)以及反向时延(即T-TSC到T-GM之间的时延)。
T-TSC记录的时延信息可以包括多组信息，每组信息可以包括一个正向时延和一个反向时延。例如，表1示出了T-TSC采集到的时延信息中的多组信息。
表1
Figure PCTCN2021086705-appb-000001
如表1所示，T-TSC共执行N次如图2所示的过程，采集到了时延信息中的N组信息。T-TSC采集到的时延信息中的第一组信息包括正向时延1和反向时延1，时延信息中的第二组信息包括正向时延2和反向时延2，以此类推。T-TSC采集正向时延和反向时延的方式可以参考图2所示的过程，为了简洁，在此就不再赘述。
如表1所示，T-TSC采集的信息除了时延信息以外，还包括频率信息。该频率信息是T-TSC的时钟频率信息。该频率信息的具体作用会在稍后进行介绍。
可选的，在另一些实施例中，T-TSC可以将获取的时间戳作为时延信息。例如，表2示出了T-TSC采集到的时延信息中的多组信息。
表2
Figure PCTCN2021086705-appb-000002
如表2所示，T-TSC共执行N次如图2所示的过程，采集到了时延信息中的N组信息。T-TSC采集到的时延信息中的第一组信息包括T1 1，T2 1，T3 1和T4 1，时延信息中的第二组信息包括T1 2，T2 2，T3 2和T4 2。以此类推。T-TSC采集正向时延和反向时延的方式可以参考图2所示的过程，为了简洁，在此就不再赘述。
T-TSC的时钟是与GNSS同步的。为了区分T-TSC中虚拟的时钟，以下将T-TSC运行所需的时钟称为实际时钟。换句话说，T-TSC的实际时钟是与GNSS同步的。由于需要与GNSS同步，因此T-TSC需要频率控制字对实际时钟的频率进行调整，以使得实际时钟同步于GNSS。
在一些实施例中，T-TSC采集到的频率信息可以是频率控制字。在另一些实施例中，T-TSC采集到的频率信息也可以是时钟源噪声。由于实际时钟存在时钟源噪声，所以需要利用频率控制字对实际时钟的频率进行调整，以使得实际时钟同步于GNSS。因此，频率 控制字和时钟源噪声可以是对应的。
如表1和表2所示，T-TSC采集的一组信息中可以包括时延信息和频率信息。换句话说，T-TSC在采集时延信息的时可以采集这一时间段内的频率信息。
T-TSC中可以有两个虚拟时钟，即虚拟时钟T-TSC和虚拟时钟T-GM。
虚拟时钟可以包括虚拟直接数字式频率合成器(direct digital synthesizer，DDS)和虚拟实时时钟(real time clock，RTC)。虚拟DDS产生时钟信号，虚拟RTC以虚拟DDS产生的时钟信号作为工作时钟产生时间信息(时间戳)。虚拟RTC产生的时间信息的格式为48比特(bit)秒(second，s)和32bit纳秒(nanosecond，ns)。该时间信息可以转换为年月日时分秒。但是为了便于描述，以下以年月日时分秒表示虚拟RTC产生的时间信息。
如上所述，虚拟时钟T-GM是用于虚拟T-GM的实际时钟。T-GM的时钟是同步于PRTC的。因此，可以认为T-GM的实际时钟是一个理想的时钟。所以，虚拟时钟T-GM产生的时钟信号可以是理想时钟信号。
虚拟时钟T-TSC产生的时钟信号是根据采集到的频率信息和理想时钟信号确定的。虚拟时钟T-TSC产生的时钟信号是理想时钟信号叠加时钟源噪声产生的。因此，如上所述，如果T-TSC采集到的频率信息是时钟源噪声，那么T-TSC可以直接利用时钟源噪声确定虚拟时钟T-TSC产生的时钟信号。如果T-TSC采集到的频率信息为频率控制字，那么还需要将该频率控制字转换为时钟源噪声，然后再根据时钟源噪声确定虚拟T-TSC产生的时钟信号。
T-TSC可以利用采集到的时延信息，虚拟时钟T-GM产生的时间戳，以及虚拟时钟T-TSC产生的时间戳对虚拟时钟T-TSC进行调整，以使得虚拟时钟T-TSC与虚拟时钟T-GM同步。
下面结合图5对如何对虚拟时钟T-TSC的频率进行调整进行简单介绍。
图5是根据本申请实施例的调整虚拟时钟T-TSC的频率的示意性流程图。
步骤501，获取虚拟时钟T-GM产生的时间戳T1 1。
步骤502，在以T1 1为起始时刻经过正向时延1后，记录虚拟时钟T-TSC的当前时戳作为T2 1。
步骤503，获取虚拟时钟T-GM产生的时间戳T1 2。
步骤504，在以T1 2为起始时刻经过正向时延2后，记录虚拟时钟T-TSC的当前时戳作为T2 2。
步骤505，根据T1 1，T1 2，T2 1和T2 2，对虚拟时钟T-TSC的频率进行调整。
若T2 2-T2 1大于T1 2-T1 1，则调慢虚拟时钟T-TSC的频率。若T2 2-T2 1小于T1 2-T1 1，则加快虚拟时钟T-TSC的频率。确定对频率的调整方法可以利用PID控制的方法确定，例如可以利用PID控制确定频率控制字F 2_1，频率控制字用于对虚拟时钟T-TSC的频率进行调整。确定频率控制字具体过程在此就不再赘述。
图5在是通过两个正向时延确定频率控制字的示意图。在另一些实施例中，也可以利用两个反向时延确定频率控制字。确定过程与图5所示的方式相反。例如，获取虚拟时钟T-TSC时戳作为T3 1，然后在以T3 1为起始时刻经过反向时延1后，记录虚拟时钟T-GM当前时戳作为T4 1；获取虚拟时钟T-TSC时戳作为T3 2，然后在以T3 2为起始时刻经过反 向时延2后，记录虚拟时钟T-GM当前时戳作为T4 2；根据T3 1，T3 2，T4 1和T4 2，生成频率控制字。
在另一些实施例中，确定频率控制字的方式也可以利用两个以上的正向时延或者两个以上的反向时延确定。具体确定方式和利用两个正向时延或两个反向时延确定的方式相似，为了简洁，在此就不再赘述。
如上所述，T-TSC采集到的时延信息可以是正向时延和反向时延，在此情况下，可以直接利用采集到的正向时延或反向时延确定频率控制字。如果T-TSC采集到的时延信息中的一组信息是四个时间戳，则可以先根据采集到的四个时间戳确定正向时延或反向时延，然后在利用确定的时延确定频率控制字。
下面结合图6和图7对如何对虚拟时钟T-TSC的相位进行调整进行简单介绍。
图6是根据本申请实施例调整虚拟时钟T-TSC的相位的示意性流程图。
步骤601，获取时间戳T1、T2、T3和T4。
在一些实施例中，时间戳T1和T4是虚拟时钟T-GM产生的，时间戳T2和T3是虚拟时钟T-TSC产生的。例如，获取虚拟时钟T-GM产生的时间戳T1，然后经过1个发包间隔后，记录虚拟时钟T-TSC产生的时间戳T2。在经过一个预设时间间隔后记录虚拟时钟T-TSC产生的时间戳T3，然后经过1个发包间隔后，记录虚拟时钟T-GM产生的时间戳T4。
在另一些实施例中，虚拟时钟T-GM可以产生时间戳T1、T2’、T3’和T4，然后在T2’和T3’上叠加采集到的时钟源噪声，得到时间戳T2和T3。
步骤602，根据正向时延，时间戳T1和时间戳T2，确定第一时延；根据反向时延，时间戳T3和时间戳T4，确定第二时延。
第一时延可以根据以下公式确定：
D 1＝D f+(T 2-T 1)，(公式6.1)
其中，D 1为第一时延，D f为正向时延，T 1为时间戳T1，T 2为时间戳T2。
公式6.1和公式6.2中的正反向时延可以是时延信息中包括的正反向时延。换句话说，T-TSC采集到的时延信息就是正反向时延。在另一些实施例中，公式6.1和公式6.2中的正反向时延是根据T-TSC采集到的四个时间戳计算得到的。
第二时延可以根据以下公式确定：
D 2＝D b+(T 4-T 3)，(公式6.2)
其中，D 2为第二时延，D b为反向时延，T 3为时间戳T3，T 4为时间戳T4。
步骤603，根据该第一时延和该第二时延，对虚拟时钟T-TSC的相位进行调整。
可选的，可以根据以下公式确定相位调整参数：
T Offset＝(D 1-D 2)/2，(公式6.3)
其中T Offset表示该相位调整参数，D 1表示该第一时延，D 2表示该第二时延。在确定了相位调整参数后，可以将相位调整参数叠加到虚拟时钟T-TSC产生的时钟信号相位上。
图7是根据本申请实施例另一调整虚拟时钟T-TSC的相位的示意性流程图。图7所示的实施例中假设T-TSC采集到的时延信息是四个时间戳而非正反向时延。
步骤701，获取时延信息包括的时间戳T1、T2、T3和T4。
步骤702，根据频率信息，对时间戳T2和T3进行调整，得到时间戳T2’和时间戳T3’。
根据频率信息，对时间戳T2和T3进行调整可以包括：可以在时间戳T2的基础上叠加对应于该频率信息的时钟源噪声，得到时间戳T2’；在时间戳T3的基础上叠加对应于该频率信息的时钟源噪声，得到时间戳T3’。
步骤703，根据正向时延，时间戳T1和时间戳T2’，确定第三时延；根据反向时延，时间戳T3’和时间戳T4，确定第四时延。
第三时延可以根据以下公式确定：
D 3＝T 2’-T 1，(公式7.1)
其中，D 3为第三时延，T 1为时间戳T1，T 2’为时间戳T2’。
第四时延可以根据以下公式确定：
D 4＝T 4-T 3’，(公式7.2)
其中，D 4为第二时延，T 3’为时间戳T3’，T 4为时间戳T4。
步骤704，根据该第三时延和该第四时延，对虚拟时钟T-TSC的相位进行调整。
可选的，可以根据以下公式确定相位调整参数：
T Offset＝(D 3-D 4)/2，(公式7.3)
其中T Offset表示该相位调整参数，D 3表示该第三时延，D 4表示该第四时延。在确定了相位调整参数后，可以将相位调整参数叠加到虚拟时钟T-TSC产生的时钟信号相位上。
图7所示的过程中需要根据T1、T2’、T3’和T4先确定第三时延和第四时延，然后再确定该相位调整参数。在另一些实施例中，可以直接根据T1、T2’、T3’和T4确定该相位调整参数。例如可以根据公式7.4确定该相位调整参数：
可选的，可以根据以下公式确定相位调整参数：
T Offset＝[(T 2’-T 1)-(T 4-T 3’)]/2，(公式7.3)
其中T Offset表示该相位调整参数，T 1为时间戳T1，T 2’为时间戳T2’，T 3’为时间戳T3’，T 4为时间戳T4。
可以理解的是，图6和图7中用于调整相位的时延信息是同一组时延信息包括的正向时延、反向时延或者时间戳。
在对虚拟时钟T-TSC进行调整后，可以根据虚拟时钟T-GM和调整后的虚拟时钟T-TSC确定时钟性能评估信息，该时钟信息评估信息用于指示虚拟时钟T-TSC的时钟时间恢复性能。
例如，时钟性能评估信息可以包括时间间隔误差(time interval error，TIE)和时间误差(time error，TE)中的一个或多个。时钟性能评估信息还可以包括最大时间间隔误差(maximum time interval error，MTIE)、时间偏差(time deviation，TDEV)、最大绝对时间误差(maximum absolute time error，max|TE|)等中的一个或多个。
例如，可以确定虚拟时钟T-GM的频率F v1和调整后的虚拟时钟T-TSC的频率F v2；根据F v1和F v2，确定TIE。
又如，可以确定该虚拟时钟T-GM的产生时间戳T v1和T v4，确定调整后的虚拟时钟T-TSC产生的时间戳T v2和T v3；根据T v1、T v2、T v3和T v4，确定TE。
T v1、T v2、T v3和T v4可以通过以下方式获取：获取虚拟时钟T-GM产生的时间戳T v1，然后经过1个发包间隔后(1为大于或等于1的正整数)，记录虚拟时钟T-TSC产生的时间戳T v2。在经过一个预设时间间隔后记录虚拟时钟T-TSC产生的时间戳T v3，然后经过1 个发包间隔后，记录虚拟时钟T-GM产生的时间戳T v4。
MTIE、TEDV和Max|TE|可以根据一段时间内统计得到的TE和TIE确定。例如，MTIE是在一段时间内统计得到的TIE最大值，Max|TE|是一段时间内统计得到的TE的最大值。
确定的时钟性能评估信息可以发送给计算机设备。管理员可以通过该计算机设备获取该时钟性能评估信息。
本申请实施例可以在基准时钟工作正常的情况下采集时延信息及T-TSC设备的时钟源噪声，利用采集到的时延信息和时钟源噪声模拟T-TSC的时钟。利用模拟的T-TSC的时钟可以对T-TSC的PTP报文同步性能进行预估。从而可以在GNSS发生失效的之前就可以对T-TSC的PTP报文同步性能进行预先判断，指导网络运维活动。利用本申请实施例的技术方案可以采集数天的时延信息，并在短时间(例如数分钟)内利用采集到的时延信息评估T-TSC的时钟时间恢复性能。整个过程可以自动化输出评估结果，无需导出采集到的数据，减少运维人员的参与，评估成本较低。
本申请实施例对时钟源的类型并不限定，例如时钟源的类型可以是晶振、铷钟以及其他类型的振荡器等。
进一步，T-TSC的报文同步性能评估是利用虚拟时钟实现的，产生的时钟信号是用于评估T-TSC的报文同步性能，因此不会对T-TSC正常工作造成影响。
图4至图7所示的方法可以由作为从设备的网络设备(例如T-TSC，或者作为从设备的T-BC)或者网络设备中的部件实现以外，还可以通过其他计算机装置来实现。例如，可以通过其他计算机设备(例如作为管理设备的计算机设备(可以是个人电脑或者服务器等)等)或计算机设备中的部件实现。从设备的网络设备采集时延信息以及从设备的实际时钟的频率信息，将采集到的信息发送给计算机设备，计算机设备根据获取的信息确定虚拟时钟T-TSC以及虚拟时钟T-GM，并利用确定的虚拟时钟T-TSC来评估该从设备的时钟时间恢复性能。
图8是根据本申请所述提供的一种确定时钟的方法的示意性流程图。图8所示的方法可以由作为从设备的网络设备或者网络设备中的部件(例如芯片、电路等)执行，也可以由计算机设备(例如作为管理设备的计算机设备)或者计算机设备中的部件(例如芯片、电路等)执行。
801，在第二网络设备和第一网络设备均同步于基准时钟的情况下，获取该第二网络设备和该第一网络设备之间的时延信息以及该第二网络设备的时钟的频率信息。
802，根据该频率信息，确定第二虚拟时钟；根据该时延信息，对该第二虚拟时钟进行调整，其中调整后的该第二虚拟时钟与第一虚拟时钟同步，该第一虚拟时钟用于模拟该第一网络设备的时钟。
该第二网络设备可以是执行图8所示方法的网络设备。
可选的，该时延信息包括N个时延，该N个时延为N个该第二网络设备到该第一网络设备的时延，或者，N个该第一网络设备到该第二网络设备的时延，N为大于或等于2的正整数；该方法还包括：获取该第一虚拟时钟产生的N个第一时间戳；该根据该时延信息，对该第二虚拟时钟进行调整，包括：根据该N个时延和该N个第一时间戳，获取该第二虚拟时钟产生的N个第二时间戳，该N个第二时间戳和该N个时延一一对应；根据该N个第二时间戳和该N个第一时间戳，对该第二虚拟时钟的频率进行调整。
可选的，该时延信息包括正向时延和反向时延，其中该正向时延为该第一网络设备到该第二网络设备的时延，该反向时延为该第二网络设备到该第一网络设备的时延，该方法还包括：获取第一虚拟时钟产生的第三时间戳和第六时间戳；获取第二虚拟时钟产生的第四时间戳和第五时间戳；该根据该时延信息，对该第二虚拟时钟进行调整，包括：根据该正向时延、该第三时间戳和该第四时间戳，确定第一时延；根据该反向时延、该第五时间戳和该第六时间戳，确定第二时延；根据该第一时延和该第二时延，对该第二虚拟时钟的相位进行调整。
可选的，该时延信息包括第七时间戳、第八时间戳、第九时间戳和第十时间戳；该根据该时延信息，对该第二虚拟时钟进行调整，包括：根据该频率信息，对该第八时间戳和该第九时间戳进行调整；根据该第七时间戳、调整后的该第八时间戳、调整后的该第九时间戳和该第十时间戳，对该第二虚拟时钟的相位进行调整。
可选的，该方法还包括：根据该第一虚拟时钟和调整后的该第二虚拟时钟确定时钟性能评估信息，该时钟性能评估信息用于指示该第二虚拟时钟的时钟时间恢复性能。
可选的，该根据该第一虚拟时钟和调整后的该第二虚拟时钟确定时钟性能评估信息，包括：确定该第一虚拟时钟的频率F v1和调整后的该第二虚拟时钟的频率F v2；根据F v1和F v2，确定时间间隔误差TIE。
可选的，该根据该第一虚拟时钟和调整后的该第二虚拟时钟确定时钟性能评估信息，包括：确定该第一虚拟时钟的产生时间戳T v1和T v4，确定调整后的该第二虚拟时钟产生的时间戳T v2和T v3；根据T v1、T v2、T v3和T v4，确定时间误差TE。
图9是根据本申请实施例提供的一种电子设备的示意性结构框图。如图9所示的电子设备900包括获取单元901和处理单元902。电子设备900可以执行上述方法实施例的各个步骤。电子设备900可以是网络设备，也可以是计算机设备。
获取单元901，用于在第二网络设备和第一网络设备均同步于基准时钟的情况下，获取该第二网络设备和该第一网络设备之间的时延信息以及该第二网络设备的时钟的频率信息。
处理单元902，可用于根据该频率信息，确定第二虚拟时钟。
处理单元902，还用于根据该时延信息，对该第二虚拟时钟进行调整，其中调整后的该第二虚拟时钟与第一虚拟时钟同步，该第一虚拟时钟用于模拟该第一网络设备的时钟。
在一些实施例中，该时延信息包括N个时延，该N个时延为N个该第二网络设备到该第一网络设备的时延，或者，N个该第一网络设备到该第二网络设备的时延，N为大于或等于2的正整数；获取单元901，还用于获取该第一虚拟时钟产生的N个第一时间戳；处理单元902，具体用于根据该N个时延和该N个第一时间戳，获取该第二虚拟时钟产生的N个第二时间戳，该N个第二时间戳和该N个时延一一对应；根据该N个第二时间戳和该N个第一时间戳，对该第二虚拟时钟的频率进行调整。
在一些实施例中，该时延信息包括正向时延和反向时延，其中该正向时延为该第一网络设备到该第二网络设备的时延，该反向时延为该第二网络设备到该第一网络设备的时延，获取单元901，还用于获取第一虚拟时钟产生的第三时间戳和第六时间戳；获取第二虚拟时钟产生的第四时间戳和第五时间戳；处理单元902，具体用于根据该正向时延、该第三时间戳和该第四时间戳，确定第一时延；根据该反向时延、该第五时间戳和该第六时 间戳，确定第二时延；根据该第一时延和该第二时延，对该第二虚拟时钟的相位进行调整。
在一些实施例中，该时延信息包括第七时间戳、第八时间戳、第九时间戳和第十时间戳；处理单元902，具体用于根据该频率信息，对该第八时间戳和该第九时间戳进行调整；根据该第七时间戳、调整后的该第八时间戳、调整后的该第九时间戳和该第十时间戳，对该第二虚拟时钟的相位进行调整。
在一些实施例中，处理单元902，还用于根据该第一虚拟时钟和调整后的该第二虚拟时钟确定时钟性能评估信息，该时钟性能评估信息用于指示该第二虚拟时钟的时钟时间恢复性能。
在一些实施例中，处理单元902，具体用于确定该第一虚拟时钟的频率F v1和调整后的该第二虚拟时钟的频率F v2；根据F v1和F v2，确定时间间隔误差TIE。
在一些实施例中，处理单元902，具体用于确定该第一虚拟时钟的产生时间戳T v1和T v4，确定调整后的该第二虚拟时钟产生的时间戳T v2和T v3；根据T v1、T v2、T v3和T v4，确定时间误差TE。
若电子设备900是该第二网络设备，则获取单元901可以是网络设备内的通信接口，处理单元902可以是该网络设备的处理器。
若电子设备900是计算机设备，则获取单元901可以是接收器，该接收器可以用于接收来自于第二网络设备的相关信息(例如时延信息和频率信息等)。处理单元902可以是计算机设备的处理器。
应理解，上述电子设备900也可以是一个芯片。例如，该电子设备可以是现场可编程门阵列(field programmable gate array，FPGA)，可以是专用集成芯片(application specific integrated circuit，ASIC)，还可以是***芯片(system on chip，SoC)，还可以是中央处理器(central processor unit，CPU)，还可以是网络处理器(network processor，NP)，还可以是数字信号处理电路(digital signal processor，DSP)，还可以是微控制器(micro controller unit，MCU)，还可以是可编程控制器(programmable logic device，PLD)、其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件，或其他集成芯片。
若电子装置900为芯片，那么获取单元901可以是输入输出电路或通信接口，处理单元902可以是芯片上集成的处理器或者集成电路。
本申请实施例还提供一种电子设备，该电子设备包处理器，该处理器用于与存储器耦合，读取并执行该存储器中的指令和/或程序代码，以执行上述实施例中任一个实施例所述的方法。
本申请实施例还提供了一种芯片***，该芯片***包括逻辑电路，该逻辑电路用于与输入/输出接口耦合，通过该输入/输出接口传输数据，以执行上述实施例中任一个实施例所述的方法。
在实现过程中，上述方法的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令或程序代码完成。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。为避免重复，这里不再详细描述。
应注意，本申请实施例中的处理器可以是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法实施例的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令或程序代码完成。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。
可以理解，本申请实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。应注意，本文描述的***和方法的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
根据本申请实施例提供的方法，本申请还提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码在计算机上运行时，使得该计算机执行上述实施例中任意一个实施例的方法。
根据本申请实施例提供的方法，本申请还提供一种计算机可读介质，该计算机可读介质存储有程序代码，当该程序代码在计算机上运行时，使得该计算机执行上述实施例中任意一个实施例的方法。
根据本申请实施例提供的方法，本申请还提供一种***，其包括前述的第二网络设备和第一网络设备。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的***、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的***、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个***，或一些特征可以忽略，或不执行。另一点，所 显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令或程序代码用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种确定时钟的方法，其特征在于，包括：
    在第二网络设备和第一网络设备均同步于基准时钟的情况下，获取所述第二网络设备和所述第一网络设备之间的时延信息以及所述第二网络设备的时钟的频率信息；
    根据所述频率信息，确定第二虚拟时钟；
    根据所述时延信息，对所述第二虚拟时钟进行调整，其中调整后的所述第二虚拟时钟与第一虚拟时钟同步，所述第一虚拟时钟用于模拟所述第一网络设备的时钟。
  2. 如权利要求1所述的方法，其特征在于，所述时延信息包括N个时延，所述N个时延为N个所述第二网络设备到所述第一网络设备的时延，或者，N个所述第一网络设备到所述第二网络设备的时延，N为大于或等于2的正整数；
    所述方法还包括：获取所述第一虚拟时钟产生的N个第一时间戳；
    所述根据所述时延信息，对所述第二虚拟时钟进行调整，包括：
    根据所述N个时延和所述N个第一时间戳，获取所述第二虚拟时钟产生的N个第二时间戳，所述N个第二时间戳和所述N个时延一一对应；
    根据所述N个第二时间戳和所述N个第一时间戳，对所述第二虚拟时钟的频率进行调整。
  3. 如权利要求1或2所述的方法，其特征在于，所述时延信息包括正向时延和反向时延，其中所述正向时延为所述第一网络设备到所述第二网络设备的时延，所述反向时延为所述第二网络设备到所述第一网络设备的时延，
    所述方法还包括：
    获取第一虚拟时钟产生的第三时间戳和第六时间戳；
    获取第二虚拟时钟产生的第四时间戳和第五时间戳；
    所述根据所述时延信息，对所述第二虚拟时钟进行调整，包括：
    根据所述正向时延、所述第三时间戳和所述第四时间戳，确定第一时延；
    根据所述反向时延、所述第五时间戳和所述第六时间戳，确定第二时延；
    根据所述第一时延和所述第二时延，对所述第二虚拟时钟的相位进行调整。
  4. 如权利要求1所述的方法，其特征在于，所述时延信息包括第七时间戳、第八时间戳、第九时间戳和第十时间戳；
    所述根据所述时延信息，对所述第二虚拟时钟进行调整，包括：
    根据所述频率信息，对所述第八时间戳和所述第九时间戳进行调整；
    根据所述第七时间戳、调整后的所述第八时间戳、调整后的所述第九时间戳和所述第十时间戳，对所述第二虚拟时钟的相位进行调整。
  5. 如权利要求1至4中任一项所述的方法，其特征在于，所述方法还包括：根据所述第一虚拟时钟和调整后的所述第二虚拟时钟确定时钟性能评估信息，所述时钟性能评估信息用于指示所述第二虚拟时钟的时钟时间恢复性能。
  6. 如权利要求5所述的方法，其特征在于，所述根据所述第一虚拟时钟和调整后的所述第二虚拟时钟确定时钟性能评估信息，包括：
    确定所述第一虚拟时钟的频率F v1和调整后的所述第二虚拟时钟的频率F v2；
    根据F v1和F v2，确定时间间隔误差TIE。
  7. 如权利要求5或6所述的方法，其特征在于，所述根据所述第一虚拟时钟和调整后的所述第二虚拟时钟确定时钟性能评估信息，包括：
    确定所述第一虚拟时钟的产生时间戳T v1和T v4，
    确定调整后的所述第二虚拟时钟产生的时间戳T v2和T v3；
    根据T v1、T v2、T v3和T v4，确定时间误差TE。
  8. 一种电子设备，其特征在于，包括：
    获取单元，用于在第二网络设备和第一网络设备均同步于基准时钟的情况下，获取所述第二网络设备和所述第一网络设备之间的时延信息以及所述第二网络设备的时钟的频率信息；
    处理单元，可用于根据所述频率信息，确定第二虚拟时钟；
    所述处理单元，还用于根据所述时延信息，对所述第二虚拟时钟进行调整，其中调整后的所述第二虚拟时钟与第一虚拟时钟同步，所述第一虚拟时钟用于模拟所述第一网络设备的时钟。
  9. 如权利要求8所述的电子设备，其特征在于，所述时延信息包括N个时延，所述N个时延为N个所述第二网络设备到所述第一网络设备的时延，或者，N个所述第一网络设备到所述第二网络设备的时延，N为大于或等于2的正整数；
    所述获取单元，还用于获取所述第一虚拟时钟产生的N个第一时间戳；
    所述处理单元，具体用于根据所述N个时延和所述N个第一时间戳，获取所述第二虚拟时钟产生的N个第二时间戳，所述N个第二时间戳和所述N个时延一一对应；
    根据所述N个第二时间戳和所述N个第一时间戳，对所述第二虚拟时钟的频率进行调整。
  10. 如权利要求8或9所述的电子设备，其特征在于，所述时延信息包括正向时延和反向时延，其中所述正向时延为所述第一网络设备到所述第二网络设备的时延，所述反向时延为所述第二网络设备到所述第一网络设备的时延，
    所述获取单元，还用于获取第一虚拟时钟产生的第三时间戳和第六时间戳；获取第二虚拟时钟产生的第四时间戳和第五时间戳；
    所述处理单元，具体用于根据所述正向时延、所述第三时间戳和所述第四时间戳，确定第一时延；
    根据所述反向时延、所述第五时间戳和所述第六时间戳，确定第二时延；
    根据所述第一时延和所述第二时延，对所述第二虚拟时钟的相位进行调整。
  11. 如权利要求8所述的电子设备，其特征在于，所述时延信息包括第七时间戳、第八时间戳、第九时间戳和第十时间戳；
    所述处理单元，具体用于根据所述频率信息，对所述第八时间戳和所述第九时间戳进行调整；
    根据所述第七时间戳、调整后的所述第八时间戳、调整后的所述第九时间戳和所述第十时间戳，对所述第二虚拟时钟的相位进行调整。
  12. 如权利要求8至11中任一项所述的电子设备，其特征在于，所述处理单元，还 用于根据所述第一虚拟时钟和调整后的所述第二虚拟时钟确定时钟性能评估信息，所述时钟性能评估信息用于指示所述第二虚拟时钟的时钟时间恢复性能。
  13. 如权利要求12所述的电子设备，其特征在于，所述处理单元，具体用于确定所述第一虚拟时钟的频率F v1和调整后的所述第二虚拟时钟的频率F v2；
    根据F v1和F v2，确定时间间隔误差TIE。
  14. 如权利要求12或13所述的电子设备，其特征在于，所述处理单元，具体用于确定所述第一虚拟时钟的产生时间戳T v1和T v4，
    确定调整后的所述第二虚拟时钟产生的时间戳T v2和T v3；
    根据T v1、T v2、T v3和T v4，确定时间误差TE。
  15. 一种电子设备，其特征在于，包括：处理器，所述处理器用于与存储器耦合，读取并执行所述存储器中的指令和/或程序代码，以执行如权利要求1-7中任一项所述的方法。
  16. 一种芯片***，其特征在于，包括：逻辑电路，所述逻辑电路用于与输入/输出接口耦合，通过所述输入/输出接口传输数据，以执行如权利要求1-7中任一项所述的方法。
  17. 一种计算机可读存储介质，其特征在于，所述计算机可读介质存储有程序代码，当所述计算机程序代码在计算机上运行时，使得计算机执行如权利要求1-7中任一项所述的方法。
PCT/CN2021/086705 2020-04-13 2021-04-12 确定时钟的方法和相关装置 WO2021208868A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP21789450.0A EP4123955A4 (en) 2020-04-13 2021-04-12 METHOD FOR DETERMINING A CLOCK AND ASSOCIATED DEVICE
US17/964,619 US20230050042A1 (en) 2020-04-13 2022-10-12 Clock determining method and related apparatus

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN202010286753.9 2020-04-13
CN202010286753 2020-04-13
CN202010586995.XA CN113541838A (zh) 2020-04-13 2020-06-24 确定时钟的方法和相关装置
CN202010586995.X 2020-06-24

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/964,619 Continuation US20230050042A1 (en) 2020-04-13 2022-10-12 Clock determining method and related apparatus

Publications (1)

Publication Number Publication Date
WO2021208868A1 true WO2021208868A1 (zh) 2021-10-21

Family

ID=78084063

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/086705 WO2021208868A1 (zh) 2020-04-13 2021-04-12 确定时钟的方法和相关装置

Country Status (3)

Country Link
US (1) US20230050042A1 (zh)
EP (1) EP4123955A4 (zh)
WO (1) WO2021208868A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116009404B (zh) * 2023-02-22 2023-05-23 广东科伺智能科技有限公司 伺服设备的调试方法、装置、设备和可读存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103873179A (zh) * 2012-12-17 2014-06-18 财团法人工业技术研究院 使无源光网络具备支持时间同步能力的装置与方法
CN108023723A (zh) * 2016-11-04 2018-05-11 华为技术有限公司 频率同步的方法以及从时钟
US20180198599A1 (en) * 2011-07-20 2018-07-12 Aviat U.S., Inc. Systems and methods of clock synchronization between devices on a network
CN108401454A (zh) * 2017-06-30 2018-08-14 深圳市大疆创新科技有限公司 事务调度方法、处理器、分布式***和无人机

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104270218B (zh) * 2014-10-17 2019-05-21 中磊电子（苏州）有限公司 频率校正方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180198599A1 (en) * 2011-07-20 2018-07-12 Aviat U.S., Inc. Systems and methods of clock synchronization between devices on a network
CN103873179A (zh) * 2012-12-17 2014-06-18 财团法人工业技术研究院 使无源光网络具备支持时间同步能力的装置与方法
CN108023723A (zh) * 2016-11-04 2018-05-11 华为技术有限公司 频率同步的方法以及从时钟
CN108401454A (zh) * 2017-06-30 2018-08-14 深圳市大疆创新科技有限公司 事务调度方法、处理器、分布式***和无人机

Also Published As

Publication number Publication date
EP4123955A1 (en) 2023-01-25
EP4123955A4 (en) 2023-09-06
US20230050042A1 (en) 2023-02-16

Similar Documents

Publication Publication Date Title
US9525502B2 (en) Timing over packet demarcation entity
US8446896B2 (en) Time synchronization using packet-layer and physical-layer protocols
KR101749202B1 (ko) 타임스탬프를 생성하는 방법, 장치, 그리고 시스템
US9178637B2 (en) Method and devices for synchronization using linear programming
US8964790B2 (en) Communication apparatus
US11287843B2 (en) Synchronisation of hardware clock using software clock synchronisation error
US20130039359A1 (en) Time Synchronization Using Packet-Layer and Physical-Layer Protocols
US11038608B2 (en) Frequency synchronization method and slave clock
CN110100408B (zh) 交互时间同步报文的方法以及网络装置
CN110324889A (zh) 时钟同步方法、通信装置及通信设备
WO2014048167A1 (zh) 分组传送网络中的***时间同步装置及方法
CN113541838A (zh) 确定时钟的方法和相关装置
CN102983927B (zh) 一种基于ieee 1588协议的主从时钟对时的时间补偿方法
CN105577349A (zh) 一种机载网络ieee1588协议主从时钟端口同步方法
CN106357362A (zh) 一种时间同步方法、装置及ptp***
CN109039514A (zh) 一种提高ieee1588时间戳精度的方法
CN112217588A (zh) 时间戳抖动补偿方法及***
WO2021208868A1 (zh) 确定时钟的方法和相关装置
US20220006547A1 (en) Systems and methods for testing time distribution
CN115801175A (zh) 时间频率同步方法、***、存储介质及电子设备
Thi et al. IEEE 802.1 TSN time synchronization over Wi-Fi and 5G mobile networks
CN111628914B (zh) 一种周期通信网络的链路延时测量方法、***及fpga
EP3080933B1 (en) Method and devices for synchronization using linear programming
CN116599616A (zh) 基站时钟切换方法、装置、基站及介质
WO2016115922A1 (zh) 空口同步***及其方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21789450

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021789450

Country of ref document: EP

Effective date: 20221018

NENP Non-entry into the national phase

Ref country code: DE