WO2021208006A1 - 封装结构、电动车辆和电子装置 - Google Patents

封装结构、电动车辆和电子装置 Download PDF

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Publication number
WO2021208006A1
WO2021208006A1 PCT/CN2020/085092 CN2020085092W WO2021208006A1 WO 2021208006 A1 WO2021208006 A1 WO 2021208006A1 CN 2020085092 W CN2020085092 W CN 2020085092W WO 2021208006 A1 WO2021208006 A1 WO 2021208006A1
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Prior art keywords
bonding layer
bonding
substrate
package structure
support
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PCT/CN2020/085092
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English (en)
French (fr)
Inventor
郎丰群
林凯文
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2020/085092 priority Critical patent/WO2021208006A1/zh
Priority to CN202080005260.1A priority patent/CN112771665B/zh
Priority to EP20926350.8A priority patent/EP3933914A4/en
Publication of WO2021208006A1 publication Critical patent/WO2021208006A1/zh

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Definitions

  • This application relates to the field of semiconductor technology, in particular to a packaging structure, an electric vehicle and an electronic device.
  • the soldering layer needs to have a flat surface and should not be easily affected by other interference factors to cause the shape to bend, so that the parallelism of the soldering layer can meet the process requirements.
  • the thickness of the soldering layer needs to meet the manufacturing requirements. The thickness should not be too thin to avoid affecting the reliability of the electronic device and shorten the service life of the electronic device, and the thickness should not be too thick to avoid the increase in the thermal resistance of the electronic device. The heat dissipation effect of the electronic device is not good.
  • solders In addition, multiple reflows are required in the manufacturing process of electronic devices. Therefore, the types of solders that can be selected are limited, and the solder is prone to the risk of re-melting, resulting in deterioration of the quality of the soldering layer, electrical short-circuiting of electronic devices, and electronic device failure. .
  • the present application provides a packaging structure, an electric vehicle, and an electronic device, so as to improve the reliability of the packaging structure, an electric vehicle, and an electronic device, and reduce the manufacturing cost of the packaging structure, an electric vehicle, and an electronic device.
  • the present application provides a package structure including: a first substrate, a first bonding layer, an electronic component, a second bonding layer, and a second substrate.
  • the first bonding layer is located between the first conductive surface of the first substrate and the first bonding surface of the electronic component, and the first bonding layer is used to realize the bonding of the electronic component and the first substrate.
  • the first bonding layer includes: a first bonding material and at least one first supporting member, the height of the at least one first supporting member is the same as the thickness of the first bonding layer, and the melting point of the at least one first supporting member is higher than that of forming the first bonding The maximum temperature of the layer to make the surface of the first bonding layer flat and uniform in thickness.
  • the second bonding layer is located between the second bonding surface of the electronic component and the first conductive surface of the second substrate.
  • the second bonding layer is used to realize the bonding of the electronic component and the second substrate, and the first bonding surface of the electronic component is connected to the electronic component.
  • the second joint surface is opposite.
  • the at least one first supporting member will not be completely dissolved in the first bonding material, so that the thickness of the at least one first supporting member is still the same as that of the first bonding layer.
  • the thickness of the layers is kept the same so that the first bonding layer having the height of the at least one first support is formed by the at least one first support.
  • the at least one first supporting member will not move with the movement of the first bonding material, so that the at least one first supporting member is evenly distributed in the first bonding layer, and Based on the supporting effect of the at least one first supporting member, the first bonding layer can withstand compression without being deformed, so that even if the at least one first supporting member is remelted, the first bonding material will not overflow, ensuring The good quality and bonding strength of the first bonding layer are avoided, and the lack of the first bonding material under the electronic components leads to electrical short circuit or failure of the electronic components, thereby ensuring that the surface of the first bonding layer is flat and the thickness is uniform.
  • the process requirements for the thickness and warpage of the first bonding layer are improved.
  • the first bonding material is no longer subject to the type limitation, which provides multiple possibilities for the production of the first bonding layer, which is beneficial to reducing the cost of the first bonding layer.
  • the reliability of the packaging structure is improved, the manufacturing cost of the packaging structure is reduced, and the competitiveness of the packaging structure is improved.
  • the second bonding layer includes: a second bonding material and at least one second supporting member, the height of the at least one second supporting member is the same as the thickness of the second bonding layer, and the at least one second supporting member
  • the melting point of is higher than the highest temperature for forming the second bonding layer, so that the surface of the second bonding layer is flat and the thickness is uniform.
  • the at least one second supporting member will not completely dissolve in the second bonding material in the second bonding layer, so that the thickness of the at least one second supporting member is still the same as the thickness of the second bonding layer. Keep the same so that the second bonding layer having the height of the at least one second support is formed by the at least one second support.
  • the at least one second supporting member will not move with the movement of the second bonding material, so that the at least one second supporting member is evenly distributed in the second bonding layer, and Based on the supporting effect of the at least one second supporting member, the second bonding layer can withstand the compression without being deformed, so that even if the at least one first supporting member is remelted, it will not cause the second bonding layer in the second bonding layer.
  • the overflow of the bonding material ensures the good quality and bonding strength of the second bonding layer, and avoids the lack of the second bonding material under the second substrate causing electrical short circuit or failure of the electronic components, thereby ensuring the second bonding layer.
  • the surface is flat and the thickness is uniform, which meets the process requirements for the thickness and warpage of the second bonding layer.
  • the second bonding material in the second bonding layer is no longer restricted by types, which provides multiple possibilities for the production of the second bonding layer, which is beneficial to reducing the cost of the second bonding layer.
  • the first conductive surface of the second substrate and the second bonding surface of the electronic component achieve a good bonding effect and electrical connection through the second bonding layer, and the bonding is also reduced. cost.
  • the first conductive surface of the first substrate, the first bonding layer, the electronic components, the second bonding layer and the first conductive surface of the second substrate are integrated.
  • Firm bonding and reliable connection improve the reliability of the package structure, reduce the bonding cost of the package structure, and enhance the competitiveness of the package structure.
  • the second support member in order to prevent the second support member from being melted by the second joining material during joining, the solder moves outside the second joining layer. Therefore, the second support member may be fixedly arranged.
  • at least one second support member is fixedly arranged on the second bonding surface of the electronic component or the first conductive surface of the second substrate. Therefore, the operation is convenient and quick, the production efficiency is high, and the position of the second support member in the second bonding layer is free, so that the second support member of the required size can be implanted at the required position.
  • the second support has a micron-level size. Since the size of the second support body in each dimension is on the order of micrometers, compared with the volume of the second bonding layer with dimensions of several millimeters, the size of the second support member is very small, so that the second support member is It has little influence on the process of the second bonding layer, and it will not prevent the bubbles formed on the second bonding layer from escaping from the second bonding material, avoiding the excessively high void rate of the second bonding layer, which will not cause damage. The reliability of the second bonding layer has an adverse effect.
  • the packaging structure further includes: a plastic encapsulation material; the first substrate, the first bonding layer, parts of the electronic component, the second bonding layer, and the second substrate are all arranged in the plastic encapsulation material.
  • the first support member in order to prevent the first support member from being melted by the first joining material during joining, the solder moves outside the first joining layer. Therefore, the first support member may be fixedly arranged.
  • at least one first support member is fixedly arranged on the first bonding surface of the electronic component or the first conductive surface of the first substrate. Therefore, the operation is convenient and quick, the production efficiency is high, and the position of the first support member in the first bonding layer is free, so that the first support member of the required size can be implanted at the required position.
  • the first support has a size of micrometers. Since the size of the first support in each dimension is in the order of micrometers, the size of the first support is small compared with the volume of the first bonding layer with a size of several millimeters, so that the first support is It has little effect on the process of the first bonding layer, and it will not prevent the bubbles formed on the first bonding layer from escaping from the first bonding material, avoiding the excessively high void rate of the first bonding layer, which will not cause damage. The reliability and thermal conductivity of the first bonding layer have an adverse effect.
  • the electronic component includes: a chip, a third bonding layer, interconnection posts, signal terminals, and power terminals .
  • the chip is located between the first bonding layer and the third bonding layer except the first bonding layer corresponding to the signal terminal and the first bonding layer corresponding to the power terminal, and the interconnection pillars are located between the third bonding layer and the corresponding third bonding layer corresponding to the chip. Between the second bonding layer.
  • the signal terminal extends from the inside of the package structure to the outside of the package structure, and one end of the signal terminal located inside the package structure is located at the first bonding layer except the first bonding layer corresponding to the chip and the first bonding layer corresponding to the power terminal
  • the first bonding layer includes a first bonding material and a first support fixedly arranged on the first conductive surface of the first substrate, the signal terminals are electrically connected to the chip, and the first bonding layer and signal terminals corresponding to the chip
  • the corresponding first bonding layers respectively correspond to different conductive regions in the first conductive surface of the first substrate.
  • the power terminal extends from the inside of the package structure to the outside of the package structure, and one end of the power terminal located inside the package structure is located at the first bonding layer except the first bonding layer corresponding to the chip and the first bonding layer corresponding to the signal terminal Layer, the first bonding layer includes a first bonding material and a first support fixedly arranged on the first conductive surface of the first substrate, the first bonding layer corresponding to the chip and the first bonding layer corresponding to the power terminal are respectively Corresponding to the same conductive area in the first conductive surface of the first substrate; and/or, the power terminal is located on a second bonding layer other than the second bonding layer corresponding to the interconnection column, and the second bonding layer includes a second bonding layer.
  • the third bonding layer includes: a third bonding material and at least one third supporting member, the height of at least one third supporting member is the same as the thickness of the third bonding layer, and the melting point of the at least one third supporting member is higher than that of forming the third bonding The highest temperature of the layer to make the surface of the third bonding layer flat and uniform in thickness.
  • the at least one third supporting member will not completely dissolve in the third bonding material in the third bonding layer, so that the thickness of the at least one third supporting member is still the same as the thickness of the third bonding layer. Keep the same so that the third bonding layer having the height of the at least one third support is formed by the at least one third support.
  • the at least one third support will not move with the movement of the third bonding material, so that the at least one third support is evenly distributed in the third bonding layer, and is based on
  • the supporting effect of the at least one third supporting member enables the third bonding layer to withstand compression without being deformed, so that even if the at least one third supporting member is remelted, it will not cause the third bonding in the third bonding layer
  • the material overflow ensures the good quality and bonding strength of the third bonding layer, and avoids the lack of the third bonding material under the interconnection pillars causing electrical short circuit or failure of the chip, thereby ensuring that the surface of the third bonding layer is flat and The thickness is uniform, which meets the process requirements for the thickness and warpage of the third bonding layer.
  • the third bonding material in the third bonding layer is no longer restricted by types, which provides multiple possibilities for the production of the third bonding layer, which is beneficial to reducing the cost of the third bonding layer.
  • the chip and the interconnection column achieve a good bonding effect and electrical connection through the third bonding layer, and the bonding cost is also reduced.
  • the first conductive surface, the first bonding layer, the chip, the third bonding layer, the interconnection pillars, and the second bonding layer of the first substrate are realized.
  • the bonding layer and the first conductive surface of the second substrate are firmly bonded and reliably connected, and the signal terminal and the first conductive surface of the first substrate are firmly bonded and reliably connected, and the power terminal is connected to the first conductive surface of the first substrate.
  • the firm bonding and reliable connection of the conductive surface and/or the first conductive surface of the second substrate not only improves the reliability of the package structure, reduces the bonding cost of the package structure, but also enables the package structure to realize a complete power conversion process.
  • the third support member in order to prevent the third support member from being melted by the third bonding material and the solder moves out of the third bonding layer during bonding, the third support member may be fixedly arranged.
  • at least one third support member is fixedly arranged on a side of the chip close to the interconnection column or a surface of the interconnection column close to the chip. Therefore, the operation is convenient and quick, the production efficiency is high, and the position of the third support member in the third bonding layer is free, so that the third support member of the required size can be implanted at the required position.
  • the third support has a micron size. Since the dimensions of the third support in each dimension are all in the order of micrometers, compared with the volume of the third bonding layer with dimensions of several millimeters, the size of the third support is small, so that the third support is It has little effect on the process of the third bonding layer, and it will not prevent the bubbles formed on the third bonding layer from escaping from the third bonding material, avoiding the excessively high void rate of the third bonding layer, which will not cause damage. The reliability of the third bonding layer has an adverse effect.
  • the electronic component includes a chip, a signal terminal, and a power terminal.
  • the chip is located between the first bonding layer and the corresponding second bonding layer except for the first bonding layer corresponding to the signal terminal and the first bonding layer corresponding to the power terminal.
  • the signal terminal extends from the inside of the package structure to the outside of the package structure, and one end of the signal terminal located inside the package structure is located at the first bonding layer except the first bonding layer corresponding to the chip and the first bonding layer corresponding to the power terminal
  • the first bonding layer includes a first bonding material and a first support fixedly arranged on the first conductive surface of the first substrate, the signal terminals are electrically connected to the chip, and the first bonding layer and signal terminals corresponding to the chip
  • the corresponding first bonding layers respectively correspond to different conductive regions in the first conductive surface of the first substrate.
  • the power terminal extends from the inside of the package structure to the outside of the package structure, and one end of the power terminal located inside the package structure is located at the first bonding layer except the first bonding layer corresponding to the chip and the first bonding layer corresponding to the signal terminal Layer, the first bonding layer includes a first bonding material and a first support fixedly arranged on the first conductive surface of the first substrate, the first bonding layer corresponding to the chip and the first bonding layer corresponding to the power terminal are respectively Corresponding to the same conductive area in the first conductive surface of the first substrate; and/or, the power terminal is located on a second bonding layer other than the second bonding layer corresponding to the chip, and the second bonding layer includes the second bonding layer.
  • the material and the second support fixedly arranged on the first conductive surface of the second substrate, the second bonding layer corresponding to the chip and the second bonding layer corresponding to the power terminal respectively correspond to the same in the first conductive surface of the second substrate Conductive area.
  • the first conductive surface, the first bonding layer, the chip, the second bonding layer and the second substrate of the first substrate are realized.
  • One conductive surface is firmly bonded and reliably connected, and the signal terminal is also firmly bonded and reliably connected to the first conductive surface of the first substrate, and the power terminal is connected to the first conductive surface of the first substrate and/or to the second conductive surface.
  • the firm bonding and reliable connection of the first conductive surface of the substrate not only improves the reliability of the package structure and reduces the bonding cost of the package structure, but also enables the package structure to realize a complete power conversion process.
  • the electronic component also includes a sensor.
  • the two ends of the sensor are respectively located on the first bonding layer except the first bonding layer corresponding to the chip, the first bonding layer corresponding to the signal terminal, and the first bonding layer corresponding to the power terminal.
  • the first bonding layer includes the first bonding layer.
  • the first bonding layer corresponding to the chip and the first bonding layer corresponding to the sensor respectively correspond to different conductivity in the first conductive surface of the first substrate. area.
  • the package structure further includes: a first heat sink and a fourth bonding layer.
  • the fourth bonding layer is located between the second conductive surface of the first substrate and the first heat sink. The second conductive surface of the first substrate is exposed to the outside of the package structure.
  • the fourth bonding layer is used to realize the first substrate and the first heat dissipation. Bonding between pieces.
  • the fourth bonding layer includes: a fourth bonding material and at least one fourth supporting member, the height of the at least one fourth supporting member is the same as the thickness of the fourth bonding layer, and the melting point of the at least one fourth supporting member is higher than that of forming the fourth bonding The highest temperature of the layer to make the surface of the fourth bonding layer flat and uniform in thickness.
  • the at least one fourth supporting member will not completely dissolve in the fourth bonding material in the fourth bonding layer, so that the thickness of the at least one fourth supporting member is still the same as the thickness of the fourth bonding layer. Keep the same so that the fourth bonding layer having the height of the at least one fourth support is formed by the at least one fourth support.
  • the at least one fourth support member will not move with the movement of the fourth bonding material, so that the at least one fourth support member is evenly distributed in the fourth bonding layer, and Based on the supporting effect of the at least one fourth supporting member, the fourth bonding layer can withstand the extrusion without being deformed, so that even if the at least one fourth supporting member is remelted, it will not cause the fourth bonding layer in the fourth bonding layer.
  • the overflow of the bonding material ensures the good quality and bonding strength of the fourth bonding layer, thereby ensuring that the surface of the fourth bonding layer is flat and uniform in thickness, and meeting the process requirements for the thickness and warpage of the fourth bonding layer.
  • the fourth bonding material in the fourth bonding layer is no longer restricted by types, which provides multiple possibilities for the production of the fourth bonding layer, which is beneficial to reducing the cost of the fourth bonding layer.
  • the first substrate and the first heat sink achieve a good bonding effect through the fourth bonding layer, which improves the reliability and cooling capacity of the package structure, and reduces the bonding.
  • the cost is conducive to the high density and high integration of the package structure.
  • the fourth support member in order to prevent the fourth support member from being melted by the fourth joining material during joining, the solder moves outside the fourth joining layer. Therefore, the fourth support member may be fixedly arranged.
  • at least one fourth support member is fixedly arranged on the second conductive surface of the first substrate or a surface of the first heat dissipation member close to the first substrate. Therefore, the operation is convenient and quick, the production efficiency is high, and the position of the fourth support member in the fourth bonding layer is free, so that the fourth support member of the required size can be implanted at the required position.
  • the fourth support has a size of micrometers. Since the dimensions of the fourth support in each dimension are all micrometers, compared with the volume of the fourth bonding layer with dimensions of several millimeters, the size of the fourth support is small, so that when the fourth support is joined It has little effect on the process of the fourth bonding layer, and it will not prevent the bubbles formed on the fourth bonding layer from escaping from the fourth bonding material, avoiding the high void ratio of the fourth bonding layer, which will not affect The reliability of the fourth bonding layer has an adverse effect.
  • the packaging structure further includes: a second heat sink and a fifth bonding layer.
  • the fifth bonding layer is located between the second conductive surface of the second substrate and the second heat sink. The second conductive surface of the second substrate is exposed to the outside of the package structure.
  • the fifth bonding layer is used to realize the second substrate and the second heat dissipation. Bonding between pieces.
  • the fifth bonding layer includes: a fifth bonding material and at least one fifth supporting member, the height of the at least one fifth supporting member is the same as the thickness of the fifth bonding layer, and the melting point of the at least one fifth supporting member is higher than that of forming the fifth bonding The highest temperature of the layer to make the surface of the fifth bonding layer flat and uniform in thickness.
  • the solder may move out of the fifth joining layer. Therefore, the fifth support member may be fixedly arranged.
  • at least one fifth support member is fixedly arranged on the second conductive surface of the second substrate or a surface of the second heat dissipation member close to the second substrate. Therefore, the operation is convenient and quick, the production efficiency is high, and the position of the fifth support member in the fifth bonding layer is free, so that the fifth support member of the required size can be implanted at the required position.
  • the fifth support has a size of micrometers. Since the dimensions of the fifth support in each dimension are all in the order of micrometers, the size of the fifth support is small compared with the volume of the fifth bonding layer with a size of several millimeters, so that the fifth support is It has little effect on the process of the fifth bonding layer, and it will not prevent the bubbles formed on the fifth bonding layer from escaping from the fifth bonding material, avoiding the excessively high void rate of the fifth bonding layer, which will not cause damage. The reliability of the fifth bonding layer has an adverse effect.
  • the support member can be set to a micron-level size, which has little effect on the bonding of the bonding layer, avoids the reduction of the bonding effect of the bonding layer due to the excessive size of the support member, and is beneficial to improve the reliability of the bonding layer .
  • the size of the support body in each dimension is micron level, the size of the support member is small compared with the volume of the bonding layer with a size of several millimeters, so that the support member has little influence on the process of the bonding layer during bonding. , It will not prevent the bubbles formed on the bonding layer from escaping from the bonding material, avoiding the excessively high void ratio of the bonding layer, and will not adversely affect the reliability of the bonding layer.
  • the shapes of the support members in different bonding layers are the same or different; and/or the shapes of multiple support members in the same bonding layer are the same or different.
  • the shape of the support includes at least one of a spherical shape, a rectangular parallelepiped shape, an ellipsoid shape, a wedge shape, or a silkworm shape.
  • the materials of the support members in different bonding layers are the same or different; and/or the materials of multiple support members in the same bonding layer are the same or different.
  • the support member is any one of a single metal material, an alloy material, a composite material, or a non-conductive material. As a result, the manufacturing cost of the package structure is reduced.
  • the support member is any one of a covering material, a coating material, a strip material, and a wire material. This provides multiple possibilities for the bonding layer.
  • the heights of the supports in different bonding layers are the same or different.
  • the number of supports in different bonding layers is the same or different.
  • the number of supports in the bonding layer can be adjusted.
  • the number of support members can be greater than or equal to 3, which is beneficial to further improve the bonding effect of the bonding layer, and can ensure the support balance of the bonded member.
  • the support member is fixedly arranged by any of the following methods: ultrasonic, sintering, electroplating or brazing.
  • the bonding material when the type of the bonding layer includes a solder layer, the bonding material includes: solder sheet or solder paste; and/or, when the type of the bonding layer is a sintered layer, the bonding material includes: Powder material or paste material.
  • the present application provides an electric vehicle, including: a power supply battery, a motor control unit MCU, and Q motors, where Q is a positive integer.
  • the motor control unit MCU includes 3R package structures in the first aspect and any one of the possible designs in the first aspect. R is a positive integer.
  • the power supply battery provides the first power to each package structure, and each motor is connected to at least three correspondingly.
  • a package structure For any one of the 3R package structures, the motor control unit MCU is used to control the package structure to convert the first electrical energy into the second electrical energy required by the motor corresponding to the package structure, and control the package structure to convert the second electrical energy Transfer to the motor connected to the package structure.
  • the present application provides an electronic device, including: at least one joined structure, and the at least one joined structure includes: a joined piece and at least one support piece with a micron size. At least one supporting member is provided on at least one surface to be joined of the joined member. Regarding the support on any of the surfaces to be joined, the height of the support is the same as the thickness of the bonding layer, the support and the bonding material form a bonding layer, and the melting point of the support is higher than the highest temperature at which the bonding layer is formed. Make the surface of the bonding layer flat and uniform in thickness.
  • the electronic device includes a 3D stereo package module.
  • the height of the supporting parts is the same as the thickness of the joining layer and The melting point of the support member is higher than the highest temperature at which the bonding layer is formed. Therefore, the support member will not be completely dissolved in the bonding material in the bonding layer, so that the thickness of the support member remains the same as the thickness of the bonding layer, so that the support member is formed with A bonding layer with the same height as the support.
  • the support will not move with the movement of the bonding material, so that the support is evenly distributed in the bonding layer, and based on the support of the support, the bonding layer can withstand It can be squeezed without being deformed, so that even if the supporting member remelts, it will not cause the bonding material in the bonding layer to overflow, ensuring the good quality and bonding strength of the bonding layer, and avoiding insufficient bonding material under the bonded part.
  • the bonding material in the bonding layer is no longer restricted by types, which provides multiple possibilities for the production of the bonding layer, which is beneficial to reduce the production cost of the bonding layer.
  • the reliability of the electronic device is improved, and the manufacturing cost of the electronic device is reduced.
  • Figure 1 is a schematic cross-sectional view of a high-density semiconductor device
  • FIG. 2 is a schematic structural diagram of a package structure provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of a structure of a support member fixedly arranged on an electronic component according to an embodiment of the application;
  • FIG. 4 is an X-ray schematic diagram of an electronic component fixedly bonded to a first substrate according to an embodiment of the application
  • FIG. 5 is a schematic flowchart of a supporting member fixedly arranged on an electronic component according to an embodiment of the application
  • FIG. 6 is a schematic flow diagram of a supporting member being fixedly arranged on an electronic component according to an embodiment of the application;
  • FIG. 7 is a schematic diagram of a manufacturing process of a package structure provided by an embodiment of the application.
  • FIG. 8 is a schematic diagram of a manufacturing process of a package structure provided by an embodiment of the application.
  • FIG. 9 is a schematic structural diagram of a package structure provided by an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of a package structure provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of a package structure provided by an embodiment of the application.
  • FIG. 12 is a schematic diagram of the position of the sensor in the packaging structure provided by an embodiment of the application.
  • FIG. 13 is a schematic diagram of the position of the sensor in the packaging structure provided by an embodiment of the application.
  • FIG. 14 is a schematic structural diagram of a package structure provided by an embodiment of the application.
  • 15 is a schematic structural diagram of a package structure provided by an embodiment of the application.
  • FIG. 16 is a schematic structural diagram of a package structure provided by an embodiment of the application.
  • FIG. 17 is a schematic structural diagram of a package structure provided by an embodiment of the application.
  • FIG. 18 is a schematic structural diagram of an electric vehicle provided by an embodiment of the application.
  • 200 High-density semiconductor device
  • 201 The first copper-clad insulating substrate
  • 202 IGBT
  • 203 FRD
  • 204 interconnect pillar a'
  • 205 interconnect pillar b'
  • 206 signal terminal a
  • 209 Second power terminal
  • 210 Plastic molding compound
  • 100 package structure; 101—first substrate; 102—first bonding layer: 102a—first support: 102b—first bonding material: 103—electronic component; 104—second bonding layer; 104a—second support 104b—second bonding material; 105—second substrate; 106—molding material; 103a—chip; 103b—third bonding layer; 103c—interconnect pillar; 103d—signal terminal; 103e—power terminal; 103ba—third support 103bb—third bonding material; 107—sensor; 108—first heat sink; 109—fourth bonding layer; 110—second heat sink; 111—fifth bonding layer; 109a—fourth support member; 109b— Fourth bonding material; 111a—fifth supporting member; 111b—fifth bonding material; 100'—DCAC conversion module;
  • 300 ultrasonic working head
  • 400 ultrasonic working head and wedge
  • 500 positioning plate
  • 601 fixing
  • 602 thickness control ring
  • 102a' first tiny metal block
  • 104a' second tiny metal block ;
  • soldering layer has requirements for thickness, parallelism and warpage to meet the technological requirements such as aluminum wire bonding and the joining of various parts in the electronic device.
  • the manufacturing process of an electronic device requires multiple reflows and requires the use of solders with different melting points.
  • the melting point of the solder used in the previous reflow process needs to be higher than the melting point of the solder used in the subsequent reflow process to avoid remelting the solder used in the previous reflow process in the subsequent reflow process.
  • the displacement of the joint body degrades the quality of the soldering layer, resulting in poor bonding effect of the soldering layer, easily causing electrical short circuit or failure of the electronic device, and seriously affecting the reliability of the electronic device.
  • the electronic device is a high-density semiconductor device 200 as an example for description.
  • the high-temperature solder is illustrated by a grid with a line to the left, and the medium-temperature solder is illustrated by a grid with a crossed line).
  • insulated bipolar transistor (IGBT) 202 on the first copper-clad insulated substrate 201
  • FRD fast recovery diode
  • the bottom surface of) 203 is welded to the first copper-clad insulating substrate 201
  • the bottom surface of the interconnection pillar a'204 is welded to the top surface of the IGBT 202
  • the bottom surface of the interconnection pillar b'205 is welded to the top surface of the FRD 203.
  • two high-temperature solders can also be used to solder the two ends of the resistor (not shown in Figure 1) to the first copper-clad insulating substrate 201, and one high-temperature solder can be used to solder one end of the signal terminal a206 in Figure 1 to the On the first copper-clad insulating substrate 201, one end of the first power terminal 207 in FIG. 1 is soldered to the first copper-clad insulating substrate 201 with a high temperature solder.
  • the above-mentioned structure is plastic-encapsulated with a plastic molding compound 210 to complete the fabrication of the high-density semiconductor device 200.
  • the operating temperature of the high-density semiconductor device 200 is limited by the lowest melting point of the solder in the above process, that is, the melting point of the medium-temperature solder or the melting point of the low-temperature solder in FIG. 1.
  • the melting point of the medium-temperature solder or the melting point of the low-temperature solder in FIG. 1 At present, for high-temperature solders, there are lead-free high-temperature solders and lead-free high-temperature solders (such as germanium gold Au-Ge, silicon gold Au-Si, tin gold Au-Sn, aluminum zinc Al-Zn, tin antimony Sn-Sb, bismuth silver (Bi-Ag) and so on.
  • solders For medium temperature solder, the available solders include tin-copper Sn-Cu and solder paste SAC305-based solder (melting point: 217°C). For low temperature solders, tin-bismuth Sn-Bi (melting point: 139°C) and tin-indium Sn-In (melting point: 118°C), etc.
  • the manufacturing process of the high-density semiconductor device 200 generally requires lead-free, which limits the use of leaded high-temperature solders to meet RoHS regulations, and the high price of gold-based high-temperature solders restricts its wide application.
  • the thermal conductivity of bismuth-silver Bi-Ag solder is too low (about 10W/km) to be overcome, the corrosiveness and wettability of aluminum-zinc Al-Zn solder need to be overcome, and the melting point of tin-antimony Sn-Sb alloy solder is slightly lower (for 243 degrees), the melting point of the rest of the solder is also lower. Therefore, the choice of the type of solder that can be used in the manufacturing process of the high-density semiconductor device 200 is limited. In addition, multiple reflows may also cause the solder to melt.
  • solder due to the type of solder that can be selected and the risk of remelting solder, it will not only cause the parallelism of the two copper-clad insulating substrates to be too large, resulting in excessive grinding after plastic packaging, but also The poor parallelism of the terminals makes it difficult to insert the high-density semiconductor device 200 and other electrical components. It also causes the quality of the solder layer of the bonded body such as the chip or terminal to deteriorate, which causes the solder to overflow, and further causes the lower part of the bonded body. Insufficient solder causes electrical short-circuiting or failure of the high-density semiconductor device 200.
  • the present application provides a package structure, an electric vehicle, and an electronic device, based on a support member fixedly arranged on the joined part, and the support function, the thickness maintaining function and the warpage maintaining function of the support member are realized.
  • a bonding layer with a flat surface and a uniform thickness is created, so that the thickness and warpage of the bonding layer meet the process requirements, and the bonding material in the bonding layer is not restricted by the type, which helps to reduce the production cost of the bonding layer, and also makes the bonding
  • the bonding material in the layer will not overflow, avoiding insufficient bonding material under the joined parts, making the electrical connection of the packaging structure, electric vehicle and electronic device convenient and firm, and improving the reliability of the packaging structure, electric vehicle and electronic device , To enhance the competitiveness of packaging structures, electric vehicles and electronic devices.
  • FIG. 2 is a schematic structural diagram of a package structure provided by an embodiment of the application.
  • the package structure 100 provided by the present application may include: a first substrate 101, a first bonding layer 102, an electronic component 103, a second bonding layer 104 and a second substrate 105.
  • a first bonding layer 102 and a second bonding layer 104 are used for illustration in FIG. 2.
  • the first bonding layer 102 is located between the first conductive surface of the first substrate 101 and the first bonding surface of the electronic component 103, and the first bonding layer 102 is used to realize the bonding of the electronic component 103 and the first substrate 101.
  • the electronic component 103 may include one component or multiple components. Multiple components may be all connected, or none of the multiple components may be connected, or some of the multiple components are all connected and the rest of the components are not connected.
  • the number of the first bonding layer 102 may be one or more, which may be specifically set according to the electrical connection of the components in the electronic component 103.
  • one component corresponds to one first bonding layer 102.
  • one component may also correspond to multiple first bonding layers 102, which is not limited in this application.
  • the first substrate 101 may include multiple implementation manners.
  • the first substrate 101 may include: a first conductive layer and a first insulating layer.
  • the first conductive layer and the first insulating layer are both disposed inside the packaging structure 100, and the first conductive surface of the first substrate 101 is the first conductive layer.
  • the first conductive layer can be made of conductive materials such as copper and Cu, and the first insulating layer can be made of insulating materials such as glass, ceramic, or epoxy.
  • the first conductive layer may be disposed on one surface of the first insulating layer by coating or etching.
  • the first substrate 101 may include: a first conductive layer, a first insulating layer, and a second conductive layer.
  • the first conductive layer and the first insulating layer are both disposed inside the packaging structure 100, the first conductive surface of the first substrate 101 is the first conductive layer, and the first insulating layer is located between the first conductive layer and the second conductive layer,
  • the second conductive surface of the first substrate 101 is a second conductive layer, and the second conductive layer is exposed to the outside of the package structure 100 to improve the heat dissipation capability of the package structure 100.
  • the first substrate 101 is illustrated with three rectangular frames, the rectangular frame close to the electronic component 103 is the first conductive layer, the middle rectangular frame is the first insulating layer, and the rectangular frame away from the electronic component 103 It is the second conductive layer.
  • the first conductive layer and the second conductive layer can be made of conductive materials such as copper and Cu
  • the first insulating layer can be made of insulating materials such as glass, ceramics, or epoxy resin.
  • the conductive layer is arranged on one surface of the first insulating layer and the second conductive layer is arranged on the other surface of the first insulating layer.
  • the first conductive surface of the first substrate 101 may include one conductive area or multiple conductive areas, and the multiple conductive areas are not connected. Generally, any conductive area corresponds to one component, or any conductive area corresponds to multiple connected components.
  • the first bonding layer 102 may include: a first bonding material 102b and at least one first supporting member 102a.
  • a first bonding material 102b may be included in the first bonding layer 102.
  • at least one first supporting member 102a may be illustrated by using two first supporting members 102a.
  • the specific type of the first bonding material 102b can be set according to the bonding mode, which is not limited in this application.
  • the first bonding material 102b may include a solder sheet or a solder paste.
  • the first bonding material 102b may include a powder material or a paste material.
  • the first bonding material 102b may include: solder sheet or solder paste; in the sintered layer, the first bonding material 102b may include: powder Material or paste material.
  • the first support member 102a may be set to a micron-level size, that is, the size of the first support member 102a in each dimension is all micron-level, since the first support member 102a has a size in each dimension that is all micron-level, therefore, Compared with the volume of the first bonding layer 102 with a size of several millimeters, the size of the first supporting member 102a is small, so that the first supporting member 102a has little influence on the process of the first bonding layer 102 during bonding, and will not It prevents the bubbles formed on the first bonding layer 102 from escaping from the first bonding material 102b, and prevents the void ratio of the first bonding layer 102 from being too high, thereby having less impact on the bonding of the first bonding layer 102, and avoiding The size of the at least one first support 102a is too large to reduce the bonding effect between the first conductive surface of the first substrate 101 and the first bonding surface of the electronic component 103, so that the first
  • each first support member 102a is fixedly arranged on the first joint surface of the electronic component 103, and the height of each first support member 102a is about 130 micrometers and the length is about 700 microns. Micron, the width is about 200 microns.
  • the electronic component 103 is bonded to the conductive surface of the first substrate 101, so that the void ratio of the electronic component 103 and the first substrate 101 after the bonding is measured by X-ray, as shown in FIG. 4, the void The rate meets the requirements of the manufacturing process, so that the setting of the first supporting member 102a has less influence on the bonding of the electronic component 103 and the first substrate 101.
  • the shapes of the first support members 102a in different first bonding layers 102 may be the same or different.
  • the shapes of the plurality of first support members 102a in the same first bonding layer 102 may be the same or different.
  • the present application does not limit the shape of the first support 102a.
  • the shape of the first support 102a includes at least one of a spherical shape, a rectangular parallelepiped shape, an ellipsoid shape, a wedge shape, or a silkworm shape.
  • the materials of the first support members 102a in different first bonding layers 102 may be the same or different.
  • the materials of the plurality of first support members 102a in the same first bonding layer 102 may be the same or different.
  • the material of the first support 102a is not limited in this application.
  • the first support 102a is any one of a single metal material, an alloy material, a composite material, or a non-conductive material.
  • the single metal material may include aluminum Al, gold Au, copper Cu, or nickel Ni.
  • the alloy material may include at least two of aluminum Al, gold Au, copper Cu, or nickel Ni.
  • the first support 102a is any one of a covering material, a coating material, a strip material, and a wire material. For example, metal coating or dissimilar metal coating. As a result, the manufacturing cost of the package structure 100 is reduced.
  • the number of first support members 102a in different first bonding layers 102 may be the same or different.
  • the present application does not limit the number of the first support members 102a in any one of the first bonding layers 102.
  • the number of the first support members 102a in the first bonding layer 102 can be adjusted.
  • the number of the first support members 102a can be greater than or equal to 3, which is beneficial to further improve the bonding effect of the first bonding layer 102, and can ensure the support balance of the first substrate 101 and the electronic component 103.
  • the positions of the first support members 102a in different first bonding layers 102 may be the same or different.
  • the present application does not limit the position of the first support member 102a in any one of the first bonding layers 102.
  • the position of the first support member 102a in the first bonding layer 102 is free, so that the first support member 102a of the required size can be implanted at the required position.
  • the first supporting member 102a in order to prevent the first supporting member 102a from being melted by the first bonding material 102b during bonding, the solder moves outside the first bonding layer 102, therefore, the first supporting member 102a may be fixedly arranged. Further, since the first supporting member 102a has a relatively small influence on the bonding of the first bonding layer 102, the first supporting member 102a can be arranged in a variety of positions, which is convenient and quick to operate and has high production efficiency.
  • At least one first support 102a may be fixedly disposed on the first joint surface of the electronic component 103.
  • the at least one first support 102a may also be fixedly disposed on the first conductive surface of the first substrate 101.
  • the at least one first support 102a may also be fixedly arranged on the first bonding surface of the electronic component 103 and the first conductive surface of the first substrate 101, and the first support on the first bonding surface of the electronic component 103
  • the members 102a and the first support members 102a on the first conductive surface of the first substrate 101 are alternately arranged.
  • the fixing method of the first support 102a is not limited in this application.
  • the first support 102a is fixedly arranged by any one of the following methods: ultrasonic wave, sintering, electroplating or brazing.
  • the height of the at least one first support 102a is the same as the thickness of the first bonding layer 102, and the melting point of the at least one first support 102a is higher than the highest temperature at which the first bonding layer 102 is formed.
  • the thickness of the first bonding layer 102 can be set according to actual conditions, which is not limited in this application.
  • the height of the first support 102a can be set according to the thickness of the corresponding first bonding layer 102, and the specific value of the height is not limited.
  • the heights of the first support members 102a in different first bonding layers 102 may be the same or different.
  • the at least one first support 102a in the process of forming the first bonding layer 102, will not completely dissolve in the first bonding material 102b in the first bonding layer 102, so that the at least one first support 102a is The thickness remains the same as the thickness of the first bonding layer 102, so that the first bonding layer 102 having the height of the at least one first supporting member 102a is formed by the at least one first supporting member 102a.
  • the at least one first supporting member 102a will not move with the movement of the first bonding material 102b, so that the at least one first supporting member 102a is on the first bonding layer 102
  • the distribution is uniform, and based on the supporting effect of the at least one first support 102a, the first bonding layer 102 can withstand compression without being deformed, so that even if the at least one first support 102a is remelted, it will not cause
  • the overflow of the first bonding material 102b in the first bonding layer 102 ensures the good quality and bonding strength of the first bonding layer 102, and avoids the lack of the first bonding material 102b under the electronic component 103 which may cause electrical short circuit of the electronic component 103 Or failures, etc., thereby ensuring that the surface of the first bonding layer 102 is flat and having a uniform thickness, which meets the process requirements for the thickness and warpage of the first bonding layer 102.
  • the first conductive surface of the first substrate 101 and the first bonding surface of the electronic component 103 achieve a good bonding effect and electrical connection through the first bonding layer 102, It also reduces joining costs.
  • the second bonding layer 104 is located between the second bonding surface of the electronic component 103 and the first conductive surface of the second substrate 105, and the second bonding layer 104 is used to realize the bonding of the electronic component 103 and the second substrate 105.
  • the first bonding surface of the electronic component 103 is opposite to the second bonding surface of the electronic component 103.
  • the number of the second bonding layer 104 can be one or more, which can be specifically set according to the electrical connection of the components in the electronic component 103.
  • one component corresponds to one second bonding layer 104.
  • one component can also correspond to multiple second bonding layers 104, which is not limited in this application.
  • the second substrate 105 may include multiple implementation manners.
  • the second substrate 105 may include: a third conductive layer and a second insulating layer.
  • the third conductive layer and the second insulating layer are both disposed inside the packaging structure 100, and the first conductive surface of the second substrate 105 is the third conductive layer.
  • the third conductive layer can be made of conductive materials such as copper and Cu, and the second insulating layer can be made of insulating materials such as glass, ceramic, or epoxy.
  • the third conductive layer may be disposed on one surface of the second insulating layer by coating or etching.
  • the second substrate 105 may include: a third conductive layer, a second insulating layer, and a fourth conductive layer.
  • the third conductive layer and the second insulating layer are both disposed inside the packaging structure 100, the first conductive surface of the second substrate 105 is the third conductive layer, and the second insulating layer is located between the third conductive layer and the fourth conductive layer,
  • the second conductive surface of the second substrate 105 is a fourth conductive layer, and the fourth conductive layer is exposed to the outside of the package structure 100 to improve the heat dissipation capability of the package structure 100.
  • the second substrate 105 is illustrated with three rectangular frames, the rectangular frame close to the electronic component 103 is the third conductive layer, the middle rectangular frame is the second insulating layer, and the rectangular frame away from the electronic component 103 It is the fourth conductive layer.
  • the third conductive layer and the fourth conductive layer can be made of conductive materials such as copper, Cu, and the second insulating layer can be made of insulating materials such as glass, ceramics, or epoxy.
  • the conductive layer is arranged on one surface of the second insulating layer and the fourth conductive layer is arranged on the other surface of the second insulating layer.
  • the first conductive surface of the second substrate 105 may include one conductive area, or may include multiple conductive areas, and the multiple conductive areas are not connected.
  • any conductive area corresponds to one component, or any conductive area corresponds to multiple connected components.
  • the first bonding layer 102 the first conductive surface of the first substrate 101, the first bonding layer 102, the electronic component 103, the second bonding layer 104, and the first conductive surface of the second substrate 105 are realized.
  • the firm bonding and reliable connection of the encapsulation structure improves the reliability of the package structure 100, reduces the manufacturing cost of the package structure 100, and improves the competitiveness of the package structure 100.
  • the packaging structure 100 may be a high-power semiconductor module, such as a double-side cooling power module (DSC-PM), and the packaging structure 100 may also be a semiconductor module with a printed circuit board, such as a control solder layer. A semiconductor device with a stacked structure to prevent solder overflow.
  • DSC-PM double-side cooling power module
  • the packaging structure 100 may also be a semiconductor module with a printed circuit board, such as a control solder layer.
  • the first bonding layer is disposed between the first conductive surface of the first substrate and the first bonding surface of the electronic component, so as to realize the bonding of the electronic component and the first substrate based on the first bonding layer .
  • the first bonding layer includes: a first bonding material and at least one first supporting member.
  • the second bonding layer is arranged between the second bonding surface of the electronic component and the first conductive surface of the second substrate, so that the bonding of the electronic component and the second substrate is realized based on the second bonding layer, and the first bonding of the electronic component The surface is opposite to the second bonding surface of the electronic component.
  • the height of the at least one first support member is the same as the thickness of the first bonding layer, and the melting point of the at least one first support member is higher than the highest temperature for forming the first bonding layer, in the process of forming the first bonding layer, The at least one first support member will not be completely dissolved in the first bonding material, so that the thickness of the at least one first support member remains the same as the thickness of the first bonding layer, so that the at least one first support member 102a has at least one The height of the first support is the first bonding layer.
  • the at least one first supporting member will not move with the movement of the first bonding material, so that the at least one first supporting member is evenly distributed in the first bonding layer, and Based on the supporting effect of the at least one first support member, the first bonding layer can withstand compression without being deformed, so that even if the at least one first support member is remelted, the first bonding material will not overflow, ensuring The good quality and bonding strength of the first bonding layer are avoided, and the lack of the first bonding material under the electronic components leads to electrical short circuit or failure of the electronic components, thereby ensuring that the surface of the first bonding layer is flat and the thickness is uniform.
  • the process requirements for the thickness and warpage of the first bonding layer are improved.
  • the first bonding material is no longer subject to the type limitation, which provides multiple possibilities for the production of the first bonding layer, which is beneficial to reducing the cost of the first bonding layer.
  • the reliability of the packaging structure is improved, the manufacturing cost of the packaging structure is reduced, and the competitiveness of the packaging structure is improved.
  • the second bonding layer 104 may include: a second bonding material 104b and at least one second support 104a.
  • a second bonding material 104b may be included in the second bonding layer 104.
  • one second bonding layer 104 in FIG. 2 is illustrated with two second supporting members 104a.
  • the specific type of the second bonding material 104b can be set in combination with the bonding method, which is not limited in this application.
  • the second bonding material 104b may include a solder sheet or a solder paste.
  • the second bonding material 104b may include a powder material or a paste material.
  • the second bonding material 104b may include: solder sheet or solder paste; in the sintered layer, the second bonding material 104b may include: powder Material or paste material.
  • the second support member 104a may be set to have a micron-level size, that is, the size of the second support member 104a in each dimension is all micron-level, because the second support member 104a has a size in each dimension that is all micron-level, therefore, Compared with the volume of the second bonding layer 104 with dimensions of several millimeters, the size of the second supporting member 104a is small, so that the second supporting member 104a has little influence on the process of the second bonding layer 104 during bonding, and will not It prevents the bubbles formed on the second bonding layer 104 from escaping from the second bonding material 104b, and prevents the void ratio of the second bonding layer 104 from being too high, so that the bonding effect on the second bonding layer 104 is small and avoids Because the size of the at least one second support 104a is too large, the bonding effect between the first conductive surface of the second substrate 105 and the second bonding surface of the electronic component 103 is reduced, so that the first
  • the shapes of the second support members 104a in different second bonding layers 104 may be the same or different.
  • the shapes of the plurality of second support members 104a in the same second bonding layer 104 may be the same or different.
  • the present application does not limit the shape of the second support 104a.
  • the shape of the second support 104a includes at least one of a spherical shape, a rectangular parallelepiped shape, an ellipsoid shape, a wedge shape, or a silkworm shape.
  • the material of the second support 104a in the different second bonding layers 104 may be the same or different.
  • the materials of the plurality of second support members 104a in the same second bonding layer 104 may be the same or different.
  • the material of the second support 104a is not limited in this application.
  • the second support 104a is any one of a single metal material, an alloy material, a composite material, or a non-conductive material.
  • the single metal material may include aluminum Al, gold Au, copper Cu, or nickel Ni.
  • the alloy material may include at least two of aluminum Al, gold Au, copper Cu, or nickel Ni.
  • the second support 104a is any one of a covering material, a coating material, a strip material, and a wire material. For example, metal coating or dissimilar metal coating. As a result, the manufacturing cost of the package structure 100 is reduced.
  • the number of second support members 104a in different second bonding layers 104 may be the same or different.
  • the present application does not limit the number of the second support members 104a in any one of the second bonding layers 104.
  • the number of the second support members 104a in the second bonding layer 104 can be adjusted.
  • the number of the second support members 104a can be greater than or equal to 3, which is beneficial to further improve the bonding effect of the second bonding layer 104, and can ensure the support balance of the second substrate 105 and the electronic component 103.
  • the positions of the second support members 104a in different second bonding layers 104 may be the same or different.
  • the present application does not limit the position of the second supporting member 104a in any one of the second bonding layers 104.
  • the position of the second support 104a in the second bonding layer 104 is free, so that the second support 104a of the required size can be implanted at the required position.
  • the second supporting member 104a in order to prevent the second supporting member 104a from being melted by the second bonding material 104b and the solder moving outside the second bonding layer 104 during bonding, the second supporting member 104a may be fixedly arranged. Further, since the second supporting member 104a has less influence on the joining of the second bonding layer 104, the second supporting member 104a can be arranged in a variety of positions, which is convenient and quick to operate and has high production efficiency.
  • At least one second support 104a may be fixedly disposed on the second joint surface of the electronic component 103.
  • the at least one second support 104a may also be fixedly disposed on the first conductive surface of the second substrate 105.
  • At least one second support 104a can also be fixedly arranged on the second bonding surface of the electronic component 103 and the first conductive surface of the second substrate 105, and the second support on the second bonding surface of the electronic component 103
  • the elements 104a and the second supporting elements 104a on the first conductive surface of the second substrate 105 are alternately arranged.
  • the fixing method of the second support 104a is not limited in this application.
  • the second support 104a is fixedly arranged by any one of the following methods: ultrasonic wave, sintering, electroplating or brazing.
  • the height of the at least one second supporting member 104a is the same as the thickness of the second bonding layer 104, and the melting point of the at least one second supporting member 104a is higher than the highest temperature at which the second bonding layer 104 is formed.
  • the thickness of the second bonding layer 104 can be set according to actual conditions, which is not limited in this application.
  • the height of the second support 104a can be set according to the thickness of the corresponding second bonding layer 104, and the specific value of the height is not limited.
  • the heights of the second support members 104a in different second bonding layers 104 may be the same or different.
  • the at least one second support 104a in the process of forming the second bonding layer 104, will not completely dissolve in the second bonding material 104b in the second bonding layer 104, so that the at least one second support 104a is The thickness remains the same as the thickness of the second bonding layer 104, so that the second bonding layer 104 having the height of the at least one second supporting member 104a is formed by the at least one second supporting member 104a.
  • the at least one second supporting member 104a will not move with the movement of the second bonding material 104b, so that the at least one second supporting member 104a is on the second bonding layer 104
  • the distribution is uniform, and based on the supporting effect of the at least one second support 104a, the second bonding layer 104 can withstand compression without being deformed, so that even if the at least one first support 102a is remelted, it will not cause
  • the overflow of the second bonding material 104b in the second bonding layer 104 ensures the good quality and bonding strength of the second bonding layer 104, and avoids that the second bonding material 104b under the second substrate 105 is insufficient and causes the electrical components of the electronic component 103
  • Such phenomena as short-circuit or failure ensure that the surface of the second bonding layer 104 is flat and the thickness is uniform, and the process requirements for the thickness and warpage of the second bonding layer 104 are met.
  • the first conductive surface of the second substrate 105 and the second bonding surface of the electronic component 103 achieve a good bonding effect and electrical connection through the second bonding layer 104, It also reduces joining costs.
  • the first conductive surface of the first substrate 101, the first bonding layer 102, the electronic components 103, the second bonding layer 104, and the second substrate are realized.
  • the firm bonding and reliable connection of the first conductive surface of 105 improves the reliability of the package structure 100, reduces the bonding cost of the package structure 100, and improves the competitiveness of the package structure 100.
  • the first support 102a can be fixed in multiple ways, and the second support 104a can also be fixed in multiple ways.
  • FIGS. 5 to 6 a specific implementation process in which both the first support member 102a and the second support member 104a are fixedly arranged on the electronic component 103 will be described as an example.
  • the shape of the first support member 102a and the second support member 104a are spherical, and the number of support members on the two joint surfaces of the electronic component 103 are both set to three.
  • FIG. 5 the shape of the first support member 102a and the second support member 104a are spherical, and the number of support members on the two joint surfaces of the electronic component 103 are both set to three.
  • the shape of the first support member 102a and the second support member 104a is a silkworm shape, and the number of support members on the two joint surfaces of the electronic component 103 is set to three. And since FIGS. 5 and 6 are cross-sectional views, FIGS. 5 and 6 only illustrate two supporting members on each of the two joint surfaces of the electronic component 103.
  • the ultrasonic working head 300 is used to implant three first minute metal blocks 102' on the upper joint surface of the electronic component 103 (only two of the first minute metal blocks are shown in FIG. 5). 102'), so that the upper joint surface of the electronic component 103 is fixedly provided with three first tiny metal blocks 102'.
  • the side of each first tiny metal block 102' close to the upper bonding surface of the electronic component 103 is spherical, and the height of each first tiny metal block 102' is greater than the thickness of the first bonding layer 102.
  • the height of the first tiny metal block 102' is between 0.02 mm and 10 mm, and the thickness of the first bonding layer 102 is between 0.01 mm and 10 mm.
  • the upper joint surface and the lower joint surface of the electronic component 103 are fixedly provided with three tiny metal blocks.
  • the upper bonding surface of the electronic component 103 is placed into the jig 601 so that the three first The supporting members 102a are respectively placed in the three holes of the jig 601, and then the jig 601 is pressed in the direction of the arrow shown in FIG.
  • the implementation process of this step is the same as the implementation process of the three first small metal blocks 102' on the upper bonding surface of the electronic component 103 to complete the planarization process, so this step is not illustrated in FIG. 5.
  • the upper joint surface of the electronic component 103 is provided with three first support members 102a
  • the lower joint surface of the electronic component 103 is provided with three second support members 104a
  • the first support member 102a and the second support member 104a are arranged symmetrically.
  • the bonding of the lower bonding surface of the electronic component 103 and the first bonding surface of the second substrate 105 can realize the control of the thickness and warpage of the second bonding layer 104, so that the surface of the second bonding layer 104 is flat and the thickness is uniform.
  • firstly, three first tiny metal blocks 102' are respectively implanted on the upper joint surface of the electronic component 103 by using the ultrasonic working head and the wedge 400 (Figure 6 only shows two of the first The tiny metal blocks 102'), so that the upper joint surface of the electronic component 103 is fixedly provided with three first tiny metal blocks 102'.
  • the side of each first tiny metal block 102 ′ close to the upper bonding surface of the electronic component 103 is silkworm-shaped, and the height of each first tiny metal block 102 ′ is greater than the thickness of the first bonding layer 102.
  • the height of the first tiny metal block 102' is between 0.02 mm and 10 mm
  • the thickness of the first bonding layer 102 is between 0.01 mm and 10 mm.
  • each second tiny metal block 104 ′ close to the lower bonding surface of the electronic component 103 is silkworm-shaped, and the height of each second tiny metal block 104 ′ is greater than the thickness of the second bonding layer 104.
  • the upper joint surface and the lower joint surface of the electronic component 103 are fixedly provided with three tiny metal blocks.
  • the upper joint surface of the electronic component 103 is placed into the jig 601 so that the three first The supporting members 102a are respectively placed in the three holes of the jig 601, and then the jig 601 is pressed along the direction of the arrow shown in FIG.
  • the remaining two thickness control rings 602 are used as an auxiliary function of height maintenance to adjust the heights of the three second tiny metal blocks 104' so that the heights of the three second tiny metal blocks 104' are connected to the second The thickness of the layer 104 is the same, so that three second support members 104a are fixedly provided on the lower bonding surface of the electronic component 103.
  • the implementation process of this step is the same as the implementation process of the three second small metal blocks 104' on the upper bonding surface of the electronic component 103 to complete the planarization process, so this step is not illustrated in FIG. 6.
  • the upper joint surface of the electronic component 103 is provided with three first support members 102a
  • the lower joint surface of the electronic component 103 is provided with three second support members 104a
  • the first support member 102a and the second support member 104a are arranged symmetrically.
  • the bonding of the lower bonding surface of the electronic component 103 and the first bonding surface of the second substrate 105 can realize the control of the thickness and warpage of the second bonding layer 104, so that the surface of the second bonding layer 104 is flat and the thickness is uniform.
  • the upper joint surface and the lower joint surface of the electronic component 103 are both provided with support members, the upper joint surface or the lower joint surface of the electronic component 103 can be arbitrarily selected to grip, which improves the efficiency of gripping.
  • the upper bonding surface of the electronic component 103 may also be provided with three second support members 104a, and the upper bonding surface of the electronic component 103 may also be provided with three first support members 102a.
  • the first substrate 101 and the second substrate 105 can be provided with supports on both sides, and the specific implementation process can refer to the above process, which will not be repeated here.
  • the electronic component 103 can also be fixedly provided with a support on only one joint surface.
  • the first substrate 101 and the second substrate 105 can also be provided with a support on one side.
  • FIGS. 7 and 8 the shape of the first support member 102a and the second support member 104a is a silkworm shape, and the number of the first support member 102a and the second support member 104a are both set to three. And since FIGS. 7 and 8 are cross-sectional views, FIGS. 7 and 8 only illustrate two first support members 102a and two second support members 104a.
  • first, three first support members 102a are implanted on the first bonding surface of the first substrate 101, and the height of each first support member 102a is kept the same as the thickness of the first bonding layer 102.
  • the melting point of each first support member 102a is higher than the highest temperature at which the first bonding layer 102 is formed.
  • the first bonding material 102b (such as solder tabs as shown in FIG. 7) is mounted on the three first supporting members 102a, and then the electronic component 103 is mounted on the first bonding material 102b. After one reflow, the electronic component 103 is soldered on the first bonding surface of the first substrate 101 through the first bonding layer 102.
  • the second bonding material 104b mounts the second bonding material 104b on the upper surface of the electronic component 103, and then implant three second support members 104a on the first bonding surface of the second substrate 105, and place the three second support members 104a facing toward On the upper surface of the second bonding material 104b, and the height of each second support 104a is the same as the thickness of the second bonding layer 104, and the melting point of each second support 104a is higher than that of the second bonding layer 104 The highest temperature.
  • the second substrate 105 is soldered on the electronic component 103 through the second bonding layer 104.
  • the first substrate 101, the electronic component 103, and the second substrate 105 can all be joined together to form the package structure 100.
  • the first bonding layer 102 is provided with the first support 102a, the height of the first support 102a can continue to be maintained during the secondary reflow process, and even if the first support 102a is melted, it will not cause When the first bonding material 102b overflows, there is no need to require the melting point of the first bonding material 102b to be higher than the melting point of the second bonding material 104b, so that the first bonding material 102b and the second bonding material 104b are not limited to types.
  • first, three first support members 102a are implanted on the first bonding surface of the first substrate 101, and the height of each first support member 102a is kept the same as the thickness of the first bonding layer 102.
  • the melting point of each first support member 102a is higher than the highest temperature at which the first bonding layer 102 is formed.
  • mount the first bonding material 102b (the solder tabs as shown in FIG. 8) on the three first support members 102a, and then mount the electronic component 103 on the first bonding material 102b.
  • the upper surface of the electronic component 103 Three second support members 104a are implanted thereon, and the height of each second support member 104a remains the same as the thickness of the second bonding layer 104, and the melting point of each second support member 104a is higher than that of the second bonding layer 104. The highest temperature.
  • the electronic component 103 is soldered on the first substrate 101 through the first bonding layer 102.
  • the second bonding material 104b is attached to the upper surface of the electronic component 103, and then the second substrate 105 is attached to the upper surface of the second bonding material 104b.
  • the second substrate 105 is soldered on the electronic component 103 through the second bonding layer 104.
  • the first substrate 101, the electronic component 103, and the second substrate 105 can all be joined together to form the package structure 100.
  • the first bonding layer 102 is provided with the first support 102a, the height of the first support 102a can continue to be maintained during the secondary reflow process, and even if the first support 102a is melted, it will not cause When the first bonding material 102b overflows, there is no need to require the melting point of the first bonding material 102b to be higher than the melting point of the second bonding material 104b, so that the first bonding material 102b and the second bonding material 104b are not limited to types.
  • FIG. 9 is a schematic structural diagram of a package structure provided by an embodiment of the application.
  • the packaging structure 100 provided in the present application may further include: a plastic packaging material 106.
  • the first substrate 101, the first bonding layer 102, the parts of the electronic component 103, the second bonding layer 104, and the second substrate 105 are all disposed in the molding material 106, so that the molding material 106 protects each part of the packaging structure 100 and The electrical connection between the various components facilitates the use of the package structure 100.
  • this application does not limit the specific type of the plastic packaging material 106.
  • one end of the terminal in the electronic component 103 is located in the plastic material 106, and the other end of the terminal is located outside the plastic material 106 to realize the electrical connection between the electronic component 103 and other parts.
  • the second conductive layer in the first substrate 101 will be exposed outside the plastic molding material 106, and the fourth conductive layer in the second substrate 105 will also be exposed outside the molding material 106.
  • the electronic component 103 may include multiple implementation manners.
  • two feasible implementation manners are adopted to illustrate the specific implementation manner of the electronic component 103.
  • the electronic component 103 may include: a chip 103a, a third bonding layer 103b, an interconnection pillar 103c, a signal terminal 103d, and a power terminal 103e.
  • a chip 103a are used as an example for illustration
  • two interconnection posts 103c are used as an example for illustration
  • two power terminals 103e are used as an example for illustration
  • a signal terminal 103d is used as an example for illustration.
  • the chip 103a is located between the first bonding layer 102 and the third bonding layer 103b except the first bonding layer 102 corresponding to the signal terminal 103d and the first bonding layer 102 corresponding to the power terminal 103e, and the interconnection pillar 103c It is located between the third bonding layer 103b corresponding to the chip 103a and the corresponding second bonding layer 104.
  • the number of chips 103a can be one or more, and the number of interconnecting posts 103c can be one or more.
  • the number of the chip 103a is one, the chip 103a is bonded to the first conductive surface of the first substrate 101 through a first bonding layer 102, and the chip 103a is bonded to an interconnection pillar 103c through a third bonding layer 103b.
  • the interconnection post 103c is bonded to the first conductive surface of the second substrate 105 through a second bonding layer 104.
  • each chip 103a is bonded to the first conductive surface of the first substrate 101 through a first bonding layer 102, and each chip 103a is bonded to an interconnection post 103c through a third bonding layer 103b.
  • Each interconnection pillar 103c is bonded to the first conductive surface of the second substrate 105 through a second bonding layer 104.
  • the thickness of each interconnection pillar 103c can be used to adjust the thickness of the chip 103a, so that the overall thickness of the package structure 100 meets actual thickness requirements, wherein the thickness of each interconnection pillar 103c is usually the same.
  • the thickness of the chip 103a can be adjusted with the help of each interconnection pillar 103c, so that the thickness of the package structure 100 maintains a flat surface, and the reliability of the package structure 100 is improved.
  • each chip 103a when multiple chips 103a have a connection relationship, the same conductive area in the first conductive surface of the first substrate 101 to which the first bonding layer 102 corresponding to each chip 103a is bonded, and/or each chip 103a corresponds to The same conductive area in the first conductive surface of the second substrate 105 to which the interconnection posts 103c are joined.
  • the conductive area in the first conductive surface of the first substrate 101 to which the first bonding layer 102 corresponding to the IGBT is bonded is the first bonding corresponding to the FRD.
  • the conductive area in the first conductive surface of the first substrate 101 joined by the layer 102 is the same, and the conductive area in the first conductive surface of the second substrate 105 joined by the interconnection pillar 103c corresponding to the IGBT is interconnected with the FRD corresponding
  • the conductive areas on the first conductive surface of the second substrate 105 joined by the pillars 103c are the same.
  • the signal terminal 103d can transmit signals output by other components to the chip 103a, or transmit signals output by the chip 103a to other components, and can also implement the above two processes, which is not limited in this application. Among them, this application does not limit the specific number of signal terminals 103d.
  • the signal terminal 103d extends from the inside of the package structure 100 to the outside of the package structure 100, and one end of the signal terminal 103d located inside the package structure 100 is located in addition to the one corresponding to the chip 103a.
  • the signal terminal 103d is electrically connected to the chip 103a, and the first bonding layer 102 corresponding to the chip 103a corresponds to the signal terminal 103d
  • Each of the first bonding layers 102 corresponds to a different conductive area in the first conductive surface of the first substrate 101.
  • the electrical connection manners of the signal terminal 103d and the chip 103a may include a variety of ways, as shown in FIG. 10, the electrical connection between the two is realized by the aluminum Al wire bonding manner. Since the wires need to be drawn from the chip 103a to the conductive area on the first conductive surface of the first substrate 101 to which the signal terminals 103d are joined, the upper part of the chip 103a needs to reserve space for the wires with the help of the interconnection posts 103c, thereby Ensure the reliable connection between the signal terminal 103d and the chip 103a to avoid interference from other factors.
  • the power terminal 103e can transmit the voltage or current after the power conversion of the chip 103a to other parts, such as transmitting alternating current to other parts. Among them, this application does not limit the specific number of power terminals 103e.
  • the power terminal 103e may be directly connected to the chip 103a, or indirectly connected to the chip 103a through the interconnection column 103c.
  • the power terminal 103e When the power terminal 103e is directly connected to the chip 103a, the power terminal 103e can extend from the inside of the package structure 100 to the outside of the package structure 100, and one end of the power terminal 103e located inside the package structure 100 is located except for the first chip corresponding to the chip 103a.
  • the first bonding layer 102 corresponding to the chip 103a and the first bonding layer 102 corresponding to the power terminal 103e each correspond to the first bonding layer 102.
  • the power terminal 103e is connected to the conductive area on the first conductive surface of the first substrate 101 through one first bonding layer 102 and the chip 103a is connected to the first substrate 101 through another first bonding layer 102.
  • the conductive area in the conductive surface is the same, so that the power terminal 103e and the chip 103a can be electrically interconnected.
  • the power terminal 103e When the power terminal 103e is indirectly connected to the chip 103a through the interconnection pillar 103c, the power terminal 103e may be located on the second bonding layer 104 except the second bonding layer 104 corresponding to the interconnection pillar 103c, and the second bonding layer 104 corresponding to the interconnection pillar 103c
  • the second bonding layers 104 corresponding to the power terminals 103e each correspond to the same conductive area in the first conductive surface of the second substrate 105.
  • the power terminal 103e is connected to the conductive area on the first conductive surface of the second substrate 105 through one second bonding layer 104 and the interconnection post 103c is connected to the second substrate 105 through another second bonding layer 104.
  • the conductive areas in one conductive surface are the same, so that the power terminal 103e and the chip 103a can be electrically interconnected.
  • the power terminals 103e can adopt any of the above-mentioned positional relationships.
  • the multiple power terminals 103e can adopt any one of the above-mentioned positional relationships, or both of the above-mentioned positional relationships can be used at the same time (this method is used for illustration in FIG. 10). Not limited.
  • the third bonding layer 103b may include: a third bonding material 103bb and at least one third support 103ba.
  • a third bonding material 103bb and at least one third support 103ba.
  • one third bonding layer 103b in FIG. 10 uses two third support members 103ba as an example for illustration.
  • the specific type of the third bonding material 103bb can be set in combination with the bonding method, which is not limited in this application.
  • the third bonding material 103bb may include: solder tabs or solder paste.
  • the third bonding material 103bb may include: powder material or paste material.
  • the third bonding material 103bb may include: solder sheet or solder paste; in the sintered layer, the third bonding material 103bb may include: powder Material or paste material.
  • the third support 103ba may be set to a micron-level size, that is, the third support 103ba has a micron-level size in each dimension. Since the third support 103ba has a micron-level size in each dimension, Compared with the volume of the third bonding layer 103b with dimensions of several millimeters, the size of the third supporting member 103ba is small, so that the third supporting member 103ba has little influence on the process of the third bonding layer 103b during bonding, and will not It prevents the bubbles formed on the third bonding layer 103b from escaping from the third bonding material 103b, and prevents the void ratio of the third bonding layer 103 from being too high, thus, the bonding effect on the third bonding layer 103b is small, and it is avoided Since the size of the at least one third support 103ba is too large, the bonding effect between the chip 103a and the interconnection pillar 103c is reduced, so that the chip 103a and the interconnection
  • the shapes of the third support members 103ba in different third bonding layers 103b may be the same or different.
  • the shapes of the plurality of third support members 103ba in the same third bonding layer 103b may be the same or different.
  • the present application does not limit the shape of the third support 103ba.
  • the shape of the third support 103ba includes at least one of a spherical shape, a rectangular parallelepiped shape, an ellipsoid shape, a wedge shape, or a silkworm shape.
  • the materials of the third support members 103ba in different third bonding layers 103b may be the same or different.
  • the materials of the plurality of third support members 103ba in the same third bonding layer 103b may be the same or different.
  • this application does not limit the material of the third support 103ba.
  • the third support 103ba is any one of a single metal material, an alloy material, a composite material, or a non-conductive material.
  • the single metal material may include aluminum Al, gold Au, copper Cu, or nickel Ni.
  • the alloy material may include at least two of aluminum Al, gold Au, copper Cu, or nickel Ni.
  • the third support 103ba is any one of a covering material, a coating material, a strip material, and a wire material. For example, metal coating or dissimilar metal coating. As a result, the manufacturing cost of the package structure 100 is reduced.
  • the number of third support members 103ba in different third bonding layers 103b may be the same or different.
  • the present application does not limit the number of third support members 103ba in any third bonding layer 103b.
  • the positions of the third support members 103ba in different third bonding layers 103b may be the same or different.
  • the present application does not limit the position of the third supporting member 103ba in any one of the third bonding layers 103b.
  • the number of third support members 103ba in the third bonding layer 103b can be adjusted.
  • the number of the third support members 103ba can be greater than or equal to 3, which is beneficial to further improve the bonding effect of the third bonding layer 103b, and can ensure the support balance of the chip 103a and the interconnection pillar 103c.
  • the positions of the third support members 103ba in different third bonding layers 103b may be the same or different.
  • the present application does not limit the position of the third supporting member 103ba in any one of the third bonding layers 103b.
  • the position of the third support 103ba in the third bonding layer 103b is free, so that the third support 103ba of the required size can be implanted at the required position.
  • the third support 103ba in order to prevent the third support 103ba from being melted by the third joining material 103bb during joining, and the solder moves out of the third joining layer 103b, the third support 103ba may be fixedly arranged. Further, since the third supporting member 103ba has less influence on the bonding of the third bonding layer 103b, the third supporting member 103ba can be arranged in a variety of positions, which is convenient and quick to operate and has high production efficiency.
  • At least one third supporting member 103ba may be fixedly disposed on a side of the chip 103a close to the interconnection pillar 103c.
  • At least one third supporting member 103ba may be fixedly disposed on the side of the interconnection pillar 103c close to the chip 103a.
  • At least one third supporting member 103ba may be fixedly disposed on the side of the chip 103a close to the interconnection column 103c and the side of the interconnection column 103c close to the chip 103a, and the first side of the chip 103a on the side close to the interconnection column 103c
  • the three support members 103ba and the third support members 103ba on the side of the interconnection column 103c close to the chip 103a are alternately arranged.
  • the third support 103ba is fixedly arranged by any one of the following methods: ultrasonic wave, sintering, electroplating or brazing.
  • the height of the at least one third support 103ba is the same as the thickness of the third bonding layer 103b, and the melting point of the at least one third support 103ba is higher than the highest temperature at which the third bonding layer 103b is formed.
  • the thickness of the third bonding layer 103b can be set according to actual conditions, which is not limited in this application.
  • the height of the third support 103ba can be set according to the thickness of the corresponding third bonding layer 103b, and the specific value of the height is not limited.
  • the heights of the third support members 103ba in different third bonding layers 103b may be the same or different.
  • the at least one third support 103ba in the process of forming the third bonding layer 103b, the at least one third support 103ba will not be completely dissolved in the third bonding material 103bb in the third bonding layer 103b, so that the at least one third support 103ba is The thickness remains the same as that of the third bonding layer 103b, so that the third bonding layer 103b having the height of the at least one third support 103ba is formed by the at least one third support 103ba.
  • the at least one third support 103ba will not move with the movement of the third bonding material 103bb, so that the at least one third support 103ba is on the third bonding layer 103b.
  • the distribution is uniform, and based on the supporting effect of the at least one third support 103ba, the third bonding layer 103b can withstand compression without being deformed, so that even if the at least one third support 103ba remelts, it will not cause
  • the third bonding material 103bb in the third bonding layer 103b overflows, ensuring the good quality and bonding strength of the third bonding layer 103b, and avoiding the lack of the third bonding material 103bb under the interconnection posts 103c, which may cause electrical short-circuits or electrical shorts of the chip 103a.
  • the third bonding material 103bb in the third bonding layer 103b is no longer restricted by types, which provides multiple possibilities for the production of the third bonding layer 103b, which is beneficial to reduce the cost of the third bonding layer 103b.
  • the chip 103a and the interconnection pillar 103c achieve a good bonding effect and electrical connection through the third bonding layer 103b, and the bonding cost is also reduced.
  • the first conductive surface of the first substrate 101, the first bonding layer 102, the chip 103a, and the third bonding layer are realized.
  • connection and the firm connection and reliable connection of the power terminal 103e with the first conductive surface of the first substrate 101 and/or with the first conductive surface of the second substrate 105 not only improve the reliability of the package structure 100, but also reduce the package structure
  • the bonding cost of 100 also enables the package structure 100 to realize a complete power conversion process.
  • the electronic component 103 may include: a chip 103a, signal terminal 103d, and power terminal 103e.
  • a chip 103a For ease of description, in FIG. 11, two chips 103a are used as an example for illustration, two power terminals 103e are used as an example for illustration, and one signal terminal 103d is used as an example for illustration.
  • the chip 103a is located between the first bonding layer 102 and the corresponding second bonding layer 104 except for the first bonding layer 102 corresponding to the signal terminal 103d and the first bonding layer 102 corresponding to the power terminal 103e.
  • the number of chips 103a may be one or more. Generally, when the number of chips 103a is one, the chip 103a is bonded to the first conductive surface of the first substrate 101 through a first bonding layer 102, and the chip 103a is bonded to the second substrate 105 through a second bonding layer 104. The first conductive surface is joined. When the number of chips 103a is multiple, each chip 103a is bonded to the first conductive surface of the first substrate 101 through a first bonding layer 102, and each chip 103a is bonded to the second substrate 105 through a second bonding layer 104 The first conductive surface is joined.
  • connection method is generally applicable to scenarios where the thickness of multiple chips 103a is the same, so that the overall thickness of the package structure 100 can meet actual thickness requirements, so that the thickness of the package structure 100 is kept flat and the reliability of the package structure 100 is improved.
  • each chip 103a when multiple chips 103a have a connection relationship, the same conductive area in the first conductive surface of the first substrate 101 to which the first bonding layer 102 corresponding to each chip 103a is bonded, and/or each chip 103a corresponds to The same conductive area in the first conductive surface of the second substrate 105 to which the second bonding layer 104 is bonded.
  • the conductive area in the first conductive surface of the first substrate 101 to which the first bonding layer 102 corresponding to the IGBT is bonded is the first bonding corresponding to the FRD.
  • the conductive area in the first conductive surface of the first substrate 101 joined by the layer 102 is the same, and the conductive area in the first conductive surface of the second substrate 105 joined by the second joining layer 104 corresponding to the IGBT corresponds to FRD
  • the conductive regions in the first conductive surface of the second substrate 105 joined by the second bonding layer 104 are the same.
  • the signal terminal 103d can transmit signals output by other components to the chip 103a, or transmit signals output by the chip 103a to other components, and can also implement the above two processes, which is not limited in this application. Among them, this application does not limit the specific number of signal terminals 103d.
  • the signal terminal 103d is joined to the signal terminal of the first substrate 101 through a welding or sintering process. Since the metal terminals have a certain weight, and in order to prevent deformation of the terminals when the packaged module 100 is manufactured, pressure is often applied to the terminals. Therefore, in order to realize signal output and/or input, the signal terminal 103d extends from the inside of the package structure 100 to the outside of the package structure 100, and in order to avoid overflowing the first bonding material 101b, the signal terminal located inside the package structure 100 One end of 103d is located on the first bonding layer 102 except for the first bonding layer 102 corresponding to the chip 103a and the first bonding layer 102 corresponding to the power terminal 103e.
  • the first bonding layer 102 includes a first bonding material 102b and The first supporting member 102a fixedly arranged on the first conductive surface of the first substrate 101, the signal terminal 103d is electrically connected to the chip 103a, the first bonding layer 102 corresponding to the chip 103a and the first bonding layer 102 corresponding to the signal terminal 103d are respectively Corresponding to different conductive areas on the first conductive surface of the first substrate 101, the interconnection between the signal electrodes of the chip 103a and the signal terminals 103d on the first substrate 101 is realized.
  • the signal terminal 103d and the chip 103a can be electrically connected in a variety of ways. As shown in FIG. The terminals are interconnected to realize the electrical connection between the two.
  • the power terminal 103e can transmit the voltage or current after the power conversion of the chip 103a to other parts, such as transmitting alternating current to other parts. Among them, this application does not limit the specific number of power terminals 103e.
  • the power terminal 103e may be connected to the chip 103a through the first bonding layer 102, or may be connected to the chip 103a through the second bonding layer 104.
  • the power terminal 103e When the power terminal 103e is connected to the chip 103a through the first bonding layer 102, the power terminal 103e may extend from the inside of the package structure 100 to the outside of the package structure 100, and one end of the power terminal 103e located inside the package structure 100 is located in addition to and The first bonding layer 102 corresponding to the chip 103a and the first bonding layer 102 other than the first bonding layer 102 corresponding to the signal terminal 103d.
  • the first bonding layer 102 includes the first bonding material 102b and is fixedly arranged on the first substrate
  • the first support 102a on the first conductive surface of 101, the first bonding layer 102 corresponding to the chip 103a, and the first bonding layer 102 corresponding to the power terminal 103e each correspond to the same conductive surface in the first conductive surface of the first substrate 101 area.
  • the power terminal 103e is connected to the conductive area on the first conductive surface of the first substrate 101 through one first bonding layer 102 and the chip 103a is connected to the first substrate 101 through another first bonding layer 102.
  • the conductive area in the conductive surface is the same, so that the power terminal 103e and the chip 103a can be electrically interconnected.
  • the power terminal 103e When the power terminal 103e is connected to the chip 103a through the second bonding layer 104, the power terminal 103e may be located on the second bonding layer 104 other than the second bonding layer 104 corresponding to the chip 103a, and the second bonding layer 104 includes the first bonding layer 104.
  • the second bonding material 104b and the second support 104a fixedly arranged on the first conductive surface of the second substrate 105, the second bonding layer 104 corresponding to the chip 103a and the second bonding layer 104 corresponding to the power terminal 103e each correspond to the second The same conductive area in the first conductive surface of the substrate 105.
  • the power terminal 103e is connected to the conductive area of the first conductive surface of the second substrate 105 through one second bonding layer 104 and the chip 103a is connected to the first of the second substrate 105 through another second bonding layer 104.
  • the conductive area in the conductive surface is the same, so that the power terminal 103e and the chip 103a can be electrically interconnected.
  • the power terminals 103e can adopt any of the above-mentioned positional relationships.
  • the multiple power terminals 103e may adopt any one of the above-mentioned positional relationships, and may also adopt the above-mentioned two positional relationships at the same time (this method is used for illustration in FIG. 11). Not limited.
  • the first conductive surface of the first substrate 101, the first bonding layer 102, the chip 103a, and the second bonding layer are realized.
  • 104 and the first conductive surface of the second substrate 105 are firmly bonded and reliably connected, and the signal terminal 103d and the first conductive surface of the first substrate 101 are firmly bonded and reliably connected, as well as the power terminal 103e and the first substrate.
  • the firm bonding and reliable connection of the first conductive surface of 101 and/or the first conductive surface of the second substrate 105 not only improves the reliability of the package structure 100, reduces the bonding cost of the package structure 100, but also makes the package structure 100 more reliable. A complete power conversion process can be realized.
  • each chip 103a in the partial chips 103a is bonded to the first conductive surface of the first substrate 101 through a first bonding layer 102
  • Each chip 103a is bonded to an interconnection pillar 103c through a third bonding layer 103b, and each interconnection pillar 103c is bonded to the first conductive surface of the second substrate 105 through a second bonding layer 104.
  • Each of the remaining chips 103a is bonded to the first conductive surface of the first substrate 101 through a first bonding layer 102, and each chip 103a is bonded to the first conductive surface of the second substrate 105 through a second bonding layer 104 combine.
  • the electronic component 103 may further include a sensor 107.
  • this application does not limit the category of the sensor 107.
  • the sensor 107 may be an NTC temperature sensor 107.
  • the present application does not limit the joining method of the sensor 107.
  • the two ends of the sensor 107 and the sensor terminals may be respectively located on the first bonding layer 102 corresponding to the chip 103a and the first bonding layer corresponding to the signal terminal 103d.
  • the first bonding layer 102 includes the first bonding material 102b and fixedly arranged on the first conductive surface of the first substrate 101
  • the first supporting member 102a, the first bonding layer 102 corresponding to the chip 103a, and the two first bonding layers 102 corresponding to the sensor 107 respectively correspond to different conductive areas in the first conductive surface of the first substrate 101, thereby realizing the sensor 107 and The first substrate 101 is bonded, and the signal of the sensor 107 is extracted to the outside of the package structure 100 through the sensor terminal.
  • one end of the sensor 107 is located except for the first bonding layer 102 corresponding to the chip 103a, the first bonding layer 102 corresponding to the signal terminal 103d, and the power terminal 103e.
  • the first bonding layer 102 includes a first bonding material 102b and a first support 102a fixedly arranged on the first conductive surface of the first substrate 101 The other end of the sensor 107 extends from the inside of the package structure 100 to the outside of the package structure 100 through a transmission wire.
  • the first bonding layer 102 corresponding to the chip 103a and the first bonding layer 102 corresponding to the sensor 107 each correspond to the first substrate 101
  • the other end of the sensor 107 is electrically connected to the sensor terminal (the upper wire of the sensor 107 in FIG. 13 is electrically connected to the bonding layer of the sensor terminal on the first substrate 101), so as to achieve
  • the sensor 107 is bonded to the first substrate 101, and the signal of the sensor 107 is led to the outside of the package structure 100 through the sensor terminal.
  • the sensor terminal is electrically connected to the sensor 107 through an aluminum Al wire. I won’t repeat it here.
  • the sensor 107 can also be arranged in conjunction with the packaging structure 100 shown in FIG. 11, and FIGS. 12 and 13 are only feasible examples.
  • the electronic component 103 may also include, but is not limited to, a resistor, a capacitor, or an inductor. Among them, the resistance, capacitance, and inductance can be joined to the sensor 107 in the first joining method of the sensor 107, which will not be repeated here.
  • the highly integrated and high-density packaging structure 100 has high requirements for heat dissipation. Based on this, in order to further improve the cooling capacity of the package structure 100, as shown in FIG. 14 and FIG. 15, the package structure 100 provided in the present application may further include: a first heat sink 108 and a fourth bonding layer 109.
  • FIG. 14 and FIG. 15 use a first heat sink 108 and a fourth bonding layer 109 for illustration, and FIG. 14 illustrates the package structure 100 based on the embodiment shown in FIG. 9, and FIG. 15 shows The embodiment shown in 10 illustrates the package structure 100 based on it.
  • the fourth bonding layer 109 is located between the first conductive surface (ie, the second conductive layer) of the first substrate 101 and the first heat sink 108, and the fourth bonding layer 109 is used to realize the first substrate 101 and the first heat sink 108.
  • the fourth bonding layer 109 may include: a fourth bonding material 109b and at least one fourth support 109a.
  • one fourth bonding layer 109 in FIG. 14 and FIG. 15 uses five fourth support members 109a for illustration.
  • the specific type of the fourth bonding material 109b can be set in combination with the bonding method, which is not limited in this application.
  • the fourth bonding material 109b may include: a solder sheet or a solder paste.
  • the fourth bonding material 109b may include a powder material or a paste material.
  • the fourth bonding material 109b may include: solder sheet or solder paste; in the sintered layer, the fourth bonding material 109b may include: powder Material or paste material.
  • the fourth support 109a may be set to have a size of micrometers, that is, the size of the fourth support 109a in each dimension is all micrometers, since the size of the fourth support 109a in each dimension is all micrometers, therefore, Compared with the volume of the fourth bonding layer 109 with dimensions of several millimeters, the size of the fourth supporting member 109a is small, so that the fourth supporting member 109a has little influence on the process of the fourth bonding layer 109 during bonding, and will not It prevents the bubbles formed on the fourth bonding layer 109 from escaping from the fourth bonding material 109b, and prevents the void ratio of the fourth bonding layer 109 from being too high, thus, the bonding effect on the fourth bonding layer 109 is small and avoids Because the size of the at least one fourth supporting member 109a is too large, the bonding effect between the second conductive surface of the first substrate 101 and the first heat sink 108 is reduced, so that the first substrate 101 and the first heat sink 108 can be reliabl.
  • the shape of the fourth support 109a in different fourth bonding layers 109 may be the same or different.
  • the shapes of the plurality of fourth support members 109a in the same fourth bonding layer 109 may be the same or different. Among them, the present application does not limit the shape of the fourth support 109a.
  • the shape of the fourth support 109a includes at least one of a spherical shape, a rectangular parallelepiped shape, an ellipsoid shape, a wedge shape, or a silkworm shape.
  • the material of the fourth support 109a in different fourth bonding layers 109 may be the same or different.
  • the materials of the plurality of fourth support members 109a in the same fourth bonding layer 109 may be the same or different.
  • the material of the fourth support 109a is not limited in this application.
  • the fourth support 109a is any one of a single metal material, an alloy material, a composite material, or a non-conductive material.
  • the single metal material may include aluminum Al, gold Au, copper Cu, or nickel Ni.
  • the alloy material may include at least two of aluminum Al, gold Au, copper Cu, or nickel Ni.
  • the first support 102a is any one of a covering material, a coating material, a strip material, and a wire material. For example, metal coating or dissimilar metal coating. As a result, the manufacturing cost of the package structure 100 is reduced.
  • the number of fourth support members 109a in different fourth bonding layers 109 may be the same or different.
  • the present application does not limit the number of the fourth supporting members 109a in any one of the fourth bonding layers 109.
  • the number of the fourth support members 109a in the first bonding layer 102 can be adjusted.
  • the number of the fourth support members 109a can be greater than or equal to 3, which is beneficial to further improve the bonding effect of the fourth bonding layer 109 and can ensure the support balance of the first substrate 101 and the first heat dissipation member 108.
  • the positions of the fourth support 109a in different fourth bonding layers 109 may be the same or different.
  • the present application does not limit the position of the fourth support 109a in any one of the fourth bonding layers 109.
  • the position of the fourth support 109a in the fourth bonding layer 109 is free, so that the fourth support 109a of the required size can be implanted at the required position.
  • the fourth support 109a in order to prevent the fourth support 109a from being melted by the fourth joining material 109b during joining, and the solder moves outside the fourth joining layer 109, the fourth support 109a may be fixedly arranged. Further, since the fourth supporting member 109a has less influence on the joining of the fourth bonding layer 109, the fourth supporting member 109a can be arranged in a variety of positions, which is convenient and quick to operate and has high production efficiency.
  • At least one fourth support 109a may be fixedly disposed on the second conductive surface of the first substrate 101.
  • At least one fourth supporting member 109a may be fixedly disposed on a surface of the first heat dissipation member 108 close to the first substrate 101.
  • At least one fourth supporting member 109a may be fixedly disposed on the second conductive surface of the first substrate 101 and a surface of the first heat sink 108 close to the first substrate 101, and the second conductive surface of the first substrate 101.
  • the upper fourth support 109a and the fourth support 109a on the side of the first heat sink 108 close to the first substrate 101 are arranged alternately.
  • the fixing method of the fourth support 109a is not limited in this application.
  • the fourth support 109a is fixedly arranged by any one of the following methods: ultrasonic, sintering, electroplating or brazing.
  • the height of at least one fourth supporting member 109a is the same as the thickness of the fourth bonding layer 109, and the melting point of the at least one fourth supporting member 109a is higher than the highest temperature at which the fourth bonding layer 109 is formed.
  • the thickness of the fourth bonding layer 109 can be set according to actual conditions, which is not limited in this application.
  • the height of the fourth support 109a can be set according to the thickness of the corresponding fourth bonding layer 109, and the specific value of the height is not limited.
  • the height of the fourth support 109a in different fourth bonding layers 109 may be the same or different.
  • At least one fourth support 109a will not completely dissolve in the fourth bonding material 109b in the fourth bonding layer 109, so that the at least one fourth support 109a is The thickness remains the same as the thickness of the fourth bonding layer 109 so that the fourth bonding layer 109 having the height of the at least one fourth supporting member 109a is formed by the at least one fourth supporting member 109a.
  • the at least one fourth support 109a will not move with the movement of the fourth bonding material 109b, so that the at least one fourth support 109a is on the fourth bonding layer 109
  • the distribution is uniform, and based on the supporting effect of the at least one fourth support 109a, the fourth bonding layer 109 can withstand compression without being deformed, so that even if the at least one fourth support 109a is remelted, it will not cause
  • the fourth bonding material 109b in the fourth bonding layer 109 overflows, ensuring the good quality and bonding strength of the fourth bonding layer 109, thereby ensuring that the surface of the fourth bonding layer 109 is flat and having uniform thickness, which satisfies the need for the fourth bonding layer.
  • the fourth bonding material 109b in the fourth bonding layer 109 is no longer restricted by type, which provides multiple possibilities for the production of the fourth bonding layer 109, which is beneficial to reducing the cost of the fourth bonding layer 109.
  • the first substrate 101 and the first heat sink 108 achieve a good bonding effect through the fourth bonding layer 109, which improves the reliability and cooling capacity of the package structure 100 , It also reduces the bonding cost, which is conducive to the high density and high integration of the package structure 100.
  • the package structure 100 provided in the present application may further include: a second heat sink 110 and a fifth bonding layer 111.
  • the number of the second heat sink 110 and the fifth bonding layer 111 is not limited in the present application, and one second heat sink 110 corresponds to one fifth bonding layer 111 or multiple fifth bonding layers 111.
  • a second heat sink 110 and a fifth bonding layer 111 are used for illustration in FIGS. 14 and 15.
  • the fifth bonding layer 111 is located between the second conductive surface (that is, the fourth conductive layer) of the second substrate 105 and the second heat sink 110, and the fifth bonding layer 111 is used to realize the second substrate 105 and the second heat sink 110.
  • the fifth bonding layer 111 may include: a fifth bonding material 111b and at least one fifth support 111a.
  • one fifth bonding layer 111 in FIG. 14 and FIG. 15 is illustrated by using five fifth supporting members 111a.
  • the specific type of the fifth bonding material 111b can be set in combination with the bonding method, which is not limited in this application.
  • the fifth bonding material 111b may include a solder sheet or a solder paste.
  • the fifth bonding material 111b may include a powder material or a paste material.
  • the fifth bonding material 111b may include: solder sheet or solder paste; in the sintered layer, the fifth bonding material 111b may include: powder Material or paste material.
  • the fifth supporting member 111a may be set to have a micron-level size, that is, the dimensions of the fifth supporting member 111a in each dimension are all micron-level, and since the fifth supporting member 111a has a size in each dimension are all micron-level, therefore, Compared with the volume of the fifth bonding layer 111 with dimensions of several millimeters, the size of the fifth supporting member 111a is small, so that the fifth supporting member 111a has little influence on the process of the fifth bonding layer 111 during bonding, and will not It prevents the bubbles formed on the fifth bonding layer 111 from escaping from the fifth bonding material 111b, and prevents the void ratio of the fifth bonding layer 111 from being too high, thus, the bonding effect on the fifth bonding layer 111 is small and avoids Because the size of the at least one fifth support 111a is too large, the bonding effect between the second conductive surface of the second substrate 105 and the second heat sink 110 is reduced, so that the second substrate 105 and the second
  • the shapes of the fifth supporting members 111a in different fifth bonding layers 111 may be the same or different. And/or, the shapes of the plurality of fifth supporting members 111a in the same fifth bonding layer 111 may be the same or different. Among them, the present application does not limit the shape of the fifth support 111a.
  • the shape of the fifth support 111a includes at least one of a spherical shape, a rectangular parallelepiped shape, an ellipsoid shape, a wedge shape, or a silkworm shape.
  • the material of the fifth support 111a in different fifth bonding layers 111 may be the same or different. And/or, the materials of the plurality of fifth support members 111a in the same fifth bonding layer 111 may be the same or different. Among them, the material of the fifth support 111a is not limited in this application.
  • the fifth support 111a is any one of a single metal material, an alloy material, a composite material, or a non-conductive material.
  • the single metal material may include aluminum Al, gold Au, copper Cu, or nickel Ni.
  • the alloy material may include at least two of aluminum Al, gold Au, copper Cu, or nickel Ni.
  • the first support 102a is any one of a covering material, a coating material, a strip material, and a wire material. For example, metal coating or dissimilar metal coating. As a result, the manufacturing cost of the package structure 100 is reduced.
  • the number of fifth support members 111a in different fifth bonding layers 111 may be the same or different.
  • the present application does not limit the number of the fifth supporting members 111a in any one of the fifth bonding layers 111.
  • the number of the fifth support members 111a in the fifth bonding layer 111 can be adjusted.
  • the number of the fifth supporting member 111a can be greater than or equal to 3, which is beneficial to further improve the bonding effect of the fifth bonding layer 111, and can ensure the support balance of the second substrate 105 and the second heat sink 110.
  • the positions of the fifth supporting members 111a in different fifth bonding layers 111 may be the same or different.
  • the present application does not limit the position of the fifth supporting member 111a in any one of the fifth bonding layers 111.
  • the position of the fifth support 111a in the fifth bonding layer 111 is free, so that the fifth support 111a of the required size can be implanted at the required position.
  • the fifth supporting member 111a may be fixedly arranged. Further, since the fifth supporting member 111a has a small influence on the joining of the fifth bonding layer 111, the fifth supporting member 111a can be arranged in a variety of positions, which is convenient and quick to operate and has high production efficiency.
  • At least one fifth supporting member 111a is fixedly disposed on a surface of the second heat dissipation member 110 close to the second substrate 105.
  • At least one fifth support 111a is fixedly disposed on the second conductive surface of the second substrate 105.
  • At least one fifth supporting member 111a may be fixedly disposed on a side of the second heat dissipation member 110 close to the second substrate 105 and the second conductive surface of the second substrate 105, and the second heat dissipation member 110 is close to the second conductive surface.
  • the fifth support 111 a on one surface of the substrate 105 and the fifth support 111 a on the second conductive surface of the second substrate 105 are alternately arranged.
  • the fixing method of the fifth support 111a is not limited in this application.
  • the fifth support 111a is fixedly arranged by any one of the following methods: ultrasonic, sintering, electroplating or brazing.
  • the height of at least one fifth supporting member 111a is the same as the thickness of the fifth bonding layer 111, and the melting point of the at least one fifth supporting member 111a is higher than the highest temperature at which the fifth bonding layer 111 is formed.
  • the thickness of the fifth bonding layer 111 can be set according to actual conditions, which is not limited in this application.
  • the height of the fifth support 111a can be set according to the thickness of the corresponding fifth bonding layer 111, and the specific value of the height is not limited.
  • the heights of the fifth supporting members 111a in different fifth bonding layers 111 may be the same or different.
  • the at least one fifth supporting member 111a in the process of forming the fifth bonding layer 111, the at least one fifth supporting member 111a will not be completely dissolved in the fifth bonding material 111b in the fifth bonding layer 111, so that the at least one fifth supporting member 111a is The thickness remains the same as the thickness of the fifth bonding layer 111 so that the fifth bonding layer 111 having the height of the at least one fifth supporting member 111a is formed by the at least one fifth supporting member 111a.
  • the at least one fifth support 111a will not move with the movement of the fifth bonding material 111b, so that the at least one fifth support 111a is on the fifth bonding layer 111
  • the distribution is uniform, and based on the supporting effect of the at least one fifth support 111a, the fifth bonding layer 111 can withstand compression without being deformed, so that even if the at least one fifth support 111a is remelted, it will not cause
  • the fifth bonding material 111b in the fifth bonding layer 111 overflows, ensuring the good quality of the fifth bonding layer 111, thereby ensuring that the surface of the fifth bonding layer 111 is flat and the thickness is uniform, which satisfies the requirements for the fifth bonding layer 111.
  • the fifth bonding material 111b in the fifth bonding layer 111 is no longer restricted by types, which provides multiple possibilities for the production of the fifth bonding layer 111, which is beneficial to reduce the cost of the fifth bonding layer 111.
  • the second substrate 105 and the second heat sink 110 achieve a good bonding effect through the fifth bonding layer 111, which improves the reliability and cooling capacity of the package structure 100 , It also reduces the bonding cost, which is conducive to the high density and high integration of the package structure 100.
  • the package structure 100 of the present application may be bonded to the first heat sink 108 on the second conductive surface of the first substrate 101, or may be bonded to the second heat sink 110 on the second conductive surface of the second substrate 105. It is also possible to join the first heat sink 108 on the second conductive surface of the first substrate 101 and join the second heat sink 110 on the second conductive surface of the second substrate 105 at the same time, which is not limited in this application.
  • a package structure 100 as shown in FIGS. 2 to 13 may be separately provided with the first heat sink 108 and/or the second heat sink 110.
  • the specific setting process is as shown in the embodiment shown in FIGS. 14 and 15 Describe the content.
  • a plurality of package structures 100 as shown in FIGS. 2 to 13 can be provided with a heat sink to save costs, that is, a heat sink is provided on one side of the multiple package structures 100 or a heat sink is provided on both sides of the multiple package structures 100 Pieces.
  • the package structure 100 shown in FIGS. 2 to 13 takes the direct current (DC) to alternating current (AC) conversion module 100' shown in FIG. 16 as an example. Since the DCAC conversion module 100' usually provides three-phase alternating current to the powered equipment, three DCAC conversion modules are often used in actual use. Based on this, in order to further improve the heat dissipation effect of the package structure 100, therefore, as shown in FIG. 17, the first heat sink 108 may be arranged on one side of the three DCAC conversion modules 100', and the second heat sink 110 may be arranged on the three The other side of the DCAC conversion module 100' forms a complete package structure 100.
  • DC direct current
  • AC alternating current
  • FIG. 18 is a schematic structural diagram of an electric vehicle provided by an embodiment of the application.
  • the electric vehicle 1 provided by the present application may include: a power supply battery, a motor control unit (MCU) 12, and Q motors 13 (in FIG. 18, one motor 13 is used for illustration), and Q is positive Integer.
  • MCU motor control unit
  • Q is positive Integer.
  • the motor control unit MCU 12 may include 3R package structures 100 as shown in FIG. 2 to FIG. 17 (three package structures 100 are illustrated in FIG. 18), and R is a positive integer.
  • the power supply battery can provide the first power to each package structure 100, and each motor 13 is correspondingly connected to at least three package structures 100 (in FIG. 18, one motor 13 is electrically connected to three package structures 100 for illustration).
  • the motor control unit MCU 12 can control the package structure 100 to convert the first electrical energy into the second electrical energy required by the motor 13 corresponding to the package structure 100 , And control the packaging structure 100 to transmit the second electric energy to the motor 13 correspondingly connected to the packaging structure 100, so that the correspondingly connected motor 13 can provide driving to the electric vehicle 1.
  • the electric vehicle 1 since the electric vehicle 1 usually uses an AC motor 13, in this application, the first electrical energy is usually direct current, and the second electrical energy is usually alternating current. Therefore, the general alternating current includes at least three-phase power. Therefore, each motor 13 at least The three packaging structures 100 are electrically connected. Among them, this application does not limit the specific sizes of the first electrical energy and the second electrical energy. In addition, the specific structure of the motor control unit MCU 12 is not described in this application. The motor control unit MCU 12 may also include other parts such as a switch control module.
  • each motor may also be electrically connected to at least one package structure 100, which is not limited in this application.
  • the electric vehicle 1 provided by the present application includes a packaging structure 100, which can implement the technical solutions of the above-mentioned embodiment of the packaging structure 100.
  • a packaging structure 100 which can implement the technical solutions of the above-mentioned embodiment of the packaging structure 100.
  • FIGS. 2 to 17, here No longer please refer to the technical solutions of the embodiments shown in FIGS. 2 to 17, here No longer.
  • this application also provides an electronic device.
  • the electronic device provided in the present application may include: at least one joined structure.
  • the number of joined structures may be one or more, which is not limited in this application.
  • the electronic device includes multiple joined structures, the multiple joined structures can be arranged separately or stacked, which is not limited in this application.
  • the joined structure may include: a joined part and at least one support member with a micron size.
  • at least one supporting member is provided on at least one surface to be joined of the joined member.
  • the size of the support in each dimension is all micrometers. Since the size of the support in each dimension is all micrometers, the size of the support is small compared with the volume of the bonding layer of several millimeters in size.
  • the support member has little influence on the process of the bonding layer during bonding, and it will not prevent the bubbles formed on the bonding layer from escaping from the bonding material, avoiding excessively high voids in the bonding layer, thereby affecting the bonding layer.
  • the joining effect is small, and the joining effect of the joined part is avoided due to the excessively large size of the at least one supporting part, so that the joined part can be reliably joined with other components.
  • the joined part may include one surface to be joined or multiple surfaces to be joined, and the specific number can be set according to the actual joining situation.
  • a support can be provided on the surface to be joined.
  • the height of the support is the same as the thickness of the joining layer, and the joining layer is formed by the support and the joining material.
  • the melting point of the part is higher than the maximum temperature at which the bonding layer is formed.
  • a plurality of support members may be arranged on the surface to be joined, and the height of each support member is kept the same as the thickness of the joining layer, and the joining layer is formed by each support member and the joining material , And the melting point of each support is higher than the highest temperature for forming the bonding layer.
  • the melting point of each supporting member may be the same or different, as long as the lowest melting point of each supporting member is higher than the highest temperature for forming the bonding layer.
  • each face to be joined can be provided with a support, and the thickness of the support on any one of the faces to be joined is the same as the height of the joining layer, and the joining layer is supported by the joining layer.
  • the member is formed with a bonding material, and the melting point of the support member is higher than the highest temperature at which the bonding layer is formed.
  • each support member can be provided on each surface to be joined, and the thickness of each support member on the same surface to be joined is the same as the height of the joining layer.
  • the layer is formed by each support and the joining material on the surface to be joined, and the melting point of each support is higher than the highest temperature at which the joining layer is formed.
  • the melting point of each support can be the same or different, as long as each support is satisfied It is sufficient that the lowest melting point of the middle support is higher than the highest temperature at which the bonding layer is formed.
  • the bonding material may include: a solder sheet or a solder paste.
  • the bonding material may include: powdery material or paste material.
  • the bonding material in the solder layer may include a solder sheet or a solder paste.
  • the bonding material may include: powdery material or paste material.
  • the shapes of the support members in different bonding layers may be the same or different.
  • the shapes of the multiple support members in the same bonding layer may be the same or different. Among them, this application does not limit the shape of the support.
  • the shape of the support includes at least one of a spherical shape, a rectangular parallelepiped shape, an ellipsoid shape, a wedge shape, or a silkworm shape.
  • the materials of the support members in different bonding layers may be the same or different. And/or, the materials of the multiple support members in the same bonding layer may be the same or different. Among them, this application does not limit the material of the support.
  • the supporting member is any one of a single metal material, an alloy material, a composite material, or a non-conductive material.
  • the single metal material may include aluminum Al, gold Au, copper Cu, or nickel Ni.
  • the alloy material may include at least two of aluminum Al, gold Au, copper Cu, or nickel Ni.
  • the support can be any one of a covering material, a coating material, a strip material, and a wire material. For example, metal coating or dissimilar metal coating. As a result, the manufacturing cost of the electronic device is reduced.
  • the heights of the support members in different bonding layers may be the same or different.
  • the height of the support member can be set according to the thickness of the corresponding bonding layer, and the specific value of the height is not limited.
  • the number of support members in different bonding layers may be the same or different. Among them, this application does not limit the number of supports. In addition, the number of support members in any one of the bonding layers is not limited. Thus, the number of supports in the bonding layer can be adjusted. In general, the number of support members can be greater than or equal to 3, which is beneficial to further improve the bonding effect of the bonding layer, and can ensure the support balance of the bonded member.
  • the positions of the support members in different bonding layers may be the same or different. Among them, this application does not limit the position of the support. Moreover, the position of the support in any one of the bonding layers is not limited. Therefore, the position of the support member in the bonding layer is free, so that the support member of the required size can be implanted at the required position.
  • the present application does not limit the manner in which the support member is fixed on the surface to be joined of the joined member.
  • the supporting member is fixedly arranged by any one of the following methods: ultrasonic wave, sintering, electroplating or brazing.
  • the support in order to prevent the support from being melted by the joining material during joining and the solder moves outside the joining layer, the support can be fixedly arranged. Further, since the supporting member has less influence on the joining of the bonding layer, the supporting member can be arranged in a variety of positions, and the operation is convenient and quick, and the production efficiency is high. Among them, this application does not limit the specific type of the joint to be treated.
  • the type of the joined part includes: at least one of a chip, an interconnection column, an insulating substrate, a resistor, a capacitor, an inductor, a sensor, a terminal, or a heat sink.
  • the support of micron size is provided on the joining surface of the joined part, the height of the support and the joining process
  • the thickness of the layer is the same and the melting point of the support is higher than the highest temperature at which the bonding layer is formed. Therefore, the support will not be completely dissolved in the bonding material in the bonding layer, so that the thickness of the support remains the same as the thickness of the bonding layer, so that The supporting member forms a bonding layer having the same height as the supporting member.
  • the support will not move with the movement of the bonding material, so that the support is evenly distributed in the bonding layer, and based on the support of the support, the bonding layer can withstand It can be squeezed without being deformed, so that even if the supporting member remelts, it will not cause the bonding material in the bonding layer to overflow, ensuring the good quality and bonding strength of the bonding layer, and avoiding insufficient bonding material under the bonded part.
  • the bonding material in the bonding layer is no longer restricted by types, which provides multiple possibilities for the production of the bonding layer, which is beneficial to reduce the production cost of the bonding layer.
  • the reliability of the electronic device is improved, and the manufacturing cost of the electronic device is reduced.
  • the electronic device may include: a 3D three-dimensional package module, such as a semiconductor power module, a laminated module of a printed circuit board PCB, and the like.
  • a 3D three-dimensional package module such as a semiconductor power module, a laminated module of a printed circuit board PCB, and the like.
  • the electronic device provided by the present application through at least one joined structure, includes: a joined part and at least one support member with a micron size, and the at least one support part is provided on at least one surface to be joined of the joined part.
  • the height of the support is the same as the thickness of the bonding layer, the support and the bonding material form a bonding layer, and the melting point of the support is higher than the highest temperature at which the bonding layer is formed. Make the surface of the bonding layer flat and uniform in thickness.
  • the height of the supporting parts is the same as the thickness of the joining layer and the melting point of the supporting parts is higher than that of the formed parts.
  • the maximum temperature of the bonding layer therefore, the support will not completely dissolve in the bonding material in the bonding layer, so that the thickness of the support remains the same as the thickness of the bonding layer, so that the support has the same height as the support. Bonding layer.
  • the support will not move with the movement of the bonding material, so that the support is evenly distributed in the bonding layer, and based on the support of the support, the bonding layer can withstand It can be squeezed without being deformed, so that even if the supporting member remelts, it will not cause the bonding material in the bonding layer to overflow, ensuring the good quality and bonding strength of the bonding layer, and avoiding insufficient bonding material under the bonded part.
  • the bonding material in the bonding layer is no longer restricted by types, which provides multiple possibilities for the production of the bonding layer, which is beneficial to reduce the production cost of the bonding layer.
  • the reliability of the electronic device is improved, and the manufacturing cost of the electronic device is reduced.

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Abstract

一种封装结构、电动车辆和电子装置，该封装结构（100）包括：第一接合层（102）位于第一基板（101）的第一导电面和电子元件（103）的第一接合面之间，用于实现电子元件（103）与第一基板（101）的接合；第一接合层（102）包括：第一接合材料（102b）和至少一个第一支撑件（102a），至少一个第一支撑件（102a）的高度与第一接合层（102）的厚度相同，且至少一个第一支撑件（102a）的熔点高于形成第一接合层（102）的最高温度，以使第一接合层（102）的表面平整且厚度均匀；第二接合层（104）位于电子元件（103）的第二接合面和第二基板（105）的第一导电面之间，用于实现电子元件（103）与第二基板（105）的接合，电子元件（103）的第一接合面与电子元件（103）的第二接合面相对，从而实现了第一接合层（102）的良好接合，提高了封装结构（100）的可靠性，降低了封装结构（100）的制作成本。

Description

封装结构、电动车辆和电子装置 技术领域
本申请涉及半导体技术领域，尤其涉及一种封装结构、电动车辆和电子装置。
背景技术
随着科技的不断发展，电子装置向着高集成和高密度的方向发展。目前，常常采用焊接和/或烧结等方式来制作电子装置。
以焊接方式为例，在电子装置的制作过程中，焊接层需要表面平整，且应该不易受到其他干扰因素的影响而导致形状弯曲，使得焊接层的平行度可以满足工艺要求。同时，焊接层的厚度需要满足制作要求，该厚度不能过薄，避免影响电子装置的可靠性而缩短电子装置的使用寿命，且该厚度也不能过厚，避免电子装置的热阻增大而导致电子装置的散热效果不佳。
并且，在电子装置的制作过程中需要多次回流，因此，焊料可选择的种类有限，且焊料容易出现重新熔融的风险，导致焊接层的质量劣化，引起电子装置电气短路以及电子装置失效的现象。
因此，如何控制焊接层和/或烧结层的厚度和翘曲度来确定电子装置的可靠性是现亟需解决的问题。
发明内容
本申请提供一种封装结构、电动车辆和电子装置，以提高封装结构、电动车辆和电子装置的可靠性，降低封装结构、电动车辆和电子装置的制作成本。
第一方面，本申请提供一种封装结构，包括：第一基板、第一接合层、电子元件、第二接合层以及第二基板。第一接合层位于第一基板的第一导电面和电子元件的第一接合面之间，第一接合层用于实现电子元件与第一基板的接合。第一接合层包括：第一接合材料和至少一个第一支撑件，至少一个第一支撑件的高度与第一接合层的厚度相同，且至少一个第一支撑件的熔点高于形成第一接合层的最高温度，以使第一接合层的表面平整且厚度均匀。第二接合层位于电子元件的第二接合面和第二基板的第一导电面之间，第二接合层用于实现电子元件与第二基板的接合，电子元件的第一接合面与电子元件的第二接合面相对。
通过第一方面提供的封装结构，在形成第一接合层的过程中，至少一个第一支撑件不会完全溶解在第一接合材料中，使得至少一个第一支撑件的厚度仍与第一接合层的厚度保持相同，以便通过至少一个第一支撑件形成具有至少一个第一支撑件的高度的第一接合层。并且，在封装结构需要多次回流的情况下，至少一个第一支撑件不会随着第一接合材料的移动而发生移动，使得至少一个第一支撑件在第一接合层中分布 均匀，且基于至少一个第一支撑件的支撑作用，使得第一接合层能够经受得住挤压而不变形，也使得即使至少一个第一支撑件出现重融也不会导致第一接合材料发生溢出，确保了第一接合层良好的质量和接合强度，避免了电子元件下的第一接合材料不足而导致电子元件的电气短路或者失效等现象，从而确保了第一接合层的表面平整且厚度均匀，满足了对第一接合层的厚度和翘曲度的工艺要求。同时，还使得第一接合材料不再受到种类的限制，为第一接合层的制作提供了多种可能性，有利于降低第一接合层的成本。由此，提高了封装结构的可靠性，降低了封装结构的制作成本，提升了封装结构的竞争力。
在一种可能的设计中，第二接合层包括：第二接合材料和至少一个第二支撑件，至少一个第二支撑件的高度与第二接合层的厚度相同，且至少一个第二支撑件的熔点高于形成第二接合层的最高温度，以使第二接合层的表面平整且厚度均匀。
在形成第二接合层的过程中，至少一个第二支撑件不会完全溶解在第二接合层中的第二接合材料中，使得至少一个第二支撑件的厚度仍与第二接合层的厚度保持相同，以便通过至少一个第二支撑件形成具有至少一个第二支撑件的高度的第二接合层。并且，在封装结构需要多次回流的情况下，至少一个第二支撑件不会随着第二接合材料的移动而发生移动，使得至少一个第二支撑件在第二接合层中分布均匀，且基于至少一个第二支撑件的支撑作用，使得第二接合层能够经受得住挤压而不变形，也使得即使至少一个第一支撑件出现重融也不会导致第二接合层中的第二接合材料发生溢出，确保了第二接合层良好的质量和接合强度，避免了第二基板下的第二接合材料不足而导致电子元件的电气短路或者失效等现象，从而确保了第二接合层的表面平整且厚度均匀，满足了对第二接合层的厚度和翘曲度的工艺要求。同时，还使得第二接合层中的第二接合材料不再受到种类的限制，为第二接合层的制作提供了多种可能性，有利于降低第二接合层的成本。
由此，基于第二接合层的表面平整且厚度均匀，第二基板的第一导电面和电子元件的第二接合面通过第二接合层实现了良好的接合效果以及电气连接，还降低了接合成本。
综上，基于上述第一接合层和第二接合层的设置，实现了第一基板的第一导电面、第一接合层、电子元件、第二接合层和第二基板的第一导电面的牢固接合和可靠连接，提高了封装结构的可靠性，降低了封装结构的接合成本，提升了封装结构的竞争力。
在一种可能的设计中，为了避免在接合时第二支撑件被第二接合材料熔融而焊料移动到第二接合层之外，因此，第二支撑件可以固定设置。可选地，至少一个第二支撑件固定设置在电子元件的第二接合面或者第二基板的第一导电面上。从而，使得操作方便快捷，生成效率高，且第二支撑件在第二接合层中的位置自由，以便在需要的位置处植入所需尺寸的第二支撑件即可。
在一种可能的设计中，第二支撑件为微米级别尺寸。由于第二支撑体在各个维度上的尺寸均为微米级别，因此，与数毫米级尺寸的第二接合层的体积相比，第二支撑件的尺寸很小，使得第二支撑件在接合时对第二接合层的工艺影响很小，也不会妨碍在第二接合层上所形成的气泡从第二接合材料中逸出，避免了第二接合层的空洞率过高，从而不会对第二接合层的可靠性造成不良影响。
在一种可能的设计中，封装结构还包括：塑封材料；第一基板、第一接合层、电子元件的部分、第二接合层以及第二基板均设置在塑封材料中。从而，通过塑封材料来保护封装结构中的各个部品以及各个部品之间的电气连接，有利于封装结构的使用。
在一种可能的设计中，为了避免在接合时第一支撑件被第一接合材料熔融而焊料移动到第一接合层之外，因此，第一支撑件可以固定设置。可选地，至少一个第一支撑件固定设置在电子元件的第一接合面或者第一基板的第一导电面上。从而，使得操作方便快捷，生成效率高，且第一支撑件在第一接合层中的位置自由，以便在需要的位置处植入所需尺寸的第一支撑件即可。
在一种可能的设计中，第一支撑件为微米级尺寸。由于第一支撑体在各个维度上的尺寸均为微米级，因此，与数毫米级尺寸的第一接合层的体积相比，第一支撑件的尺寸很小，使得第一支撑件在接合时对第一接合层的工艺影响很小，也不会妨碍在第一接合层上所形成的气泡从第一接合材料中逸出，避免了第一接合层的空洞率过高，从而不会对第一接合层的可靠性和导热性造成不良影响。
在一种可能的设计中，若包括多个不连接的第一接合层和多个不连接的第二接合层，则电子元件包括：芯片、第三接合层、互联柱、信号端子和功率端子。芯片位于除与信号端子对应的第一接合层和功率端子对应的第一接合层之外的第一接合层和第三接合层之间，互联柱位于与芯片对应的第三接合层和对应的第二接合层之间。信号端子从封装结构的内部向封装结构的外部延伸设置，位于封装结构的内部的信号端子的一端位于除与芯片对应的第一接合层和功率端子对应的第一接合层之外的第一接合层上，第一接合层中包括有第一接合材料和固定设置在第一基板的第一导电面上的第一支撑件，信号端子与芯片电连接，芯片对应的第一接合层和信号端子对应的第一接合层各自对应于第一基板的第一导电面中的不同导电区域。功率端子从封装结构的内部向封装结构的外部延伸设置，位于封装结构的内部的功率端子的一端位于除与芯片对应的第一接合层和信号端子对应的第一接合层之外的第一接合层上，第一接合层中包括有第一接合材料和固定设置在第一基板的第一导电面上的第一支撑件，芯片对应的第一接合层和功率端子对应的第一接合层各自对应于第一基板的第一导电面中的同一导电区域；和/或，功率端子位于除互联柱对应的第二接合层之外的第二接合层上，第二接合层中包括有第二接合材料和固定设置在第二基板的第一导电面上的第二支撑件，互联柱对应的第二接合层和功率端子对应的第二接合层各自对应于第二基板的第一导电面中的同一导电区域。第三接合层包括：第三接合材料和至少一个第三支撑件，至少一个第三支撑件的高度与第三接合层的厚度相同，且至少一个第三支撑件的熔点高于形成第三接合层的最高温度，以使第三接合层的表面平整且厚度均匀。
在形成第三接合层的过程中，至少一个第三支撑件不会完全溶解在第三接合层中的第三接合材料中，使得至少一个第三支撑件的厚度仍与第三接合层的厚度保持相同，以便通过至少一个第三支撑件形成具有至少一个第三支撑件的高度的第三接合层。并且，在封装结构需要多次回流的情况下，至少一个第三支撑件不会随着第三接合材料的移动而发生移动，使得至少一个第三支撑在第三接合层中分布均匀，且基于至少一个第三支撑件的支撑作用，使得第三接合层能够经受得住挤压而不变形，也使得即使至少一个第三支撑件出现重融也不会导致第三接合层中的第三接合材料发生溢出，确 保了第三接合层良好的质量和接合强度，避免了互联柱下的第三接合材料不足而导致芯片的电气短路或者失效等现象，从而确保了第三接合层的表面平整且厚度均匀，满足了对第三接合层的厚度和翘曲度的工艺要求。同时，还使得第三接合层中的第三接合材料不再受到种类的限制，为第三接合层的制作提供了多种可能性，有利于降低第三接合层的成本。
由此，基于第三接合层的表面平整且厚度均匀，芯片和互联柱通过第三接合层实现了良好的接合效果以及电气连接，还降低了接合成本。
综上，基于上述第一接合层、第二接合层和第三接合层的设置，实现了第一基板的第一导电面、第一接合层、芯片、第三接合层、互联柱、第二接合层和第二基板的第一导电面的牢固接合和可靠连接，且还实现了信号端子与第一基板的第一导电面的牢固接合和可靠连接，以及功率端子与第一基板的第一导电面和/或与第二基板的第一导电面的牢固接合和可靠连接，不仅提高了封装结构的可靠性，降低了封装结构的接合成本，还使得封装结构可以实现完整的功率转换过程。
在一种可能的设计中，为了避免在接合时第三支撑件被第三接合材料熔融而焊料移动到第三接合层之外，因此，第三支撑件可以固定设置。可选地，至少一个第三支撑件固定设置在芯片上靠近互联柱的一面或者互联柱上靠近芯片的一面上。从而，使得操作方便快捷，生成效率高，且第三支撑件在第三接合层中的位置自由，以便在需要的位置处植入所需尺寸的第三支撑件即可。
在一种可能的设计中，第三支撑件为微米级尺寸。由于第三支撑体在各个维度上的尺寸均为微米级，因此，与数毫米级尺寸的第三接合层的体积相比，第三支撑件的尺寸很小，使得第三支撑件在接合时对第三接合层的工艺影响很小，也不会妨碍在第三接合层上所形成的气泡从第三接合材料中逸出，避免了第三接合层的空洞率过高，从而不会对第三接合层的可靠性造成不良影响。
在一种可能的设计中，若包括多个不连接的第一接合层和多个不连接的第二接合层，则电子元件包括：芯片、信号端子和功率端子。芯片位于除与信号端子对应的第一接合层和功率端子对应的第一接合层之外的第一接合层与对应的第二接合层之间。信号端子从封装结构的内部向封装结构的外部延伸设置，位于封装结构的内部的信号端子的一端位于除与芯片对应的第一接合层和功率端子对应的第一接合层之外的第一接合层上，第一接合层中包括有第一接合材料和固定设置在第一基板的第一导电面上的第一支撑件，信号端子与芯片电连接，芯片对应的第一接合层和信号端子对应的第一接合层各自对应于第一基板的第一导电面中的不同导电区域。功率端子从封装结构的内部向封装结构的外部延伸设置，位于封装结构的内部的功率端子的一端位于除与芯片对应的第一接合层和信号端子对应的第一接合层之外的第一接合层上，第一接合层中包括有第一接合材料和固定设置在第一基板的第一导电面上的第一支撑件，芯片对应的第一接合层和功率端子对应的第一接合层各自对应于第一基板的第一导电面中的同一导电区域；和/或，功率端子位于除芯片对应的第二接合层之外的第二接合层上，第二接合层中包括有第二接合材料和固定设置在第二基板的第一导电面上的第二支撑件，芯片对应的第二接合层和功率端子对应的第二接合层各自对应于第二基板的第一导电面中的同一导电区域。
综上，基于上述第一接合层、第二接合层和第三接合层的设置，实现了第一基板的第一导电面、第一接合层、芯片、第二接合层和第二基板的第一导电面的牢固接合和可靠连接，且还实现了信号端子与第一基板的第一导电面的牢固接合和可靠连接，以及功率端子与第一基板的第一导电面和/或与第二基板的第一导电面的牢固接合和可靠连接，不仅提高了封装结构的可靠性，降低了封装结构的接合成本，还使得封装结构可以实现完整的功率转换过程。
在一种可能的设计中，电子元件还包括：传感器。传感器的两端分别位于除与芯片对应的第一接合层、信号端子对应的第一接合层和功率端子对应的第一接合层之外的第一接合层上，第一接合层中包括有第一接合材料和固定设置在第一基板的第一导电面上的第一支撑件，芯片对应的第一接合层和传感器对应的两个第一接合层各自对应于第一基板的第一导电面中的不同导电区域；和/或，传感器的一端位于除与芯片对应的第一接合层、信号端子对应的第一接合层和功率端子对应的第一接合层之外的第一接合层上，传感器的另一端通过传输导线从封装结构的内部向封装结构的外部延伸设置，芯片对应的第一接合层和传感器对应的第一接合层各自对应于第一基板的第一导电面中的不同导电区域。
在一种可能的设计中，封装结构还包括：第一散热件和第四接合层。第四接合层位于第一基板的第二导电面与第一散热件之间，第一基板的第二导电面暴露在封装结构的外部，第四接合层用于实现第一基板与第一散热件之间的接合。第四接合层包括：第四接合材料和至少一个第四支撑件，至少一个第四支撑件的高度与第四接合层的厚度相同，且至少一个第四支撑件的熔点高于形成第四接合层的最高温度，以使第四接合层的表面平整且厚度均匀。
在形成第四接合层的过程中，至少一个第四支撑件不会完全溶解在第四接合层中的第四接合材料中，使得至少一个第四支撑件的厚度仍与第四接合层的厚度保持相同，以便通过至少一个第四支撑件形成具有至少一个第四支撑件的高度的第四接合层。并且，在封装结构需要多次回流的情况下，至少一个第四支撑件不会随着第四接合材料的移动而发生移动，使得至少一个第四支撑件在第四接合层中分布均匀，且基于至少一个第四支撑件的支撑作用，使得第四接合层能够经受得住挤压而不变形，也使得即使至少一个第四支撑件出现重融也不会导致第四接合层中的第四接合材料发生溢出，确保了第四接合层良好的质量和接合强度，从而确保了第四接合层的表面平整且厚度均匀，满足了对第四接合层的厚度和翘曲度的工艺要求。同时，还使得第四接合层中的第四接合材料不再受到种类的限制，为第四接合层的制作提供了多种可能性，有利于降低第四接合层的成本。
由此，基于第四接合层的表面平整且厚度均匀，第一基板和第一散热件通过第四接合层实现了良好的接合效果，提高了封装结构的可靠性和冷却能力，还降低了接合成本，有利于封装结构的高密度和高集成。
在一种可能的设计中，为了避免在接合时第四支撑件被第四接合材料熔融而焊料移动到第四接合层之外，因此，第四支撑件可以固定设置。可选地，至少一个第四支撑件固定设置在第一基板的第二导电面或者第一散热件上靠近第一基板的一面上。从而，使得操作方便快捷，生成效率高，且第四支撑件在第四接合层中的位置自由，以 便在需要的位置处植入所需尺寸的第四支撑件即可。
在一种可能的设计中，第四支撑件为微米级尺寸。由于第四支撑体在各个维度上的尺寸均为微米级，因此，与数毫米级尺寸的第四接合层的体积相比，第四支撑件的尺寸很小，使得第四支撑件在接合时对第四接合层的工艺影响很小，也不会妨碍在第四接合层上所形成的气泡从第四接合材料中逸出，避免了第四接合层的空洞率过高，从而不会对第四接合层的可靠性造成不良影响。
在一种可能的设计中，封装结构还包括：第二散热件和第五接合层。第五接合层位于第二基板的第二导电面与第二散热件之间，第二基板的第二导电面暴露在封装结构的外部，第五接合层用于实现第二基板与第二散热件之间的接合。第五接合层包括：第五接合材料和至少一个第五支撑件，至少一个第五支撑件的高度与第五接合层的厚度相同，且至少一个第五支撑件的熔点高于形成第五接合层的最高温度，以使第五接合层的表面平整且厚度均匀。
在一种可能的设计中，为了避免在接合时第五支撑件被第五接合材料熔融而焊料移动到第五接合层之外，因此，第五支撑件可以固定设置。可选地，至少一个第五支撑件固定设置在第二基板的第二导电面或者第二散热件上靠近第二基板的一面上。从而，使得操作方便快捷，生成效率高，且第五支撑件在第五接合层中的位置自由，以便在需要的位置处植入所需尺寸的第五支撑件即可。
在一种可能的设计中，第五支撑件为微米级尺寸。由于第五支撑体在各个维度上的尺寸均为微米级，因此，与数毫米级尺寸的第五接合层的体积相比，第五支撑件的尺寸很小，使得第五支撑件在接合时对第五接合层的工艺影响很小，也不会妨碍在第五接合层上所形成的气泡从第五接合材料中逸出，避免了第五接合层的空洞率过高，从而不会对第五接合层的可靠性造成不良影响。
在一种可能的设计中，支撑件可以设置为微米级尺寸，对接合层的接合影响较小，避免由于支撑件的尺寸过大而降低接合层的接合效果，有利于提高接合层的可靠性。由于支撑体在各个维度上的尺寸均为微米级，因此，与数毫米级尺寸的接合层的体积相比，支撑件的尺寸很小，使得支撑件在接合时对接合层的工艺影响很小，也不会妨碍在接合层上所形成的气泡从接合材料中逸出，避免了接合层的空洞率过高，从而不会对接合层的可靠性造成不良影响。在一种可能的设计中，不同的接合层中的支撑件的形状相同或者不同；和/或，同一接合层中的多个支撑件的形状相同或者不同。
在一种可能的设计中，支撑件的形状包括：球状、长方体状、椭球状、楔形状或者蚕状中的至少一个。
在一种可能的设计中，不同的接合层中的支撑件的材料相同或者不同；和/或，同一接合层中的多个支撑件的材料相同或者不同。
在一种可能的设计中，支撑件为单金属材料、合金材料、复合材料或者不导电材料中的任意一种。从而使得封装结构的制作成本降低。
在一种可能的设计中，支撑件为包覆材料、涂层材料、带材材料、线材材料中的任意一种。从而为接合层提供了多种可能性。
在一种可能的设计中，不同的接合层中的支撑件的高度相同或者不同。
在一种可能的设计中，不同的接合层中的支撑件的数量相同或者不同。从而使得 接合层中的支撑件的数量可调。一般情况下，支撑件的数量可以大于等于3个，有利于进一步提升接合层的接合效果，且可以确保被接合件的支撑平衡。
在一种可能的设计中，支撑件通过如下任意一种方式进行固定设置：超音波、烧结、电镀或者钎焊。
在一种可能的设计中，在接合层的类型包括焊接层的情况下，接合材料包括：焊片或者焊膏；和/或，在接合层的类型为烧结层的情况下，接合材料包括：粉状物料或者膏状物料。
第二方面，本申请提供一种电动车辆，包括：供电电池、电机控制单元MCU以及Q个电机，Q为正整数。电机控制单元MCU包括3R个第一方面及第一方面任一种可能的设计中的封装结构，R为正整数，供电电池向每个封装结构均提供第一电能，每个电机对应连接至少三个封装结构。针对3R个封装结构中的任意一个封装结构，电机控制单元MCU，用于控制封装结构将第一电能转换为与封装结构对应连接的电机所需的第二电能，并控制封装结构将第二电能传输至与封装结构对应连接的电机。
上述第二方面以及上述第二方面的各可能的设计中所提供的电动车辆，其有益效果可以参见上述第一方面和第一方面的各可能的实施方式所带来的有益效果，在此不再赘述。
第三方面，本申请提供一种电子装置，包括：至少一个被接合结构，至少一个被接合结构包括：被接合件和微米级尺寸的至少一个支撑件。至少一个支撑件设置在被接合件的至少一个待接合面上。针对被接合件的任意一个待接合面上的支撑件，支撑件的高度与接合层的厚度相同，支撑件与接合材料形成接合层，且支撑件的熔点高于形成接合层的最高温度，以使接合层的表面平整且厚度均匀。
在一种可能的设计中，电子装置包括：3D立体封装模块。
通过第三方面提供的电子装置，在被接合件实现接合的过程中，由于在该被接合件的待接合面上设置有微米级尺寸的支撑件，支撑件的高度与接合层的厚度相同以及支撑件的熔点高于形成接合层的最高温度，因此，支撑件不会完全溶解在接合层中的接合材料中，使得支撑件的厚度仍与接合层的厚度保持相同，以便通过支撑件形成具有与支撑件的高度相同的接合层。并且，在电子装置需要多次回流的情况下，支撑件不会随着接合材料的移动而发生移动，使得支撑件在接合层中分布均匀，且基于支撑件的支撑作用，使得接合层能够经受得住挤压而不变形，也使得即使支撑件出现重融也不会导致接合层中的接合材料发生溢出，确保了接合层良好的质量和接合强度，避免了被接合件下的接合材料不足而导致电子装置的电气短路或者失效等现象，从而确保了接合层的表面平整且厚度均匀，满足了对接合层的厚度和翘曲度的工艺要求。同时，还使得接合层中的接合材料不再受到种类的限制，为接合层的制作提供了多种可能性，有利于降低接合层的制作成本。由此，提高了电子装置的可靠性，且降低了电子装置的制作成本。
附图说明
图1为一种高密度半导体装置的截面示意图；
图2为本申请一实施例提供的封装结构的结构示意图；
图3为本申请一实施例提供的支撑件固定设置在电子元件上的结构示意图；
图4为本申请一实施例提供的电子元件固接合在第一基板上的X射线示意图；
图5为本申请一实施例提供的支撑件固定设置在电子元件上的流程示意图；
图6为本申请一实施例提供的支撑件固定设置在电子元件上的流程示意图；
图7为本申请一实施例提供的封装结构的制作流程示意图；
图8为本申请一实施例提供的封装结构的制作流程示意图；
图9为本申请一实施例提供的封装结构的结构示意图；
图10为本申请一实施例提供的封装结构的结构示意图；
图11为本申请一实施例提供的封装结构的结构示意图；
图12为本申请一实施例提供的封装结构中传感器的位置示意图；
图13为本申请一实施例提供的封装结构中传感器的位置示意图；
图14为本申请一实施例提供的封装结构的结构示意图；
图15为本申请一实施例提供的封装结构的结构示意图；
图16为本申请一实施例提供的封装结构的结构示意图；
图17为本申请一实施例提供的封装结构的结构示意图；
图18为本申请一实施例提供的电动车辆的结构示意图。
附图标记说明：
200—高密度半导体装置；201—第一敷铜绝缘基板；202—IGBT；203—FRD；204—互联柱a＇；205—互联柱b＇；206—信号端子a；207—第一功率端子；208—第二敷铜绝缘基板；209—第二功率端子；210—塑封料；
100—封装结构；101—第一基板；102—第一接合层：102a—第一支撑件：102b—第一接合材料：103—电子元件；104—第二接合层；104a—第二支撑件；104b—第二接合材料；105—第二基板；106—塑封材料；103a—芯片；103b—第三接合层；103c—互联柱；103d—信号端子；103e—功率端子；103ba—第三支撑件；103bb—第三接合材料；107—传感器；108—第一散热件；109—第四接合层；110—第二散热件；111—第五接合层；109a—第四支撑件；109b—第四接合材料；111a—第五支撑件；111b—第五接合材料；100＇—DCAC变换模块；
300—超音波工作头；400—超音波工作头和劈刀；500—定位板；601—治具；602—控厚环；102a＇—第一微小金属块；104a＇—第二微小金属块；
1—电动车辆；11—供电电池；12—电机控制单元MCU；13—电机。
具体实施方式
电子装置向着高集成和高密度的方向发展。常常采用焊接和/或烧结等方式来制作电子装置。以焊接方式为例，为了保证电子装置的可靠性，焊接层有厚度、平行度和翘曲度的要求，以满足如电子装置中铝线键合和各个部品的接合等工艺需求。
通常，电子装置的制作过程需要多次回流，且需要使用不同熔点的焊料。一般而言，前道回流工序所使用的焊料的熔点需要高于后道回流工序所使用的焊料的熔点，以免在后道回流工序中，将前道回流工序所使用的焊料重融而导致被接合体发生移位，使得焊接层的质量劣化，导致焊接层的接合效果不佳，容易引起电子装置电气短路或 者失效的现象，严重影响电子装置的可靠性。
下面，结合图1，以电子装置为高密度半导体装置200为例进行说明。图1中，高温焊料采用向左划线方格进行示意，中温焊料采用交叉线方格进行示意)。
首先，如图1所示，分别用四个高温焊料，将绝缘栅双极型晶体管(insulated bipolar transisitor，IGBT)202的底面焊接在第一敷铜绝缘基板201上、将快恢复二极管(简称FRD)203的底面焊接在第一敷铜绝缘基板201上、将互联柱a＇204的底面焊接在IGBT 202的顶面上，以及将互联柱b＇205的底面焊接在FRD 203的顶面上。另外，还可以用两个高温焊料分别将电阻(图1中未进行示意)的两端焊接在第一敷铜绝缘基板201上，用一个高温焊料将图1中的信号端子a206的一端焊接在第一敷铜绝缘基板201上，用一个高温焊料将图1中的第一功率端子207的一端焊接在第一敷铜绝缘基板201上。
其次，继续结合图1，分别用两个中温焊料，将第二敷铜绝缘基板208焊接在互联柱a＇204的顶面和互联柱b＇205的顶面上。并且，还可以用中温焊料将第二功率端子209的一端分别焊接在第二敷铜绝缘基板208上。
接着，继续结合图1，分别用两个低温焊料(图1中未进行示意)，将下散热件焊接在图1中的第一敷铜绝缘基板201的底面上，将上散热件焊接在图1中的第二敷铜绝缘基板208的顶面上。需要说明的是，这个步骤为可选步骤。
最后，继续结合图1，用塑封料210将上述结构实现塑封，从而完成高密度半导体装置200的制作。
基于上述描述，高密度半导体装置200的工作温度受限于上述过程中焊料的最低熔点，即图1中的中温焊料的熔点或者低温焊料的熔点。目前，对高温焊料而言，可供选择的焊料有有铅高温焊料和无铅高温焊料(如锗金Au-Ge、硅金Au-Si、锡金Au-Sn、铝锌Al-Zn、锡锑Sn-Sb、铋银Bi-Ag)等。对于中温焊料而言，可供选择的焊料有锡铜Sn-Cu和锡膏SAC305基焊料(熔点：217℃)等。对于低温焊料而言，锡铋Sn-Bi(熔点：139℃)和锡铟Sn-In(熔点：118℃)等。
然而，高密度半导体装置200的制作过程通常有无铅化需求，限制了有铅高温焊料的使用，以便满足RoHS的规定，且金基高温焊料的高价格，限制了其广泛应用。铋银Bi-Ag焊料的热导率过低(约10W/km)需要克服，铝锌Al-Zn焊料的腐蚀性和润湿性需要克服，锡锑Sn-Sb合金焊料的熔点略低(为243度)，其余焊料的熔点也较低。因此，在高密度半导体装置200的制作过程中能够采用的焊料的种类的选择余地有限。并且，多次回流也会使得焊料存在熔融的风险。
综上，由于受限于焊料可选择的种类以及焊料所存在的重融风险，因此，不仅会导致两个敷铜绝缘基板的平行度过大而引起塑封后的研磨量过大，也会导致端子的平行度差而引起高密度半导体装置200与其余电气部品之间的插接困难，还会导致芯片或者端子等被接合体的焊接层质量劣化而引起焊料溢出，进一步导致被接合体下方的焊料不足而引起高密度半导体装置200的电气短路或者失效等现象。
为了解决上述问题，本申请提供一种封装结构、电动车辆和电子装置，基于在被接合件上固定设置支撑件，通过支撑件所起到支撑作用、厚度保持作用和翘曲度维持作用，实现了表面平整且厚度均匀的接合层，使得接合层的厚度和翘曲度满足工艺要 求，还使得接合层中的接合材料不受到种类的限制，有助于降低接合层的制作成本，还使得接合层中的接合材料不会发生溢出，避免了被接合件下方的接合材料不足，使得封装结构、电动车辆和电子装置的电气连接方便且牢固，提高了封装结构、电动车辆和电子装置的可靠性，提升了封装结构、电动车辆和电子装置的竞争力。
下面，结合具体的实施例，对本申请的封装结构100的具体实现方式进行详细说明。
图2为本申请一实施例提供的封装结构的结构示意图。如图2所示，本申请提供的封装结构100可以包括：第一基板101、第一接合层102、电子元件103、第二接合层104以及第二基板105。为了便于说明，图2中采用一个第一接合层102和一个第二接合层104进行示意。
本申请中，第一接合层102位于第一基板101的第一导电面和电子元件103的第一接合面之间，第一接合层102用于实现电子元件103与第一基板101的接合。
其中，电子元件103可以包括一个元器件，也可以多个元器件。多个元器件可以均连接，或者，多个元器件可以均不连接，或者，多个元器件中部分的元器件均连接且剩余部分的元器件均不连接。
其中，第一接合层102的数量可以为一个或者多个，具体可以根据电子元件103中元器件的电气连接情况进行设置。一般情况下，一个元器件对应一个第一接合层102。另外，一个元器件也可对应多个第一接合层102，本申请对此不做限定。
本申请中，第一基板101可以包括多种实现方式。
一种可行的实现方式中，可选地，第一基板101可以包括：第一导电层和第一绝缘层。第一导电层和第一绝缘层均设置在封装结构100的内部，第一基板101的第一导电面为第一导电层。
其中，第一导电层可以采用铜Cu等导电材料，第一绝缘层可以采用玻璃、陶瓷或者环氧树脂等绝缘材料。且本申请可以采用涂覆或者蚀刻等方式将第一导电层设置在第一绝缘层的一面上。
另一种可行的实现方式中，可选地，第一基板101可以包括：第一导电层、第一绝缘层和第二导电层。第一导电层和第一绝缘层均设置在封装结构100的内部，第一基板101的第一导电面为第一导电层，第一绝缘层位于第一导电层和第二导电层之间，第一基板101的第二导电面为第二导电层，第二导电层暴露在封装结构100的外部，以提高封装结构100的散热能力。为了便于说明，图2中，第一基板101采用三个长方形框进行示意，靠近电子元件103的长方形框为第一导电层，中间的长方形框为第一绝缘层，远离电子元件103的长方形框为第二导电层。
其中，第一导电层和第二导电层可以采用铜Cu等导电材料，第一绝缘层可以采用玻璃、陶瓷或者环氧树脂等绝缘材料，且本申请可以采用涂覆或者蚀刻等方式将第一导电层设置在第一绝缘层的一面上且将第二导电层设置在第一绝缘层的另一面上。
另外，第一基板101的第一导电面可以包括一个导电区域，也可以包括多个导电区域，且多个导电区域不连接。一般情况下，任意一个导电区域对应一个元器件，或者，任意一个导电区域对应多个连接的元器件。
本申请中，第一接合层102可以包括：第一接合材料102b和至少一个第一支撑件 102a。为了便于说明，图2中一个第一接合层102采用两个第一支撑件102a进行示意。
其中，第一接合材料102b的具体类型可以根据接合方式进行设置，本申请对此不做限定。可选地，在第一接合层102的类型包括焊接层的情况下，第一接合材料102b可以包括：焊片或者焊膏。在第一接合层102的类型包括烧结层的情况下，第一接合材料102b可以包括：粉状物料或者膏状物料。在第一接合层102的类型包括焊接层和烧结层的情况下，焊接层中，第一接合材料102b可以包括：焊片或者焊膏；烧结层中，第一接合材料102b可以包括：粉状物料或者膏状物料。
其中，第一支撑件102a可以设置为微米级尺寸，即第一支撑件102a在各个维度上的尺寸均为微米级，由于第一支撑体102a在各个维度上的尺寸均为微米级，因此，与数毫米级尺寸的第一接合层102的体积相比，第一支撑件102a的尺寸很小，使得第一支撑件102a在接合时对第一接合层102的工艺影响很小，也不会妨碍在第一接合层102上所形成的气泡从第一结合材料102b中逸出，避免了第一接合层102的空洞率过高，从而对第一接合层102的接合影响较小，避免由于至少一个第一支撑件102a的尺寸过大而降低第一基板101的第一导电面和电子元件103的第一接合面之间的接合效果，使得第一基板101的第一导电面和电子元件103的第一接合面之间能够可靠接合。
在一个具体的实施例中，如图3所示，电子元件103的第一接合面上固定设置有4个第一支撑件102a，每个第一支撑件102a的高度约130微米，长度约700微米，宽度约200微米。并将该电子元件103接合在第一基板101的导电面上，使得用X射线(X-ray)测得电子元件103和第一基板101接合后的空洞率，如图4所示，该空洞率满足制作工艺需求，从而第一支撑件102a的设置对电子元件103和第一基板101接合的影响较小。
可选地，不同的第一接合层102中的第一支撑件102a的形状可以相同或者不同。同一第一接合层102中的多个第一支撑件102a的形状可以相同或者不同。其中，本申请对第一支撑件102a的形状不做限定。可选地，第一支撑件102a的形状包括：球状、长方体状、椭球状、楔形状或者蚕状中的至少一个。
可选地，不同的第一接合层102中的第一支撑件102a的材料可以相同或者不同。同一第一接合层102中的多个第一支撑件102a的材料可以相同或者不同。其中，本申请对第一支撑件102a的材料不做限定。可选地，第一支撑件102a为单金属材料、合金材料、复合材料或者不导电材料中的任意一种。例如，单金属材料可以包括：铝Al、金Au、铜Cu或者镍Ni。合金材料可以包括：铝Al、金Au、铜Cu或者镍Ni中的至少两种。可选地，第一支撑件102a为包覆材料、涂层材料、带材材料、线材材料中的任意一种。例如，金属涂层或异种金属包覆。从而使得封装结构100的制作成本降低。
可选地，不同的第一接合层102中的第一支撑件102a的数量可以相同或者不同。其中，本申请对任意一个第一接合层102中的第一支撑件102a的数量不做限定。从而使得第一接合层102中的第一支撑件102a的数量可调。一般情况下，第一支撑件102a的数量可以大于等于3个，有利于进一步提升第一接合层102的接合效果，且可以确保第一基板101和电子元件103的支撑平衡。
可选地，不同的第一接合层102中的第一支撑件102a的位置可以相同或者不同。其中，本申请对任意一个第一接合层102中的第一支撑件102a的位置不做限定。从而 使得第一支撑件102a在第一接合层102中的位置自由，以便在需要的位置处植入所需尺寸的第一支撑件102a即可。
本申请中，为了避免在接合时第一支撑件102a被第一接合材料102b熔融而焊料移动到第一接合层102之外，因此，第一支撑件102a可以固定设置。进一步地，由于第一支撑件102a对第一接合层102的接合影响较小，因此，第一支撑件102a的设置位置可以包括多种，操作方便快捷，生成效率高。
可选地，至少一个第一支撑件102a可以固定设置在电子元件103的第一接合面上。
可选地，至少一个第一支撑件102a也可以固定设置在第一基板101的第一导电面上。
可选地，至少一个第一支撑件102a也可以固定设置在电子元件103的第一接合面和第一基板101的第一导电面上，且电子元件103的第一接合面上的第一支撑件102a与第一基板101的第一导电面上的第一支撑件102a交错设置。
其中，本申请对第一支撑件102a的固定方式不做限定。可选地，第一支撑件102a通过如下任意一种方式进行固定设置：超音波、烧结、电镀或者钎焊。
本申请中，至少一个第一支撑件102a的高度与第一接合层102的厚度相同，且至少一个第一支撑件102a的熔点高于形成第一接合层102的最高温度。其中，第一接合层102的厚度可以结合实际情况进行设置，本申请对此不做限定。第一支撑件102a的高度可以根据对应的第一接合层102的厚度进行设置，其高度的具体数值不做限定。可选地，不同的第一接合层102中的第一支撑件102a的高度可以相同或者不同。
基于前述设置，在形成第一接合层102的过程中，至少一个第一支撑件102a不会完全溶解在第一接合层102中的第一接合材料102b中，使得至少一个第一支撑件102a的厚度仍与第一接合层102的厚度保持相同，以便通过至少一个第一支撑件102a形成具有至少一个第一支撑件102a的高度的第一接合层102。并且，在封装结构100需要多次回流的情况下，至少一个第一支撑件102a不会随着第一接合材料102b的移动而发生移动，使得至少一个第一支撑件102a在第一接合层102中分布均匀，且基于至少一个第一支撑件102a的支撑作用，使得第一接合层102能够经受得住挤压而不变形，也使得即使至少一个第一支撑件102a出现重融也不会导致第一接合层102中的第一接合材料102b发生溢出，确保了第一接合层102良好的质量和接合强度，避免了电子元件103下的第一接合材料102b不足而导致电子元件103的电气短路或者失效等现象，从而确保了第一接合层102的表面平整且厚度均匀，满足了对第一接合层102的厚度和翘曲度的工艺要求。同时，还使得第一接合层102中的第一接合材料102b不再受到种类的限制，为第一接合层102的制作提供了多种可能性，有利于降低第一接合层102的成本。
由此，基于第一接合层102的表面平整且厚度均匀，第一基板101的第一导电面和电子元件103的第一接合面通过第一接合层102实现了良好的接合效果以及电气连接，还降低了接合成本。
本申请中，第二接合层104位于电子元件103的第二接合面和第二基板105的第一导电面之间，第二接合层104用于实现电子元件103与第二基板105的接合，且电子元件103的第一接合面与电子元件103的第二接合面相对。
其中，第二接合层104的数量可以为一个或者多个，具体可以根据电子元件103中元器件的电气连接情况进行设置。一般情况下，一个元器件对应一个第二接合层104。另外，一个元器件也可对应多个第二接合层104，本申请对此不做限定。
本申请中，第二基板105可以包括多种实现方式。
一种可行的实现方式中，可选地，第二基板105可以包括：第三导电层和第二绝缘层。第三导电层和第二绝缘层均设置在封装结构100的内部，第二基板105的第一导电面为第三导电层。
其中，第三导电层可以采用铜Cu等导电材料，第二绝缘层可以采用玻璃、陶瓷或者环氧树脂等绝缘材料。且本申请可以采用涂覆或者蚀刻等方式将第三导电层设置在第二绝缘层的一面上。
另一种可行的实现方式中，可选地，第二基板105可以包括：第三导电层、第二绝缘层和第四导电层。第三导电层和第二绝缘层均设置在封装结构100的内部，第二基板105的第一导电面为第三导电层，第二绝缘层位于第三导电层和第四导电层之间，第二基板105的第二导电面为第四导电层，第四导电层暴露在封装结构100的外部，以提高封装结构100的散热能力。为了便于说明，图2中，第二基板105采用三个长方形框进行示意，靠近电子元件103的长方形框为第三导电层，中间的长方形框为第二绝缘层，远离电子元件103的长方形框为第四导电层。
其中，第三导电层和第四导电层可以采用铜Cu等导电材料，第二绝缘层可以采用玻璃、陶瓷或者环氧树脂等绝缘材料，且本申请可以采用涂覆或者蚀刻等方式将第三导电层设置在第二绝缘层的一面上且将第四导电层设置在第二绝缘层的另一面上。
另外，第二基板105的第一导电面可以包括一个导电区域，也可以包括多个导电区域，且多个导电区域不连接。一般情况下，任意一个导电区域对应一个元器件，或者，任意一个导电区域对应多个连接的元器件。
综上，基于上述第一接合层102的设置，实现了第一基板101的第一导电面、第一接合层102、电子元件103、第二接合层104和第二基板105的第一导电面的牢固接合和可靠连接，提高了封装结构100的可靠性，降低了封装结构100的制作成本，提升了封装结构100的竞争力。
其中，本申请对封装结构100的具体类型不做限定。例如，该封装结构100可以为大功率半导体模块，如两面冷却模块(double-side cooling power module，DSC-PM)，该封装结构100也可以为具有印刷电路板的半导体模块，如需要控制焊层厚度和防止焊料溢出的具有叠层结构的半导体装置。
本申请提供的封装结构，通过将第一接合层设置在位于第一基板的第一导电面和电子元件的第一接合面之间，以便基于第一接合层实现电子元件与第一基板的接合。其中，第一接合层包括：第一接合材料和至少一个第一支撑件。并将第二接合层设置在位于电子元件的第二接合面和第二基板的第一导电面之间，以便基于第二接合层实现电子元件与第二基板的接合，电子元件的第一接合面与电子元件的第二接合面相对。由于至少一个第一支撑件的高度与第一接合层的厚度相同，且至少一个第一支撑件的熔点高于形成第一接合层的最高温度，因此，在形成第一接合层的过程中，至少一个第一支撑件不会完全溶解在第一接合材料中，使得至少一个第一支撑件的厚度仍与第 一接合层的厚度保持相同，以便通过至少一个第一支撑件102a形成具有至少一个第一支撑件的高度的第一接合层。并且，在封装结构需要多次回流的情况下，至少一个第一支撑件不会随着第一接合材料的移动而发生移动，使得至少一个第一支撑件在第一接合层中分布均匀，且基于至少一个第一支撑件的支撑作用，使得第一接合层能够经受得住挤压而不变形，也使得即使至少一个第一支撑件出现重融也不会导致第一接合材料发生溢出，确保了第一接合层良好的质量和接合强度，避免了电子元件下的第一接合材料不足而导致电子元件的电气短路或者失效等现象，从而确保了第一接合层的表面平整且厚度均匀，满足了对第一接合层的厚度和翘曲度的工艺要求。同时，还使得第一接合材料不再受到种类的限制，为第一接合层的制作提供了多种可能性，有利于降低第一接合层的成本。由此，提高了封装结构的可靠性，降低了封装结构的制作成本，提升了封装结构的竞争力。
下面，在上述图2-图4所示实施例的基础上，结合几个具体的实施例，对本申请的封装结构100中各个部品的具体结构进行详细说明。
继续结合图2，本申请中，第二接合层104可以包括：第二接合材料104b和至少一个第二支撑件104a。为了便于说明，图2中一个第二接合层104采用两个第二支撑件104a进行示意。
其中，第二接合材料104b的具体类型可以结合接合方式进行设置，本申请对此不做限定。可选地，在第二接合层104的类型包括焊接层的情况下，第二接合材料104b可以包括：焊片或者焊膏。在第二接合层104的类型包括烧结层的情况下，第二接合材料104b可以包括：粉状物料或者膏状物料。在第二接合层104的类型包括焊接层和烧结层的情况下，焊接层中，第二接合材料104b可以包括：焊片或者焊膏；烧结层中，第二接合材料104b可以包括：粉状物料或者膏状物料。
其中，第二支撑件104a可以设置为微米级尺寸，即第二支撑件104a在各个维度上的尺寸均为微米级，由于第二支撑件104a在各个维度上的尺寸均为微米级，因此，与数毫米级尺寸的第二接合层104的体积相比，第二支撑件104a的尺寸很小，使得第二支撑件104a在接合时对第二接合层104的工艺影响很小，也不会妨碍在第二接合层104上所形成的气泡从第二接合材料104b中逸出，避免了第二接合层104的空洞率过高，从而，对第二接合层104的接合影响较小，避免由于至少一个第二支撑件104a的尺寸过大而降低第二基板105的第一导电面和电子元件103的第二接合面之间的接合效果，使得第二基板105的第一导电面和电子元件103的第二接合面之间能够可靠接合。
可选地，不同的第二接合层104中的第二支撑件104a的形状可以相同或者不同。同一第二接合层104中的多个第二支撑件104a的形状可以相同或者不同。其中，本申请对第二支撑件104a的形状不做限定。可选地，第二支撑件104a的形状包括：球状、长方体状、椭球状、楔形状或者蚕状中的至少一个。
可选地，不同的第二接合层104中的第二支撑件104a的材料可以相同或者不同。同一第二接合层104中的多个第二支撑件104a的材料可以相同或者不同。其中，本申请对第二支撑件104a的材料不做限定。可选地，第二支撑件104a为单金属材料、合金材料、复合材料或者不导电材料中的任意一种。例如，单金属材料可以包括：铝Al、 金Au、铜Cu或者镍Ni。合金材料可以包括：铝Al、金Au、铜Cu或者镍Ni中的至少两种。可选地，第二支撑件104a为包覆材料、涂层材料、带材材料、线材材料中的任意一种。例如，金属涂层或异种金属包覆。从而使得封装结构100的制作成本降低。
可选地，不同的第二接合层104中的第二支撑件104a的数量可以相同或者不同。其中，本申请对任意一个第二接合层104中的第二支撑件104a的数量不做限定。从而使得第二接合层104中的第二支撑件104a的数量可调。一般情况下，第二支撑件104a的数量可以大于等于3个，有利于进一步提升第二接合层104的接合效果，且可以确保第二基板105和电子元件103的支撑平衡。
可选地，不同的第二接合层104中的第二支撑件104a的位置可以相同或者不同。其中，本申请对任意一个第二接合层104中的第二支撑件104a的位置不做限定。从而使得第二支撑件104a在第二接合层104中的位置自由，以便在需要的位置处植入所需尺寸的第二支撑件104a即可。
本申请中，为了避免在接合时第二支撑件104a被第二接合材料104b熔融而焊料移动到第二接合层104之外，因此，第二支撑件104a可以固定设置。进一步地，由于第二支撑件104a对第二接合层104的接合影响较小，因此，第二支撑件104a的设置位置可以包括多种，操作方便快捷，生成效率高。
可选地，至少一个第二支撑件104a可以固定设置在电子元件103的第二接合面上。
可选地，至少一个第二支撑件104a也可以固定设置在第二基板105的第一导电面上。
可选地，至少一个第二支撑件104a也可以固定设置在电子元件103的第二接合面和第二基板105的第一导电面上，且电子元件103的第二接合面上的第二支撑件104a与第二基板105的第一导电面上的第二支撑件104a交错设置。
其中，本申请对第二支撑件104a的固定方式不做限定。可选地，第二支撑件104a通过如下任意一种方式进行固定设置：超音波、烧结、电镀或者钎焊。
本申请中，至少一个第二支撑件104a的高度与第二接合层104的厚度相同，且至少一个第二支撑件104a的熔点高于形成第二接合层104的最高温度。其中，第二接合层104的厚度可以结合实际情况进行设置，本申请对此不做限定。第二支撑件104a的高度可以根据对应的第二接合层104的厚度进行设置，其高度的具体数值不做限定。可选地，不同的第二接合层104中的第二支撑件104a的高度可以相同或者不同。
基于前述设置，在形成第二接合层104的过程中，至少一个第二支撑件104a不会完全溶解在第二接合层104中的第二接合材料104b中，使得至少一个第二支撑件104a的厚度仍与第二接合层104的厚度保持相同，以便通过至少一个第二支撑件104a形成具有至少一个第二支撑件104a的高度的第二接合层104。并且，在封装结构100需要多次回流的情况下，至少一个第二支撑件104a不会随着第二接合材料104b的移动而发生移动，使得至少一个第二支撑件104a在第二接合层104中分布均匀，且基于至少一个第二支撑件104a的支撑作用，使得第二接合层104能够经受得住挤压而不变形，也使得即使至少一个第一支撑件102a出现重融也不会导致第二接合层104中的第二接合材料104b发生溢出，确保了第二接合层104良好的质量和接合强度，避免了第二基板105下的第二接合材料104b不足而导致电子元件103的电气短路或者失效等现象， 从而确保了第二接合层104的表面平整且厚度均匀，满足了对第二接合层104的厚度和翘曲度的工艺要求。同时，还使得第二接合层104中的第二接合材料104b不再受到种类的限制，为第二接合层104的制作提供了多种可能性，有利于降低第二接合层104的成本。
由此，基于第二接合层104的表面平整且厚度均匀，第二基板105的第一导电面和电子元件103的第二接合面通过第二接合层104实现了良好的接合效果以及电气连接，还降低了接合成本。
综上，基于上述第一接合层102和第二接合层104的设置，实现了第一基板101的第一导电面、第一接合层102、电子元件103、第二接合层104和第二基板105的第一导电面的牢固接合和可靠连接，提高了封装结构100的可靠性，降低了封装结构100的接合成本，提升了封装结构100的竞争力。
本申请中，第一支撑件102a的固定方式可以包括多种，第二支撑件104a的固定方式也可以包括多种。下面，结合图5-图6，对第一支撑件102a和第二支撑件104a均固定设置在电子元件103的具体实现过程进行举例说明。为了便于说明，图5中，第一支撑件102a和第二支撑件104a的形状为球状，电子元件103的两个接合面上支撑件的数量均设置为三个。图6中，第一支撑件102a和第二支撑件104a的形状为蚕状，电子元件103的两个接合面上支撑件的数量均设置为三个。且由于图5和图6为截面图，因此，图5和图6仅示意出电子元件103的两个接合面上各自的两个支撑件。
如图5所示，首先，利用超音波工作头300在电子元件103的上接合面上分别植入三个第一微小金属块102＇(图5中仅示意出其中两个第一微小金属块102＇)，使得电子元件103的上接合面上固定设置有三个第一微小金属块102＇。其中，每个第一微小金属块102＇靠近电子元件103的上接合面的一侧呈球状，且每个第一微小金属块102＇的高度大于第一接合层102的厚度。例如，第一微小金属块102＇的高度位于0.02mm-10mm之间，第一接合层102的厚度位于0.01mm-10mm之间。
其次，在电子元件103的上接合面植入三个第一微小金属块102＇完成后，将电子元件103进行翻转，将三个第一微小金属块102＇分别放置在定位板500的三个孔中，以避免三个第一微小金属块102＇妨碍后续的超声波操作。再利用超音波工作头300在电子元件103的下接合面上分别植入三个第二微小金属块104＇(图5中仅示意出其中两个第二微小金属块104＇)，使得电子元件103的下接合面上固定设置有三个第二微小金属块104＇。其中，每个第二微小金属块104＇靠近电子元件103的下接合面的一侧呈球状，且每个第二微小金属块104＇的高度大于第二接合层104的厚度。
从而，电子元件103的上接合面和下接合面上均固定设置有三个微小金属块。
接着，将电子元件103的下接合面朝下放入到治具601中，使得三个第二微小金属块104＇分别放置在治具601的两个孔中，再沿着图5所示箭头的方向对治具601进行施压，通过其中两个控厚环602对三个第一微小金属块102＇进行平整化处理，剩余两个控厚环602作以高度维持的辅助功能，来调节三个第一微小金属块102＇的高度，使得三个第一微小金属块102＇的高度与第一接合层102的厚度相同，从而调节第一接合层102的厚度，这样电子元件103的上接合面上固定设置有三个第一支撑件102a。
然后，在电子元件103的上接合面上的三个第一微小金属块102＇完成平整化处理之后，将电子元件103的上接合面朝下放入到治具601中，使得三个第一支撑件102a分别放置在治具601的三个孔中，再沿着图5所示箭头的方向对治具601进行施压，通过其中两个个控厚环602对三个第二微小金属块104＇进行平整化处理，剩余两个控厚环602作以高度维持的辅助功能，来调节三个第二微小金属块104＇的高度，使得三个第二微小金属块104＇的高度与第二接合层104的厚度相同，从而调节第二接合层104的厚度，这样电子元件103的下接合面上固定设置有三个第二支撑件104a。需要说明的是，这个步骤的实现过程与电子元件103的上接合面上的三个第一微小金属块102＇完成平整化处理的实现过程原理相同，故图5中未对此步骤进行示意。
从而，电子元件103的上接合面设置有三个第一支撑件102a，电子元件103的下接合面上设置有三个第二支撑件104a，且第一支撑件102a和第二支撑件104a对称设置。由此，电子元件103的上接合面与第一基板101的第一接合面的接合可以实现第一接合层102的厚度与翘曲度的控制，使得第一接合层102的表面平整且厚度均匀，电子元件103的下接合面与第二基板105的第一接合面的接合可以实现第二接合层104的厚度与翘曲度的控制，使得第二接合层104的表面平整且厚度均匀。
如图6所示，首先，利用超音波工作头和劈刀400在电子元件103的上接合面上分别植入三个第一微小金属块102＇(图6中仅示意出其中两个第一微小金属块102＇)，使得电子元件103的上接合面上固定设置有三个第一微小金属块102＇。其中，每个第一微小金属块102＇靠近电子元件103的上接合面的一侧呈蚕状，且每个第一微小金属块102＇的高度大于第一接合层102的厚度。例如，第一微小金属块102＇的高度位于0.02mm-10mm之间，第一接合层102的厚度位于0.01mm-10mm之间。
其次，在电子元件103的上接合面植入三个第一微小金属块102＇完成后，将电子元件103进行翻转，将三个第二微小金属块104＇(图6中仅示意出其中两个第二微小金属块104＇)分别放置在定位板500的三个孔中，以避免三个第二微小金属块104＇妨碍后续的超声波操作。再利用超音波工作头和劈刀400在电子元件103的下接合面上分别植入三个第二微小金属块104＇，使得电子元件103的下接合面上固定设置有三个第二微小金属块104＇。其中，每个第二微小金属块104＇靠近电子元件103的下接合面的一侧呈蚕状，且每个第二微小金属块104＇的高度大于第二接合层104的厚度。
从而，电子元件103的上接合面和下接合面上均固定设置有三个微小金属块。
接着，将电子元件103的下接合面朝下放入到治具601中，使得三个第二微小金属块104＇分别放置在治具601的三个孔中，再沿着图6所示箭头的方向对治具601进行施压，通过其中两个控厚环602对三个第二微小金属块104＇进行平整化处理，剩余两个控厚环602作以高度维持的辅助功能，来调节三个第二微小金属块104＇的高度，使得三个第二微小金属块104＇的高度与第一接合层102的厚度相同，从而电子元件103的上接合面上固定设置有三个第一支撑件102a。
然后，在电子元件103的上接合面上的三个第二微小金属块104＇完成平整化处理之后，将电子元件103的上接合面朝下放入到治具601中，使得三个第一支撑件102a分别放置在治具601的三个孔中，再沿着图6所示箭头的方向对治具601进行施压， 通过四个控厚环602对三个第二微小金属块104＇进行平整化处理，剩余两个控厚环602作以高度维持的辅助功能，来调节三个第二微小金属块104＇的高度，使得三个第二微小金属块104＇的高度与第二接合层104的厚度相同，从而电子元件103的下接合面上固定设置有三个第二支撑件104a。需要说明的是，这个步骤的实现过程与电子元件103的上接合面上的三个第二微小金属块104＇完成平整化处理的实现过程原理相同，故图6中未对此步骤进行示意。
从而，电子元件103的上接合面设置有三个第一支撑件102a，电子元件103的下接合面上设置有三个第二支撑件104a，且第一支撑件102a和第二支撑件104a对称设置。由此，电子元件103的上接合面与第一基板101的第一接合面的接合可以实现第一接合层102的厚度与翘曲度的控制，使得第一接合层102的表面平整且厚度均匀，电子元件103的下接合面与第二基板105的第一接合面的接合可以实现第二接合层104的厚度与翘曲度的控制，使得第二接合层104的表面平整且厚度均匀。
另外，由于电子元件103的上接合面和下接合面均设置有支撑件，因此，可以任意选择抓取电子元件103的上接合面或者下接合面，提高了抓取的效率。
需要说明的是，除了上述方式之外，电子元件103的上接合面也可设置有三个第二支撑件104a，电子元件103的上接合面也可设置有三个第一支撑件102a。同样的，第一基板101和第二基板105可以两面设置支撑件，具体实现过程可参见上述过程，此处不做赘述。并且，电子元件103也可以只在一个接合面上固定设置支撑件。同样的，第一基板101和第二基板105也可以一面设置支撑件。
基于上述描述，支撑件的固定方式包括多种，因此，制作封装结构100的实现方式也包括多种。下面，结合图7-图8，对制作封装结构100的具体实现过程进行举例说明。为了便于说明，图7和图8中，第一支撑件102a和第二支撑件104a的形状为蚕状，第一支撑件102a和第二支撑件104a的数量均设置为三个。且由于图7和图8为截面图，因此，图7和图8仅示意出两个第一支撑件102a和两个第二支撑件104a。
如图7所示，首先，在第一基板101的第一接合面上植入三个第一支撑件102a，且每个第一支撑件102a的高度与第一接合层102的厚度保持相同，每个第一支撑件102a的熔点均高于形成第一接合层102的最高温度。其次，在三个第一支撑件102a上贴装第一接合材料102b(如图7所示的焊片)，再在第一接合材料102b上贴装电子元件103。经过一次回流后，电子元件103通过第一接合层102焊接在第一基板101的第一接合面上。接着，在电子元件103的上表面贴装第二接合材料104b，再将第二基板105的第一接合面上植入三个第二支撑件104a，将三个第二支撑件104a朝向贴设在第二接合材料104b的上表面，且每个第二支撑件104a的高度与第二接合层104的厚度保持相同，每个第二支撑件104a的熔点均高于形成第二接合层104的最高温度。经过二次回流后，第二基板105通过第二接合层104焊接在电子元件103上。由此，第一基板101、电子元件103和第二基板105均可以接合在一起形成封装结构100。
另外，由于第一接合层102设置有第一支撑件102a，因此，在二次回流的过程中，第一支撑件102a的高度能够继续保持，且即使第一支撑件102a发生熔融也不会使得第一接合材料102b发生溢出，也无需要求第一接合材料102b的熔点高于第二接合材料104b的熔点，使得第一接合材料102b和第二接合材料104b不受限于种类的限制。
如图8所示，首先，在第一基板101的第一接合面上植入三个第一支撑件102a，且每个第一支撑件102a的高度与第一接合层102的厚度保持相同，每个第一支撑件102a的熔点均高于形成第一接合层102的最高温度。其次，在三个第一支撑件102a上贴装第一接合材料102b(如图8所示的焊片)，再在第一接合材料102b上贴装电子元件103，该电子元件103的上表面上植入有三个第二支撑件104a，且每个第二支撑件104a的高度与第二接合层104的厚度保持相同，每个第二支撑件104a的熔点均高于形成第二接合层104的最高温度。经过一次回流后，电子元件103通过第一接合层102焊接在第一基板101上。接着，在电子元件103的上表面贴装第二接合材料104b，再在第二接合材料104b的上表面贴设第二基板105。经过二次回流后，第二基板105通过第二接合层104焊接在电子元件103上。由此，第一基板101、电子元件103和第二基板105均可以接合在一起形成封装结构100。
另外，由于第一接合层102设置有第一支撑件102a，因此，在二次回流的过程中，第一支撑件102a的高度能够继续保持，且即使第一支撑件102a发生熔融也不会使得第一接合材料102b发生溢出，也无需要求第一接合材料102b的熔点高于第二接合材料104b的熔点，使得第一接合材料102b和第二接合材料104b不受限于种类的限制。
图9为本申请一实施例提供的封装结构的结构示意图。如图9所示，与图2所示封装结构100不同的是，本申请提供的封装结构100还可以包括：塑封材料106。第一基板101、第一接合层102、电子元件103的部分、第二接合层104以及第二基板105均设置在塑封材料106中，从而通过塑封材料106来保护封装结构100中的各个部品以及各个部品之间的电气连接，有利于封装结构100的使用。
其中，本申请对塑封材料106的具体类型不做限定。且为了实现信号的输入和/或输出，电子元件103中的端子的一端位于塑封材料106中，该端子的另一端位于塑封材料106之外，以实现电子元件103与其他部品的电气连接。另外，为了加快封装结构100的散热，第一基板101中第二导电层会暴露设置在塑封材料106之外，第二基板105中第四导电层也会暴露设置在塑封材料106之外。
本申请中，电子元件103可以包括多种实现方式。下面，结合图10和图11，采用两种可行的实现方式，对电子元件103的具体实现方式进行举例说明。
一种可行的实现方式中，为了实现封装结构100与其他部品的连接，如图10所示，若封装结构100包括多个不连接的第一接合层102和多个不连接的第二接合层104，则电子元件103可以包括：芯片103a、第三接合层103b、互联柱103c、信号端子103d和功率端子103e。为了便于说明，图10中，采用两个芯片103a为例进行示意，以两个互联柱103c为例进行示意，采用两个功率端子103e为例进行示意，采用一个信号端子103d为例进行示意。
本申请中，芯片103a位于除与信号端子103d对应的第一接合层102和功率端子103e对应的第一接合层102之外的第一接合层102和第三接合层103b之间，互联柱103c位于与芯片103a对应的第三接合层103b和对应的第二接合层104之间。
其中，芯片103a的数量可以为一个或者多个，互联柱103c的数量可以为一个或者多个。一般情况下，当芯片103a的数量为一个时，该芯片103a通过一个第一接合层102与第一基板101的第一导电面接合，该芯片103a通过一个第三接合层103b与 一个互联柱103c接合，该互联柱103c通过一个第二接合层104与第二基板105的第一导电面接合。当芯片103a的数量为多个时，每个芯片103a通过一个第一接合层102与第一基板101的第一导电面接合，每个芯片103a通过一个第三接合层103b与一个互联柱103c接合，每个互联柱103c通过一个第二接合层104与第二基板105的第一导电面接合。
这样，在多个芯片103a的厚度相同时，借助各个互联柱103c的厚度可以调节芯片103a的厚度，使得封装结构100的整体厚度以满足实际厚度需求，其中各个互联柱103c的厚度通常相同。在多个芯片103a的厚度不相同时，借助各个互联柱103c可以调节芯片103a的厚度，使得封装结构100的厚度保持表面平整，提高封装结构100的可靠性。
另外，在多个芯片103a存在连接关系时，各个芯片103a对应的第一接合层102所接合的第一基板101的第一导电面中的同一个导电区域，和/或，各个芯片103a对应的互联柱103c所接合的第二基板105的第一导电面中的同一个导电区域。
例如，如图10所示，若芯片103a包括连接的IGBT和FRD，则IGBT对应的第一接合层102所接合的第一基板101的第一导电面中的导电区域与FRD对应的第一接合层102所接合的第一基板101的第一导电面中的导电区域为同一个，且IGBT对应的互联柱103c所接合的第二基板105的第一导电面中的导电区域与FRD对应的互联柱103c所接合的第二基板105的第一导电面中的导电区域为同一个。
本申请中，信号端子103d可以将其他部品输出的信号传输至芯片103a，也可以将芯片103a输出的信号传输至其他部品，也可以实现上述两个过程，本申请对此不做限定。其中，本申请对信号端子103d的具体数量不做限定。
基于此，为了实现信号的输出和/或输入，信号端子103d从封装结构100的内部向封装结构100的外部延伸设置，位于封装结构100的内部的信号端子103d的一端位于除与芯片103a对应的第一接合层102和功率端子103e对应的第一接合层102之外的第一接合层102上，信号端子103d与芯片103a电连接，芯片103a对应的第一接合层102和信号端子103d对应的第一接合层102各自对应于第一基板101的第一导电面中的不同导电区域。
其中，信号端子103d与芯片103a的电连接方式可以包括多种，如图10中采用铝Al线键合方式实现两者的电连接。由于需要从芯片103a中引出导线至信号端子103d所接合的第一基板101的第一导电面中的导电区域上，因此，芯片103a的上方需要借助互联柱103c为导线预留出放置空间，从而确保信号端子103d与芯片103a之间的可靠连接，避免了其他因素的干扰。
本申请中，功率端子103e可以将芯片103a功率转换后的电压或者电流传输给其他部品，如向其他部品传输交流电等。其中，本申请对功率端子103e的具体数量不做限定。
基于此，为了实现功率端子103e的功率传输，功率端子103e可以直接与芯片103a连接，也可以通过互联柱103c间接与芯片103a连接。
当功率端子103e直接与芯片103a连接时，功率端子103e可以从封装结构100的内部向封装结构100的外部延伸设置，位于封装结构100的内部的功率端子103e的一 端位于除与芯片103a对应的第一接合层102和信号端子103d对应的第一接合层102之外的第一接合层102上，芯片103a对应的第一接合层102和功率端子103e对应的第一接合层102各自对应于第一基板101的第一导电面中的同一导电区域。
由此，功率端子103e通过一个第一接合层102所连接的第一基板101的第一导电面中的导电区域与芯片103a通过另一个第一接合层102所连接的第一基板101的第一导电面中的导电区域为同一个，使得功率端子103e与芯片103a能够电气互连。
当功率端子103e通过互联柱103c间接与芯片103a连接时，功率端子103e可以位于除互联柱103c对应的第二接合层104之外的第二接合层104，互联柱103c对应的第二接合层104和功率端子103e对应的第二接合层104各自对应于第二基板105的第一导电面中的同一导电区域。
由此，功率端子103e通过一个第二接合层104所连接的第二基板105的第一导电面中的导电区域与互联柱103c通过另一个第二接合层104所连接的第二基板105的第一导电面中的导电区域为同一个，使得功率端子103e与芯片103a能够电气互连。
需要说明的是，当功率端子103e的数量为一个时，该功率端子103e可以采用上述位置关系的任意一种。当功率端子103e的数量为多个时，多个功率端子103e可以采用上述位置关系的任意一种，也可以同时采用上述两种位置关系(图10中采用该方式进行示意)，本申请对此不做限定。
本申请中，第三接合层103b可以包括：第三接合材料103bb和至少一个第三支撑件103ba。为了便于说明，图10中一个第三接合层103b采用两个第三支撑件103ba为例进行示意。
其中，第三接合材料103bb的具体类型可以结合接合方式进行设置，本申请对此不做限定。可选地，在第三接合层103b的类型包括焊接层的情况下，第三接合材料103bb可以包括：焊片或者焊膏。在第三接合层103b的类型包括烧结层的情况下，第三接合材料103bb可以包括：粉状物料或者膏状物料。在第三接合层103b的类型包括焊接层和烧结层的情况下，焊接层中，第三接合材料103bb可以包括：焊片或者焊膏；烧结层中，第三接合材料103bb可以包括：粉状物料或者膏状物料。
其中，第三支撑件103ba可以设置为微米级尺寸，即第三支撑件103ba在各个维度上的尺寸均为微米级，由于第三支撑件103ba在各个维度上的尺寸均为微米级，因此，与数毫米级尺寸的第三接合层103b的体积相比，第三支撑件103ba的尺寸很小，使得第三支撑件103ba在接合时对第三接合层103b的工艺影响很小，也不会妨碍在第三接合层103b上所形成的气泡从第三接合材料103b中逸出，避免了第三接合层103的空洞率过高，从而，对第三接合层103b的接合影响较小，避免由于至少一个第三支撑件103ba的尺寸过大而降低芯片103a和互联柱103c之间的接合效果，使得芯片103a和互联柱103c之间能够可靠接合。
可选地，不同的第三接合层103b中的第三支撑件103ba的形状可以相同或者不同。同一第三接合层103b中的多个第三支撑件103ba的形状可以相同或者不同。其中，本申请对第三支撑件103ba的形状不做限定。可选地，第三支撑件103ba的形状包括：球状、长方体状、椭球状、楔形状或者蚕状中的至少一个。
可选地，不同的第三接合层103b中的第三支撑件103ba的材料可以相同或者不同。 同一第三接合层103b中的多个第三支撑件103ba的材料可以相同或者不同。其中，本申请对第三支撑件103ba的材料不做限定。可选地，第三支撑件103ba为单金属材料、合金材料、复合材料或者不导电材料中的任意一种。例如，单金属材料可以包括：铝Al、金Au、铜Cu或者镍Ni。合金材料可以包括：铝Al、金Au、铜Cu或者镍Ni中的至少两种。可选地，第三支撑件103ba为包覆材料、涂层材料、带材材料、线材材料中的任意一种。例如，金属涂层或异种金属包覆。从而使得封装结构100的制作成本降低。
可选地，不同的第三接合层103b中的第三支撑件103ba的数量可以相同或者不同。其中，本申请对任意一个第三接合层103b中的第三支撑件103ba的数量不做限定。
可选地，不同的第三接合层103b中的第三支撑件103ba的位置可以相同或者不同。其中，本申请对任意一个第三接合层103b中的第三支撑件103ba的位置不做限定。从而使得第三接合层103b中的第三支撑件103ba的数量可调。一般情况下，第三支撑件103ba的数量可以大于等于3个，有利于进一步提升第三接合层103b的接合效果，且可以确保芯片103a和互联柱103c的支撑平衡。
可选地，不同的第三接合层103b中的第三支撑件103ba的位置可以相同或者不同。其中，本申请对任意一个第三接合层103b中的第三支撑件103ba的位置不做限定。从而使得第三支撑件103ba在第三接合层103b中的位置自由，以便在需要的位置处植入所需尺寸的第三支撑件103ba即可。
本申请中，为了避免在接合时第三支撑件103ba被第三接合材料103bb熔融而焊料移动到第三接合层103b之外，因此，第三支撑件103ba可以固定设置。进一步地，由于第三支撑件103ba对第三接合层103b的接合影响较小，因此，第三支撑件103ba的设置位置可以包括多种，操作方便快捷，生成效率高。
可选地，至少一个第三支撑件103ba可以固定设置在芯片103a上靠近互联柱103c的一面上。
可选地，至少一个第三支撑件103ba可以固定设置在互联柱103c上靠近芯片103a的一面上。
可选地，至少一个第三支撑件103ba可以固定设置在芯片103a上靠近互联柱103c的一面上和互联柱103c上靠近芯片103a的一面上，且芯片103a上靠近互联柱103c的一面上的第三支撑件103ba与互联柱103c上靠近芯片103a的一面上的第三支撑件103ba交错设置。
其中，本申请对第三支撑件103ba的固定方式不做限定。可选地，第三支撑件103ba通过如下任意一种方式进行固定设置：超音波、烧结、电镀或者钎焊。
本申请中，至少一个第三支撑件103ba的高度与第三接合层103b的厚度相同，且至少一个第三支撑件103ba的熔点高于形成第三接合层103b的最高温度。其中，第三接合层103b的厚度可以结合实际情况进行设置，本申请对此不做限定。第三支撑件103ba的高度可以根据对应的第三接合层103b的厚度进行设置，其高度的具体数值不做限定。可选地，不同的第三接合层103b中的第三支撑件103ba的高度可以相同或者不同。
基于前述设置，在形成第三接合层103b的过程中，至少一个第三支撑件103ba不 会完全溶解在第三接合层103b中的第三接合材料103bb中，使得至少一个第三支撑件103ba的厚度仍与第三接合层103b的厚度保持相同，以便通过至少一个第三支撑件103ba形成具有至少一个第三支撑件103ba的高度的第三接合层103b。并且，在封装结构100需要多次回流的情况下，至少一个第三支撑件103ba不会随着第三接合材料103bb的移动而发生移动，使得至少一个第三支撑件103ba在第三接合层103b中分布均匀，且基于至少一个第三支撑件103ba的支撑作用，使得第三接合层103b能够经受得住挤压而不变形，也使得即使至少一个第三支撑件103ba出现重融也不会导致第三接合层103b中的第三接合材料103bb发生溢出，确保了第三接合层103b良好的质量和接合强度，避免了互联柱103c下的第三接合材料103bb不足而导致芯片103a的电气短路或者失效等现象，从而确保了第三接合层103b的表面平整且厚度均匀，满足了对第三接合层103b的厚度和翘曲度的工艺要求。同时，还使得第三接合层103b中的第三接合材料103bb不再受到种类的限制，为第三接合层103b的制作提供了多种可能性，有利于降低第三接合层103b的成本。
由此，基于第三接合层103b的表面平整且厚度均匀，芯片103a和互联柱103c通过第三接合层103b实现了良好的接合效果以及电气连接，还降低了接合成本。
综上，基于上述第一接合层102、第二接合层104和第三接合层103b的设置，实现了第一基板101的第一导电面、第一接合层102、芯片103a、第三接合层103b、互联柱103c、第二接合层104和第二基板105的第一导电面的牢固接合和可靠连接，且还实现了信号端子103d与第一基板101的第一导电面的牢固接合和可靠连接，以及功率端子103e与第一基板101的第一导电面和/或与第二基板105的第一导电面的牢固接合和可靠连接，不仅提高了封装结构100的可靠性，降低了封装结构100的接合成本，还使得封装结构100可以实现完整的功率转换过程。
另一种可行的实现方式中，如图11所示，若封装结构100包括多个不连接的第一接合层102和多个不连接的第二接合层104，则电子元件103可以包括：芯片103a、信号端子103d和功率端子103e。为了便于说明，图11中，采用两个芯片103a为例进行示意，采用两个功率端子103e为例进行示意，采用一个信号端子103d为例进行示意。
本申请中，芯片103a位于除与信号端子103d对应的第一接合层102和功率端子103e对应的第一接合层102之外的第一接合层102与对应的第二接合层104之间。
其中，芯片103a的数量可以为一个或者多个。一般情况下，当芯片103a的数量为一个时，该芯片103a通过一个第一接合层102与第一基板101的第一导电面接合，该芯片103a通过一个第二接合层104与第二基板105的第一导电面接合。当芯片103a的数量为多个时，每个芯片103a通过一个第一接合层102与第一基板101的第一导电面接合，每个芯片103a通过一个第二接合层104与第二基板105的第一导电面接合。
这样，上述连接方式通常适用于多个芯片103a的厚度相同的场景下，以便封装结构100的整体厚度可以满足实际厚度需求，使得封装结构100的厚度保持表面平整，提高封装结构100的可靠性。
另外，在多个芯片103a存在连接关系时，各个芯片103a对应的第一接合层102所接合的第一基板101的第一导电面中的同一个导电区域，和/或，各个芯片103a对应的 第二接合层104所接合的第二基板105的第一导电面中的同一个导电区域。
例如，如图11所示，若芯片103a包括连接的IGBT和FRD，则IGBT对应的第一接合层102所接合的第一基板101的第一导电面中的导电区域与FRD对应的第一接合层102所接合的第一基板101的第一导电面中的导电区域为同一个，且IGBT对应的第二接合层104所接合的第二基板105的第一导电面中的导电区域与FRD对应的第二接合层104所接合的第二基板105的第一导电面中的导电区域为同一个。
本申请中，信号端子103d可以将其他部品输出的信号传输至芯片103a，也可以将芯片103a输出的信号传输至其他部品，也可以实现上述两个过程，本申请对此不做限定。其中，本申请对信号端子103d的具体数量不做限定。
基于此，信号端子103d通过焊接或烧结工艺与第一基板101的信号端子接合在一起。由于金属端子有一定重量，且在制造封装模块100时为了防止端子变形而常常在端子上施加压力。因此，为了实现信号的输出和/或输入，信号端子103d从封装结构100的内部向封装结构100的外部延伸设置，且为了避免将第一接合材料101b溢出，位于封装结构100的内部的信号端子103d的一端位于除与芯片103a对应的第一接合层102和功率端子103e对应的第一接合层102之外的第一接合层102上，第一接合层102中包括有第一接合材料102b和固定设置在第一基板101的第一导电面上的第一支撑件102a，信号端子103d与芯片103a电连接，芯片103a对应的第一接合层102和信号端子103d对应的第一接合层102各自对应于第一基板101的第一导电面中的不同导电区域，实现了芯片103a的信号电极与第一基板101上的信号端子103d之间的互联。
其中，信号端子103d与芯片103a的电连接方式可以包括多种，如图11中采用铝Al线或者铝Al包覆铜Cu线等键合方式将芯片103a的信号电极与第一基板101的信号端子互联来实现两者的电连接。本申请中，功率端子103e可以将芯片103a功率转换后的电压或者电流传输给其他部品，如向其他部品传输交流电等。其中，本申请对功率端子103e的具体数量不做限定。
基于此，为了实现功率端子103e的功率传输，功率端子103e可以通过第一接合层102与芯片103a连接，也可以通过第二接合层104与芯片103a连接。
当功率端子103e通过第一接合层102与芯片103a连接时，功率端子103e可以从封装结构100的内部向封装结构100的外部延伸设置，位于封装结构100的内部的功率端子103e的一端位于除与芯片103a对应的第一接合层102和信号端子103d对应的第一接合层102之外的第一接合层102上，第一接合层102中包括有第一接合材料102b和固定设置在第一基板101的第一导电面上的第一支撑件102a，芯片103a对应的第一接合层102和功率端子103e对应的第一接合层102各自对应于第一基板101的第一导电面中的同一导电区域。
由此，功率端子103e通过一个第一接合层102所连接的第一基板101的第一导电面中的导电区域与芯片103a通过另一个第一接合层102所连接的第一基板101的第一导电面中的导电区域为同一个，使得功率端子103e与芯片103a能够电气互连。
当功率端子103e通过第二接合层104与芯片103a连接时，功率端子103e可以位于除芯片103a对应的第二接合层104之外的第二接合层104上，第二接合层104中包括有第二接合材料104b和固定设置在第二基板105的第一导电面上的第二支撑件104a， 芯片103a对应的第二接合层104和功率端子103e对应的第二接合层104各自对应于第二基板105的第一导电面中的同一导电区域。
由此，功率端子103e通过一个第二接合层104所连接的第二基板105的第一导电面中的导电区域与芯片103a通过另一个第二接合层104所连接的第二基板105的第一导电面中的导电区域为同一个，使得功率端子103e与芯片103a能够电气互连。
需要说明的是，当功率端子103e的数量为一个时，该功率端子103e可以采用上述位置关系的任意一种。当功率端子103e的数量为多个时，多个功率端子103e可以采用上述位置关系的任意一种，也可以同时采用上述两种位置关系(图11中采用该方式进行示意)，本申请对此不做限定。
综上，基于上述第一接合层102、第二接合层104和第三接合层103b的设置，实现了第一基板101的第一导电面、第一接合层102、芯片103a、第二接合层104和第二基板105的第一导电面的牢固接合和可靠连接，且还实现了信号端子103d与第一基板101的第一导电面的牢固接合和可靠连接，以及功率端子103e与第一基板101的第一导电面和/或与第二基板105的第一导电面的牢固接合和可靠连接，不仅提高了封装结构100的可靠性，降低了封装结构100的接合成本，还使得封装结构100可以实现完整的功率转换过程。
需要说明的是，除了上述两种方式之外，当芯片103a的数量为多个时，部分芯片103a中的每个芯片103a通过一个第一接合层102与第一基板101的第一导电面接合，每个芯片103a通过一个第三接合层103b与一个互联柱103c接合，每个互联柱103c通过一个第二接合层104与第二基板105的第一导电面接合。剩余部分芯片103a中的每个芯片103a通过一个第一接合层102与第一基板101的第一导电面接合，每个芯片103a通过一个第二接合层104与第二基板105的第一导电面接合。
这样，在多个芯片103a的厚度不相同时，借助互联柱103c的厚度可以调节对应的芯片103a的厚度，使得封装结构100的整体厚度以满足实际厚度需求，使得封装结构100的厚度保持表面平整，提高封装结构100的可靠性。基于上述描述，在图10所示实施例的基础上，如图12和图13所示，电子元件103还可以包括：传感器107。其中，本申请对传感器107的类别不做限定。例如，该传感器107可以为NTC温度传感器107。且本申请对传感器107的接合方式不做限定。
一种可行的实现方式中，可选地，如图12所示，传感器107的两端以及传感器端子可以分别位于除与芯片103a对应的第一接合层102、信号端子103d对应的第一接合层102和功率端子103e对应的第一接合层102之外的第一接合层102上，第一接合层102中包括有第一接合材料102b和固定设置在第一基板101的第一导电面上的第一支撑件102a，芯片103a对应的第一接合层102和传感器107对应的两个第一接合层102各自对应于第一基板101的第一导电面中的不同导电区域，从而实现传感器107与第一基板101的接合，且通过传感器端子将传感器107的信号引出到封装结构100的外部。另一种可行的实现方式中，可选地，如图13所示，传感器107的一端位于除与芯片103a对应的第一接合层102、信号端子103d对应的第一接合层102和功率端子103e对应的第一接合层102之外的第一接合层102上，第一接合层102中包括有第一接合材料102b和固定设置在第一基板101的第一导电面上的第一支撑件102a，传 感器107的另一端通过传输导线从封装结构100的内部向封装结构100的外部延伸设置，芯片103a对应的第一接合层102和传感器107对应的第一接合层102各自对应于第一基板101的第一导电面中的不同导电区域，传感器107的另一端与传感器端子电连接(图13中传感器107的上部搭线与传感器端子接合在第一基板101上的接合层电连接)，从而实现传感器107在第一基板101的接合，且通过传感器端子将传感器107的信号引出到封装结构100的外部。
其中，与信号端子103d的设置方式不同的是，传感器端子是通过铝Al线与传感器107电连接，传感器端子的其他设置方式与信号端子103d的设置方式相同，具体实现方式参见前述描述内容，此处不做赘述。需要说明的是，传感器107还可以接合图11所示封装结构100进行设置，图12和图13仅为可行的示例。另外，除了上述元器件之外，电子元件103还可以但不限于包括：电阻、电容或者电感。其中，电阻、电容和电感与传感器107的接合方式均可以采用传感器107的第一种接合方式，此处不做赘述。
本领域技术人员可以理解，高集成和高密度的封装结构100对散热效果要求很高。基于此，为了进一步地提高封装结构100的冷却能力，如图14和图15所示，本申请提供的封装结构100还可以包括：第一散热件108和第四接合层109。
其中，本申请对第一散热件108和第四接合层109的数量不做限定，一个第一散热件108对应一个第四接合层109或者多个第四接合层109。为了便于说明，图14和图15中采用一个第一散热件108和一个第四接合层109进行示意，且图14以图9所示实施例为基础对封装结构100进行示意，图15以图10所示实施例为基础对封装结构100进行示意。
本申请中，第四接合层109位于第一基板101的第一导电面(即第二导电层)与第一散热件108之间，第四接合层109用于实现第一基板101与第一散热件108之间的接合。第四接合层109可以包括：第四接合材料109b和至少一个第四支撑件109a。为了便于说明，图14和图15中一个第四接合层109采用五个第四支撑件109a进行示意。
其中，第四接合材料109b的具体类型可以结合接合方式进行设置，本申请对此不做限定。可选地，在第四接合层109的类型包括焊接层的情况下，第四接合材料109b可以包括：焊片或者焊膏。在第四接合层109的类型包括烧结层的情况下，第四接合材料109b可以包括：粉状物料或者膏状物料。在第四接合层109的类型包括焊接层和烧结层的情况下，焊接层中，第四接合材料109b可以包括：焊片或者焊膏；烧结层中，第四接合材料109b可以包括：粉状物料或者膏状物料。
其中，第四支撑件109a可以设置为微米级尺寸，即第四支撑件109a在各个维度上的尺寸均为微米级，由于第四支撑件109a在各个维度上的尺寸均为微米级，因此，与数毫米级尺寸的第四接合层109的体积相比，第四支撑件109a的尺寸很小，使得第四支撑件109a在接合时对第四接合层109的工艺影响很小，也不会妨碍在第四接合层109上所形成的气泡从第四接合材料109b中逸出，避免了第四接合层109的空洞率过高，从而，对第四接合层109的接合影响较小，避免由于至少一个第四支撑件109a的尺寸过大而降低第一基板101的第二导电面和第一散热件108之间的接合效果，使得 第一基板101和第一散热件108之间能够可靠接合。
可选地，不同的第四接合层109中的第四支撑件109a的形状可以相同或者不同。同一第四接合层109中的多个第四支撑件109a的形状可以相同或者不同。其中，本申请对第四支撑件109a的形状不做限定。可选地，第四支撑件109a的形状包括：球状、长方体状、椭球状、楔形状或者蚕状中的至少一个。
可选地，不同的第四接合层109中的第四支撑件109a的材料可以相同或者不同。同一第四接合层109中的多个第四支撑件109a的材料可以相同或者不同。其中，本申请对第四支撑件109a的材料不做限定。可选地，第四支撑件109a为单金属材料、合金材料、复合材料或者不导电材料中的任意一种。例如，单金属材料可以包括：铝Al、金Au、铜Cu或者镍Ni。合金材料可以包括：铝Al、金Au、铜Cu或者镍Ni中的至少两种。可选地，第一支撑件102a为包覆材料、涂层材料、带材材料、线材材料中的任意一种。例如，金属涂层或异种金属包覆。从而使得封装结构100的制作成本降低。
可选地，不同的第四接合层109中的第四支撑件109a的数量可以相同或者不同。其中，本申请对任意一个第四接合层109中的第四支撑件109a的数量不做限定。从而使得第一接合层102中的第四支撑件109a的数量可调。一般情况下，第四支撑件109a的数量可以大于等于3个，有利于进一步提升第四接合层109的接合效果，且可以确保第一基板101和第一散热件108的支撑平衡。可选地，不同的第四接合层109中的第四支撑件109a的位置可以相同或者不同。其中，本申请对任意一个第四接合层109中的第四支撑件109a的位置不做限定。从而使得第四支撑件109a在第四接合层109中的位置自由，以便在需要的位置处植入所需尺寸的第四支撑件109a即可。
本申请中，为了避免在接合时第四支撑件109a被第四接合材料109b熔融而焊料移动到第四接合层109之外，因此，第四支撑件109a可以固定设置。进一步地，由于第四支撑件109a对第四接合层109的接合影响较小，因此，第四支撑件109a的设置位置可以包括多种，操作方便快捷，生成效率高。
可选地，至少一个第四支撑件109a可以固定设置在第一基板101的第二导电面上。
可选地，至少一个第四支撑件109a可以固定设置在第一散热件108上靠近第一基板101的一面上。
可选地，至少一个第四支撑件109a可以固定设置在第一基板101的第二导电面和第一散热件108上靠近第一基板101的一面上，且第一基板101的第二导电面上的第四支撑件109a与第一散热件108上靠近第一基板101的一面上的第四支撑件109a交错设置。
其中，本申请对第四支撑件109a的固定方式不做限定。可选地，第四支撑件109a通过如下任意一种方式进行固定设置：超音波、烧结、电镀或者钎焊。
本申请中，至少一个第四支撑件109a的高度与第四接合层109的厚度相同，且至少一个第四支撑件109a的熔点高于形成第四接合层109的最高温度。其中，第四接合层109的厚度可以结合实际情况进行设置，本申请对此不做限定。第四支撑件109a的高度可以根据对应的第四接合层109的厚度进行设置，其高度的具体数值不做限定。可选地，不同的第四接合层109中的第四支撑件109a的高度可以相同或者不同。
基于前述设置，在形成第四接合层109的过程中，至少一个第四支撑件109a不会 完全溶解在第四接合层109中的第四接合材料109b中，使得至少一个第四支撑件109a的厚度仍与第四接合层109的厚度保持相同，以便通过至少一个第四支撑件109a形成具有至少一个第四支撑件109a的高度的第四接合层109。并且，在封装结构100需要多次回流的情况下，至少一个第四支撑件109a不会随着第四接合材料109b的移动而发生移动，使得至少一个第四支撑件109a在第四接合层109中分布均匀，且基于至少一个第四支撑件109a的支撑作用，使得第四接合层109能够经受得住挤压而不变形，也使得即使至少一个第四支撑件109a出现重融也不会导致第四接合层109中的第四接合材料109b发生溢出，确保了第四接合层109良好的质量和接合强度，从而确保了第四接合层109的表面平整且厚度均匀，满足了对第四接合层109的厚度和翘曲度的工艺要求。同时，还使得第四接合层109中的第四接合材料109b不再受到种类的限制，为第四接合层109的制作提供了多种可能性，有利于降低第四接合层109的成本。
由此，基于第四接合层109的表面平整且厚度均匀，第一基板101和第一散热件108通过第四接合层109实现了良好的接合效果，提高了封装结构100的可靠性和冷却能力，还降低了接合成本，有利于封装结构100的高密度和高集成。
继续结合图14和图15，本申请提供的封装结构100还可以包括：第二散热件110和第五接合层111。其中，本申请对第二散热件110和第五接合层111的数量不做限定，一个第二散热件110对应一个第五接合层111或者多个第五接合层111。为了便于说明，图14和图15中采用一个第二散热件110和一个第五接合层111进行示意。
本申请中，第五接合层111位于第二基板105的第二导电面(即第四导电层)与第二散热件110之间，第五接合层111用于实现第二基板105与第二散热件110之间的接合。第五接合层111可以包括：第五接合材料111b和至少一个第五支撑件111a。为了便于说明，图14和图15中一个第五接合层111采用五个第五支撑件111a进行示意。
其中，第五接合材料111b的具体类型可以结合接合方式进行设置，本申请对此不做限定。可选地，在第五接合层111的类型包括焊接层的情况下，第五接合材料111b可以包括：焊片或者焊膏。在第五接合层111的类型包括烧结层的情况下，第五接合材料111b可以包括：粉状物料或者膏状物料。在第五接合层111的类型包括焊接层和烧结层的情况下，焊接层中，第五接合材料111b可以包括：焊片或者焊膏；烧结层中，第五接合材料111b可以包括：粉状物料或者膏状物料。
其中，第五支撑件111a可以设置为微米级尺寸，即第五支撑件111a在各个维度上的尺寸均为微米级，由于第五支撑件111a在各个维度上的尺寸均为微米级，因此，与数毫米级尺寸的第五接合层111的体积相比，第五支撑件111a的尺寸很小，使得第五支撑件111a在接合时对第五接合层111的工艺影响很小，也不会妨碍在第五接合层111上所形成的气泡从第五接合材料111b中逸出，避免了第五接合层111的空洞率过高，从而，对第五接合层111的接合影响较小，避免由于至少一个第五支撑件111a的尺寸过大而降低第二基板105的第二导电面和第二散热件110之间的接合效果，使得第二基板105和第二散热件110之间能够可靠接合。
可选地，不同的第五接合层111中的第五支撑件111a的形状可以相同或者不同。和/或，同一第五接合层111中的多个第五支撑件111a的形状可以相同或者不同。其 中，本申请对第五支撑件111a的形状不做限定。可选地，第五支撑件111a的形状包括：球状、长方体状、椭球状、楔形状或者蚕状中的至少一个。
可选地，不同的第五接合层111中的第五支撑件111a的材料可以相同或者不同。和/或，同一第五接合层111中的多个第五支撑件111a的材料可以相同或者不同。其中，本申请对第五支撑件111a的材料不做限定。可选地，第五支撑件111a为单金属材料、合金材料、复合材料或者不导电材料中的任意一种。例如，单金属材料可以包括：铝Al、金Au、铜Cu或者镍Ni。合金材料可以包括：铝Al、金Au、铜Cu或者镍Ni中的至少两种。可选地，第一支撑件102a为包覆材料、涂层材料、带材材料、线材材料中的任意一种。例如，金属涂层或异种金属包覆。从而使得封装结构100的制作成本降低。
可选地，不同的第五接合层111中的第五支撑件111a的数量可以相同或者不同。其中，本申请对任意一个第五接合层111中的第五支撑件111a的数量不做限定。从而使得第五接合层111中的第五支撑件111a的数量可调。一般情况下，第五支撑件111a的数量可以大于等于3个，有利于进一步提升第五接合层111的接合效果，且可以确保第二基板105和第二散热件110的支撑平衡。
可选地，不同的第五接合层111中的第五支撑件111a的位置可以相同或者不同。其中，本申请对任意一个第五接合层111中的第五支撑件111a的位置不做限定。从而使得第五支撑件111a在第五接合层111中的位置自由，以便在需要的位置处植入所需尺寸的第五支撑件111a即可。
本申请中，为了避免在接合时第五支撑件11a被第五接合材料111b熔融而焊料移动到第五接合层111之外，因此，第五支撑件111a可以固定设置。进一步地，由于第五支撑件111a对第五接合层111的接合影响较小，因此，第五支撑件111a的设置位置可以包括多种，操作方便快捷，生成效率高。
可选地，至少一个第五支撑件111a固定设置在第二散热件110上靠近第二基板105的一面上。
可选地，至少一个第五支撑件111a固定设置在第二基板105的第二导电面上。
可选地，至少一个第五支撑件111a可以固定设置在第二散热件110上靠近第二基板105的一面和第二基板105的第二导电面上，且第二散热件110上靠近第二基板105的一面上的第五支撑件111a与第二基板105的第二导电面上的第五支撑件111a交错设置。
其中，本申请对第五支撑件111a的固定方式不做限定。可选地，第五支撑件111a通过如下任意一种方式进行固定设置：超音波、烧结、电镀或者钎焊。
本申请中，至少一个第五支撑件111a的高度与第五接合层111的厚度相同，且至少一个第五支撑件111a的熔点高于形成第五接合层111的最高温度。其中，第五接合层111的厚度可以结合实际情况进行设置，本申请对此不做限定。第五支撑件111a的高度可以根据对应的第五接合层111的厚度进行设置，其高度的具体数值不做限定。可选地，不同的第五接合层111中的第五支撑件111a的高度可以相同或者不同。
基于前述设置，在形成第五接合层111的过程中，至少一个第五支撑件111a不会完全溶解在第五接合层111中的第五接合材料111b中，使得至少一个第五支撑件111a 的厚度仍与第五接合层111的厚度保持相同，以便通过至少一个第五支撑件111a形成具有至少一个第五支撑件111a的高度的第五接合层111。并且，在封装结构100需要多次回流的情况下，至少一个第五支撑件111a不会随着第五接合材料111b的移动而发生移动，使得至少一个第五支撑件111a在第五接合层111中分布均匀，且基于至少一个第五支撑件111a的支撑作用，使得第五接合层111能够经受得住挤压而不变形，也使得即使至少一个第五支撑件111a出现重融也不会导致第五接合层111中的第五接合材料111b发生溢出，确保了第五接合层111良好的质量，从而确保了第五接合层111的表面平整且厚度均匀，满足了对第五接合层111的厚度和翘曲度的工艺要求。同时，还使得第五接合层111中的第五接合材料111b不再受到种类的限制，为第五接合层111的制作提供了多种可能性，有利于降低第五接合层111的成本。
由此，基于第五接合层111的表面平整且厚度均匀，第二基板105和第二散热件110通过第五接合层111实现了良好的接合效果，提高了封装结构100的可靠性和冷却能力，还降低了接合成本，有利于封装结构100的高密度和高集成。
需要说明的是，本申请的封装结构100可以在第一基板101的第二导电面上接合第一散热件108，也可以在第二基板105的第二导电面上接合第二散热件110，也可以同时在第一基板101的第二导电面上接合第一散热件108以及在第二基板105的第二导电面上接合第二散热件110，本申请对此不做限定。
另外，本申请中，一个如图2-图13所示的封装结构100可以单独设置第一散热件108和/或第二散热件110，具体设置过程如图14和图15所示实施例的描述内容。多个如图2-图13所示的封装结构100可以共同设置散热件，以节省成本，即在多个封装结构100的一侧设置散热件或者在多个封装结构100的两侧均设置散热件。
在一个具体的实施例中，如图2-图13所示的封装结构100以图16所示直流电(direct current，DC)转交流电(alternating current，AC)变换模块100＇为例。由于DCAC变换模块100＇通常向被供电设备提供三相交流电，因此，在实际使用过程中往往使用三个DCAC变换模块。基于此，为了进一步提高封装结构100的散热效果，因此，如图17所示，第一散热件108可以设置在三个DCAC变换模块100＇的一侧，第二散热件110可以设置在三个DCAC变换模块100＇的另一侧，从而构成一个完整的封装结构100。
示例性地，本申请还提供一种电动车辆。图18为本申请一实施例提供的电动车辆的结构示意图。如图18所示，本申请提供的电动车辆1可以包括：供电电池、电机控制单元(motor control unit，MCU)12以及Q个电机13(图18中以一个电机13进行示意)，Q为正整数。
其中，电机控制单元MCU 12可以包括3R个如图2-图17所示的封装结构100(图18中以三个封装结构100进行示意)，R为正整数。供电电池可以向每个封装结构100均提供第一电能，每个电机13对应连接至少三个封装结构100(图18中以一个电机13电连接三个封装结构100进行示意)。
本申请中，针对3R个封装结构100中的任意一个封装结构100，电机控制单元MCU 12可以控制该封装结构100将第一电能转换为与封装结构100对应连接的电机13所需的第二电能，并控制该封装结构100将第二电能传输至与封装结构100对应连 接的电机13，使得对应连接的电机13可以向电动车辆1提供驱动。
一般情况下，由于电动车辆1通常采用交流电机13，因此，本申请中，第一电能通常为直流电，第二电能通常为交流电，故一般交流电至少包括三相电，因此，每个电机13至少电连接三个封装结构100。其中，本申请对第一电能和第二电能的具体大小不做限定。另外，本申请对电机控制单元MCU 12的具体结构不做下的。该电机控制单元MCU 12还可以包括如开关控制模块等其他部品。
需要说明的是，除了上述连接方式之外，每个电机也可以电连接至少一个封装结构100，本申请对此不做限定。
本申请提供的电动车辆1包括封装结构100，可执行上述封装结构100实施例的技术方案，其具体实现原理和技术效果，可参见上述图2-图17所示实施例的技术方案，此处不再赘述。
示例性地，本申请还提供一种电子装置。本申请提供的电子装置可以包括：至少一个被接合结构。其中，被接合结构的数量可以为一个或者多个，本申请对此不做限定。当电子装置中包括多个被接合结构时，多个被接合结构可以单独设置，也可以叠放设置，本申请对此不做限定。
针对至少一个被接合结构中的任意一个被接合结构，该被接合结构可以包括：被接合件和微米级尺寸的至少一个支撑件。其中，至少一个支撑件设置在该被接合件的至少一个待接合面上。且支撑件在各个维度上的尺寸均为微米级，由于支撑件在各个维度上的尺寸均为微米级，因此，与数毫米级尺寸的接合层的体积相比，支撑件的尺寸很小，使得支撑件在接合时对接合层的工艺影响很小，也不会妨碍在接合层上所形成的气泡从接合材料中逸出，避免了接合层的空洞率过高，从而，对接合层的接合影响较小，避免由于至少一个支撑件的尺寸过大而降低被接合件的接合效果，使得被接合件能够与其他部件可靠接合。
也就是说，该被接合件可以包括一个待接合面，也可以包括多个待接合面，具体数量可以结合实际接合情况进行设置。
当该被接合件包括一个待接合面时，该待接合面上可以设置一个支撑件，该支撑件的高度与接合层的厚度相同，该接合层由该支撑件与接合材料形成，且该支撑件的熔点高于形成接合层的最高温度。
当该被接合件包括一个待接合面时，该待接合面上可以设置多个支撑件，每个支撑件的高度均与接合层的厚度保持相同，该接合层由各个支撑件与接合材料形成，且每个支撑件的熔点均高于形成该接合层的最高温度。其中，各个支撑件的熔点可以相同或者不同，只需满足各个支撑件中支撑件的最低熔点高于形成该接合层的最高温度即可。
当该被接合件包括多个待接合面时，每个待接合面上可以设置一个支撑件，任意一个待接合面上的支撑件的厚度与接合层的高度保持相同，该接合层由该支撑件与接合材料形成，且该支撑件的熔点高于形成该接合层的最高温度。
当该被接合件包括多个待接合面时，每个待接合面上可以设置多个支撑件，同一个待接合面上的每个支撑件的厚度均与接合层的高度保持相同，该接合层由该待接合面上的各个支撑件与接合材料形成，且每个支撑件的熔点均高于形成该接合层的最高 温度，各个支撑件的熔点可以相同或者不同，只需满足各个支撑件中支撑件的最低熔点高于形成接合层的最高温度即可。
本申请中，本申请对接合材料的具体类型不做限定。可选地，在接合层的类型包括焊接层的情况下，接合材料可以包括：焊片或者焊膏。在接合层的类型为烧结层的情况下，接合材料可以包括：粉状物料或者膏状物料。在接合层的类型包括焊接层和烧结层的情况下，焊接层中，接合材料可以包括：焊片或者焊膏。在烧结层中，接合材料可以包括：粉状物料或者膏状物料。
本申请中，不同的接合层中的支撑件的形状可以相同或者不同。同一接合层中的多个支撑件的形状可以相同或者不同。其中，本申请对支撑件的形状不做限定。可选地，支撑件的形状包括：球状、长方体状、椭球状、楔形状或者蚕状中的至少一个。
本申请中，不同的接合层中的支撑件的材料可以相同或者不同。和/或，同一接合层中的多个支撑件的材料可以相同或者不同。其中，本申请对支撑件的材料不做限定。可选地，支撑件为单金属材料、合金材料、复合材料或者不导电材料中的任意一种。例如，单金属材料可以包括：铝Al、金Au、铜Cu或者镍Ni。合金材料可以包括：铝Al、金Au、铜Cu或者镍Ni中的至少两种。可选地，支撑件可以为包覆材料、涂层材料、带材材料、线材材料中的任意一种。例如，金属涂层或异种金属包覆。从而使得电子装置的制作成本降低。
本申请中，不同的接合层中的支撑件的高度可以相同或者不同。其中，支撑件的高度可以根据对应的接合层的厚度进行设置，其高度的具体数值不做限定。
本申请中，不同的接合层中的支撑件的数量可以相同或者不同。其中，本申请对支撑件的数量不做限定。且任意一个的接合层中的支撑件的数量也不做限定。从而使得接合层中的支撑件的数量可调。一般情况下，支撑件的数量可以大于等于3个，有利于进一步提升接合层的接合效果，且可以确保被接合件的支撑平衡。
本申请中，不同的接合层中的支撑件的位置可以相同或者不同。其中，本申请对支撑件的位置不做限定。且任意一个的接合层中的支撑件的位置也不做限定。从而使得支撑件在接合层中的位置自由，以便在需要的位置处植入所需尺寸的支撑件即可。
另外，本申请对支撑件固定在被接合件的待接合面上的方式不做限定。可选地，支撑件通过如下任意一种方式进行固定设置：超音波、烧结、电镀或者钎焊。
本申请中，为了避免在接合时支撑件被接合材料熔融而焊料移动到接合层之外，因此，支撑件可以固定设置。进一步地，由于支撑件对接合层的接合影响较小，因此，支撑件的设置位置可以包括多种，且操作方便快捷，生成效率高。其中，本申请对待接合件的具体类型不做限定。可选地，被接合件的类型包括：芯片、互联柱、绝缘基板、电阻、电容、电感、传感器、端子或者散热板中的至少一种。
基于上述描述，在该被接合件的任意一个待接合面与其他部件实现接合的过程中，由于在该被接合件的待接合面上设置有微米级尺寸的支撑件，支撑件的高度与接合层的厚度相同以及支撑件的熔点高于形成接合层的最高温度，因此，支撑件不会完全溶解在接合层中的接合材料中，使得支撑件的厚度仍与接合层的厚度保持相同，以便通过支撑件形成具有与支撑件的高度相同的接合层。并且，在电子装置需要多次回流的情况下，支撑件不会随着接合材料的移动而发生移动，使得支撑件在接合层中分布均 匀，且基于支撑件的支撑作用，使得接合层能够经受得住挤压而不变形，也使得即使支撑件出现重融也不会导致接合层中的接合材料发生溢出，确保了接合层良好的质量和接合强度，避免了被接合件下的接合材料不足而导致电子装置的电气短路或者失效等现象，从而确保了接合层的表面平整且厚度均匀，满足了对接合层的厚度和翘曲度的工艺要求。同时，还使得接合层中的接合材料不再受到种类的限制，为接合层的制作提供了多种可能性，有利于降低接合层的制作成本。由此，提高了电子装置的可靠性，且降低了电子装置的制作成本。
其中，本申请对电子装置的具体类型不做限定。可选地，电子装置可以包括：3D立体封装模块，如半导体功率模块、印刷电路板PCB的叠层模块等。
本申请提供的电子装置，通过至少一个被接合结构包括：被接合件和微米级尺寸的至少一个支撑件，至少一个支撑件设置在被接合件的至少一个待接合面上。针对被接合件的任意一个待接合面上的支撑件，支撑件的高度与接合层的厚度相同，支撑件与接合材料形成接合层，且支撑件的熔点高于形成接合层的最高温度，以使接合层的表面平整且厚度均匀。从而，在被接合件实现接合的过程中，由于在该被接合件的待接合面上设置有微米级尺寸的支撑件，支撑件的高度与接合层的厚度相同以及支撑件的熔点高于形成接合层的最高温度，因此，支撑件不会完全溶解在接合层中的接合材料中，使得支撑件的厚度仍与接合层的厚度保持相同，以便通过支撑件形成具有与支撑件的高度相同的接合层。并且，在电子装置需要多次回流的情况下，支撑件不会随着接合材料的移动而发生移动，使得支撑件在接合层中分布均匀，且基于支撑件的支撑作用，使得接合层能够经受得住挤压而不变形，也使得即使支撑件出现重融也不会导致接合层中的接合材料发生溢出，确保了接合层良好的质量和接合强度，避免了被接合件下的接合材料不足而导致电子装置的电气短路或者失效等现象，从而确保了接合层的表面平整且厚度均匀，满足了对接合层的厚度和翘曲度的工艺要求。同时，还使得接合层中的接合材料不再受到种类的限制，为接合层的制作提供了多种可能性，有利于降低接合层的制作成本。由此，提高了电子装置的可靠性，且降低了电子装置的制作成本。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (25)

  1. 一种封装结构，其特征在于，包括：第一基板、第一接合层、电子元件、第二接合层以及第二基板；
    所述第一接合层位于所述第一基板的第一导电面和所述电子元件的第一接合面之间，所述第一接合层用于实现所述电子元件与所述第一基板的接合；
    所述第一接合层包括：第一接合材料和至少一个第一支撑件，所述至少一个第一支撑件的高度与所述第一接合层的厚度相同，且所述至少一个第一支撑件的熔点高于形成所述第一接合层的最高温度，以使所述第一接合层的表面平整且厚度均匀；
    所述第二接合层位于所述电子元件的第二接合面和所述第二基板的第一导电面之间，所述第二接合层用于实现所述电子元件与所述第二基板的接合，所述电子元件的第一接合面与所述电子元件的第二接合面相对。
  2. 根据权利要求1所述的封装结构，其特征在于，
    所述第二接合层包括：第二接合材料和至少一个第二支撑件，所述至少一个第二支撑件的高度与所述第二接合层的厚度相同，且所述至少一个第二支撑件的熔点高于形成所述第二接合层的最高温度，以使所述第二接合层的表面平整且厚度均匀。
  3. 根据权利要求2所述的封装结构，其特征在于，
    所述至少一个第二支撑件固定设置在所述电子元件的第二接合面或者所述第二基板的第一导电面上。
  4. 根据权利要求1-3任一项所述的封装结构，其特征在于，所述封装结构还包括：塑封材料；所述第一基板、所述第一接合层、所述电子元件的部分、所述第二接合层以及所述第二基板均设置在所述塑封材料中。
  5. 根据权利要求1-4任一项所述的封装结构，其特征在于，
    所述至少一个第一支撑件固定设置在所述电子元件的第一接合面或者所述第一基板的第一导电面上。
  6. 根据权利要求1-5任一项所述的封装结构，其特征在于，
    若包括多个不连接的第一接合层和多个不连接的第二接合层，则所述电子元件包括：芯片、第三接合层、互联柱、信号端子和功率端子；
    所述芯片位于除与所述信号端子对应的第一接合层和所述功率端子对应的第一接合层之外的第一接合层和所述第三接合层之间，所述互联柱位于与所述芯片对应的第三接合层和对应的第二接合层之间；
    所述信号端子从所述封装结构的内部向所述封装结构的外部延伸设置，位于所述封装结构的内部的信号端子的一端位于除与所述芯片对应的第一接合层和所述功率端子对应的第一接合层之外的第一接合层上，所述信号端子与所述芯片电连接，所述芯片对应的第一接合层和所述信号端子对应的第一接合层各自对应于所述第一基板的第一导电面中的不同导电区域；
    所述功率端子从所述封装结构的内部向所述封装结构的外部延伸设置，位于所述封装结构的内部的功率端子的一端位于除与所述芯片对应的第一接合层和所述信号端子对应的第一接合层之外的第一接合层上，所述芯片对应的第一接合层和所述功率端子对应的第一接合层各自对应于所述第一基板的第一导电面中的同一导电区域；和/ 或，所述功率端子位于除所述互联柱对应的第二接合层之外的第二接合层上，所述互联柱对应的第二接合层和所述功率端子对应的第二接合层各自对应于所述第二基板的第一导电面中的同一导电区域；
    所述第三接合层包括：第三接合材料和至少一个第三支撑件，所述至少一个第三支撑件的高度与所述第三接合层的厚度相同，且所述至少一个第三支撑件的熔点高于形成所述第三接合层的最高温度，以使所述第三接合层的表面平整且厚度均匀。
  7. 根据权利要求6所述的封装结构，其特征在于，
    所述至少一个第三支撑件固定设置在所述芯片上靠近所述互联柱的一面或者所述互联柱上靠近所述芯片的一面上。
  8. 根据权利要求1-5任一项所述的封装结构，其特征在于，
    若包括多个不连接的第一接合层和多个不连接的第二接合层，则所述电子元件包括：芯片、信号端子和功率端子；
    所述芯片位于除与所述信号端子对应的第一接合层和所述功率端子对应的第一接合层之外的第一接合层与对应的第二接合层之间；
    所述信号端子从所述封装结构的内部向所述封装结构的外部延伸设置，位于所述封装结构的内部的信号端子的一端位于除与所述芯片对应的第一接合层和所述功率端子对应的第一接合层之外的第一接合层上，第一接合层中包括有第一接合材料和固定设置在第一基板的第一导电面上的第一支撑件，所述信号端子与所述芯片电连接，所述芯片对应的第一接合层和所述信号端子对应的第一接合层各自对应于所述第一基板的第一导电面中的不同导电区域；
    所述功率端子从所述封装结构的内部向所述封装结构的外部延伸设置，位于所述封装结构的内部的功率端子的一端位于除与所述芯片对应的第一接合层和所述信号端子对应的第一接合层之外的第一接合层上，第一接合层中包括有第一接合材料和固定设置在第一基板的第一导电面上的第一支撑件，所述芯片对应的第一接合层和所述功率端子对应的第一接合层各自对应于所述第一基板的第一导电面中的同一导电区域；和/或，所述功率端子位于除所述芯片对应的第二接合层之外的第二接合层上，第二接合层中包括有第二接合材料和固定设置在第二基板的第一导电面上的第二支撑件，所述芯片对应的第二接合层和所述功率端子对应的第二接合层各自对应于所述第二基板的第一导电面中的同一导电区域。
  9. 根据权利要求6-8任一项所述的封装结构，其特征在于，所述电子元件还包括：传感器；
    所述传感器的两端分别位于除与所述芯片对应的第一接合层、所述信号端子对应的第一接合层和所述功率端子对应的第一接合层之外的第一接合层上，第一接合层中包括有第一接合材料和固定设置在第一基板的第一导电面上的第一支撑件，所述芯片对应的第一接合层和所述传感器对应的两个第一接合层各自对应于所述第一基板的第一导电面中的不同导电区域；和/或，
    所述传感器的一端位于除与所述芯片对应的第一接合层、所述信号端子对应的第一接合层和所述功率端子对应的第一接合层之外的第一接合层上，第一接合层中包括有第一接合材料和固定设置在第一基板的第一导电面上的第一支撑件，所述传感器的 另一端通过传输导线从所述封装结构的内部向所述封装结构的外部延伸设置，所述芯片对应的第一接合层和所述传感器对应的第一接合层各自对应于所述第一基板的第一导电面中的不同导电区域。
  10. 根据权利要求1-9任一项所述的封装结构，其特征在于，所述封装结构还包括：第一散热件和第四接合层；
    所述第四接合层位于所述第一基板的第二导电面与所述第一散热件之间，所述第一基板的第二导电面暴露在所述封装结构的外部，所述第四接合层用于实现所述第一基板与所述第一散热件之间的接合；
    所述第四接合层包括：第四接合材料和至少一个第四支撑件，所述至少一个第四支撑件的高度与所述第四接合层的厚度相同，且所述至少一个第四支撑件的熔点高于形成所述第四接合层的最高温度，以使所述第四接合层的表面平整且厚度均匀。
  11. 根据权利要求10所述的封装结构，其特征在于，
    所述至少一个第四支撑件固定设置在所述第一基板的第二导电面或者所述第一散热件上靠近所述第一基板的一面上。
  12. 根据权利要求1-11任一项所述的封装结构，其特征在于，所述封装结构还包括：第二散热件和第五接合层；
    所述第五接合层位于所述第二基板的第二导电面与所述第二散热件之间，所述第二基板的第二导电面暴露在所述封装结构的外部，所述第五接合层用于实现所述第二基板与所述第二散热件之间的接合；
    所述第五接合层包括：第五接合材料和至少一个第五支撑件，所述至少一个第五支撑件的高度与所述第五接合层的厚度相同，且所述至少一个第五支撑件的熔点高于形成所述第五接合层的最高温度，以使所述第五接合层的表面平整且厚度均匀。
  13. 根据权利要求12所述的封装结构，其特征在于，
    所述至少一个第五支撑件固定设置在所述第二基板的第二导电面或者所述第二散热件上靠近所述第二基板的一面上。
  14. 根据权利要求1-13任一项所述的封装结构，其特征在于，
    不同的接合层中的支撑件的形状相同或者不同；和/或
    同一接合层中的多个支撑件的形状相同或者不同。
  15. 根据权利要求14所述的封装结构，其特征在于，支撑件的形状包括：球状、长方体状、椭球状、楔形状或者蚕状中的至少一个。
  16. 根据权利要求1-15任一项所述的封装结构，其特征在于，
    不同的接合层中的支撑件的材料相同或者不同；和/或，
    同一接合层中的多个支撑件的材料相同或者不同。
  17. 根据权利要求16所述的封装结构，其特征在于，支撑件为单金属材料、合金材料、复合材料或者不导电材料中的任意一种。
  18. 根据权利要求16所述的封装结构，其特征在于，所述支撑件为包覆材料、涂层材料、带材材料、线材材料中的任意一种。
  19. 根据权利要求1-18任一项所述的封装结构，其特征在于，
    不同的接合层中的支撑件的高度相同或者不同。
  20. 根据权利要求1-19任一项所述的封装结构，其特征在于，
    不同的接合层中的支撑件的数量相同或者不同。
  21. 根据权利要求1-20任一项所述的封装结构，其特征在于，支撑件通过如下任意一种方式进行固定设置：超音波、烧结、电镀或者钎焊。
  22. 根据权利要求1-21任一项所述的封装结构，其特征在于，在接合层的类型包括焊接层的情况下，接合材料包括：焊片或者焊膏；和/或，在接合层的类型为烧结层的情况下，接合材料包括：粉状物料或者膏状物料。
  23. 一种电动车辆，其特征在于，包括：供电电池、电机控制单元MCU以及Q个电机，Q为正整数；
    所述电机控制单元MCU包括3R个如权利要求1-22任一项所述的封装结构，R为正整数，所述供电电池向每个封装结构均提供第一电能，每个电机对应连接至少三个封装结构；
    针对所述3R个封装结构中的任意一个封装结构，所述电机控制单元MCU，用于控制所述封装结构将所述第一电能转换为与所述封装结构对应连接的电机所需的第二电能，并控制所述封装结构将所述第二电能传输至与所述封装结构对应连接的电机。
  24. 一种电子装置，其特征在于，包括：至少一个被接合结构，所述至少一个被接合结构包括：被接合件和微米级尺寸的至少一个支撑件；
    所述至少一个支撑件设置在所述被接合件的至少一个待接合面上；
    针对所述被接合件的任意一个待接合面上的支撑件，所述支撑件的高度与接合层的厚度相同，所述支撑件与接合材料形成所述接合层，且所述支撑件的熔点高于形成所述接合层的最高温度，以使所述接合层的表面平整且厚度均匀。
  25. 根据权利要求24所述的电子装置，其特征在于，所述电子装置包括：3D立体封装模块。
PCT/CN2020/085092 2020-04-16 2020-04-16 封装结构、电动车辆和电子装置 WO2021208006A1 (zh)

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