WO2021205926A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2021205926A1
WO2021205926A1 PCT/JP2021/013300 JP2021013300W WO2021205926A1 WO 2021205926 A1 WO2021205926 A1 WO 2021205926A1 JP 2021013300 W JP2021013300 W JP 2021013300W WO 2021205926 A1 WO2021205926 A1 WO 2021205926A1
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WO
WIPO (PCT)
Prior art keywords
insulating layer
external terminal
semiconductor element
semiconductor device
connection wiring
Prior art date
Application number
PCT/JP2021/013300
Other languages
French (fr)
Japanese (ja)
Inventor
小鵬 呉
和則 富士
Original Assignee
ローム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ローム株式会社 filed Critical ローム株式会社
Priority to DE212021000110.6U priority Critical patent/DE212021000110U1/en
Priority to DE112021000937.0T priority patent/DE112021000937T5/en
Priority to JP2022514419A priority patent/JPWO2021205926A1/ja
Priority to CN202180024850.3A priority patent/CN115335992A/en
Priority to US17/915,975 priority patent/US20230163069A1/en
Publication of WO2021205926A1 publication Critical patent/WO2021205926A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Definitions

  • This disclosure relates to a Fan-Out type semiconductor device.
  • the semiconductor device includes a semiconductor element having a plurality of electrodes, an insulating layer in contact with the semiconductor element, a plurality of connection wirings arranged in the insulating layer and connected to the plurality of electrodes, and the semiconductor element in contact with the insulating layer. It is provided with a sealing resin that partially covers it. In the thickness direction, the plurality of connection wirings include a portion located outside the semiconductor element. This has the advantage that the shape of the wiring pattern of the wiring board on which the semiconductor device is mounted can be flexibly adapted while reducing the size of the semiconductor device.
  • Patent Document 1 discloses an example of a Fan-Out type semiconductor device.
  • the semiconductor device is formed inside a semiconductor element having a plurality of electrodes on the main surface, an insulating layer in contact with the main surface of the semiconductor element, a sealing resin in contact with the insulating layer and covering a part of the semiconductor element, and an insulating layer. It is provided with a plurality of connecting wires including a portion located outside the semiconductor element in the thickness direction.
  • the semiconductor element is covered with an insulating layer and a sealing resin. Since the semiconductor device does not include an interposer or a printed wiring board, it can be made thinner.
  • a semiconductor device that constitutes a bridge circuit in which two switching elements are connected in series is required for use in a converter or an inverter.
  • the semiconductor device is realized by a Fan-Out type semiconductor device, two semiconductor elements, which are switching elements, are arranged in a direction orthogonal to the thickness direction, and the source electrode of one semiconductor element is the other semiconductor element.
  • the drain electrode of one of the semiconductor elements is made conductive to an external terminal to which a DC voltage is applied from the outside.
  • the source electrode of the other semiconductor element is made conductive to an external terminal connected to the ground.
  • it is required to suppress the inductance of the current path inside the semiconductor device in order to suppress the surge voltage generated when the semiconductor element is switched to the ON state.
  • one object of the present disclosure is to provide a semiconductor device capable of suppressing the inductance of the internal current path.
  • the semiconductor device provided by the first aspect of the present disclosure has an element main surface and an element back surface facing opposite sides in the thickness direction, and a plurality of main surface electrodes arranged on the element main surface, respectively. Then, the first semiconductor element and the second semiconductor element arranged side by side in the first direction orthogonal to the thickness direction, and the back surface of the insulating layer that covers the main surface of each element and faces the main surface of each element.
  • An insulating layer having an insulating layer main surface facing away from the back surface of the insulating layer in the thickness direction, a resin main surface in contact with the back surface of the insulating layer, and the resin main surface in the thickness direction.
  • the first external terminal and the second external terminal each of which is arranged and exposed from the back surface of the resin, and the main surface electrode of any one of the first semiconductor elements and the first external terminal, which are arranged in the insulating layer, are electrically connected to each other. It is provided with a first connection wiring to be made to be connected, and a second connection wiring arranged on the insulating layer to conduct the main surface electrode of any one of the second semiconductor elements and the second external terminal.
  • the generated area) can be reduced, and the inductance of the current path can be suppressed.
  • FIG. 1 It is a top view which shows the semiconductor device which concerns on 1st Embodiment of this disclosure, and is the figure which transmitted through the 3rd insulating layer. It is a top view which shows the semiconductor device of FIG. 1, and is also the figure which transmitted through the 2nd insulation layer and the 3rd connection wiring. It is a top view which shows the semiconductor device of FIG. 1, and is also the figure which transmitted through the 1st insulation layer and all the connection wirings. It is a bottom view which shows the semiconductor device of FIG. It is sectional drawing which follows the VV line of FIG. It is sectional drawing which follows the VI-VI line of FIG. It is a partially enlarged view of FIG. It is sectional drawing which shows one process of an example of the manufacturing method of the semiconductor device of FIG.
  • something A is formed on a certain thing B
  • something A is formed on a certain thing B
  • something B means “there is a certain thing A” unless otherwise specified. It includes “being formed directly on the object B” and “being formed on the object B with the object A while interposing another object between the object A and the object B”.
  • something A is placed on something B” and “something A is placed on something B” means “something A is placed on something B” unless otherwise specified. It includes "being placed directly on B” and “being placed on a certain thing B while having another thing intervening between a certain thing A and a certain thing B".
  • something A is located on something B
  • something A is in contact with something B and some thing A is on something B” unless otherwise specified.
  • What you are doing and "The thing A is located on the thing B while another thing is intervening between the thing A and the thing B”.
  • something A overlaps with a certain thing B when viewed in a certain direction means “something A overlaps with all of a certain thing B” and “something A overlaps” unless otherwise specified. "Overlapping a part of a certain object B" is included.
  • the semiconductor device A1 of the present embodiment includes an insulating layer 1, a plurality of connection wirings 2, two semiconductor elements 3, a sealing resin 4, two heat spreaders 5, and a plurality of external terminals 6.
  • the insulating layer 1 includes a first insulating layer 11, a second insulating layer 12, and a third insulating layer 13.
  • the connection wiring 2 includes a first connection wiring 21, a second connection wiring 22, a third connection wiring 23, a connection wiring 26, and a connection wiring 27.
  • the semiconductor device A1 is a Fan-Out type that is surface-mounted on a wiring board.
  • FIG. 1 is a plan view showing the semiconductor device A1 and is a view that has passed through the third insulating layer 13.
  • FIG. 2 is a plan view showing the semiconductor device A1, and is a view through which the second insulating layer 12 and the third connecting wiring 23 are transmitted.
  • FIG. 3 is a plan view showing the semiconductor device A1, and is a view through which the first insulating layer 11 and all the connecting wirings 2 are transmitted.
  • FIG. 4 is a bottom view showing the semiconductor device A1.
  • FIG. 5 is a cross-sectional view taken along the line VV of FIG.
  • FIG. 6 is a cross-sectional view taken along the line VI-VI of FIG.
  • FIG. 7 is a partially enlarged view of FIG.
  • the semiconductor device A1 has a plate shape and a rectangular shape in the thickness direction (plan view).
  • the thickness direction (plan view direction) of the semiconductor device A1 is the z direction
  • the direction along one side of the semiconductor device A1 orthogonal to the z direction is the x direction.
  • the direction orthogonal to the z direction and the x direction is defined as the y direction.
  • the z direction is an example of the "thickness direction”.
  • the x direction is an example of the "first direction”.
  • the size of the semiconductor device A1 is not particularly limited.
  • the semiconductor element 3 is an element that exerts an electrical function of the semiconductor device A1.
  • the semiconductor device A1 includes two semiconductor elements 3.
  • the semiconductor element 3 is a high electron mobility transistor (HEMT) having an electron traveling layer made of a nitride semiconductor, and gallium nitride (GaN) is used in the present embodiment.
  • HEMT high electron mobility transistor
  • GaN gallium nitride
  • Each semiconductor element 3 has a rectangular plate shape in the z-direction, and includes an element main surface 3a, an element back surface 3b, a plurality of input electrodes 31, a plurality of output electrodes 32, and a control electrode 33.
  • the element main surface 3a and the element back surface 3b face opposite to each other in the z direction.
  • an input electrode 31, an output electrode 32, and a control electrode 33 are arranged on the element main surface 3a.
  • the input electrode 31 is, for example, a drain electrode.
  • the output electrode 32 is, for example, a source electrode.
  • the control electrode 33 is, for example, a gate electrode.
  • the semiconductor element 301 and the semiconductor element 302 are arranged side by side in the x direction at substantially the center of the semiconductor device A1 in the y direction in the z direction.
  • the semiconductor element 301 is arranged on the right side of FIG. 3
  • the semiconductor element 302 is arranged on the left side of FIG.
  • the type and arrangement position of the semiconductor element 3 are not particularly limited.
  • the heat spreader 5 has a rectangular plate shape in the z-direction, and is a member for radiating the heat generated by the semiconductor element 3 to the wiring substrate on which the semiconductor device A1 is mounted.
  • the semiconductor device A1 includes two heat spreaders 5 according to the number of semiconductor elements 3.
  • One heat spreader 5 is bonded to the semiconductor element 301, and the other heat spreader 5 is bonded to the semiconductor element 302.
  • Each heat spreader 5 is made of a material having high thermal conductivity, and in this embodiment, is made of Cu.
  • the material of the heat spreader 5 is not limited, and may be another metal such as Al, ceramic or the like.
  • Each heat spreader 5 includes a spreader main surface 5a and a spreader back surface 5b.
  • the spreader main surface 5a and the spreader back surface 5b face each other in the z direction.
  • the heat spreader 5 is joined to the element back surface 3b of the semiconductor element 3 with the spreader main surface 5a facing the semiconductor element 3.
  • the dimensions of the heat spreader 5 in the x-direction and the y-direction match the dimensions of the semiconductor element 3, but the present disclosure is not limited to this.
  • the back surface 5b of the spreader of the heat spreader 5 is exposed from the sealing resin 4.
  • the spreader back surface 5b is joined to the wiring board by a joining member such as solder. As a result, the heat spreader 5 releases the heat generated by the semiconductor element 3 to the wiring board.
  • the sealing resin 4 covers a part of each of the semiconductor element 3 and the heat spreader 5.
  • the sealing resin 4 is made of a material containing, for example, a black epoxy resin.
  • the sealing resin 4 includes a resin main surface 4a, a resin back surface 4b, and a resin opening 4c.
  • the resin main surface 4a and the resin back surface 4b face each other in the z direction.
  • the resin main surface 4a is flush with the element main surface 3a of the semiconductor element 3 and is in contact with the insulating layer 1.
  • the input electrode 31, the output electrode 32, and the control electrode 33 may be exposed from the sealing resin 4, and a part of the element main surface 3a may be covered with the sealing resin 4.
  • the resin back surface 4b is a surface facing the wiring board when the semiconductor device A1 is mounted on the wiring board.
  • the resin opening 4c is an opening formed on the resin back surface 4b side and overlaps with the semiconductor element 3 in the z-direction view.
  • the back surface 5b of the spreader of the heat spreader 5 is exposed from the resin opening 4c, and the back surface 4b of the resin and the back surface 5b of the spreader are flush with each other.
  • the back surface 5b of the spreader may be partially exposed from the back surface 4b of the resin, and may be partially covered with the sealing resin 4.
  • the plurality of external terminals 6 are made of a conductor, and in this embodiment, are made of Cu.
  • the external terminal 6 includes a first external terminal 61, a second external terminal 62, a third external terminal 63, a fourth external terminal 64, and a fifth external terminal 65. Is done.
  • the first external terminal 61, the second external terminal 62, and the third external terminal 63 each have a plate shape with the x direction as the thickness direction and a rectangular shape in the thickness direction (x direction view).
  • the first external terminal 61, the second external terminal 62, and the third external terminal 63 are arranged at equal intervals between the semiconductor element 301 and the semiconductor element 302 in the z-direction view.
  • the first external terminal 61 is arranged adjacent to and separated from the semiconductor element 301.
  • the third external terminal 63 is arranged adjacent to and separated from the semiconductor element 302.
  • the second external terminal 62 is arranged apart from the first external terminal 61 and the second external terminal 62.
  • the first external terminal 61 conducts to the input electrode 31 of the semiconductor element 301.
  • the second external terminal 62 conducts to the output electrode 32 of the semiconductor element 302.
  • the third external terminal 63 conducts to the output electrode 32 of the semiconductor element 301 and the input electrode 31 of the semiconductor element 302.
  • the external terminals 6 other than the first external terminal 61, the second external terminal 62, and the third external terminal 63 each have a rectangular parallelepiped shape, and one end of the semiconductor device A1 in the y direction (FIG. 3). (See), they are arranged side by side at equal intervals in the x direction, and are separated from each other.
  • the fourth external terminal 64 is an external terminal 6 arranged at the right end in FIG. 3, and is conductive to the control electrode 33 of the semiconductor element 301.
  • the fifth external terminal 65 is the fourth external terminal 6 arranged from the right side in FIG. 3, and is conductive to the control electrode 33 of the semiconductor element 302.
  • the number, shape, and arrangement position of the external terminals 6 other than the first external terminal 61, the second external terminal 62, and the third external terminal 63 are not particularly limited.
  • each external terminal 6 is covered with the sealing resin 4. As shown in FIGS. 5 and 6, one surface of each external terminal 6 in the z direction is exposed from the resin main surface 4a of the sealing resin 4. One of the surfaces is connected to the semiconductor element 3 or the like via the connection wiring 2. Further, as shown in FIGS. 5 and 6, the other surface of each external terminal 6 in the z direction is exposed from the resin back surface 4b of the sealing resin 4. When the semiconductor device A1 is mounted on the wiring board, the other surface is joined to the wiring of the wiring board by a joining member such as solder.
  • a metal layer in which a nickel (Ni) layer, a palladium layer (Pd), and a gold (Au) layer are laminated in this order may be formed, and a bump portion made of a material containing tin (Sn) may be formed. May be formed.
  • the first external terminal 61 is connected to the input electrode 31 (drain electrode) of the semiconductor element 301 via the first connection wiring 21 (see FIGS. 2 and 5), and is a Vin terminal to which a DC voltage is applied from the outside.
  • the second external terminal 62 is connected to the output electrode 32 (source electrode) of the semiconductor element 302 via the second connection wiring 22 (see FIGS. 2 and 6), and functions as a PGND terminal connected to the ground. ..
  • the third external terminal 63 is connected to the output electrode 32 (source electrode) of the semiconductor element 301 and the input electrode 31 (drain electrode) of the semiconductor element 302 via the third connection wiring 23 (FIGS. 1 and 5). And FIG. 6), it functions as a SW terminal that outputs a switching signal.
  • the fourth external terminal 64 is connected to the control electrode 33 (gate electrode) of the semiconductor element 301 via the connection wiring 26 (see FIG. 2), and functions as a signal terminal for inputting a drive signal to the semiconductor element 301. do.
  • the fifth external terminal 65 is connected to the control electrode 33 (gate electrode) of the semiconductor element 302 via the connection wiring 27 (see FIG. 2), and functions as a signal terminal for inputting a drive signal to the semiconductor element 302. do.
  • the insulating layer 1 is in contact with the element main surface 3a of each semiconductor element 3 and the resin main surface 4a of the sealing resin 4.
  • the insulating layer 1 is made of a material containing a thermosetting synthetic resin and an additive containing a metal element that constitutes a part of a plurality of connecting wirings 2.
  • the synthetic resin is, for example, an epoxy resin or a polyimide resin.
  • the insulating layer 1 has an insulating layer main surface 1a and an insulating layer back surface 1b. The main surface 1a of the insulating layer and the back surface 1b of the insulating layer face opposite to each other in the z direction.
  • the back surface 1b of the insulating layer is in contact with the element main surface 3a of each semiconductor element 3 and the resin main surface 4a of the sealing resin 4 facing each other, and the element main surface 3a of each semiconductor element 3 and the resin main surface of the sealing resin 4 are in contact with each other. It covers the surface 4a.
  • the back surface 1b of the insulating layer does not have to be in contact with the element main surface 3a of each semiconductor element 3.
  • the insulating layer 1 includes a first insulating layer 11, a second insulating layer 12, and a third insulating layer 13. As shown in FIGS. 5 and 6, the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13 are laminated on the sealing resin 4 in this order.
  • the first insulating layer 11 is in contact with the element main surface 3a of each semiconductor element 3 and the resin main surface 4a of the sealing resin 4, and includes the back surface 1b of the insulating layer.
  • the second insulating layer 12 is in contact with the first insulating layer 11.
  • the third insulating layer 13 is in contact with the second insulating layer 12 and includes the main surface 1a of the insulating layer.
  • the plurality of connection wirings 2 are conductors that connect each external terminal 6 and each semiconductor element 3, and form a conductive path for supplying electric power to the semiconductor element 3 and inputting / outputting signals. As shown in FIGS. 5 and 6, the plurality of connection wirings 2 are arranged inside the insulating layer 1.
  • the first connection wiring 21 includes an embedded portion 211 and a rewiring portion 212.
  • the embedded portion 211 is entirely embedded in the first insulating layer 11.
  • the side surface of the embedded portion 211 is inclined with respect to the z direction, and a taper is formed in which the area of the cross section of the embedded portion 211 orthogonal to the z direction becomes smaller as it approaches the back surface 1b of the insulating layer.
  • the rewiring portion 212 is arranged between the first insulating layer 11 and the second insulating layer 12. The rewiring portion 212 is connected to the embedded portion 211. As shown in FIG.
  • the rewiring portion 212 has a comb-teeth shape that avoids the output electrode 32 of the semiconductor element 301 in the z-direction view.
  • the shape is a shape for forming the embedded portion 231 of the third connection wiring 23, which will be described later, so as to be connected to the output electrode 32.
  • the rewiring portion 212 may not have a comb-teeth shape but may have a shape in which a through hole for arranging the embedded portion 231 connected to the output electrode 32 is formed.
  • the rewiring portion 212 of the first connection wiring 21 partially overlaps the semiconductor element 301 and is partially located outside the semiconductor element 301 in the z-direction view.
  • each of the embedded portion 211 and the rewiring portion 212 has a base layer 201 and a plating layer 202.
  • the base layer 201 is composed of a metal element contained in the additive contained in the first insulating layer 11, and is in contact with the first insulating layer 11.
  • the plating layer 202 is made of, for example, a material containing copper (Cu) and is in contact with the base layer 201.
  • the base layer 201 of the embedded portion 211 is in contact with the first insulating layer 11.
  • the plating layer 202 of the embedded portion 211 is surrounded by the base layer 201 of the embedded portion 211.
  • the base layer 201 of the rewiring portion 212 is in contact with the first insulating layer 11.
  • the plating layer 202 of the rewiring portion 212 covers the base layer 201 of the rewiring portion 212 and is surrounded by the base layer 201 of the rewiring portion 212 and the second insulating layer 12.
  • the second connection wiring 22 includes an embedded portion 221 and a rewiring portion 222.
  • the embedded portion 221 is entirely embedded in the first insulating layer 11.
  • the shape of the embedded portion 221 is the same as that of the embedded portion 211.
  • the rewiring portion 222 is arranged between the first insulating layer 11 and the second insulating layer 12.
  • the rewiring portion 222 is connected to the embedded portion 221.
  • the rewiring portion 222 has a comb-teeth shape that avoids the input electrode 31 of the semiconductor element 302 in the z-direction view.
  • the shape is a shape for forming the embedded portion 231 of the third connection wiring 23 so as to be connected to the input electrode 31.
  • the rewiring portion 222 may not have a comb-teeth shape but may have a shape in which a through hole for arranging the embedded portion 231 connected to the input electrode 31 is formed. As shown in FIGS. 2, 5, and 6, the rewiring portion 222 includes a plurality of through holes 222a. Each through hole 222a is a hole through which the rewiring portion 222 penetrates in the z direction, and is arranged at a position overlapping the third external terminal 63 in the z direction view. An embedded portion 231 of the third connection wiring 23, which will be described later, is arranged in the through hole 222a.
  • the rewiring portion 222 of the second connection wiring 22 partially overlaps the semiconductor element 302 and is partially located outside the semiconductor element 302 in the z-direction view.
  • Each of the embedded portion 221 and the rewiring portion 222 has a base layer 201 and a plating layer 202, similarly to the embedded portion 211 and the rewiring portion 212.
  • the connection wiring 26 includes an embedded portion 261 and a rewiring portion 262.
  • the entire embedded portion 261 is embedded in the first insulating layer 11.
  • the shape of the embedded portion 261 is the same as that of the embedded portion 211.
  • the rewiring portion 262 is arranged between the first insulating layer 11 and the second insulating layer 12.
  • the rewiring portion 262 is connected to the embedded portion 261.
  • the rewiring portion 262 of the connection wiring 26 partially overlaps the semiconductor element 301 and is partially located outside the semiconductor element 301 in the z-direction view.
  • Each of the embedded portion 261 and the rewiring portion 262 has a base layer 201 and a plating layer 202, similarly to the embedded portion 211 and the rewiring portion 212.
  • the connection wiring 27 includes an embedded portion 271 and a rewiring portion 272.
  • the entire embedded portion 271 is embedded in the first insulating layer 11.
  • the shape of the embedded portion 271 is the same as that of the embedded portion 211.
  • the rewiring portion 272 is arranged between the first insulating layer 11 and the second insulating layer 12.
  • the rewiring portion 272 is connected to the embedded portion 271.
  • the rewiring portion 272 of the connection wiring 27 partially overlaps the semiconductor element 302 and is partially located outside the semiconductor element 302 in the z-direction view.
  • Each of the embedded portion 271 and the rewiring portion 272 has a base layer 201 and a plating layer 202, similarly to the embedded portion 211 and the rewiring portion 212.
  • the third connection wiring 23 includes an embedded portion 231 and a rewiring portion 232. As shown in FIGS. 5 and 6, the embedded portion 231 is entirely embedded through the first insulating layer 11 and the second insulating layer 12. Further, the embedded portion 231 is arranged so as not to overlap the rewiring portion 212 and the rewiring portion 222 in the z-direction view. The embedded portion 231 connected to the third external terminal 63 is arranged inside the through hole 222a of the rewiring portion 222. The embedded portion 231 connected to the output electrode 32 of the semiconductor element 301 is arranged in the gap between the comb teeth of the rewiring portion 212.
  • the embedded portion 231 connected to the input electrode 31 of the semiconductor element 302 is arranged in the gap between the comb teeth of the rewiring portion 222.
  • the shape of the embedded portion 231 is the same as that of the embedded portion 211.
  • the rewiring portion 232 is arranged between the second insulating layer 12 and the third insulating layer 13.
  • the rewiring portion 232 is connected to the embedded portion 231.
  • the rewiring portion 232 has a rectangular shape in the z-direction.
  • the z-direction view shape of the rewiring portion 232 is not particularly limited, and may be a shape that overlaps all the embedded portions 231. As shown in FIG.
  • the rewiring portion 232 of the third connection wiring 23 partially overlaps the semiconductor element 301 and the semiconductor element 302 in the z-direction view, and partly from the semiconductor element 301 and the semiconductor element 302. Is also located on the outside (in this embodiment, between the semiconductor element 301 and the semiconductor element 302).
  • Each of the embedded portion 231 and the rewiring portion 232 has a base layer 201 and a plating layer 202, similarly to the embedded portion 211 and the rewiring portion 212.
  • the semiconductor device A1 is a rewiring portion that overlaps only the semiconductor element 3 in the z-direction view and has no portion located outside the semiconductor element 3, or a rewiring portion located only outside the semiconductor element 3. It may include a wiring part.
  • FIGS. 8 to 18 are diagrams showing one step of an example of a manufacturing method of the semiconductor device A1, respectively.
  • FIG. 13, FIG. 15, FIG. 16, FIG. 18, and FIG. 19 are cross-sectional views, which correspond to FIGS. 5.
  • FIG. 11 is a partially enlarged view of FIG. 10, which corresponds to FIG. 7.
  • FIG. 12 is a plan view and is a view corresponding to FIG.
  • FIG. 14 is a partially enlarged view of FIG. 13, which corresponds to FIG. 7.
  • FIG. 17 is a plan view and is a view corresponding to FIG.
  • the sealing resin 81 is made of a material containing a black epoxy resin.
  • an input electrode 31, an output electrode 32, and a control electrode 33 are arranged on the element main surface 3a, and a heat spreader 5 is bonded to the element back surface 3b.
  • compression molding is performed after arranging the material of the sealing resin 81, the semiconductor element 3 to which the heat spreader 5 is bonded, and the external terminal 6 in the mold. At this time, the input electrode 31, the output electrode 32, the control electrode 33, and the spreader back surface 5b of the heat spreader 5 are exposed from the sealing resin 81.
  • a first insulating layer 82 is formed, which is laminated on the sealing resin 81 and covers the input electrode 31, the output electrode 32, and the control electrode 33 of the semiconductor element 3.
  • the first insulating layer 82 is made of a material containing a thermosetting synthetic resin and an additive containing a metal element that constitutes a part of a plurality of connection wirings 83 (details will be described later).
  • the synthetic resin is, for example, an epoxy resin or a polyimide resin.
  • the first insulating layer 82 is formed by compression molding.
  • each of the plurality of connection wirings 83 has an embedded portion 831 and a rewiring portion 832.
  • the embedded portion 831 is embedded in the first insulating layer 82 and is connected to any of the input electrode 31, the output electrode 32, the control electrode 33, or the external terminal 6.
  • the rewiring portion 832 is arranged on the first insulating layer 82 and is connected to the embedded portion 831.
  • each of the embedded portion 831 and the rewiring portion 832 of the plurality of connecting wirings 83 has a base layer 83A and a plating layer 83B.
  • the step of forming the plurality of connection wirings 83 includes a step of depositing the base layer 83A on the surface of the first insulating layer 82 and a step of forming a plating layer 83B covering the base layer 83A.
  • the base layer 83A is deposited on the surface of the first insulating layer 82.
  • a plurality of holes 821 and a plurality of recesses 822 are formed in the first insulating layer 82 by a laser.
  • the plurality of holes 821 penetrate the first insulating layer 82 in the z direction.
  • the input electrode 31, the output electrode 32, the control electrode 33, and the external terminal 6 are individually exposed from the plurality of holes 821.
  • the plurality of holes 821 have the input electrode 31, the output electrode 32, the control electrode 33, and the external terminal 6 while recognizing the positions of the input electrode 31, the output electrode 32, the control electrode 33, and the external terminal 6 by an infrared camera or the like. Is formed by irradiating the first insulating layer 82 with a laser until the first insulating layer 82 is exposed. The position where the laser is irradiated is corrected one by one based on the position information of the input electrode 31, the output electrode 32, the control electrode 33, and the external terminal 6 obtained by image recognition.
  • the plurality of recesses 822 are recessed from the surface of the first insulating layer 82 and are connected to the plurality of holes 821.
  • the plurality of recesses 822 are formed by irradiating the surface of the first insulating layer 82 with a laser.
  • the laser is, for example, an ultraviolet laser having a wavelength of 355 nm and a beam diameter of 17 ⁇ m.
  • the base layer 83A covering the wall surface defining each of the plurality of holes 821 and the plurality of recesses 822. Is deposited.
  • the base layer 83A is composed of metal elements contained in the additive contained in the first insulating layer 82. The metal element contained in the additive is excited by laser irradiation. As a result, the metal layer containing the metal element is precipitated as the base layer 83A.
  • a plating layer 83B covering the base layer 83A is formed.
  • the plating layer 83B is made of a material containing copper.
  • the plating layer 83B is formed by electroless plating.
  • an embedded portion 831 is formed in each of the plurality of holes 821.
  • a rewiring portion 832 is formed in each of the plurality of recesses 822.
  • a plurality of connection wirings 83 are formed.
  • a second insulating layer 84 is formed which is laminated on the first insulating layer 82 and covers the plurality of connection wirings 83.
  • the second insulating layer 84 is made of the same material as the first insulating layer 82.
  • the second insulating layer 84 is formed by compression molding.
  • connection wiring 85 connected to the input electrode 31, the output electrode 32, or the third external terminal 63 of the semiconductor element 3 is formed.
  • the connection wiring 85 corresponds to the third connection wiring 23 of the semiconductor device A1.
  • the connection wiring 85 has an embedded portion 851 and a rewiring portion 852.
  • the embedded portion 851 is entirely embedded through the first insulating layer 82 and the second insulating layer 84, and is connected to any of the input electrode 31, the output electrode 32, or the third external terminal 63.
  • the rewiring portion 852 is arranged on the second insulating layer 84 and is connected to the embedded portion 851.
  • Each of the embedded portion 851 and the rewiring portion 852 of the connecting wiring 85 has a base layer and a plating layer, similarly to the embedded portion 831 and the rewiring portion 832.
  • the step of forming the connection wiring 85 includes a step of precipitating a base layer on the surface of the second insulating layer 84 and a step of forming a plating layer covering the base layer.
  • a base layer is deposited on the surface of the second insulating layer 84.
  • a plurality of holes 841 and recesses 842 are formed in the second insulating layer 84 by a laser.
  • the plurality of holes 841 penetrate the second insulating layer 84 in the z direction.
  • the input electrode 31, the output electrode 32, and the third external terminal 63 are individually exposed from the plurality of holes 841.
  • the plurality of holes 841 recognize the positions of the input electrode 31, the output electrode 32, and the third external terminal 63 by an infrared camera or the like, and until the input electrode 31, the output electrode 32, and the third external terminal 63 are exposed.
  • the recess 842 is recessed from the surface of the second insulating layer 84 and is connected to a plurality of holes 841.
  • the recess 842 is formed by irradiating the surface of the second insulating layer 84 with a laser.
  • the laser is, for example, an ultraviolet laser having a wavelength of 355 nm and a beam diameter of 17 ⁇ m.
  • the base layer is composed of metal elements contained in the additive contained in the second insulating layer 84.
  • the metal element contained in the additive is excited by laser irradiation. As a result, the metal layer containing the metal element is precipitated as the base layer.
  • the plating layer is made of a material containing copper.
  • the plating layer is formed by electroless plating.
  • an embedded portion 851 is formed in each of the plurality of holes 841.
  • a rewiring portion 852 is formed in the recess 842.
  • a plurality of connection wirings 85 are formed.
  • a third insulating layer 86 is formed which is laminated on the second insulating layer 84 and covers the plurality of connection wirings 85.
  • the third insulating layer 86 is made of the same material as the first insulating layer 82.
  • the third insulating layer 86 is formed by compression molding.
  • the sealing resin 81, the first insulating layer 82, the second insulating layer 84, and the third insulating layer 86 are divided into a plurality of pieces by cutting along a predetermined cutting line with a dicing blade or the like. ..
  • the piece is configured to include two semiconductor elements 3, a plurality of connection wires 83, 85 connected to them, and a plurality of external terminals 6.
  • the sealing resin 81, the first insulating layer 82, the second insulating layer 84, and the third insulating layer 86, which are individually formed by this step, are the sealing resin 4 and the first insulating layer 11 of the semiconductor device A1, respectively. It corresponds to the second insulating layer 12 and the third insulating layer 13. Through the above steps, the semiconductor device A1 is manufactured.
  • FIG. 20 shows the current flow when the semiconductor element 301 is in the ON state and the semiconductor element 302 is in the OFF state.
  • the current input from the first external terminal 61 flows through the first connection wiring 21 and is input to the input electrode 31 of the semiconductor element 301. Then, the current flows from the input electrode 31 to the output electrode 32 in the semiconductor element 301 and is output.
  • the current output from the output electrode 32 of the semiconductor element 301 flows through the third connection wiring 23 and is output from the third external terminal 63.
  • FIG. 21 shows the current flow when the semiconductor element 301 is switched from the state of FIG. 20 to the OFF state. Even if the semiconductor element 301 is switched to the OFF state, the output current from the third external terminal 63 continues due to the inductance of the load, and the current is input from the load to the second external terminal 62.
  • the current input from the second external terminal 62 flows through the second connection wiring 22 and is input to the output electrode 32 of the semiconductor element 302. Then, the current flows through a diode (not shown) connected in antiparallel to the output electrode 32 and the input electrode 31, and is output from the input electrode 31.
  • the current output from the input electrode 31 of the semiconductor element 302 flows through the third connection wiring 23 and is output from the third external terminal 63.
  • the current output from the third external terminal 63 gradually decreases.
  • FIG. 22 shows the current flow after the semiconductor element 302 is switched to the ON state at the timing when the current output from the third external terminal 63 becomes “0” from the state of FIG. 21.
  • the current input from the third external terminal 63 flows through the third connection wiring 23 and is input to the input electrode 31 of the semiconductor element 302. Then, the current flows from the input electrode 31 to the output electrode 32 in the semiconductor element 302 and is output.
  • the current output from the output electrode 32 of the semiconductor element 302 flows through the second connection wiring 22 and is output from the second external terminal 62.
  • FIG. 23 shows the current flow when the semiconductor element 302 is switched from the state of FIG. 22 to the OFF state. Even if the semiconductor element 302 is switched to the OFF state, the input current to the third external terminal 63 continues due to the inductance of the load, and the current is input from the load to the third external terminal 63.
  • the current input from the third external terminal 63 flows through the third connection wiring 23 and is input to the output electrode 32 of the semiconductor element 301. Then, the current flows through a diode (not shown) connected in antiparallel to the output electrode 32 and the input electrode 31, and is output from the input electrode 31.
  • the current output from the input electrode 31 of the semiconductor element 301 flows through the first connection wiring 21 and is output from the first external terminal 61.
  • the current output from the first external terminal 61 gradually decreases. Then, at the timing when the current input to the third external terminal 63 becomes “0”, the semiconductor element 301 is switched to the ON state, and the state shown in FIG. 20 is reached. By repeating the states of FIGS. 20 to 23, a switching signal is output from the third external terminal 63 to the load.
  • the semiconductor device A1 has a first external terminal 61 that conducts to the input electrode 31 of the semiconductor element 301 via the first connection wiring 21, and an output electrode of the semiconductor element 302 via the second connection wiring 22. It is provided with a second external terminal 62 that conducts to 32.
  • the first external terminal 61 and the second external terminal 62 are arranged between the semiconductor element 301 and the semiconductor element 302, and each is exposed from the resin back surface 4b.
  • the semiconductor device A1 is mounted on the wiring board, the first external terminal 61 and the second external terminal 62 are joined to the wiring of the wiring board.
  • the first external terminal 61 functions as a Vin terminal
  • the second external terminal 62 functions as a PGND terminal
  • a DC voltage is applied from the outside between the first external terminal 61 and the second external terminal 62.
  • the current path from the first external terminal 61 to the second external terminal 62 via the first connection wiring 21, the semiconductor element 301, the third connection wiring 23, the semiconductor element 302, and the second connection wiring 22 The loop area (magnetic field generation area) can be reduced. Therefore, the inductance of the current path can be suppressed. By suppressing the inductance of the current path, the electric energy stored in the current path is suppressed, and the surge voltage generated when the semiconductor element 301 or the semiconductor element 302 is switched to the ON state can be suppressed.
  • the first external terminal 61 and the second external terminal 62 are arranged adjacent to each other. Therefore, as compared with the case where the third external terminal 63 is arranged between the first external terminal 61 and the second external terminal 62, from the first external terminal 61, the first connection wiring 21, the semiconductor element 301, The area (magnetic field generation area) of the loop of the current path connected to the second external terminal 62 via the third connection wiring 23, the semiconductor element 302, and the second connection wiring 22 can be made smaller. Therefore, the inductance of the current path can be further suppressed.
  • the third external terminal 63 may be arranged not between the second external terminal 62 and the semiconductor element 302 but between the first external terminal 61 and the semiconductor element 301.
  • the current at the first external terminal 61 is on the resin back surface 4b side (lower in FIG. 20). It flows from the side) to the resin main surface 4a side (upper side in FIG. 20).
  • the third external terminal 63 the current flows from the resin main surface 4a side to the resin back surface 4b side. That is, the direction of the current flowing through the first external terminal 61 and the direction of the current flowing through the third external terminal 63 are opposite to each other in the z direction.
  • the magnetic field generated by the current flowing through the first external terminal 61 and the magnetic field generated by the current flowing through the third external terminal 63 cancel each other out, so that the generated inductance is reduced.
  • the direction of the current flowing through the second external terminal 62 and the direction of the current flowing through the third external terminal 63 are in the z direction. Opposite each other.
  • the magnetic field generated by the current flowing through the second external terminal 62 and the magnetic field generated by the current flowing through the third external terminal 63 cancel each other out, so that the generated inductance is reduced.
  • the first external terminal 61, the second external terminal 62, and the third external terminal 63 each have a plate shape with the x direction as the thickness direction, and overlap each other in a large area in the x direction. ing. Therefore, the effect of reducing the inductance is great because the currents flow in opposite directions in the z direction.
  • the current input from the first external terminal 61 flows through the rewiring portion 212 of the first connection wiring 21 from the first external terminal 61 toward the semiconductor element 301. ..
  • the current output from the semiconductor element 301 flows through the rewiring portion 232 of the third connection wiring 23 from the semiconductor element 301 toward the semiconductor element 302. That is, the direction of the current flowing through the rewiring unit 212 and the direction of the current flowing through the rewiring unit 232 are opposite to each other in the x direction.
  • the magnetic field generated by the current flowing through the rewiring unit 212 and the magnetic field generated by the current flowing through the rewiring unit 232 cancel each other out, so that the generated inductance is reduced.
  • the direction of the current flowing through the rewiring unit 212 and the direction of the current flowing through the rewiring unit 232 are opposite to each other in the x direction, so that the generated inductance is reduced. ..
  • the direction of the current flowing through the rewiring unit 222 and the direction of the current flowing through the rewiring unit 232 are opposite to each other in the x direction.
  • the magnetic field generated by the current flowing through the rewiring unit 222 and the magnetic field generated by the current flowing through the rewiring unit 232 cancel each other out, so that the generated inductance is reduced.
  • the rewiring portion 212 of the first connection wiring 21 and the rewiring portion 232 of the third connection wiring 23 overlap each other in a large area in the z-direction view.
  • both the rewiring portion 222 of the second connection wiring 22 and the rewiring portion 232 of the third connection wiring 23 overlap each other in a large area in the z-direction view. Therefore, the effect of reducing the inductance is great because the currents flow in opposite directions in the x direction.
  • each semiconductor element 3 has a heat spreader 5 bonded to the back surface 3b of the element.
  • the back surface 5b of the spreader of the heat spreader 5 is exposed from the back surface 4b of the resin of the sealing resin 4.
  • the semiconductor device A1 is mounted on a wiring board by an external terminal 6 exposed from the resin back surface 4b.
  • the spreader back surface 5b exposed from the resin back surface 4b is also joined to the wiring board by a joining member such as solder.
  • the semiconductor device A1 can release the heat generated by the semiconductor element 3 to the wiring board via the heat spreader 5. Therefore, the semiconductor device A1 has higher heat dissipation than the conventional semiconductor device in which the semiconductor element 3 is covered with the insulating layer 1 and the sealing resin 4.
  • a heat spreader 5 made of Cu is bonded to each semiconductor element 3. As a result, it is possible to prevent the semiconductor device A1 from warping due to thermal expansion.
  • the first insulating layer 82 or the second insulating layer 84 made of a material containing an additive containing a metal element is irradiated with a laser to irradiate the base layer 83A.
  • Laser irradiation is performed while being corrected one by one based on the position information of each electrode obtained by image recognition. Therefore, even if the semiconductor element 3 or the external terminal 6 is displaced due to the curing shrinkage of the sealing resin 4, the connection wiring 2 is accurately formed according to the actual positions of each electrode and each external terminal 6. be able to. As a result, it is possible to suppress the positional deviation at the joint portion between each electrode and each external terminal 6 and the connection wiring 2.
  • the present invention is not limited to this.
  • the third insulating layer 13 does not have to be a material containing an additive containing a metal element.
  • the first insulating layer 82 made of a material containing an additive containing a metal element is irradiated with a laser to precipitate the base layer 83A, and the plating layer 83B covering the base layer 83A is formed.
  • the connection wiring 83 (first connection wiring 21, second connection wiring 22, and connection wiring 26, 27) is formed has been described in the above, but the present invention is not limited to this.
  • the connection wiring 8 3 may be formed by other methods. For example, by photolithography patterning using a mask, a plurality of openings are formed in the first insulating layer 82 so that each electrode is exposed, and a connection wiring 83 is formed by plating on the openings and the first insulating layer 82. May be good. In this case, the first insulating layer 82 does not have to be a material containing an additive containing a metal element.
  • the connection wiring 85 (third connection wiring 23) may be formed by other methods.
  • a third external terminal 63 may be arranged between the first external terminal 61 and the second external terminal 62.
  • FIG. 24 is a diagram for explaining the semiconductor device A2 according to the second embodiment of the present disclosure.
  • FIG. 24 is a cross-sectional view showing the semiconductor device A2, and is a diagram corresponding to FIG.
  • the semiconductor device A2 of the present embodiment is different from the first embodiment in that the heat spreader 5 is not provided.
  • the semiconductor device A2 does not include the heat spreader 5, and the element back surface 3b of each semiconductor element 3 is exposed from the resin opening 4c.
  • the resin back surface 4b and the element back surface 3b are flush with each other.
  • the back surface 3b of the element may be partially exposed from the back surface 4b of the resin, and may be partially covered with the sealing resin 4.
  • the back surface 3b of the element is joined to the wiring board by a joining member such as solder. As a result, each semiconductor element 3 can release the generated heat from the element back surface 3b to the wiring board.
  • the element back surface 3b of each semiconductor element 3 is exposed from the resin back surface 4b of the sealing resin 4, and is joined to the wiring board when the semiconductor device A2 is mounted on the wiring board.
  • the semiconductor device A2 can release the heat generated by the semiconductor element 3 to the wiring board. Therefore, the semiconductor device A2 has higher heat dissipation than the conventional semiconductor device in which the semiconductor element 3 is covered with the insulating layer 1 and the sealing resin 4.
  • the semiconductor device A2 as in the first embodiment, the first external terminal 61 and the second external terminal 62 are arranged between the semiconductor element 301 and the semiconductor element 302, and each is exposed from the resin back surface 4b. There is. As a result, the semiconductor device A2 can reduce the magnetic field generation area, so that the inductance of the current path can be suppressed.
  • FIG. 25 is a diagram for explaining the semiconductor device A3 according to the third embodiment of the present disclosure.
  • FIG. 25 is a cross-sectional view showing the semiconductor device A3, and is a diagram corresponding to FIG.
  • the semiconductor device A3 of the present embodiment is different from the first embodiment in that a plurality of main surface connection wirings 25 for mounting the electronic component 9 are further provided on the main surface 1a of the insulating layer.
  • the electronic component 9 is shown by an imaginary line (dashed line). The same applies to the following figure.
  • the semiconductor device A3 is designed so that the electronic component 9 can be mounted on the main surface 1a of the insulating layer, and further includes a plurality of main surface connection wirings 25.
  • the electronic component 9 is, for example, a resistor, a capacitor, a driver IC, or the like, but is not limited thereto. Further, the number of electronic components 9 mounted on the semiconductor device A3 and the arrangement position of each electronic component 9 are not limited.
  • the plurality of main surface connection wirings 25 are conductors that connect the electronic component 9, the first connection wiring 21, the second connection wiring 22, the third connection wiring 23, the connection wirings 26, 27, the external terminal 6, and the like. Yes, it constitutes a conductive path.
  • the plurality of main surface connection wirings 25 are arranged in the insulating layer 1.
  • the structure of each main surface connection wiring 25 is the same as that of the first connection wiring 21 and the like, and each main surface connection wiring 25 includes an embedded portion 251 and a rewiring portion 252, respectively. At least a part of the embedded portion 251 is embedded in the third insulating layer 13.
  • the embedded portion 251 of the main surface connection wiring 25 connected to the third connection wiring 23 is completely embedded in the third insulating layer 13.
  • the embedded portion 251 of the main surface connection wiring 25 connected to the first connection wiring 21, the second connection wiring 22, or the connection wirings 26 and 27 is embedded through the third insulation layer 13 and the second insulation layer 12. There is. Further, the embedded portion 251 of the main surface connection wiring 25 connected to the external terminal 6 is embedded through the third insulating layer 13, the second insulating layer 12, and the first insulating layer 11.
  • the rewiring portion 252 is arranged on the surface of the third insulating layer 13 opposite to the second insulating layer 12, that is, the main surface 1a of the insulating layer.
  • the rewiring portion 252 is connected to the embedded portion 251.
  • the rewiring unit 252 functions as wiring and can join the terminals of the electronic component 9.
  • Each of the embedded portion 251 and the rewiring portion 252 has a base layer 201 and a plating layer 202, similarly to the embedded portion 211 and the rewiring portion 212.
  • the base layer 201 is composed of a metal element contained in the additive contained in the third insulating layer 13, and is in contact with the third insulating layer 13.
  • the plating layer 202 is made of, for example, a material containing copper (Cu) and is in contact with the base layer 201.
  • the base layer 201 of the embedded portion 251 is in contact with the third insulating layer 13.
  • the plating layer 202 of the embedded portion 251 is surrounded by the base layer 201 of the embedded portion 251.
  • the base layer 201 of the rewiring portion 252 is in contact with the third insulating layer 13.
  • the plating layer 202 of the rewiring portion 252 covers the base layer 201 of the rewiring portion 252.
  • the semiconductor device A3 is manufactured in the same manufacturing process as the semiconductor device A1 according to the first embodiment until the step of forming the third insulating layer 86 (third insulating layer 13).
  • a plurality of holes and a plurality of recesses are formed in the formed third insulating layer 86 by a laser, and the base layer 201 of the main surface connection wiring 25 is deposited in these holes and the recesses.
  • the plating layer 202 covering the base layer 201 is formed by electroless plating. As a result, the main surface connection wiring 25 is formed.
  • the subsequent steps are the same as those of the semiconductor device A1.
  • the semiconductor device A3 as in the first embodiment, the first external terminal 61 and the second external terminal 62 are arranged between the semiconductor element 301 and the semiconductor element 302, and each of them is a resin back surface 4b. Is exposed from.
  • the semiconductor device A3 can reduce the magnetic field generation area, so that the inductance of the current path can be suppressed.
  • the semiconductor device A3 since the semiconductor device A3 includes a main surface connecting wiring 25 having a rewiring portion 252 arranged on the insulating layer main surface 1a and functioning as wiring, the electronic component 9 can be mounted on the insulating layer main surface 1a. be.
  • FIG. 26 is a diagram for explaining the semiconductor device A4 according to the fourth embodiment of the present disclosure.
  • FIG. 26 is a cross-sectional view showing the semiconductor device A4, and is a diagram corresponding to FIG.
  • the semiconductor device A4 of the present embodiment is different from the third embodiment in that the fourth insulating layer 14 and the fourth connection wiring 24 are further provided.
  • the insulating layer 1 further includes a fourth insulating layer 14 as shown in FIG. 26.
  • the fourth insulating layer 14 is laminated between the third insulating layer 13 and the second insulating layer 12. That is, the fourth insulating layer 14 is in contact with the third insulating layer 13 and the second insulating layer 12.
  • the fourth insulating layer 14 is formed in the same manner as the second insulating layer 12 after forming the second insulating layer 12 and the third connecting wiring 23 and before forming the third insulating layer 13.
  • the semiconductor device A4 further includes a fourth connection wiring 24.
  • the fourth connection wiring 24 is a conductor connected to the second connection wiring 22, and constitutes a conductive path.
  • the fourth connection wiring 24 is arranged in the fourth insulating layer 14.
  • the structure of the fourth connection wiring 24 is the same as that of the first connection wiring 21 and the like, and the fourth connection wiring 24 includes an embedded portion 241 and a rewiring portion 242.
  • the embedded portion 241 is embedded through the fourth insulating layer 14 and the second insulating layer 12, and is connected to the second connection wiring 22.
  • the embedded portion 241 may be embedded through the third insulating layer 13, the second insulating layer 12, and the first insulating layer 11 and connected to the second external terminal 62.
  • the rewiring portion 242 is arranged between the third insulating layer 13 and the fourth insulating layer 14. The rewiring portion 242 is connected to the embedded portion 241.
  • Each of the embedded portion 241 and the rewiring portion 242 has a base layer 201 and a plating layer 202, similarly to the embedded portion 211 and the rewiring portion 212.
  • the base layer 201 is composed of metal elements contained in the additives contained in the fourth insulating layer 14 and the second insulating layer 12, and is in contact with the fourth insulating layer 14 and the second insulating layer 12.
  • the plating layer 202 is made of, for example, a material containing copper (Cu) and is in contact with the base layer 201.
  • the base layer 201 of the embedded portion 241 is in contact with the fourth insulating layer 14 and the second insulating layer 12.
  • the plating layer 202 of the embedded portion 241 is surrounded by the base layer 201 of the embedded portion 241.
  • the base layer 201 of the rewiring portion 242 is in contact with the fourth insulating layer 14.
  • the plating layer 202 of the rewiring portion 242 covers the base layer 201 of the rewir
  • the semiconductor device A4 is manufactured in the same manufacturing process as the semiconductor device A3 according to the third embodiment until the step of forming the connection wiring 85 (third connection wiring 23).
  • a fourth insulating layer 14 is formed which is laminated on the second insulating layer 84 (second insulating layer 12) and covers the connecting wiring 85 (third connecting wiring 23).
  • a plurality of holes and a plurality of recesses are formed in the formed fourth insulating layer 14 by a laser, and the base layer 201 of the fourth connection wiring 24 is deposited in these holes and the recesses.
  • the plating layer 202 covering the base layer 201 is formed by electroless plating. As a result, the fourth connection wiring 24 is formed.
  • the subsequent steps are the same as those of the semiconductor device A3.
  • the semiconductor device A4 as in the first embodiment, the first external terminal 61 and the second external terminal 62 are arranged between the semiconductor element 301 and the semiconductor element 302, and each of them is a resin back surface 4b. It is exposed from. As a result, the semiconductor device A4 can reduce the magnetic field generation area, so that the inductance of the current path can be suppressed. Further, the semiconductor device A4 is arranged on the fourth insulating layer 14 and the fourth insulating layer 14 laminated between the third insulating layer 13 and the second insulating layer 12, and is connected to the second connection wiring 22. It is provided with a 4-connection wiring 24.
  • the rewiring portion 242 of the fourth connection wiring 24 is arranged between the third insulating layer 13 and the fourth insulating layer 14, and is located between the semiconductor element 3 and the electronic component 9. As a result, the semiconductor device A4 can suppress the influence of the high frequency noise output from the semiconductor element 3 on the electronic component 9.
  • FIG. 27 and 28 are diagrams for explaining the semiconductor device A5 according to the fifth embodiment of the present disclosure.
  • FIG. 27 is a plan view showing the semiconductor device A5, and is a diagram corresponding to FIG.
  • FIG. 28 is a cross-sectional view showing the semiconductor device A5, and is a diagram corresponding to FIG.
  • the semiconductor device A5 of the present embodiment is different from the first embodiment in that the first external terminal 61 and the second external terminal 62 are arranged in the y direction instead of the x direction.
  • the first external terminal 61 and the second external terminal 62 have a dimension in the y direction about half that of the third external terminal 63, and are the same distance from the third external terminal 63. They are separated and lined up in the y direction.
  • the shape of the rewiring portion 212 is such that it overlaps with the first external terminal 61 in the z-direction view, but does not overlap with the second external terminal 62.
  • the shape of the rewiring portion 222 is such that it overlaps with the second external terminal 62 in the z-direction view, but does not overlap with the first external terminal 61.
  • the semiconductor device A5 in the semiconductor device A5, the first external terminal 61 and the second external terminal 62 are arranged between the semiconductor element 301 and the semiconductor element 302, and each is exposed from the resin back surface 4b. As a result, the semiconductor device A5 can reduce the magnetic field generation area, so that the inductance of the current path can be suppressed. Further, in the semiconductor device A5, since the first external terminals 61 and 62 are arranged in the y direction, the dimension in the x direction can be made smaller than that of the semiconductor device A1.
  • FIG. 29 and 30 are diagrams for explaining the semiconductor device A6 according to the sixth embodiment of the present disclosure.
  • FIG. 29 is a plan view showing the semiconductor device A6, and is a diagram corresponding to FIG.
  • FIG. 30 is a cross-sectional view showing the semiconductor device A6, and is a cross-sectional view taken along the line XXX-XXX of FIG. 29.
  • the semiconductor device A6 of the present embodiment is different from the first embodiment in that the second insulating layer 12 is not provided and the third connection wiring 23 is also arranged in the first insulating layer 11.
  • the semiconductor device A6 does not include the second insulating layer 12, and the third insulating layer 13 is laminated on the first insulating layer 11.
  • the third connection wiring 23 is formed in the first insulating layer 11 in the same manner as the first connection wiring 21 and the second connection wiring 22.
  • the shape of the rewiring portion 232 does not contact the rewiring portion 212 and the rewiring portion 222, and overlaps with the output electrode 32 of the semiconductor element 301 in the z-direction view while inputting the semiconductor element 302. It has a shape that overlaps with the electrode 31.
  • the semiconductor device A6 as in the first embodiment, the first external terminal 61 and the second external terminal 62 are arranged between the semiconductor element 301 and the semiconductor element 302, and each of them is a resin back surface 4b. It is exposed from.
  • the semiconductor device A5 can reduce the magnetic field generation area, so that the inductance of the current path can be suppressed.
  • the semiconductor device A6 does not include the second insulating layer 12, the dimension in the z direction can be made smaller than that of the semiconductor device A1. Moreover, since the number of layers of the insulating layer 1 is small, the manufacturing process can be simplified.
  • the semiconductor element 3 may be provided with a back surface electrode on the back surface 3b of the device.
  • the spreader back surface 5b of the heat spreader 5 exposed from the resin opening 4c is externally joined to the wiring of the wiring board by a conductive joining member.
  • the heat spreader 5 needs to have conductivity.
  • the semiconductor device A2 is mounted on the wiring board, the element back surface 3b of the semiconductor element 3 exposed from the resin opening 4c becomes an external terminal that is joined to the wiring of the wiring board by a conductive joining member.
  • first external terminal 61, the second external terminal 62, and the third external terminal 63 are plate-shaped members, respectively, but the present disclosure is not limited to this.
  • the shapes of the first external terminal 61, the second external terminal 62, and the third external terminal 63 are not particularly limited.
  • the first external terminal 61, the second external terminal 62, and the third external terminal 63 may be via holes penetrating the sealing resin 4 in the z direction.
  • the third external terminal 63 is arranged between the semiconductor element 301 and the semiconductor element 302 in the above first to sixth embodiments, but the present disclosure is not limited to this.
  • the third external terminal 63 is located at a position other than between the semiconductor element 301 and the semiconductor element 302, for example, on the side opposite to the first external terminal 61 in the x direction with respect to the semiconductor element 301, or with respect to the semiconductor element 302. It may be arranged on the side opposite to the second external terminal 62 in the x direction. Similar to the fourth external terminal 64 and the fifth external terminal 65, even if they are arranged side by side with the other external terminals 6 at one end (upper end in FIG. 3) of the semiconductor devices A1 to A6 in the y direction. good.
  • the semiconductor device according to the present disclosure is not limited to the above-described embodiment.
  • the specific configuration of each part of the semiconductor device according to the present disclosure can be freely redesigned.
  • the present disclosure includes the configurations described in the appendix below.
  • Each of the element main surface and the element back surface facing the opposite sides in the thickness direction and a plurality of main surface electrodes arranged on the element main surface are arranged in a first direction orthogonal to the thickness direction.
  • the first semiconductor element and the second semiconductor element arranged in An insulating layer having an insulating layer back surface that covers each element main surface and faces each element main surface, and an insulating layer main surface that faces the opposite side of the insulating layer back surface in the thickness direction. It has a resin main surface in contact with the back surface of the insulating layer and a resin back surface facing the side opposite to the resin main surface in the thickness direction, and partially comprises the first semiconductor element and the second semiconductor element.
  • a first connection wiring arranged on the insulating layer and conducting the main surface electrode of any one of the first semiconductor elements and the first external terminal.
  • a second connection wiring that is arranged in the insulating layer and conducts the main surface electrode of any of the second semiconductor elements and the second external terminal.
  • the plurality of main surface electrodes of the first semiconductor element include a first input electrode and a first output electrode.
  • the plurality of main surface electrodes of the second semiconductor element include a second input electrode and a second output electrode.
  • the first connection wiring is connected to the first input electrode and the first external terminal, and is connected to the first input electrode.
  • the semiconductor device according to Appendix 1 wherein the second connection wiring is connected to the second output electrode and the second external terminal.
  • Appendix 3 The semiconductor device according to Appendix 2, further comprising a third connection wiring arranged on the insulating layer and connected to the first output electrode and the second input electrode.
  • the insulating layer includes a laminated first insulating layer, a second insulating layer, and a third insulating layer.
  • the first insulating layer includes the back surface of the insulating layer.
  • the semiconductor device according to Appendix 3, wherein the third insulating layer includes the main surface of the insulating layer. Appendix 5.
  • the first connection wiring includes a first rewiring portion arranged between the first insulating layer and the second insulating layer.
  • the second connection wiring includes a second rewiring portion arranged between the first insulating layer and the second insulating layer.
  • the semiconductor device according to Appendix 4 wherein the third connection wiring includes a third rewiring portion arranged between the second insulating layer and the third insulating layer.
  • Appendix 6. The semiconductor device according to Appendix 5, wherein at least a part of the third rewiring portion overlaps the first rewiring portion and the second rewiring portion in the thickness direction.
  • Appendix 7. A fourth connection wiring that is arranged in the insulation layer and connects to the third connection wiring is further provided.
  • the insulating layer further includes a fourth insulating layer laminated between the second insulating layer and the third insulating layer.
  • the semiconductor device according to any one of Supplementary note 4 to 6, wherein the fourth connection wiring includes a fourth rewiring portion arranged between the fourth insulating layer and the third insulating layer.
  • Appendix 8 The first insulating layer is made of a material containing a thermosetting synthetic resin and an additive containing a metal element constituting a part of the first connection wiring, according to any one of Supplementary note 4 to 7. Semiconductor equipment.
  • the first connection wiring has a base layer in contact with the first insulating layer and a plating layer in contact with the base layer.
  • Appendix 8 wherein the base layer is composed of the metal element contained in the additive.
  • Appendix 10 Appendix 3 to 9 further include a third external terminal arranged between the first semiconductor element and the second semiconductor element, exposed from the back surface of the resin, and connected to the third connection wiring.
  • the semiconductor device according to any one of. Appendix 11. The semiconductor according to Appendix 10, wherein the third external terminal is arranged between the first semiconductor element and the first external terminal, or between the second semiconductor element and the second external terminal.
  • the resin In the first direction, the resin is arranged on the side opposite to the second semiconductor element with respect to the first semiconductor element, or on the side opposite to the first semiconductor element with respect to the second semiconductor element.
  • the semiconductor device according to any one of Appendix 3 to 9, further comprising a third external terminal exposed from the back surface and connected to the third connection wiring.
  • Appendix 13 The first semiconductor element and the second semiconductor element are transistors having an electron traveling layer made of a nitride semiconductor.
  • the first input electrode and the second input electrode are drain electrodes.
  • the semiconductor device according to any one of Supplementary note 2 to 12, wherein the first output electrode and the second output electrode are source electrodes.
  • Appendix 14 The semiconductor device according to any one of Supplementary note 1 to 13, wherein the first external terminal and the second external terminal are exposed from the resin main surface. Appendix 15.
  • the semiconductor device according to any one of Appendix 1 to 14, further comprising a main surface connection wiring having a main surface rewiring portion arranged on the main surface of the insulating layer.
  • Appendix 16 The semiconductor device according to any one of Supplementary note 1 to 15, wherein the sealing resin is provided with a resin opening that overlaps with the first semiconductor element in the thickness direction on the back surface side of the resin.
  • Appendix 17. The semiconductor device according to Appendix 16, wherein the back surface of the first semiconductor element is exposed from the resin opening.
  • the heat spreader The main surface of the spreader facing the back surface of the first element and The back surface of the spreader facing the opposite side of the main surface of the spreader in the thickness direction, Have, The semiconductor device according to Appendix 16, wherein the back surface of the spreader is exposed from the resin opening.

Abstract

This semiconductor device is provided with a first semiconductor element, a second semiconductor element, an insulating layer, a sealing resin, a first external terminal, a second external terminal, a first connecting wire, and a second connecting wire. Each of the semiconductor elements has an element major surface, an element back surface, and a plurality of major surface electrodes disposed on the element major surface. The insulating layer has an insulating layer back surface opposing each of the element major surfaces, and an insulating layer major surface opposite the insulating layer back surface. The sealing resin has a resin major surface in contact with the insulating layer back surface, and a resin back surface opposite the resin major surface. The sealing resin covers each of the semiconductor elements partially. Each of the external terminals is disposed between the first and second semiconductor elements, and is exposed from the resin back surface. The first connecting wire is disposed on the insulating layer and connects any of the major surface electrodes of the first semiconductor element to the first external terminal. The second connecting wire is disposed on the insulating layer and connects any of the major surface electrodes of the second semiconductor element to the second external terminal.

Description

半導体装置Semiconductor device
　本開示は、Ｆａｎ－Ｏｕｔ型の半導体装置に関する。 This disclosure relates to a Fan-Out type semiconductor device.
　近年における電子機器の小型化に伴い、当該電子機器に用いられる半導体装置の小型化が進められている。こうした動向を受け、いわゆるＦａｎ－Ｏｕｔ型の半導体装置が開発されている。当該半導体装置は、複数の電極を有する半導体素子と、半導体素子に接する絶縁層と、絶縁層に配置され、かつ複数の電極につながる複数の接続配線と、絶縁層に接し、かつ前記半導体素子の一部を覆う封止樹脂とを備える。厚さ方向視において、複数の接続配線は、半導体素子よりも外方に位置する部分を含む。これにより、半導体装置の小型化を図りつつ、当該半導体装置が実装される配線基板の配線パターンの形状に柔軟に対応できるという利点を有する。 With the miniaturization of electronic devices in recent years, the miniaturization of semiconductor devices used in the electronic devices is being promoted. In response to these trends, so-called Fan-Out type semiconductor devices have been developed. The semiconductor device includes a semiconductor element having a plurality of electrodes, an insulating layer in contact with the semiconductor element, a plurality of connection wirings arranged in the insulating layer and connected to the plurality of electrodes, and the semiconductor element in contact with the insulating layer. It is provided with a sealing resin that partially covers it. In the thickness direction, the plurality of connection wirings include a portion located outside the semiconductor element. This has the advantage that the shape of the wiring pattern of the wiring board on which the semiconductor device is mounted can be flexibly adapted while reducing the size of the semiconductor device.
　特許文献１には、Ｆａｎ－Ｏｕｔ型の半導体装置の一例が開示されている。当該半導体装置は、主面に複数の電極を有する半導体素子と、半導体素子の主面に接する絶縁層と、絶縁層に接し半導体素子の一部を覆う封止樹脂と、絶縁層の内部に形成され、厚さ方向視において半導体素子よりも外方に位置する部分を含む複数の接続配線とを備えている。半導体素子は、絶縁層と封止樹脂とによって覆われている。当該半導体装置は、インターポーザーやプリント配線板を含まないので、薄型化することができる。 Patent Document 1 discloses an example of a Fan-Out type semiconductor device. The semiconductor device is formed inside a semiconductor element having a plurality of electrodes on the main surface, an insulating layer in contact with the main surface of the semiconductor element, a sealing resin in contact with the insulating layer and covering a part of the semiconductor element, and an insulating layer. It is provided with a plurality of connecting wires including a portion located outside the semiconductor element in the thickness direction. The semiconductor element is covered with an insulating layer and a sealing resin. Since the semiconductor device does not include an interposer or a printed wiring board, it can be made thinner.
　コンバータやインバータなどに用いるために、２個のスイッチング素子を直列接続したブリッジ回路を構成する半導体装置が求められている。当該半導体装置をＦａｎ－Ｏｕｔ型の半導体装置で実現する場合、スイッチング素子である半導体素子を、厚さ方向に直交する方向に２個配置して、一方の半導体素子のソース電極を他方の半導体素子のドレイン電極に導通させる。一方の半導体素子のドレイン電極を、外部から直流電圧を印加される外部端子に導通させる。他方の半導体素子のソース電極を、グランドに接続される外部端子に導通させる。このような半導体装置においては、半導体素子がＯＮ状態に切り替えられるときに発生するサージ電圧を抑制するために、半導体装置内部の電流経路のインダクタンスを抑制することが要求される。 A semiconductor device that constitutes a bridge circuit in which two switching elements are connected in series is required for use in a converter or an inverter. When the semiconductor device is realized by a Fan-Out type semiconductor device, two semiconductor elements, which are switching elements, are arranged in a direction orthogonal to the thickness direction, and the source electrode of one semiconductor element is the other semiconductor element. Conducting to the drain electrode of. The drain electrode of one of the semiconductor elements is made conductive to an external terminal to which a DC voltage is applied from the outside. The source electrode of the other semiconductor element is made conductive to an external terminal connected to the ground. In such a semiconductor device, it is required to suppress the inductance of the current path inside the semiconductor device in order to suppress the surge voltage generated when the semiconductor element is switched to the ON state.
特開２０１９－２９５５７号公報Japanese Unexamined Patent Publication No. 2019-29557
　上記した事情に鑑み、本開示は、内部の電流経路のインダクタンスを抑制できる半導体装置を提供することを一の課題とする。 In view of the above circumstances, one object of the present disclosure is to provide a semiconductor device capable of suppressing the inductance of the internal current path.
　本開示の第１の側面によって提供される半導体装置は、厚さ方向において互いに反対側を向く素子主面および素子裏面と、前記素子主面に配置された複数の主面電極とを各々が有し、前記厚さ方向に直交する第１方向に並んで配置された第１半導体素子および第２半導体素子と、前記各素子主面を覆い、かつ、前記各素子主面に対向する絶縁層裏面と、前記厚さ方向において前記絶縁層裏面とは反対側を向く絶縁層主面と、を有する絶縁層と、前記絶縁層裏面に接する樹脂主面と、前記厚さ方向において前記樹脂主面とは反対側を向く樹脂裏面とを有し、かつ、前記第１半導体素子および前記第２半導体素子を部分的に覆う封止樹脂と、前記第１半導体素子と前記第２半導体素子との間に配置され、各々が前記樹脂裏面から露出する第１外部端子および第２外部端子と、前記絶縁層に配置され、前記第１半導体素子のいずれかの主面電極と前記第１外部端子とを導通させる第１接続配線と、前記絶縁層に配置され、前記第２半導体素子のいずれかの主面電極と前記第２外部端子とを導通させる第２接続配線とを備えている。 The semiconductor device provided by the first aspect of the present disclosure has an element main surface and an element back surface facing opposite sides in the thickness direction, and a plurality of main surface electrodes arranged on the element main surface, respectively. Then, the first semiconductor element and the second semiconductor element arranged side by side in the first direction orthogonal to the thickness direction, and the back surface of the insulating layer that covers the main surface of each element and faces the main surface of each element. An insulating layer having an insulating layer main surface facing away from the back surface of the insulating layer in the thickness direction, a resin main surface in contact with the back surface of the insulating layer, and the resin main surface in the thickness direction. Has a resin back surface facing the opposite side, and is between the sealing resin that partially covers the first semiconductor element and the second semiconductor element, and between the first semiconductor element and the second semiconductor element. The first external terminal and the second external terminal, each of which is arranged and exposed from the back surface of the resin, and the main surface electrode of any one of the first semiconductor elements and the first external terminal, which are arranged in the insulating layer, are electrically connected to each other. It is provided with a first connection wiring to be made to be connected, and a second connection wiring arranged on the insulating layer to conduct the main surface electrode of any one of the second semiconductor elements and the second external terminal.
　上述の構成によれば、第１外部端子から、第１接続配線、第１半導体素子、第２半導体素子、および第２接続配線を介して第２外部端子につながる電流経路のループの面積（磁界発生面積）を小さくでき、当該電流経路のインダクタンスを抑制できる。 According to the above configuration, the area (magnetic field) of the loop of the current path from the first external terminal to the second external terminal via the first connection wiring, the first semiconductor element, the second semiconductor element, and the second connection wiring. The generated area) can be reduced, and the inductance of the current path can be suppressed.
　本開示のその他の特徴および利点は、添付図面を参照して以下に行う詳細な説明によって、より明らかとなろう。 Other features and advantages of this disclosure will become more apparent with the detailed description given below with reference to the accompanying drawings.
本開示の第１実施形態に係る半導体装置を示す平面図であり、第３絶縁層を透過した図である。It is a top view which shows the semiconductor device which concerns on 1st Embodiment of this disclosure, and is the figure which transmitted through the 3rd insulating layer. 図１の半導体装置を示す平面図であり、さらに第２絶縁層および第３接続配線を透過した図である。It is a top view which shows the semiconductor device of FIG. 1, and is also the figure which transmitted through the 2nd insulation layer and the 3rd connection wiring. 図１の半導体装置を示す平面図であり、さらに第１絶縁層およびすべての接続配線を透過した図である。It is a top view which shows the semiconductor device of FIG. 1, and is also the figure which transmitted through the 1st insulation layer and all the connection wirings. 図１の半導体装置を示す底面図である。It is a bottom view which shows the semiconductor device of FIG. 図１のＶ－Ｖ線に沿う断面図である。It is sectional drawing which follows the VV line of FIG. 図１のＶＩ－ＶＩ線に沿う断面図である。It is sectional drawing which follows the VI-VI line of FIG. 図５の部分拡大図である。It is a partially enlarged view of FIG. 図１の半導体装置の製造方法の一例の一工程を示す断面図である。It is sectional drawing which shows one process of an example of the manufacturing method of the semiconductor device of FIG. 図１の半導体装置の製造方法の一例の一工程を示す断面図である。It is sectional drawing which shows one process of an example of the manufacturing method of the semiconductor device of FIG. 図１の半導体装置の製造方法の一例の一工程を示す断面図である。It is sectional drawing which shows one process of an example of the manufacturing method of the semiconductor device of FIG. 図１０の部分拡大図である。It is a partially enlarged view of FIG. 図１の半導体装置の製造方法の一例の一工程を示す平面図である。It is a top view which shows one process of an example of the manufacturing method of the semiconductor device of FIG. 図１の半導体装置の製造方法の一例の一工程を示す断面図である。It is sectional drawing which shows one process of an example of the manufacturing method of the semiconductor device of FIG. 図１３の部分拡大図である。It is a partially enlarged view of FIG. 図１の半導体装置の製造方法の一例の一工程を示す断面図である。It is sectional drawing which shows one process of an example of the manufacturing method of the semiconductor device of FIG. 図１の半導体装置の製造方法の一例の一工程を示す断面図である。It is sectional drawing which shows one process of an example of the manufacturing method of the semiconductor device of FIG. 図１の半導体装置の製造方法の一例の一工程を示す平面図である。It is a top view which shows one process of an example of the manufacturing method of the semiconductor device of FIG. 図１の半導体装置の製造方法の一例の一工程を示す断面図である。It is sectional drawing which shows one process of an example of the manufacturing method of the semiconductor device of FIG. 図１の半導体装置の製造方法の一例の一工程を示す断面図である。It is sectional drawing which shows one process of an example of the manufacturing method of the semiconductor device of FIG. 図１の半導体装置を示す模式図であり、電流の流れを示している。It is a schematic diagram which shows the semiconductor device of FIG. 1, and shows the flow of an electric current. 図１の半導体装置を示す模式図であり、電流の流れを示している。It is a schematic diagram which shows the semiconductor device of FIG. 1, and shows the flow of an electric current. 図１の半導体装置を示す模式図であり、電流の流れを示している。It is a schematic diagram which shows the semiconductor device of FIG. 1, and shows the flow of an electric current. 図１の半導体装置を示す模式図であり、電流の流れを示している。It is a schematic diagram which shows the semiconductor device of FIG. 1, and shows the flow of an electric current. 本開示の第２実施形態に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment of this disclosure. 本開示の第３実施形態に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on 3rd Embodiment of this disclosure. 本開示の第４実施形態に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on 4th Embodiment of this disclosure. 本開示の第５実施形態に係る半導体装置を示す平面図である。It is a top view which shows the semiconductor device which concerns on 5th Embodiment of this disclosure. 図２７の半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device of FIG. 本開示の第６実施形態に係る半導体装置を示す平面図である。It is a top view which shows the semiconductor device which concerns on 6th Embodiment of this disclosure. 図２９のＸＸＸ-ＸＸＸ線に沿う断面図である。It is sectional drawing which follows the XXXX-XXX line of FIG.
　以下、本開示の好ましい実施の形態につき、図面を参照して具体的に説明する。 Hereinafter, preferred embodiments of the present disclosure will be specifically described with reference to the drawings.
　本開示において、「ある物Ａがある物Ｂに形成されている」および「ある物Ａがある物Ｂ上に形成されている」とは、特段の断りのない限り、「ある物Ａがある物Ｂに直接形成されていること」、および、「ある物Ａとある物Ｂとの間に他の物を介在させつつ、ある物Ａがある物Ｂに形成されていること」を含む。同様に、「ある物Ａがある物Ｂに配置されている」および「ある物Ａがある物Ｂ上に配置されている」とは、特段の断りのない限り、「ある物Ａがある物Ｂに直接配置されていること」、および、「ある物Ａとある物Ｂとの間に他の物を介在させつつ、ある物Ａがある物Ｂに配置されていること」を含む。同様に、「ある物Ａがある物Ｂ上に位置している」とは、特段の断りのない限り、「ある物Ａがある物Ｂに接して、ある物Ａがある物Ｂ上に位置していること」、および、「ある物Ａとある物Ｂとの間に他の物が介在しつつ、ある物Ａがある物Ｂ上に位置していること」を含む。また、「ある物Ａがある物Ｂにある方向に見て重なる」とは、特段の断りのない限り、「ある物Ａがある物Ｂのすべてに重なること」、および、「ある物Ａがある物Ｂの一部に重なること」を含む。 In the present disclosure, "something A is formed on a certain thing B" and "something A is formed on a certain thing B" means "there is a certain thing A" unless otherwise specified. It includes "being formed directly on the object B" and "being formed on the object B with the object A while interposing another object between the object A and the object B". Similarly, "something A is placed on something B" and "something A is placed on something B" means "something A is placed on something B" unless otherwise specified. It includes "being placed directly on B" and "being placed on a certain thing B while having another thing intervening between a certain thing A and a certain thing B". Similarly, "something A is located on something B" means "something A is in contact with something B and some thing A is on something B" unless otherwise specified. "What you are doing" and "The thing A is located on the thing B while another thing is intervening between the thing A and the thing B". In addition, "something A overlaps with a certain thing B when viewed in a certain direction" means "something A overlaps with all of a certain thing B" and "something A overlaps" unless otherwise specified. "Overlapping a part of a certain object B" is included.
　図１～図７は、本開示に係る半導体装置の一例を示している。本実施形態の半導体装置Ａ１は、絶縁層１、複数の接続配線２、２個の半導体素子３、封止樹脂４、２個のヒートスプレッダ５、および複数の外部端子６を備えている。絶縁層１は、第１絶縁層１１、第２絶縁層１２、および第３絶縁層１３を含んでいる。接続配線２は、第１接続配線２１、第２接続配線２２、第３接続配線２３、接続配線２６、および接続配線２７を含んでいる。半導体装置Ａ１は、配線基板に表面実装されるＦａｎ－Ｏｕｔ型である。 1 to 7 show an example of the semiconductor device according to the present disclosure. The semiconductor device A1 of the present embodiment includes an insulating layer 1, a plurality of connection wirings 2, two semiconductor elements 3, a sealing resin 4, two heat spreaders 5, and a plurality of external terminals 6. The insulating layer 1 includes a first insulating layer 11, a second insulating layer 12, and a third insulating layer 13. The connection wiring 2 includes a first connection wiring 21, a second connection wiring 22, a third connection wiring 23, a connection wiring 26, and a connection wiring 27. The semiconductor device A1 is a Fan-Out type that is surface-mounted on a wiring board.
　図１は、半導体装置Ａ１を示す平面図であり、第３絶縁層１３を透過した図である。図２は、半導体装置Ａ１を示す平面図であり、さらに、第２絶縁層１２および第３接続配線２３を透過した図である。図３は、半導体装置Ａ１を示す平面図であり、さらに第１絶縁層１１およびすべての接続配線２を透過した図である。図４は、半導体装置Ａ１を示す底面図である。図５は、図１のＶ－Ｖ線に沿う断面図である。図６は、図１のＶＩ－ＶＩ線に沿う断面図である。図７は、図５の部分拡大図である。 FIG. 1 is a plan view showing the semiconductor device A1 and is a view that has passed through the third insulating layer 13. FIG. 2 is a plan view showing the semiconductor device A1, and is a view through which the second insulating layer 12 and the third connecting wiring 23 are transmitted. FIG. 3 is a plan view showing the semiconductor device A1, and is a view through which the first insulating layer 11 and all the connecting wirings 2 are transmitted. FIG. 4 is a bottom view showing the semiconductor device A1. FIG. 5 is a cross-sectional view taken along the line VV of FIG. FIG. 6 is a cross-sectional view taken along the line VI-VI of FIG. FIG. 7 is a partially enlarged view of FIG.
　半導体装置Ａ１は、板状であり、厚さ方向視(平面視)の形状が矩形状である。説明の便宜上、半導体装置Ａ１の厚さ方向（平面視方向）をｚ方向とし、ｚ方向に直交する半導体装置Ａ１の一方の辺に沿う方向（図１～図７における左右方向）をｘ方向、ｚ方向およびｘ方向に直交する方向（図１～図４における上下方向）をｙ方向とする。ｚ方向が「厚さ方向」の一例である。また、ｘ方向が「第１方向」の一例である。半導体装置Ａ１の大きさは特に限定されない。 The semiconductor device A1 has a plate shape and a rectangular shape in the thickness direction (plan view). For convenience of explanation, the thickness direction (plan view direction) of the semiconductor device A1 is the z direction, and the direction along one side of the semiconductor device A1 orthogonal to the z direction (the left-right direction in FIGS. 1 to 7) is the x direction. The direction orthogonal to the z direction and the x direction (the vertical direction in FIGS. 1 to 4) is defined as the y direction. The z direction is an example of the "thickness direction". Further, the x direction is an example of the "first direction". The size of the semiconductor device A1 is not particularly limited.
　半導体素子３は、半導体装置Ａ１の電気的機能を発揮する要素である。本実施形態では、半導体装置Ａ１は、２個の半導体素子３を備えている。２個の半導体素子３を区別して記載する場合、一方を半導体素子３０１とし、他方を半導体素子３０２とする。両者を区別しない場合は、単に半導体素子３とする。本実施形態では、半導体素子３は、窒化物半導体からなる電子走行層を有する高電子移動度トランジスタ（ＨＥＭＴ）であり、本実施形態では、窒化ガリウム（ＧａＮ）が用いられている。 The semiconductor element 3 is an element that exerts an electrical function of the semiconductor device A1. In this embodiment, the semiconductor device A1 includes two semiconductor elements 3. When the two semiconductor elements 3 are described separately, one is referred to as a semiconductor element 301 and the other is referred to as a semiconductor element 302. When the two are not distinguished, it is simply referred to as the semiconductor element 3. In the present embodiment, the semiconductor element 3 is a high electron mobility transistor (HEMT) having an electron traveling layer made of a nitride semiconductor, and gallium nitride (GaN) is used in the present embodiment.
　各半導体素子３は、ｚ方向視矩形状の板状であり、素子主面３ａ、素子裏面３ｂ、複数の入力電極３１、複数の出力電極３２、および制御電極３３を備えている。素子主面３ａおよび素子裏面３ｂは、ｚ方向において互いに反対側を向いている。素子主面３ａには、図３に示すように、入力電極３１、出力電極３２、および制御電極３３が配置されている。入力電極３１は、たとえばドレイン電極である。出力電極３２は、たとえばソース電極である。制御電極３３は、たとえばゲート電極である。 Each semiconductor element 3 has a rectangular plate shape in the z-direction, and includes an element main surface 3a, an element back surface 3b, a plurality of input electrodes 31, a plurality of output electrodes 32, and a control electrode 33. The element main surface 3a and the element back surface 3b face opposite to each other in the z direction. As shown in FIG. 3, an input electrode 31, an output electrode 32, and a control electrode 33 are arranged on the element main surface 3a. The input electrode 31 is, for example, a drain electrode. The output electrode 32 is, for example, a source electrode. The control electrode 33 is, for example, a gate electrode.
　図３に示すように、半導体素子３０１および半導体素子３０２は、ｚ方向視において、半導体装置Ａ１のｙ方向のほぼ中央に、ｘ方向に並んで配置されている。本実施形態では、半導体素子３０１は図３の右側に配置され、半導体素子３０２は図３の左側に配置されている。半導体素子３の種類、および配置位置は特に限定されない。 As shown in FIG. 3, the semiconductor element 301 and the semiconductor element 302 are arranged side by side in the x direction at substantially the center of the semiconductor device A1 in the y direction in the z direction. In this embodiment, the semiconductor element 301 is arranged on the right side of FIG. 3, and the semiconductor element 302 is arranged on the left side of FIG. The type and arrangement position of the semiconductor element 3 are not particularly limited.
　ヒートスプレッダ５は、ｚ方向視矩形状の板状であり、半導体素子３が発する熱を、半導体装置Ａ１が実装された配線基板に放熱するための部材である。本実施形態では、半導体装置Ａ１は、半導体素子３の数に合わせて、２個のヒートスプレッダ５を備えている。一方のヒートスプレッダ５は、半導体素子３０１に接合され、他方のヒートスプレッダ５は、半導体素子３０２に接合されている。各ヒートスプレッダ５は、熱伝導率が高い材料からなり、本実施形態ではＣｕからなる。ヒートスプレッダ５の材料は限定されず、Ａｌなどの他の金属であってもよいし、セラミックなどであってもよい。各ヒートスプレッダ５は、スプレッダ主面５ａおよびスプレッダ裏面５ｂを備えている。スプレッダ主面５ａおよびスプレッダ裏面５ｂは、ｚ方向において互いに反対側を向いている。ヒートスプレッダ５は、スプレッダ主面５ａを半導体素子３に対向させて、半導体素子３の素子裏面３ｂに接合されている。本実施形態では、ヒートスプレッダ５は、ｘ方向およびｙ方向の寸法が半導体素子３の各寸法に一致しているが、本開示はこれに限定されない。ヒートスプレッダ５のスプレッダ裏面５ｂは、封止樹脂４から露出している。スプレッダ裏面５ｂは、半導体装置Ａ１が配線基板に実装される際に、たとえばハンダなどの接合部材によって、配線基板に接合される。これにより、ヒートスプレッダ５は、半導体素子３が発する熱を配線基板に放出する。 The heat spreader 5 has a rectangular plate shape in the z-direction, and is a member for radiating the heat generated by the semiconductor element 3 to the wiring substrate on which the semiconductor device A1 is mounted. In the present embodiment, the semiconductor device A1 includes two heat spreaders 5 according to the number of semiconductor elements 3. One heat spreader 5 is bonded to the semiconductor element 301, and the other heat spreader 5 is bonded to the semiconductor element 302. Each heat spreader 5 is made of a material having high thermal conductivity, and in this embodiment, is made of Cu. The material of the heat spreader 5 is not limited, and may be another metal such as Al, ceramic or the like. Each heat spreader 5 includes a spreader main surface 5a and a spreader back surface 5b. The spreader main surface 5a and the spreader back surface 5b face each other in the z direction. The heat spreader 5 is joined to the element back surface 3b of the semiconductor element 3 with the spreader main surface 5a facing the semiconductor element 3. In the present embodiment, the dimensions of the heat spreader 5 in the x-direction and the y-direction match the dimensions of the semiconductor element 3, but the present disclosure is not limited to this. The back surface 5b of the spreader of the heat spreader 5 is exposed from the sealing resin 4. When the semiconductor device A1 is mounted on the wiring board, the spreader back surface 5b is joined to the wiring board by a joining member such as solder. As a result, the heat spreader 5 releases the heat generated by the semiconductor element 3 to the wiring board.
　封止樹脂４は、半導体素子３およびヒートスプレッダ５の各々の一部を覆っている。封止樹脂４は、たとえば黒色のエポキシ樹脂を含む材料からなる。封止樹脂４は、樹脂主面４ａ、樹脂裏面４ｂ、および樹脂開口４ｃを備えている。樹脂主面４ａおよび樹脂裏面４ｂは、ｚ方向において互いに反対側を向いている。本実施形態では、樹脂主面４ａは、半導体素子３の素子主面３ａと面一であり、絶縁層１に接している。入力電極３１、出力電極３２、および制御電極３３が封止樹脂４から露出していればよく、素子主面３ａの一部が封止樹脂４に覆われていてもよい。樹脂裏面４ｂは、半導体装置Ａ１を配線基板に実装した場合に、配線基板に対向する面である。樹脂開口４ｃは、樹脂裏面４ｂ側に形成された開口であり、ｚ方向視において半導体素子３に重なっている。本実施形態では、ヒートスプレッダ５のスプレッダ裏面５ｂが樹脂開口４ｃから露出し、樹脂裏面４ｂとスプレッダ裏面５ｂとが面一である。スプレッダ裏面５ｂは、一部が樹脂裏面４ｂから露出していればよく、一部が封止樹脂４に覆われていてもよい。 The sealing resin 4 covers a part of each of the semiconductor element 3 and the heat spreader 5. The sealing resin 4 is made of a material containing, for example, a black epoxy resin. The sealing resin 4 includes a resin main surface 4a, a resin back surface 4b, and a resin opening 4c. The resin main surface 4a and the resin back surface 4b face each other in the z direction. In the present embodiment, the resin main surface 4a is flush with the element main surface 3a of the semiconductor element 3 and is in contact with the insulating layer 1. The input electrode 31, the output electrode 32, and the control electrode 33 may be exposed from the sealing resin 4, and a part of the element main surface 3a may be covered with the sealing resin 4. The resin back surface 4b is a surface facing the wiring board when the semiconductor device A1 is mounted on the wiring board. The resin opening 4c is an opening formed on the resin back surface 4b side and overlaps with the semiconductor element 3 in the z-direction view. In the present embodiment, the back surface 5b of the spreader of the heat spreader 5 is exposed from the resin opening 4c, and the back surface 4b of the resin and the back surface 5b of the spreader are flush with each other. The back surface 5b of the spreader may be partially exposed from the back surface 4b of the resin, and may be partially covered with the sealing resin 4.
　複数の外部端子６は、導電体からなり、本実施形態ではＣｕからなる。本実施形態では、図３に示すように、外部端子６には、第１外部端子６１、第２外部端子６２、第３外部端子６３、第４外部端子６４、および第５外部端子６５が含まれる。 The plurality of external terminals 6 are made of a conductor, and in this embodiment, are made of Cu. In the present embodiment, as shown in FIG. 3, the external terminal 6 includes a first external terminal 61, a second external terminal 62, a third external terminal 63, a fourth external terminal 64, and a fifth external terminal 65. Is done.
　第１外部端子６１、第２外部端子６２、および第３外部端子６３は、それぞれ、ｘ方向を厚さ方向とする板状であり、厚さ方向視（ｘ方向視）矩形状である。第１外部端子６１、第２外部端子６２、および第３外部端子６３は、ｚ方向視において、半導体素子３０１と半導体素子３０２との間に、等間隔で配置されている。第１外部端子６１は、半導体素子３０１に隣接し、かつ、離間して配置されている。第３外部端子６３は、半導体素子３０２に隣接し、かつ、離間して配置されている。第２外部端子６２は、第１外部端子６１と第２外部端子６２との間に、離間して配置されている。第１外部端子６１は、半導体素子３０１の入力電極３１に導通する。第２外部端子６２は、半導体素子３０２の出力電極３２に導通する。第３外部端子６３は、半導体素子３０１の出力電極３２および半導体素子３０２の入力電極３１に導通する。 The first external terminal 61, the second external terminal 62, and the third external terminal 63 each have a plate shape with the x direction as the thickness direction and a rectangular shape in the thickness direction (x direction view). The first external terminal 61, the second external terminal 62, and the third external terminal 63 are arranged at equal intervals between the semiconductor element 301 and the semiconductor element 302 in the z-direction view. The first external terminal 61 is arranged adjacent to and separated from the semiconductor element 301. The third external terminal 63 is arranged adjacent to and separated from the semiconductor element 302. The second external terminal 62 is arranged apart from the first external terminal 61 and the second external terminal 62. The first external terminal 61 conducts to the input electrode 31 of the semiconductor element 301. The second external terminal 62 conducts to the output electrode 32 of the semiconductor element 302. The third external terminal 63 conducts to the output electrode 32 of the semiconductor element 301 and the input electrode 31 of the semiconductor element 302.
　第１外部端子６１、第２外部端子６２、および第３外部端子６３以外の外部端子６は、それぞれ、直方体形状であり、ｚ方向視において、半導体装置Ａ１のｙ方向の一方端部（図３参照）に、ｘ方向に等間隔で並んで配置されており、互いに離間されている。第４外部端子６４は、図３における右端に配置された外部端子６であり、半導体素子３０１の制御電極３３に導通する。第５外部端子６５は、図３における右側から４番目に配置された外部端子６であり、半導体素子３０２の制御電極３３に導通する。第１外部端子６１、第２外部端子６２、および第３外部端子６３以外の外部端子６の数、形状、および配置位置は特に限定されない。 The external terminals 6 other than the first external terminal 61, the second external terminal 62, and the third external terminal 63 each have a rectangular parallelepiped shape, and one end of the semiconductor device A1 in the y direction (FIG. 3). (See), they are arranged side by side at equal intervals in the x direction, and are separated from each other. The fourth external terminal 64 is an external terminal 6 arranged at the right end in FIG. 3, and is conductive to the control electrode 33 of the semiconductor element 301. The fifth external terminal 65 is the fourth external terminal 6 arranged from the right side in FIG. 3, and is conductive to the control electrode 33 of the semiconductor element 302. The number, shape, and arrangement position of the external terminals 6 other than the first external terminal 61, the second external terminal 62, and the third external terminal 63 are not particularly limited.
　各外部端子６は、封止樹脂４によって大部分が覆われている。各外部端子６は、図５および図６に示すように、ｚ方向の一方の面が封止樹脂４の樹脂主面４ａから露出している。当該一方の面は、接続配線２を介して、半導体素子３などに接続している。また、各外部端子６は、図５および図６に示すように、ｚ方向の他方の面が封止樹脂４の樹脂裏面４ｂから露出している。当該他方の面は、半導体装置Ａ１が配線基板に実装される際に、たとえばハンダなどの接合部材によって、配線基板の配線に接合される。当該他方の面には、たとえばニッケル（Ｎｉ）層、パラジウム層（Ｐｄ）、金（Ａｕ）層の順に積層された金属層が形成されてもよく、錫（Ｓｎ）を含む材料からなるバンプ部が形成されてもよい。 Most of each external terminal 6 is covered with the sealing resin 4. As shown in FIGS. 5 and 6, one surface of each external terminal 6 in the z direction is exposed from the resin main surface 4a of the sealing resin 4. One of the surfaces is connected to the semiconductor element 3 or the like via the connection wiring 2. Further, as shown in FIGS. 5 and 6, the other surface of each external terminal 6 in the z direction is exposed from the resin back surface 4b of the sealing resin 4. When the semiconductor device A1 is mounted on the wiring board, the other surface is joined to the wiring of the wiring board by a joining member such as solder. On the other surface, for example, a metal layer in which a nickel (Ni) layer, a palladium layer (Pd), and a gold (Au) layer are laminated in this order may be formed, and a bump portion made of a material containing tin (Sn) may be formed. May be formed.
　第１外部端子６１は、第１接続配線２１を介して半導体素子３０１の入力電極３１（ドレイン電極）に接続されており（図２および図５参照）、外部から直流電圧を印加されるＶｉｎ端子として機能する。第２外部端子６２は、第２接続配線２２を介して半導体素子３０２の出力電極３２（ソース電極）に接続されており（図２および図６参照）、グランドに接続されるＰＧＮＤ端子として機能する。第３外部端子６３は、第３接続配線２３を介して、半導体素子３０１の出力電極３２（ソース電極）および半導体素子３０２の入力電極３１（ドレイン電極）に接続されており（図１、図５および図６参照）、スイッチング信号を出力するＳＷ端子として機能する。第４外部端子６４は、接続配線２６を介して、半導体素子３０１の制御電極３３（ゲート電極）に接続されており（図２参照）、半導体素子３０１への駆動信号を入力する信号端子として機能する。第５外部端子６５は、接続配線２７を介して、半導体素子３０２の制御電極３３（ゲート電極）に接続されており（図２参照）、半導体素子３０２への駆動信号を入力する信号端子として機能する。 The first external terminal 61 is connected to the input electrode 31 (drain electrode) of the semiconductor element 301 via the first connection wiring 21 (see FIGS. 2 and 5), and is a Vin terminal to which a DC voltage is applied from the outside. Functions as. The second external terminal 62 is connected to the output electrode 32 (source electrode) of the semiconductor element 302 via the second connection wiring 22 (see FIGS. 2 and 6), and functions as a PGND terminal connected to the ground. .. The third external terminal 63 is connected to the output electrode 32 (source electrode) of the semiconductor element 301 and the input electrode 31 (drain electrode) of the semiconductor element 302 via the third connection wiring 23 (FIGS. 1 and 5). And FIG. 6), it functions as a SW terminal that outputs a switching signal. The fourth external terminal 64 is connected to the control electrode 33 (gate electrode) of the semiconductor element 301 via the connection wiring 26 (see FIG. 2), and functions as a signal terminal for inputting a drive signal to the semiconductor element 301. do. The fifth external terminal 65 is connected to the control electrode 33 (gate electrode) of the semiconductor element 302 via the connection wiring 27 (see FIG. 2), and functions as a signal terminal for inputting a drive signal to the semiconductor element 302. do.
　絶縁層１は、図５および図６に示すように、各半導体素子３の素子主面３ａおよび封止樹脂４の樹脂主面４ａに接している。絶縁層１は、熱硬化性の合成樹脂、および、複数の接続配線２の一部を組成する金属元素が含有された添加剤を含む材料からなる。当該合成樹脂は、たとえばエポキシ樹脂やポリイミド樹脂である。絶縁層１は、絶縁層主面１ａおよび絶縁層裏面１ｂを有する。絶縁層主面１ａおよび絶縁層裏面１ｂは、ｚ方向において 互いに反対側を向く。絶縁層裏面１ｂは、各半導体素子３の素子主面３ａおよび封止樹脂４の樹脂主面４ａに対向して接しており、各半導体素子３の素子主面３ａおよび封止樹脂４の樹脂主面４ａを覆っている。絶縁層裏面１ｂは、各半導体素子３の素子主面３ａに接していなくてもよい。 As shown in FIGS. 5 and 6, the insulating layer 1 is in contact with the element main surface 3a of each semiconductor element 3 and the resin main surface 4a of the sealing resin 4. The insulating layer 1 is made of a material containing a thermosetting synthetic resin and an additive containing a metal element that constitutes a part of a plurality of connecting wirings 2. The synthetic resin is, for example, an epoxy resin or a polyimide resin. The insulating layer 1 has an insulating layer main surface 1a and an insulating layer back surface 1b. The main surface 1a of the insulating layer and the back surface 1b of the insulating layer face opposite to each other in the z direction. The back surface 1b of the insulating layer is in contact with the element main surface 3a of each semiconductor element 3 and the resin main surface 4a of the sealing resin 4 facing each other, and the element main surface 3a of each semiconductor element 3 and the resin main surface of the sealing resin 4 are in contact with each other. It covers the surface 4a. The back surface 1b of the insulating layer does not have to be in contact with the element main surface 3a of each semiconductor element 3.
　絶縁層１は、第１絶縁層１１、第２絶縁層１２、および第３絶縁層１３を備えている。図５および図６に示すように、第１絶縁層１１、第２絶縁層１２、および第３絶縁層１３は、この順に、封止樹脂４に積層されている。第１絶縁層１１は、各半導体素子３の素子主面３ａおよび封止樹脂４の樹脂主面４ａに接し、絶縁層裏面１ｂを含んでいる。第２絶縁層１２は、第１絶縁層１１に接している。第３絶縁層１３は、第２絶縁層１２に接し、絶縁層主面１ａを含んでいる。 The insulating layer 1 includes a first insulating layer 11, a second insulating layer 12, and a third insulating layer 13. As shown in FIGS. 5 and 6, the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13 are laminated on the sealing resin 4 in this order. The first insulating layer 11 is in contact with the element main surface 3a of each semiconductor element 3 and the resin main surface 4a of the sealing resin 4, and includes the back surface 1b of the insulating layer. The second insulating layer 12 is in contact with the first insulating layer 11. The third insulating layer 13 is in contact with the second insulating layer 12 and includes the main surface 1a of the insulating layer.
　複数の接続配線２は、各外部端子６および各半導体素子３などを接続する導電体であり、半導体素子３に電力を供給したり、信号を入出力するための導電経路を構成している。複数の接続配線２は、図５および図６に示すように、絶縁層１の内部に配置されている。 The plurality of connection wirings 2 are conductors that connect each external terminal 6 and each semiconductor element 3, and form a conductive path for supplying electric power to the semiconductor element 3 and inputting / outputting signals. As shown in FIGS. 5 and 6, the plurality of connection wirings 2 are arranged inside the insulating layer 1.
　第１接続配線２１は、埋込部２１１および再配線部２１２を備えている。埋込部２１１は、図５および図７に示すように、第１絶縁層１１に全体が埋め込まれている。図７に示すように、埋込部２１１の側面はｚ方向に対して傾斜しており、埋込部２１１のｚ方向に直交する断面の面積が絶縁層裏面１ｂに近づくほど小さくなるテーパが形成されている。再配線部２１２は、図５および図７に示すように、第１絶縁層１１と第２絶縁層１２との間に配置されている。再配線部２１２は、埋込部２１１につながっている。再配線部２１２は、図２に示すように、ｚ方向視において、半導体素子３０１の出力電極３２を避ける櫛歯形状になっている。当該形状は、第３接続配線２３の後述する埋込部２３１を出力電極３２に接続させるように形成するための形状である。再配線部２１２は、櫛歯形状ではなく、出力電極３２に接続する埋込部２３１を配置させるための貫通孔が形成された形状であってもよい。図２に示すように、第１接続配線２１の再配線部２１２は、ｚ方向視において、一部が半導体素子３０１に重なっており、一部が半導体素子３０１よりも外方に位置する。 The first connection wiring 21 includes an embedded portion 211 and a rewiring portion 212. As shown in FIGS. 5 and 7, the embedded portion 211 is entirely embedded in the first insulating layer 11. As shown in FIG. 7, the side surface of the embedded portion 211 is inclined with respect to the z direction, and a taper is formed in which the area of the cross section of the embedded portion 211 orthogonal to the z direction becomes smaller as it approaches the back surface 1b of the insulating layer. Has been done. As shown in FIGS. 5 and 7, the rewiring portion 212 is arranged between the first insulating layer 11 and the second insulating layer 12. The rewiring portion 212 is connected to the embedded portion 211. As shown in FIG. 2, the rewiring portion 212 has a comb-teeth shape that avoids the output electrode 32 of the semiconductor element 301 in the z-direction view. The shape is a shape for forming the embedded portion 231 of the third connection wiring 23, which will be described later, so as to be connected to the output electrode 32. The rewiring portion 212 may not have a comb-teeth shape but may have a shape in which a through hole for arranging the embedded portion 231 connected to the output electrode 32 is formed. As shown in FIG. 2, the rewiring portion 212 of the first connection wiring 21 partially overlaps the semiconductor element 301 and is partially located outside the semiconductor element 301 in the z-direction view.
　図７に示すように、埋込部２１１および再配線部２１２の各々は、下地層２０１およびめっき層２０２を有する。下地層２０１は、第１絶縁層１１に含まれる添加剤に含有された金属元素により組成され、第１絶縁層１１に接している。めっき層２０２は、たとえば銅（Ｃｕ）を含む材料からなり、下地層２０１に接している。埋込部２１１の下地層２０１は、第１絶縁層１１に接している。埋込部２１１のめっき層２０２は、埋込部２１１の下地層２０１によって囲まれている。再配線部２１２の下地層２０１は、第１絶縁層１１に接している。再配線部２１２のめっき層２０２は、再配線部２１２の下地層２０１を覆い、再配線部２１２の下地層２０１および第２絶縁層１２によって囲まれている。 As shown in FIG. 7, each of the embedded portion 211 and the rewiring portion 212 has a base layer 201 and a plating layer 202. The base layer 201 is composed of a metal element contained in the additive contained in the first insulating layer 11, and is in contact with the first insulating layer 11. The plating layer 202 is made of, for example, a material containing copper (Cu) and is in contact with the base layer 201. The base layer 201 of the embedded portion 211 is in contact with the first insulating layer 11. The plating layer 202 of the embedded portion 211 is surrounded by the base layer 201 of the embedded portion 211. The base layer 201 of the rewiring portion 212 is in contact with the first insulating layer 11. The plating layer 202 of the rewiring portion 212 covers the base layer 201 of the rewiring portion 212 and is surrounded by the base layer 201 of the rewiring portion 212 and the second insulating layer 12.
　第２接続配線２２は、埋込部２２１および再配線部２２２を備えている。埋込部２２１は、図６に示すように、第１絶縁層１１に全体が埋め込まれている。埋込部２２１の形状は、埋込部２１１と同様である。再配線部２２２は、図５および図６に示すように、第１絶縁層１１と第２絶縁層１２との間に配置されている。再配線部２２２は、埋込部２２１につながっている。再配線部２２２は、図２に示すように、ｚ方向視において、半導体素子３０２の入力電極３１を避ける櫛歯形状になっている。当該形状は、第３接続配線２３の埋込部２３１を入力電極３１に接続させるように形成するための形状である。再配線部２２２は、櫛歯形状ではなく、入力電極３１に接続する埋込部２３１を配置させるための貫通孔が形成された形状であってもよい。図２、図５、および図６に示すように、再配線部２２２は、複数の貫通孔２２２ａを備えている。各貫通孔２２２ａは、再配線部２２２をｚ方向に貫通させる孔であり、ｚ方向視において第３外部端子６３に重なる位置に配置されている。貫通孔２２２ａには、第３接続配線２３の後述する埋込部２３１が配置されている。図２に示すように、第２接続配線２２の再配線部２２２は、ｚ方向視において、一部が半導体素子３０２に重なっており、一部が半導体素子３０２よりも外方に位置する。埋込部２２１および再配線部２２２の各々は、埋込部２１１および再配線部２１２と同様に、下地層２０１およびめっき層２０２を有する。 The second connection wiring 22 includes an embedded portion 221 and a rewiring portion 222. As shown in FIG. 6, the embedded portion 221 is entirely embedded in the first insulating layer 11. The shape of the embedded portion 221 is the same as that of the embedded portion 211. As shown in FIGS. 5 and 6, the rewiring portion 222 is arranged between the first insulating layer 11 and the second insulating layer 12. The rewiring portion 222 is connected to the embedded portion 221. As shown in FIG. 2, the rewiring portion 222 has a comb-teeth shape that avoids the input electrode 31 of the semiconductor element 302 in the z-direction view. The shape is a shape for forming the embedded portion 231 of the third connection wiring 23 so as to be connected to the input electrode 31. The rewiring portion 222 may not have a comb-teeth shape but may have a shape in which a through hole for arranging the embedded portion 231 connected to the input electrode 31 is formed. As shown in FIGS. 2, 5, and 6, the rewiring portion 222 includes a plurality of through holes 222a. Each through hole 222a is a hole through which the rewiring portion 222 penetrates in the z direction, and is arranged at a position overlapping the third external terminal 63 in the z direction view. An embedded portion 231 of the third connection wiring 23, which will be described later, is arranged in the through hole 222a. As shown in FIG. 2, the rewiring portion 222 of the second connection wiring 22 partially overlaps the semiconductor element 302 and is partially located outside the semiconductor element 302 in the z-direction view. Each of the embedded portion 221 and the rewiring portion 222 has a base layer 201 and a plating layer 202, similarly to the embedded portion 211 and the rewiring portion 212.
　接続配線２６は、埋込部２６１および再配線部２６２を備えている。埋込部２６１は、第１絶縁層１１に全体が埋め込まれている。埋込部２６１の形状は、埋込部２１１と同様である。再配線部２６２は、第１絶縁層１１と第２絶縁層１２との間に配置されている。再配線部２６２は、埋込部２６１につながっている。図２に示すように、接続配線２６の再配線部２６２は、ｚ方向視において、一部が半導体素子３０１に重なっており、一部が半導体素子３０１よりも外方に位置する。埋込部２６１および再配線部２６２の各々は、埋込部２１１および再配線部２１２と同様に、下地層２０１およびめっき層２０２を有する。 The connection wiring 26 includes an embedded portion 261 and a rewiring portion 262. The entire embedded portion 261 is embedded in the first insulating layer 11. The shape of the embedded portion 261 is the same as that of the embedded portion 211. The rewiring portion 262 is arranged between the first insulating layer 11 and the second insulating layer 12. The rewiring portion 262 is connected to the embedded portion 261. As shown in FIG. 2, the rewiring portion 262 of the connection wiring 26 partially overlaps the semiconductor element 301 and is partially located outside the semiconductor element 301 in the z-direction view. Each of the embedded portion 261 and the rewiring portion 262 has a base layer 201 and a plating layer 202, similarly to the embedded portion 211 and the rewiring portion 212.
　接続配線２７は、埋込部２７１および再配線部２７２を備えている。埋込部２７１は、第１絶縁層１１に全体が埋め込まれている。埋込部２７１の形状は、埋込部２１１と同様である。再配線部２７２は、第１絶縁層１１と第２絶縁層１２との間に配置されている。再配線部２７２は、埋込部２７１につながっている。図２に示すように、接続配線２７の再配線部２７２は、ｚ方向視において、一部が半導体素子３０２に重なっており、一部が半導体素子３０２よりも外方に位置する。埋込部２７１および再配線部２７２の各々は、埋込部２１１および再配線部２１２と同様に、下地層２０１およびめっき層２０２を有する。 The connection wiring 27 includes an embedded portion 271 and a rewiring portion 272. The entire embedded portion 271 is embedded in the first insulating layer 11. The shape of the embedded portion 271 is the same as that of the embedded portion 211. The rewiring portion 272 is arranged between the first insulating layer 11 and the second insulating layer 12. The rewiring portion 272 is connected to the embedded portion 271. As shown in FIG. 2, the rewiring portion 272 of the connection wiring 27 partially overlaps the semiconductor element 302 and is partially located outside the semiconductor element 302 in the z-direction view. Each of the embedded portion 271 and the rewiring portion 272 has a base layer 201 and a plating layer 202, similarly to the embedded portion 211 and the rewiring portion 212.
　第３接続配線２３は、埋込部２３１および再配線部２３２を備えている。埋込部２３１は、図５および図６に示すように、第１絶縁層１１および第２絶縁層１２を貫いて全体が埋め込まれている。また、埋込部２３１は、ｚ方向視において、再配線部２１２および再配線部２２２に重ならないように配置されている。第３外部端子６３に接続する埋込部２３１は、再配線部２２２の貫通孔２２２ａの内側に配置されている。半導体素子３０１の出力電極３２に接続する埋込部２３１は、再配線部２１２の櫛歯の隙間に配置されている。半導体素子３０２の入力電極３１に接続する埋込部２３１は、再配線部２２２の櫛歯の隙間に配置されている。埋込部２３１の形状は、埋込部２１１と同様である。再配線部２３２は、図５および図６に示すように、第２絶縁層１２と第３絶縁層１３との間に配置されている。再配線部２３２は、埋込部２３１につながっている。再配線部２３２は、図１に示すように、ｚ方向視矩形状である。再配線部２３２のｚ方向視形状は、特に限定されず、すべての埋込部２３１に重なる形状であればよい。図１に示すように、第３接続配線２３の再配線部２３２は、ｚ方向視において、一部が半導体素子３０１および半導体素子３０２に重なっており、一部が半導体素子３０１および半導体素子３０２よりも外方（本実施形態では、半導体素子３０１と半導体素子３０２との間）に位置する。埋込部２３１および再配線部２３２の各々は、埋込部２１１および再配線部２１２と同様に、下地層２０１およびめっき層２０２を有する。 The third connection wiring 23 includes an embedded portion 231 and a rewiring portion 232. As shown in FIGS. 5 and 6, the embedded portion 231 is entirely embedded through the first insulating layer 11 and the second insulating layer 12. Further, the embedded portion 231 is arranged so as not to overlap the rewiring portion 212 and the rewiring portion 222 in the z-direction view. The embedded portion 231 connected to the third external terminal 63 is arranged inside the through hole 222a of the rewiring portion 222. The embedded portion 231 connected to the output electrode 32 of the semiconductor element 301 is arranged in the gap between the comb teeth of the rewiring portion 212. The embedded portion 231 connected to the input electrode 31 of the semiconductor element 302 is arranged in the gap between the comb teeth of the rewiring portion 222. The shape of the embedded portion 231 is the same as that of the embedded portion 211. As shown in FIGS. 5 and 6, the rewiring portion 232 is arranged between the second insulating layer 12 and the third insulating layer 13. The rewiring portion 232 is connected to the embedded portion 231. As shown in FIG. 1, the rewiring portion 232 has a rectangular shape in the z-direction. The z-direction view shape of the rewiring portion 232 is not particularly limited, and may be a shape that overlaps all the embedded portions 231. As shown in FIG. 1, the rewiring portion 232 of the third connection wiring 23 partially overlaps the semiconductor element 301 and the semiconductor element 302 in the z-direction view, and partly from the semiconductor element 301 and the semiconductor element 302. Is also located on the outside (in this embodiment, between the semiconductor element 301 and the semiconductor element 302). Each of the embedded portion 231 and the rewiring portion 232 has a base layer 201 and a plating layer 202, similarly to the embedded portion 211 and the rewiring portion 212.
　半導体装置Ａ１は、ｚ方向視において、半導体素子３にのみ重なっており、半導体素子３よりも外方に位置する部分がない再配線部、または、半導体素子３よりも外方にのみ位置する再配線部を含んでいてもよい。 The semiconductor device A1 is a rewiring portion that overlaps only the semiconductor element 3 in the z-direction view and has no portion located outside the semiconductor element 3, or a rewiring portion located only outside the semiconductor element 3. It may include a wiring part.
　次に、半導体装置Ａ１の製造方法の一例について、図８～図１８を参照しつつ以下に説明する。図８～図１９はそれぞれ、半導体装置Ａ１の製造方法の一例の一工程を示す図である。図８～図１０、図１３、図１５、図１６、図１８、図１９は断面図であり、図５に対応する図である。図１１は、図１０の部分拡大図であり、図７に対応する図である。図１２は、平面図であり、図２に対応する図である。図１４は、図１３の部分拡大図であり、図７に対応する図である。図１７は、平面図であり、図１に対応する図である。 Next, an example of the manufacturing method of the semiconductor device A1 will be described below with reference to FIGS. 8 to 18. 8 to 19 are diagrams showing one step of an example of a manufacturing method of the semiconductor device A1, respectively. 8 to 10, FIG. 13, FIG. 15, FIG. 16, FIG. 18, and FIG. 19 are cross-sectional views, which correspond to FIGS. 5. FIG. 11 is a partially enlarged view of FIG. 10, which corresponds to FIG. 7. FIG. 12 is a plan view and is a view corresponding to FIG. FIG. 14 is a partially enlarged view of FIG. 13, which corresponds to FIG. 7. FIG. 17 is a plan view and is a view corresponding to FIG.
　まず、図８に示すように、ヒートスプレッダ５が接合された半導体素子３、および外部端子６を封止樹脂８１に埋め込む。封止樹脂８１は、黒色のエポキシ樹脂を含む材料からなる。半導体素子３は、素子主面３ａに入力電極３１、出力電極３２、および制御電極３３が配置されており、素子裏面３ｂにヒートスプレッダ５が接合されている。本工程においては、金型内に封止樹脂８１の材料と、ヒートスプレッダ５が接合された半導体素子３および外部端子６とを配置した後、コンプレッション成形を行う。この際、入力電極３１、出力電極３２、制御電極３３、およびヒートスプレッダ５のスプレッダ裏面５ｂが封止樹脂８１から露出するようにする。 First, as shown in FIG. 8, the semiconductor element 3 to which the heat spreader 5 is bonded and the external terminal 6 are embedded in the sealing resin 81. The sealing resin 81 is made of a material containing a black epoxy resin. In the semiconductor element 3, an input electrode 31, an output electrode 32, and a control electrode 33 are arranged on the element main surface 3a, and a heat spreader 5 is bonded to the element back surface 3b. In this step, compression molding is performed after arranging the material of the sealing resin 81, the semiconductor element 3 to which the heat spreader 5 is bonded, and the external terminal 6 in the mold. At this time, the input electrode 31, the output electrode 32, the control electrode 33, and the spreader back surface 5b of the heat spreader 5 are exposed from the sealing resin 81.
　次いで、図９に示すように、封止樹脂８１に積層され、かつ半導体素子３の入力電極３１、出力電極３２、および制御電極３３を覆う第１絶縁層８２を形成する。第１絶縁層８２は、熱硬化性の合成樹脂、および複数の接続配線８３（詳細は後述）の一部を組成する金属元素が含有された添加剤を含む材料からなる。当該合成樹脂は、たとえばエポキシ樹脂やポリイミド樹脂である。第１絶縁層８２は、コンプレッション成形により形成される。 Next, as shown in FIG. 9, a first insulating layer 82 is formed, which is laminated on the sealing resin 81 and covers the input electrode 31, the output electrode 32, and the control electrode 33 of the semiconductor element 3. The first insulating layer 82 is made of a material containing a thermosetting synthetic resin and an additive containing a metal element that constitutes a part of a plurality of connection wirings 83 (details will be described later). The synthetic resin is, for example, an epoxy resin or a polyimide resin. The first insulating layer 82 is formed by compression molding.
　次いで、図１０～図１４に示すように、半導体素子３の入力電極３１、出力電極３２、制御電極３３、または外部端子６につながる複数の接続配線８３を形成する。複数の接続配線８３が、半導体装置Ａ１の第１接続配線２１、第２接続配線２２、接続配線２６，２７に相当する。図１４に示すように、複数の接続配線８３の各々は、埋込部８３１および再配線部８３２を有する。埋込部８３１は、第１絶縁層８２に埋め込まれ、かつ、入力電極３１、出力電極３２、制御電極３３、または外部端子６のいずれかにつながる。再配線部８３２は、第１絶縁層８２の上に配置され、かつ、埋込部８３１につながる。図１４に示すように、複数の接続配線８３の埋込部８３１および再配線部８３２の各々は、下地層８３Ａおよびめっき層８３Ｂを有する。複数の接続配線８３を形成する工程は、第１絶縁層８２の表面に下地層８３Ａを析出させる工程と、下地層８３Ａを覆うめっき層８３Ｂを形成する工程とを含む。 Next, as shown in FIGS. 10 to 14, a plurality of connection wirings 83 connected to the input electrode 31, the output electrode 32, the control electrode 33, or the external terminal 6 of the semiconductor element 3 are formed. The plurality of connection wirings 83 correspond to the first connection wiring 21, the second connection wiring 22, and the connection wirings 26 and 27 of the semiconductor device A1. As shown in FIG. 14, each of the plurality of connection wirings 83 has an embedded portion 831 and a rewiring portion 832. The embedded portion 831 is embedded in the first insulating layer 82 and is connected to any of the input electrode 31, the output electrode 32, the control electrode 33, or the external terminal 6. The rewiring portion 832 is arranged on the first insulating layer 82 and is connected to the embedded portion 831. As shown in FIG. 14, each of the embedded portion 831 and the rewiring portion 832 of the plurality of connecting wirings 83 has a base layer 83A and a plating layer 83B. The step of forming the plurality of connection wirings 83 includes a step of depositing the base layer 83A on the surface of the first insulating layer 82 and a step of forming a plating layer 83B covering the base layer 83A.
　まず、図１１に示すように、第１絶縁層８２の表面に下地層８３Ａを析出させる。本工程では、図１０および図１２に示すように、複数の孔８２１および複数の凹部８２２をレーザにより第１絶縁層８２に形成する。複数の孔８２１は、第１絶縁層８２をｚ方向に貫通している。複数の孔８２１から、入力電極３１、出力電極３２、制御電極３３、および外部端子６が個別に露出している。複数の孔８２１は、入力電極３１、出力電極３２、制御電極３３、および外部端子６の位置を赤外線カメラなどにより画像認識しつつ、入力電極３１、出力電極３２、制御電極３３、および外部端子６が露出するまで第１絶縁層８２にレーザを照射させることにより形成される。レーザが照射される位置は、画像認識により得られた入力電極３１、出力電極３２、制御電極３３、および外部端子６の位置情報に基づき、逐一補正される。複数の凹部８２２は、第１絶縁層８２の表面から凹み、かつ複数の孔８２１につながっている。複数の凹部８２２は、第１絶縁層８２の表面にレーザを照射させることにより形成される。なお、当該レーザは、たとえば波長が３５５ｎｍ、かつビームの直径が１７μｍの紫外線レーザである。複数の孔８２１および複数の凹部８２２を第１絶縁層８２に形成することにより、図１１に示すように、複数の孔８２１の各々を規定する壁面と、複数の凹部８２２とを覆う下地層８３Ａが析出される。下地層８３Ａは、第１絶縁層８２に含まれる添加剤に含有された金属元素により組成される。レーザ照射により当該添加剤に含有された金属元素が励起される。これにより、当該金属元素を含む金属層が下地層８３Ａとして析出される。 First, as shown in FIG. 11, the base layer 83A is deposited on the surface of the first insulating layer 82. In this step, as shown in FIGS. 10 and 12, a plurality of holes 821 and a plurality of recesses 822 are formed in the first insulating layer 82 by a laser. The plurality of holes 821 penetrate the first insulating layer 82 in the z direction. The input electrode 31, the output electrode 32, the control electrode 33, and the external terminal 6 are individually exposed from the plurality of holes 821. The plurality of holes 821 have the input electrode 31, the output electrode 32, the control electrode 33, and the external terminal 6 while recognizing the positions of the input electrode 31, the output electrode 32, the control electrode 33, and the external terminal 6 by an infrared camera or the like. Is formed by irradiating the first insulating layer 82 with a laser until the first insulating layer 82 is exposed. The position where the laser is irradiated is corrected one by one based on the position information of the input electrode 31, the output electrode 32, the control electrode 33, and the external terminal 6 obtained by image recognition. The plurality of recesses 822 are recessed from the surface of the first insulating layer 82 and are connected to the plurality of holes 821. The plurality of recesses 822 are formed by irradiating the surface of the first insulating layer 82 with a laser. The laser is, for example, an ultraviolet laser having a wavelength of 355 nm and a beam diameter of 17 μm. By forming the plurality of holes 821 and the plurality of recesses 822 in the first insulating layer 82, as shown in FIG. 11, the base layer 83A covering the wall surface defining each of the plurality of holes 821 and the plurality of recesses 822. Is deposited. The base layer 83A is composed of metal elements contained in the additive contained in the first insulating layer 82. The metal element contained in the additive is excited by laser irradiation. As a result, the metal layer containing the metal element is precipitated as the base layer 83A.
　次いで、図１４に示すように、下地層８３Ａを覆うめっき層８３Ｂを形成する。めっき層８３Ｂは、銅を含む材料からなる。めっき層８３Ｂは、無電解めっきにより形成される。これにより、図１３に示すように、複数の孔８２１の各々には、埋込部８３１が形成される。あわせて、複数の凹部８２２の各々には、再配線部８３２が形成される。以上により、複数の接続配線８３の形成がなされる。 Next, as shown in FIG. 14, a plating layer 83B covering the base layer 83A is formed. The plating layer 83B is made of a material containing copper. The plating layer 83B is formed by electroless plating. As a result, as shown in FIG. 13, an embedded portion 831 is formed in each of the plurality of holes 821. In addition, a rewiring portion 832 is formed in each of the plurality of recesses 822. As described above, a plurality of connection wirings 83 are formed.
　次いで、図１５に示すように、第１絶縁層８２に積層され、かつ複数の接続配線８３を覆う第２絶縁層８４を形成する。第２絶縁層８４は、第１絶縁層８２と同じ材料からなる。第２絶縁層８４は、コンプレッション成形により形成される。 Next, as shown in FIG. 15, a second insulating layer 84 is formed which is laminated on the first insulating layer 82 and covers the plurality of connection wirings 83. The second insulating layer 84 is made of the same material as the first insulating layer 82. The second insulating layer 84 is formed by compression molding.
　次いで、図１６～図１８に示すように、半導体素子３の入力電極３１、出力電極３２、または第３外部端子６３につながる接続配線８５を形成する。接続配線８５が、半導体装置Ａ１の第３接続配線２３に相当する。図１８に示すように、接続配線８５は、埋込部８５１および再配線部８５２を有する。埋込部８５１は、第１絶縁層８２および第２絶縁層８４を貫いて全体が埋め込まれ、かつ、入力電極３１、出力電極３２、または第３外部端子６３のいずれかにつながる。再配線部８５２は第２絶縁層８４の上に配置され、かつ、埋込部８５１につながる。接続配線８５の埋込部８５１および再配線部８５２の各々は、埋込部８３１および再配線部８３２と同様に、下地層およびめっき層を有する。接続配線８５を形成する工程は、第２絶縁層８４の表面に下地層を析出させる工程と、下地層を覆うめっき層を形成する工程とを含む。 Next, as shown in FIGS. 16 to 18, the connection wiring 85 connected to the input electrode 31, the output electrode 32, or the third external terminal 63 of the semiconductor element 3 is formed. The connection wiring 85 corresponds to the third connection wiring 23 of the semiconductor device A1. As shown in FIG. 18, the connection wiring 85 has an embedded portion 851 and a rewiring portion 852. The embedded portion 851 is entirely embedded through the first insulating layer 82 and the second insulating layer 84, and is connected to any of the input electrode 31, the output electrode 32, or the third external terminal 63. The rewiring portion 852 is arranged on the second insulating layer 84 and is connected to the embedded portion 851. Each of the embedded portion 851 and the rewiring portion 852 of the connecting wiring 85 has a base layer and a plating layer, similarly to the embedded portion 831 and the rewiring portion 832. The step of forming the connection wiring 85 includes a step of precipitating a base layer on the surface of the second insulating layer 84 and a step of forming a plating layer covering the base layer.
　まず、第２絶縁層８４の表面に下地層を析出させる。本工程では、図１６および図１７に示すように、複数の孔８４１および凹部８４２をレーザにより第２絶縁層８４に形成する。複数の孔８４１は、第２絶縁層８４をｚ方向に貫通している。複数の孔８４１から、入力電極３１、出力電極３２、および第３外部端子６３が個別に露出している。複数の孔８４１は、入力電極３１、出力電極３２、および第３外部端子６３の位置を赤外線カメラなどにより画像認識しつつ、入力電極３１、出力電極３２、および第３外部端子６３が露出するまで第２絶縁層８４にレーザを照射させることにより形成される。レーザが照射される位置は、画像認識により得られた入力電極３１、出力電極３２、および第３外部端子６３の位置情報に基づき、逐一補正される。凹部８４２は、第２絶縁層８４の表面から凹み、かつ複数の孔８４１につながっている。凹部８４２は、第２絶縁層８４の表面にレーザを照射させることにより形成される。なお、当該レーザは、たとえば波長が３５５ｎｍ、かつビームの直径が１７μｍの紫外線レーザである。複数の孔８４１および凹部８４２を第２絶縁層８４に形成することにより、複数の孔８４１の各々を規定する壁面と、凹部８４２とを覆う下地層が析出される。下地層は、第２絶縁層８４に含まれる添加剤に含有された金属元素により組成される。レーザ照射により当該添加剤に含有された金属元素が励起される。これにより、当該金属元素を含む金属層が下地層として析出される。 First, a base layer is deposited on the surface of the second insulating layer 84. In this step, as shown in FIGS. 16 and 17, a plurality of holes 841 and recesses 842 are formed in the second insulating layer 84 by a laser. The plurality of holes 841 penetrate the second insulating layer 84 in the z direction. The input electrode 31, the output electrode 32, and the third external terminal 63 are individually exposed from the plurality of holes 841. The plurality of holes 841 recognize the positions of the input electrode 31, the output electrode 32, and the third external terminal 63 by an infrared camera or the like, and until the input electrode 31, the output electrode 32, and the third external terminal 63 are exposed. It is formed by irradiating the second insulating layer 84 with a laser. The position where the laser is irradiated is corrected one by one based on the position information of the input electrode 31, the output electrode 32, and the third external terminal 63 obtained by image recognition. The recess 842 is recessed from the surface of the second insulating layer 84 and is connected to a plurality of holes 841. The recess 842 is formed by irradiating the surface of the second insulating layer 84 with a laser. The laser is, for example, an ultraviolet laser having a wavelength of 355 nm and a beam diameter of 17 μm. By forming the plurality of holes 841 and the recess 842 in the second insulating layer 84, a wall surface defining each of the plurality of holes 841 and a base layer covering the recess 842 are deposited. The base layer is composed of metal elements contained in the additive contained in the second insulating layer 84. The metal element contained in the additive is excited by laser irradiation. As a result, the metal layer containing the metal element is precipitated as the base layer.
　次いで、下地層を覆うめっき層を形成する。めっき層は、銅を含む材料からなる。めっき層は、無電解めっきにより形成される。これにより、図１８に示すように、複数の孔８４１の各々には、埋込部８５１が形成される。あわせて、凹部８４２には、再配線部８５２が形成される。以上により、複数の接続配線８５の形成がなされる。 Next, a plating layer covering the base layer is formed. The plating layer is made of a material containing copper. The plating layer is formed by electroless plating. As a result, as shown in FIG. 18, an embedded portion 851 is formed in each of the plurality of holes 841. At the same time, a rewiring portion 852 is formed in the recess 842. As described above, a plurality of connection wirings 85 are formed.
　次いで、図１９に示すように、第２絶縁層８４に積層され、かつ複数の接続配線８５を覆う第３絶縁層８６を形成する。第３絶縁層８６は、第１絶縁層８２と同じ材料からなる。第３絶縁層８６は、コンプレッション成形により形成される。 Next, as shown in FIG. 19, a third insulating layer 86 is formed which is laminated on the second insulating layer 84 and covers the plurality of connection wirings 85. The third insulating layer 86 is made of the same material as the first insulating layer 82. The third insulating layer 86 is formed by compression molding.
　最後に、封止樹脂８１、第１絶縁層８２、第２絶縁層８４、および第３絶縁層８６を所定の切断線に沿ってダイシングブレードなどで切断することにより、複数の個片に分割する。当該個片は、２個の半導体素子３と、これらにつながる複数の接続配線８３，８５、および複数の外部端子６とが含まれるようにする。本工程により個片となった封止樹脂８１、第１絶縁層８２、第２絶縁層８４、および第３絶縁層８６が、それぞれ、半導体装置Ａ１の封止樹脂４、第１絶縁層１１、第２絶縁層１２、および第３絶縁層１３に相当する。以上の工程を経ることにより、半導体装置Ａ１が製造される。 Finally, the sealing resin 81, the first insulating layer 82, the second insulating layer 84, and the third insulating layer 86 are divided into a plurality of pieces by cutting along a predetermined cutting line with a dicing blade or the like. .. The piece is configured to include two semiconductor elements 3, a plurality of connection wires 83, 85 connected to them, and a plurality of external terminals 6. The sealing resin 81, the first insulating layer 82, the second insulating layer 84, and the third insulating layer 86, which are individually formed by this step, are the sealing resin 4 and the first insulating layer 11 of the semiconductor device A1, respectively. It corresponds to the second insulating layer 12 and the third insulating layer 13. Through the above steps, the semiconductor device A1 is manufactured.
　図２０～図２３は、半導体装置Ａ１を示す模式図であり、半導体装置Ａ１内の電流の流れを示している。図２０は、半導体素子３０１がＯＮ状態であり、半導体素子３０２がＯＦＦ状態のときの電流の流れを示している。第１外部端子６１から入力された電流は、第１接続配線２１を流れて、半導体素子３０１の入力電極３１に入力される。そして、電流は、半導体素子３０１内を入力電極３１から出力電極３２に流れて出力される。半導体素子３０１の出力電極３２から出力された電流は、第３接続配線２３を流れて、第３外部端子６３から出力される。 20 to 23 are schematic views showing the semiconductor device A1 and show the current flow in the semiconductor device A1. FIG. 20 shows the current flow when the semiconductor element 301 is in the ON state and the semiconductor element 302 is in the OFF state. The current input from the first external terminal 61 flows through the first connection wiring 21 and is input to the input electrode 31 of the semiconductor element 301. Then, the current flows from the input electrode 31 to the output electrode 32 in the semiconductor element 301 and is output. The current output from the output electrode 32 of the semiconductor element 301 flows through the third connection wiring 23 and is output from the third external terminal 63.
　図２１は、図２０の状態から、半導体素子３０１がＯＦＦ状態に切り替えられたときの電流の流れを示している。半導体素子３０１がＯＦＦ状態に切り替えられても、負荷のインダクタンスにより、第３外部端子６３からの出力電流は継続し、負荷から第２外部端子６２に電流が入力される。第２外部端子６２から入力された電流は、第２接続配線２２を流れて、半導体素子３０２の出力電極３２に入力される。そして、電流は、出力電極３２と入力電極３１とに逆並列接続されたダイオード（図示なし）を流れて、入力電極３１から出力される。半導体素子３０２の入力電極３１から出力された電流は、第３接続配線２３を流れて、第３外部端子６３から出力される。第３外部端子６３から出力される電流は徐々に減少する。 FIG. 21 shows the current flow when the semiconductor element 301 is switched from the state of FIG. 20 to the OFF state. Even if the semiconductor element 301 is switched to the OFF state, the output current from the third external terminal 63 continues due to the inductance of the load, and the current is input from the load to the second external terminal 62. The current input from the second external terminal 62 flows through the second connection wiring 22 and is input to the output electrode 32 of the semiconductor element 302. Then, the current flows through a diode (not shown) connected in antiparallel to the output electrode 32 and the input electrode 31, and is output from the input electrode 31. The current output from the input electrode 31 of the semiconductor element 302 flows through the third connection wiring 23 and is output from the third external terminal 63. The current output from the third external terminal 63 gradually decreases.
　図２２は、図２１の状態から、第３外部端子６３から出力される電流が「０」になったタイミングで、半導体素子３０２がＯＮ状態に切り替えられた後の電流の流れを示している。第３外部端子６３から入力された電流は、第３接続配線２３を流れて、半導体素子３０２の入力電極３１に入力される。そして、電流は、半導体素子３０２内を入力電極３１から出力電極３２に流れて出力される。半導体素子３０２の出力電極３２から出力された電流は、第２接続配線２２を流れて、第２外部端子６２から出力される。 FIG. 22 shows the current flow after the semiconductor element 302 is switched to the ON state at the timing when the current output from the third external terminal 63 becomes “0” from the state of FIG. 21. The current input from the third external terminal 63 flows through the third connection wiring 23 and is input to the input electrode 31 of the semiconductor element 302. Then, the current flows from the input electrode 31 to the output electrode 32 in the semiconductor element 302 and is output. The current output from the output electrode 32 of the semiconductor element 302 flows through the second connection wiring 22 and is output from the second external terminal 62.
　図２３は、図２２の状態から、半導体素子３０２がＯＦＦ状態に切り替えられたときの電流の流れを示している。半導体素子３０２がＯＦＦ状態に切り替えられても、負荷のインダクタンスにより、第３外部端子６３への入力電流は継続し、負荷から第３外部端子６３に電流が入力される。第３外部端子６３から入力された電流は、第３接続配線２３を流れて、半導体素子３０１の出力電極３２に入力される。そして、電流は、出力電極３２と入力電極３１とに逆並列接続されたダイオード（図示なし）を流れて、入力電極３１から出力される。半導体素子３０１の入力電極３１から出力された電流は、第１接続配線２１を流れて、第１外部端子６１から出力される。第１外部端子６１から出力される電流は徐々に減少する。そして、第３外部端子６３に入力される電流が「０」になったタイミングで、半導体素子３０１がＯＮ状態に切り替えられて、図２０の状態になる。図２０～図２３の状態が繰り返されることで、第３外部端子６３から負荷に、スイッチング信号が出力される。 FIG. 23 shows the current flow when the semiconductor element 302 is switched from the state of FIG. 22 to the OFF state. Even if the semiconductor element 302 is switched to the OFF state, the input current to the third external terminal 63 continues due to the inductance of the load, and the current is input from the load to the third external terminal 63. The current input from the third external terminal 63 flows through the third connection wiring 23 and is input to the output electrode 32 of the semiconductor element 301. Then, the current flows through a diode (not shown) connected in antiparallel to the output electrode 32 and the input electrode 31, and is output from the input electrode 31. The current output from the input electrode 31 of the semiconductor element 301 flows through the first connection wiring 21 and is output from the first external terminal 61. The current output from the first external terminal 61 gradually decreases. Then, at the timing when the current input to the third external terminal 63 becomes “0”, the semiconductor element 301 is switched to the ON state, and the state shown in FIG. 20 is reached. By repeating the states of FIGS. 20 to 23, a switching signal is output from the third external terminal 63 to the load.
　次に、半導体装置Ａ１の作用効果について説明する。 Next, the action and effect of the semiconductor device A1 will be described.
　本実施形態によると、半導体装置Ａ１は、第１接続配線２１を介して半導体素子３０１の入力電極３１に導通する第１外部端子６１と、第２接続配線２２を介して半導体素子３０２の出力電極３２に導通する第２外部端子６２とを備えている。第１外部端子６１および第２外部端子６２は、半導体素子３０１と半導体素子３０２との間に配置され、各々が 樹脂裏面４ｂから露出している。半導体装置Ａ１を配線基板に実装する際、第１外部端子６１および第２外部端子６２は、配線基板の配線に接合される。第１外部端子６１はＶｉｎ端子として機能し、第２外部端子６２はＰＧＮＤ端子として機能し、第１外部端子６１と第２外部端子６２との間には、外部から直流電圧が印加される。これにより、第１外部端子６１から、第１接続配線２１、半導体素子３０１、第３接続配線２３、半導体素子３０２、および第２接続配線２２を介して、第２外部端子６２につながる電流経路のループの面積（磁界発生面積）を小さくできる。したがって、当該電流経路のインダクタンスを抑制できる。電流経路のインダクタンスが抑制されることで、電流経路に蓄積される電気エネルギが抑制され、半導体素子３０１または半導体素子３０２がＯＮ状態に切り替えられるときに発生するサージ電圧を抑制できる。 According to the present embodiment, the semiconductor device A1 has a first external terminal 61 that conducts to the input electrode 31 of the semiconductor element 301 via the first connection wiring 21, and an output electrode of the semiconductor element 302 via the second connection wiring 22. It is provided with a second external terminal 62 that conducts to 32. The first external terminal 61 and the second external terminal 62 are arranged between the semiconductor element 301 and the semiconductor element 302, and each is exposed from the resin back surface 4b. When the semiconductor device A1 is mounted on the wiring board, the first external terminal 61 and the second external terminal 62 are joined to the wiring of the wiring board. The first external terminal 61 functions as a Vin terminal, the second external terminal 62 functions as a PGND terminal, and a DC voltage is applied from the outside between the first external terminal 61 and the second external terminal 62. As a result, the current path from the first external terminal 61 to the second external terminal 62 via the first connection wiring 21, the semiconductor element 301, the third connection wiring 23, the semiconductor element 302, and the second connection wiring 22 The loop area (magnetic field generation area) can be reduced. Therefore, the inductance of the current path can be suppressed. By suppressing the inductance of the current path, the electric energy stored in the current path is suppressed, and the surge voltage generated when the semiconductor element 301 or the semiconductor element 302 is switched to the ON state can be suppressed.
　本実施形態によると、第１外部端子６１と第２外部端子６２とが隣接して配置されている。したがって、第１外部端子６１と第２外部端子６２との間に、第３外部端子６３が配置される場合と比較して、第１外部端子６１から、第１接続配線２１、半導体素子３０１、第３接続配線２３、半導体素子３０２、および第２接続配線２２を介して、第２外部端子６２につながる電流経路のループの面積（磁界発生面積）をより小さくできる。したがって、電流経路のインダクタンスをより抑制できる。なお、第３外部端子６３は、第２外部端子６２と半導体素子３０２との間ではなく、第１外部端子６１と半導体素子３０１との間に配置されてもよい。 According to this embodiment, the first external terminal 61 and the second external terminal 62 are arranged adjacent to each other. Therefore, as compared with the case where the third external terminal 63 is arranged between the first external terminal 61 and the second external terminal 62, from the first external terminal 61, the first connection wiring 21, the semiconductor element 301, The area (magnetic field generation area) of the loop of the current path connected to the second external terminal 62 via the third connection wiring 23, the semiconductor element 302, and the second connection wiring 22 can be made smaller. Therefore, the inductance of the current path can be further suppressed. The third external terminal 63 may be arranged not between the second external terminal 62 and the semiconductor element 302 but between the first external terminal 61 and the semiconductor element 301.
　本実施形態によると、図２０に示すように、半導体素子３０１がＯＮ状態で、半導体素子３０２がＯＦＦ状態のとき、第１外部端子６１では、電流は、樹脂裏面４ｂ側（図２０においては下側）から樹脂主面４ａ側（図２０においては上側）に流れる。一方、第３外部端子６３では、電流は、樹脂主面４ａ側から樹脂裏面４ｂ側に流れる。つまり、第１外部端子６１を流れる電流の向きと、第３外部端子６３を流れる電流の向きとでは、ｚ方向において互いに反対向きになる。これにより、第１外部端子６１を流れる電流により発生する磁場と、第３外部端子６３を流れる電流により発生する磁場とが打ち消し合うので、発生するインダクタンスは低減される。同様に、図２１に示すように、半導体素子３０１がＯＦＦ状態に切り替えられた場合、第２外部端子６２を流れる電流の向きと、第３外部端子６３を流れる電流の向きとでは、ｚ方向において互いに反対向きになる。これにより、第２外部端子６２を流れる電流により発生する磁場と、第３外部端子６３を流れる電流により発生する磁場とが打ち消し合うので、発生するインダクタンスは低減される。 According to the present embodiment, as shown in FIG. 20, when the semiconductor element 301 is in the ON state and the semiconductor element 302 is in the OFF state, the current at the first external terminal 61 is on the resin back surface 4b side (lower in FIG. 20). It flows from the side) to the resin main surface 4a side (upper side in FIG. 20). On the other hand, at the third external terminal 63, the current flows from the resin main surface 4a side to the resin back surface 4b side. That is, the direction of the current flowing through the first external terminal 61 and the direction of the current flowing through the third external terminal 63 are opposite to each other in the z direction. As a result, the magnetic field generated by the current flowing through the first external terminal 61 and the magnetic field generated by the current flowing through the third external terminal 63 cancel each other out, so that the generated inductance is reduced. Similarly, as shown in FIG. 21, when the semiconductor element 301 is switched to the OFF state, the direction of the current flowing through the second external terminal 62 and the direction of the current flowing through the third external terminal 63 are in the z direction. Opposite each other. As a result, the magnetic field generated by the current flowing through the second external terminal 62 and the magnetic field generated by the current flowing through the third external terminal 63 cancel each other out, so that the generated inductance is reduced.
　図２２に示すように、半導体素子３０１がＯＦＦ状態で、半導体素子３０２がＯＮ状態のとき、第２外部端子６２を流れる電流の向きと、第３外部端子６３を流れる電流の向きとでは、ｚ方向において互いに反対向きになる。これにより、第２外部端子６２を流れる電流により発生する磁場と、第３外部端子６３を流れる電流により発生する磁場とが打ち消し合うので、発生するインダクタンスは低減される。同様に、図２３に示すように、半導体素子３０２がＯＦＦ状態に切り替えられた場合、第１外部端子６１を流れる電流の向きと、第３外部端子６３を流れる電流の向きとでは、ｚ方向において互いに反対向きになる。これにより、第１外部端子６１を流れる電流により発生する磁場と、第３外部端子６３を流れる電流により発生する磁場とが打ち消し合うので、発生するインダクタンスは低減される。 As shown in FIG. 22, when the semiconductor element 301 is in the OFF state and the semiconductor element 302 is in the ON state, the direction of the current flowing through the second external terminal 62 and the direction of the current flowing through the third external terminal 63 are z. The directions are opposite to each other. As a result, the magnetic field generated by the current flowing through the second external terminal 62 and the magnetic field generated by the current flowing through the third external terminal 63 cancel each other out, so that the generated inductance is reduced. Similarly, as shown in FIG. 23, when the semiconductor element 302 is switched to the OFF state, the direction of the current flowing through the first external terminal 61 and the direction of the current flowing through the third external terminal 63 are in the z direction. Opposite each other. As a result, the magnetic field generated by the current flowing through the first external terminal 61 and the magnetic field generated by the current flowing through the third external terminal 63 cancel each other out, so that the generated inductance is reduced.
　本実施形態によると、第１外部端子６１、第２外部端子６２、および第３外部端子６３は、それぞれ、ｘ方向を厚さ方向とする板状であり、ｘ方向視において互いに大きな面積で重なっている。したがって、電流がｚ方向において互いに反対向きに流れることによる、インダクタンス低減の効果が大きい。 According to the present embodiment, the first external terminal 61, the second external terminal 62, and the third external terminal 63 each have a plate shape with the x direction as the thickness direction, and overlap each other in a large area in the x direction. ing. Therefore, the effect of reducing the inductance is great because the currents flow in opposite directions in the z direction.
　本実施形態によると、図２０に示すように、第１外部端子６１から入力された電流は、第１接続配線２１の再配線部２１２を、第１外部端子６１から半導体素子３０１に向かって流れる。一方、半導体素子３０１から出力された電流は、第３接続配線２３の再配線部２３２を、半導体素子３０１から半導体素子３０２に向かって流れる。つまり、再配線部２１２を流れる電流の向きと、再配線部２３２を流れる電流の向きとでは、ｘ方向において互いに反対向きになる。これにより、再配線部２１２を流れる電流により発生する磁場と、再配線部２３２を流れる電流により発生する磁場とが打ち消し合うので、発生するインダクタンスは低減される。同様に、図２３に示す状態でも、再配線部２１２を流れる電流の向きと、再配線部２３２を流れる電流の向きとでは、ｘ方向において互いに反対向きになるので、発生するインダクタンスは低減される。また、図２１および図２２に示すように、再配線部２２２を流れる電流の向きと、再配線部２３２を流れる電流の向きとでは、ｘ方向において互いに反対向きになる。これにより、再配線部２２２を流れる電流により発生する磁場と、再配線部２３２を流れる電流により発生する磁場とが打ち消し合うので、発生するインダクタンスは低減される。 According to the present embodiment, as shown in FIG. 20, the current input from the first external terminal 61 flows through the rewiring portion 212 of the first connection wiring 21 from the first external terminal 61 toward the semiconductor element 301. .. On the other hand, the current output from the semiconductor element 301 flows through the rewiring portion 232 of the third connection wiring 23 from the semiconductor element 301 toward the semiconductor element 302. That is, the direction of the current flowing through the rewiring unit 212 and the direction of the current flowing through the rewiring unit 232 are opposite to each other in the x direction. As a result, the magnetic field generated by the current flowing through the rewiring unit 212 and the magnetic field generated by the current flowing through the rewiring unit 232 cancel each other out, so that the generated inductance is reduced. Similarly, even in the state shown in FIG. 23, the direction of the current flowing through the rewiring unit 212 and the direction of the current flowing through the rewiring unit 232 are opposite to each other in the x direction, so that the generated inductance is reduced. .. Further, as shown in FIGS. 21 and 22, the direction of the current flowing through the rewiring unit 222 and the direction of the current flowing through the rewiring unit 232 are opposite to each other in the x direction. As a result, the magnetic field generated by the current flowing through the rewiring unit 222 and the magnetic field generated by the current flowing through the rewiring unit 232 cancel each other out, so that the generated inductance is reduced.
　本実施形態によると、第１接続配線２１の再配線部２１２と、第３接続配線２３の再配線部２３２とは、ｚ方向視において互いに大きな面積で重なっている。同様に、第２接続配線２２の再配線部２２２と第３接続配線２３の再配線部２３２とも、ｚ方向視において互いに大きな面積で重なっている。したがって、電流がｘ方向において互いに反対向きに流れることによる、インダクタンス低減の効果が大きい。 According to the present embodiment, the rewiring portion 212 of the first connection wiring 21 and the rewiring portion 232 of the third connection wiring 23 overlap each other in a large area in the z-direction view. Similarly, both the rewiring portion 222 of the second connection wiring 22 and the rewiring portion 232 of the third connection wiring 23 overlap each other in a large area in the z-direction view. Therefore, the effect of reducing the inductance is great because the currents flow in opposite directions in the x direction.
　本実施形態によると、各半導体素子３は、素子裏面３ｂにヒートスプレッダ５が接合されている。ヒートスプレッダ５のスプレッダ裏面５ｂは、封止樹脂４の樹脂裏面４ｂから露出している。半導体装置Ａ１は、樹脂裏面４ｂから露出する外部端子６によって、配線基板に実装される。このとき、樹脂裏面４ｂから露出するスプレッダ裏面５ｂも、たとえばハンダなどの接合部材によって、配線基板に接合される。これにより、半導体装置Ａ１は、半導体素子３が発する熱を、ヒートスプレッダ５を介して、配線基板に放出できる。したがって、半導体装置Ａ１は、半導体素子３が絶縁層１と封止樹脂４とによって覆われている従来の半導体装置と比較して、放熱性が高い。 According to this embodiment, each semiconductor element 3 has a heat spreader 5 bonded to the back surface 3b of the element. The back surface 5b of the spreader of the heat spreader 5 is exposed from the back surface 4b of the resin of the sealing resin 4. The semiconductor device A1 is mounted on a wiring board by an external terminal 6 exposed from the resin back surface 4b. At this time, the spreader back surface 5b exposed from the resin back surface 4b is also joined to the wiring board by a joining member such as solder. As a result, the semiconductor device A1 can release the heat generated by the semiconductor element 3 to the wiring board via the heat spreader 5. Therefore, the semiconductor device A1 has higher heat dissipation than the conventional semiconductor device in which the semiconductor element 3 is covered with the insulating layer 1 and the sealing resin 4.
　本実施形態によると、各半導体素子３にＣｕからなるヒートスプレッダ５が接合されている。これにより、熱膨張によって半導体装置Ａ１が反ることを抑制できる。 According to this embodiment, a heat spreader 5 made of Cu is bonded to each semiconductor element 3. As a result, it is possible to prevent the semiconductor device A1 from warping due to thermal expansion.
　本実施形態によれば、半導体装置Ａ１の各接続配線２は、金属元素が含有された添加剤を含む材料からなる第１絶縁層８２または第２絶縁層８４にレーザを照射して下地層８３Ａを析出させ、これを覆うめっき層８３Ｂを形成することで形成される。レーザ照射は、画像認識により得られた各電極の位置情報に基づき、逐一補正されながら行われる。したがって、封止樹脂４の硬化収縮により半導体素子３または外部端子６に変位が生じた場合であっても、各電極および各外部端子６の実際の位置に応じて精度よく接続配線２を形成することができる。これにより、各電極および各外部端子６と接続配線２との接合部における位置ずれを抑制することが可能となる。 According to the present embodiment, in each connection wiring 2 of the semiconductor device A1, the first insulating layer 82 or the second insulating layer 84 made of a material containing an additive containing a metal element is irradiated with a laser to irradiate the base layer 83A. Is formed by precipitating and forming a plating layer 83B that covers the plating layer 83B. Laser irradiation is performed while being corrected one by one based on the position information of each electrode obtained by image recognition. Therefore, even if the semiconductor element 3 or the external terminal 6 is displaced due to the curing shrinkage of the sealing resin 4, the connection wiring 2 is accurately formed according to the actual positions of each electrode and each external terminal 6. be able to. As a result, it is possible to suppress the positional deviation at the joint portion between each electrode and each external terminal 6 and the connection wiring 2.
　本実施形態では、第１絶縁層１１、第２絶縁層１２、および第３絶縁層１３が同じ材料からなる場合について説明したが、これに限られない。たとえば、第３絶縁層１３は、金属元素が含有された添加剤を含む材料でなくてもよい。 In the present embodiment, the case where the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13 are made of the same material has been described, but the present invention is not limited to this. For example, the third insulating layer 13 does not have to be a material containing an additive containing a metal element.
　本実施形態では、製造工程において、金属元素が含有された添加剤を含む材料からなる第１絶縁層８２にレーザを照射して下地層８３Ａを析出させ、これを覆うめっき層８３Ｂを形成することで接続配線８３（第１接続配線２１、第２接続配線２２、および接続配線２６，２７）を形成する場合について説明したが、これに限られない。接続配線８ ３は、その他の方法で形成されてもよい。たとえば、マスクを用いたフォトリソグラフィパターニングにより、各電極が露出するように第１絶縁層８２に複数の開口を形成し、当該開口と第１絶縁層８２上にめっきにより接続配線８３を形成してもよい。この場合、第１絶縁層８２は、金属元素が含有された添加剤を含む材料でなくてもよい。同様に、接続配線８５（第３接続配線２３）も、その他の方法で形成されてもよい。 In the present embodiment, in the manufacturing process, the first insulating layer 82 made of a material containing an additive containing a metal element is irradiated with a laser to precipitate the base layer 83A, and the plating layer 83B covering the base layer 83A is formed. The case where the connection wiring 83 (first connection wiring 21, second connection wiring 22, and connection wiring 26, 27) is formed has been described in the above, but the present invention is not limited to this. The connection wiring 8 3 may be formed by other methods. For example, by photolithography patterning using a mask, a plurality of openings are formed in the first insulating layer 82 so that each electrode is exposed, and a connection wiring 83 is formed by plating on the openings and the first insulating layer 82. May be good. In this case, the first insulating layer 82 does not have to be a material containing an additive containing a metal element. Similarly, the connection wiring 85 (third connection wiring 23) may be formed by other methods.
　本実施形態では、第１外部端子６１と第２外部端子６２とが隣接して配置されている場合について説明したが、これに限られない。第１外部端子６１と第２外部端子６２との間に、第３外部端子６３が配置されてもよい。 In the present embodiment, the case where the first external terminal 61 and the second external terminal 62 are arranged adjacent to each other has been described, but the present invention is not limited to this. A third external terminal 63 may be arranged between the first external terminal 61 and the second external terminal 62.
　図２４～図３０は、本開示の他の実施形態を示している。これらの図において、上記実施形態と同一または類似の要素には、上記実施形態と同一の符号を付している。 24 to 30 show other embodiments of the present disclosure. In these figures, the same or similar elements as those in the above embodiment are designated by the same reference numerals as those in the above embodiment.
　図２４は、本開示の第２実施形態に係る半導体装置Ａ２を説明するための図である。図２４は、半導体装置Ａ２を示す断面図であり、図５に対応する図である。本実施形態の半導体装置Ａ２は、ヒートスプレッダ５を備えていない点で、第１実施形態と異なっている。 FIG. 24 is a diagram for explaining the semiconductor device A2 according to the second embodiment of the present disclosure. FIG. 24 is a cross-sectional view showing the semiconductor device A2, and is a diagram corresponding to FIG. The semiconductor device A2 of the present embodiment is different from the first embodiment in that the heat spreader 5 is not provided.
　半導体装置Ａ２は、ヒートスプレッダ５を備えておらず、各半導体素子３の素子裏面３ｂが樹脂開口４ｃから露出している。本実施形態では、樹脂裏面４ｂと素子裏面３ｂとが面一である。素子裏面３ｂは、一部が樹脂裏面４ｂから露出していればよく、一部が封止樹脂４に覆われていてもよい。素子裏面３ｂは、半導体装置Ａ２が配線基板に実装される際に、たとえばハンダなどの接合部材によって、配線基板に接合される。これにより、各半導体素子３は、発する熱を、素子裏面３ｂから配線基板に放出できる。 The semiconductor device A2 does not include the heat spreader 5, and the element back surface 3b of each semiconductor element 3 is exposed from the resin opening 4c. In this embodiment, the resin back surface 4b and the element back surface 3b are flush with each other. The back surface 3b of the element may be partially exposed from the back surface 4b of the resin, and may be partially covered with the sealing resin 4. When the semiconductor device A2 is mounted on the wiring board, the back surface 3b of the element is joined to the wiring board by a joining member such as solder. As a result, each semiconductor element 3 can release the generated heat from the element back surface 3b to the wiring board.
　本実施形態によると、各半導体素子３の素子裏面３ｂは、封止樹脂４の樹脂裏面４ｂから露出しており、半導体装置Ａ２が配線基板に実装される際に、配線基板に接合される。これにより、半導体装置Ａ２は、半導体素子３が発する熱を、配線基板に放出できる。したがって、半導体装置Ａ２は、半導体素子３が絶縁層１と封止樹脂４とによって覆われている従来の半導体装置と比較して、放熱性が高い。また、半導体装置Ａ２は、第１実施形態と同様、第１外部端子６１および第２外部端子６２が、半導体素子３０１と半導体素子３０２との間に配置され、各々が樹脂裏面４ｂから露出している。これにより、半導体装置Ａ２は、磁界発生面積を小さくできるので、電流経路のインダクタンスを抑制できる。 According to this embodiment, the element back surface 3b of each semiconductor element 3 is exposed from the resin back surface 4b of the sealing resin 4, and is joined to the wiring board when the semiconductor device A2 is mounted on the wiring board. As a result, the semiconductor device A2 can release the heat generated by the semiconductor element 3 to the wiring board. Therefore, the semiconductor device A2 has higher heat dissipation than the conventional semiconductor device in which the semiconductor element 3 is covered with the insulating layer 1 and the sealing resin 4. Further, in the semiconductor device A2, as in the first embodiment, the first external terminal 61 and the second external terminal 62 are arranged between the semiconductor element 301 and the semiconductor element 302, and each is exposed from the resin back surface 4b. There is. As a result, the semiconductor device A2 can reduce the magnetic field generation area, so that the inductance of the current path can be suppressed.
　図２５は、本開示の第３実施形態に係る半導体装置Ａ３を説明するための図である。図２５は、半導体装置Ａ３を示す断面図であり、図５に対応する図である。本実施形態の半導体装置Ａ３は、絶縁層主面１ａに電子部品９を搭載するための複数の主面接続配線２５をさらに備えている点で、第１実施形態と異なっている。なお、図２５においては、電子部品９を想像線（二点鎖線）で示している。以下の図においても同様である。 FIG. 25 is a diagram for explaining the semiconductor device A3 according to the third embodiment of the present disclosure. FIG. 25 is a cross-sectional view showing the semiconductor device A3, and is a diagram corresponding to FIG. The semiconductor device A3 of the present embodiment is different from the first embodiment in that a plurality of main surface connection wirings 25 for mounting the electronic component 9 are further provided on the main surface 1a of the insulating layer. In FIG. 25, the electronic component 9 is shown by an imaginary line (dashed line). The same applies to the following figure.
　半導体装置Ａ３は、絶縁層主面１ａに電子部品９を搭載できるように設計されており、複数の主面接続配線２５をさらに備えている。電子部品９は、たとえば抵抗、コンデンサ、ドライバＩＣなどであるが、これに限定されない。また、半導体装置Ａ３に搭載される電子部品９の数、および、各電子部品９の配置位置は限定されない。 The semiconductor device A3 is designed so that the electronic component 9 can be mounted on the main surface 1a of the insulating layer, and further includes a plurality of main surface connection wirings 25. The electronic component 9 is, for example, a resistor, a capacitor, a driver IC, or the like, but is not limited thereto. Further, the number of electronic components 9 mounted on the semiconductor device A3 and the arrangement position of each electronic component 9 are not limited.
　複数の主面接続配線２５は、電子部品９と、第１接続配線２１、第２接続配線２２、第３接続配線２３、接続配線２６，２７、または外部端子６などとを接続する導電体であり、導電経路を構成している。複数の主面接続配線２５は、絶縁層１に配置されている。各 主面接続配線２５の構造は、第１接続配線２１などの構造と同様であり、各主面接続配線２５は、それぞれ、埋込部２５１および再配線部２５２を備えている。埋込部２５１は、第３絶縁層１３に少なくともその一部が埋め込まれている。第３接続配線２３に接続する主面接続配線２５の埋込部２５１は、第３絶縁層１３に全部が埋め込まれている。第１接続配線２１、第２接続配線２２、または接続配線２６，２７に接続する主面接続配線２５の埋込部２５１は、第３絶縁層１３および第２絶縁層１２を貫いて埋め込まれている。また、外部端子６に接続する主面接続配線２５の埋込部２５１は、第３絶縁層１３、第２絶縁層１２、および第１絶縁層１１を貫いて埋め込まれている。再配線部２５２は、第３絶縁層１３の第２絶縁層１２とは反対側の面、すなわち絶縁層主面１ａに配置されている。再配線部２５２は、埋込部２５１につながっている。再配線部２５２は、配線として機能し、電子部品９の端子を接合できる。 The plurality of main surface connection wirings 25 are conductors that connect the electronic component 9, the first connection wiring 21, the second connection wiring 22, the third connection wiring 23, the connection wirings 26, 27, the external terminal 6, and the like. Yes, it constitutes a conductive path. The plurality of main surface connection wirings 25 are arranged in the insulating layer 1. The structure of each main surface connection wiring 25 is the same as that of the first connection wiring 21 and the like, and each main surface connection wiring 25 includes an embedded portion 251 and a rewiring portion 252, respectively. At least a part of the embedded portion 251 is embedded in the third insulating layer 13. The embedded portion 251 of the main surface connection wiring 25 connected to the third connection wiring 23 is completely embedded in the third insulating layer 13. The embedded portion 251 of the main surface connection wiring 25 connected to the first connection wiring 21, the second connection wiring 22, or the connection wirings 26 and 27 is embedded through the third insulation layer 13 and the second insulation layer 12. There is. Further, the embedded portion 251 of the main surface connection wiring 25 connected to the external terminal 6 is embedded through the third insulating layer 13, the second insulating layer 12, and the first insulating layer 11. The rewiring portion 252 is arranged on the surface of the third insulating layer 13 opposite to the second insulating layer 12, that is, the main surface 1a of the insulating layer. The rewiring portion 252 is connected to the embedded portion 251. The rewiring unit 252 functions as wiring and can join the terminals of the electronic component 9.
　埋込部２５１および再配線部２５２の各々は、埋込部２１１および再配線部２１２と同様に、下地層２０１およびめっき層２０２を有する。下地層２０１は、第３絶縁層１３に含まれる添加剤に含有された金属元素により組成され、第３絶縁層１３に接している。めっき層２０２は、たとえば銅（Ｃｕ）を含む材料からなり、下地層２０１に接している。埋込部２５１の下地層２０１は、第３絶縁層１３に接している。埋込部２５１のめっき層２０２は、埋込部２５１の下地層２０１によって囲まれている。再配線部２５２の下地層２０１は、第３絶縁層１３に接している。再配線部２５２のめっき層２０２は、再配線部２５２の下地層２０１を覆っている。 Each of the embedded portion 251 and the rewiring portion 252 has a base layer 201 and a plating layer 202, similarly to the embedded portion 211 and the rewiring portion 212. The base layer 201 is composed of a metal element contained in the additive contained in the third insulating layer 13, and is in contact with the third insulating layer 13. The plating layer 202 is made of, for example, a material containing copper (Cu) and is in contact with the base layer 201. The base layer 201 of the embedded portion 251 is in contact with the third insulating layer 13. The plating layer 202 of the embedded portion 251 is surrounded by the base layer 201 of the embedded portion 251. The base layer 201 of the rewiring portion 252 is in contact with the third insulating layer 13. The plating layer 202 of the rewiring portion 252 covers the base layer 201 of the rewiring portion 252.
　半導体装置Ａ３は、第３絶縁層８６（第３絶縁層１３）を形成する工程までは、第１実施形態に係る半導体装置Ａ１と同様の製造工程で製造される。本実施形態の場合、形成された第３絶縁層８６に、レーザで複数の孔および複数の凹部を形成し、これらの孔および凹部に主面接続配線２５の下地層２０１を析出させる。次いで、無電解めっきにより、下地層２０１を覆うめっき層２０２を形成する。以上により、主面接続配線２５が形成される。その後の工程は、半導体装置Ａ１と同様である。 The semiconductor device A3 is manufactured in the same manufacturing process as the semiconductor device A1 according to the first embodiment until the step of forming the third insulating layer 86 (third insulating layer 13). In the case of the present embodiment, a plurality of holes and a plurality of recesses are formed in the formed third insulating layer 86 by a laser, and the base layer 201 of the main surface connection wiring 25 is deposited in these holes and the recesses. Next, the plating layer 202 covering the base layer 201 is formed by electroless plating. As a result, the main surface connection wiring 25 is formed. The subsequent steps are the same as those of the semiconductor device A1.
　本実施形態によると、半導体装置Ａ３は、第１実施形態と同様、第１外部端子６１および第２外部端子６２が、半導体素子３０１と半導体素子３０２との間に配置され、各々が樹脂裏面４ｂから露出している。これにより、半導体装置Ａ３は、磁界発生面積を小さくできるので、電流経路のインダクタンスを抑制できる。さらに、半導体装置Ａ３は、絶縁層主面１ａに配置されて配線として機能する再配線部２５２を有する主面接続配線２５を備えているので、絶縁層主面１ａに電子部品９を搭載可能である。 According to the present embodiment, in the semiconductor device A3, as in the first embodiment, the first external terminal 61 and the second external terminal 62 are arranged between the semiconductor element 301 and the semiconductor element 302, and each of them is a resin back surface 4b. Is exposed from. As a result, the semiconductor device A3 can reduce the magnetic field generation area, so that the inductance of the current path can be suppressed. Further, since the semiconductor device A3 includes a main surface connecting wiring 25 having a rewiring portion 252 arranged on the insulating layer main surface 1a and functioning as wiring, the electronic component 9 can be mounted on the insulating layer main surface 1a. be.
　図２６は、本開示の第４実施形態に係る半導体装置Ａ４を説明するための図である。図２６は、半導体装置Ａ４を示す断面図であり、図５に対応する図である。本実施形態の半導体装置Ａ４は、第４絶縁層１４および第４接続配線２４をさらに備えている点で、第３実施形態と異なっている。 FIG. 26 is a diagram for explaining the semiconductor device A4 according to the fourth embodiment of the present disclosure. FIG. 26 is a cross-sectional view showing the semiconductor device A4, and is a diagram corresponding to FIG. The semiconductor device A4 of the present embodiment is different from the third embodiment in that the fourth insulating layer 14 and the fourth connection wiring 24 are further provided.
　半導体装置Ａ４において、絶縁層１は、図２６に示すように、第４絶縁層１４をさらに備えている。第４絶縁層１４は、第１絶縁層１１、第２絶縁層１２、および第３絶縁層１３と同様に、熱硬化性の合成樹脂、および、複数の接続配線２の一部を組成する金属元素が含有された添加剤を含む材料からなる。第４絶縁層１４は、第３絶縁層１３と第２絶縁層１２との間に積層されている。つまり、第４絶縁層１４は、第３絶縁層１３および第２絶縁層１２に接している。第４絶縁層１４は、第２絶縁層１２および第３接続配線２３を形成した後、第３絶縁層１３を形成する前に、第２絶縁層１２と同様にして形成される。 In the semiconductor device A4, the insulating layer 1 further includes a fourth insulating layer 14 as shown in FIG. 26. The fourth insulating layer 14, like the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13, is a thermosetting synthetic resin and a metal that constitutes a part of a plurality of connection wirings 2. It consists of a material containing an additive containing an element. The fourth insulating layer 14 is laminated between the third insulating layer 13 and the second insulating layer 12. That is, the fourth insulating layer 14 is in contact with the third insulating layer 13 and the second insulating layer 12. The fourth insulating layer 14 is formed in the same manner as the second insulating layer 12 after forming the second insulating layer 12 and the third connecting wiring 23 and before forming the third insulating layer 13.
　半導体装置Ａ４は、第４接続配線２４をさらに備えている。第４接続配線２４は 、第２接続配線２２に接続する導電体であり、導電経路を構成している。第４接続配線２４は、第４絶縁層１４に配置されている。第４接続配線２４の構造は、第１接続配線２１などの構造と同様であり、第４接続配線２４は、埋込部２４１および再配線部２４２を備えている。埋込部２４１は、第４絶縁層１４および第２絶縁層１２を貫いて埋め込まれており、第２接続配線２２に接続している。埋込部２４１は、第３絶縁層１３、第２絶縁層１２、および第１絶縁層１１を貫いて埋め込まれて、第２外部端子６２に接続してもよい。再配線部２４２は、第３絶縁層１３と第４絶縁層１４との間に配置されている。再配線部２４２は、埋込部２４１につながっている。 The semiconductor device A4 further includes a fourth connection wiring 24. The fourth connection wiring 24 is a conductor connected to the second connection wiring 22, and constitutes a conductive path. The fourth connection wiring 24 is arranged in the fourth insulating layer 14. The structure of the fourth connection wiring 24 is the same as that of the first connection wiring 21 and the like, and the fourth connection wiring 24 includes an embedded portion 241 and a rewiring portion 242. The embedded portion 241 is embedded through the fourth insulating layer 14 and the second insulating layer 12, and is connected to the second connection wiring 22. The embedded portion 241 may be embedded through the third insulating layer 13, the second insulating layer 12, and the first insulating layer 11 and connected to the second external terminal 62. The rewiring portion 242 is arranged between the third insulating layer 13 and the fourth insulating layer 14. The rewiring portion 242 is connected to the embedded portion 241.
　埋込部２４１および再配線部２４２の各々は、埋込部２１１および再配線部２１２と同様に、下地層２０１およびめっき層２０２を有する。下地層２０１は、第４絶縁層１４および第２絶縁層１２に含まれる添加剤に含有された金属元素により組成され、第４絶縁層１４および第２絶縁層１２に接している。めっき層２０２は、たとえば銅（Ｃｕ）を含む材料からなり、下地層２０１に接している。埋込部２４１の下地層２０１は、第４絶縁層１４および第２絶縁層１２に接している。埋込部２４１のめっき層２０２は、埋込部２４１の下地層２０１によって囲まれている。再配線部２４２の下地層２０１は、第４絶縁層１４に接している。再配線部２４２のめっき層２０２は、再配線部２４２の下地層２０１を覆っている。 Each of the embedded portion 241 and the rewiring portion 242 has a base layer 201 and a plating layer 202, similarly to the embedded portion 211 and the rewiring portion 212. The base layer 201 is composed of metal elements contained in the additives contained in the fourth insulating layer 14 and the second insulating layer 12, and is in contact with the fourth insulating layer 14 and the second insulating layer 12. The plating layer 202 is made of, for example, a material containing copper (Cu) and is in contact with the base layer 201. The base layer 201 of the embedded portion 241 is in contact with the fourth insulating layer 14 and the second insulating layer 12. The plating layer 202 of the embedded portion 241 is surrounded by the base layer 201 of the embedded portion 241. The base layer 201 of the rewiring portion 242 is in contact with the fourth insulating layer 14. The plating layer 202 of the rewiring portion 242 covers the base layer 201 of the rewiring portion 242.
　半導体装置Ａ４は、接続配線８５（第３接続配線２３）を形成する工程までは、第３実施形態に係る半導体装置Ａ３と同様の製造工程で製造される。本実施形態の場合、第２絶縁層８４（第２絶縁層１２）に積層され、かつ接続配線８５（第３接続配線２３）を覆う第４絶縁層１４を形成する。そして、形成された第４絶縁層１４に、レーザで複数の孔および複数の凹部を形成し、これらの孔および凹部に第４接続配線２４の下地層２０１を析出させる。次いで、無電解めっきにより、下地層２０１を覆うめっき層２０２を形成する。以上により、第４接続配線２４が形成される。その後の工程は、半導体装置Ａ３と同様である。 The semiconductor device A4 is manufactured in the same manufacturing process as the semiconductor device A3 according to the third embodiment until the step of forming the connection wiring 85 (third connection wiring 23). In the case of the present embodiment, a fourth insulating layer 14 is formed which is laminated on the second insulating layer 84 (second insulating layer 12) and covers the connecting wiring 85 (third connecting wiring 23). Then, a plurality of holes and a plurality of recesses are formed in the formed fourth insulating layer 14 by a laser, and the base layer 201 of the fourth connection wiring 24 is deposited in these holes and the recesses. Next, the plating layer 202 covering the base layer 201 is formed by electroless plating. As a result, the fourth connection wiring 24 is formed. The subsequent steps are the same as those of the semiconductor device A3.
　本実施形態によると、半導体装置Ａ４は、第１実施形態と同様、第１外部端子６１および第２外部端子６２が、半導体素子３０１と半導体素子３０２との間に配置され、各々が樹脂裏面４ｂから露出している。これにより、半導体装置Ａ４は、磁界発生面積を小さくできるので、電流経路のインダクタンスを抑制できる。さらに、半導体装置Ａ４は、第３絶縁層１３と第２絶縁層１２との間に積層される第４絶縁層１４と、第４絶縁層１４に配置され、第２接続配線２２に接続する第４接続配線２４とを備えている。第４接続配線２４の再配線部２４２は、第３絶縁層１３と第４絶縁層１４との間に配置され、半導体素子３と電子部品９との間に位置している。これにより、半導体装置Ａ４は、半導体素子３から出力される高周波ノイズが電子部品９に影響を及ぼすことを抑制できる。 According to the present embodiment, in the semiconductor device A4, as in the first embodiment, the first external terminal 61 and the second external terminal 62 are arranged between the semiconductor element 301 and the semiconductor element 302, and each of them is a resin back surface 4b. It is exposed from. As a result, the semiconductor device A4 can reduce the magnetic field generation area, so that the inductance of the current path can be suppressed. Further, the semiconductor device A4 is arranged on the fourth insulating layer 14 and the fourth insulating layer 14 laminated between the third insulating layer 13 and the second insulating layer 12, and is connected to the second connection wiring 22. It is provided with a 4-connection wiring 24. The rewiring portion 242 of the fourth connection wiring 24 is arranged between the third insulating layer 13 and the fourth insulating layer 14, and is located between the semiconductor element 3 and the electronic component 9. As a result, the semiconductor device A4 can suppress the influence of the high frequency noise output from the semiconductor element 3 on the electronic component 9.
　図２７および図２８は、本開示の第５実施形態に係る半導体装置Ａ５を説明するための図である。図２７は、半導体装置Ａ５を示す平面図であり、図２に対応する図である。図２８は、半導体装置Ａ５を示す断面図であり、図５に対応する図である。本実施形態の半導体装置Ａ５は、第１外部端子６１と第２外部端子６２とがｘ方向ではなくｙ方向に並んでいる点で、第１実施形態と異なっている。 27 and 28 are diagrams for explaining the semiconductor device A5 according to the fifth embodiment of the present disclosure. FIG. 27 is a plan view showing the semiconductor device A5, and is a diagram corresponding to FIG. FIG. 28 is a cross-sectional view showing the semiconductor device A5, and is a diagram corresponding to FIG. The semiconductor device A5 of the present embodiment is different from the first embodiment in that the first external terminal 61 and the second external terminal 62 are arranged in the y direction instead of the x direction.
　半導体装置Ａ５において、第１外部端子６１および第２外部端子６２は、図２７に示すように、ｙ方向の寸法が第３外部端子６３の半分程度であり、第３外部端子６３から同じ距離だけ離間して、ｙ方向に並んでいる。再配線部２１２の形状は、ｚ方向視において第１外部端子６１に重なりつつ、第２外部端子６２には重ならない形状になっている。また、再配線部２２２の形状は、ｚ方向視において第２外部端子６２に重なりつつ、第１外部端子６１には重ならない形状になっている。 In the semiconductor device A5, as shown in FIG. 27, the first external terminal 61 and the second external terminal 62 have a dimension in the y direction about half that of the third external terminal 63, and are the same distance from the third external terminal 63. They are separated and lined up in the y direction. The shape of the rewiring portion 212 is such that it overlaps with the first external terminal 61 in the z-direction view, but does not overlap with the second external terminal 62. Further, the shape of the rewiring portion 222 is such that it overlaps with the second external terminal 62 in the z-direction view, but does not overlap with the first external terminal 61.
　本実施形態においても、半導体装置Ａ５は、第１外部端子６１および第２外部端子６２が、半導体素子３０１と半導体素子３０２との間に配置され、各々が樹脂裏面４ｂから露出している。これにより、半導体装置Ａ５は、磁界発生面積を小さくできるので、電流経路のインダクタンスを抑制できる。さらに、半導体装置Ａ５は、第１外部端子６１と６２とがｙ方向に並んでいるので、半導体装置Ａ１よりｘ方向の寸法を小さくできる。 Also in this embodiment, in the semiconductor device A5, the first external terminal 61 and the second external terminal 62 are arranged between the semiconductor element 301 and the semiconductor element 302, and each is exposed from the resin back surface 4b. As a result, the semiconductor device A5 can reduce the magnetic field generation area, so that the inductance of the current path can be suppressed. Further, in the semiconductor device A5, since the first external terminals 61 and 62 are arranged in the y direction, the dimension in the x direction can be made smaller than that of the semiconductor device A1.
　図２９および図３０は、本開示の第６実施形態に係る半導体装置Ａ６を説明するための図である。図２９は、半導体装置Ａ６を示す平面図であり、図２に対応する図である。図３０は、半導体装置Ａ６を示す断面図であり、図２９のＸＸＸ-ＸＸＸ線に沿う断面図である。本実施形態の半導体装置Ａ６は、第２絶縁層１２を備えておらず、第３接続配線２３も第１絶縁層１１に配置されている点で、第１実施形態と異なっている。 29 and 30 are diagrams for explaining the semiconductor device A6 according to the sixth embodiment of the present disclosure. FIG. 29 is a plan view showing the semiconductor device A6, and is a diagram corresponding to FIG. FIG. 30 is a cross-sectional view showing the semiconductor device A6, and is a cross-sectional view taken along the line XXX-XXX of FIG. 29. The semiconductor device A6 of the present embodiment is different from the first embodiment in that the second insulating layer 12 is not provided and the third connection wiring 23 is also arranged in the first insulating layer 11.
　半導体装置Ａ６は、図３０に示すように、第２絶縁層１２を備えておらず、第３絶縁層１３が第１絶縁層１１に積層されている。半導体装置Ａ６では、第３接続配線２３が、第１接続配線２１および第２接続配線２２と同様に、第１絶縁層１１に形成されている。図２９に示すように、再配線部２３２の形状は、再配線部２１２および再配線部２２２に接触せず、ｚ方向視において、半導体素子３０１の出力電極３２に重なりつつ、半導体素子３０２の入力電極３１に重なる形状になっている。 As shown in FIG. 30, the semiconductor device A6 does not include the second insulating layer 12, and the third insulating layer 13 is laminated on the first insulating layer 11. In the semiconductor device A6, the third connection wiring 23 is formed in the first insulating layer 11 in the same manner as the first connection wiring 21 and the second connection wiring 22. As shown in FIG. 29, the shape of the rewiring portion 232 does not contact the rewiring portion 212 and the rewiring portion 222, and overlaps with the output electrode 32 of the semiconductor element 301 in the z-direction view while inputting the semiconductor element 302. It has a shape that overlaps with the electrode 31.
　本実施形態によると、半導体装置Ａ６は、第１実施形態と同様、第１外部端子６１および第２外部端子６２が、半導体素子３０１と半導体素子３０２との間に配置され、各々が樹脂裏面４ｂから露出している。これにより、半導体装置Ａ５は、磁界発生面積を小さくできるので、電流経路のインダクタンスを抑制できる。さらに、半導体装置Ａ６は、第２絶縁層１２を備えていないので、半導体装置Ａ１よりｚ方向の寸法を小さくできる。また、絶縁層１の積層数が少ないので、製造工程が簡略化できる。 According to the present embodiment, in the semiconductor device A6, as in the first embodiment, the first external terminal 61 and the second external terminal 62 are arranged between the semiconductor element 301 and the semiconductor element 302, and each of them is a resin back surface 4b. It is exposed from. As a result, the semiconductor device A5 can reduce the magnetic field generation area, so that the inductance of the current path can be suppressed. Further, since the semiconductor device A6 does not include the second insulating layer 12, the dimension in the z direction can be made smaller than that of the semiconductor device A1. Moreover, since the number of layers of the insulating layer 1 is small, the manufacturing process can be simplified.
　上記第１～６実施形態においては、半導体素子３が素子主面３ａにのみ電極を備える場合について説明したが、本開示はこれに限定されない。半導体素子３は、素子裏面３ｂに裏面電極を備えてもよい。この場合、半導体装置Ａ１、Ａ３～Ａ６が配線基板に実装される際に、樹脂開口４ｃから露出するヒートスプレッダ５のスプレッダ裏面５ｂは、導電性を有する接合部材で配線基板の配線に接合される外部端子になる。この場合、ヒートスプレッダ５は導電性を有する必要がある。また、半導体装置Ａ２が配線基板に実装される際に、樹脂開口４ｃから露出する半導体素子３の素子裏面３ｂは、導電性を有する接合部材で配線基板の配線に接合される外部端子になる。 In the above first to sixth embodiments, the case where the semiconductor device 3 includes the electrode only on the element main surface 3a has been described, but the present disclosure is not limited to this. The semiconductor element 3 may be provided with a back surface electrode on the back surface 3b of the device. In this case, when the semiconductor devices A1 and A3 to A6 are mounted on the wiring board, the spreader back surface 5b of the heat spreader 5 exposed from the resin opening 4c is externally joined to the wiring of the wiring board by a conductive joining member. Become a terminal. In this case, the heat spreader 5 needs to have conductivity. Further, when the semiconductor device A2 is mounted on the wiring board, the element back surface 3b of the semiconductor element 3 exposed from the resin opening 4c becomes an external terminal that is joined to the wiring of the wiring board by a conductive joining member.
　上記第１～６実施形態においては、第１外部端子６１、第２外部端子６２、および第３外部端子６３が、それぞれ板状部材である場合について説明したが、本開示はこれに限定されない。第１外部端子６１、第２外部端子６２、および第３外部端子６３の形状は特に限定されない。第１外部端子６１、第２外部端子６２、および第３外部端子６３は、封止樹脂４をｚ方向に貫通するビアホールであってもよい。 In the above first to sixth embodiments, the case where the first external terminal 61, the second external terminal 62, and the third external terminal 63 are plate-shaped members, respectively, has been described, but the present disclosure is not limited to this. The shapes of the first external terminal 61, the second external terminal 62, and the third external terminal 63 are not particularly limited. The first external terminal 61, the second external terminal 62, and the third external terminal 63 may be via holes penetrating the sealing resin 4 in the z direction.
　上記第１～６実施形態においては、第３外部端子６３が、半導体素子３０１と半導体素子３０２との間に配置されている場合について説明したが、本開示はこれに限定されない。第３外部端子６３は、半導体素子３０１と半導体素子３０２との間以外の位置、例えば、半導体素子３０１に対してｘ方向において第１外部端子６１とは反対側、または、半導体素 子３０２に対してｘ方向において第２外部端子６２とは反対側に配置されてもよい。第４外部端子６４および第５外部端子６５と同様に、半導体装置Ａ１～Ａ６のｙ方向の一方端部（図３における上方側端部）に、他の外部端子６と並んで配置されてもよい。 In the above first to sixth embodiments, the case where the third external terminal 63 is arranged between the semiconductor element 301 and the semiconductor element 302 has been described, but the present disclosure is not limited to this. The third external terminal 63 is located at a position other than between the semiconductor element 301 and the semiconductor element 302, for example, on the side opposite to the first external terminal 61 in the x direction with respect to the semiconductor element 301, or with respect to the semiconductor element 302. It may be arranged on the side opposite to the second external terminal 62 in the x direction. Similar to the fourth external terminal 64 and the fifth external terminal 65, even if they are arranged side by side with the other external terminals 6 at one end (upper end in FIG. 3) of the semiconductor devices A1 to A6 in the y direction. good.
　本開示に係る半導体装置は、先述した実施形態に限定されるものではない。本開示に係る半導体装置の各部の具体的な構成は、種々に設計変更自在である。本開示は、以下の付記に記載された構成を含む。 The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely redesigned. The present disclosure includes the configurations described in the appendix below.
　付記１．
　厚さ方向において互いに反対側を向く素子主面および素子裏面と、前記素子主面に配置された複数の主面電極と、を各々が有し、前記厚さ方向に直交する第１方向に並んで配置された第１半導体素子および第２半導体素子と、
　前記各素子主面を覆い、かつ、前記各素子主面に対向する絶縁層裏面と、前記厚さ方向において前記絶縁層裏面とは反対側を向く絶縁層主面と、を有する絶縁層と、
　前記絶縁層裏面に接する樹脂主面と、前記厚さ方向において前記樹脂主面とは反対側を向く樹脂裏面と、を有し、かつ、前記第１半導体素子および前記第２半導体素子を部分的に覆う封止樹脂と、
　前記第１半導体素子と前記第２半導体素子との間に配置され、各々が前記樹脂裏面から露出する第１外部端子および第２外部端子と、
　前記絶縁層に配置され、前記第１半導体素子のいずれかの主面電極と前記第１外部端子とを導通させる第１接続配線と、
　前記絶縁層に配置され、前記第２半導体素子のいずれかの主面電極と前記第２外部端子とを導通させる第２接続配線と、
を備えている半導体装置。
　付記２．
　前記第１半導体素子の複数の主面電極は、第１入力電極および第１出力電極を含み、
　前記第２半導体素子の複数の主面電極は、第２入力電極および第２出力電極を含み、
　前記第１接続配線は、前記第１入力電極および前記第１外部端子に接続し、
　前記第２接続配線は、前記第２出力電極および前記第２外部端子に接続する、付記１に記載の半導体装置。
　付記３．
　前記絶縁層に配置され、前記第１出力電極および前記第２入力電極に接続する第３接続配線をさらに備えている、付記２に記載の半導体装置。
　付記４．
　前記絶縁層は、積層された第１絶縁層、第２絶縁層、および第３絶縁層を備え、
　前記第１絶縁層は、前記絶縁層裏面を含み、
　前記第３絶縁層は、前記絶縁層主面を含んでいる、付記３に記載の半導体装置。
　付記５．
　前記第１接続配線は、前記第１絶縁層と前記第２絶縁層との間に配置された第１再配線部を備え、
　前記第２接続配線は、前記第１絶縁層と前記第２絶縁層との間に配置された第２再配線部を備え、
　前記第３接続配線は、前記第２絶縁層と前記第３絶縁層との間に配置された第３再配線部を備えている、付記４に記載の半導体装置。
　付記６．
　前記厚さ方向視において、前記第３再配線部の少なくとも一部は、前記第１再配線部および前記第２再配線部に重なっている、付記５に記載の半導体装置。
　付記７．
　前記絶縁層に配置され、前記第３接続配線に接続する第４接続配線をさらに備え、
　前記絶縁層は、前記第２絶縁層と前記第３絶縁層との間に積層された第４絶縁層をさらに備え、
　前記第４接続配線は、前記第４絶縁層と前記第３絶縁層との間に配置された第４再配線部を備えている、付記４ないし６のいずれかに記載の半導体装置。
　付記８．
　前記第１絶縁層は、熱硬化性の合成樹脂、および、前記第１接続配線の一部を組成する金属元素が含有された添加剤を含む材料からなる、付記４ないし７のいずれかに記載の半導体装置。
　付記９．
　前記第１接続配線は、前記第１絶縁層に接する下地層と、前記下地層に接するめっき層と、を有し、
　前記下地層は、前記添加剤に含有された前記金属元素により組成される、付記８に記載の半導体装置。
　付記１０．
　前記第１半導体素子と前記第２半導体素子との間に配置されて前記樹脂裏面から露出し、かつ、前記第３接続配線に接続される第３外部端子をさらに備えている、付記３ないし９のいずれかに記載の半導体装置。
　付記１１．
　前記第３外部端子は、前記第１半導体素子と前記第１外部端子との間、または、前記第２半導体素子と前記第２外部端子との間に配置されている、付記１０に記載の半導体装置。
　付記１２．
　前記第１方向において、前記第１半導体素子に対して前記第２半導体素子とは反対側、または、前記第２半導体素子に対して前記第１半導体素子とは反対側に配置されて、前記樹脂裏面から露出し、かつ、前記第３接続配線に接続される第３外部端子をさらに備えている、　付記３ないし９のいずれかに記載の半導体装置。
　付記１３．
　前記第１半導体素子および前記第２半導体素子は、窒化物半導体からなる電子走行層を有するトランジスタであり、
　前記第１入力電極および前記第２入力電極は、ドレイン電極であり、
　前記第１出力電極および前記第２出力電極は、ソース電極である、付記２ないし１２のいずれかに記載の半導体装置。
　付記１４．
　前記第１外部端子および前記第２外部端子は、前記樹脂主面から露出している、付記１ないし１３のいずれかに記載の半導体装置。
　付記１５．
　前記絶縁層主面に配置された主面再配線部を有する主面接続配線をさらに備えている、付記１ないし１４のいずれかに記載の半導体装置。
　付記１６．
　前記封止樹脂は、前記樹脂裏面側に、前記厚さ方向視において前記第１半導体素子に重なる樹脂開口を備えている、付記１ないし１５のいずれかに記載の半導体装置。
　付記１７．
　前記第１半導体素子の前記素子裏面は、前記樹脂開口から露出している、付記１６に記載の半導体装置。
　付記１８．
　前記第１半導体素子の前記素子裏面である第１素子裏面に接合されたヒートスプレッダをさらに備え、
　前記ヒートスプレッダは、
　前記第１素子裏面に対向するスプレッダ主面と、
　前記厚さ方向において前記スプレッダ主面とは反対側を向くスプレッダ裏面と、
を有し、
　前記スプレッダ裏面は、前記樹脂開口から露出している、付記１６に記載の半導体装置。 Appendix 1.
Each of the element main surface and the element back surface facing the opposite sides in the thickness direction and a plurality of main surface electrodes arranged on the element main surface are arranged in a first direction orthogonal to the thickness direction. The first semiconductor element and the second semiconductor element arranged in
An insulating layer having an insulating layer back surface that covers each element main surface and faces each element main surface, and an insulating layer main surface that faces the opposite side of the insulating layer back surface in the thickness direction.
It has a resin main surface in contact with the back surface of the insulating layer and a resin back surface facing the side opposite to the resin main surface in the thickness direction, and partially comprises the first semiconductor element and the second semiconductor element. With the sealing resin that covers
A first external terminal and a second external terminal, which are arranged between the first semiconductor element and the second semiconductor element and are exposed from the back surface of the resin, respectively.
A first connection wiring arranged on the insulating layer and conducting the main surface electrode of any one of the first semiconductor elements and the first external terminal.
A second connection wiring that is arranged in the insulating layer and conducts the main surface electrode of any of the second semiconductor elements and the second external terminal.
A semiconductor device equipped with.
Appendix 2.
The plurality of main surface electrodes of the first semiconductor element include a first input electrode and a first output electrode.
The plurality of main surface electrodes of the second semiconductor element include a second input electrode and a second output electrode.
The first connection wiring is connected to the first input electrode and the first external terminal, and is connected to the first input electrode.
The semiconductor device according to Appendix 1, wherein the second connection wiring is connected to the second output electrode and the second external terminal.
Appendix 3.
The semiconductor device according to Appendix 2, further comprising a third connection wiring arranged on the insulating layer and connected to the first output electrode and the second input electrode.
Appendix 4.
The insulating layer includes a laminated first insulating layer, a second insulating layer, and a third insulating layer.
The first insulating layer includes the back surface of the insulating layer.
The semiconductor device according to Appendix 3, wherein the third insulating layer includes the main surface of the insulating layer.
Appendix 5.
The first connection wiring includes a first rewiring portion arranged between the first insulating layer and the second insulating layer.
The second connection wiring includes a second rewiring portion arranged between the first insulating layer and the second insulating layer.
The semiconductor device according to Appendix 4, wherein the third connection wiring includes a third rewiring portion arranged between the second insulating layer and the third insulating layer.
Appendix 6.
The semiconductor device according to Appendix 5, wherein at least a part of the third rewiring portion overlaps the first rewiring portion and the second rewiring portion in the thickness direction.
Appendix 7.
A fourth connection wiring that is arranged in the insulation layer and connects to the third connection wiring is further provided.
The insulating layer further includes a fourth insulating layer laminated between the second insulating layer and the third insulating layer.
The semiconductor device according to any one of Supplementary note 4 to 6, wherein the fourth connection wiring includes a fourth rewiring portion arranged between the fourth insulating layer and the third insulating layer.
Appendix 8.
The first insulating layer is made of a material containing a thermosetting synthetic resin and an additive containing a metal element constituting a part of the first connection wiring, according to any one of Supplementary note 4 to 7. Semiconductor equipment.
Appendix 9.
The first connection wiring has a base layer in contact with the first insulating layer and a plating layer in contact with the base layer.
The semiconductor device according to Appendix 8, wherein the base layer is composed of the metal element contained in the additive.
Appendix 10.
Appendix 3 to 9 further include a third external terminal arranged between the first semiconductor element and the second semiconductor element, exposed from the back surface of the resin, and connected to the third connection wiring. The semiconductor device according to any one of.
Appendix 11.
The semiconductor according to Appendix 10, wherein the third external terminal is arranged between the first semiconductor element and the first external terminal, or between the second semiconductor element and the second external terminal. Device.
Appendix 12.
In the first direction, the resin is arranged on the side opposite to the second semiconductor element with respect to the first semiconductor element, or on the side opposite to the first semiconductor element with respect to the second semiconductor element. The semiconductor device according to any one of Appendix 3 to 9, further comprising a third external terminal exposed from the back surface and connected to the third connection wiring.
Appendix 13.
The first semiconductor element and the second semiconductor element are transistors having an electron traveling layer made of a nitride semiconductor.
The first input electrode and the second input electrode are drain electrodes.
The semiconductor device according to any one of Supplementary note 2 to 12, wherein the first output electrode and the second output electrode are source electrodes.
Appendix 14.
The semiconductor device according to any one of Supplementary note 1 to 13, wherein the first external terminal and the second external terminal are exposed from the resin main surface.
Appendix 15.
The semiconductor device according to any one of Appendix 1 to 14, further comprising a main surface connection wiring having a main surface rewiring portion arranged on the main surface of the insulating layer.
Appendix 16.
The semiconductor device according to any one of Supplementary note 1 to 15, wherein the sealing resin is provided with a resin opening that overlaps with the first semiconductor element in the thickness direction on the back surface side of the resin.
Appendix 17.
The semiconductor device according to Appendix 16, wherein the back surface of the first semiconductor element is exposed from the resin opening.
Appendix 18.
A heat spreader bonded to the back surface of the first element, which is the back surface of the element of the first semiconductor element, is further provided.
The heat spreader
The main surface of the spreader facing the back surface of the first element and
The back surface of the spreader facing the opposite side of the main surface of the spreader in the thickness direction,
Have,
The semiconductor device according to Appendix 16, wherein the back surface of the spreader is exposed from the resin opening.
Ａ１，Ａ２，Ａ３，Ａ４，Ａ５，Ａ６：半導体装置
１：絶縁層　　　　１１：第１絶縁層　　　１２：第２絶縁層
１３：第３絶縁層　　　　１４：第４絶縁層　　　　１ａ：絶縁層主面
１ｂ：絶縁層裏面　　　　２：接続配線　　　　２１：第１接続配線
２１１：埋込部　　　　２１２：再配線部　　　　２２：第２接続配線
２２１：埋込部　　　　２２２：再配線部　　　　２２２ａ：貫通孔
２３：第３接続配線　　　　２３１：埋込部　　　　２３２：再配線部
２４：第４接続配線　　　　２４１：埋込部　　　　２４２：再配線部
２５：主面接続配線　　　　２５１：埋込部　　　　２５２：再配線部
２６：接続配線　　　　２６１：埋込部　　　　２６２：再配線部
２７：接続配線　　　　２７１：埋込部　　　　２７２：再配線部
２０１：下地層　　　　２０２：めっき層　　　　３：半導体素子
３０１：半導体素子　　　　３０２：半導体素子　　　　３１：入力電極
３２：出力電極　　　　３３：制御電極　　　　３ａ：素子主面
３ｂ：素子裏面　　　　４：封止樹脂　　　　４ａ：樹脂主面
４ｂ：樹脂裏面　　　　４ｃ：樹脂開口　　　　５：ヒートスプレッダ
５ａ：スプレッダ主面　　　　５ｂ：スプレッダ裏面　　　　６：外部端子
６１：第１外部端子　　　　６２：第２外部端子　　　　
６３：第３外部端子
６４：第４外部端子　　　　６５：第５外部端子　　　　９：電子部品
８１：封止樹脂　　　　８２：第１絶縁層　　　　８２１：孔
８２２：凹部　　　　８３：接続配線　　　　８３Ａ：下地層
８３Ｂ：めっき層　　　　８３１：埋込部　　　　８３２：再配線部
８４：第２絶縁層　　　　８４１：孔　　　　８４２：凹部
８５：接続配線　　　　８５１：埋込部　　　　８５２：再配線部
８６：第３絶縁層 A1, A2, A3, A4, A5, A6: Semiconductor device 1: Insulation layer 11: First insulation layer 12: Second insulation layer 13: Third insulation layer 14: Fourth insulation layer 1a: Insulation layer main surface 1b: Insulation layer back surface 2: Connection wiring 21: First connection wiring 211: Embedded part 212: Rewiring part 22: Second connection wiring 221: Embedded part 222: Rewiring part 222a: Through hole 23: Third connection wiring 231 : Embedded part 232: Rewiring part 24: Fourth connection wiring 241: Embedded part 242: Rewiring part 25: Main surface connection wiring 251: Embedded part 252: Rewiring part 26: Connection wiring 261: Embedded part 262: Rewiring part 27: Connection wiring 271: Embedded part 272: Rewiring part 201: Underlayer layer 202: Plating layer 3: Semiconductor element 301: Semiconductor element 302: Semiconductor element 31: Input electrode 32: Output electrode 33: Control Electrode 3a: Element main surface 3b: Element back surface 4: Encapsulating resin 4a: Resin main surface 4b: Resin back surface 4c: Resin opening 5: Heat spreader 5a: Spreader main surface 5b: Spreader back surface 6: External terminal 61: First external terminal 62: Second external terminal
63: 3rd external terminal 64: 4th external terminal 65: 5th external terminal 9: Electronic component 81: Encapsulating resin 82: 1st insulating layer 821: Hole 822: Recessed 83: Connection wiring 83A: Base layer 83B: Plating Layer 831: Embedded part 832: Rewiring part 84: Second insulating layer 841: Hole 842: Recessed 85: Connection wiring 851: Embedded part 852: Rewiring part 86: Third insulating layer

Claims (18)

  1. 　厚さ方向において互いに反対側を向く素子主面および素子裏面と、前記素子主面に配置された複数の主面電極と、を各々が有し、前記厚さ方向に直交する第１方向に並んで配置された第１半導体素子および第２半導体素子と、
    　前記各素子主面を覆い、かつ、前記各素子主面に対向する絶縁層裏面と、前記厚さ方向において前記絶縁層裏面とは反対側を向く絶縁層主面と、を有する絶縁層と、
    　前記絶縁層裏面に接する樹脂主面と、前記厚さ方向において前記樹脂主面とは反対側を向く樹脂裏面と、を有し、かつ、前記第１半導体素子および前記第２半導体素子を部分的に覆う封止樹脂と、
    　前記第１半導体素子と前記第２半導体素子との間に配置され、各々が前記樹脂裏面から露出する第１外部端子および第２外部端子と、
    　前記絶縁層に配置され、前記第１半導体素子のいずれかの主面電極と前記第１外部端子とを導通させる第１接続配線と、
    　前記絶縁層に配置され、前記第２半導体素子のいずれかの主面電極と前記第２外部端子とを導通させる第２接続配線と、を備えている半導体装置。     Each of the element main surface and the element back surface facing the opposite sides in the thickness direction and a plurality of main surface electrodes arranged on the element main surface are arranged in a first direction orthogonal to the thickness direction. The first semiconductor element and the second semiconductor element arranged in
    An insulating layer having an insulating layer back surface that covers each element main surface and faces each element main surface, and an insulating layer main surface that faces the opposite side of the insulating layer back surface in the thickness direction.
    It has a resin main surface in contact with the back surface of the insulating layer and a resin back surface facing the side opposite to the resin main surface in the thickness direction, and partially comprises the first semiconductor element and the second semiconductor element. With the sealing resin that covers
    A first external terminal and a second external terminal, which are arranged between the first semiconductor element and the second semiconductor element and are exposed from the back surface of the resin, respectively.
    A first connection wiring arranged on the insulating layer and conducting the main surface electrode of any one of the first semiconductor elements and the first external terminal.
    A semiconductor device arranged on the insulating layer and provided with a second connection wiring for conducting any main surface electrode of the second semiconductor element and the second external terminal.
  2. 　前記第１半導体素子の複数の主面電極は、第１入力電極および第１出力電極を含み、
    　前記第２半導体素子の複数の主面電極は、第２入力電極および第２出力電極を含み、
    　前記第１接続配線は、前記第１入力電極および前記第１外部端子に接続し、
    　前記第２接続配線は、前記第２出力電極および前記第２外部端子に接続する、請求項１に記載の半導体装置。     The plurality of main surface electrodes of the first semiconductor element include a first input electrode and a first output electrode.
    The plurality of main surface electrodes of the second semiconductor element include a second input electrode and a second output electrode.
    The first connection wiring is connected to the first input electrode and the first external terminal, and is connected to the first input electrode.
    The semiconductor device according to claim 1, wherein the second connection wiring is connected to the second output electrode and the second external terminal.
  3. 　前記絶縁層に配置され、前記第１出力電極および前記第２入力電極に接続する第３接続配線をさらに備えている、請求項２に記載の半導体装置。 The semiconductor device according to claim 2, further comprising a third connection wiring arranged on the insulating layer and connected to the first output electrode and the second input electrode.
  4. 　前記絶縁層は、積層された第１絶縁層、第２絶縁層、および第３絶縁層を備え、
    　前記第１絶縁層は、前記絶縁層裏面を含み、
    　前記第３絶縁層は、前記絶縁層主面を含んでいる、請求項３に記載の半導体装置。     The insulating layer includes a laminated first insulating layer, a second insulating layer, and a third insulating layer.
    The first insulating layer includes the back surface of the insulating layer.
    The semiconductor device according to claim 3, wherein the third insulating layer includes the main surface of the insulating layer.
  5. 　前記第１接続配線は、前記第１絶縁層と前記第２絶縁層との間に配置された第１再配線部を備え、
    　前記第２接続配線は、前記第１絶縁層と前記第２絶縁層との間に配置された第２再配線部を備え、
    　前記第３接続配線は、前記第２絶縁層と前記第３絶縁層との間に配置された第３再配線部を備えている、請求項４に記載の半導体装置。     The first connection wiring includes a first rewiring portion arranged between the first insulating layer and the second insulating layer.
    The second connection wiring includes a second rewiring portion arranged between the first insulating layer and the second insulating layer.
    The semiconductor device according to claim 4, wherein the third connection wiring includes a third rewiring portion arranged between the second insulating layer and the third insulating layer.
  6. 　前記厚さ方向視において、前記第３再配線部の少なくとも一部は、前記第１再配線部および前記第２再配線部に重なっている、請求項５に記載の半導体装置。 The semiconductor device according to claim 5, wherein at least a part of the third rewiring portion overlaps the first rewiring portion and the second rewiring portion in the thickness direction.
  7. 　前記絶縁層に配置され、前記第３接続配線に接続する第４接続配線をさらに備え、
    　前記絶縁層は、前記第２絶縁層と前記第３絶縁層との間に積層された第４絶縁層をさらに備え、
    　前記第４接続配線は、前記第４絶縁層と前記第３絶縁層との間に配置された第４再配線部を備えている、請求項４ないし６のいずれかに記載の半導体装置。     A fourth connection wiring that is arranged in the insulation layer and connects to the third connection wiring is further provided.
    The insulating layer further includes a fourth insulating layer laminated between the second insulating layer and the third insulating layer.
    The semiconductor device according to any one of claims 4 to 6, wherein the fourth connection wiring includes a fourth rewiring portion arranged between the fourth insulating layer and the third insulating layer.
  8. 　前記第１絶縁層は、熱硬化性の合成樹脂、および、前記第１接続配線の一部を組成する金属元素が含有された添加剤を含む材料からなる、請求項４ないし７のいずれかに記載の半導体装置。 The first insulating layer is made of a material containing a thermosetting synthetic resin and an additive containing a metal element constituting a part of the first connection wiring, according to any one of claims 4 to 7. The semiconductor device described.
  9. 　前記第１接続配線は、前記第１絶縁層に接する下地層と、前記下地層に接するめっき層と、を有し、
    　前記下地層は、前記添加剤に含有された前記金属元素により組成される、請求項８に記載の半導体装置。     The first connection wiring has a base layer in contact with the first insulating layer and a plating layer in contact with the base layer.
    The semiconductor device according to claim 8, wherein the base layer is composed of the metal element contained in the additive.
  10. 　前記第１半導体素子と前記第２半導体素子との間に配置されて前記樹脂裏面から露出し、かつ、前記第３接続配線に接続される第３外部端子をさらに備えている、請求項３ないし９のいずれかに記載の半導体装置。 3. 9. The semiconductor device according to any one of 9.
  11. 　前記第３外部端子は、前記第１半導体素子と前記第１外部端子との間、または、前記第２半導体素子と前記第２外部端子との間に配置されている、請求項１０に記載の半導体装置。 The tenth aspect of the present invention, wherein the third external terminal is arranged between the first semiconductor element and the first external terminal, or between the second semiconductor element and the second external terminal. Semiconductor device.
  12. 　前記第１方向において、前記第１半導体素子に対して前記第２半導体素子とは反対側、または、前記第２半導体素子に対して前記第１半導体素子とは反対側に配置されて、前記樹脂裏面から露出し、かつ、前記第３接続配線に接続される第３外部端子をさらに備えている、請求項３ないし９のいずれかに記載の半導体装置。 In the first direction, the resin is arranged on the side opposite to the second semiconductor element with respect to the first semiconductor element, or on the side opposite to the first semiconductor element with respect to the second semiconductor element. The semiconductor device according to any one of claims 3 to 9, further comprising a third external terminal exposed from the back surface and connected to the third connection wiring.
  13. 　前記第１半導体素子および前記第２半導体素子は、窒化物半導体からなる電子走行層を有するトランジスタであり、
    　前記第１入力電極および前記第２入力電極は、ドレイン電極であり、
    　前記第１出力電極および前記第２出力電極は、ソース電極である。請求項２ないし１２のいずれかに記載の半導体装置。     The first semiconductor element and the second semiconductor element are transistors having an electron traveling layer made of a nitride semiconductor.
    The first input electrode and the second input electrode are drain electrodes.
    The first output electrode and the second output electrode are source electrodes. The semiconductor device according to any one of claims 2 to 12.
  14. 　前記第１外部端子および前記第２外部端子は、前記樹脂主面から露出している、請求項１ないし１３のいずれかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 13, wherein the first external terminal and the second external terminal are exposed from the resin main surface.
  15. 　前記絶縁層主面に配置された主面再配線部を有する主面接続配線をさらに備えている、請求項１ないし１４のいずれかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 14, further comprising a main surface connection wiring having a main surface rewiring portion arranged on the main surface of the insulating layer.
  16. 　前記封止樹脂は、前記樹脂裏面側に、前記厚さ方向視において前記第１半導体素子に重なる樹脂開口を備えている、請求項１ないし１５のいずれかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 15, wherein the sealing resin is provided with a resin opening that overlaps with the first semiconductor element in the thickness direction on the back surface side of the resin.
  17. 　前記第１半導体素子の前記素子裏面は、前記樹脂開口から露出している、請求項１６に記載の半導体装置。 The semiconductor device according to claim 16, wherein the back surface of the first semiconductor element is exposed from the resin opening.
  18. 　前記第１半導体素子の前記素子裏面である第１素子裏面に接合されたヒートスプレッダをさらに備え、
    　前記ヒートスプレッダは、
    　前記第１素子裏面に対向するスプレッダ主面と、
    　前記厚さ方向において前記スプレッダ主面とは反対側を向くスプレッダ裏面と、
    を有し、
    　前記スプレッダ裏面は、前記樹脂開口から露出している、請求項１６に記載の半導体装置。     A heat spreader bonded to the back surface of the first element, which is the back surface of the element of the first semiconductor element, is further provided.
    The heat spreader
    The main surface of the spreader facing the back surface of the first element and
    The back surface of the spreader facing the opposite side of the main surface of the spreader in the thickness direction,
    Have,
    The semiconductor device according to claim 16, wherein the back surface of the spreader is exposed from the resin opening.
PCT/JP2021/013300 2020-04-08 2021-03-29 Semiconductor device WO2021205926A1 (en)

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JP2022514419A JPWO2021205926A1 (en) 2020-04-08 2021-03-29
CN202180024850.3A CN115335992A (en) 2020-04-08 2021-03-29 Semiconductor device with a plurality of semiconductor chips
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JP2016213466A (en) * 2015-05-11 2016-12-15 サムソン エレクトロ−メカニックス カンパニーリミテッド． Fan-out semiconductor package and manufacturing method of the same
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