WO2021192245A1 - High heat-dissipation module structure - Google Patents

High heat-dissipation module structure Download PDF

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Publication number
WO2021192245A1
WO2021192245A1 PCT/JP2020/014109 JP2020014109W WO2021192245A1 WO 2021192245 A1 WO2021192245 A1 WO 2021192245A1 JP 2020014109 W JP2020014109 W JP 2020014109W WO 2021192245 A1 WO2021192245 A1 WO 2021192245A1
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WO
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Prior art keywords
layer
core layer
opening
heat dissipation
metal core
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PCT/JP2020/014109
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French (fr)
Japanese (ja)
Inventor
横田英樹
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太陽誘電株式会社
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Priority to PCT/JP2020/014109 priority Critical patent/WO2021192245A1/en
Publication of WO2021192245A1 publication Critical patent/WO2021192245A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks

Definitions

  • the present invention relates to a high heat dissipation module structure.
  • Patent Documents 1 and 2 In order to increase the mounting density of electronic components, it is known that not only the electronic components are mounted on the surface of the substrate but also the modular structure in which the electronic components are embedded in the substrate (for example, Patent Documents 1 and 2).
  • the characteristics of the semiconductor component may fluctuate due to the stress applied to the semiconductor component when the heat sink is mounted on the semiconductor component in the module assembly process or during use after modularization.
  • the present invention has been made in view of the above problems, and an object of the present invention is to improve heat dissipation from a semiconductor component and reduce stress applied to the semiconductor component.
  • the present invention includes a metal core layer having a first opening, a semiconductor component provided in the first opening, and a heat radiating member joined to at least a part of the upper surface of the metal core layer and the upper surface of the semiconductor component.
  • the first insulating layer provided under the metal core layer, the first metal layer provided on the lower surface of the first insulating layer, and the metal core layer and the first metal layer provided in the first insulating layer. It is a high heat dissipation module structure including a first wiring for connecting one metal layer.
  • the heat radiating member may be joined to at least a part of the upper surface of the metal core layer surrounding the first opening.
  • the first opening has a substantially quadrangular shape
  • the heat radiating member is joined to an outer region of at least two opposite sides of the first opening on the upper surface of the metal core layer. be able to.
  • the electronic component provided in the second opening of the metal core layer may be provided, and the heat radiating member may not be provided above the electronic component.
  • the electronic component provided in the second opening of the metal core layer may be provided, and the heat radiating member may be provided above the electronic component and not joined to the upper surface of the electronic component. can.
  • the heat radiating member is joined to the upper surface of the metal core layer with at least a part of the first region surrounding the first opening and the second region on the opposite side of the semiconductor component with the electronic component interposed therebetween.
  • the electronic component provided in the second opening of the metal core layer is provided, and the heat radiating member includes at least a part of the first region of the upper surface of the metal core layer surrounding the first opening and the metal.
  • the structure is such that at least a part of the second region surrounding the second opening of the upper surface of the core layer is joined to the upper surface of the electronic component, and the first region and the second region are not connected. Can be done.
  • a second insulating layer provided on the metal core layer, surrounding the heat radiating member, and exposing the upper surface of the heat radiating member can be provided.
  • a plurality of the semiconductor components may be provided in the first opening, and the heat radiating member may be joined to the upper surface of the plurality of semiconductor components.
  • the present invention it is possible to improve the heat dissipation from the semiconductor component and reduce the stress applied to the semiconductor component.
  • 1 (a) and 1 (b) are a cross-sectional view and a plan view of the high heat dissipation module structure according to the first embodiment.
  • 2 (a) and 2 (b) are cross-sectional views of the module structure according to Comparative Example 1.
  • 3 (a) and 3 (b) are cross-sectional views of the high heat dissipation module structure according to the first embodiment.
  • 4 (a) to 4 (d) are plan views showing the heat radiating plate and the bonding layer in the first embodiment.
  • 5 (a) and 5 (b) are a cross-sectional view and a plan view of the high heat dissipation module structure according to the first modification of the first embodiment.
  • 6 (a) and 6 (b) are a cross-sectional view and a plan view of the high heat dissipation module structure according to the second modification of the first embodiment.
  • 7 (a) to 7 (c) are plan views showing the heat radiating plate and the bonding layer in the modified example 3 of the first embodiment.
  • FIG. 1 (a) and 1 (b) are a cross-sectional view and a plan view of the high heat dissipation module structure according to the first embodiment.
  • FIG. 1B mainly illustrates the core layer 10 (cross-hatching), the heat sink 36 (dotted line), the bonding layer 38 (broken line), the semiconductor component 40, the electronic components 42 and 44, and the like.
  • the outer circumference of the heat sink 36 and the outer circumference of the joint layer 38 are substantially the same, but in FIG. 1 (b), the outer circumference of the heat sink 36 and the outer circumference of the joint layer 38 are for easy viewing. Is shown separately.
  • the outer circumference of the joint layer 38 may be located inside or outside the heat sink 36.
  • FIG. 1A corresponds to the AA cross section of FIG. 1B.
  • the core layer 10 has openings 12, 13 and 14.
  • the semiconductor component 40 is provided in the opening 12 (first opening).
  • the semiconductor component 40 has an electrode 41 on the lower surface (front surface).
  • An electronic component 42 is provided in the opening 13 (second opening).
  • the electronic component 42 has an electrode 43 on the lower surface.
  • An electronic component 44 is provided in the opening 14.
  • the electronic component 44 has an electrode 45.
  • An insulating layer 20 is provided in the openings 12 to 14 so as to seal the semiconductor component 40 and the electronic components 42 and 44.
  • An insulating layer 22 is provided under the insulating layer 20 and the core layer 10. Vias 31 (via plugs) that penetrate the insulating layer 22 and connect to the electrodes 41, 43, 45 and the core layer 10 are provided.
  • a metal layer 32 connected to the via 31 is provided under the insulating layer 22.
  • An insulating layer 24 is provided under the insulating layer 22 so as to cover the metal layer 32.
  • the insulating layers 22 and 24 form an insulating layer 23 (first insulating layer).
  • a via 33 is provided that penetrates the insulating layer 24 and connects to the metal layer 32.
  • a metal layer 34 connected to the via 33 is provided under the insulating layer 24.
  • a solder resist 26 that covers the metal layer 34 is provided under the insulating layer 24.
  • a part of the metal layer 34 is exposed to the opening 27 of the solder resist 26.
  • the metal layer 34 exposed to the opening 27 functions as a terminal for connecting the high heat dissipation module structure to the outside such as a mounting board.
  • the metal layer 34a first metal layer
  • the metal layer 34b second metal layer
  • the electrode 41 of the semiconductor component 40 via the wiring 35b (second wiring) including the via 33, the metal layer 32, and the via 31.
  • a heat radiating plate 36 (heat radiating member) is bonded to the upper surface of the semiconductor component 40 and the upper surface of the core layer 10 around the opening 12 via a bonding layer 38.
  • An insulating layer 28 (second insulating layer) is provided on the core layer 10, the electronic components 42, and 44 so as to surround the heat radiating plate 36. The upper surface of the heat radiating plate 36 is exposed from the insulating layer 28.
  • the core layer 10 is, for example, a metal core layer made of a metal material whose main material is copper, a metal material whose main component is iron, or a metal material whose main material is aluminum.
  • the insulating layers 20, 22, 24 and 28 are, for example, synthetic resins, such as epoxy resins, bismaleimide triazine resins or polyimide resins.
  • the insulating layers 20, 22, 24 and 28 may be a synthetic resin mixed with an inorganic filler such as silica.
  • the metal layers 32 and 34 are layers mainly made of, for example, copper, gold or silver, and may include a barrier layer such as titanium, nickel, chromium and titanium nitride and an adhesion layer as the base layer of the metal layers 32 and 34. good.
  • the vias 31 and 33 are layers mainly made of, for example, copper, gold or silver.
  • the solder resist 26 is a synthetic resin such as an epoxy resin.
  • the thickness of the core layer 10 is, for example, 340 ⁇ m, for example, 30 ⁇ m to 1000 ⁇ m.
  • the thickness of the insulating layer 22 is, for example, 20 ⁇ m, for example, 10 ⁇ m to 100 ⁇ m, respectively.
  • the thickness of the insulating layer 24 is, for example, 30 ⁇ m, for example, 5 ⁇ m to 100 ⁇ m, respectively.
  • the thickness of the metal layers 32 and 34 is, for example, 12 ⁇ m, for example 5 ⁇ m to 100 ⁇ m.
  • the thickness of the solder resist 26 is, for example, 25 ⁇ m, for example, 5 ⁇ m to 100 ⁇ m.
  • the semiconductor component 40 includes, for example, a power transistor 48 such as an IGBT (Insulated Gate Bipolar Transistor), a bipolar transistor, or a FET (Field Effect Transistor).
  • a semiconductor material such as Si, GaN or SiC is used for the transistor.
  • the semiconductor component 40 is, for example, a bare chip or a package in which a bare chip is sealed and mounted.
  • the package on which the bare chip is mounted is a package such as WLP (Wafer Level Package).
  • the semiconductor component 40 is a bare chip of a horizontal transistor such as a GaN FET.
  • the thickness of the semiconductor component 40 is, for example, 10 ⁇ m to several hundred ⁇ m.
  • the thickness of the semiconductor component 40 is, for example, less than or equal to the thickness of the core layer 10.
  • the electronic component 42 is, for example, an integrated circuit having a silicon substrate, and controls a transistor provided in the semiconductor component 40.
  • the electronic component 42 is, for example, a bare chip or a package in which a bare chip is sealed and mounted.
  • the electronic component 44 is a discrete passive component such as a chip capacitor, a chip inductor or a chip resistor.
  • the electronic component 44 has external electrodes 45 at both ends.
  • the electrodes 41, 43 and 45 are metal layers mainly made of, for example, copper, gold, silver or aluminum.
  • the heat radiating plate 36 (heat radiating member) is a metal layer such as a copper layer or an aluminum layer or an insulating layer such as aluminum oxide or aluminum nitride.
  • the heat sink 36 may be a heat sink in which an insulating layer such as DBC (Direct Bonded Cupper) or DBA (Direct Bonded Aluminum) is sandwiched between metal layers.
  • the thickness of the heat radiating plate 36 is, for example, 100 ⁇ m to several mm.
  • the bonding layer 38 is a sintered metal layer in which a conductive paste such as silver paste is sintered, or a brazing material such as solder.
  • the thickness of the bonding layer 38 is, for example, several tens of ⁇ m.
  • the heat generated in the semiconductor component 40 is conducted to the heat sink 36 as in the path 50, and is discharged to the outside from the heat sink 36. Further, heat is conducted through the via 31, the metal layer 32, the via 33 and the metal layer 34, and is released from the metal layer 34 to the outside (for example, a mounting substrate).
  • paths 50 and 52 alone are not sufficient heat release paths.
  • Comparative Example 1 when the heat sink 36 is mounted on the semiconductor component 40 in the process of manufacturing the module, or when the module is used, as shown by the arrow 60.
  • stress is applied to the heat sink 36
  • stress is applied to the semiconductor component 40 as shown by arrow 64.
  • the characteristics of the semiconductor component 40 may change.
  • the semiconductor component 40 is a bare chip of a GaN FET
  • the characteristics of the GaN FET change (deteriorate) when stress is applied to the chip.
  • 3 (a) and 3 (b) are cross-sectional views of the high heat dissipation module structure according to the first embodiment, and is an enlarged view of the vicinity of the semiconductor component 40 of FIG. 1 (a).
  • the heat sink 36 is joined to at least a part of the upper surface of the core layer 10 and the upper surface of the semiconductor component 40.
  • heat is conducted from the heat sink 36 to the core layer 10 like the path 54.
  • Heat is conducted in the core layer 10 as in the path 56.
  • heat is conducted from the core layer 10 to the metal layer 34a via the wiring 35a provided in the insulating layer 23 and connecting the core layer 10 and the metal layer 34a as in the path 58.
  • the heat dissipation from the semiconductor component 40 can be improved by these paths.
  • heat is conducted from the semiconductor component 40 to the metal layer 34b via the wiring 35b provided in the insulating layer 23 and connecting the core layer 10 and the metal layer 34b as in the path 52. This path can further improve the heat dissipation from the semiconductor component 40.
  • the heat sink 36 when the heat sink 36 is mounted on the semiconductor component 40 or when the module is used, stress is applied to the heat sink 36 as shown by an arrow 60.
  • stress is applied to the core layer 10 rather than the semiconductor component 40 as shown by the arrow 62.
  • the stress applied to the semiconductor component 40 becomes smaller than that in FIG. 2 (b) of Comparative Example 1. Therefore, the change (deterioration) of the characteristics of the semiconductor component 40 can be suppressed.
  • the semiconductor component 40 is a bare chip of a GaN FET, the change (deterioration) in the characteristics of the GaN FET due to stress can be further suppressed.
  • planar shapes of the semiconductor component 40 is a substantially rectangular shape (for example, a substantially rectangular shape)
  • planar shape of the opening 12 is a substantially rectangular shape (for example, a substantially rectangular shape).
  • the heat sink 36 overlaps all of the openings 12, and the bonding layer 38 is provided in the outer region of all four sides of the opening 12. As a result, heat can be efficiently conducted from the heat sink 36 to the core layer 10. Therefore, heat dissipation can be improved.
  • the distance D1 is preferably 2 mm or less.
  • the distance D1 is preferably 25 ⁇ m or more in consideration of the alignment for mounting the semiconductor component 40 in the opening 12.
  • the width D2 of the bonding layer 38 that is, the width of the region where the heat sink 36 is bonded to the core layer 10.
  • the width D2 is preferably 50 ⁇ m or more. In order to increase the heat dissipation of the path 54, it is preferable to increase the width D2.
  • the bonding layer 38 is provided in the region outside the three sides of the opening 12, and the heat sink 36 is bonded to the core layer 10 in the region outside the three sides of the opening 12. ..
  • the bonding layer 38 is provided in the outer region of the two opposite sides of the opening 12, and the heat sink 36 is bonded to the core layer 10 in the outer region of the two opposite sides of the opening 12. ing.
  • the bonding layer 38 is provided in the region outside one side of the opening 12, and the heat sink 36 is bonded to the core layer 10 in the region outside one side of the opening 12. ..
  • the heat sink 36 is joined to at least a part of the upper surface of the core layer 10 surrounding the opening 12.
  • the heat generated in the semiconductor component 40 is transmitted from the heat radiating plate 36 to the core layer 10, so that the heat radiating property can be improved.
  • the heat sink 36 is formed as shown in FIGS. 4 (a) to 4 (c). It is preferable that the upper surface of the core layer 10 is joined to the outer regions of at least two opposite sides of the opening 12.
  • the heat sink 36 is joined to the outer regions of at least two opposite long sides of the inner opening 12 on the upper surface of the core layer 10. As a result, the stress of the arrow 60 is dispersed in the core layer 10, and the stress applied to the semiconductor component 40 can be suppressed.
  • FIG. 5A and 5 (b) are a cross-sectional view and a plan view of the high heat dissipation module structure according to the first modification of the first embodiment.
  • FIG. 5A corresponds to the AA cross section of FIG. 5B.
  • the heat sink 36 is also arranged above the electronic components 42 and 44.
  • the heat sink 36 is not joined to the electronic components 42 and 44.
  • the bonding layer 38 is provided in the upper surface of the semiconductor component 40 and the upper surface region of the core layer 10 outside the opening 12, and the bonding layer 38a is a core layer at the end of the heat sink 36 opposite to the semiconductor component 40 with the electronic component 42 sandwiched therein. It is provided on the upper surface of 10. No bonding layer is provided on the other parts of the heat sink 36.
  • Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.
  • the heat sink 36 In order to improve heat dissipation, it is preferable to increase the heat sink 36. Therefore, it is preferable that the heat sink 36 is provided above the electronic components 42 and 44. However, when the electronic component 44 is connected to the heat sink 36 with a joining material, both electrodes 45 of the electronic component 44 are short-circuited. Further, when the heat sink 36 is joined to the electronic components 42 and 44, the heat generated in the semiconductor component 40 raises the temperature of the electronic components 42 and 44. Therefore, it is preferable that the heat sink 36 is not bonded to the upper surface of the electronic component 42. Further, when the heat radiating plate 36 is joined to the entire heat radiating plate 36, the thermal stress becomes large.
  • the bonding layer 38 should be provided on the upper surface of the semiconductor component 40 that generates heat and the upper surface of the core layer 10 in the vicinity thereof, and the bonding layer 38 should not be provided on the upper surfaces of the other electronic components 42 and 44 and the upper surface of the other core layer 10. Is preferable.
  • the bonding layer 38 When the bonding layer 38 is provided only in a part of the upper surface of the core layer 10, a clearance is formed between the heat sink 36 and the core layer 10, and the thermal stress is relaxed. However, if the heat sink 36 is large, the heat sink 36 is tilted with respect to the upper surface of the core layer 10. Therefore, a bonding layer 38a is provided at the end of the heat radiating plate 36. As a result, it is possible to prevent the heat radiating plate 36 from tilting with respect to the upper surface of the core layer 10. For example, when the heat radiating plate 36 is not joined to the electronic component 42, the heat radiating plate 36 sandwiches at least a part of the first region surrounding the opening 12 on the upper surface of the core layer 10 and the electronic component 42 with the semiconductor component 40. It is joined to the second region on the opposite side. As a result, even if the heat sink 36 is not joined to the electronic component 42, it is possible to prevent the heat sink 36 from tilting with respect to the upper surface of the core layer 10.
  • FIG. 6A and 6 (b) are a cross-sectional view and a plan view of the high heat dissipation module structure according to the second modification of the first embodiment.
  • FIG. 6A corresponds to the AA cross section of FIG. 6B.
  • the heat sink 36 is also arranged above the electronic components 42 and 44.
  • the heat sink 36 is joined to the electronic component 42, not to the electronic component 44.
  • the bonding layer 38 is provided in the upper surface region of the semiconductor component 40 and the upper surface region of the core layer 10 outside the opening 12, and the bonding layer 38b is provided in the upper surface region of the electronic component 42 and the upper surface region of the core layer 10 outside the opening 13. Has been done. No bonding layer is provided between the bonding layers 38 and 38b.
  • Other configurations are the same as those of the first modification of the first embodiment, and the description thereof will be omitted.
  • the heat radiating plate 36 includes at least a first region of the upper surface of the semiconductor component 40 and the upper surface of the core layer 10 surrounding the opening 12, and the upper surface of the electronic component 42 and the upper surface of the electronic component 42. It is joined to at least a part of the second region surrounding the opening 13 of the upper surface of the core layer 10. Thereby, the heat dissipation from the semiconductor component 40 and the electronic component 42 can be improved.
  • the thermal stress becomes large.
  • the heat sink 36 is not bonded to the upper surface of the core layer 10 in the region between the bonding layers 38 and 38b or in the upper surface of the electronic component 44 or in the vicinity thereof. That is, it is preferable that the first region and the second region are not connected. If thermal stress is not a problem, the bonding layers 38 and 38b may be connected.
  • the electronic component 42 may include a power transistor 48 similar to the semiconductor component 40.
  • FIG. 7A two semiconductor parts 40a and 40b are housed in one opening 12.
  • One heat sink 36 is joined to the upper surfaces of the semiconductor parts 40a and 40b via a joining layer 38.
  • the heat radiating plate 36 is joined to a region surrounding the opening 12 on the upper surface of the core layer 10 via a joining layer 38.
  • Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.
  • two semiconductor parts 40a and 40b are housed in one opening 12.
  • One heat sink 36 is joined to the upper surfaces of the semiconductor parts 40a and 40b via the joining layers 38a and 38b, respectively.
  • Two bonding layers 38a and 38b are provided corresponding to the semiconductor components 40a and 40b, and are separated from each other.
  • Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.
  • two semiconductor parts 40a and 40b are housed in one opening 12.
  • the two heat sinks 36a and 36b are joined to the upper surfaces of the semiconductor parts 40a and 40b via the joining layers 38a and 38b, respectively.
  • Two heat sinks 36a and 36b are provided corresponding to the semiconductor parts 40a and 40b, and are separated from each other.
  • Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.
  • a plurality of semiconductor parts 40a and 40b may be provided in one opening 12.
  • One heat sink 36 and one bonding layer 38 may be provided for one opening 12, or a plurality of heat sinks 36a and 36b and a plurality of bonding layers 38a and 38b are provided corresponding to the semiconductor parts 40a and 40b. It may have been.
  • a plurality of semiconductor parts 40a and 40b may be provided in one opening 12.

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Abstract

This high heat-dissipation module structure comprises: a metal core layer 10 having a first opening 12; a semiconductor component 40 provided inside the first opening 12; a heat dissipation member joined to at least a portion of the upper surface of the metal core layer 10 and to the upper surface of the semiconductor component 40; a first insulating layer 23 provided under the metal core layer 10; a first metal layer 34a provided to the lower surface of the first insulating layer 23; and a first wire 35a that is provided inside the first insulating layer 23 and connects the metal core layer 10 and the first metal layer 34a.　

Description

高放熱モジュール構造High heat dissipation module structure
　本発明は、高放熱モジュール構造に関する。 The present invention relates to a high heat dissipation module structure.
　電子部品の実装密度を高くするため、基板の表面に電子部品を実装するだけでなく、基板に電子部品を内蔵するモジュール構造が知られている（例えば特許文献１および２)。 In order to increase the mounting density of electronic components, it is known that not only the electronic components are mounted on the surface of the substrate but also the modular structure in which the electronic components are embedded in the substrate (for example, Patent Documents 1 and 2).
特開２０１３－４２１３６号公報Japanese Unexamined Patent Publication No. 2013-42136 特開２００８－２１８５２１号公報Japanese Unexamined Patent Publication No. 2008-218521
　パワートランジスタ等の半導体部品を有するモジュール構造おいて、発熱する半導体部品の熱を効率よくモジュール外へ逃がすことは、そのモジュールの発揮する特性・機能にも影響する重要な要素である。そのため、いかにして多くの熱を放熱させるかが重要になり、それを考慮した構造が求められている。また、モジュール組み立て工程内での半導体部品への放熱板搭載時や、モジュール化した後の使用中において半導体部品にかかる応力により、半導体部品の特性が変動する場合がある。 In a module structure having semiconductor parts such as power transistors, efficiently releasing the heat of the semiconductor parts that generate heat to the outside of the module is an important factor that affects the characteristics and functions of the module. Therefore, how to dissipate a lot of heat is important, and a structure that takes this into consideration is required. In addition, the characteristics of the semiconductor component may fluctuate due to the stress applied to the semiconductor component when the heat sink is mounted on the semiconductor component in the module assembly process or during use after modularization.
　本発明は、上記課題に鑑みなされたものであり、半導体部品からの放熱性を向上させ、かつ半導体部品に加わる応力を低減させることを目的とする。 The present invention has been made in view of the above problems, and an object of the present invention is to improve heat dissipation from a semiconductor component and reduce stress applied to the semiconductor component.
　本発明は、第１開口を有する金属コア層と、前記第１開口内に設けられた半導体部品と、前記金属コア層の上面の少なくとも一部および前記半導体部品の上面に接合された放熱部材と、前記金属コア層下に設けられた第１絶縁層と、前記第１絶縁層の下面に設けられた第１金属層と、前記第１絶縁層内に設けられ、前記金属コア層と前記第１金属層とを接続する第１配線と、を備える高放熱モジュール構造である。 The present invention includes a metal core layer having a first opening, a semiconductor component provided in the first opening, and a heat radiating member joined to at least a part of the upper surface of the metal core layer and the upper surface of the semiconductor component. , The first insulating layer provided under the metal core layer, the first metal layer provided on the lower surface of the first insulating layer, and the metal core layer and the first metal layer provided in the first insulating layer. It is a high heat dissipation module structure including a first wiring for connecting one metal layer.
　上記構成において、前記放熱部材は、前記金属コア層の上面うち前記第１開口を囲む少なくとも一部の領域に接合されている構成とすることができる。 In the above configuration, the heat radiating member may be joined to at least a part of the upper surface of the metal core layer surrounding the first opening.
　上記構成において、前記第１絶縁層の下面に設けられた第２金属層と、前記第１絶縁層内に設けられ、前記金属コア層と前記第２金属層とを接続する第２配線と、を備える構成とすることができる。 In the above configuration, a second metal layer provided on the lower surface of the first insulating layer, a second wiring provided in the first insulating layer and connecting the metal core layer and the second metal layer, and Can be configured to include.
　上記構成において、前記第１開口は略四角形状であり、前記放熱部材は、前記金属コア層の上面のうち前記第１開口の少なくとも対向する２辺の外側の領域に接合されている構成とすることができる。 In the above configuration, the first opening has a substantially quadrangular shape, and the heat radiating member is joined to an outer region of at least two opposite sides of the first opening on the upper surface of the metal core layer. be able to.
　上記構成において、前記金属コア層の第２開口内に設けられた電子部品を備え、前記放熱部材は前記電子部品の上方に設けられていない構成とすることができる。 In the above configuration, the electronic component provided in the second opening of the metal core layer may be provided, and the heat radiating member may not be provided above the electronic component.
　上記構成において、前記金属コア層の第２開口内に設けられた電子部品を備え、前記放熱部材は前記電子部品の上方に設けられ、前記電子部品の上面に接合されていない構成とすることができる。 In the above configuration, the electronic component provided in the second opening of the metal core layer may be provided, and the heat radiating member may be provided above the electronic component and not joined to the upper surface of the electronic component. can.
　上記構成において、前記放熱部材は、前記金属コア層の上面にうち前記第１開口を囲む少なくとも一部の第１領域および前記電子部品を挟み前記半導体部品と反対側の第２領域と接合されている構成とすることができる。 In the above configuration, the heat radiating member is joined to the upper surface of the metal core layer with at least a part of the first region surrounding the first opening and the second region on the opposite side of the semiconductor component with the electronic component interposed therebetween. Can be configured as
　上記構成において、前記金属コア層の第２開口内に設けられた電子部品を備え、前記放熱部材は、前記金属コア層の上面うち前記第１開口を囲む少なくとも一部の第１領域および前記金属コア層の上面うち前記第２開口を囲む少なくとも一部の第２領域と、前記電子部品の上面に接合され、前記第１領域と前記第２領域との間が接続されていない構成とすることができる。 In the above configuration, the electronic component provided in the second opening of the metal core layer is provided, and the heat radiating member includes at least a part of the first region of the upper surface of the metal core layer surrounding the first opening and the metal. The structure is such that at least a part of the second region surrounding the second opening of the upper surface of the core layer is joined to the upper surface of the electronic component, and the first region and the second region are not connected. Can be done.
　上記構成において、前記金属コア層上に設けられ、前記放熱部材を囲み、前記放熱部材の上面が露出する第２絶縁層を備える構成とすることができる。 In the above configuration, a second insulating layer provided on the metal core layer, surrounding the heat radiating member, and exposing the upper surface of the heat radiating member can be provided.
　上記構成において、前記第１開口内に複数の前記半導体部品が設けられ、前記放熱部材は前記複数の半導体部品の上面に接合されている構成とすることができる。 In the above configuration, a plurality of the semiconductor components may be provided in the first opening, and the heat radiating member may be joined to the upper surface of the plurality of semiconductor components.
　本発明によれば、半導体部品からの放熱性を向上させ、かつ半導体部品に加わる応力を低減させることができる。 According to the present invention, it is possible to improve the heat dissipation from the semiconductor component and reduce the stress applied to the semiconductor component.
図１（ａ）および図１（ｂ）は、実施例１に係る高放熱モジュール構造の断面図および平面図である。1 (a) and 1 (b) are a cross-sectional view and a plan view of the high heat dissipation module structure according to the first embodiment. 図２（ａ）および図２（ｂ）は、比較例１に係るモジュール構造の断面図である。2 (a) and 2 (b) are cross-sectional views of the module structure according to Comparative Example 1. 図３（ａ）および図３（ｂ）は、実施例１に係る高放熱モジュール構造の断面図である。3 (a) and 3 (b) are cross-sectional views of the high heat dissipation module structure according to the first embodiment. 図４（ａ）から図４（ｄ）は、実施例１における放熱板および接合層を示す平面図である。4 (a) to 4 (d) are plan views showing the heat radiating plate and the bonding layer in the first embodiment. 図５（ａ）および図５（ｂ）は、実施例１の変形例１に係る高放熱モジュール構造の断面図および平面図である。5 (a) and 5 (b) are a cross-sectional view and a plan view of the high heat dissipation module structure according to the first modification of the first embodiment. 図６（ａ）および図６（ｂ）は、実施例１の変形例２に係る高放熱モジュール構造の断面図および平面図である。6 (a) and 6 (b) are a cross-sectional view and a plan view of the high heat dissipation module structure according to the second modification of the first embodiment. 図７（ａ）から図７（ｃ）は、実施例１の変形例３における放熱板および接合層を示す平面図である。7 (a) to 7 (c) are plan views showing the heat radiating plate and the bonding layer in the modified example 3 of the first embodiment.
　以下、図面を参照し本発明の実施例について説明する。 Hereinafter, examples of the present invention will be described with reference to the drawings.
　図１（ａ）および図１（ｂ）は、実施例１に係る高放熱モジュール構造の断面図および平面図である。図１（ｂ）は、主にコア層１０（クロスハッチング）、放熱板３６（点線）、接合層３８（破線）、半導体部品４０、電子部品４２および４４等を図示している。図１（ａ）のように、放熱板３６の外周と接合層３８の外周とは略一致しているが、図１（ｂ）では、見やすいように放熱板３６の外周と接合層３８の外周を離して図示している。なお、接合層３８の外周は放熱板３６の内側に位置してもよいし、外側に位置してもよい。図１（ａ）は、図１（ｂ）のＡ－Ａ断面に相当する。 1 (a) and 1 (b) are a cross-sectional view and a plan view of the high heat dissipation module structure according to the first embodiment. FIG. 1B mainly illustrates the core layer 10 (cross-hatching), the heat sink 36 (dotted line), the bonding layer 38 (broken line), the semiconductor component 40, the electronic components 42 and 44, and the like. As shown in FIG. 1 (a), the outer circumference of the heat sink 36 and the outer circumference of the joint layer 38 are substantially the same, but in FIG. 1 (b), the outer circumference of the heat sink 36 and the outer circumference of the joint layer 38 are for easy viewing. Is shown separately. The outer circumference of the joint layer 38 may be located inside or outside the heat sink 36. FIG. 1A corresponds to the AA cross section of FIG. 1B.
　図１（ａ）および図１（ｂ）に示すように、コア層１０は開口１２、１３および１４を有する。開口１２（第１開口）内に半導体部品４０が設けられている。半導体部品４０は、下面（表の面）に電極４１を有する。開口１３（第２開口）内に電子部品４２が設けられている。電子部品４２は、下面に電極４３を有する。開口１４内に電子部品４４が設けられている。電子部品４４は、電極４５を有する。 As shown in FIGS. 1 (a) and 1 (b), the core layer 10 has openings 12, 13 and 14. The semiconductor component 40 is provided in the opening 12 (first opening). The semiconductor component 40 has an electrode 41 on the lower surface (front surface). An electronic component 42 is provided in the opening 13 (second opening). The electronic component 42 has an electrode 43 on the lower surface. An electronic component 44 is provided in the opening 14. The electronic component 44 has an electrode 45.
　開口１２～１４内に半導体部品４０、電子部品４２および４４を封止するように絶縁層２０が設けられている。絶縁層２０およびコア層１０下に絶縁層２２が設けられている。絶縁層２２を貫通し電極４１、４３、４５およびコア層１０に接続するビア３１（ビアプラグ）が設けられている。絶縁層２２下にビア３１に接続する金属層３２が設けられている。絶縁層２２下に金属層３２を覆うように絶縁層２４が設けられている。絶縁層２２と２４とは絶縁層２３（第１絶縁層）を形成する。絶縁層２４を貫通し金属層３２に接続するビア３３が設けられている。絶縁層２４下にビア３３に接続する金属層３４が設けられている。絶縁層２４下に金属層３４を覆うソルダーレジスト２６が設けられている。 An insulating layer 20 is provided in the openings 12 to 14 so as to seal the semiconductor component 40 and the electronic components 42 and 44. An insulating layer 22 is provided under the insulating layer 20 and the core layer 10. Vias 31 (via plugs) that penetrate the insulating layer 22 and connect to the electrodes 41, 43, 45 and the core layer 10 are provided. A metal layer 32 connected to the via 31 is provided under the insulating layer 22. An insulating layer 24 is provided under the insulating layer 22 so as to cover the metal layer 32. The insulating layers 22 and 24 form an insulating layer 23 (first insulating layer). A via 33 is provided that penetrates the insulating layer 24 and connects to the metal layer 32. A metal layer 34 connected to the via 33 is provided under the insulating layer 24. A solder resist 26 that covers the metal layer 34 is provided under the insulating layer 24.
　金属層３４の一部はソルダーレジスト２６の開口２７に露出する。開口２７に露出する金属層３４は、高放熱モジュール構造を実装基板等の外部と接続するための端子として機能する。金属層３４のうち金属層３４ａ（第１金属層）はビア３３、金属層３２およびビア３１を含む配線３５ａ（第１配線）を介しコア層１０に接続される。金属層３４のうち金属層３４ｂ（第２金属層）はビア３３、金属層３２およびビア３１を含む配線３５ｂ（第２配線）を介し半導体部品４０の電極４１に接続される。 A part of the metal layer 34 is exposed to the opening 27 of the solder resist 26. The metal layer 34 exposed to the opening 27 functions as a terminal for connecting the high heat dissipation module structure to the outside such as a mounting board. Of the metal layers 34, the metal layer 34a (first metal layer) is connected to the core layer 10 via a wiring 35a (first wiring) including the via 33, the metal layer 32, and the via 31. Of the metal layers 34, the metal layer 34b (second metal layer) is connected to the electrode 41 of the semiconductor component 40 via the wiring 35b (second wiring) including the via 33, the metal layer 32, and the via 31.
　半導体部品４０の上面および開口１２の周辺のコア層１０の上面に接合層３８を介し放熱板３６（放熱部材）が接合されている。コア層１０、電子部品４２および４４上に放熱板３６を囲むように絶縁層２８（第２絶縁層）が設けられている。放熱板３６の上面は絶縁層２８から露出する。 A heat radiating plate 36 (heat radiating member) is bonded to the upper surface of the semiconductor component 40 and the upper surface of the core layer 10 around the opening 12 via a bonding layer 38. An insulating layer 28 (second insulating layer) is provided on the core layer 10, the electronic components 42, and 44 so as to surround the heat radiating plate 36. The upper surface of the heat radiating plate 36 is exposed from the insulating layer 28.
　コア層１０は、例えば銅を主材料とする金属材料、鉄を主成分とする金属材料、またはアルミニウムを主材料とする金属材料からなる金属コア層である。絶縁層２０、２２、２４および２８は、例えば合成樹脂であり、エポキシ樹脂、ビスマレイミドトリアジン樹脂またはポリイミド樹脂である。絶縁層２０、２２，２４および２８は、例えば合成樹脂にシリカ等の無機フィラーが混合されていてもよい。金属層３２および３４は、例えば銅、金または銀を主材料とする層であり、金属層３２および３４の下地層として、チタン、ニッケル、クロム、窒化チタン等のバリア層および密着層を含んでもよい。ビア３１および３３は、例えば銅、金または銀を主材料とする層である。ソルダーレジスト２６は、例えばエポキシ樹脂等の合成樹脂である。 The core layer 10 is, for example, a metal core layer made of a metal material whose main material is copper, a metal material whose main component is iron, or a metal material whose main material is aluminum. The insulating layers 20, 22, 24 and 28 are, for example, synthetic resins, such as epoxy resins, bismaleimide triazine resins or polyimide resins. The insulating layers 20, 22, 24 and 28 may be a synthetic resin mixed with an inorganic filler such as silica. The metal layers 32 and 34 are layers mainly made of, for example, copper, gold or silver, and may include a barrier layer such as titanium, nickel, chromium and titanium nitride and an adhesion layer as the base layer of the metal layers 32 and 34. good. The vias 31 and 33 are layers mainly made of, for example, copper, gold or silver. The solder resist 26 is a synthetic resin such as an epoxy resin.
　コア層１０の厚さは、一例として３４０μｍであり、例えば３０μｍから１０００μｍである。絶縁層２２の厚さは、一例として２０μｍであり、例えば各々１０μｍから１００μｍである。絶縁層２４の厚さは、一例として３０μｍであり、例えば各々５μｍから１００μｍである。金属層３２および３４の厚さは一例として１２μｍであり、例えば５μｍから１００μｍである。ソルダーレジスト２６の厚さは一例として２５μｍであり、例えば５μｍから１００μｍである。 The thickness of the core layer 10 is, for example, 340 μm, for example, 30 μm to 1000 μm. The thickness of the insulating layer 22 is, for example, 20 μm, for example, 10 μm to 100 μm, respectively. The thickness of the insulating layer 24 is, for example, 30 μm, for example, 5 μm to 100 μm, respectively. The thickness of the metal layers 32 and 34 is, for example, 12 μm, for example 5 μm to 100 μm. The thickness of the solder resist 26 is, for example, 25 μm, for example, 5 μm to 100 μm.
　半導体部品４０は、例えばＩＧＢＴ（Insulated Gate Bipolar Transistor）、バイポーラトランジスタまたはＦＥＴ（Field Effect Transistor）等のパワートランジスタ４８を含む。トランジスタには、Ｓｉ、ＧａＮまたはＳｉＣ等の半導体材料が用いられる。半導体部品４０は、例えばベアチップまたはベアチップが封止実装されたパッケージである。ベアチップが実装されたパッケージは、ＷＬＰ（Wafer Level Package）等のパッケージである。実施例１では、半導体部品４０はＧａＮＦＥＴ等の横型トランジスタのベアチップである。半導体部品４０の厚さは例えば１０μｍから数１００μｍである。半導体部品４０の厚さは例えばコア層１０の厚さ以下である。 The semiconductor component 40 includes, for example, a power transistor 48 such as an IGBT (Insulated Gate Bipolar Transistor), a bipolar transistor, or a FET (Field Effect Transistor). A semiconductor material such as Si, GaN or SiC is used for the transistor. The semiconductor component 40 is, for example, a bare chip or a package in which a bare chip is sealed and mounted. The package on which the bare chip is mounted is a package such as WLP (Wafer Level Package). In the first embodiment, the semiconductor component 40 is a bare chip of a horizontal transistor such as a GaN FET. The thickness of the semiconductor component 40 is, for example, 10 μm to several hundred μm. The thickness of the semiconductor component 40 is, for example, less than or equal to the thickness of the core layer 10.
　電子部品４２は、例えばシリコン基板を有する集積回路であり、半導体部品４０に設けられたトランジスタを制御する。電子部品４２は、例えばベアチップまたはベアチップが封止実装されたパッケージである。電子部品４４は、例えばチップコンデンサ、チップインダクタまたはチップ抵抗等のディスクリート受動部品である。電子部品４４は両端に外部電極４５を有する。電極４１、４３および４５は、例えば銅、金、銀またはアルミニウム等を主材料とする金属層である。 The electronic component 42 is, for example, an integrated circuit having a silicon substrate, and controls a transistor provided in the semiconductor component 40. The electronic component 42 is, for example, a bare chip or a package in which a bare chip is sealed and mounted. The electronic component 44 is a discrete passive component such as a chip capacitor, a chip inductor or a chip resistor. The electronic component 44 has external electrodes 45 at both ends. The electrodes 41, 43 and 45 are metal layers mainly made of, for example, copper, gold, silver or aluminum.
　放熱板３６（放熱部材）は、銅層またはアルミニウム層等の金属層または酸化アルミニウムまたは窒化アルミニウム等の絶縁層である。放熱板３６は、ＤＢＣ（Direct Bonded Cupper）またはＤＢＡ（Direct Bonded Aluminum）等の絶縁層を金属層で挟んだ放熱板でもよい。放熱板３６の厚さは例えば１００μｍから数ｍｍである。接合層３８は、例えば銀ペースト等の導電性ペーストが焼結された焼結金属層、またははんだ等のロウ材である。接合層３８の厚さは例えば数１０μｍである。 The heat radiating plate 36 (heat radiating member) is a metal layer such as a copper layer or an aluminum layer or an insulating layer such as aluminum oxide or aluminum nitride. The heat sink 36 may be a heat sink in which an insulating layer such as DBC (Direct Bonded Cupper) or DBA (Direct Bonded Aluminum) is sandwiched between metal layers. The thickness of the heat radiating plate 36 is, for example, 100 μm to several mm. The bonding layer 38 is a sintered metal layer in which a conductive paste such as silver paste is sintered, or a brazing material such as solder. The thickness of the bonding layer 38 is, for example, several tens of μm.
［比較例１］
　図２（ａ）および図２（ｂ）は、比較例１に係るモジュール構造の断面図である。 [Comparative Example 1]
2 (a) and 2 (b) are cross-sectional views of the module structure according to Comparative Example 1.
　図２（ａ）および図２（ｂ）に示すように、比較例１では、放熱板３６は半導体部品４０上に接合されているが、コア層１０上には接合されていない。その他の構成は実施例１の図１（ａ）と同じである。 As shown in FIGS. 2A and 2B, in Comparative Example 1, the heat sink 36 is bonded on the semiconductor component 40, but not on the core layer 10. Other configurations are the same as those in FIG. 1 (a) of the first embodiment.
　図２（ａ）に示すように、比較例１では、半導体部品４０において発生した熱は、経路５０のように放熱板３６に伝導し、放熱板３６から外部に放出される。また、熱はビア３１、金属層３２、ビア３３および金属層３４を伝導し、金属層３４から外部（例えば実装基板）に放出される。しかし、経路５０および５２だけでは熱の放出経路は十分でない。 As shown in FIG. 2A, in Comparative Example 1, the heat generated in the semiconductor component 40 is conducted to the heat sink 36 as in the path 50, and is discharged to the outside from the heat sink 36. Further, heat is conducted through the via 31, the metal layer 32, the via 33 and the metal layer 34, and is released from the metal layer 34 to the outside (for example, a mounting substrate). However, paths 50 and 52 alone are not sufficient heat release paths.
　図２（ｂ）に示すように、比較例１では、例えばモジュールを製造する工程において半導体部品４０上に放熱板３６を実装するとき、またはモジュールを使用しているときに、矢印６０のように放熱板３６に応力が加わると、矢印６４のように半導体部品４０に応力が加わる。これにより、半導体部品４０の特性が変化する可能性がある。特に、半導体部品４０がＧａＮＦＥＴのベアチップの場合、チップに応力が加わると、ＧａＮＦＥＴの特性が変化（劣化）してしまう。 As shown in FIG. 2B, in Comparative Example 1, for example, when the heat sink 36 is mounted on the semiconductor component 40 in the process of manufacturing the module, or when the module is used, as shown by the arrow 60. When stress is applied to the heat sink 36, stress is applied to the semiconductor component 40 as shown by arrow 64. As a result, the characteristics of the semiconductor component 40 may change. In particular, when the semiconductor component 40 is a bare chip of a GaN FET, the characteristics of the GaN FET change (deteriorate) when stress is applied to the chip.
　図３（ａ）および図３（ｂ）は、実施例１に係る高放熱モジュール構造の断面図であり、図１（ａ）の半導体部品４０付近を拡大した図である。 3 (a) and 3 (b) are cross-sectional views of the high heat dissipation module structure according to the first embodiment, and is an enlarged view of the vicinity of the semiconductor component 40 of FIG. 1 (a).
　図３（ａ）に示すように、放熱板３６は、コア層１０の上面のうち少なくとも一部および半導体部品４０の上面に接合されている。これにより、経路５０に加え、経路５４のように放熱板３６からコア層１０に熱が伝導する。経路５６のようにコア層１０内を熱が伝導する。さらに、経路５８のように、絶縁層２３内に設けられコア層１０と金属層３４ａとを接続する配線３５ａを介しコア層１０から金属層３４ａに熱が伝導する。これらの経路により半導体部品４０からの放熱性を向上させることができる。さらに、経路５２のように、絶縁層２３内に設けられコア層１０と金属層３４ｂとを接続する配線３５ｂを介し半導体部品４０から金属層３４ｂに熱が伝導する。この経路により半導体部品４０からの放熱性をより向上させることができる。 As shown in FIG. 3A, the heat sink 36 is joined to at least a part of the upper surface of the core layer 10 and the upper surface of the semiconductor component 40. As a result, in addition to the path 50, heat is conducted from the heat sink 36 to the core layer 10 like the path 54. Heat is conducted in the core layer 10 as in the path 56. Further, heat is conducted from the core layer 10 to the metal layer 34a via the wiring 35a provided in the insulating layer 23 and connecting the core layer 10 and the metal layer 34a as in the path 58. The heat dissipation from the semiconductor component 40 can be improved by these paths. Further, heat is conducted from the semiconductor component 40 to the metal layer 34b via the wiring 35b provided in the insulating layer 23 and connecting the core layer 10 and the metal layer 34b as in the path 52. This path can further improve the heat dissipation from the semiconductor component 40.
　図３（ｂ）に示すように、実施例１では、例えば半導体部品４０上に放熱板３６を実装するとき、またはモジュールを使用しているときに、矢印６０のように放熱板３６に応力が加わると、矢印６２のように半導体部品４０よりもコア層１０に応力が加わる。これにより、半導体部品４０に加わる応力が比較例１の図２（ｂ）より小さくなる。よって、半導体部品４０の特性の変化（劣化）を抑制できる。特に、半導体部品４０がＧａＮＦＥＴのベアチップの場合、応力に起因するＧａＮＦＥＴの特性の変化（劣化）をより抑制できる。 As shown in FIG. 3B, in the first embodiment, for example, when the heat sink 36 is mounted on the semiconductor component 40 or when the module is used, stress is applied to the heat sink 36 as shown by an arrow 60. When applied, stress is applied to the core layer 10 rather than the semiconductor component 40 as shown by the arrow 62. As a result, the stress applied to the semiconductor component 40 becomes smaller than that in FIG. 2 (b) of Comparative Example 1. Therefore, the change (deterioration) of the characteristics of the semiconductor component 40 can be suppressed. In particular, when the semiconductor component 40 is a bare chip of a GaN FET, the change (deterioration) in the characteristics of the GaN FET due to stress can be further suppressed.
　図４（ａ）から図４（ｄ）は、実施例１における放熱板および接合層を示す平面図である。図４（ａ）に示すように、半導体部品４０の平面形状は略四角形状（例えば略矩形）であり、開口１２の平面形状は略四角形状（例えば略矩形）である。放熱板３６は開口１２の全てと重なり、接合層３８は開口１２の４辺全ての外側の領域に設けられている。これにより、放熱板３６からコア層１０に熱が効率よく伝導できる。よって、放熱性を向上できる。 4 (a) to 4 (d) are plan views showing the heat sink and the bonding layer in the first embodiment. As shown in FIG. 4A, the planar shape of the semiconductor component 40 is a substantially rectangular shape (for example, a substantially rectangular shape), and the planar shape of the opening 12 is a substantially rectangular shape (for example, a substantially rectangular shape). The heat sink 36 overlaps all of the openings 12, and the bonding layer 38 is provided in the outer region of all four sides of the opening 12. As a result, heat can be efficiently conducted from the heat sink 36 to the core layer 10. Therefore, heat dissipation can be improved.
　半導体部品４０の側面と開口１２の側面との距離Ｄ１が大きすぎると、図３（ａ）の経路５４のよる放熱板３６からコア層１０への熱抵抗が高くなる。よって、距離Ｄ１は２ｍｍ以下が好ましい。半導体部品４０を開口１２内に実装するための位置合わせを考慮して、距離Ｄ１は２５μｍ以上が好ましい。接合層３８の幅Ｄ２（すなわち放熱板３６がコア層１０に接合される領域の幅）が小さすぎると、図３（ａ）の経路５４により放熱板３６からコア層１０へ熱が伝わり難くなる。よって、幅Ｄ２は５０μｍ以上が好ましい。経路５４の放熱を大きくするためには、幅Ｄ２を大きくすることが好ましい。 If the distance D1 between the side surface of the semiconductor component 40 and the side surface of the opening 12 is too large, the thermal resistance from the heat sink 36 to the core layer 10 by the path 54 in FIG. 3A becomes high. Therefore, the distance D1 is preferably 2 mm or less. The distance D1 is preferably 25 μm or more in consideration of the alignment for mounting the semiconductor component 40 in the opening 12. If the width D2 of the bonding layer 38 (that is, the width of the region where the heat sink 36 is bonded to the core layer 10) is too small, it becomes difficult for heat to be transferred from the heat sink 36 to the core layer 10 by the path 54 in FIG. 3 (a). .. Therefore, the width D2 is preferably 50 μm or more. In order to increase the heat dissipation of the path 54, it is preferable to increase the width D2.
　図４（ｂ）に示すように、接合層３８は開口１２の３辺の外側の領域に設けられ、放熱板３６は、開口１２の３辺の外側の領域においてコア層１０と接合されている。 As shown in FIG. 4B, the bonding layer 38 is provided in the region outside the three sides of the opening 12, and the heat sink 36 is bonded to the core layer 10 in the region outside the three sides of the opening 12. ..
　図４（ｃ）に示すように、接合層３８は開口１２の対向する２辺の外側の領域に設けられ、放熱板３６は、開口１２の２辺の外側の領域においてコア層１０と接合されている。 As shown in FIG. 4C, the bonding layer 38 is provided in the outer region of the two opposite sides of the opening 12, and the heat sink 36 is bonded to the core layer 10 in the outer region of the two opposite sides of the opening 12. ing.
　図４（ｄ）に示すように、接合層３８は開口１２の１辺の外側の領域に設けられ、放熱板３６は、開口１２の１辺の外側の領域においてコア層１０と接合されている。 As shown in FIG. 4D, the bonding layer 38 is provided in the region outside one side of the opening 12, and the heat sink 36 is bonded to the core layer 10 in the region outside one side of the opening 12. ..
　図４（ａ）から図４（ｄ）のように、放熱板３６は、コア層１０の上面のうち開口１２を囲む少なくとも一部の領域に接合されている。これにより、図３（ａ）のように、半導体部品４０において発生した熱は、放熱板３６からコア層１０の伝送するため放熱性を向上できる。図３（ｂ）のように、放熱板３６に加わる矢印６０の応力が半導体部品４０に加わり難くするためには、図４（ａ）から図４（ｃ）のように、放熱板３６は、コア層１０の上面のうち開口１２の少なくとも対向する２辺の外側の領域に接合されていることが好ましい。開口の平面形状は略長方形状の場合、放熱板３６はコア層１０の上面の内開口１２の少なくとも対向する２つの長辺の外側の領域と接合されていることが好ましい。これにより、矢印６０の応力がコア層１０に分散され、半導体部品４０に加わる応力を抑制できる。 As shown in FIGS. 4A to 4D, the heat sink 36 is joined to at least a part of the upper surface of the core layer 10 surrounding the opening 12. As a result, as shown in FIG. 3A, the heat generated in the semiconductor component 40 is transmitted from the heat radiating plate 36 to the core layer 10, so that the heat radiating property can be improved. In order to make it difficult for the stress of the arrow 60 applied to the heat sink 36 to be applied to the semiconductor component 40 as shown in FIG. 3 (b), the heat sink 36 is formed as shown in FIGS. 4 (a) to 4 (c). It is preferable that the upper surface of the core layer 10 is joined to the outer regions of at least two opposite sides of the opening 12. When the planar shape of the opening is substantially rectangular, it is preferable that the heat sink 36 is joined to the outer regions of at least two opposite long sides of the inner opening 12 on the upper surface of the core layer 10. As a result, the stress of the arrow 60 is dispersed in the core layer 10, and the stress applied to the semiconductor component 40 can be suppressed.
［実施例１の変形例１］
　図５（ａ）および図５（ｂ）は、実施例１の変形例１に係る高放熱モジュール構造の断面図および平面図である。図５（ａ）は、図５（ｂ）のＡ－Ａ断面に相当する。 [Modification 1 of Example 1]
5 (a) and 5 (b) are a cross-sectional view and a plan view of the high heat dissipation module structure according to the first modification of the first embodiment. FIG. 5A corresponds to the AA cross section of FIG. 5B.
　図５（ａ）および図５（ｂ）に示すように、放熱板３６は電子部品４２および４４の上方にも配置されている。放熱板３６は電子部品４２および４４には接合されていない。接合層３８は半導体部品４０の上面および開口１２の外側のコア層１０の上面の領域に設けられ、接合層３８ａは電子部品４２を挟み半導体部品４０と反対の放熱板３６の端部におけるコア層１０の上面に設けられている。放熱板３６のその他の部分には接合層は設けられていない。その他の構成は実施例１と同じであり説明を省略する。 As shown in FIGS. 5A and 5B, the heat sink 36 is also arranged above the electronic components 42 and 44. The heat sink 36 is not joined to the electronic components 42 and 44. The bonding layer 38 is provided in the upper surface of the semiconductor component 40 and the upper surface region of the core layer 10 outside the opening 12, and the bonding layer 38a is a core layer at the end of the heat sink 36 opposite to the semiconductor component 40 with the electronic component 42 sandwiched therein. It is provided on the upper surface of 10. No bonding layer is provided on the other parts of the heat sink 36. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.
　放熱性を向上させるためには、放熱板３６を大きくすることが好ましい。そこで、放熱板３６は電子部品４２および４４の上方に設けることが好ましい。しかし、電子部品４４を接合材で放熱板３６と接続すると、電子部品４４の両電極４５を短絡させてしまう。また、放熱板３６を電子部品４２および４４に接合させると、半導体部品４０において発生した熱が電子部品４２および４４の温度を上昇させる。このため、放熱板３６は、電子部品４２の上面に接合しないことが好ましい。また、放熱板３６が放熱板３６の全体と接合されていると、熱応力が大きくなる。そこで、発熱する半導体部品４０の上面およびその近傍のコア層１０の上面に接合層３８を設け、他の電子部品４２および４４の上面および他のコア層１０の上面に接合層３８を設けないことが好ましい。 In order to improve heat dissipation, it is preferable to increase the heat sink 36. Therefore, it is preferable that the heat sink 36 is provided above the electronic components 42 and 44. However, when the electronic component 44 is connected to the heat sink 36 with a joining material, both electrodes 45 of the electronic component 44 are short-circuited. Further, when the heat sink 36 is joined to the electronic components 42 and 44, the heat generated in the semiconductor component 40 raises the temperature of the electronic components 42 and 44. Therefore, it is preferable that the heat sink 36 is not bonded to the upper surface of the electronic component 42. Further, when the heat radiating plate 36 is joined to the entire heat radiating plate 36, the thermal stress becomes large. Therefore, the bonding layer 38 should be provided on the upper surface of the semiconductor component 40 that generates heat and the upper surface of the core layer 10 in the vicinity thereof, and the bonding layer 38 should not be provided on the upper surfaces of the other electronic components 42 and 44 and the upper surface of the other core layer 10. Is preferable.
　接合層３８をコア層１０の上面の一部の領域のみに設けると、放熱板３６とコア層１０との間にクリアランスが形成され、熱応力が緩和される。しかし、放熱板３６が大きいと、放熱板３６がコア層１０の上面に対し傾いてしまう。そこで、放熱板３６の端部に接合層３８ａを設ける。これにより、放熱板３６がコア層１０の上面に対し傾くことを抑制できる。例えば、放熱板３６が電子部品４２と接合されていないときに、放熱板３６は、コア層１０の上面にうち開口１２を囲む少なくとも一部の第１領域と電子部品４２を挟み半導体部品４０と反対側の第２領域と接合されている。これにより、放熱板３６が電子部品４２と接合されていなくても、放熱板３６がコア層１０の上面に対し傾くことを抑制できる。 When the bonding layer 38 is provided only in a part of the upper surface of the core layer 10, a clearance is formed between the heat sink 36 and the core layer 10, and the thermal stress is relaxed. However, if the heat sink 36 is large, the heat sink 36 is tilted with respect to the upper surface of the core layer 10. Therefore, a bonding layer 38a is provided at the end of the heat radiating plate 36. As a result, it is possible to prevent the heat radiating plate 36 from tilting with respect to the upper surface of the core layer 10. For example, when the heat radiating plate 36 is not joined to the electronic component 42, the heat radiating plate 36 sandwiches at least a part of the first region surrounding the opening 12 on the upper surface of the core layer 10 and the electronic component 42 with the semiconductor component 40. It is joined to the second region on the opposite side. As a result, even if the heat sink 36 is not joined to the electronic component 42, it is possible to prevent the heat sink 36 from tilting with respect to the upper surface of the core layer 10.
［実施例１の変形例２］
　図６（ａ）および図６（ｂ）は、実施例１の変形例２に係る高放熱モジュール構造の断面図および平面図である。図６（ａ）は、図６（ｂ）のＡ－Ａ断面に相当する。 [Modification 2 of Example 1]
6 (a) and 6 (b) are a cross-sectional view and a plan view of the high heat dissipation module structure according to the second modification of the first embodiment. FIG. 6A corresponds to the AA cross section of FIG. 6B.
　図６（ａ）および図６（ｂ）に示すように、放熱板３６は電子部品４２および４４の上方にも配置されている。放熱板３６は電子部品４２に接合されており、電子部品４４に接合されていない。接合層３８は半導体部品４０の上面および開口１２の外側のコア層１０の上面の領域に設けられ、接合層３８ｂは電子部品４２の上面および開口１３の外側のコア層１０の上面の領域に設けられている。接合層３８と３８ｂとの間等に接合層は設けられていない。その他の構成は実施例１の変形例１と同じであり説明を省略する。 As shown in FIGS. 6 (a) and 6 (b), the heat sink 36 is also arranged above the electronic components 42 and 44. The heat sink 36 is joined to the electronic component 42, not to the electronic component 44. The bonding layer 38 is provided in the upper surface region of the semiconductor component 40 and the upper surface region of the core layer 10 outside the opening 12, and the bonding layer 38b is provided in the upper surface region of the electronic component 42 and the upper surface region of the core layer 10 outside the opening 13. Has been done. No bonding layer is provided between the bonding layers 38 and 38b. Other configurations are the same as those of the first modification of the first embodiment, and the description thereof will be omitted.
　半導体部品４０および電子部品４２の両方が発熱する場合、放熱板３６は、半導体部品４０の上面およびコア層１０の上面うち開口１２を囲む少なくとも一部の第１領域、並びに電子部品４２の上面およびコア層１０の上面うち開口１３を囲む少なくとも一部の第２領域に接合する。これにより、半導体部品４０および電子部品４２からの放熱性を向上できる。放熱板３６が放熱板３６の全体と接合されていると、熱応力が大きくなる。そこで、放熱板３６は接合層３８と３８ｂとの間の領域や電子部品４４の上面およびその近傍においてコア層１０の上面と接合されていないことが好ましい。すなわち、第１領域と第２領域との間が接続されていないことが好ましい。熱応力が問題とならない場合には、接合層３８と３８ｂとはつながっていてもよい。電子部品４２は半導体部品４０と同様のパワートランジスタ４８を含んでもよい。 When both the semiconductor component 40 and the electronic component 42 generate heat, the heat radiating plate 36 includes at least a first region of the upper surface of the semiconductor component 40 and the upper surface of the core layer 10 surrounding the opening 12, and the upper surface of the electronic component 42 and the upper surface of the electronic component 42. It is joined to at least a part of the second region surrounding the opening 13 of the upper surface of the core layer 10. Thereby, the heat dissipation from the semiconductor component 40 and the electronic component 42 can be improved. When the heat radiating plate 36 is joined to the entire heat radiating plate 36, the thermal stress becomes large. Therefore, it is preferable that the heat sink 36 is not bonded to the upper surface of the core layer 10 in the region between the bonding layers 38 and 38b or in the upper surface of the electronic component 44 or in the vicinity thereof. That is, it is preferable that the first region and the second region are not connected. If thermal stress is not a problem, the bonding layers 38 and 38b may be connected. The electronic component 42 may include a power transistor 48 similar to the semiconductor component 40.
［実施例１の変形例３］
　図７（ａ）から図７（ｃ）は、実施例１の変形例３における放熱板および接合層を示す平面図である。 [Modification 3 of Example 1]
7 (a) to 7 (c) are plan views showing the heat radiating plate and the bonding layer in the modified example 3 of the first embodiment.
　図７（ａ）に示すように、１つの開口１２内に２つの半導体部品４０ａおよび４０ｂが収納されている。１つの放熱板３６は半導体部品４０ａおよび４０ｂの上面に接合層３８を介し接合されている。放熱板３６はコア層１０の上面のうち開口１２を囲む領域と接合層３８を介し接合されている。その他の構成は実施例１と同じであり説明を省略する。 As shown in FIG. 7A, two semiconductor parts 40a and 40b are housed in one opening 12. One heat sink 36 is joined to the upper surfaces of the semiconductor parts 40a and 40b via a joining layer 38. The heat radiating plate 36 is joined to a region surrounding the opening 12 on the upper surface of the core layer 10 via a joining layer 38. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.
　図７（ｂ）に示すように、１つの開口１２内に２つの半導体部品４０ａおよび４０ｂが収納されている。１つの放熱板３６は半導体部品４０ａおよび４０ｂの上面にそれぞれ接合層３８ａおよび３８ｂを介し接合されている。接合層３８ａおよび３８ｂは半導体部品４０ａおよび４０ｂに対応し２つ設けられ、互いに分離されている。その他の構成は実施例１と同じであり説明を省略する。 As shown in FIG. 7B, two semiconductor parts 40a and 40b are housed in one opening 12. One heat sink 36 is joined to the upper surfaces of the semiconductor parts 40a and 40b via the joining layers 38a and 38b, respectively. Two bonding layers 38a and 38b are provided corresponding to the semiconductor components 40a and 40b, and are separated from each other. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.
　図７（ｃ）に示すように、１つの開口１２内に２つの半導体部品４０ａおよび４０ｂが収納されている。２つの放熱板３６ａおよび３６ｂはそれぞれ半導体部品４０ａおよび４０ｂの上面に接合層３８ａおよび３８ｂを介し接合されている。放熱板３６ａおよび３６ｂは半導体部品４０ａおよび４０ｂに対応し２つ設けられ、互いに分離されている。その他の構成は実施例１と同じであり説明を省略する。 As shown in FIG. 7C, two semiconductor parts 40a and 40b are housed in one opening 12. The two heat sinks 36a and 36b are joined to the upper surfaces of the semiconductor parts 40a and 40b via the joining layers 38a and 38b, respectively. Two heat sinks 36a and 36b are provided corresponding to the semiconductor parts 40a and 40b, and are separated from each other. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.
　実施例１の変形例３の図７（ａ）から図７（ｂ）のように、１つの開口１２内に複数の半導体部品４０ａおよび４０ｂが設けられていてもよい。放熱板３６および接合層３８は１つの開口１２に対し１つ設けられていてもよいし、半導体部品４０ａおよび４０ｂに対応し複数の放熱板３６ａおよび３６ｂ、並びに複数の接合層３８ａおよび３８ｂが設けられていてもよい。実施例１の変形例１および２の図５（ａ）から図６（ｂ）においても１つの開口１２内に複数の半導体部品４０ａおよび４０ｂが設けられていてもよい。 As shown in FIGS. 7 (a) to 7 (b) of the third modification of the first embodiment, a plurality of semiconductor parts 40a and 40b may be provided in one opening 12. One heat sink 36 and one bonding layer 38 may be provided for one opening 12, or a plurality of heat sinks 36a and 36b and a plurality of bonding layers 38a and 38b are provided corresponding to the semiconductor parts 40a and 40b. It may have been. In FIGS. 5 (a) to 6 (b) of the first and second modifications of the first embodiment, a plurality of semiconductor parts 40a and 40b may be provided in one opening 12.
　以上、本発明の実施例について詳述したが、本発明はかかる特定の実施例に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。 Although the examples of the present invention have been described in detail above, the present invention is not limited to such specific examples, and various modifications and modifications are made within the scope of the gist of the present invention described in the claims. It can be changed.
　１０　コア層
　１２、１３、１４　開口
　２０、２２、２３、２４、２８　絶縁層
　２６　ソルダーレジスト
　３２、３４、３４ａ、３４ｂ　金属層
　３５ａ、３５ｂ　配線
　３６、３６ａ、３６ｂ　放熱板
　３８、３８ａ－３８ｄ　接合層
　４０、４０ａ、４０ｂ　半導体部品
　４１、４３、４５　電極
　４２、４４　電子部品
　 10 Core layer 12, 13, 14 Opening 20, 22, 23, 24, 28 Insulation layer 26 Solder resist 32, 34, 34a, 34b Metal layer 35a, 35b Wiring 36, 36a, 36b Heat sink 38, 38a- 38d Bonding layer 40, 40a, 40b Semiconductor parts 41, 43, 45 Electrodes 42, 44 Electronic parts

Claims (10)

  1. 　第１開口を有する金属コア層と、
    　前記第１開口内に設けられた半導体部品と、
    　前記金属コア層の上面の少なくとも一部および前記半導体部品の上面に接合された放熱部材と、
    　前記金属コア層下に設けられた第１絶縁層と、
    　前記第１絶縁層の下面に設けられた第１金属層と、
    　前記第１絶縁層内に設けられ、前記金属コア層と前記第１金属層とを接続する第１配線と、
    を備える高放熱モジュール構造。     A metal core layer with a first opening and
    The semiconductor component provided in the first opening and
    A heat radiating member bonded to at least a part of the upper surface of the metal core layer and the upper surface of the semiconductor component,
    The first insulating layer provided under the metal core layer and
    A first metal layer provided on the lower surface of the first insulating layer and
    A first wiring provided in the first insulating layer and connecting the metal core layer and the first metal layer, and
    High heat dissipation module structure with.
  2. 　前記放熱部材は、前記金属コア層の上面うち前記第１開口を囲む少なくとも一部の領域に接合されている請求項１に記載の高放熱モジュール構造。 The high heat dissipation module structure according to claim 1, wherein the heat dissipation member is joined to at least a part of the upper surface of the metal core layer surrounding the first opening.
  3. 　前記第１絶縁層の下面に設けられた第２金属層と、
    　前記第１絶縁層内に設けられ、前記金属コア層と前記第２金属層とを接続する第２配線と、
    を備える請求項１または２に記載の高放熱モジュール構造。     A second metal layer provided on the lower surface of the first insulating layer and
    A second wiring provided in the first insulating layer and connecting the metal core layer and the second metal layer, and
    The high heat dissipation module structure according to claim 1 or 2.
  4. 　前記第１開口は略四角形状であり、
    　前記放熱部材は、前記金属コア層の上面のうち前記第１開口の少なくとも対向する２辺の外側の領域に接合されている請求項１から３のいずれか一項に記載の高放熱モジュール構造。     The first opening has a substantially quadrangular shape.
    The high heat dissipation module structure according to any one of claims 1 to 3, wherein the heat dissipation member is joined to an outer region of at least two opposite sides of the first opening on the upper surface of the metal core layer.
  5. 　前記金属コア層の第２開口内に設けられた電子部品を備え、
    　前記放熱部材は前記電子部品の上方に設けられていない請求項１から４のいずれか一項に記載の高放熱モジュール構造。     An electronic component provided in the second opening of the metal core layer is provided.
    The high heat dissipation module structure according to any one of claims 1 to 4, wherein the heat dissipation member is not provided above the electronic component.
  6. 　前記金属コア層の第２開口内に設けられた電子部品を備え、
    　前記放熱部材は前記電子部品の上方に設けられ、前記電子部品の上面に接合されていない請求項１から４のいずれか一項に記載の高放熱モジュール構造。     An electronic component provided in the second opening of the metal core layer is provided.
    The high heat dissipation module structure according to any one of claims 1 to 4, wherein the heat dissipation member is provided above the electronic component and is not joined to the upper surface of the electronic component.
  7. 　前記放熱部材は、前記金属コア層の上面にうち前記第１開口を囲む少なくとも一部の第１領域および前記電子部品を挟み前記半導体部品と反対側の第２領域と接合されている請求項６に記載の高放熱モジュール構造。 6. The heat radiating member is joined to an upper surface of the metal core layer with at least a part of a first region surrounding the first opening and a second region on the opposite side of the semiconductor component with the electronic component interposed therebetween. High heat dissipation module structure described in.
  8. 　前記金属コア層の第２開口内に設けられた電子部品を備え、
    　前記放熱部材は、前記金属コア層の上面うち前記第１開口を囲む少なくとも一部の第１領域および前記金属コア層の上面うち前記第２開口を囲む少なくとも一部の第２領域と、前記電子部品の上面に接合され、前記第１領域と前記第２領域との間が接続されていない請求項１から４のいずれか一項に記載の高放熱モジュール構造。     An electronic component provided in the second opening of the metal core layer is provided.
    The heat radiating member includes at least a part of the first region of the upper surface of the metal core layer surrounding the first opening, at least a part of the second region of the upper surface of the metal core layer surrounding the second opening, and the electrons. The high heat dissipation module structure according to any one of claims 1 to 4, which is joined to the upper surface of a component and is not connected between the first region and the second region.
  9. 　前記金属コア層上に設けられ、前記放熱部材を囲み、前記放熱部材の上面が露出する第２絶縁層を備える請求項１から８のいずれか一項に記載の高放熱モジュール構造。 The high heat dissipation module structure according to any one of claims 1 to 8, which is provided on the metal core layer, surrounds the heat dissipation member, and includes a second insulating layer in which the upper surface of the heat dissipation member is exposed.
  10. 　前記第１開口内に複数の前記半導体部品が設けられ、
    　前記放熱部材は前記複数の半導体部品の上面に接合されている請求項１から９のいずれか一項に記載の高放熱モジュール構造。
    　     A plurality of the semiconductor parts are provided in the first opening, and the semiconductor parts are provided.
    The high heat dissipation module structure according to any one of claims 1 to 9, wherein the heat dissipation member is joined to the upper surface of the plurality of semiconductor parts.
PCT/JP2020/014109 2020-03-27 2020-03-27 High heat-dissipation module structure WO2021192245A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012253118A (en) * 2011-06-01 2012-12-20 Denso Corp Semiconductor device
JP2017028060A (en) * 2015-07-21 2017-02-02 株式会社デンソー Electronic device
JP2018019057A (en) * 2017-01-12 2018-02-01 Tdk株式会社 Electronic circuit package
JP2019033178A (en) * 2017-08-08 2019-02-28 太陽誘電株式会社 Semiconductor module
WO2019167908A1 (en) * 2018-02-28 2019-09-06 株式会社村田製作所 High frequency module

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012253118A (en) * 2011-06-01 2012-12-20 Denso Corp Semiconductor device
JP2017028060A (en) * 2015-07-21 2017-02-02 株式会社デンソー Electronic device
JP2018019057A (en) * 2017-01-12 2018-02-01 Tdk株式会社 Electronic circuit package
JP2019033178A (en) * 2017-08-08 2019-02-28 太陽誘電株式会社 Semiconductor module
WO2019167908A1 (en) * 2018-02-28 2019-09-06 株式会社村田製作所 High frequency module

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