WO2021190385A1 - Semiconductor structure - Google Patents

Semiconductor structure Download PDF

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Publication number
WO2021190385A1
WO2021190385A1 PCT/CN2021/081445 CN2021081445W WO2021190385A1 WO 2021190385 A1 WO2021190385 A1 WO 2021190385A1 CN 2021081445 W CN2021081445 W CN 2021081445W WO 2021190385 A1 WO2021190385 A1 WO 2021190385A1
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WO
WIPO (PCT)
Prior art keywords
mechanical damage
chip
semiconductor structure
ring
guard ring
Prior art date
Application number
PCT/CN2021/081445
Other languages
French (fr)
Chinese (zh)
Inventor
刘志拯
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/430,093 priority Critical patent/US20220310462A1/en
Publication of WO2021190385A1 publication Critical patent/WO2021190385A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Definitions

  • the present invention relates to the field of semiconductors, in particular to a semiconductor structure.
  • the preparation process of the chip firstly coats the wafer, develops, etches, doping and other processes to form a die, and then performs a pin test on the die to confirm the device performance of the die, and then the qualified die Carry out slicing and packaging, and finally perform the final performance test on the packaged chip.
  • a semiconductor structure is provided.
  • a semiconductor structure is provided on the surface of a substrate of a bare chip, the bare chip includes an internal circuit of the chip, and the semiconductor structure includes:
  • the first protection ring is arranged around the internal circuit of the chip and is used to suppress mechanical damage of the die;
  • the second protection ring is arranged around the internal circuit of the chip, and is used to suppress the mechanical damage and to monitor the magnitude of the mechanical damage;
  • the second guard ring includes a plurality of first structures and a plurality of second structures, and the first structure and the second structure have different mechanical strengths and different resistivities.
  • the above-mentioned semiconductor structure is provided on the surface of the substrate of the bare chip, the bare chip includes the internal circuit of the chip, and the semiconductor structure includes: a first protection ring arranged in a ring around the internal circuit of the chip to suppress the damage of the bare chip. Mechanical damage; a second protection ring, which is arranged in a ring around the internal circuit of the chip, is used to suppress the mechanical damage and is used to monitor the size of the mechanical damage; wherein, the second protection ring includes a plurality of first structures And a plurality of second structures, the first structure and the second structure have different mechanical strengths and different resistivities.
  • the first guard ring and the second guard ring provide double protection for the internal circuit of the chip, solve the problem of insufficient resistance of a single guard ring to the deformation of the substrate, and effectively suppress the mechanical damage of the die, thereby improving the protection ring and the internal chip
  • the reliability of the circuit, and by monitoring the size of the mechanical damage, the mechanical damage of the die can be obtained in real time, so that the cutting and protection strategy of the die can be adjusted in time to improve the processing yield of the chip.
  • FIG. 1 is a schematic top view of a semiconductor structure according to an embodiment
  • Fig. 2 is a partial enlarged schematic view of the crack in the embodiment of Fig. 1;
  • FIG. 3 is a schematic top view of a semiconductor structure according to another embodiment
  • Fig. 4 is a schematic top view of a first protection ring according to an embodiment
  • Fig. 5 is a schematic top view of a second guard ring according to an embodiment
  • FIG. 6 is a schematic cross-sectional view of the second guard ring 200 in the embodiment of FIG. 5 along the A-A direction;
  • FIG. 7 is a schematic cross-sectional view of the second guard ring 200 in the embodiment of FIG. 5 along the B-B direction;
  • Fig. 8 is a schematic top view of a second protection ring provided with two openings according to an embodiment
  • FIG. 9 is a schematic cross-sectional view of a conductor structure according to an embodiment.
  • FIG. 10 is a schematic cross-sectional view of a conductor structure of another embodiment
  • FIG. 11 is a schematic cross-sectional view of a through hole of a groove structure according to an embodiment
  • Figure 12 is a schematic partial cross-sectional view of a second guard ring according to an embodiment
  • FIG. 13 is a schematic cross-sectional view of the first structure of the embodiment in FIG. 12;
  • FIG. 14 is a schematic cross-sectional view of the second structure of the embodiment in FIG. 12;
  • FIG. 15 is a flowchart of a method of manufacturing a semiconductor structure according to an embodiment
  • FIG. 16 is a sub-flow chart of step S300 in an embodiment.
  • FIG. 1 is a schematic top view of a semiconductor structure according to an embodiment. As shown in FIG. 1, the semiconductor structure is provided on the surface of the substrate of a die 300.
  • the die 300 includes an internal circuit 301 of the chip.
  • the semiconductor structure includes a first guard ring 100 and a first guard ring 100. Two protection ring 200.
  • the first guard ring 100 is arranged in a ring around the internal circuit 301 of the chip, and is used to suppress mechanical damage of the die 300.
  • the mechanical damage of the die 300 refers to cracks caused by the deformation of the substrate of the die 300.
  • the first protection ring 100 is disposed between the internal circuit 301 of the chip and the dicing lane 302.
  • the first protection ring 100 is a closed ring structure with a relatively large ring width and mechanical strength.
  • the first guard ring 100 can eliminate the internal stress of the die 300 caused by the slicing and packaging process, thereby reducing the probability of mechanical damage to the die 300; on the other hand, when the die 300 is mechanically damaged, the first guard ring
  • the greater mechanical strength of 100 can inhibit the further spread and development of mechanical damage.
  • the first guard ring 100 can also prevent the intrusion of external water molecules and oxygen molecules, thereby avoiding oxidation or corrosion of the metal lines of the internal chip circuit, and improving the reliability and reliability of the packaged chip. stability.
  • the second guard ring 200 is annularly arranged around the internal circuit 301 of the chip, and is used to suppress mechanical damage and to monitor the magnitude of the mechanical damage.
  • the size of the mechanical damage includes the length and width of the crack.
  • Figure 2 is a partial enlarged schematic diagram of the crack in the embodiment of Figure 1. As shown in Figure 2, the length of the crack refers to the dimension d1 of the crack in the X direction, and the width of the crack is Refers to the dimension d2 of the crack in the Y direction.
  • the second guard ring 200 is also provided between the internal circuit 301 of the chip and the dicing lane 302.
  • the second guard ring 200 includes a plurality of first structures and a plurality of second structures, and the first structure and the second structure have Different mechanical strength and different resistivity.
  • the high mechanical strength part of the second guard ring 200 has a stronger ability to resist internal stress and is used to suppress mechanical damage; while the mechanical damage of the second guard ring 200 causes the resistance value of the internal structure to change, the resistance value of the high resistivity part
  • the magnitude of change is larger than that of the part with low resistivity, so the part with high resistivity can more accurately reflect the size of mechanical damage, so as to realize real-time monitoring of mechanical damage.
  • the above-mentioned semiconductor structure is provided on the surface of the substrate of the die 300.
  • the die 300 includes the internal circuit 301 of the chip.
  • the semiconductor structure includes: The mechanical damage of the die 300; the second guard ring 200, which is arranged in a ring around the internal circuit 301 of the chip, is used to suppress the mechanical damage and is used to monitor the magnitude of the mechanical damage; wherein, the second The guard ring 200 includes a plurality of first structures and a plurality of second structures, and the first structures and the second structures have different mechanical strengths and different resistivities.
  • the first guard ring 100 and the second guard ring 200 provide double protection for the internal circuit 301 of the chip, solve the problem of insufficient resistance of a single guard ring to the deformation of the substrate, and effectively suppress the mechanical damage of the die 300, thereby improving protection
  • the reliability of the ring and the internal circuit 301 of the chip, and by monitoring the size of the mechanical damage, the mechanical damage of the die 300 can be obtained in real time, so that the cutting and protection strategy of the die 300 can be adjusted in time to improve the processing yield of the chip.
  • the projections of the first guard ring 100 and the second guard ring 200 on the substrate do not overlap with each other.
  • the first protection ring 100 is disposed between the second protection ring 200 and the dicing lane 302
  • the second protection ring 200 is disposed between the internal circuit 301 of the chip and the first protection ring 100.
  • a schematic top view of the semiconductor structure of another embodiment is shown in FIG. 3, the first guard ring 100 is provided between the internal circuit 301 of the chip and the second guard ring 200, and the second guard ring 200 is provided between the first guard ring 100 and the cutting Between Road 302.
  • the two embodiments of Fig. 1 and Fig. 3 can both achieve the purpose of suppressing mechanical damage and monitoring the magnitude of mechanical damage.
  • the first protection ring 100 includes two sub-protection rings 110.
  • the guard ring 110 is used together to suppress mechanical damage.
  • the ring widths of the two sub-protection rings 110 can be the same, for example, the ring widths of the two sub-protection rings 110 are both 2um; the ring widths of the two sub-protection rings 110 can also be different, for example, the ring of the outer sub-protection ring 110 The width is 2.5um, and the ring width of the sub-protection ring 110 located on the inner side is 1.5um.
  • the first protection ring 100 may also include a plurality of sub-protection rings 110.
  • the size of the die 300 is larger, for example, 100 mm 2 , the die 300 is more prone to mechanical damage, so three sub-protection rings 110 may be provided. , So as to better protect the internal chip circuit; when the size of the die 300 is small, for example, 10mm 2 , the die 300 is not prone to mechanical damage, so only two sub-protection rings 110 can be provided, thereby reducing the first protection The area occupied by the ring 100 on the surface of the substrate.
  • the first guard ring 100 is arranged in contact with the surface of the active area of the substrate, and the active area has an N-type or a P-type.
  • FIG. 5 is a schematic top view of the second protection ring 200 of an embodiment
  • FIG. 6 is a schematic cross-sectional view of the second protection ring 200 of the embodiment of FIG. 5 along the AA direction
  • FIG. 7 is a schematic view of the second protection ring 200 of the embodiment of FIG.
  • the cross-sectional schematic diagram in the BB direction is shown in FIGS. 5 to 7.
  • the projections of the first structure 210 and the second structure 220 on the substrate do not overlap, and the first structure 210 and the second structure 220 are The extension path of the second protection ring 200 is spaced apart from each other.
  • the rectangular path drawn by the dashed line in FIG. 5 is the extension path of the second protection ring 200.
  • the first structure 210 and the second structure 220 are spaced apart from each other.
  • the second structure 220, and adjacent to each second structure 220 is the first structure 210.
  • This embodiment is based on the first structure 210 and the second structure 220 arranged at intervals, which can protect the die 300 uniformly in all directions, thereby preventing the die 300 from mechanical damage due to excessive stress in a certain direction. Damage; it is possible to obtain resistance changes in various directions at the same time to monitor mechanical damage in different directions, so as to flexibly monitor and adjust the cutting and protection strategies of the die 300 accordingly.
  • the cross-sectional schematic diagrams in the following embodiments are all cross-sectional schematic diagrams along the B-B direction, and will not be repeated in the following embodiments.
  • the mechanical strength of the first structure 210 is greater than the mechanical strength of the second structure 220, and the first structure 210 is used to suppress mechanical damage. It can be understood that the mechanical strength of the structure is determined by the characteristics of the material itself and the composition characteristics of the structure. Therefore, the first structure 210 can be formed by using a material with a higher shear resistance coefficient and a higher tensile force coefficient to improve the first structure. The mechanical strength of the structure 210; the first structure 210 with a larger cross-sectional area can also be formed to improve the mechanical strength of the first structure 210.
  • the resistivity of the second structure 220 is greater than the resistivity of the first structure 210, and the resistivity of the second structure 220 matches the magnitude of the mechanical damage. It can be understood that the resistivity of the structure is determined by the characteristics of the material itself and the composition characteristics of the structure. Therefore, the second structure 220 can be formed with a material with a higher resistivity to increase the resistivity of the second structure 220; it can also be formed The second structure 220 with a smaller cross-sectional area or a longer length improves the resistivity of the second structure 220.
  • the matching of the resistance value of the second structure 220 with the size of the mechanical damage means that the resistance value of the second structure 220 has a correlation with the size of the mechanical damage.
  • the correlation may be a positive correlation, that is, the larger the width and/or the length of the crack, the greater the resistance value of the second structure 220; the correlation may also be a negative correlation, that is, the width of the crack and the /Or the greater the length of the crack, the smaller the resistance value of the second structure 220.
  • the second protection ring 200 is a non-closed ring
  • the second protection ring 200 is provided with an opening 201
  • the opening 201 is provided with a lead-out terminal 202
  • the modules are connected to obtain the resistance information of the second protection ring 200.
  • the resistance value information can be the resistance value, such as 5 ⁇ , 10 ⁇ , etc.; it can also be the resistance change value, that is, the difference between the resistance value at the current test moment and the resistance value at the previous test moment, such as 0.5 ⁇ , 0.1 ⁇ It can also be the rate of resistance change, that is, the ratio of the difference between the resistance value at the current test moment and the resistance value at the previous test moment to the test time interval, such as 0.005 ⁇ /ms, 0.01 ⁇ /ms, etc.
  • the resistance change rate has a sudden change, it indicates that the size of the mechanical damage has undergone a sudden change, so that the change of the mechanical damage can be obtained more accurately and quickly.
  • the monitoring module has a monitoring function and a warning function.
  • the monitoring function is used to obtain the resistance value information of the second protection ring 200 in real time
  • the warning function is used to send a warning signal according to preset warning conditions and resistance value information.
  • the preset warning condition is that the real-time resistance value exceeds the resistance threshold. When the real-time resistance value is less than the resistance threshold, no warning signal will be sent; when the real-time resistance value is not less than the resistance threshold, a warning signal will be sent out to remind the operator and slicer.
  • the equipment or packaging equipment adjusts the die cutting and protection strategy.
  • the monitoring module is an external resistance test device.
  • the test probe of the resistance test device is connected to the lead terminal 202 to obtain the second protection ring. 200 resistance value information.
  • the external resistance test equipment can be compatible with a larger data storage space, and store resistance information within a longer time range in the data storage space, so it can provide more reference data for slicing and packaging process control of other bare chips.
  • the monitoring module is a monitoring circuit provided on the surface of the substrate.
  • the monitoring circuit can be integrated in the internal circuit 301 of the chip, or can be independently provided outside the internal circuit 301 of the chip.
  • the monitoring circuit provided on the surface of the substrate is not limited by the test location and the external test equipment, so the resistance information of the second guard ring 200 can be monitored more flexibly.
  • the second protection ring 200 is provided with an opening 201, and two lead terminals 202 are provided at the opening 201.
  • the two lead-out terminals 202 can both be connected to the first structure 210; or both can be connected to the second structure 220; it is also possible that one lead-out terminal 202 is connected to the first structure 210, and the other lead-out terminal 202 is connected to the first structure 210.
  • the second structure 220 It should be noted that the "connection" connected to the first structure 210 or the second structure 220 can either use one of the functional layers in the first structure 210 or the second structure 220 as the lead terminal 202, or it can be an additional lead.
  • the terminal 202 is connected to the first structure 210 or the second structure 220 through a metal wire.
  • FIG. 8 is a schematic top view of a second protection ring 200 provided with two openings 201 according to an embodiment.
  • the second protection ring 200 is provided with two openings 201, and each opening 201 is provided Two lead-out terminals 202, the second protection ring 200 is divided into two protection sections by two openings 201, each pair of lead-out terminals 202 is used to obtain the resistance value information of the corresponding protection section.
  • two pairs of lead-out terminals With the structure of 202 and two protection sections, the position and direction of cracks can be obtained more accurately.
  • the second protection ring 200 may also be provided with a plurality of openings 201, and each opening 201 is provided with two lead terminals 202, and the second protection ring 200 is divided into a plurality of protections by the plurality of openings 201. part. Further, multiple protection sections can be provided in areas prone to mechanical damage, such as the corner areas of the die 300, and only one protection section can be provided in areas where mechanical damage is not prone to occur, such as the straight edge of the die 300, so as to prevent The size of mechanical damage is monitored more accurately.
  • the first structure 210 and the second structure 220 are both stacked structures and include the same conductor structure.
  • the same conductor structure refers to a conductor structure in which the arrangement order and materials of each functional layer in the device are the same, but the same conductor structure does not limit the specific size of the first structure 210 and the second structure 220, that is, the first structure 210 and the second structure 220 The size of the conductor structure in the second structure 220 may be different.
  • the conductor structure includes: at least two metal layers; and a via layer, which is arranged between two adjacent metal layers and is used to connect the adjacent metal layers. Specifically, two adjacent metal layers at least partially overlap in the vertical direction, and a through hole layer is provided in the overlapped portion to conduct the adjacent metal layers.
  • FIG. 9 is a schematic cross-sectional view of a conductor structure of an embodiment. As shown in FIG. 9, the conductor structure includes two metal layers, namely, a top metal layer 233 and a bottom metal layer 231, between the top metal layer 233 and the bottom metal layer 231 A via layer 234 for conducting the metal layer is provided.
  • FIG. 10 is a schematic cross-sectional view of a conductor structure of another embodiment. As shown in FIG.
  • the conductor structure includes three metal layers, which are a top metal layer 233, a middle metal layer 232, and a bottom metal layer 231, and the top metal layer 233 and A via layer 234 for conducting the metal layer is provided between the middle metal layer 232, and a via layer 234 for conducting the metal layer is also provided between the middle metal layer 232 and the bottom metal layer 231.
  • the conductor structure may include at least four metal layers, which are the top metal layer 233, at least two intermediate metal layers 232, and the top metal layer 233, respectively.
  • a conductive structure is provided between two adjacent metal layers. Via layer 234 of the metal layer.
  • the dielectric material and at least one through hole 236 provided in the dielectric material wherein the through hole 236 penetrates the dielectric material in a vertical direction for conducting two adjacent conductive layers;
  • the dielectric material is used to maintain the structural stability of the through hole 236 to improve the mechanical strength of the first structure 210 and the second structure 220.
  • the dielectric material can be silicon oxide, silicon nitride, or silicon oxynitride, and is formed by atomic layer deposition (Atomic Layer Deposition) or chemical vapor deposition (Chemical Vapor Deposition), so as to ensure that the thickness of the through hole 236 is accurate. Performance and film flatness.
  • the through hole 236 may be a groove-shaped structure.
  • 11 is a schematic cross-sectional view of the through hole 236 of the groove structure of this embodiment.
  • the conductive structure of this embodiment includes two conductive layers.
  • the through hole 236 of the groove structure refers to the conductive
  • the surface of the layer 235 is provided with a groove of a predetermined depth, and a through hole 236 formed of a conductive material is also filled in the groove to be electrically connected to the underlying metal layer 231.
  • the conductive layer 235 may be an active region or polysilicon.
  • the through hole 236 of the groove structure can ensure a larger contact area between the through hole 236 and the conductive layer 235, thereby reducing the contact resistance.
  • FIG. 12 is a schematic partial cross-sectional view of the second guard ring 200 according to an embodiment.
  • FIG. 12 shows only two first structures 210 and one second structure 220, and FIG. 12 is used to show the first structure 210 and the second structure 220 It should be noted that the other unshown connection relationships of the first structure 210 and the second structure 220 are the same as the connection relationship shown in FIG. 12.
  • the first structure 210 includes: a first conductive structure; a substrate contact hole 215 for connecting the first underlying metal layer 211 and the liner The active area in the bottom; the first conductor contact hole 216 is used to connect the first bottom metal layer 211 and the conductor layer 203.
  • the first conductive structure includes a first bottom metal layer 211, a first middle metal layer 212, and a first top metal layer 213 stacked in sequence, and a first via layer 214 disposed between two adjacent metal layers.
  • the first top metal layer 211 and the first intermediate metal layer 212 may be one of aluminum and copper
  • the first bottom metal layer 211 may be one of tungsten, aluminum, and copper
  • the conductive layer 203 may be polysilicon.
  • the second structure 220 includes: a second conductive structure; a second conductor contact hole 225 for connecting the second underlying metal layer 221 and Conductor layer 203; the second conductive structure includes a second bottom metal layer 221, a second middle metal layer 222, and a second top metal layer 223 that are stacked in sequence, and a second pass provided between two adjacent metal layers Hole layer 224; the second conductive structure is the same as the first conductive structure, and the second top metal layer 223 is connected to the first top metal layer 213.
  • the second protection ring 200 with high mechanical strength and accurate mechanical damage monitoring is realized.
  • the two first top metal layers 213 can be used as the lead-out terminals 202 connected to the monitoring module, and the two first bottom metal layers 211 can also be used as the lead-out terminals 202 connected to the monitoring module.
  • This embodiment does not The positions of the lead-out terminals 202 in the first structure 210 and the second structure 220 are specifically defined. The above-mentioned arrangement of the lead-out terminals 202 can accurately monitor the mechanical damage of the die 300.
  • the width d3 of the cross-section longitudinally cut along the extension path of the second protection ring 200 of the first structure 210 may be 5um to 50um, and the second structure 220 may extend along the second protection ring.
  • the width d4 of the cross section longitudinally cut by the extension path of 200 may be 0.5 um to 1 um.
  • FIG. 15 is a flowchart of a manufacturing method of a semiconductor structure according to an embodiment. As shown in FIG. 15, the manufacturing method includes steps S100 to S300.
  • S100 Provide a substrate, and an isolation structure and an active area have been formed in the substrate.
  • S200 forming a substrate contact hole 215, a first conductor contact hole 216, and a second conductor contact hole 225 on the surface of the substrate, wherein the top of the substrate contact hole 215 and the first conductor contact hole 216 are flush.
  • a first conductive structure is formed on the surface of the substrate contact hole 215 and the first conductor contact hole 216, and a second conductive structure is formed on the surface of the second conductor contact hole 225.
  • both the first conductive structure and the second conductive structure include two metal layers, that is, the first conductive structure includes a first bottom metal layer 211 and a first top metal layer 213, and the second conductive structure includes a second bottom metal layer.
  • the metal layer 221 and the second top metal layer 223 FIG. 16 is a sub-flow chart of step S300 in this embodiment. As shown in FIG. 16, step S300 includes steps S310 to S330.
  • a first top metal layer 213 is formed on the surface of the first via layer 214, and a second top metal layer 223 is formed on the surface of the second via layer 224, wherein the first top metal layer 213 and the second top metal layer 223 is connected.
  • FIGS. 15 to 16 are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless specifically stated in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least part of the steps in FIGS. 15 to 16 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. These sub-steps or The execution order of the stages is not necessarily carried out sequentially, but may be executed alternately or alternately with other steps or at least a part of other steps or sub-steps or stages.

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Abstract

Provided is a semiconductor structure, which is arranged on the surface of a substrate of a die. The die comprises a chip internal circuit. The semiconductor structure comprises: a first protection ring, which is arranged surrounding the chip internal circuit and is used for inhibiting mechanical damage to the die; and a second protection ring, which is arranged surrounding the chip internal circuit and is used for inhibiting mechanical damage and for monitoring the magnitude of mechanical damage. The second protection ring comprises a plurality of first structures and a plurality of second structures, wherein the first structures and the second structures have different mechanical strengths and different resistivities.

Description

半导体结构Semiconductor structure
相关申请的交叉引用Cross-references to related applications
本申请要求于2020年3月25日提交中国专利局、申请号为2020102164393、发明名称为“半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims the priority of a Chinese patent application filed with the Chinese Patent Office with the application number 2020102164393 and the invention title "Semiconductor Structure" on March 25, 2020, the entire content of which is incorporated into this application by reference.
技术领域Technical field
本发明涉及半导体领域，特别是涉及一种半导体结构。The present invention relates to the field of semiconductors, in particular to a semiconductor structure.
背景技术Background technique
随着半导体技术的不断发展，人们对芯片的制备工艺的要求也在不断提高。目前，芯片的制备工艺先对晶圆进行涂膜、显影、蚀刻、掺杂等工艺制程形成裸片，再对裸片进行针测以确认裸片的器件性能，之后对针测合格的裸片进行切片和封装，最后再对封装后的芯片进行最终的性能测试。With the continuous development of semiconductor technology, people's requirements for chip preparation technology are also constantly increasing. At present, the preparation process of the chip firstly coats the wafer, develops, etches, doping and other processes to form a die, and then performs a pin test on the die to confirm the device performance of the die, and then the qualified die Carry out slicing and packaging, and finally perform the final performance test on the packaged chip.
但是，在对晶圆进行切割和封装时，容易由于切片刀的切割压力过大、封装压力过大等原因导致裸片发生机械损伤。而且，当裸片发生机械损伤后，当机械损伤较为严重时，芯片内部电路的结构会发生损坏，导致器件的部分功能甚至全部功能失效；当机械损伤较小时，另一方面水分子和氧分子会从机械损伤处进入裸片的芯片内部电路，从而导致芯片内部电路中的金属导线氧化或腐蚀，进而致使芯片内部电路失效。However, when cutting and packaging the wafer, it is easy to cause mechanical damage to the die due to excessive cutting pressure of the slicing knife and excessive packaging pressure. Moreover, when the die is mechanically damaged, when the mechanical damage is severe, the internal circuit structure of the chip will be damaged, causing some or even all functions of the device to fail; when the mechanical damage is small, on the other hand, water molecules and oxygen molecules It will enter the chip's internal circuit of the die from the mechanical damage, which will cause the metal wires in the chip's internal circuit to oxidize or corrode, thereby causing the internal circuit of the chip to fail.
发明内容Summary of the invention
根据各个实施例，提供一种半导体结构。According to various embodiments, a semiconductor structure is provided.
一种半导体结构，设于裸片的衬底表面，所述裸片包括芯片内部电路，所述半导体结构包括：A semiconductor structure is provided on the surface of a substrate of a bare chip, the bare chip includes an internal circuit of the chip, and the semiconductor structure includes:
第一保护环，围绕所述芯片内部电路设置，用于抑制所述裸片的机械损伤；The first protection ring is arranged around the internal circuit of the chip and is used to suppress mechanical damage of the die;
第二保护环，围绕所述芯片内部电路设置，用于抑制所述机械损伤，且用于监测所述机械损伤的大小；The second protection ring is arranged around the internal circuit of the chip, and is used to suppress the mechanical damage and to monitor the magnitude of the mechanical damage;
其中，所述第二保护环包括多个第一结构和多个第二结构，所述第一结构和所述第二结构具有不同的机械强度和不同的电阻率。Wherein, the second guard ring includes a plurality of first structures and a plurality of second structures, and the first structure and the second structure have different mechanical strengths and different resistivities.
上述半导体结构，设于裸片的衬底表面，所述裸片包括芯片内部电路，所述半导体结构包括：第一保护环，围绕所述芯片内部电路环形设置，用于抑制所述裸片的机械损伤；第二保护环，围绕所述芯片内部电路环形设置，用于抑制所述机械损伤，且用于监测所述机械损伤的大小；其中，所述第二保护环包括多个第一结构和多个第二结构，所述第一结构和所述第二结构具有不同的机械强度和不同的电阻率。第一保护环和第二保护环为芯片内部电路提供了双重保护，解决了单一保护环对衬底形变抵抗力不足的问题，有效抑制了裸片的机械损伤，从而提高了保护环和芯片内部电路的可靠性，而且通过监测机械损伤的大小，实时获取裸片的机械损伤情况，从而及时调整裸片的切割和保护策略，以提高芯片的加工良率。The above-mentioned semiconductor structure is provided on the surface of the substrate of the bare chip, the bare chip includes the internal circuit of the chip, and the semiconductor structure includes: a first protection ring arranged in a ring around the internal circuit of the chip to suppress the damage of the bare chip. Mechanical damage; a second protection ring, which is arranged in a ring around the internal circuit of the chip, is used to suppress the mechanical damage and is used to monitor the size of the mechanical damage; wherein, the second protection ring includes a plurality of first structures And a plurality of second structures, the first structure and the second structure have different mechanical strengths and different resistivities. The first guard ring and the second guard ring provide double protection for the internal circuit of the chip, solve the problem of insufficient resistance of a single guard ring to the deformation of the substrate, and effectively suppress the mechanical damage of the die, thereby improving the protection ring and the internal chip The reliability of the circuit, and by monitoring the size of the mechanical damage, the mechanical damage of the die can be obtained in real time, so that the cutting and protection strategy of the die can be adjusted in time to improve the processing yield of the chip.
附图说明Description of the drawings
为了更好地描述和说明本申请的实施例，可参考一幅或多幅附图，但用于描述附图的附加细节或示例不应当被认为是对本申请的发明创造、目前所 描述的实施例或优选方式中任何一者的范围的限制。In order to better describe and illustrate the embodiments of the present application, one or more drawings may be referred to, but the additional details or examples used to describe the drawings should not be considered as the invention and the implementation of the present description of the present application. The scope of any one of the examples or preferred modes is limited.
图1为一实施例的半导体结构的俯视示意图；FIG. 1 is a schematic top view of a semiconductor structure according to an embodiment;
图2为图1实施例的裂纹处的局部放大示意图；Fig. 2 is a partial enlarged schematic view of the crack in the embodiment of Fig. 1;
图3为另一实施例的半导体结构的俯视示意图；3 is a schematic top view of a semiconductor structure according to another embodiment;
图4为一实施例的第一保护环的俯视示意图；Fig. 4 is a schematic top view of a first protection ring according to an embodiment;
图5为一实施例的第二保护环的俯视示意图；Fig. 5 is a schematic top view of a second guard ring according to an embodiment;
图6为图5实施例的第二保护环200沿A-A方向的截面示意图；6 is a schematic cross-sectional view of the second guard ring 200 in the embodiment of FIG. 5 along the A-A direction;
图7为图5实施例的第二保护环200沿B-B方向的截面示意图；FIG. 7 is a schematic cross-sectional view of the second guard ring 200 in the embodiment of FIG. 5 along the B-B direction;
图8为一实施例的设有两个开口的第二保护环的俯视示意图；Fig. 8 is a schematic top view of a second protection ring provided with two openings according to an embodiment;
图9为一实施例的导体结构的截面示意图；FIG. 9 is a schematic cross-sectional view of a conductor structure according to an embodiment;
图10为另一实施例的导体结构的截面示意图；10 is a schematic cross-sectional view of a conductor structure of another embodiment;
图11为一实施例的槽型结构的通孔的截面示意图；11 is a schematic cross-sectional view of a through hole of a groove structure according to an embodiment;
图12为一实施例的第二保护环的部分截面示意图；Figure 12 is a schematic partial cross-sectional view of a second guard ring according to an embodiment;
图13为图12实施例的第一结构的截面示意图；13 is a schematic cross-sectional view of the first structure of the embodiment in FIG. 12;
图14为图12实施例的第二结构的截面示意图；14 is a schematic cross-sectional view of the second structure of the embodiment in FIG. 12;
图15为一实施例的半导体结构的制备方法的流程图；FIG. 15 is a flowchart of a method of manufacturing a semiconductor structure according to an embodiment;
图16为一实施例的步骤S300的子流程图。FIG. 16 is a sub-flow chart of step S300 in an embodiment.
具体实施方式Detailed ways
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiment of the present invention is shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The term "and/or" as used herein includes any and all combinations of one or more related listed items.
在本发明的描述中，需要理解的是，术语“上”、“下”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. are based on the figures shown in the drawings. The method or positional relationship is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the pointed device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention .
图1为一实施例的半导体结构的俯视示意图，如图1所示，半导体结构设于裸片300的衬底表面，裸片300包括芯片内部电路301，半导体结构包括第一保护环100和第二保护环200。1 is a schematic top view of a semiconductor structure according to an embodiment. As shown in FIG. 1, the semiconductor structure is provided on the surface of the substrate of a die 300. The die 300 includes an internal circuit 301 of the chip. The semiconductor structure includes a first guard ring 100 and a first guard ring 100. Two protection ring 200.
第一保护环100，围绕芯片内部电路301环形设置，用于抑制裸片300的机械损伤。The first guard ring 100 is arranged in a ring around the internal circuit 301 of the chip, and is used to suppress mechanical damage of the die 300.
裸片300的机械损伤是指由裸片300衬底的形变引发的裂纹，裸片300所处环境的温、湿度变化以及切片和封装工艺均有导致该机械损伤发生的风险。The mechanical damage of the die 300 refers to cracks caused by the deformation of the substrate of the die 300. The temperature and humidity changes of the environment where the die 300 is located, as well as the slicing and packaging processes all have the risk of causing the mechanical damage.
具体地，第一保护环100设于芯片内部电路301和切割道302之间，第一保护环100为闭合环形结构，且具有较大的环宽和机械强度。第一保护环100一方面可以消除切片和封装工艺导致的裸片300的内应力，从而降低裸片300发生机械损伤的概率；另一方面,当裸片300发生机械损伤时，第一保护环100所具有的较大的机械强度可以抑制机械损伤的进一步扩散和发展。 而且，在裸片300进行封装之后，第一保护环100还可以防止外部的水分子和氧分子侵入，从而避免了内部芯片电路的金属线路发生氧化或腐蚀现象，提高了封装芯片的可靠性和稳定性。Specifically, the first protection ring 100 is disposed between the internal circuit 301 of the chip and the dicing lane 302. The first protection ring 100 is a closed ring structure with a relatively large ring width and mechanical strength. On the one hand, the first guard ring 100 can eliminate the internal stress of the die 300 caused by the slicing and packaging process, thereby reducing the probability of mechanical damage to the die 300; on the other hand, when the die 300 is mechanically damaged, the first guard ring The greater mechanical strength of 100 can inhibit the further spread and development of mechanical damage. Moreover, after the bare chip 300 is packaged, the first guard ring 100 can also prevent the intrusion of external water molecules and oxygen molecules, thereby avoiding oxidation or corrosion of the metal lines of the internal chip circuit, and improving the reliability and reliability of the packaged chip. stability.
第二保护环200，围绕芯片内部电路301环形设置，用于抑制机械损伤，且用于监测机械损伤的大小。The second guard ring 200 is annularly arranged around the internal circuit 301 of the chip, and is used to suppress mechanical damage and to monitor the magnitude of the mechanical damage.
机械损伤的大小包括裂纹的长度和宽度，图2为图1实施例的裂纹处的局部放大示意图，如图2所示，裂纹的长度是指裂纹在X方向上的尺寸d1，裂纹的宽度是指裂纹在Y方向上的尺寸d2。The size of the mechanical damage includes the length and width of the crack. Figure 2 is a partial enlarged schematic diagram of the crack in the embodiment of Figure 1. As shown in Figure 2, the length of the crack refers to the dimension d1 of the crack in the X direction, and the width of the crack is Refers to the dimension d2 of the crack in the Y direction.
具体地，第二保护环200也设于芯片内部电路301和切割道302之间，其中，第二保护环200包括多个第一结构和多个第二结构，第一结构和第二结构具有不同的机械强度和不同的电阻率。第二保护环200中高机械强度的部分抵抗内应力的能力较强，用于抑制机械损伤；而第二保护环200的机械损伤导致内部结构的阻值变化时，高电阻率的部分的阻值变化幅度比低电阻率的部分的阻值变化幅度大，因此高电阻率的部分可以更加准确地反映机械损伤的大小，从而实现对机械损伤的实时监测。Specifically, the second guard ring 200 is also provided between the internal circuit 301 of the chip and the dicing lane 302. The second guard ring 200 includes a plurality of first structures and a plurality of second structures, and the first structure and the second structure have Different mechanical strength and different resistivity. The high mechanical strength part of the second guard ring 200 has a stronger ability to resist internal stress and is used to suppress mechanical damage; while the mechanical damage of the second guard ring 200 causes the resistance value of the internal structure to change, the resistance value of the high resistivity part The magnitude of change is larger than that of the part with low resistivity, so the part with high resistivity can more accurately reflect the size of mechanical damage, so as to realize real-time monitoring of mechanical damage.
上述半导体结构，设于裸片300的衬底表面，所述裸片300包括芯片内部电路301，所述半导体结构包括：第一保护环100，围绕所述芯片内部电路301环形设置，用于抑制所述裸片300的机械损伤；第二保护环200，围绕所述芯片内部电路301环形设置，用于抑制所述机械损伤，且用于监测所述机械损伤的大小；其中，所述第二保护环200包括多个第一结构和多个第二结构，所述第一结构和所述第二结构具有不同的机械强度和不同的电阻率。第一保护环100和第二保护环200为芯片内部电路301提供了双重保护，解决了单一保护环对衬底形变抵抗力不足的问题，有效抑制了裸片300的机械损 伤，从而提高了保护环和芯片内部电路301的可靠性，而且通过监测机械损伤的大小，可以实时获取裸片300的机械损伤情况，从而及时调整裸片300的切割和保护策略，以提高芯片的加工良率。The above-mentioned semiconductor structure is provided on the surface of the substrate of the die 300. The die 300 includes the internal circuit 301 of the chip. The semiconductor structure includes: The mechanical damage of the die 300; the second guard ring 200, which is arranged in a ring around the internal circuit 301 of the chip, is used to suppress the mechanical damage and is used to monitor the magnitude of the mechanical damage; wherein, the second The guard ring 200 includes a plurality of first structures and a plurality of second structures, and the first structures and the second structures have different mechanical strengths and different resistivities. The first guard ring 100 and the second guard ring 200 provide double protection for the internal circuit 301 of the chip, solve the problem of insufficient resistance of a single guard ring to the deformation of the substrate, and effectively suppress the mechanical damage of the die 300, thereby improving protection The reliability of the ring and the internal circuit 301 of the chip, and by monitoring the size of the mechanical damage, the mechanical damage of the die 300 can be obtained in real time, so that the cutting and protection strategy of the die 300 can be adjusted in time to improve the processing yield of the chip.
需要说明的是，第一保护环100和第二保护环200在衬底上的投影没有互相重叠的部分。如图1所示，第一保护环100设于第二保护环200与切割道302之间，第二保护环200设于芯片内部电路301与第一保护环100之间。另一实施例的半导体结构的俯视示意图如图3所示，第一保护环100设于芯片内部电路301与第二保护环200之间，第二保护环200设于第一保护环100与切割道302之间。图1和图3的两个实施例均能实现抑制机械损伤，并监测机械损伤的大小的目的。It should be noted that the projections of the first guard ring 100 and the second guard ring 200 on the substrate do not overlap with each other. As shown in FIG. 1, the first protection ring 100 is disposed between the second protection ring 200 and the dicing lane 302, and the second protection ring 200 is disposed between the internal circuit 301 of the chip and the first protection ring 100. A schematic top view of the semiconductor structure of another embodiment is shown in FIG. 3, the first guard ring 100 is provided between the internal circuit 301 of the chip and the second guard ring 200, and the second guard ring 200 is provided between the first guard ring 100 and the cutting Between Road 302. The two embodiments of Fig. 1 and Fig. 3 can both achieve the purpose of suppressing mechanical damage and monitoring the magnitude of mechanical damage.
图4为一实施例的第一保护环100的俯视示意图，如图4所示，第一保护环100包括两个子保护环110，两个子保护环110在径向上依次环绕且间隔设置，两个子保护环110共同用于抑制机械损伤。其中，两个子保护环110的环宽可以相同，例如，两个子保护环110的环宽均为2um；两个子保护环110的环宽也可以不同，例如，位于外侧的子保护环110的环宽为2.5um，位于内侧的子保护环110的环宽为1.5um。4 is a schematic top view of the first protection ring 100 according to an embodiment. As shown in FIG. 4, the first protection ring 100 includes two sub-protection rings 110. The guard ring 110 is used together to suppress mechanical damage. Wherein, the ring widths of the two sub-protection rings 110 can be the same, for example, the ring widths of the two sub-protection rings 110 are both 2um; the ring widths of the two sub-protection rings 110 can also be different, for example, the ring of the outer sub-protection ring 110 The width is 2.5um, and the ring width of the sub-protection ring 110 located on the inner side is 1.5um.
进一步地，第一保护环100还可以包括多个子保护环110，具体地，当裸片300尺寸较大例如为100mm 2时，裸片300更容易发生机械损伤，则可以设置三个子保护环110，从而对内部芯片电路进行更好的保护；当裸片300尺寸较小例如为10mm 2时，裸片300不容易发生机械损伤，则可以只设置两个子保护环110，从而减小第一保护环100在衬底表面的占用面积。 Further, the first protection ring 100 may also include a plurality of sub-protection rings 110. Specifically, when the size of the die 300 is larger, for example, 100 mm 2 , the die 300 is more prone to mechanical damage, so three sub-protection rings 110 may be provided. , So as to better protect the internal chip circuit; when the size of the die 300 is small, for example, 10mm 2 , the die 300 is not prone to mechanical damage, so only two sub-protection rings 110 can be provided, thereby reducing the first protection The area occupied by the ring 100 on the surface of the substrate.
在一实施例中，第一保护环100与衬底的有源区表面接触设置，有源区具有N型或P型。In an embodiment, the first guard ring 100 is arranged in contact with the surface of the active area of the substrate, and the active area has an N-type or a P-type.
图5为一实施例的第二保护环200的俯视示意图，图6为图5实施例的第二保护环200沿A-A方向的截面示意图，图7为图5实施例的第二保护环200沿B-B方向的截面示意图，如图5至图7所示，在本实施例中，第一结构210和第二结构220在衬底上的投影不重叠，且第一结构210和第二结构220在第二保护环200的延伸路径上互相间隔设置。5 is a schematic top view of the second protection ring 200 of an embodiment, FIG. 6 is a schematic cross-sectional view of the second protection ring 200 of the embodiment of FIG. 5 along the AA direction, and FIG. 7 is a schematic view of the second protection ring 200 of the embodiment of FIG. The cross-sectional schematic diagram in the BB direction is shown in FIGS. 5 to 7. In this embodiment, the projections of the first structure 210 and the second structure 220 on the substrate do not overlap, and the first structure 210 and the second structure 220 are The extension path of the second protection ring 200 is spaced apart from each other.
具体地，图5中虚线绘制的矩形路径即为第二保护环200的延伸路径，第一结构210和第二结构220互相间隔设置是指，与每个第一结构210相邻设置的均为第二结构220，且与每个第二结构220相邻设置的均为第一结构210。本实施例基于间隔设置的第一结构210和第二结构220，既可以对裸片300在各个方向上进行均匀的保护，从而防止裸片300由于在某一个方向上的应力过大导致的机械损伤；又可以同时获取各个方向上的电阻变化以监测不同方向上的机械损伤，从而灵活地监测并相应调整裸片300的切割和保护策略。需要说明的是，以下实施例中的截面示意图均为沿B-B方向的截面示意图，在以下实施例中将不再进行赘述。Specifically, the rectangular path drawn by the dashed line in FIG. 5 is the extension path of the second protection ring 200. The first structure 210 and the second structure 220 are spaced apart from each other. The second structure 220, and adjacent to each second structure 220 is the first structure 210. This embodiment is based on the first structure 210 and the second structure 220 arranged at intervals, which can protect the die 300 uniformly in all directions, thereby preventing the die 300 from mechanical damage due to excessive stress in a certain direction. Damage; it is possible to obtain resistance changes in various directions at the same time to monitor mechanical damage in different directions, so as to flexibly monitor and adjust the cutting and protection strategies of the die 300 accordingly. It should be noted that the cross-sectional schematic diagrams in the following embodiments are all cross-sectional schematic diagrams along the B-B direction, and will not be repeated in the following embodiments.
在一实施例中，第一结构210的机械强度大于第二结构220的机械强度，第一结构210用于抑制机械损伤。可以理解的是，结构的机械强度决定于材料的自身特性和结构的组成特性等，因此，可以采用抗剪切力系数和抗拉力系数较高的材料形成第一结构210，以提高第一结构210的机械强度；也可以形成横截面积较大的第一结构210，以提高第一结构210的机械强度。In one embodiment, the mechanical strength of the first structure 210 is greater than the mechanical strength of the second structure 220, and the first structure 210 is used to suppress mechanical damage. It can be understood that the mechanical strength of the structure is determined by the characteristics of the material itself and the composition characteristics of the structure. Therefore, the first structure 210 can be formed by using a material with a higher shear resistance coefficient and a higher tensile force coefficient to improve the first structure. The mechanical strength of the structure 210; the first structure 210 with a larger cross-sectional area can also be formed to improve the mechanical strength of the first structure 210.
在一实施例中，第二结构220的电阻率大于第一结构210的电阻率，且第二结构220的电阻值与机械损伤的大小相匹配。可以理解的是，结构的电阻率决定于材料的自身特性和结构的组成特性等，因此可以采用电阻率较高的材料形成第二结构220，以提高第二结构220的电阻率；也可以形成横截 面积较小或长度较长的第二结构220，以提高第二结构220的电阻率。其中，第二结构220的电阻值与机械损伤的大小相匹配是指第二结构220的电阻值与机械损伤的大小存在相关关系。具体地，该相关关系可以是正相关关系，即裂纹的宽度和/或裂纹的长度越大，则第二结构220的电阻值越大；该相关关系也可以是负相关关系，即裂纹的宽度和/或裂纹的长度越大，则第二结构220的电阻值越小。In one embodiment, the resistivity of the second structure 220 is greater than the resistivity of the first structure 210, and the resistivity of the second structure 220 matches the magnitude of the mechanical damage. It can be understood that the resistivity of the structure is determined by the characteristics of the material itself and the composition characteristics of the structure. Therefore, the second structure 220 can be formed with a material with a higher resistivity to increase the resistivity of the second structure 220; it can also be formed The second structure 220 with a smaller cross-sectional area or a longer length improves the resistivity of the second structure 220. The matching of the resistance value of the second structure 220 with the size of the mechanical damage means that the resistance value of the second structure 220 has a correlation with the size of the mechanical damage. Specifically, the correlation may be a positive correlation, that is, the larger the width and/or the length of the crack, the greater the resistance value of the second structure 220; the correlation may also be a negative correlation, that is, the width of the crack and the /Or the greater the length of the crack, the smaller the resistance value of the second structure 220.
在一实施例中，如图5至图7所示，第二保护环200为非闭合环形，第二保护环200设有开口201，且开口201处设有引出端子202，引出端子202与监测模块连接以获取第二保护环200的阻值信息。其中，阻值信息可以是电阻值，如5Ω、10Ω等；也可以是电阻变化值，即当前测试时刻的电阻值与前一测试时刻的电阻值之间的差值，如0.5Ω、0.1Ω等；还可以是阻值变化速率，即当前测试时刻的电阻值和前一测试时刻的电阻值之间的差值与测试时间间隔的比值，如0.005Ω/ms、0.01Ω/ms等，当阻值变化速率发生突变时，说明机械损伤的大小发生了突变，从而更加准确、快速地获取机械损伤的变化情况。In one embodiment, as shown in FIGS. 5 to 7, the second protection ring 200 is a non-closed ring, the second protection ring 200 is provided with an opening 201, and the opening 201 is provided with a lead-out terminal 202, the lead-out terminal 202 and the monitor The modules are connected to obtain the resistance information of the second protection ring 200. Among them, the resistance value information can be the resistance value, such as 5Ω, 10Ω, etc.; it can also be the resistance change value, that is, the difference between the resistance value at the current test moment and the resistance value at the previous test moment, such as 0.5Ω, 0.1Ω It can also be the rate of resistance change, that is, the ratio of the difference between the resistance value at the current test moment and the resistance value at the previous test moment to the test time interval, such as 0.005Ω/ms, 0.01Ω/ms, etc. When the resistance change rate has a sudden change, it indicates that the size of the mechanical damage has undergone a sudden change, so that the change of the mechanical damage can be obtained more accurately and quickly.
进一步地，监测模块具有监测功能和警示功能，监测功能用于实时获取第二保护环200的阻值信息，警示功能用于根据预设的警示条件和阻值信息发出警示信号。例如，预设的警示条件为实时电阻值超过电阻阈值，则当实时电阻值小于电阻阈值时，不发出警示信号；当实时电阻值不小于电阻阈值时，发出警示信号，以提示操作人员、切片设备或封装设备调整裸片的切割和保护策略。Further, the monitoring module has a monitoring function and a warning function. The monitoring function is used to obtain the resistance value information of the second protection ring 200 in real time, and the warning function is used to send a warning signal according to preset warning conditions and resistance value information. For example, the preset warning condition is that the real-time resistance value exceeds the resistance threshold. When the real-time resistance value is less than the resistance threshold, no warning signal will be sent; when the real-time resistance value is not less than the resistance threshold, a warning signal will be sent out to remind the operator and slicer. The equipment or packaging equipment adjusts the die cutting and protection strategy.
在一示例中，监测模块是外接的电阻测试设备，当使用外接的电阻测试设备对第二保护环200进行监测时，将电阻测试设备的测试探针连接至引出 端子202以获取第二保护环200的阻值信息。外接的电阻测试设备可以兼容较大的数据存储空间，并在数据存储空间中保存较长时间范围内的阻值信息，因此可以为其他裸片的切片和封装工艺控制提供更多的参考数据。In an example, the monitoring module is an external resistance test device. When the external resistance test device is used to monitor the second protection ring 200, the test probe of the resistance test device is connected to the lead terminal 202 to obtain the second protection ring. 200 resistance value information. The external resistance test equipment can be compatible with a larger data storage space, and store resistance information within a longer time range in the data storage space, so it can provide more reference data for slicing and packaging process control of other bare chips.
在另一示例中，监测模块是设于衬底表面的监测电路，进一步地，监测电路可以集成于芯片内部电路301中，也可以在芯片内部电路301以外独立设置。设置在衬底表面的监测电路不受测试位置和外接测试设备的限制，因此可以更加灵活地监测第二保护环200的阻值信息。In another example, the monitoring module is a monitoring circuit provided on the surface of the substrate. Further, the monitoring circuit can be integrated in the internal circuit 301 of the chip, or can be independently provided outside the internal circuit 301 of the chip. The monitoring circuit provided on the surface of the substrate is not limited by the test location and the external test equipment, so the resistance information of the second guard ring 200 can be monitored more flexibly.
在图5至图7所示的实施例中，第二保护环200设有一个开口201，并在开口201处设有两个引出端子202。其中，两个引出端子202可以都连接至第一结构210中；也可以都连接至第二结构220中；还可以一个引出端子202连接至第一结构210中，另一个引出端子202连接至第二结构220中。需要说明的是，连接至第一结构210或第二结构220中的“连接”既可以是将第一结构210或第二结构220中的一个功能层作为引出端子202，也可以是额外设置引出端子202，并将该引出端子202通过金属线连接至第一结构210或第二结构220。In the embodiment shown in FIGS. 5 to 7, the second protection ring 200 is provided with an opening 201, and two lead terminals 202 are provided at the opening 201. Wherein, the two lead-out terminals 202 can both be connected to the first structure 210; or both can be connected to the second structure 220; it is also possible that one lead-out terminal 202 is connected to the first structure 210, and the other lead-out terminal 202 is connected to the first structure 210. The second structure 220. It should be noted that the "connection" connected to the first structure 210 or the second structure 220 can either use one of the functional layers in the first structure 210 or the second structure 220 as the lead terminal 202, or it can be an additional lead. The terminal 202 is connected to the first structure 210 or the second structure 220 through a metal wire.
图8为一实施例的设有两个开口201的第二保护环200的俯视示意图，如图8所示，第二保护环200设有两个开口201，并在每个开口201处设有两个引出端子202，第二保护环200被两个开口201划分为两个保护段，每对引出端子202用于获取相应保护段的阻值信息，在本实施例中，通过两对引出端子202和两个保护段的结构，可以更加准确地获取裂缝的位置和方向。FIG. 8 is a schematic top view of a second protection ring 200 provided with two openings 201 according to an embodiment. As shown in FIG. 8, the second protection ring 200 is provided with two openings 201, and each opening 201 is provided Two lead-out terminals 202, the second protection ring 200 is divided into two protection sections by two openings 201, each pair of lead-out terminals 202 is used to obtain the resistance value information of the corresponding protection section. In this embodiment, two pairs of lead-out terminals With the structure of 202 and two protection sections, the position and direction of cracks can be obtained more accurately.
在其他实施例中，第二保护环200也可以设有多个开口201，并在每个开口201处设有两个引出端子202，第二保护环200被多个开口201划分为多个保护段。进一步地，可以在易于发生机械损伤的区域如裸片300的边角 区域设置多个保护段，并在不易于发生机械损伤的区域如裸片300的直线边上只设置一个保护段，从而对机械损伤的大小进行更加准确的监测。In other embodiments, the second protection ring 200 may also be provided with a plurality of openings 201, and each opening 201 is provided with two lead terminals 202, and the second protection ring 200 is divided into a plurality of protections by the plurality of openings 201. part. Further, multiple protection sections can be provided in areas prone to mechanical damage, such as the corner areas of the die 300, and only one protection section can be provided in areas where mechanical damage is not prone to occur, such as the straight edge of the die 300, so as to prevent The size of mechanical damage is monitored more accurately.
在一实施例中，第一结构210和第二结构220均为叠层结构，且包括相同的导体结构。其中，相同的导体结构是指器件中各个功能层的设置顺序和材料都相同的导体结构，但是相同的导体结构不限定第一结构210和第二结构220的具体尺寸，即第一结构210和第二结构220中的导体结构的尺寸可以不同。In one embodiment, the first structure 210 and the second structure 220 are both stacked structures and include the same conductor structure. Wherein, the same conductor structure refers to a conductor structure in which the arrangement order and materials of each functional layer in the device are the same, but the same conductor structure does not limit the specific size of the first structure 210 and the second structure 220, that is, the first structure 210 and the second structure 220 The size of the conductor structure in the second structure 220 may be different.
在一实施例中，导体结构包括：至少两层金属层；通孔层，设于相邻的两层金属层之间，用于连接相邻的金属层。具体地，相邻的两层金属层在垂直方向上至少部分重叠，且在重叠部分设有通孔层以导通相邻的金属层。In an embodiment, the conductor structure includes: at least two metal layers; and a via layer, which is arranged between two adjacent metal layers and is used to connect the adjacent metal layers. Specifically, two adjacent metal layers at least partially overlap in the vertical direction, and a through hole layer is provided in the overlapped portion to conduct the adjacent metal layers.
图9为一实施例的导体结构的截面示意图，如图9所示，导体结构包括两层金属层，分别为顶层金属层233和底层金属层231，顶层金属层233和底层金属层231之间设有用于导通金属层的通孔层234。图10为另一实施例的导体结构的截面示意图，如图10所示，导体结构包括三层金属层，分别为顶层金属层233、中间金属层232和底层金属层231，顶层金属层233和中间金属层232之间设有用于导通金属层的通孔层234，中间金属层232和底层金属层231之间也设有用于导通金属层的通孔层234。在其他实施例中，导体结构可以包括至少四层金属层，分别为顶层金属层233、至少两层中间金属层232和顶层金属层233，相邻的两层金属层之间均设有用于导通金属层的通孔层234。FIG. 9 is a schematic cross-sectional view of a conductor structure of an embodiment. As shown in FIG. 9, the conductor structure includes two metal layers, namely, a top metal layer 233 and a bottom metal layer 231, between the top metal layer 233 and the bottom metal layer 231 A via layer 234 for conducting the metal layer is provided. FIG. 10 is a schematic cross-sectional view of a conductor structure of another embodiment. As shown in FIG. 10, the conductor structure includes three metal layers, which are a top metal layer 233, a middle metal layer 232, and a bottom metal layer 231, and the top metal layer 233 and A via layer 234 for conducting the metal layer is provided between the middle metal layer 232, and a via layer 234 for conducting the metal layer is also provided between the middle metal layer 232 and the bottom metal layer 231. In other embodiments, the conductor structure may include at least four metal layers, which are the top metal layer 233, at least two intermediate metal layers 232, and the top metal layer 233, respectively. A conductive structure is provided between two adjacent metal layers. Via layer 234 of the metal layer.
在一实施例中，如图11所示，介质材料和设于介质材料中至少一个通孔236，其中，通孔236沿垂直方向贯穿介质材料，用于导通相邻的两层导电层；介质材料用于维持通孔236的结构稳定，以提高第一结构210和第二结构220 的机械强度。可选地，介质材料可以为氧化硅、氮化硅或氮氧化硅，并采用原子层沉积(Atomic Layer Deposition)或者化学气相沉积(Chemical Vapor Deposition)的方法形成，从而保证通孔236的厚度精确性和膜层平整度。In an embodiment, as shown in FIG. 11, the dielectric material and at least one through hole 236 provided in the dielectric material, wherein the through hole 236 penetrates the dielectric material in a vertical direction for conducting two adjacent conductive layers; The dielectric material is used to maintain the structural stability of the through hole 236 to improve the mechanical strength of the first structure 210 and the second structure 220. Optionally, the dielectric material can be silicon oxide, silicon nitride, or silicon oxynitride, and is formed by atomic layer deposition (Atomic Layer Deposition) or chemical vapor deposition (Chemical Vapor Deposition), so as to ensure that the thickness of the through hole 236 is accurate. Performance and film flatness.
在一实施例中，通孔236可以为槽型结构。图11为本实施例的槽型结构的通孔236的截面示意图，如图11所示，本实施例的导电结构包括两个导电层，槽型结构的通孔236是指在需要连接的导电层235的表面设置设定深度的凹槽，并在凹槽内也填入导电材料形成的通孔236，以与底层金属层231电连接，其中，导电层235可以为有源区或多晶硅。本实施例通过槽型结构的通孔236，可以保证通孔236与导电层235之间具有较大的接触面积，从而减小了接触电阻。In an embodiment, the through hole 236 may be a groove-shaped structure. 11 is a schematic cross-sectional view of the through hole 236 of the groove structure of this embodiment. As shown in FIG. 11, the conductive structure of this embodiment includes two conductive layers. The through hole 236 of the groove structure refers to the conductive The surface of the layer 235 is provided with a groove of a predetermined depth, and a through hole 236 formed of a conductive material is also filled in the groove to be electrically connected to the underlying metal layer 231. The conductive layer 235 may be an active region or polysilicon. In this embodiment, the through hole 236 of the groove structure can ensure a larger contact area between the through hole 236 and the conductive layer 235, thereby reducing the contact resistance.
图12为一实施例的第二保护环200的部分截面示意图，图12中仅示出两个第一结构210和一个第二结构220，图12用于表示第一结构210和第二结构220的连接关系，需要说明的是，其他未示出的第一结构210和第二结构220的连接关系与图12所示的连接关系相同。FIG. 12 is a schematic partial cross-sectional view of the second guard ring 200 according to an embodiment. FIG. 12 shows only two first structures 210 and one second structure 220, and FIG. 12 is used to show the first structure 210 and the second structure 220 It should be noted that the other unshown connection relationships of the first structure 210 and the second structure 220 are the same as the connection relationship shown in FIG. 12.
图13为图12实施例的第一结构210的截面示意图，如图13所示，第一结构210包括：第一导电结构；衬底接触孔215，用于连接第一底层金属层211和衬底中的有源区；第一导体接触孔216，用于连接第一底层金属层211和导体层203。13 is a schematic cross-sectional view of the first structure 210 of the embodiment of FIG. 12. As shown in FIG. 13, the first structure 210 includes: a first conductive structure; a substrate contact hole 215 for connecting the first underlying metal layer 211 and the liner The active area in the bottom; the first conductor contact hole 216 is used to connect the first bottom metal layer 211 and the conductor layer 203.
第一导电结构包括层叠依次设置的第一底层金属层211、第一中间金属层212和第一顶层金属层213，以及设于相邻的两层金属层之间的第一通孔层214。第一顶层金属层211和第一中间金属层212可以为铝、铜中的一种，第一底层金属层211可以为钨、铝、铜中的一种，导体层203可以为多晶硅。The first conductive structure includes a first bottom metal layer 211, a first middle metal layer 212, and a first top metal layer 213 stacked in sequence, and a first via layer 214 disposed between two adjacent metal layers. The first top metal layer 211 and the first intermediate metal layer 212 may be one of aluminum and copper, the first bottom metal layer 211 may be one of tungsten, aluminum, and copper, and the conductive layer 203 may be polysilicon.
图14为图12实施例的第二结构220的截面示意图，如图14所示，第二 结构220包括：第二导电结构；第二导体接触孔225，用于连接第二底层金属层221和导体层203；第二导电结构包括层叠依次设置的第二底层金属层221、第二中间金属层222和第二顶层金属层223，以及设于相邻的两层金属层之间的第二通孔层224；第二导电结构与第一导电结构相同，且第二顶层金属层223与第一顶层金属层213相连接。14 is a schematic cross-sectional view of the second structure 220 of the embodiment of FIG. 12. As shown in FIG. 14, the second structure 220 includes: a second conductive structure; a second conductor contact hole 225 for connecting the second underlying metal layer 221 and Conductor layer 203; the second conductive structure includes a second bottom metal layer 221, a second middle metal layer 222, and a second top metal layer 223 that are stacked in sequence, and a second pass provided between two adjacent metal layers Hole layer 224; the second conductive structure is the same as the first conductive structure, and the second top metal layer 223 is connected to the first top metal layer 213.
本实施例通过上述第一结构210和第二结构220，实现了机械强度大且监测机械损伤准确的第二保护环200。需要说明的是，可以将两个第一顶层金属层213作为与监测模块连接的引出端子202，也可以将两个第一底层金属层211作为与监测模块连接的引出端子202，本实施例不具体限定引出端子202在第一结构210和第二结构220中的位置，以上引出端子202的设置方式均能够准确地监测裸片300的机械损伤。In this embodiment, through the above-mentioned first structure 210 and second structure 220, the second protection ring 200 with high mechanical strength and accurate mechanical damage monitoring is realized. It should be noted that the two first top metal layers 213 can be used as the lead-out terminals 202 connected to the monitoring module, and the two first bottom metal layers 211 can also be used as the lead-out terminals 202 connected to the monitoring module. This embodiment does not The positions of the lead-out terminals 202 in the first structure 210 and the second structure 220 are specifically defined. The above-mentioned arrangement of the lead-out terminals 202 can accurately monitor the mechanical damage of the die 300.
在一实施例中，如图13至图14所示，第一结构210沿第二保护环200的延伸路径纵向切割的截面的宽度d3可以为5um至50um，第二结构220沿第二保护环200的延伸路径纵向切割的截面的宽度d4可以为0.5um至1um。In one embodiment, as shown in FIGS. 13 to 14, the width d3 of the cross-section longitudinally cut along the extension path of the second protection ring 200 of the first structure 210 may be 5um to 50um, and the second structure 220 may extend along the second protection ring. The width d4 of the cross section longitudinally cut by the extension path of 200 may be 0.5 um to 1 um.
需要说明的是，上述具体数值只是一种示意，并不构成对本发明所涉及的半导体结构的限定。It should be noted that the above specific numerical value is only an illustration, and does not constitute a limitation on the semiconductor structure involved in the present invention.
图15为一实施例的半导体结构的制备方法的流程图，如图15所示，制备方法包括步骤S100至S300。FIG. 15 is a flowchart of a manufacturing method of a semiconductor structure according to an embodiment. As shown in FIG. 15, the manufacturing method includes steps S100 to S300.
S100：提供衬底，衬底中已形成有隔离结构和有源区。S100: Provide a substrate, and an isolation structure and an active area have been formed in the substrate.
S200：在衬底表面形成衬底接触孔215、第一导体接触孔216和第二导体接触孔225，其中衬底接触孔215和第一导体接触孔216的顶部相齐平。S200: forming a substrate contact hole 215, a first conductor contact hole 216, and a second conductor contact hole 225 on the surface of the substrate, wherein the top of the substrate contact hole 215 and the first conductor contact hole 216 are flush.
S300：在衬底接触孔215和第一导体接触孔216的表面形成第一导电结构，在第二导体接触孔225的表面形成第二导电结构。S300: A first conductive structure is formed on the surface of the substrate contact hole 215 and the first conductor contact hole 216, and a second conductive structure is formed on the surface of the second conductor contact hole 225.
在一实施例中，第一导电结构和第二导电结构均包括两层金属层，即第一导电结构包括第一底层金属层211和第一顶层金属层213，第二导电结构包括第二底层金属层221和第二顶层金属层223，图16为本实施例的步骤S300的子流程图，如图16所示，步骤S300包括步骤S310至S330。In an embodiment, both the first conductive structure and the second conductive structure include two metal layers, that is, the first conductive structure includes a first bottom metal layer 211 and a first top metal layer 213, and the second conductive structure includes a second bottom metal layer. For the metal layer 221 and the second top metal layer 223, FIG. 16 is a sub-flow chart of step S300 in this embodiment. As shown in FIG. 16, step S300 includes steps S310 to S330.
S310：在衬底接触孔215和第一导体接触孔216的表面形成第一底层金属层211，在第二导体接触孔225的表面形成第二底层金属层221；S310: forming a first bottom metal layer 211 on the surface of the substrate contact hole 215 and the first conductor contact hole 216, and forming a second bottom metal layer 221 on the surface of the second conductor contact hole 225;
S320：在第一底层金属层211的表面形成第一通孔层214，在第二底层金属层221的表面形成第二通孔层224；S320: forming a first via layer 214 on the surface of the first bottom metal layer 211, and forming a second via layer 224 on the surface of the second bottom metal layer 221;
S330：在第一通孔层214的表面形成第一顶层金属层213，在第二通孔层224的表面形成第二顶层金属层223，其中，第一顶层金属层213与第二顶层金属层223相连接。S330: A first top metal layer 213 is formed on the surface of the first via layer 214, and a second top metal layer 223 is formed on the surface of the second via layer 224, wherein the first top metal layer 213 and the second top metal layer 223 is connected.
应该理解的是，虽然图15至图16的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图15至图16中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。It should be understood that although the various steps in the flowcharts of FIGS. 15 to 16 are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless specifically stated in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least part of the steps in FIGS. 15 to 16 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. These sub-steps or The execution order of the stages is not necessarily carried out sequentially, but may be executed alternately or alternately with other steps or at least a part of other steps or sub-steps or stages.
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be It is considered as the range described in this specification.
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细， 但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。The above examples only express several implementations of the present invention, and the descriptions are relatively specific and detailed, but they should not be understood as limiting the scope of the invention patent. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can be made, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims (10)

  1. 一种半导体结构，设于裸片的衬底表面，所述裸片包括芯片内部电路，所述半导体结构包括：A semiconductor structure is provided on the surface of a substrate of a bare chip, the bare chip includes an internal circuit of the chip, and the semiconductor structure includes:
    第一保护环，围绕所述芯片内部电路设置，用于抑制所述裸片的机械损伤；及The first protection ring is arranged around the internal circuit of the chip and is used to suppress mechanical damage of the die; and
    第二保护环，围绕所述芯片内部电路设置，用于抑制所述机械损伤，且用于监测所述机械损伤的大小；The second protection ring is arranged around the internal circuit of the chip, and is used to suppress the mechanical damage and to monitor the magnitude of the mechanical damage;
    其中，所述第二保护环包括多个第一结构和多个第二结构，所述第一结构和所述第二结构具有不同的机械强度和不同的电阻率。Wherein, the second guard ring includes a plurality of first structures and a plurality of second structures, and the first structure and the second structure have different mechanical strengths and different resistivities.
  2. 根据权利要求1所述的半导体结构，其中所述第一结构和所述第二结构在所述第二保护环的延伸路径上互相间隔设置。The semiconductor structure according to claim 1, wherein the first structure and the second structure are spaced apart from each other on an extension path of the second guard ring.
  3. 根据权利要求1所述的半导体结构，其中所述第一结构的机械强度大于所述第二结构的机械强度，所述第一结构用于抑制所述机械损伤。The semiconductor structure according to claim 1, wherein the mechanical strength of the first structure is greater than the mechanical strength of the second structure, and the first structure is used to suppress the mechanical damage.
  4. 根据权利要求1所述的半导体结构，其中所述第二结构的电阻率大于所述第一结构的电阻率，且所述第二结构的电阻值与所述机械损伤的大小相匹配。4. The semiconductor structure of claim 1, wherein the resistivity of the second structure is greater than the resistivity of the first structure, and the resistivity of the second structure matches the magnitude of the mechanical damage.
  5. 根据权利要求1所述的半导体结构，其中所述第二保护环设有开口，且所述开口处设有引出端子，所述引出端子与监测模块连接以获取所述第二保护环的阻值信息。The semiconductor structure according to claim 1, wherein the second guard ring is provided with an opening, and a lead-out terminal is provided at the opening, and the lead-out terminal is connected to a monitoring module to obtain the resistance value of the second guard ring information.
  6. 根据权利要求5所述的半导体结构，其中所述监测模块为监测电路，所述监测电路设于所述衬底的表面，用于获取所述第二保护环的阻值信息。5. The semiconductor structure according to claim 5, wherein the monitoring module is a monitoring circuit, and the monitoring circuit is provided on the surface of the substrate for obtaining resistance information of the second guard ring.
  7. 根据权利要求1所述的半导体结构，其中所述第一结构和所述第二结构在所述衬底上的投影不重叠。The semiconductor structure according to claim 1, wherein the projections of the first structure and the second structure on the substrate do not overlap.
  8. 根据权利要求1所述的半导体结构，其中所述第一结构和所述第二结构均为叠层结构，且包括相同的导体结构。The semiconductor structure according to claim 1, wherein the first structure and the second structure are both stacked structures and include the same conductor structure.
  9. 根据权利要求8所述的半导体结构，其中所述导体结构包括：The semiconductor structure of claim 8, wherein the conductor structure comprises:
    至少两层金属层；At least two metal layers;
    通孔层，设于相邻的两层所述金属层之间，用于连接相邻的所述金属层。The through hole layer is arranged between two adjacent metal layers and is used to connect the adjacent metal layers.
  10. 根据权利要求9所述的半导体结构，其中所述第一结构还包括衬底接触结构，所述导体结构通过所述衬底接触结构与所述衬底电连接。9. The semiconductor structure according to claim 9, wherein the first structure further comprises a substrate contact structure, and the conductor structure is electrically connected to the substrate through the substrate contact structure.
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