WO2021189470A1

WO2021189470A1 - Magnetic random access memory and electronic device

Info

Publication number: WO2021189470A1
Application number: PCT/CN2020/081833
Authority: WO
Inventors: 叶力; 李文静
Original assignee: 华为技术有限公司
Priority date: 2020-03-27
Filing date: 2020-03-27
Publication date: 2021-09-30
Also published as: CN115315748A

Abstract

A magnetic random access memory and an electronic device, which are used for increasing the storage density of the magnetic random access memory. The magnetic random access memory comprises a plurality of storage blocks and a plurality of groups of same-layer interconnect lines, wherein each of the plurality of storage blocks comprises a plurality of structural units and a plurality of voltage control lines; each of the plurality of structural units comprises a plurality of layers of storage structures, which are successively stacked; each of the plurality of layers of storage structures comprises an electrode line and a plurality of storage units provided on the electrode line; each of the plurality of storage units comprises a magnetic tunnel junction; one end of each storage unit is connected to the electrode line, and the other end thereof is connected to one of the plurality of voltage control lines; the plurality of storage blocks are arranged in parallel in the direction of the electrode lines; the plurality of groups of same-layer interconnect lines are parallel to the electrode lines, and the plurality of same-layer interconnect lines are used for connecting the voltage control lines, which correspond to each other in terms of position, in each storage block.

Description

一种磁性随机存储器及电子设备Magnetic random access memory and electronic equipment

技术领域Technical field

本申请涉存储技术领域，尤其涉及一种磁性随机存储器及电子设备。This application relates to the field of storage technology, and in particular to a magnetic random access memory and electronic equipment.

背景技术Background technique

信息技术的发展对存储介质提出了更高要求，相比于传统的半导体存储技术，以磁性隧道结(magnetic tunnel junction，MTJ)为存储单元的磁性随机存储器(magnetic random access memory，MRAM)由于同时具有很多优异的特性，例如：读写速度快、低功耗、读写次数多、耐辐射等，被认为是具有广阔应用前景的高密度存储器。The development of information technology has put forward higher requirements for storage media. Compared with traditional semiconductor storage technology, magnetic random access memory (MRAM) with magnetic tunnel junction (MTJ) as the storage unit is due to the simultaneous With many excellent characteristics, such as: fast reading and writing speed, low power consumption, many times of reading and writing, radiation resistance, etc., it is considered to be a high-density memory with broad application prospects.

MRAM的核心存储单元是MTJ，每个MTJ包括自由层、势垒层和参考层。在MTJ中写入数据时，可以通过改变自由层的磁矩方向(即控制MTJ自由层和参考层的磁矩平行排列或反平行排列)写入不同的数据。从MTJ中读取数据时，可以通过判断MTJ的高低阻态来实现。The core memory cell of MRAM is MTJ, and each MTJ includes a free layer, a barrier layer and a reference layer. When writing data in the MTJ, different data can be written by changing the direction of the magnetic moment of the free layer (that is, controlling the parallel or anti-parallel arrangement of the magnetic moments of the MTJ free layer and the reference layer). When reading data from MTJ, it can be realized by judging the high and low resistance state of MTJ.

现有技术中，MRAM的存储阵列通常是二维(2 dimensions，2D)的。为了提高MRAM的存储密度，采用的方案是不断缩小MTJ的尺寸和间距，从而增加单位面积内的存储单元个数。这种方式虽然可以在一定程度上提高MRAM的存储密度，但是当MTJ的尺寸缩小到一定程度时，MTJ的热稳定性就会下降，导致存储数据的可靠性降低。In the prior art, the MRAM storage array is usually two-dimensions (2D). In order to increase the storage density of MRAM, the solution adopted is to continuously reduce the size and spacing of the MTJ, thereby increasing the number of memory cells per unit area. Although this method can increase the storage density of the MRAM to a certain extent, when the size of the MTJ is reduced to a certain extent, the thermal stability of the MTJ will decrease, resulting in a decrease in the reliability of the stored data.

因此，亟需一种MRAM的存储阵列方案，以提高MRAM的存储密度。Therefore, there is an urgent need for a MRAM storage array solution to increase the storage density of MRAM.

发明内容Summary of the invention

本申请实施例提供了一种磁性随机存储器及电子设备，用以提高磁性随机存储器的存储密度。The embodiments of the present application provide a magnetic random access memory and electronic equipment to improve the storage density of the magnetic random access memory.

第一方面，本申请实施例提供一种磁性随机存储器，该磁性随机存储器包括多个存储块以及多组同层互连线；多个存储块中的每个存储块包括多个结构单元以及多个电压控制线；多个结构单元中的每个结构单元包括依次堆叠的多层存储结构，多层存储结构中的每层存储结构包括电极线以及设置于电极线上的多个存储单元，多个存储单元中的每个存储单元包括一个磁性隧道结，每个存储单元的一端与电极线连接，另一端与多个电压控制线中的一个电压控制线连接；其中，多个存储块沿着电极线的方向平行排列，多组同层互连线与电极线平行，多组同层互连线用于连接每个存储块中位置对应的电压控制线。In the first aspect, an embodiment of the present application provides a magnetic random access memory, which includes multiple memory blocks and multiple sets of interconnects at the same layer; each memory block in the multiple memory blocks includes multiple structural units and multiple A voltage control line; each of the plurality of structural units includes a multilayer memory structure stacked in sequence, and each layer of the memory structure in the multilayer memory structure includes an electrode line and a plurality of memory cells arranged on the electrode line, and Each memory cell in the two memory cells includes a magnetic tunnel junction, one end of each memory cell is connected to the electrode line, and the other end is connected to one of the plurality of voltage control lines; wherein, the plurality of memory blocks are connected along the The electrode lines are arranged in parallel, and multiple sets of same-layer interconnection lines are parallel to the electrode lines, and multiple sets of same-layer interconnection lines are used to connect voltage control lines corresponding to positions in each memory block.

其中，每个磁性隧道结包括依次堆叠的自由层、势垒层和参考层，自由层与电极线连接，参考层与电压控制线连接。Wherein, each magnetic tunnel junction includes a free layer, a barrier layer and a reference layer stacked in sequence, the free layer is connected to the electrode line, and the reference layer is connected to the voltage control line.

采用第一方面提供的磁性随机存储器，由于存储阵列是三维(3 dimensions，3D)的，该方案相比现有技术中的2D阵列，可以在保证存储单元的热稳定的前提下，通过垂直方向存储单元的叠加增加面存储密度，进而提高磁性随机存储器的存储密度。此外，由于在该磁性随机存储器中，通过多组同层互连线将每个存储块中位置对应的电压控制线连接起来，因而在向磁性随机存储器中写入数据或者从磁性随机存储器中读取数据时，可以通过一个同层互连线实现同时向位置对应的多个电压控制线施加相应电压，从而减少位线在***电路平面的排线空间，通过较少的位线实现对磁性随机存储器中多层存储结构的寻址和访问。Using the magnetic random access memory provided in the first aspect, since the storage array is three-dimensional (3 dimensions, 3D), compared with the 2D array in the prior art, this solution can pass through the vertical direction under the premise of ensuring the thermal stability of the storage unit. The stacking of storage units increases the surface storage density, thereby increasing the storage density of the magnetic random access memory. In addition, because in the magnetic random access memory, the voltage control lines corresponding to the positions in each memory block are connected through multiple sets of the same layer interconnection lines, so data is written to or read from the magnetic random access memory. When fetching data, it is possible to simultaneously apply corresponding voltages to multiple voltage control lines corresponding to the position through an interconnection line of the same layer, thereby reducing the wiring space of the bit line in the peripheral circuit plane, and achieving random magnetic resistance through fewer bit lines. Addressing and accessing the multi-level storage structure in the memory.

具体地，多组同层互连线中的每组同层互连线用于连接多层存储结构中的一层存储结构所对应的电压控制线。Specifically, each group of same-layer interconnection lines in the multiple sets of same-layer interconnection lines is used to connect a voltage control line corresponding to a storage structure of one layer in the multi-layer storage structure.

此外，在第一方面提供的磁性随机存储器中，多个电压控制线平行，多个结构单元所在的平面平行，且多个结构单元中每个结构单元所在的平面与多个电压控制线垂直。In addition, in the magnetic random access memory provided by the first aspect, the multiple voltage control lines are parallel, the planes on which the multiple structural units are located are parallel, and the plane on which each structural unit of the multiple structural units is located is perpendicular to the multiple voltage control lines.

在第一方面提供的磁性随机存储器中，电压控制线、同层互连线以及***电路中的位线之间的连接方式可以有多种，下面以其中两种为例进行说明。In the magnetic random access memory provided in the first aspect, there may be multiple connection modes between the voltage control line, the same-layer interconnection line, and the bit line in the peripheral circuit, and two of them are described as examples below.

第一种The first

每个存储块中位置对应的电压控制线中的一个电压控制线通过层间金属互连线与第一位线对应连接，第一位线用于向对应连接的电压控制线施加电压，第一位线与对应连接的电压控制线平行。One of the voltage control lines corresponding to the position in each memory block is connected to the first bit line through the interlayer metal interconnection line. The first bit line is used to apply voltage to the correspondingly connected voltage control line. The bit line is parallel to the correspondingly connected voltage control line.

采用第一种连接方式，在通过同一个同层互连线连接的位置对应的多个电压控制线中，有一个电压控制线通过层间金属互连线与第一位线连接。也就是说，在第一种连接方式中，是由电压控制线通过层间金属互连线与第一位线连接。In the first connection mode, among the multiple voltage control lines corresponding to the positions connected by the same layer interconnection line, one voltage control line is connected to the first bit line through the interlayer metal interconnection line. That is, in the first connection mode, the voltage control line is connected to the first bit line through the interlayer metal interconnection line.

第二种The second

多组同层互连线通过层间金属互连线分别与多组第一位线对应连接，多组第一位线分别用于向多组同层互连线对应连接的电压控制线施加电压，多组第一位线与多个电压控制线平行。Multiple sets of same-layer interconnection lines are respectively connected to multiple sets of first bit lines through interlayer metal interconnection lines, and multiple sets of first bit lines are respectively used to apply voltage to voltage control lines corresponding to multiple sets of same-layer interconnection lines. , The first bit lines of multiple groups are parallel to the multiple voltage control lines.

采用第二种连接方式，由同层互连线通过层间金属互连线与第一位线连接，所有同层互连线被平移到了第一层存储结构所在的平面。Using the second connection method, the same layer interconnection line is connected to the first bit line through the interlayer metal interconnection line, and all the same layer interconnection lines are translated to the plane where the first layer storage structure is located.

在一种可能的设计中，第一方面提供的磁性随机存储器中还可以包括多个字线，多个字线与电极线平行，多个字线与多个结构单元一一对应；每个存储块还包括第二位线和第三位线，第二位线、第三位线与多个电压控制线之间相互平行；每个结构单元还包括第一晶体管和第二晶体管，第一晶体管的栅极以及第二晶体管的栅极均与第一晶体管所属的结构单元对应的字线连接，第一晶体管的源极和漏极中的一个端口与第二位线连接、另一个端口通过金属导线与电极线的第一端连接，第二晶体管的源极和漏极中的一个端口与第三位线连接、另一个端口通过金属导线与电极线的第二端连接。In a possible design, the magnetic random access memory provided in the first aspect may further include multiple word lines, the multiple word lines are parallel to the electrode lines, and the multiple word lines correspond to multiple structural units one-to-one; each memory The block also includes a second bit line and a third bit line, the second bit line, the third bit line and the plurality of voltage control lines are parallel to each other; each structural unit also includes a first transistor and a second transistor, the first transistor The gate of the second transistor and the gate of the second transistor are both connected to the word line corresponding to the structural unit to which the first transistor belongs. One port of the source and drain of the first transistor is connected to the second bit line, and the other port is connected through the metal The wire is connected to the first end of the electrode line, one port of the source and drain of the second transistor is connected to the third bit line, and the other port is connected to the second end of the electrode line through a metal wire.

采用上述方案，第一晶体管和第二晶体管的栅极分别与字线连接，字线可用于为第一晶体管和第二晶体管提供栅极偏置电压，以使得第一晶体管和第二晶体管导通。分别在第二位线和第三位线上施加不同的电压，可以使得电极线中有电流通过，即为电极线上的存储单元提供写入电流。此外，通过第一位线还可以向待写入存储单元对应的电压控制线施加偏置电压。With the above solution, the gates of the first transistor and the second transistor are respectively connected to the word line, and the word line can be used to provide a gate bias voltage for the first transistor and the second transistor, so that the first transistor and the second transistor are turned on . Applying different voltages on the second bit line and the third bit line respectively can make the electrode lines flow through, that is, provide write current for the memory cells on the electrode lines. In addition, a bias voltage can also be applied to the voltage control line corresponding to the memory cell to be written through the first bit line.

进一步地，在向磁性随机存储器写入数据时，待写入存储单元所属的结构单元对应的字线分别向待写入存储单元所属的结构单元中的第一晶体管和第二晶体管施加栅极偏置电压；待写入存储单元所属的存储块中的第二位线和第三位线中的一个位线施加写入电压、另一个位线接地；与待写入存储单元连接的电压控制线对应的第一位线施加偏置电压。Further, when writing data to the magnetic random access memory, the word lines corresponding to the structural unit to which the memory cell to be written belongs respectively apply gate bias to the first transistor and the second transistor in the structural unit to which the memory cell to be written belongs. Set voltage; one of the second bit line and the third bit line in the memory block to which the memory cell to be written belongs is applied with a write voltage, and the other bit line is grounded; a voltage control line connected to the memory cell to be written A bias voltage is applied to the corresponding first bit line.

采用上述方案，与待写入存储单元连接的电压控制线对应的第一位线施加偏置电压，可以实现向多个存储块中与待写入存储单元位置相同的存储单元的电压控制线上同时施加偏置电压。进一步地，待写入存储单元所属的存储块中的第二位线和第三位线中的一个位线施加写入电压、另一个位线接地，非写入存储单元所属的存储块中的第二位线和第三位线均接地，因此采用上述方案在向磁性随机存储器中写入数据时即可选中待写入存储单元。With the above solution, the bias voltage is applied to the first bit line corresponding to the voltage control line connected to the memory cell to be written, and the voltage control line of the memory cell in the same position as the memory cell to be written in the multiple memory blocks can be applied. Simultaneously apply a bias voltage. Further, one of the second bit line and the third bit line in the memory block to which the memory cell to be written belongs is applied with a write voltage, and the other bit line is grounded, and the non-write memory cell in the memory block to which the memory cell belongs The second bit line and the third bit line are both grounded. Therefore, the memory cell to be written can be selected when writing data to the magnetic random access memory using the above-mentioned solution.

进一步地，在从磁性随机存储器读取数据时，待读取结构单元对应的字线分别向待读取结构单元中的第一晶体管和第二晶体管施加栅极偏置电压；磁性随机存储器中的所有第一位线施加读取电压；待读取结构单元所属的存储块中的第二位线和第三位线接地。Further, when reading data from the magnetic random access memory, the word line corresponding to the structure unit to be read applies gate bias voltages to the first transistor and the second transistor in the structure unit to be read; A read voltage is applied to all the first bit lines; the second bit line and the third bit line in the memory block to which the structural unit to be read belongs are grounded.

采用上述方案，可以一次性读取磁性随机存储器中某一结构单元的数据：待读取结构单元对应的字线分别向待读取结构单元中的第一晶体管和第二晶体管施加栅极偏置电压，第一晶体管和第二晶体管导通；同时，磁性随机存储器中的所有第一位线施加读取电压，此时相当于选中了多个存储块中与待读取结构单元位置相同的所有结构单元；此外，待读取结构单元所属的存储块中的第二位线和第三位线接地，从而为待读取结构单元提供接地回路。由于所有第一位线均施加读取电压，相当于与待读取结构单元中所有存储单元所连接的电压控制线上均施加读取电压，使得待读取结构单元中的每个存储单元都包含在一条独立的读出回路中，进而读取待读取结构单元中的每个存储单元所存储的数据。With the above solution, the data of a structural unit in the magnetic random access memory can be read at one time: the word line corresponding to the structural unit to be read applies gate bias to the first transistor and the second transistor in the structural unit to be read respectively Voltage, the first transistor and the second transistor are turned on; at the same time, all the first bit lines in the magnetic random access memory are applied with a read voltage. At this time, it is equivalent to selecting all of the multiple memory blocks with the same position as the structural unit to be read. Structural unit; In addition, the second bit line and the third bit line in the memory block to which the structural unit to be read belongs are grounded, so as to provide a ground loop for the structural unit to be read. Since all the first bit lines are applied with the read voltage, it is equivalent to applying the read voltage on the voltage control line connected to all the memory cells in the structure unit to be read, so that each memory cell in the structure unit to be read is It is included in an independent read loop to read the data stored in each memory cell in the structure unit to be read.

此外，第一方面提供的磁性随机存储器还可以包括：分别与磁性随机存储器中的所有第一位线一一对应连接的多个放大器，多个放大器中的每个放大器用于读取对应连接的第一位线所接收的反馈信息。In addition, the magnetic random access memory provided by the first aspect may further include: a plurality of amplifiers respectively connected to all the first bit lines in the magnetic random access memory in a one-to-one correspondence, and each amplifier of the plurality of amplifiers is used to read the correspondingly connected The feedback information received by the first bit line.

采用上述方案，在从磁性随机存储器读取数据时，在与待读取结构单元中所有存储单元所连接的电压控制线上施加读取电压后，所有第一位线均会接收到反馈信息，该反馈信息反应了待读取结构单元中所有存储单元中存储的数据，通过该反馈信息可以获取待读取结构单元中所有存储单元所存储的数据。With the above solution, when reading data from the magnetic random access memory, after applying the read voltage on the voltage control line connected to all the memory cells in the structure unit to be read, all the first bit lines will receive the feedback information. The feedback information reflects the data stored in all the storage units in the structural unit to be read, and the data stored in all the storage units in the structural unit to be read can be obtained through the feedback information.

在一种可能的设计中，每个磁性隧道结的电阻值大于或等于100KΩ。In one possible design, the resistance value of each magnetic tunnel junction is greater than or equal to 100KΩ.

在写入数据时，电极线上的电流流经MTJ，形成潜行通路(sneak path)，会对写入数据的准确性产生影响。采用上述方案，可以使得MTJ的电阻值远大于电极线的电阻值，这样可以有效避免写入电流流经MTJ，降低sneak path的影响。When writing data, the current on the electrode line flows through the MTJ to form a sneak path, which will affect the accuracy of the written data. With the above solution, the resistance value of the MTJ can be made much larger than the resistance value of the electrode line, which can effectively prevent the writing current from flowing through the MTJ and reduce the influence of the sneak path.

第二方面，本申请实施例提供一种电子设备，该电子设备包括处理器以及与处理器耦合的、第一方面及其任一可能的设计中提供的磁性随机存储器。In the second aspect, an embodiment of the present application provides an electronic device including a processor and the magnetic random access memory provided in the first aspect and any possible design thereof coupled with the processor.

具体地，处理器可以调用磁性随机存储器中存储的软件程序，以执行相应的方法，实现电子设备的相应功能。Specifically, the processor may call a software program stored in the magnetic random access memory to execute a corresponding method to realize the corresponding function of the electronic device.

附图说明Description of the drawings

图1为本申请实施例提供的第一种磁性随机存储器的结构示意图；FIG. 1 is a schematic structural diagram of a first magnetic random access memory provided by an embodiment of this application;

图2为本申请实施例提供的第二种磁性随机存储器的结构示意图；2 is a schematic structural diagram of a second type of magnetic random access memory provided by an embodiment of the application;

图3为本申请实施例提供的第三种磁性随机存储器的结构示意图；3 is a schematic structural diagram of a third type of magnetic random access memory provided by an embodiment of the application;

图4为本申请实施例提供的第四种磁性随机存储器的结构示意图；4 is a schematic structural diagram of a fourth type of magnetic random access memory provided by an embodiment of the application;

图5为本申请实施例提供的第五种磁性随机存储器的结构示意图；FIG. 5 is a schematic structural diagram of a fifth type of magnetic random access memory provided by an embodiment of the application;

图6为本申请实施例提供的第六种磁性随机存储器的结构示意图；6 is a schematic structural diagram of a sixth type of magnetic random access memory provided by an embodiment of the application;

图7为本申请实施例提供的第七种磁性随机存储器的结构示意图；FIG. 7 is a schematic structural diagram of a seventh magnetic random access memory provided by an embodiment of the application;

图8为本申请实施例提供的第八种磁性随机存储器的结构示意图；FIG. 8 is a schematic structural diagram of an eighth type of magnetic random access memory provided by an embodiment of the application;

图9为本申请实施例提供的一种电子设备的结构示意图。FIG. 9 is a schematic structural diagram of an electronic device provided by an embodiment of the application.

具体实施方式Detailed ways

本申请实施例提供一种磁性随机存储器及电子设备，用以提高磁性随机存储器的存储密度。The embodiments of the present application provide a magnetic random access memory and an electronic device to improve the storage density of the magnetic random access memory.

下面，对本申请实施例的应用场景加以简单介绍。Below, the application scenarios of the embodiments of the present application are briefly introduced.

本申请实施例可以应用于图1所示的磁性随机存储器。该磁性随机存储器包括控制电路以及至少一个存储电路。The embodiments of this application can be applied to the magnetic random access memory shown in FIG. 1. The magnetic random access memory includes a control circuit and at least one storage circuit.

具体地，每个存储电路用于写入和读取数据。控制电路用于对存储电路写入和读取数据的过程进行控制，比如，在写入数据时选择要写入数据的存储单元、通过施加相应电压和通入相应电流以实现在选择的存储单元中写入数据，再比如，在读取数据时选择要读取的存储单元，通过施加相应电压和通入相应电流以实现从选择的存储单元中读取数据。Specifically, each storage circuit is used for writing and reading data. The control circuit is used to control the process of writing and reading data from the storage circuit. For example, when writing data, select the storage unit to write data, apply the corresponding voltage and pass the corresponding current to realize the selected storage unit Write data in the middle, for example, select the memory cell to be read when reading the data, and read the data from the selected memory cell by applying the corresponding voltage and passing the corresponding current.

其中，每个存储电路中包括多个存储单元，存储单元是磁性随机存储器中具有数据存储和读写功能的最小单元，可以用于存储一个最小信息单位，即1比特数据(例如0或1)，也就是一个二进制位。Among them, each storage circuit includes multiple storage units. The storage unit is the smallest unit with data storage and reading and writing functions in the magnetic random access memory. It can be used to store a minimum unit of information, that is, 1-bit data (for example, 0 or 1) , Which is a binary bit.

下面将结合附图对本申请实施例作进一步地详细描述。The embodiments of the present application will be described in further detail below in conjunction with the accompanying drawings.

需要说明的是，本申请中所涉及的多个，是指两个或两个以上。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。It should be noted that the multiple involved in this application refers to two or more. In addition, it should be understood that in the description of this application, words such as "first" and "second" are only used for the purpose of distinguishing description, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating Or imply the order.

参见图2，为本申请实施例提供的一种磁性随机存储器的结构示意图，该磁性随机存储器包括多个存储块(即Block)201以及多组同层互连线202。多个存储块201以及多组同层互连线202可以视为图1中的存储电路。Refer to FIG. 2, which is a schematic structural diagram of a magnetic random access memory provided by an embodiment of the application. The magnetic random access memory includes a plurality of memory blocks (ie, Block) 201 and a plurality of sets of interconnections 202 on the same layer. The multiple memory blocks 201 and multiple sets of the same layer interconnection lines 202 can be regarded as the memory circuit in FIG. 1.

其中，每个存储块201包括多个结构单元(cell)以及多个电压控制线；多个结构单元中的每个结构单元包括依次堆叠的多层存储结构，多层存储结构中的每层存储结构包括电极线以及设置于电极线上的多个存储单元，多个存储单元中的每个存储单元包括一个磁性隧道结，每个存储单元的一端与电极线连接，另一端与多个电压控制线中的一个电压控制线连接；多个存储块201沿着电极线的方向平行排列，多组同层互连线202与电极线平行，多组同层互连线202用于连接每个存储块201中位置对应的电压控制线。Among them, each memory block 201 includes a plurality of structural units (cells) and a plurality of voltage control lines; each structural unit of the plurality of structural units includes a multilayer memory structure stacked in sequence, and each layer of the multilayer memory structure stores The structure includes electrode lines and a plurality of memory cells arranged on the electrode lines. Each memory cell of the plurality of memory cells includes a magnetic tunnel junction. One end of each memory cell is connected to the electrode line, and the other end is controlled by a plurality of voltages. One of the lines is connected to a voltage control line; a plurality of memory blocks 201 are arranged in parallel along the direction of the electrode lines, and multiple sets of the same-layer interconnection lines 202 are parallel to the electrode lines, and multiple sets of the same-layer interconnection lines 202 are used to connect each memory The voltage control line corresponding to the position in block 201.

在每个存储块201中，电压控制线与存储单元是一一对应的，也就是说，每个存储单元均有与之对应的一个电压控制线，用于向该存储单元施加电压。In each memory block 201, the voltage control line and the memory cell have a one-to-one correspondence, that is, each memory cell has a corresponding voltage control line for applying voltage to the memory cell.

可选地，在每个存储块201中，多个电压控制线平行；多个结构单元所在的平面平行，且每个结构单元所在的平面与多个电压控制线垂直。Optionally, in each memory block 201, multiple voltage control lines are parallel; the plane where the multiple structure units are located is parallel, and the plane where each structure unit is located is perpendicular to the multiple voltage control lines.

需要说明的是，本申请实施例中，多个电压控制线平行的概念并不是严格意义上的平行，在磁性随机存储器的制备过程中，由于制备工艺和制备设备的影响，可能存在多个电压控制线并非严格平行的情况，这种情况是由于具体制备流程导致的，并不能说明多个电压控制线不严格平行的情况超脱本申请的保护范围。此外，对于平面平行和垂直这两种位置关系也有类似理解，此处不再赘述。It should be noted that in the embodiments of the present application, the concept of multiple voltage control lines being parallel is not strictly parallel. In the manufacturing process of the magnetic random access memory, due to the influence of the manufacturing process and the manufacturing equipment, there may be multiple voltages. The control lines are not strictly parallel. This situation is caused by the specific preparation process, and does not mean that the fact that the multiple voltage control lines are not strictly parallel is beyond the scope of protection of this application. In addition, there are similar understandings for the two positional relationships of plane parallel and vertical, which will not be repeated here.

为了方便描述，图2所示的磁性随机存储器中示出了xyz坐标系。其中，在每个存储块201中，电压控制线沿x轴平行排列；每个存储块201中的电极线沿y轴平行排列，磁性随机存储器中的多个同层互连线202沿y轴平行排列，多个存储块201沿y轴平行排列；在每个存储块201中，多层存储结构沿着z轴方向依次堆叠。每个结构单元所在的平面均与x轴垂直。For the convenience of description, an xyz coordinate system is shown in the magnetic random access memory shown in FIG. 2. Among them, in each memory block 201, the voltage control lines are arranged in parallel along the x-axis; the electrode lines in each memory block 201 are arranged in parallel along the y-axis, and the multiple interconnections 202 of the same layer in the magnetic random access memory are arranged along the y-axis. In a parallel arrangement, a plurality of storage blocks 201 are arranged in parallel along the y-axis; in each storage block 201, a multi-layer storage structure is sequentially stacked along the z-axis direction. The plane of each structural unit is perpendicular to the x-axis.

应理解，存储单元是磁性随机存储器中具有数据存储和读写功能的最小单元，可以用于存储一个最小信息单位，即1比特数据(例如0或1)，也就是一个二进制位。通过多个存储单元，可以实现多个二进制位数据的存储。具体地，本申请实施例中，一个存储单元中包括一个MTJ，用于存储一个二进制位。每个MTJ可以包括沿z轴正方向依次堆叠的自由层、势垒层和参考层。其中，参考层的磁矩方向固定，自由层的磁矩方向可以在数据写入时发生改变，自由层与参考层的磁矩呈平行或反平行排列时对应不同的数据，势垒层用于产生隧道磁电阻效应。具体地，本申请中，自由层与电极线连接，参考层与电压控制线连接。也就是说，自由层靠近与MTJ连接的电极线，参考层与该电极线距离最远，势垒层位于自由层和参考层之间。It should be understood that the storage unit is the smallest unit with data storage and reading and writing functions in the magnetic random access memory, and can be used to store a minimum information unit, that is, 1-bit data (for example, 0 or 1), that is, a binary bit. Through multiple storage units, the storage of multiple binary bit data can be realized. Specifically, in the embodiment of the present application, one storage unit includes one MTJ for storing one binary bit. Each MTJ may include a free layer, a barrier layer, and a reference layer sequentially stacked along the positive direction of the z-axis. Among them, the direction of the magnetic moment of the reference layer is fixed, and the direction of the magnetic moment of the free layer can be changed when data is written. When the magnetic moments of the free layer and the reference layer are arranged in parallel or anti-parallel to correspond to different data, the barrier layer is used for Produce tunnel magnetoresistance effect. Specifically, in this application, the free layer is connected to the electrode line, and the reference layer is connected to the voltage control line. That is, the free layer is close to the electrode line connected to the MTJ, the reference layer is the farthest from the electrode line, and the barrier layer is located between the free layer and the reference layer.

具体地，本申请实施例中，对于自由层和参考层的磁矩方向平行排列或反平行排列，可以有如下理解：自由层和参考层的磁矩方向可以在xy平面内，可以垂直于xy平面，或者与xy平面呈一定倾斜角度。本申请实施例中对自由层和参考层的磁矩方向不做具体限定，只要自由层和参考层的磁矩方向平行排列或反平行排列即可。Specifically, in the embodiments of the present application, regarding the parallel or anti-parallel arrangement of the magnetic moment directions of the free layer and the reference layer, it can be understood that the magnetic moment directions of the free layer and the reference layer can be in the xy plane and can be perpendicular to the xy plane. Plane, or at a certain angle of inclination to the xy plane. In the embodiments of the present application, the directions of the magnetic moments of the free layer and the reference layer are not specifically limited, as long as the directions of the magnetic moments of the free layer and the reference layer are arranged in parallel or anti-parallel.

此外，需要说明的是，在图2所示的磁性随机存储器中，为了示意简便，仅示出了用于连接第一层存储结构中位置对应的电压控制线的同层互连线202，用于连接第二层存储结构中位置对应的电压控制线的同层互连线202、用于连接第三层存储结构中位置对应的电压控制线的同层互连线202等并未在图2中示出。In addition, it should be noted that in the magnetic random access memory shown in FIG. 2, for simplicity of illustration, only the same-layer interconnection line 202 used to connect the voltage control line corresponding to the position in the first-layer storage structure is shown. The same layer interconnection line 202 connecting the voltage control line corresponding to the position in the second layer storage structure, the same layer interconnection line 202 connecting the voltage control line corresponding to the position in the third layer storage structure, etc. are not shown in FIG. 2 Shown in.

在图2所示的磁性随机存储器中，同层互连线202与电极线平行，但实际应用中，同层互连线202在连接每个存储块201中位置对应的电压控制线时，由于空间位置的限制，可能需要通过一些金属导线将电压控制线引出后再通过同层互连线202实现位置对应的电压控制线的互连，比如图2中与同层互连线202相连的虚线部分即可视为引出电压控制线的金属导线。In the magnetic random access memory shown in FIG. 2, the interconnection line 202 of the same layer is parallel to the electrode line, but in practical applications, the interconnection line 202 of the same layer connects the voltage control line corresponding to the position in each memory block 201 because The space location is limited, it may be necessary to lead the voltage control line through some metal wires and then realize the interconnection of the voltage control line corresponding to the position through the interconnection line 202 of the same layer, such as the dotted line connected to the interconnection line 202 of the same layer in FIG. 2 The part can be regarded as the metal wire leading out the voltage control line.

本申请实施例中，对于位置对应的电压控制线可以有如下理解：在图2所示的磁性随机存储器中，每个存储块201的结构是相同的，因而每个存储块201中包括的结构单元的数量以及电压控制线的数量都是相同的。在存储块201中，位于同一层存储结构、且在沿着y轴方向排列序号相同的电压控制线可以视为位置对应的电压控制线。In the embodiment of the present application, the voltage control line corresponding to the position can be understood as follows: In the magnetic random access memory shown in FIG. 2, the structure of each memory block 201 is the same, so the structure included in each memory block 201 The number of cells and the number of voltage control lines are the same. In the memory block 201, voltage control lines with the same sequence numbers arranged along the y-axis direction and located in the same layer of the memory structure can be regarded as voltage control lines with corresponding positions.

为了更准确地理解“位置对应的电压控制线”这一概念，将图2所示的磁性随机存储器中的同层互连线202以及图2中的文字标注略去，并为每个电压控制线进行编号，如图3所示。电压控制线标记为CT _mnk，m表示存储块的序号，n表示每个存储块中存储结构的层数序号，k表示每一层电极线上的电压控制线的序号。沿着y轴正方向，电压控制线的序号从1到k。那么，不难理解，在图3的示例中，CT ₁₁₁、CT ₂₁₁…CT _m11为位置对应的电压控制线，可以通过一个同层互连线201连接；CT ₁₁₂、CT ₂₁₂…CT _m12为位置对应的电压控制线，可以通过一个同层互连线201连接；CT _11k、CT _21k…CT _m1k为位置对应的电压控制线，可以通过一个同层互连线201连接；CT _1n1、CT _2n1…CT _mn1为位置对应的电压控制线，可以通过一个同层互连线201连接；CT _1n2、CT _2n2…CT _mn2为位置对应的电压控制线，可以通过一个同层互连线201连接；CT _1nk、CT _2nk…CT _mnk为位置对应的电压控制线，可以通过一个同层互连线201连接。 In order to understand the concept of "voltage control line corresponding to the position" more accurately, the same layer interconnection line 202 in the magnetic random access memory shown in FIG. 2 and the text in FIG. 2 are omitted, and each voltage control is omitted. The lines are numbered, as shown in Figure 3. The voltage control line is marked as CT _mnk , m represents the sequence number of the memory block, n represents the layer number of the storage structure in each memory block, and k represents the sequence number of the voltage control line on the electrode line of each layer. Along the positive direction of the y-axis, the voltage control lines are numbered from 1 to k. Then, it is not difficult to understand that in the example in Figure 3, CT ₁₁₁ , CT ₂₁₁ ...CT _m11 are the voltage control lines corresponding to the positions, which can be connected by a same-layer interconnection line 201; CT ₁₁₂ , CT ₂₁₂ ...CT _m12 are the positions The corresponding voltage control line can be connected through a same-layer interconnection line 201; CT _11k , CT _21k ...CT _m1k are the voltage control lines corresponding to the position, and can be connected through a same-layer interconnection line 201; CT _1n1 , CT _2n1 ... CT _mn1 is the voltage control line corresponding to the position, which can be connected by a same-layer interconnection line 201; CT _1n2 , CT _2n2 ...CT _mn2 is the voltage control line corresponding to the position, and can be connected by a same-layer interconnection line 201; CT _1nk , CT _2nk ... CT _mnk for the location corresponding to the voltage control line 201 can be connected by a same interconnect layer.

本申请实施例中，多组同层互连线中的每组同层互连线用于连接多层存储结构中的一层存储结构所对应的电压控制线。以图3为例，用于连接CT ₁₁₁～CT _m11的同层互连线、用于连接CT ₁₁₂～CT _m12的同层互连线……用于连接CT _11k～CT _m1k的同层互连线，这k个同层互连线可以视为一组同层互连线，这组同层互连线用于连接多层存储结构中的第一层存储结构所对应的电压控制线。 In the embodiment of the present application, each group of same-layer interconnection lines in the multiple sets of same-layer interconnection lines is used to connect a voltage control line corresponding to a storage structure of one layer in the multi-layer storage structure. Take Figure 3 as an example, _{the same-layer interconnection line used to connect CT 111} to CT _m11 , the same-layer interconnection line used to connect CT ₁₁₂ to CT _m12 ...the same-layer interconnection line used to connect CT _11k to CT _m1k The k same-layer interconnection lines can be regarded as a group of same-layer interconnection lines, and this same-layer interconnection line is used to connect the voltage control lines corresponding to the first-layer storage structure in the multi-layer storage structure.

通过同层互连线202将每个存储块201中位置对应的电压控制线连接起来，那么在向图2所示的磁性随机存储器中写入数据或者从图2所示的磁性随机存储器中读取数据时，通过位线向一个同层互连线202施加电压，即可通过该同层互连线202实现同时向位置对应的多个电压控制线施加电压，即位置对应的多个电压控制线共用一个位线。采用这种方式，可以减少位线在***电路平面的排线空间，通过较少的位线实现对磁性随机存储器中多层存储结构的寻址和访问。Connect the voltage control line corresponding to the position in each memory block 201 through the same layer interconnection line 202, then write data to the magnetic random access memory shown in FIG. 2 or read from the magnetic random access memory shown in FIG. When fetching data, apply a voltage to a same-layer interconnection 202 through the bit line, and then the same-layer interconnection 202 can simultaneously apply voltages to multiple voltage control lines corresponding to the position, that is, to control multiple voltages corresponding to the position. The lines share one bit line. In this way, the wiring space of the bit lines in the peripheral circuit plane can be reduced, and the addressing and accessing of the multilayer storage structure in the magnetic random access memory can be realized through fewer bit lines.

本申请实施例提供的磁性随机存储器在写入数据时利用了自旋轨道力矩(spin-orbit torque，SOT)效应和电压调控磁各向异性(voltage-controlled magnetic anisotropy，VCMA)效应，在读取数据时利用了隧穿磁电阻(tunnel magneto resistance，TMR)效应。The magnetic random access memory provided by the embodiments of the present application utilizes the spin-orbit torque (SOT) effect and the voltage-controlled magnetic anisotropy (VCMA) effect when writing data. The data uses the tunnel magneto resistance (TMR) effect.

SOT效应的原理是：在电极线中通入电流，将会产生向上(即向z轴正方向)扩散的自旋极化电流，进入MTJ的自由层中。当电流达到一定值(临界翻转电流密度)时，在自旋轨道相互作用力矩作用下，自由层的磁矩发生翻转，实现数据的写入。改变电极线中电流的方向，自旋流的极化方向发生改变，自由层的磁矩翻转方向也相应改变，实现不同数据的写入。VCMA效应的原理是：在MTJ两端施加偏置电压可以改变MTJ自由层与势垒层的界面电荷密度，从而改变自由层的垂直各向异性和矫顽力，进而降低MTJ的临界翻转电流密度。利用VCMA效应降低MTJ临界翻转电流密度的同时，在电极线中通入电流，在SOT效应和VCMA效应的共同作用下使得自由层中的磁矩发生翻转，实现数据的写入，这种写入方式可以显著降低数据写入的功耗。The principle of the SOT effect is: passing a current through the electrode line will generate a spin-polarized current that diffuses upward (that is, in the positive direction of the z-axis) and enters the free layer of the MTJ. When the current reaches a certain value (critical switching current density), the magnetic moment of the free layer is reversed under the action of the spin-orbit interaction torque to realize data writing. Changing the direction of the current in the electrode line changes the polarization direction of the spin current, and the direction of the magnetic moment reversal of the free layer is also changed accordingly to realize the writing of different data. The principle of the VCMA effect is: applying a bias voltage across the MTJ can change the interface charge density of the MTJ free layer and the barrier layer, thereby changing the vertical anisotropy and coercivity of the free layer, thereby reducing the critical switching current density of the MTJ . While using the VCMA effect to reduce the critical switching current density of the MTJ, a current is passed into the electrode line, and the magnetic moment in the free layer is reversed under the combined action of the SOT effect and the VCMA effect to realize data writing. This method can significantly reduce the power consumption of data writing.

实际应用中，电极线可以由重金属材料制成，或者由其他可以产生自旋流的材料制成，电极线也可以称为SOT电极线。In practical applications, the electrode wires can be made of heavy metal materials or other materials that can generate spin currents. The electrode wires can also be referred to as SOT electrode wires.

此外，为了避免在写入数据时，电极线上的电流流经MTJ，形成潜行通路(sneak path)，对写入数据的准确性产生影响，本申请实施例中，MTJ可以具有高电阻特性，例如MTJ的电阻值不低于100KΩ，使得MTJ的电阻值远大于电极线的电阻值，这样可以有效避免写入电流流经MTJ，降低sneak path的影响。In addition, in order to prevent the current on the electrode line from flowing through the MTJ when writing data, forming a sneak path, which will affect the accuracy of the written data, in the embodiment of the present application, the MTJ may have high resistance characteristics. For example, the resistance value of the MTJ is not less than 100KΩ, so that the resistance value of the MTJ is much larger than the resistance value of the electrode line, which can effectively prevent the writing current from flowing through the MTJ and reduce the influence of the sneak path.

TMR效应的原理是：当MTJ的自由层和参考层的磁矩平行排列时，MTJ为低电阻态；当自由层和参考层的磁矩反平行排列(即平行且方向相反)时，MTJ为高电阻态。高低电阻代表了两种不同的数据状态，例如0或1；根据MTJ为高阻态或低阻态可以读取出不同的数据。The principle of the TMR effect is: when the magnetic moments of the free layer and the reference layer of the MTJ are arranged in parallel, the MTJ is in a low resistance state; when the magnetic moments of the free layer and the reference layer are arranged in antiparallel (that is, parallel and opposite in direction), the MTJ is High resistance state. High and low resistance represent two different data states, such as 0 or 1. Different data can be read according to whether the MTJ is in a high-impedance state or a low-impedance state.

为了实现图2所示的磁性随机存储器的数据写入和读取，可以通过***电路向磁性随机存储器中的电压控制线施加电压以及向电极线通入电流。如前所述，对于图2所示的磁性随机存储器，在写入数据或读取数据时，可以通过***电路中的一个位线实现同时向位置对应的多个电压控制线施加相应电压。具体地，本申请实施例中，电压控制线、同层互连线以及***电路中的位线之间的连接方式可以有多种，下面介绍其中两种。In order to realize the data writing and reading of the magnetic random access memory shown in FIG. 2, a voltage can be applied to the voltage control line in the magnetic random access memory and a current can be applied to the electrode lines through a peripheral circuit. As mentioned above, for the magnetic random access memory shown in FIG. 2, when data is written or read, a bit line in the peripheral circuit can be used to simultaneously apply corresponding voltages to multiple voltage control lines corresponding to the positions. Specifically, in the embodiment of the present application, there may be multiple connection modes between the voltage control line, the same-layer interconnection line, and the bit line in the peripheral circuit, two of which are described below.

方式一method one

在方式一中，每个存储块201中位置对应的电压控制线中的一个电压控制线通过层间金属互连线与第一位线对应连接，第一位线用于向对应连接的电压控制线施加电压，第一位线与对应连接的电压控制线平行。In mode one, one of the voltage control lines corresponding to the position in each memory block 201 is connected to the first bit line through the interlayer metal interconnection line, and the first bit line is used to control the voltage of the corresponding connection. Voltage is applied to the lines, and the first bit line is parallel to the correspondingly connected voltage control line.

也就是说，在方式一中，在通过同一个同层互连线202连接的位置对应的多个电压控制线中，有一个电压控制线通过层间金属互连线与第一位线连接。That is, in the first method, among the multiple voltage control lines corresponding to the positions connected by the same same-layer interconnection line 202, one voltage control line is connected to the first bit line through the interlayer metal interconnection line.

比如，图3中，CT ₁₁₁、CT ₂₁₁…CT _m11中的一个电压控制线(比如CT ₁₁₁)通过层间金属互连线与第一位线连接，通过该第一位线可以向电压控制线CT ₁₁₁施加电压，由于CT ₁₁₁、CT ₂₁₁…CT _m11通过同层互连线202连接，因而通过该第一位线也可同时向CT ₂₁₁…CT _m11施加电压。 For example, in Figure 3, a voltage control line (such as CT ₁₁₁ _{) in CT 111} , CT ₂₁₁ ...CT _m11 is connected to the first bit line through an interlayer metal interconnection line, and the voltage control line can be connected to the voltage control line through the first bit line. CT ₁₁₁ applies voltage. Since CT ₁₁₁ , CT ₂₁₁ ... CT _{m11 are} connected by the same layer interconnection 202, voltage _{can also be applied to CT 211} ... CT _m11 at the same time through the first bit line.

再比如，图3中，CT _1nk、CT _2nk…CT _mnk中的一个电压控制线(比如CT _nnk)通过层间金属互连线与另一第一位线连接，通过该第一位线可以向电压控制线CT _nnk施加电压，由于CT _1nk、CT _2nk…CT _mnk通过同层互连线202连接，因而通过该第一位线可同时向CT _1nk、CT _2nk…CT _mnk施加电压。 As another example, in FIG. _{_{3, CT 1nk, CT 2nk ...}} CT mnk one control line voltage (such as _CT nnk) by a metal interconnect layer and the other between the first bit line is connected, through the first bit line to be voltage is applied to a voltage control line _CT nnk, since _CT 1nk, CT _2nk ... CT _mnk same layer via interconnect 202, thereby simultaneously applying a voltage to the _CT 1nk, CT _2nk ... CT _mnk through the first bit line.

方式二Way two

在方式二中，多组同层互连线202通过层间金属互连线分别与多组第一位线对应连接，多组第一位线分别用于向多组同层互连线202对应连接的电压控制线施加电压，多组第一位线与多个电压控制线平行。In the second method, multiple sets of same-layer interconnection lines 202 are respectively connected to multiple sets of first bit lines through interlayer metal interconnection lines, and the multiple sets of first bit lines are respectively used to correspond to multiple sets of same-layer interconnection lines 202. The connected voltage control lines apply voltage, and the first bit lines of the plurality of groups are parallel to the plurality of voltage control lines.

比如，图3中，用于连接CT ₁₁₁、CT ₂₁₁…CT _m11的同层互连线与第一位线1连接，通过该第一位线1可以同时向电压控制线CT ₁₁₁、CT ₂₁₁…CT _m11施加电压；用于连接CT ₁₁₂、CT ₂₁₂…CT _m12的同层互连线与第一位线2连接，通过该第一位线2可以同时向电压控制线CT ₁₁₂、CT ₂₁₂…CT _m12施加电压；……；用于连接CT _11k、CT _21k…CT _m1k的同层互连线与第一位线k连接，通过该第一位线k可以同时向电压控制线CT _11k、CT _21k…CT _m1k施加电压。第一位线1、第一位线2……第一位线k这k个第一位线可以视为一组第一位线，用于向第一层存储结构对应的电压控制线施加电压。 For example, in Fig. 3, _{the same-layer interconnection lines used to connect CT 111} , CT ₂₁₁ ...CT _m11 are connected to the first bit line 1, and the voltage control lines CT ₁₁₁ , CT ₂₁₁ ... CT _m11 applies voltage; the same-layer interconnection lines used to connect CT ₁₁₂ , CT ₂₁₂ ...CT _m12 are connected to the first bit line 2, through which the voltage control lines CT ₁₁₂ , CT ₂₁₂ ...CT can be simultaneously connected to the first bit line 2. _m12 applies voltage; ...; _{the same-layer interconnection line used to connect CT 11k} , CT _21k ...CT _m1k is connected to the first bit line k, and the voltage control lines CT _11k , CT _{21k can be simultaneously connected to the voltage control lines CT 11k and CT 21k through the first bit line k.} … CT _m1k applies voltage. The first bit line 1, the first bit line 2... the first bit line k These k first bit lines can be regarded as a group of first bit lines, which are used to apply voltage to the voltage control lines corresponding to the first layer storage structure .

方式二与方式一的不同之处在于，方式一中，是由电压控制线通过层间金属互连线与第一位线连接；而在方式二中，是由同层互连线202通过层间金属互连线与第一位线连接。无论采用方式一还是方式二，均可以实现位置对应的电压控制线、同层互连线以及第一位线之间的连接，因此对于方式一和方式二，数据的读取和写入的原理和具体过程并无差别。The difference between the second method and the first method is that in the first method, the voltage control line is connected to the first bit line through the interlayer metal interconnection line; and in the second method, the same layer interconnection line 202 passes through the layer The intermetallic interconnection line is connected to the first bit line. Regardless of the method 1 or the method 2, the connection between the voltage control line corresponding to the position, the interconnection line of the same layer and the first bit line can be realized. Therefore, for the method 1 and the method 2, the principle of data reading and writing There is no difference from the specific process.

为了实现磁性随机存储器中数据的写入和读取，图2所示的磁性随机存储器还可以包括多个字线，多个字线与电极线平行，多个字线与多个结构单元一一对应；每个存储块201还可以包括第二位线和第三位线，第二位线、第三位线与多个电压控制线之间相互平行；每个结构单元还包括第一晶体管和第二晶体管，第一晶体管的栅极以及第二晶体管的栅极均与第一晶体管所属的结构单元对应的字线连接，第一晶体管的源极和漏极中的一个端口与第二位线连接、另一个端口通过金属导线与电极线的第一端连接，第二晶体管的源极和漏极中的一个端口与第三位线连接、另一个端口通过金属导线与电极线的第二端连接。In order to realize the writing and reading of data in the magnetic random access memory, the magnetic random access memory shown in FIG. 2 may also include multiple word lines, the multiple word lines are parallel to the electrode lines, and the multiple word lines and multiple structural units are one by one. Corresponding; each memory block 201 may also include a second bit line and a third bit line, the second bit line, the third bit line and a plurality of voltage control lines are parallel to each other; each structural unit also includes a first transistor and The second transistor, the gate of the first transistor and the gate of the second transistor are all connected to the word line corresponding to the structural unit to which the first transistor belongs, and one port of the source and drain of the first transistor is connected to the second bit line Connection, the other port is connected to the first end of the electrode line through a metal wire, one port of the source and drain of the second transistor is connected to the third bit line, and the other port is connected to the second end of the electrode line through a metal wire connect.

其中，金属导线的材料可以与电极线的材料相同，也可以与电极线的材料不同。第一晶体管和第二晶体管可以是N型金属氧化物半导体(N metal oxide semiconductor，NMOS)晶体管。当然，第一晶体管和第二晶体管也可以是其他类型的晶体管，例如可以是P型金属氧化物半导体(P metal oxide semiconductor，NMOS)晶体管。本申请实施例对此不做具体限定。Among them, the material of the metal wire may be the same as the material of the electrode wire, or may be different from the material of the electrode wire. The first transistor and the second transistor may be N-type metal oxide semiconductor (NMOS) transistors. Of course, the first transistor and the second transistor may also be other types of transistors, such as P-type metal oxide semiconductor (P metal oxide semiconductor, NMOS) transistors. The embodiments of the present application do not specifically limit this.

不难看出，第一晶体管和第二晶体管的栅极分别与字线连接，字线可用于为第一晶体管和第二晶体管提供栅极偏置电压，以使得第一晶体管和第二晶体管导通。分别在第二位线和第三位线上施加不同的电压，可以使得电极线中有电流通过，即为电极线上的存储单元提供写入电流。此外，通过第一位线还可以向待写入存储单元对应的电压控制线施加偏置电压。It is not difficult to see that the gates of the first transistor and the second transistor are respectively connected to the word line, and the word line can be used to provide a gate bias voltage for the first transistor and the second transistor, so that the first transistor and the second transistor are turned on. . Applying different voltages on the second bit line and the third bit line respectively can make the electrode lines flow through, that is, provide write current for the memory cells on the electrode lines. In addition, a bias voltage can also be applied to the voltage control line corresponding to the memory cell to be written through the first bit line.

下面通过两个具体示例对包括上述字线、位线的磁性随机存储器进行介绍。The following introduces the magnetic random access memory including the above-mentioned word line and bit line through two specific examples.

示例一Example one

示例性地，第一位线的连接方式采用前述方式一时，图2所示的磁性随机存储器的一个具体示例可以如图4所示。Exemplarily, when the connection method of the first bit line adopts the aforementioned method 1, a specific example of the magnetic random access memory shown in FIG. 2 may be as shown in FIG. 4.

在图4所示的磁性随机存储器中包括四个存储块，分别为存储块1(Block1)、存储块2(Block2)、存储块3(Block3)和存储块4(Block4)，四个存储块沿着y轴方向排布。每个存储块包括沿着x轴方向排布的四个结构单元(cell)(图4中为了示意简便，每个存储块中仅画出了一个cell)。每个cell中包括四层存储结构，每层的SOT电极线上有四个存储单元，每个存储单元包括一个MTJ，MTJ的上端与电压控制线连接，下端与SOT电极线连接。每个cell中的四层SOT电极线通过金属导线连通。每个cell配置两个NMOS，用于给cell中所有层的SOT电极线并行通入电流。每个cell中的两个NMOS共用一个字线(word line，WL)，WL连接NMOS的栅极并控制其开关。WL沿着y方向延伸，4个Block共用WL。NMOS1和NMOS2的一端分别连接bl _m1和bl _m2(m为Block的序号)，bl _m1和bl _m2可以分别视为第二位线和第三位线，bl _m1和bl _m2沿着x方向延伸，同一个Block里的不同cell之间共用bl _m1和bl _m2。NMOS1和NMOS2的另一端通过金属导线连接到SOT电极线上。同层互连线将4个Block中相同层相同位置的电压控制线连通，其中，同层互连线的连接方式可以参见图5。 The magnetic random access memory shown in Figure 4 includes four storage blocks, namely storage block 1 (Block1), storage block 2 (Block2), storage block 3 (Block3) and storage block 4 (Block4), four storage blocks Arrange along the y-axis. Each storage block includes four structural units (cells) arranged along the x-axis direction (in FIG. 4 for simplicity of illustration, only one cell is drawn in each storage block). Each cell includes a four-layer storage structure, each layer has four storage cells on the SOT electrode line, and each storage cell includes an MTJ. The upper end of the MTJ is connected to the voltage control line, and the lower end is connected to the SOT electrode line. The four-layer SOT electrode lines in each cell are connected by metal wires. Each cell is configured with two NMOSs, which are used to pass current in parallel to the SOT electrode lines of all layers in the cell. The two NMOSs in each cell share a word line (WL), and the WL is connected to the gate of the NMOS and controls its switch. WL extends along the y direction, and 4 blocks share WL. One ends of NMOS1 and NMOS2 are respectively connected to bl _m1 and bl _m2 (m is the serial number of Block), bl _m1 and bl _m2 can be regarded as the second and third bit lines respectively, and bl _m1 and bl _m2 extend along the x direction, Different cells in the same block share bl _m1 and bl _m2 . The other ends of NMOS1 and NMOS2 are connected to the SOT electrode line through metal wires. The same-layer interconnection line connects the voltage control lines at the same layer and the same position in the four blocks. Among them, the connection mode of the same-layer interconnection line can be seen in Figure 5.

电压控制线标记为CT _mnk，m表示Block的序号，n表示层数序号，k表示每一层SOT电极线上的电压控制线的序号。为了示意简便，图5中仅展示了第一层的同层互连线和第四层的同层互连线的连接示意图，即：电压控制线(CT ₁₁₁，CT ₂₁₁，CT ₃₁₁，CT ₄₁₁)通过同层互连线H ₁₁相连，电压控制线(CT ₁₁₂，CT ₂₁₂，CT ₃₁₂，CT ₄₁₂)通过同层互连线H ₁₂相连，电压控制线(CT ₁₁₃，CT ₂₁₃，CT ₃₁₃，CT ₄₁₃)通过同层互连线H ₁₃相连，电压控制线(CT ₁₁₄，CT ₂₁₄，CT ₃₁₄，CT ₄₁₄)通过同层互连线H ₁₄相连；电压控制线(CT ₁₄₁，CT ₂₄₁，CT ₃₄₁，CT ₄₄₁)通过同层互连线H ₄₁相连，电压控制线(CT ₁₄₂，CT ₂₄₂，CT ₃₄₂，CT ₄₄₂)通过同层金属线H ₄₂相连，电压控制线(CT ₁₄₃，CT ₂₄₃，CT ₃₄₃，CT ₄₄₃)通过同层互连线H ₄₃相连，电压控制线(CT ₁₄₄，CT ₂₄₄，CT ₃₄₄，CT ₄₄₄)通过同层互连线H ₄₄相连。 The voltage control line is marked as CT _mnk , m represents the serial number of the Block, n represents the serial number of the layer, and k represents the serial number of the voltage control line on the SOT electrode line of each layer. For the sake of simplicity, Figure 5 only shows the connection diagrams of the same layer interconnection lines of the first layer and the fourth layer of the same layer interconnection lines, namely: voltage control lines (CT ₁₁₁ , CT ₂₁₁ , CT ₃₁₁ , CT ₄₁₁₎ ) Are connected through the same layer interconnection line H ₁₁ , and the voltage control lines (CT ₁₁₂ , CT ₂₁₂ , CT ₃₁₂ , CT ₄₁₂ ) are connected through the same layer interconnection line H ₁₂ , and the voltage control lines (CT ₁₁₃ , CT ₂₁₃ , CT ₃₁₃ , CT ₄₁₃₎ by the same layer as the interconnect ₁₃ is connected to H, the interconnect layer is connected by the same control voltage line H ₁₄ _{_{(CT 114, CT 214, CT}} 314, CT 414); a voltage control line (CT _141, CT _241, CT ₃₄₁ , CT ₄₄₁ ) are connected through the same layer interconnection line H ₄₁ , the voltage control lines (CT ₁₄₂ , CT ₂₄₂ , CT ₃₄₂ , CT ₄₄₂ ) are connected through the same layer metal line H ₄₂ , and the voltage control lines (CT ₁₄₃ , CT ₂₄₃ , CT ₃₄₃ , CT ₄₄₃ ) are connected through the same-layer interconnection H ₄₃ , and voltage control lines (CT ₁₄₄ , CT ₂₄₄ , CT ₃₄₄ , CT ₄₄₄ ) are connected through the same-layer interconnection H ₄₄ .

在图4所示的磁性随机存储器中，电压控制线通过层间金属互连线W _nk连接至NMOS所在的平面，并与相应的位线BL _nk连通，这样通过位线BL _nk就可以一次访问四个存储块中位置对应的4个MTJ，BL _nk可以视为前述第一位线。按照上述互连原则，位于Block1的第1层的4个电压控制线CT _11k，将通过4个层间金属互连线W _1k引到NMOS所在的平面，位于Block2的第2层的4个电压控制线CT _22k，将通过4个层间金属互连线W _2k引到NMOS所在的平面，位于Block3的第3层的4个电压控制线CT _33k，将通过4个层间金属互连线W _3k引到NMOS所在的平面，位于Block4的第4层的4个电压控制线CT _44k，将通过4个层间金属互连线W _4k引到NMOS所在的平面。在图4所示的磁性随机存储器中，4*4*4个电压控制线只需要16个第一位线BL来访问和控制。 In the magnetic random access memory shown in Figure 4, the voltage control line is _{connected to the plane where the NMOS is located through the interlayer metal interconnection line W nk} , and is connected to the corresponding bit line BL _nk , so that it can be accessed at one time through the bit line BL _nk _{The 4 MTJs and BL nk} corresponding to the positions in the four memory blocks can be regarded as the aforementioned first bit line. According to the above interconnection principle, the 4 voltage control lines CT _11k located on the first layer of Block1 will be led to the plane where the NMOS is located through the 4 interlayer metal interconnections W _1k , and the 4 voltages located on the second layer of Block2 The control line CT _22k will be led to the plane where the NMOS is located through the 4 interlayer metal interconnection lines W _2k _{. The 4 voltage control lines CT 33k} on the third layer of Block 3 will pass through the 4 interlayer metal interconnection lines W _{The 3k} leads to the plane where the NMOS is located, and the four voltage control lines CT _44k located on the fourth layer of Block4 will be led to the plane where the NMOS is located through the four interlayer metal interconnect lines W _4k. In the magnetic random access memory shown in FIG. 4, 4*4*4 voltage control lines only need 16 first bit lines BL to access and control.

示例二Example two

示例性地，第一位线的连接方式采用前述方式二时，图2所示的磁性随机存储器的一个具体示例可以如图6所示。Exemplarily, when the connection method of the first bit line adopts the foregoing method 2, a specific example of the magnetic random access memory shown in FIG. 2 may be as shown in FIG. 6.

在图6所示的磁性随机存储器中包括四个存储块，分别为存储块1(Block1)、存储块2(Block2)、存储块3(Block3)和存储块4(Block4)，四个存储块沿着y轴方向排布。每个存储块包括沿着x轴方向排布的四个结构单元(cell)(图4中为了示意简便，每个存储块中仅画出了一个cell)。每个cell中包括4层存储结构，每层的SOT电极线上有四个存储单元，每个存储单元包括一个MTJ，MTJ的上端与电压控制线连接，下端与SOT电极线连接。每个cell中的四层SOT电极线通过金属导线连通。The magnetic random access memory shown in Figure 6 includes four storage blocks, namely storage block 1 (Block1), storage block 2 (Block2), storage block 3 (Block3) and storage block 4 (Block4), four storage blocks Arrange along the y-axis. Each storage block includes four structural units (cells) arranged along the x-axis direction (in FIG. 4 for simplicity of illustration, only one cell is drawn in each storage block). Each cell includes a four-layer storage structure, each layer has four storage cells on the SOT electrode line, and each storage cell includes an MTJ. The upper end of the MTJ is connected to the voltage control line, and the lower end is connected to the SOT electrode line. The four-layer SOT electrode lines in each cell are connected by metal wires.

图6所示的磁性随机存储器中，同层互连线的排布位置与图4所示的磁性随机存储器中同层互连线的排布位置不同。在图6中，所有同层互连线被平移到了第一层存储结构所在的平面。为了示意简便，图6中仅示出了第一层同层互连线的排布，第4层同层互连线的排布可以如图7所示。In the magnetic random access memory shown in FIG. 6, the arrangement position of the same layer interconnection lines is different from the arrangement position of the same layer interconnection line in the magnetic random access memory shown in FIG. 4. In Figure 6, all interconnects of the same layer have been translated to the plane where the first-layer storage structure is located. For simplicity of illustration, FIG. 6 only shows the arrangement of the same layer interconnection lines of the first layer, and the arrangement of the same layer interconnection lines of the fourth layer may be as shown in FIG. 7.

从图6和图7可以看出，每一层存储结构对应的同层互连线均排布在第一层存储结构所在的平面，电压控制线与同层互连线之间通过金属导线连接(如图7中的虚线所示)。It can be seen from Figure 6 and Figure 7 that the same layer interconnection lines corresponding to each layer of the storage structure are arranged on the plane where the first layer storage structure is located, and the voltage control lines and the same layer interconnection lines are connected by metal wires. (As shown by the dotted line in Figure 7).

具体地，在图6和图7的示例中，电压控制线标记为CT _mnk，m表示Block的序号，n表示层数序号，k表示每一层SOT电极线上的电压控制线的序号。如图6所示，电压控制线(CT ₁₁₁，CT ₂₁₁，CT ₃₁₁，CT ₄₁₁)通过同层互连线H ₁₁相连，电压控制线(CT ₁₁₂，CT ₂₁₂，CT ₃₁₂，CT ₄₁₂)通过同层互连线H ₁₂相连，电压控制线(CT ₁₁₃，CT ₂₁₃，CT ₃₁₃，CT ₄₁₃)通过同层互连线H ₁₃相连，电压控制线(CT ₁₁₄，CT ₂₁₄，CT ₃₁₄，CT ₄₁₄)通过同层互连线H ₁₄相连，这4根同层互连线H _1k通过金属导线平移至第一层存储结构所在的平面，并沿着x轴的方向依次排开。同理如图7所示，第4层的电压控制线(CT _14k，CT _24k，CT _34k，CT _44k)也是通过4根同层互连线H _4k连接，这4根同层互连线H _4k通过金属导线平移至第一层存储结构所在的平面，并沿着x轴的方向依次排开。 Specifically, in the examples of FIGS. 6 and 7, the voltage control line is marked as CT _mnk , m represents the sequence number of Block, n represents the layer number sequence number, and k represents the sequence number of the voltage control line on the SOT electrode line of each layer. As shown in Figure 6, the voltage control lines (CT ₁₁₁ , CT ₂₁₁ , CT ₃₁₁ , CT ₄₁₁ ) are connected through the same layer interconnection line H ₁₁ , and the voltage control lines (CT ₁₁₂ , CT ₂₁₂ , CT ₃₁₂ , CT ₄₁₂ ) are connected through the same layer. The layer interconnection lines H _{12 are} connected, and the voltage control lines (CT ₁₁₃ , CT ₂₁₃ , CT ₃₁₃ , CT ₄₁₃ ) are connected through the same layer interconnection line H ₁₃ , and the voltage control lines (CT ₁₁₄ , CT ₂₁₄ , CT ₃₁₄ , CT ₄₁₄ ) layer ₁₄ is connected through the same interconnection line H, which the same layer as the interconnect 4 H _1k metal wire to move through the flat plane memory structure where a first layer, and arranged in order along the x-axis direction. Similarly, as shown in Figure 7, the voltage control lines (CT _14k , CT _24k , CT _34k , CT _44k ) of the fourth layer are also connected by four same-layer interconnection lines H _4k , and these four same-layer interconnection lines H _{The 4k} is translated to the plane where the first-layer storage structure is located through the metal wire, and is arranged in sequence along the x-axis direction.

此外，如图8所示，四层存储结构的16根同层互连线H _nk都通过金属导线平移至了第一层存储结构所在的平面，选中其中的一根同层互连线就对应选中了与之连接的四个电压控制线。将上述16根同层互连线H _nk分别通过层间金属互连线W _nk依次错开连接至NMOS所在的平面，与相应的位线BL _nk相连。位线BL _nk连通对应的同层互连线H _nk，进而可以一次控制被该同层互连线连通的4根电压控制线。上述16根位线BL _nk在NMOS所在平面的y轴方向上依次排开，排列的间距可以根据MRAM的制造工艺进行调整。 In addition, as shown in Figure 8, the 16 same-layer interconnection lines H _{nk of the} four-layer storage structure are all translated to the plane where the first-layer storage structure is located through metal wires, and one of the same-layer interconnection lines corresponds to The four voltage control lines connected to it are selected. The above-mentioned 16 same-layer interconnection lines H _nk are respectively staggered and connected to the plane where the NMOS is located through the interlayer metal interconnection line W _nk, _{and are connected to the corresponding bit line BL nk} . The bit line BL _{nk is} connected to the corresponding same-layer interconnection line H _nk , and then the four voltage control lines connected by the same-layer interconnection line can be controlled at one time. The above-mentioned 16 bit lines BL _nk are sequentially arranged in the y-axis direction of the plane where the NMOS is located, and the arrangement pitch can be adjusted according to the manufacturing process of the MRAM.

此外，如图8所示，在每个cell中配置两个NMOS，用于给cell中所有层的SOT电极线并行通入电流(图8中仅示出了Block1中为cell配置的两个NMOS)。每个cell中的两个NMOS共用一个WL，WL连接NMOS的栅极并控制其开关。WL沿着y方向延伸，4个Block共用WL。NMOS1和NMOS2的一端分别连接bl _m1和bl _m2(m为Block的序号，图8中仅示出了Block1中的bl ₁₁和bl ₁₂，其他Block中的bl _m1和bl _m2与Block1类似)，bl _m1和bl _m2可以分别视为第二位线和第三位线，bl _m1和bl _m2沿着x方向延伸，同一个Block里的不同cell之间共用bl _m1和bl _m2。NMOS1和NMOS2的另一端通过金属导线连接到SOT电极线上。 In addition, as shown in Figure 8, two NMOSs are configured in each cell to pass current in parallel to the SOT electrode lines of all layers in the cell (Figure 8 only shows the two NMOSs configured for the cell in Block1. ). The two NMOSs in each cell share a WL, which is connected to the gate of the NMOS and controls its switch. WL extends along the y direction, and 4 blocks share WL. One ends of NMOS1 and NMOS2 are respectively connected to bl _m1 and bl _m2 (m is the serial number of Block, only bl ₁₁ and bl ₁₂ in Block 1 _{are shown in Figure 8, bl m1} and bl _m2 in other blocks are similar to Block 1), bl _m1 and bl _m2 can be regarded as the second bit line and the third bit line, respectively, bl _m1 and bl _m2 _{extend along the x direction, and bl m1} and bl _m2 are shared between different cells in the same block. The other ends of NMOS1 and NMOS2 are connected to the SOT electrode line through metal wires.

需要说明的是，上述示例一和示例二仅为两个具体示例，实际应用中，本申请实施例提供的磁性随机存储器中包括的存储块的数量、每个存储块中包括的结构单元的数量、每个结构单元包括的存储结构的层数以及每层SOT电极线上包括的存储单元的个数均不做具体限定。It should be noted that the foregoing example 1 and example 2 are only two specific examples. In actual applications, the number of memory blocks included in the magnetic random access memory provided in the embodiments of the present application and the number of structural units included in each memory block are The number of layers of the memory structure included in each structural unit and the number of memory cells included in each layer of the SOT electrode line are not specifically limited.

前面已经介绍了本申请实施例提供的磁性随机存储器的数据写入和读取的原理，下面对数据写入和读取的具体过程进行介绍。如前所述，采用前述方式一和方式二中同层互连线的不同排布方式时，数据读取和写入的原理和具体过程并无差别。The principle of data writing and reading of the magnetic random access memory provided in the embodiment of the present application has been introduced above, and the specific process of data writing and reading will be introduced below. As mentioned above, there is no difference in the principle and specific process of data reading and writing when the different arrangements of the same layer interconnection lines in the aforementioned method 1 and method 2 are used.

本申请实施例中，可以通过在第一位线、第二位线、第三位线以及字线上施加相应电压，实现向磁性随机存储器中任一存储单元写入数据。具体地，在向磁性随机存储器写入数据时，待写入存储单元所属的结构单元对应的字线分别向待写入存储单元所属的结构单元中的第一晶体管和第二晶体管施加栅极偏置电压；待写入存储单元所属的存储块201中的第二位线和第三位线中的一个位线施加写入电压、另一个位线接地；与待写入存储单元连接的电压控制线对应的第一位线施加偏置电压。In the embodiment of the present application, data can be written to any memory cell in the magnetic random access memory by applying corresponding voltages on the first bit line, the second bit line, the third bit line, and the word line. Specifically, when writing data to the magnetic random access memory, the word line corresponding to the structural unit to which the memory cell to be written belongs applies gate bias to the first transistor and the second transistor in the structural unit to which the memory cell to be written belongs, respectively. Set voltage; one of the second bit line and the third bit line in the memory block 201 to which the memory cell to be written belongs is applied with the write voltage, and the other bit line is grounded; the voltage control connected to the memory cell to be written A bias voltage is applied to the first bit line corresponding to the line.

为了向磁性随机存储器中的某一个特定的待写入存储单元写入数据，可以通过在第一位线、第二位线和第三位线上施加不同的电压实现待写入存储单元的选中：与待写入存储单元连接的电压控制线对应的第一位线施加第一偏置电压，其他第一位线施加第二偏置电压，可以实现向多个存储块中与待写入存储单元位置相同的存储单元的电压控制线上同时施加第一偏置电压。进一步地，待写入存储单元所属的存储块201中的第二位线和第三位线中的一个位线施加写入电压、另一个位线接地，非写入存储单元所属的存储块201中的第二位线和第三位线均接地，即可选中待写入存储单元。In order to write data to a specific memory cell to be written in the magnetic random access memory, the selection of the memory cell to be written can be achieved by applying different voltages on the first bit line, the second bit line and the third bit line. : The first bit line corresponding to the voltage control line connected to the memory cell to be written is applied with a first bias voltage, and other first bit lines are applied with a second bias voltage. The first bias voltage is simultaneously applied to the voltage control lines of the memory cells with the same cell position. Further, one of the second bit line and the third bit line in the memory block 201 to which the memory cell to be written belongs is applied with a write voltage, the other bit line is grounded, and the memory block 201 to which the non-write memory cell belongs The second bit line and the third bit line in both are grounded, and the memory cell to be written can be selected.

此外，字线向第一晶体管和第二晶体管施加栅极偏置电压，第一晶体管和第二晶体管导通；在第二位线上施加写入电压、第三位线接地的情况下，电流通过第一晶体管和金属导线流入待写入存储单元所属的结构单元中的所有电极线，然后经金属导线和第二晶体管流入第三位线，在这种情况下，相当于第一晶体管的源极与第二位线连接、漏极与金属导线连接，第二晶体管的源极与金属导线连接、漏极与第三位线连接；在第三位线上施加写入电压、第二位线接地的情况下，电流通过第二晶体管和金属导线流入待写入存储单元所属的结构单元中的所有电极线(电流方向与前述第二位线上施加写入电压、第三位线接地的情况下的电流方向相反)，然后经金属导线和第一晶体管流入第二位线，在这种情况下，相当于第二晶体管的源极与第三位线连接、漏极与金属导线连接，第一晶体管的源极与金属导线连接、漏极与第二位线连接。当电极线中通入不同方向的电流时，利用前述SOT效应和VCMA效应，可以向电极线连接的存储单元中写入不同的数据(例如0或1)。In addition, the word line applies a gate bias voltage to the first transistor and the second transistor, and the first transistor and the second transistor are turned on; when the write voltage is applied to the second bit line and the third bit line is grounded, the current It flows through the first transistor and the metal wire into all the electrode lines in the structural unit to which the memory cell to be written belongs, and then flows into the third bit line through the metal wire and the second transistor. In this case, it is equivalent to the source of the first transistor. The electrode is connected to the second bit line, the drain is connected to the metal wire, the source of the second transistor is connected to the metal wire, and the drain is connected to the third bit line; the write voltage and the second bit line are applied to the third bit line In the case of grounding, the current flows through the second transistor and the metal wire into all the electrode lines in the structural unit to which the memory cell to be written belongs (the current direction is the same as the case where the write voltage is applied to the second bit line and the third bit line is grounded. The direction of the current is opposite), and then flows into the second bit line through the metal wire and the first transistor. In this case, the source of the second transistor is connected to the third bit line, and the drain is connected to the metal wire. The source of a transistor is connected with the metal wire, and the drain is connected with the second bit line. When currents in different directions are applied to the electrode lines, using the aforementioned SOT effect and VCMA effect, different data (for example, 0 or 1) can be written into the memory cells connected to the electrode lines.

以图6～图8所示的磁性随机存储器为例，当要向该磁性随机存储器的第m个Block中的第n层存储层的第k个存储单元(以下称为待写入存储单元)写入信息时，首先通过列地址解码电路(或行地址解码电路)找到待写入存储单元所在cell的WL，选通WL，则与该WL相连的4个cell中的8个NMOS晶体管开启，这4个cell沿Y方向并排分别属于4个Block，如图8所示。通过行地址解码电路(或列地址解码电路)找到待写入存储单元的电压控制线CT _mnk所连通的第一位线BL _nk，电平控制电路在该BL _nk上施加第一偏置电压(写入电压)，在其他BL上施加第二偏置电压(非写入电压)。与此同时，通过次级地址解码电路和电平控制电路在待写入存储单元所属cell的bl _m1和bl _m2上分别施加第三偏置电压和接地，使得该cell中的SOT电极线上有正向电流通过，其他cell的bl _m1和bl _m2均接地。这样在电压控制线施加的偏置电压和SOT电极线通入的电流的共同作用下，待写入存储单元的自由层磁矩发生翻转，其他非写入存储单元的磁矩方向不变，完成信息的写入。改变SOT电极线中电流方向，例如将待写入存储单元所属cell的bl _m1和bl _m2分别接地和接第三偏置电压，则待写入存储单元的自由层磁矩翻转方向反向，从而写入不同的信息。 Take the magnetic random access memory shown in Figures 6 to 8 as an example, when it is necessary to write the kth memory cell of the nth storage layer in the mth Block of the magnetic random access memory (hereinafter referred to as the memory cell to be written) When writing information, first find the WL of the cell where the memory cell to be written is located through the column address decoding circuit (or row address decoding circuit), and strobe the WL, then 8 NMOS transistors in the 4 cells connected to the WL are turned on, These 4 cells are arranged side by side along the Y direction and belong to 4 Blocks respectively, as shown in Figure 8. Found to be the first bit line by a row address decoder circuit (or a column address decoder circuit) voltage written in the memory cell controls the communication line CT _mnk BL _nk, the level control circuit applies a first bias voltage on the BL _nk ( Write voltage), and apply a second bias voltage (non-write voltage) to other BLs. _{At the same time, the third bias voltage and ground are applied to the bl m1} and bl _m2 of the cell to which the memory cell belongs through the secondary address decoding circuit and the level control circuit, respectively, so that the SOT electrode line in the cell has The forward current passes, and bl _m1 and bl _{m2 of} other cells are all grounded. In this way, under the combined action of the bias voltage applied by the voltage control line and the current through the SOT electrode line, the free layer magnetic moment of the memory cell to be written is reversed, and the direction of the magnetic moment of the other non-write memory cells remains unchanged. Information writing. Change the direction of the current in the SOT electrode line, for example, connect the bl _m1 and bl _{m2 of the} cell to which the memory cell to be written belongs to ground and connect to the third bias voltage respectively, and the direction of the free layer magnetic moment of the memory cell to be written is reversed, thereby Write different information.

其中，电平控制电路、行地址解码电路、列地址解码电路和次级地址解码电路可以视为图1中所示的控制电路。Among them, the level control circuit, the row address decoding circuit, the column address decoding circuit, and the secondary address decoding circuit can be regarded as the control circuit shown in FIG. 1.

本申请实施例中，可以通过在第一位线、第二位线、第三位线以及字线上施加相应电压，实现从磁性随机存储器中读取数据。本申请实施例中，数据读取时是以结构单元为单位的，即一次读取一个结构单元中的所有数据。具体地，在从磁性随机存储器读取数据时，待读取结构单元对应的字线分别向待读取结构单元中的第一晶体管和第二晶体管施加栅极偏置电压；磁性随机存储器中的所有第一位线施加读取电压；待读取结构单元所属的存储块201中的第二位线和第三位线接地。In the embodiment of the present application, data can be read from the magnetic random access memory by applying corresponding voltages on the first bit line, the second bit line, the third bit line, and the word line. In the embodiment of the present application, the structure unit is used as the unit when data is read, that is, all data in one structure unit is read at a time. Specifically, when reading data from the magnetic random access memory, the word line corresponding to the structure unit to be read applies gate bias voltages to the first transistor and the second transistor in the structure unit to be read; A read voltage is applied to all the first bit lines; the second bit line and the third bit line in the memory block 201 to which the structural unit to be read belongs are grounded.

为了读取磁性随机存储器中某一结构单元中的数据，可以通过在第一位线、第二位线和第三位线上施加不同的电压实现对待读取结构单元的选中：待读取结构单元对应的字线分别向待读取结构单元中的第一晶体管和第二晶体管施加栅极偏置电压，第一晶体管和第二晶体管导通；同时，磁性随机存储器中的所有第一位线施加读取电压，此时相当于选中了多个存储块中与待读取结构单元位置相同的所有结构单元；此外，待读取结构单元所属的存储块201中的第二位线和第三位线接地，从而为待读取结构单元提供接地回路，非读取结构单元所属的存储块201中的第二位线和第三位线施加读取电压，即实现了待读取结构单元的选中。由于所有第一位线均施加读取电压，相当于与待读取结构单元中所有存储单元所连接的电压控制线上均施加读取电压，使得待读取结构单元中的每个存储单元都包含在一条独立的读出回路中，那么利用前述TMR效应，可以实现待读取结构单元的数据读取。In order to read the data in a certain structural unit in the magnetic random access memory, the selection of the structural unit to be read can be achieved by applying different voltages on the first bit line, the second bit line and the third bit line: the structure to be read The word line corresponding to the cell applies gate bias voltage to the first transistor and the second transistor in the structure cell to be read, and the first transistor and the second transistor are turned on; at the same time, all the first bit lines in the magnetic random access memory Applying the read voltage at this time is equivalent to selecting all the structural units in the multiple memory blocks that have the same position as the structural unit to be read; in addition, the second bit line and the third bit line in the memory block 201 to which the structural unit to be read belongs are selected. The bit line is grounded to provide a ground loop for the structure unit to be read. The second bit line and the third bit line in the memory block 201 to which the non-read structure unit belongs are applied with a read voltage, that is, the structure unit to be read is realized Selected. Since all the first bit lines are applied with the read voltage, it is equivalent to applying the read voltage on the voltage control line connected to all the memory cells in the structure unit to be read, so that each memory cell in the structure unit to be read is Included in an independent readout loop, the aforementioned TMR effect can be used to read data from the structural unit to be read.

具体地，该磁性随机存储器还可以包括：分别与磁性随机存储器中的所有第一位线一一对应连接的多个放大器，多个放大器中的每个放大器用于读取对应连接的第一位线所接收的反馈信息。Specifically, the magnetic random access memory may further include: a plurality of amplifiers respectively connected to all the first bit lines in the magnetic random access memory in a one-to-one correspondence, and each amplifier of the plurality of amplifiers is used to read the correspondingly connected first bit line. The feedback information received by the line.

存储单元中数据的读取利用TMR效应。在从磁性随机存储器读取数据时，在与待读取结构单元中所有存储单元所连接的电压控制线上施加读取电压后，所有第一位线均会接收到反馈信息，该反馈信息反应了待读取结构单元中所有存储单元中存储的数据。The reading of data in the memory cell utilizes the TMR effect. When reading data from the magnetic random access memory, after applying the read voltage on the voltage control line connected to all the memory cells in the structure unit to be read, all the first bit lines will receive feedback information, which reflects the feedback information. The data stored in all the storage units in the structural unit to be read is obtained.

其中，反馈信息可以是流过存储单元的电流、电荷量等信息，在与待读取结构单元中所有存储单元所连接的电压控制线上均施加相同的读取电压的情况下，存储单元处于不同阻态时，反馈的电流或电荷量不同。具体地，每个放大器可以通过将存储单元的反馈信息(例如电流、电荷量、充放电时间)与参考值做比较，来判断该存储单元处于高阻态还是低阻态，进而确定该存储单元中存储的数据。Wherein, the feedback information can be information such as the current flowing through the memory cell, the amount of charge, etc., when the same read voltage is applied to the voltage control line connected to all memory cells in the structure unit to be read, the memory cell is in In different resistance states, the feedback current or charge is different. Specifically, each amplifier can determine whether the memory cell is in a high-impedance state or a low-impedance state by comparing the feedback information (such as current, charge amount, charge and discharge time) of the memory cell with a reference value, and then determine the memory cell Data stored in.

以图6～图8所示的磁性随机存储器为例，当要读取某个cell(以下称为待读取cell)中的数据时，首先通过列地址解码电路(或行地址解码电路)找到待读取cell的WL，选通WL，则与该WL相连的4个cell中的8个NMOS晶体管开启，这4个cell沿y轴方向排布，并分别属于4个Block。通过电平控制电路在所有BL上施加读电压V1，并将待读取cell的bl _m1和bl _m2均接地，WL选通的其他3个非读取cell的bl _m1和bl _m2均接电压V1。这样只有待读取cell中的存储单元上有读电流流过，非读取cell中的存储单元上无读电流流过，即完成对待读取cell中的所有存储单元数据的读取。 Take the magnetic random access memory shown in Figure 6 to Figure 8 as an example, when you want to read the data in a certain cell (hereinafter referred to as the cell to be read), first find it through the column address decoding circuit (or row address decoding circuit) When the WL of the cell to be read and the WL are strobed, 8 NMOS transistors in the 4 cells connected to the WL are turned on. The 4 cells are arranged along the y-axis direction and belong to 4 blocks respectively. And bl _m2 bl _m1 through level control circuit is applied in all read BL voltages V1, and the cell to be read and bl _m2 bl _m1 are grounded, WL gating other non-read cell 3 are connected to the voltage V1 . In this way, only the memory cells in the cell to be read have read current flowing, and no read current flows in the memory cells in the non-read cell, that is, the reading of all memory cell data in the cell to be read is completed.

其中，电平控制电路、行地址解码电路和列地址解码电路可以视为图1中所示的控制电路。Among them, the level control circuit, the row address decoding circuit, and the column address decoding circuit can be regarded as the control circuit shown in FIG. 1.

综上，采用本申请实施例提供的磁性随机存储器，由于存储阵列是3D的，该方案相比现有技术中的2D阵列，可以在保证存储单元的热稳定的前提下，通过垂直方向存储单元的叠加增加面存储密度，进而提高磁性随机存储器的存储密度。此外，由于在该磁性随机存储器中，通过多组同层互连线将每个存储块中位置对应的电压控制线连接起来，因而在向磁性随机存储器中写入数据或者从磁性随机存储器中读取数据时，可以通过一个同层互连线实现同时向位置对应的多个电压控制线施加相应电压，从而减少位线在***电路平面的排线空间，通过较少的位线实现对磁性随机存储器中多层存储结构的寻址和访问。In summary, using the magnetic random access memory provided by the embodiments of the present application, since the storage array is 3D, compared with the 2D array in the prior art, this solution can ensure the thermal stability of the storage unit through the vertical direction of the storage unit. The superposition increases the surface storage density, thereby increasing the storage density of the magnetic random access memory. In addition, because in the magnetic random access memory, the voltage control lines corresponding to the positions in each memory block are connected through multiple sets of the same layer interconnection lines, so data is written to or read from the magnetic random access memory. When fetching data, it is possible to simultaneously apply corresponding voltages to multiple voltage control lines corresponding to the position through an interconnection line of the same layer, thereby reducing the wiring space of the bit line in the peripheral circuit plane, and achieving random magnetic resistance through fewer bit lines. Addressing and accessing the multi-level storage structure in the memory.

基于同一发明构思，本申请实施例还提供一种电子设备。参见图9，该电子设备包括处理器901以及与处理器耦合的磁性随机存储器902，磁性随机存储器902可以是图2所示的磁性随机存储器。Based on the same inventive concept, the embodiments of the present application also provide an electronic device. Referring to FIG. 9, the electronic device includes a processor 901 and a magnetic random access memory 902 coupled with the processor. The magnetic random access memory 902 may be the magnetic random access memory shown in FIG. 2.

具体地，处理器901可以调用磁性随机存储器902中存储的软件程序，以执行相应的方法，实现电子设备的相应功能。Specifically, the processor 901 may call a software program stored in the magnetic random access memory 902 to execute a corresponding method to realize the corresponding function of the electronic device.

显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the scope of the embodiments of the present application. In this way, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

一种磁性随机存储器，其特征在于，包括多个存储块以及多组同层互连线；A magnetic random access memory, which is characterized in that it comprises a plurality of memory blocks and a plurality of sets of same-layer interconnection lines;

所述多个存储块中的每个存储块包括多个结构单元以及多个电压控制线；所述多个结构单元中的每个结构单元包括依次堆叠的多层存储结构，所述多层存储结构中的每层存储结构包括电极线以及设置于所述电极线上的多个存储单元，所述多个存储单元中的每个存储单元包括一个磁性隧道结，所述每个存储单元的一端与所述电极线连接，另一端与所述多个电压控制线中的一个电压控制线连接；Each of the plurality of memory blocks includes a plurality of structural units and a plurality of voltage control lines; each of the plurality of structural units includes a multilayer memory structure stacked in sequence, and the multilayer memory Each layer of the memory structure in the structure includes an electrode line and a plurality of memory cells arranged on the electrode line, each memory cell of the plurality of memory cells includes a magnetic tunnel junction, and one end of each memory cell Connected to the electrode line, and the other end connected to one voltage control line of the plurality of voltage control lines;

其中，所述多个存储块沿着所述电极线的方向平行排列，所述多组同层互连线与所述电极线平行，所述多组同层互连线用于连接所述每个存储块中位置对应的电压控制线。Wherein, the plurality of memory blocks are arranged in parallel along the direction of the electrode lines, the multiple sets of same-layer interconnection lines are parallel to the electrode lines, and the multiple sets of same-layer interconnection lines are used to connect each The voltage control line corresponding to the position in each memory block.
如权利要求1所述的磁性随机存储器，其特征在于，所述多组同层互连线中的每组同层互连线用于连接所述多层存储结构中的一层存储结构所对应的电压控制线。The magnetic random access memory according to claim 1, wherein each group of the same layer interconnection lines in the plurality of sets of same layer interconnection lines is used to connect the corresponding layer of the storage structure in the multilayer storage structure. The voltage control line.
如权利要求1或2所述的磁性随机存储器，其特征在于，所述多个电压控制线平行；所述多个结构单元所在的平面平行，且所述多个结构单元中每个结构单元所在的平面与所述多个电压控制线垂直。The magnetic random access memory of claim 1 or 2, wherein the multiple voltage control lines are parallel; the planes on which the multiple structural units are located are parallel, and each structural unit of the multiple structural units is located The plane of is perpendicular to the plurality of voltage control lines.
如权利要求1～3任一项所述的磁性随机存储器，其特征在于，所述每个存储块中位置对应的电压控制线中的一个电压控制线通过层间金属互连线与第一位线对应连接，所述第一位线用于向对应连接的电压控制线施加电压，所述第一位线与对应连接的电压控制线平行。The magnetic random access memory according to any one of claims 1 to 3, wherein one of the voltage control lines corresponding to the position in each memory block is connected to the first bit through an interlayer metal interconnection line. The lines are correspondingly connected, the first bit line is used to apply a voltage to the correspondingly connected voltage control line, and the first bit line is parallel to the correspondingly connected voltage control line.
如权利要求1～3任一项所述的磁性随机存储器，其特征在于，所述多组同层互连线通过层间金属互连线分别与多组第一位线对应连接，所述多组第一位线分别用于向所述多组同层互连线对应连接的电压控制线施加电压，所述多组第一位线与所述多个电压控制线平行。The magnetic random access memory according to any one of claims 1 to 3, wherein the multiple sets of same-layer interconnection lines are respectively connected to multiple sets of first bit lines through interlayer metal interconnection lines, and the multiple The first bit lines of the group are respectively used for applying voltage to the voltage control lines corresponding to the multiple groups of the same layer interconnection lines, and the first bit lines of the multiple groups are parallel to the voltage control lines.
如权利要求4或5所述的磁性随机存储器，其特征在于，还包括：多个字线，所述多个字线与所述电极线平行，所述多个字线与所述多个结构单元一一对应；The magnetic random access memory according to claim 4 or 5, further comprising: a plurality of word lines, the plurality of word lines are parallel to the electrode lines, and the plurality of word lines are connected to the plurality of structures Unit one to one correspondence;

所述每个存储块还包括第二位线和第三位线，所述第二位线、所述第三位线与所述多个电压控制线之间相互平行；Each of the memory blocks further includes a second bit line and a third bit line, and the second bit line, the third bit line, and the plurality of voltage control lines are parallel to each other;

所述每个结构单元还包括第一晶体管和第二晶体管，所述第一晶体管的栅极以及所述第二晶体管的栅极均与所述第一晶体管所属的结构单元对应的字线连接，所述第一晶体管的源极和漏极中的一个端口与所述第二位线连接、另一个端口通过金属导线与所述电极线的第一端连接，所述第二晶体管的源极和漏极中的一个端口与所述第三位线连接、另一个端口通过金属导线与所述电极线的第二端连接。Each of the structural units further includes a first transistor and a second transistor, and the gate of the first transistor and the gate of the second transistor are both connected to the word line corresponding to the structural unit to which the first transistor belongs, One port of the source and drain of the first transistor is connected to the second bit line, the other port is connected to the first end of the electrode line through a metal wire, and the source of the second transistor is connected to the first end of the electrode line. One port in the drain is connected to the third bit line, and the other port is connected to the second end of the electrode line through a metal wire.
如权利要求6所述的磁性随机存储器，其特征在于，在向所述磁性随机存储器写入数据时，待写入存储单元所属的结构单元对应的字线分别向所述待写入存储单元所属的结构单元中的第一晶体管和第二晶体管施加栅极偏置电压；所述待写入存储单元所属的存储块中的第二位线和第三位线中的一个位线施加写入电压、另一个位线接地；与所述待写入存储单元连接的电压控制线对应的第一位线施加偏置电压。7. The magnetic random access memory according to claim 6, wherein when data is written to the magnetic random access memory, the word lines corresponding to the structural unit to which the memory cell to be written belongs are respectively assigned to the memory cell to be written. The first transistor and the second transistor in the structural unit apply gate bias voltage; one of the second bit line and the third bit line in the memory block to which the memory cell to be written belongs is applied with a write voltage The other bit line is grounded; the first bit line corresponding to the voltage control line connected to the memory cell to be written is applied with a bias voltage.
如权利要求6所述的磁性随机存储器，其特征在于，在从所述磁性随机存储器读取数据时，待读取结构单元对应的字线分别向所述待读取结构单元中的第一晶体管和第二晶体管施加栅极偏置电压；所述磁性随机存储器中的所有第一位线施加读取电压；所述待读取结构单元所属的存储块中的第二位线和第三位线接地。7. The magnetic random access memory of claim 6, wherein when data is read from the magnetic random access memory, the word lines corresponding to the structure unit to be read are directed to the first transistor in the structure unit to be read. And the second transistor apply a gate bias voltage; all the first bit lines in the magnetic random access memory apply a read voltage; the second bit line and the third bit line in the memory block to which the structure unit to be read belongs Grounded.
如权利要求8所述的磁性随机存储器，其特征在于，还包括：8. The magnetic random access memory of claim 8, further comprising:

分别与所述磁性随机存储器中的所有第一位线一一对应连接的多个放大器，所述多个放大器中的每个放大器用于读取对应连接的第一位线所接收的反馈信息。A plurality of amplifiers respectively connected to all the first bit lines in the magnetic random access memory in a one-to-one correspondence, and each amplifier of the plurality of amplifiers is used for reading the feedback information received by the correspondingly connected first bit line.
如权利要求1～9任一项所述的磁性随机存储器，其特征在于，所述每个磁性隧道结包括依次堆叠的自由层、势垒层和参考层，所述自由层与所述电极线连接，所述参考层与电压控制线连接。The magnetic random access memory according to any one of claims 1-9, wherein each magnetic tunnel junction includes a free layer, a barrier layer, and a reference layer stacked in sequence, and the free layer and the electrode line Connected, the reference layer is connected with the voltage control line.
如权利要求1～10任一项所述的磁性随机存储器，其特征在于，所述每个磁性隧道结的电阻值大于或等于100KΩ。The magnetic random access memory according to any one of claims 1 to 10, wherein the resistance value of each magnetic tunnel junction is greater than or equal to 100KΩ.
一种电子设备，其特征在于，包括处理器，以及与所述处理器耦合的、如权利要求1～11任一项所述的磁性随机存储器。An electronic device, characterized by comprising a processor, and the magnetic random access memory according to any one of claims 1 to 11 coupled with the processor.