WO2021189205A1 - 电源管理***和电子设备 - Google Patents

电源管理***和电子设备 Download PDF

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Publication number
WO2021189205A1
WO2021189205A1 PCT/CN2020/080732 CN2020080732W WO2021189205A1 WO 2021189205 A1 WO2021189205 A1 WO 2021189205A1 CN 2020080732 W CN2020080732 W CN 2020080732W WO 2021189205 A1 WO2021189205 A1 WO 2021189205A1
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WIPO (PCT)
Prior art keywords
transistor
circuit
output port
voltage
output
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PCT/CN2020/080732
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English (en)
French (fr)
Inventor
范团宝
孙宁波
时小山
王易
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202080002157.1A priority Critical patent/CN113711482B/zh
Priority to PCT/CN2020/080732 priority patent/WO2021189205A1/zh
Priority to EP20927240.0A priority patent/EP4106170A4/en
Publication of WO2021189205A1 publication Critical patent/WO2021189205A1/zh
Priority to US17/951,469 priority patent/US20230015278A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/1566—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H02J7/00712—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the embodiments of the present application relate to the field of circuit technology, and in particular to a power management system and electronic equipment.
  • the performance of electronic devices has been improved day by day, which can provide users with diversified functional applications.
  • Processors and other components used to drive electronic devices to achieve various functions are running at higher and higher rates.
  • the increase in the operating speed of components such as processors has led to increasing power consumption of electronic devices.
  • the power management system needs to adjust the output voltage of the power management system in real time and dynamically according to the power consumption of the load such as the processor. Especially when the load power consumption increases sharply, causing the output voltage to drop below the voltage required by the load instantaneously, the power management system needs to respond quickly to stabilize the output voltage within the voltage range required by the load to avoid abnormal load power failure.
  • the output voltage of the power management system is stable within the range of VT ⁇ VB.
  • the power management system requires a longer response time (for example, 2 us), so that the output voltage of the output terminal Vout returns to the threshold voltage VB. And the longer the response time, the greater the output voltage drop, and the longer the callback time.
  • the prior art realizes a solution for dynamically adjusting the output voltage.
  • the output voltage drops below the voltage required by the load, it usually takes a long time to return to the stable voltage range, which affects the stability of the output voltage. This affects the stability of load work.
  • the power management system provided by the present application can quickly respond to the load to supply power to the load when the power consumption of the load surges while ensuring the utilization rate of electric energy, which is beneficial to improve the stability of the electronic device and the endurance of the electronic device.
  • an embodiment of the present application provides a power management system.
  • the power management system includes a DC-DC DC-DC conversion circuit, a first control circuit, a power supply circuit, an input port, and an output port; wherein the input The port is used to receive input voltage; the output port is connected to a load and is used to provide output voltage to the load; the DC-DC conversion circuit is connected between the input port and the output port and is used to pass the The output port obtains a first feedback voltage for reflecting the output voltage, and based on the first feedback voltage and a first reference signal, charges the output port through the input port to adjust the output voltage;
  • a control circuit connected between the output port and the power supply circuit, for obtaining a second feedback voltage of the output voltage through the output port, based on the second feedback voltage and a second reference signal, Generate a first control signal and provide the first control signal to the power supply circuit; the power supply circuit is connected between the input port and the output port for: based on the first control The signal is charged from the input port to the output port to
  • the supplementary circuit may be, for example, the supplementary electronic circuit (not shown in the figure) in the supplementary circuit 02 shown in FIG. Circuits other than the hysteresis comparator in the supplementary circuit 02 may also include the circuit including the transistor Q4 and the inductor L1 in the embodiment shown in FIG. 8, or may include the circuit including the transistor Q4 in the embodiment shown in FIG. 11 , The inductor L1, the transistor Q6, and the circuit including the inductor L2.
  • the first reference signal may be, for example, the reference signal Vset shown in FIG. 2.
  • the DC-DC conversion circuit 01 dynamically adjusts the voltage and current provided by the input port to generate the voltage and current required by the load to output to the load through the output port.
  • the first control circuit controls the supplementary circuit to provide the power input from the input port to the output port to supplement the load, thereby suppressing the continuous drop of the output port voltage , So that the voltage of the hand output port can be quickly adjusted back to the expected output voltage range, which is beneficial to improve the stability of the power supply of the power management system, thereby ensuring the stability of the load work.
  • the first control circuit includes a comparator for comparing the second feedback voltage with the second reference signal to obtain the first control signal.
  • the first control circuit compares the second feedback voltage with the second reference signal, and when it is determined that the second feedback voltage is less than or equal to the second reference signal, the first control signal is used to control the turn-on of the transistor in the supplementary circuit , So that the power supply circuit provides the power provided by the input port to the output port to suppress the output port voltage drop; when the first control circuit determines that the second feedback voltage is higher than the second reference signal, the first control signal is used to control the compensation
  • the transistor in the electrical circuit is turned off, thereby stopping the supply of electrical energy to the output port. As a result, the output voltage of the output port is maintained within the desired output voltage range.
  • the first control circuit may be a hysteresis comparator.
  • the second reference signal includes multiple threshold signals, which are used for hysteresis comparison of the hysteresis comparator.
  • the multiple threshold signals may include, for example, the reference signal VT and the reference signal VB shown in FIG. 2.
  • the DC-DC conversion circuit includes a second control circuit and at least one first power stage circuit; the second control circuit is used to obtain information for reflecting the The first feedback voltage of the output voltage generates at least one second control signal based on the first feedback voltage and the first reference signal; each first power stage circuit in the at least one first power stage circuit includes a first power stage circuit A transistor, a second transistor and an inductor, the first pole of the first transistor is connected to the input port, the second pole of the first transistor is connected to the first pole of the second transistor, and the second pole is connected to the first pole of the second transistor.
  • the second pole of the transistor is connected to the common ground, one end of the inductor is connected to the second pole of the first transistor, and the other end of the inductor is connected to the output port; the first transistor is used for In at least one second control signal, a second control signal corresponding to the first power stage circuit is charged from the input port to the output port through the inductor; the second transistor is used to charge the output port based on the corresponding The second control signal of the first power stage circuit charges the output port through the inductor.
  • the power stage circuit may include, but is not limited to, a step-up-step-down circuit or a step-down circuit, for example.
  • the DC-DC conversion circuit may include one power stage circuit, or may include multiple (for example, 2 or 3) power stage circuits.
  • the first transistor may be transistor Q1
  • the second transistor may be transistor Q2
  • the inductance may be inductance L0, which is used to control the control of the power stage circuit.
  • the signal is the signal output by the control terminals c01 and c02 of the Buck control circuit.
  • one of the power stage circuits may include transistor Q1, transistor Q2, and inductor L0, and the other power stage circuit may include transistor Q4, transistor Q5, and inductor. L1.
  • the first transistor may include a transistor Q1 and a transistor Q4, the second transistor may include a transistor Q2 and a transistor Q5, and the inductor may include an inductor L0 and an inductor L1.
  • one of the power stage circuits may include a transistor Q1, a transistor Q2, and an inductor L0, and one of the power stage circuits may include a transistor Q4, a transistor Q5, and an inductor.
  • L1 another power stage circuit can include transistor Q6, transistor Q7 and inductor L2.
  • the power supply circuit includes a third transistor; the control electrode of the third transistor is used to receive the first control signal, and the first control signal of the third transistor is The electrode is connected to the input port, the second electrode of the third transistor is connected to the output port, and the third transistor is used for charging from the input port to the output port based on the first control signal.
  • the third transistor may be, for example, the transistor Q4 shown in FIG. 2.
  • the third transistor When the third transistor is turned on, the power input from the input port is provided to the output port through the third transistor to increase the voltage of the output port; when the third transistor is turned off, charging to the output port is stopped.
  • the power supply circuit includes a third transistor, a fourth transistor, and a capacitor; the control electrode of the third transistor and the control electrode of the fourth transistor are respectively used for Receiving the first control signal, the first electrode of the third transistor is connected to the second electrode of the fourth transistor, the second electrode of the third transistor is connected to the output port, and the fourth transistor
  • the first electrode of the capacitor is connected to the input port; the first electrode of the capacitor is connected to the first electrode of the third transistor, and the second electrode of the capacitor is connected to the common ground; the fourth transistor is used for The first control signal charges the capacitor from the input port; the third transistor is used to charge the output port from the capacitor based on the first control signal.
  • the third transistor may be, for example, the transistor Q4 shown in FIG. 5
  • the fourth transistor may be, for example, the transistor Q3 shown in FIG. 5
  • the capacitor may be, for example, the capacitor C2 shown in FIG.
  • the third transistor When the third transistor is turned on and the fourth transistor is turned off, the voltage input from the output port is supplied to the capacitor to charge the capacitor; when the third transistor is turned off and the fourth transistor is turned on, the capacitor provides the stored charge to the output port to Charge the output port to adjust the output voltage of the output port.
  • the first transistor in the second power stage circuit in the at least one first power stage circuit is powered by the second power stage circuit and the supplementary power The circuit is multiplexed; the first transistor in the second power stage circuit is specifically used to obtain data from the second power stage circuit based on the first control signal and the second control signal corresponding to the second power stage circuit
  • the input port charges the output port through the inductor.
  • the DC-DC conversion circuit when the DC-DC conversion circuit includes a plurality of power stage circuits, some of the first transistors in the power stage circuit are multiplexed by the power stage circuit and the supplementary circuit.
  • the multiplexing here means that when the voltage output by the output port is within the expected output voltage range, the first transistor in this part of the power stage circuit is used as a part of the DC-DC converter circuit and is controlled by the second control signal.
  • the output port is charged; when the voltage of the output port drops below the voltage required by the load, the first transistor in this part of the power stage circuit is used as a part of the recharge circuit and is controlled by the first control signal to charge the output port.
  • the above-mentioned second power stage circuit may include, for example, the circuit formed by the transistor Q4, the transistor Q5, and the inductor L1 shown in FIG. 8, and may also include the circuit formed by the transistor Q6, the transistor Q7, and the inductor L2 shown in FIG.
  • the first transistor to be multiplexed may include the transistor Q4 and the transistor Q6 shown in FIG. 11.
  • the second control circuit is further configured to: acquire the first control signal, based on the first control signal and the signal corresponding to the second power stage circuit The second control signal generates a third control signal; the first transistor in the second power stage circuit is specifically configured to transmit from the input port to the The output port is charged.
  • the second control circuit includes an error amplifier, a signal modulator, and at least one driver; the error amplifier combines the first feedback voltage with the first reference signal Amplify the error between the two to obtain an amplified signal; the signal modulator is used to receive the amplified signal and generate the at least one modulated signal; each of the at least one driver is used to receive the modulated signal and generate One of the at least one second control signal.
  • the power management system further includes a reference signal adjustment circuit connected between the first control circuit and the DC-DC conversion circuit; the reference signal adjustment circuit The circuit is used to adjust the size of the first reference signal based on the first control signal, and provide the adjusted first reference signal to the DC-DC conversion circuit.
  • the voltage at the output port increases as a result of the power supply circuit supplementing the load through the output port; and the voltage at the output port received by the first input terminal of the second control circuit may be a voltage
  • the compensated value, the difference between the value and the second reference signal is usually small. This allows the second control circuit to reduce the power supply duration in the power supply cycle to reduce the output power. At this time, if the power supply circuit does not continue to supply power or the voltage remaining after the capacitor is discharged is not enough to support the load, the power supply is usually insufficient.
  • the value of the first reference signal can be increased when the supplementary circuit provides output current to the output port to increase the voltage between the output port and the first reference signal
  • the DC-DC converter circuit By setting the signal adjustment circuit to adjust the size of the first reference signal, the value of the first reference signal can be increased when the supplementary circuit provides output current to the output port to increase the voltage between the output port and the first reference signal
  • the power supply circuit stops providing output current to the output port it means that the voltage is adjusted back to the upper limit of the expected output voltage.
  • the value of a reference signal is used to reduce the difference between the voltage of the output port and the first reference signal, so as to prevent the DC-DC conversion circuit from maintaining a high power supply capacity, resulting in waste of electric energy.
  • an embodiment of the present application provides an electronic device, including the power management system described in any implementation manner of the first aspect.
  • an embodiment of the present application provides a power management method, which is applied to the power management system described in any implementation manner of the first aspect.
  • the power management method includes: a DC-DC conversion circuit in a power management system obtains a first feedback voltage reflecting the output voltage through the output port, and based on the first feedback voltage and a first reference signal, The input port charges the output port to adjust the output voltage; the first control circuit in the power management system is configured to obtain a second feedback voltage of the output voltage through the output port, based on the second feedback voltage And a second reference signal, generating a first control signal, and providing the first control signal to the power supply circuit; the power supply circuit in the power management system sends the power supply circuit from the input port to the The output port is charged to supplement the regulation of the output voltage.
  • FIG. 1 is a schematic diagram of an application scenario of a power management system provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a power management system provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of the internal structure of a Buck control circuit provided by an embodiment of the present application.
  • 4A is a schematic diagram of the internal structure of the hysteresis comparator provided by an embodiment of the present application.
  • 4B is another schematic diagram of the internal structure of the hysteresis comparator provided by the embodiment of the present application.
  • FIG. 5 is another schematic diagram of the structure of the power management system provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a reference signal adjustment circuit provided by an embodiment of the present application.
  • FIG. 7 is a waveform comparison diagram between the output terminal of the power management system shown in FIG. 5 and the output terminal of the power management system in the related art provided by an embodiment of the present application;
  • FIG. 8 is another schematic structural diagram of a power management system provided by an embodiment of the present application.
  • FIG. 9 is another schematic diagram of the internal structure of the Buck control circuit provided by an embodiment of the present application.
  • FIG. 10 is an equivalent circuit diagram of the power supplement circuit provided by the embodiment of the present application during the power supplement period
  • FIG. 11 is another schematic structural diagram of a power management system provided by an embodiment of the present application.
  • FIG. 12 is another schematic diagram of the internal structure of the Buck control circuit provided by an embodiment of the present application.
  • FIG. 13 is a flowchart of a power management method provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the “module” mentioned in this article generally refers to a functional structure divided logically.
  • the “module” can be implemented by pure hardware, or a combination of software and hardware.
  • "and/or” describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone. three conditions.
  • words such as “exemplary” or “for example” are used as examples, illustrations, or illustrations. Any embodiment or design solution described as “exemplary” or “for example” in the embodiments of the present application should not be construed as being more preferable or advantageous than other embodiments or design solutions. To be precise, words such as “exemplary” or “for example” are used to present related concepts in a specific manner.
  • FIG. 1 shows a schematic diagram of an application scenario of the power management system provided by an embodiment of the present application.
  • the power supply system 1 is connected to the input port Vin of the power management system 2 to provide power to the power management system.
  • the power supply system 1 may be an active circuit, which usually includes a battery, an active device, and the like.
  • the power supply system 1 may also be a grid power supply transmission line and an external power adapter.
  • the power management system 2 is connected to the grid power supply transmission line through the external power adapter, so that the power grid can transmit electric energy to the power management system 2 through the power adapter.
  • the output port Vout of the power management system 2 is connected to the load 3, and is used to transmit the electric energy provided by the power supply system 1 to the load 3, so as to provide the load 3 with electric energy required for operation.
  • the load 3 may be various processors or other types of devices, such as an image processing unit (GPU), a central processing unit (CPU), a computing accelerator, or various digital circuits and analog circuits.
  • the load 3 may also be various integrated circuit chips, which include but are not limited to artificial intelligence chips, image processing chips, and the like. There is no limitation here.
  • the power management system 2 includes a DC-DC (Direct Current-Direct Current, direct current-direct current) conversion circuit 01 and a power supplement circuit 02.
  • DC-DC Direct Current-Direct Current, direct current-direct current
  • the DC-DC conversion circuit 01 is connected to the input port Vin and the output port Vout of the power management system 2. During the operation of the load 3, the DC-DC conversion circuit 01 adjusts the input to the load based on the first feedback voltage of the electrical parameters (such as voltage value, current value, power value) of the output port Vout and the preset first reference signal Voltage and current to supply power to load 3.
  • the electrical parameters such as voltage value, current value, power value
  • the first reference signal is used to control the expected output voltage of the current output port Vout, that is, the voltage required by the load 3 to work; it may be the expected output voltage or an adjusted voltage adjusted based on the expected output voltage.
  • the first feedback voltage may be the voltage actually output by the output port Vout, or may be the voltage obtained by adjusting the actual output voltage.
  • the DC-DC conversion circuit 01 may include a first control circuit and a power stage circuit.
  • the first control circuit can be realized by a discrete device, or can be realized by a programmable device.
  • Programmable devices include but are not limited to programmable logic controllers (PLC, Programmable Logic Controller), digital signal processors (DSP, digital signal processor), signal generators, etc.
  • the power stage circuit includes, but is not limited to, a boost-buck (BOOST-BUCK) circuit, or a buck (BUCK) circuit, for example.
  • the first control circuit may adjust the duty cycle of the transistor in the power stage circuit based on the electrical parameter (for example, the current value, the voltage value or the power value) of the output port Vout and the first reference signal to control the load 3 Provided electrical energy (such as the voltage and current required for load operation).
  • the electrical parameter for example, the current value, the voltage value or the power value
  • the first reference signal to control the load 3 Provided electrical energy (such as the voltage and current required for load operation).
  • the power supply circuit 02 is also connected to the input port Vin and the output port Vout of the power management system 2.
  • the supplementary circuit 02 is based on the second feedback voltage, the second reference signal and the third reference signal of the output voltage of the output port Vout. When the output voltage is lower than the second reference signal, it provides output current to the load through the output port Vout; When the voltage is higher than the third reference signal, the output current to the load is stopped.
  • the second feedback voltage may be the voltage actually output by the output port Vout, or may be the voltage obtained by adjusting the actual output voltage.
  • the second reference signal and the third reference signal are used to control the voltage expected to be output by the current output port Vout, that is, the voltage required by the load 3 to work.
  • the second reference signal and the third reference signal may be the same or different.
  • the value of the third reference signal is higher than the value of the second reference signal.
  • the second reference signal is the same as the third reference signal, it may be the desired output voltage, or may be an adjusted voltage adjusted based on the desired output voltage.
  • the second reference signal and the third reference signal are different, the second reference signal is used to control the lower limit of the expected output voltage of the output port Vout, and the third reference signal is used to control the lower limit of the expected output voltage of the output port Vout.
  • the second reference signal and/or the third reference signal can be changed, which changes based on the working condition of the load 3. For example, when the load 3 is in a low power consumption state, the working voltage of the load 3 is lower, and the second reference signal is smaller at this time; when the load 3 is in a high power consumption state, the working voltage of the load 3 is higher, and then the first Second, the reference signal is relatively large.
  • the supplementary circuit 02 includes a second control circuit and a supplementary electronic circuit.
  • the second control circuit can be realized by a discrete device, or can be realized by a programmable device.
  • Programmable devices include but are not limited to PLC, DSP, signal generator, etc.
  • the second control circuit When the second control circuit detects that the second feedback voltage is lower than the second reference signal, it controls at least part of the transistors in the complementary electronic circuit to be turned on, thereby converting the current input from the input port Vin into an output current, and passing it through the output port Vout in time Provided to the load 3; when the second control circuit detects that the second feedback voltage is higher than the third reference signal, it controls at least part of the transistors in the complementary electronic circuit to turn off, thereby stopping the supply of output current to the load 3.
  • the above-mentioned second control circuit includes a comparator.
  • the comparator may be a single-limit comparator.
  • the single-limit comparator usually includes two input terminals for inputting the second reference signal (or the third reference signal) and the second feedback voltage respectively.
  • the comparator may be a double limit comparator.
  • the dual-limit comparator is used to compare the second feedback voltage with the second reference signal and the third reference signal respectively, and when it is detected that the second feedback voltage is lower than the second reference signal, control the compensation in the electronic circuit At least part of the transistors are turned on, and the load 3 is supplemented in time through the output port Vout; when it is detected that the voltage value of the output port Vout is higher than the third reference signal, at least part of the transistors in the supplementary electronic circuit are controlled to turn off to stop the supply Load 3 recharges.
  • the double limit comparator may be a hysteresis comparator.
  • the DC-DC conversion circuit 01 dynamically adjusts the voltage and current provided by the input port Vin to generate the voltage and current required by the load to output to the output port Vout. load.
  • the output voltage of the output port Vout drops instantaneously, which usually drops below the voltage required by the load 3 to operate.
  • the supplementary circuit 02 obtains the input current from the input port Vin, converts the input current into an output current, and supplements the load 3 in time.
  • the supplementary circuit 02 provides an output current to the load 3 in advance, and after the DC-DC conversion circuit 01 responds, it is connected in parallel with the DC-DC conversion circuit 01 to provide an output current to the load 3 at the same time. Therefore, the callback time of the output voltage can be quickly increased, which is beneficial to improve the stability of the power supply of the power management system, thereby ensuring the stability of the load operation.
  • the power supply terminal Vcc that is, the input port Vin shown in FIG. 1
  • the power supply terminal is denoted by the reference sign Vcc.
  • FIG. 2 shows a schematic structural diagram of the power management system provided by an embodiment of the present application.
  • the power management system 2 includes a Buck control circuit, a transistor Q1, a transistor Q2, an inductor L0, a capacitor C1, a power supply circuit 02, a power supply terminal Vcc, and an output port Vout.
  • the transistor Q1, the transistor Q2, the inductor L0 and the capacitor C1 work as a one-phase Buck circuit.
  • control electrode of the transistor Q1 and the control electrode of the transistor Q2 are respectively connected to the output terminal c01 and the output terminal c02 of the Buck control circuit, the first electrode of the transistor Q1 is connected to the power supply terminal Vcc; the second electrode of the transistor Q2 is connected to the common Ground Gnd; one end of the inductor L0 is connected to the second pole of the transistor Q1 and the first pole of the transistor Q2, the other end of the inductor L0 is connected to the output port Vout; the first electrode of the capacitor C1 is connected to the output terminal Vout, and the second electrode is connected To the public Gnd.
  • the input terminal Via of the Buck control circuit is connected to the output port Vout, and the input terminal Vib of the Buck control circuit is used to input the reference signal Vset.
  • the reference signal Vset is used to control the voltage signal expected to be output by the output port Vout.
  • the feedback value of the voltage value of the output port Vout is lower than the reference signal Vset, it indicates that the power supply is insufficient and more power needs to be provided to the load 3.
  • the feedback value of the voltage value of the output port Vout is higher than the reference signal Vset, it indicates that the power supply is over. It is necessary to reduce the power supplied to the load 3.
  • the feedback value may be equal to the voltage value of the output port Vout or another voltage value reflecting the voltage value of the output port Vout, such as the voltage division value of the voltage value of the output port Vout, which is not limited in this embodiment.
  • the reference signal Vset can be changed based on the current working condition of the load and the required voltage.
  • the conduction time of the transistor Q1 and the transistor Q2 are different. In other words, when the transistor Q1 is turned on, the transistor Q2 is turned off; when the transistor Q1 is turned off, the transistor Q2 is turned on.
  • the transistor Q1 and the transistor Q2 may be Nmos transistors or Pmos transistors. Generally, the transistor Q1 is a Pmos transistor, and the transistor Q2 is an Nmos transistor.
  • an inverter is provided between the output terminal c02 and the transistor Q2 for inverting the driving signal.
  • the inductor L0 can be a relatively large-capacity inductor, for example, the inductor capacity can be 470nH.
  • the Buck control circuit can obtain the feedback value of the voltage value of the output port Vout in real time, and based on the difference between the obtained feedback value and the reference signal Vset, control the conduction time of the transistor Q1 and the conduction time of the transistor Q2 to control The electric energy provided by the power supply terminal Vcc to the load.
  • the transistor Q1 when the feedback value is less than the reference voltage value and the difference between the two is greater than the preset threshold, the transistor Q1 can be controlled to be fully turned on during a power supply cycle, and the transistor Q2 can be controlled to be completely turned off during the power supply cycle; for another example, when When the feedback value is less than the reference voltage value, but the difference between the two does not reach the preset threshold, the transistor Q1 and the transistor Q2 can be controlled to account for 50% of the conduction time in one power supply cycle.
  • the feedback value obtained by the Buck control circuit is the voltage value of the output port Vout itself as an example for description, but it is not used for limitation.
  • Buck control circuit includes error amplifier EA, signal modulator T and driver P1. Among them, one input end of the error amplifier EA is connected to the output port Vout, the other input end is used to input the reference signal Vset, the output end of the error amplifier EA is connected to the input end of the signal modulator T, and the output end of the signal modulator T is connected To the input terminal of the driver P1, the driver P1 is connected to the control electrode of the transistor Q1 through the output terminal c01, and the driver P1 is connected to the control electrode of the transistor Q2 through the output terminal c02.
  • the error amplifier EA is used to compare the voltage value of the output port Vout with the reference signal Vset, amplify the difference between the two and provide it to the signal modulator T.
  • the signal modulator T is used to modulate the error signal into a pulse signal to control the transistor Q1 and the transistor Q2 to be turned on or off.
  • the signal modulator T may be a pulse width modulator (PWM, Pulse Width Modulation), or a pulse frequency modulator (PFM, Pulse Frequency Modulation).
  • the pulse width modulator adjusts the duty cycle between the high level and the low level in a switching cycle based on the size of the error signal to control the power supply duration;
  • the pulse frequency modulator adjusts the duration of the switching period based on the magnitude of the error signal by fixing the on-time of the transistor Q1 or the on-time of the transistor Q2 to control the power supply duration.
  • the driver P1 is used to process the signal input by the signal modulator T, such as increasing the pulse amplitude, optimizing the rising and falling edges of the pulse (for example, reducing the pulse rise time and fall time to make the transistor turn on and off quickly), and generate drive Signal to control the transistor Q1 and the transistor Q2 to be turned on or off.
  • the specific structure of the Buck control circuit shown in FIG. 3 is schematic, and the specific structure can also be adjusted according to the needs of the application scenario.
  • the power compensation circuit 02 includes a hysteresis comparator B and a transistor Q4.
  • the hysteresis comparator B shown in FIG. 2 includes three input terminals: an input terminal V1, an input terminal V2, and an input terminal V3.
  • the input terminal V1 of the hysteresis comparator B is connected to the output port Vout, the input terminal V2 of the hysteresis comparator B is used to input the reference signal VB, and the input terminal V3 of the hysteresis comparator B is used to input the reference signal VT.
  • the output terminal K of the hysteresis comparator B is connected to the control electrode of the transistor Q4, the first electrode of the transistor Q4 is connected to the power supply terminal Vcc, and the second electrode of the transistor Q4 is connected to the output port Vout.
  • the load operates based on a specific voltage, and the voltage output by the output port Vout needs to be stabilized within the floating range of the specific voltage to ensure stable operation of the load.
  • the aforementioned reference signal VT is used to control the upper limit of the voltage signal expected to be output by the output port Vout
  • the reference signal VB is used to control the lower limit of the voltage signal expected to output from the output port Vout
  • the value of the reference signal VB is smaller than the value of the reference signal VT.
  • the reference signal VT and the reference signal VB may be set based on the reference signal Vset.
  • the reference signal VT may be the sum of the value of the reference signal Vset and the first offset ⁇ V1
  • the reference signal VB may be the difference between the value of the reference signal Vset and the second offset ⁇ V2.
  • the first offset ⁇ V1 and the second offset ⁇ V2 are preset.
  • the hysteresis comparator B can obtain the voltage value of the output port Vout in real time, and then compare the voltage value of the output port Vout with the reference signal VT and the reference signal VB. When the voltage value of the output port Vout is lower than the reference signal VB, an output current needs to be generated to stabilize the voltage output by the output port Vout within a preset range. At this time, the transistor Q4 can be controlled to be turned on to provide the input current provided by the power supply terminal Vcc to the output port Vout as an output current to the load. When the hysteresis comparator B detects that the voltage value of the output port Vout is higher than the reference signal VT, the transistor Q4 can be controlled to turn off. When the hysteresis comparator B detects that the voltage value of the output port Vout is lower than the reference signal VT again, the control transistor Q4 is turned on.
  • the circuit structure of a hysteresis comparator is shown in FIG. 4A.
  • the hysteresis comparator B includes integrated operational amplifier F1, integrated operational amplifier F2 and D flip-flops.
  • the non-inverting input terminal of the integrated operational amplifier F1 and the inverting input terminal of the integrated operational amplifier F2 are respectively connected to the output port Vout.
  • the inverting input terminal of the integrated operational amplifier F1 is used to input the reference signal VT
  • the non-inverting input terminal of the integrated operational amplifier F2 is used to input the reference signal VB.
  • the output terminal of the integrated operational amplifier F1 is connected with the reset terminal Rst of the D flip-flop
  • the output terminal of the integrated operational amplifier F2 is connected with the clock signal terminal CP of the D flip-flop.
  • the output terminal Q of the D flip-flop is the output terminal K of the hysteresis comparator B for outputting control signals.
  • the input terminal D inputs a high level signal as an example
  • the reset terminal Rst high level signal is valid as an example
  • the transistor Q4 is an Nmos transistor.
  • the working principle of the compensation circuit 02 including the hysteresis comparator B shown in FIG. 4A is described.
  • the integrated operational amplifier F1 When the voltage of the output port Vout is higher than the reference signal VT, the integrated operational amplifier F1 outputs a high-level signal, and the integrated operational amplifier F2 outputs a low-level signal. At this time, the D flip-flop outputs a low-level signal, and the transistor Q4 is turned off.
  • the integrated operational amplifier F1 When the voltage of the output port Vout gradually decreases from higher than the reference signal VT to lower than the reference signal VB, the integrated operational amplifier F1 outputs a low-level signal, and the signal output by the integrated operational amplifier F2 changes from a low level to a high level. At this time, the D flip-flop is turned on, the D flip-flop transmits the high-level signal input from the input terminal D to the output terminal Q, and the transistor Q4 is turned on.
  • the output terminal Q of the D flip-flop keeps outputting a high-level signal unchanged.
  • the signal output by the integrated op amp F1 jumps from low to high, and the signal output by the integrated op amp F2 is low.
  • the D flip-flop is reset, the output terminal Q of the D flip-flop outputs a low-level signal, and the transistor Q4 is turned off.
  • the circuit structure of a hysteresis comparator can also be as shown in FIG. 4B.
  • the circuit structure of the hysteresis comparator shown in FIG. 4B includes two input terminals. It generates the reference signal VT and the reference signal VB by adjusting the input reference voltage signal Vref.
  • the hysteresis comparator B shown in FIG. 4A includes an integrated operational amplifier, a resistor R1, and a resistor R2.
  • the inverting input terminal of the integrated operational amplifier is connected to the output port Vout, the forward input terminal of the integrated operational amplifier is connected to one end of the resistor R1, the other end of the resistor R1 is used to input the reference voltage signal Vref, and the branch where the resistor R2 is located is used as feedback
  • the path is arranged between the forward input terminal and the output terminal of the integrated operational amplifier, and the output terminal K of the integrated operational amplifier is connected to the transistor Q4.
  • Vcc ⁇ R1/(R1+R2)+Vref ⁇ R2/(R1+R2) VT (2)
  • the reference signal VT and the reference signal VB are determined based on the load operating power and the voltage required for load operation.
  • Vcc is the voltage value of the external power supply system.
  • the reference voltage can be determined by adjusting the resistance of the resistors R1 and R2.
  • the hysteresis comparator B as shown in FIG. 4B can generate the reference signal VT and the reference signal VB.
  • the reference signal VT and the reference signal VB need to be dynamically adjusted based on the voltage required for load operation, at this time, by adjusting the resistance of the resistor R1 and the resistor R2, the voltage value of the reference voltage signal Vref can be changed, thereby adjusting the reference The size of the signal VT and the reference signal VB.
  • the power management system in the traditional technology usually does not have the power supply circuit 02.
  • the Buck circuit usually supplies power to the load based on the power supply cycle.
  • the Buck circuit needs to change the duty cycle of the control signal in the next power supply cycle after the current power supply cycle is completed to increase the transistor Q1 conduction time, thereby increasing The amount of power supplied causes the output voltage to be adjusted back.
  • the transient response time is usually improved by reducing the duration of the power supply cycle and increasing the switching frequency of the transistor Q1 and the transistor Q2. For example, increase the switching rate from 2MHz to 4MHz.
  • the transistor Q1 and the transistor Q2 are energy-consuming components. Due to the existence of their own parasitic resistance, as their turn-on or turn-off time increases, their energy consumption increases. It can be seen that by increasing the switching frequency of the transistor Q1 and the transistor Q2 in exchange for the transient response of the Buck circuit, the energy conversion efficiency is greatly reduced.
  • the power management system in the traditional technology also improves the transient response time by reducing the inductance of the inductor L0.
  • the inductor is an energy storage element. Since the current on the inductor L0 cannot change suddenly, after the external power supply system stops supplying power, the energy stored in the inductor can provide electrical energy to the load to supply power to the load. The greater the inductance, the more energy it can store in a switching cycle.
  • the inductance of the inductor L0 When the inductance of the inductor L0 is reduced, the energy that can be stored in a power supply cycle is also reduced.
  • the value of the reference signal Vset needs to be increased to increase the energy provided by the power supply terminal. In this way, when the energy consumed by the load is less than the energy input by the Buck circuit, electrical energy is wasted and the energy usage rate is reduced.
  • the power supplement circuit 02 by setting the power supplement circuit 02, the load can be supplemented in time at the moment when the load energy consumption is too large to pull down the voltage of the output port Vout, and the supplementary power can be stopped after the voltage of the output port Vout rises, so as to prevent the load from supplying power. Insufficiency leads to abnormal power failure and other situations.
  • the Buck circuit shown in the embodiment of the present application can reduce the switching frequency of the transistor Q1 and the transistor Q2, and does not need to reduce the energy value of the inductor L0, thereby ensuring the efficiency of power use.
  • the capacity of the capacitor C1 in the Buck circuit can be reduced (for example, a 23uF capacitor can be used in this embodiment, while a 60uF capacitor is required in a traditional Buck circuit), which is beneficial to simplify the layout area.
  • FIG. 5 shows a schematic structural diagram of another embodiment of the power management system 2 shown in FIG. 1.
  • the power management system 2 includes a DC-DC conversion circuit 01 and a supplementary circuit 02.
  • the DC-DC conversion circuit 01 includes a Buck control circuit, a transistor Q1, a transistor Q2, an inductor L0, and a capacitor C1
  • the supplementary circuit 02 includes a hysteresis comparator B and a transistor Q4.
  • the internal structure of the Buck control circuit can refer to the related description shown in Figure 3
  • the internal structure of the hysteresis comparator B can refer to the related description shown in Figure 4A or Figure 4B
  • the connection relationship between the circuit and the components can refer to the related description shown in Figure 2. The relevant description of the illustrated embodiment will not be repeated here.
  • the power supplement circuit 02 further includes a transistor Q3 and a capacitor C2.
  • the control electrode of the transistor Q3 is connected to the output terminal K of the hysteresis comparator B
  • the first electrode of the transistor Q4 is connected to the second electrode of the transistor Q3 and one end of the capacitor C2
  • the second electrode of the transistor Q4 is connected to the output port Vout
  • the other end of the capacitor C2 is connected to the common ground Gnd.
  • the transistor Q3 and the transistor Q4 have different conduction times. When the transistor Q3 is turned on, the transistor Q4 is turned off; when the transistor Q4 is turned on, the transistor Q3 is turned off.
  • the transistor Q3 and the transistor Q4 may be the same type of transistor (for example, a Pmos transistor or an Nmos transistor), or may be different types of transistors. When the two are the same type of transistors, an inverter is provided between the output terminal K and the transistor Q3 or the transistor Q4.
  • the hysteresis comparator B can obtain the voltage value of the output port Vout in real time, and then compare the voltage value of the output port Vout with the reference signal VT and the reference signal VB.
  • the control transistor Q3 is turned on and the control transistor Q4 is turned off.
  • the external power supply system charges the capacitor C2 through the transistor Q3; when the hysteresis comparator B detects that the voltage value of the output port Vout is lower than the reference signal VB, it needs to generate an output current to stabilize the voltage output by the output port Vout at a preset value Within range.
  • the transistor Q3 can be controlled to turn off, the transistor Q4 can be controlled to turn on, and the capacitor C2 quickly supplements the load through the transistor Q4.
  • the control transistor Q3 is turned on and the control transistor Q4 is turned off to charge the capacitor C2.
  • the voltage at the output port Vout increases; and the voltage at the output port Vout received by the input terminal Via of the Buck control circuit may be After voltage compensation, the difference between this value and the reference signal Vset is usually small. This allows the Buck control circuit to reduce the power supply duration in the power supply cycle to reduce the output power (reduce the output current or output voltage). At this time, if the power supply circuit 02 does not continue to supply power or the voltage remaining after the capacitor C2 is discharged is not enough to support the load, the power supply is usually insufficient.
  • a reference signal adjusting circuit 03 may also be provided. Specifically, the input end of the reference signal adjustment circuit 03 is connected to the output end K of the hysteresis comparator B, and the output end of the reference signal adjustment circuit 03 is connected to the input end Vib of the Bcuk control circuit.
  • the reference signal adjusting circuit 03 is used to increase the value of the reference signal Vset input to the Buck control circuit during the charging period of the charging circuit 02. Wherein, the time period during which the value of the reference signal Vset is increased is greater than or equal to the time during which the Buck control circuit responds to the excessive consumption of the load power.
  • the value of the reference signal Vset can be increased when the supplementary circuit 02 provides output current to the output port Vout, so as to increase the voltage of the output port Vout and the reference signal Vset.
  • the DC-DC conversion circuit 01 By setting the signal adjustment circuit 03 to adjust the size of the reference signal Vset, the value of the reference signal Vset can be increased when the supplementary circuit 02 provides output current to the output port Vout, so as to increase the voltage of the output port Vout and the reference signal Vset.
  • the DC-DC conversion circuit 01 By reducing the value of the reference signal Vset, the difference between the voltage of the output port Vout and the reference signal Vset is reduced, and the DC-DC conversion circuit 01 is prevented from maintaining a high power supply, which causes a waste of electric energy.
  • the reference signal adjustment circuit 03 may include a D flip-flop, a counter, a reference signal register A1, a reference signal register A2, and a reference voltage divider network.
  • the clock signal terminal CP of the D flip-flop is connected to the output terminal K of the hysteresis comparator B
  • the input terminal D of the D flip-flop is used to input the transmission signal
  • the reset terminal Rst of the D flip-flop is connected to the output terminal of the counter
  • the D trigger The signal output from the output terminal Q of the converter is used to control the reference signal register A1 or the reference signal register A2 to connect to the input terminal of the reference voltage divider network
  • the output terminal of the reference voltage divider network is connected to the input terminal Vib of the Buck control circuit.
  • the control terminal Gate of the counter is connected to the output terminal Q of the D flip-flop, and the clock signal terminal Clk of the counter is used to input a clock signal.
  • the D flip-flop is an edge flip-flop.
  • the signal input by the clock signal terminal CP of the D flip-flop changes from invalid to valid (for example, when the low level turns to the high level), that is, when the input signal has a rising edge
  • the D flip-flop The signal input from the input terminal D is provided to the output terminal Q to be output from the output terminal Q.
  • the reset terminal Rst of the D flip-flop receives the reset signal, the D flip-flop is reset, and the output terminal Q outputs an initial setting signal.
  • Fig. 6 schematically shows a situation where the input terminal D of the D flip-flop inputs logic "1” and the D flip-flop is reset so that the output terminal Q outputs the initial setting signal logic "0".
  • the trigger transistor Q4 when the signal output by the output terminal K of the hysteresis comparator B transitions from low level to high level, the trigger transistor Q4 is turned on. At this time, the transistor Q4 is an Nmos transistor ; When the transistor Q4 is a Pmos transistor, an inverter can be provided between the output terminal of the hysteresis comparator B and the transistor Q4.
  • the input terminal D of the D flip-flop inputs a high level signal or a "logic 1" signal. When the D flip-flop is reset, the output terminal Q of the D flip-flop outputs "logic 0".
  • the reference signal register A1 stores the first voltage value of the reference signal Vset
  • the reference signal register A2 stores the second voltage value of the reference signal Vset.
  • the first voltage value is higher than the second voltage value, and the higher value is determined based on the voltage raised by the output port Vout during the charging period.
  • the reference voltage divider network is used to convert the first voltage value or the second voltage value into an analog signal.
  • the reference voltage divider network here can be a digital-to-analog conversion circuit.
  • the reference voltage divider network may include a voltage stabilizing chip, a single-input multiple-output selector, and a voltage divider exclusion.
  • the voltage regulator chip is used to output a voltage of a specific size (for example, 3V).
  • the output terminal of the voltage regulator chip is connected with the input terminal of the selector.
  • the first voltage signal or the second voltage signal can control the selector so that the input terminal of the selector is connected to one of the voltage divider terminals of the voltage divider exclusion, and the corresponding analog voltage signal is obtained through the voltage division of the voltage divider exclusion.
  • the input terminal D of the D flip-flop inputs "logic 1".
  • the reference signal register A1 is connected to the reference voltage divider network.
  • the reference voltage divider network processes the first voltage value stored in the reference signal register A1 to generate an analog voltage signal and provide it to the Buck control circuit. Input Vib; at the same time, the counter starts timing. When the counter counts to the ⁇ T time, it sends a reset signal to the D flip-flop. After the D flip-flop receives the reset signal, the output terminal Q outputs "logic 0".
  • the reference signal register A2 is connected to the reference voltage divider network, and the reference voltage divider network processes the second voltage value stored in the reference signal register A2 to generate an analog voltage signal and provide it to the input terminal Vib of the Buck control circuit.
  • the ⁇ T time is greater than or equal to the time that the Buck control circuit responds to the load power consumption.
  • FIG. 7 shows the voltage waveform output by the output port Vout after the power supply circuit 02 is installed
  • FIG. 7 shows the voltage waveform output by the output port Vout when the power supply circuit 02 is not installed.
  • VB is the difference between the reference signal Vset and the offset ⁇ V2
  • VT is the sum of the reference signal Vset and the offset ⁇ V1. It can be seen from Figure 7 that when the power supply circuit 02 is not provided, the voltage waveform output by the output port Vout drops far below VB at a certain moment, and it takes a long time for the voltage of the output port Vout to recover above VB. For example, 2us.
  • the hysteresis comparator B controls the transistor Q4 to turn on, so that the output port Vout of the power supply circuit 02 provides output current, and the voltage at the output port Vout rises;
  • the hysteresis comparator B controls the transistor Q4 to turn off, and the power supply circuit 02 stops outputting current.
  • FIG. 8 shows a schematic structural diagram of another embodiment of the power management system 2 shown in FIG. 1.
  • the power management system 2 includes a Buck control circuit, a hysteresis comparator B, a transistor Q1, a transistor Q2, a transistor Q4, a transistor Q5, an inductor L0, an inductor L1, and a capacitor C1.
  • the transistor Q1, the transistor Q2, the inductor L0, and the capacitor C1 belong to a one-phase Buck circuit.
  • the transistor Q4, the transistor Q5, the inductor L1, and the capacitor C1 can belong to another phase Buck circuit. That is, the Buck circuit shown in this embodiment is a two-phase Buck circuit.
  • the supplementary circuit 02 and the DC-DC conversion circuit 01 multiplex the transistor Q4, the transistor Q5, and the inductor L1.
  • the output terminal K of the hysteresis comparator B is connected to the input terminal Vic of the Buck control circuit
  • the control electrode of the transistor Q4 is connected to the output terminal c04 of the Buck control circuit
  • the control electrode of the transistor Q5 is connected to the output terminal c05 of the Buck control circuit.
  • the first pole of the transistor Q4 is connected to the power supply terminal Vcc
  • the second pole of the transistor Q5 is connected to the common ground Gnd
  • the second pole of the transistor Q4 and the first pole of the transistor Q5 are connected to one end of the inductor L1, and the other of the inductor L1 One end is connected to the output port Vout.
  • the internal structure of the hysteresis comparator B can refer to the internal structure shown in FIG. 4A or FIG. 4B.
  • the transistor Q4 and the transistor Q5 have different conduction times.
  • the output terminal K of the hysteresis comparator B in this embodiment is not directly connected to the control terminals of the transistors Q4 and Q5, but is connected to the transistors through the Buck control circuit.
  • the control terminal of the transistor Q5 is connected. Therefore, when the voltage of the output port Vout is lower than the reference signal VB, the transistor Q4 is turned on, and the compensation circuit 02 provides an output current to the output port Vout; when the voltage of the output port Vout is higher than the reference signal VT, the transistor Q4 is turned off to compensate The electrical circuit 02 stops supplying current. At this time, the transistor Q4, the transistor Q5 and the inductor L1 work as a one-phase Buck under the control of the Buck control circuit.
  • the specific structure of the Buck control circuit can be as shown in FIG. 9.
  • the Buck control circuit includes an error amplifier EA, a signal modulator T, a driver P1, a driver P2, and a NOR gate H1.
  • one input end of the error amplifier EA is connected to the output port Vout, the other input end is used to input the reference signal Vset, the output end of the error amplifier EA is connected to the input end of the signal modulator T, one of the output of the signal modulator T
  • the terminal is connected to the input terminal of the driver P1
  • the other output terminal of the signal modulator T is connected to one of the input terminals of the NOR gate H1
  • the output terminal K of the hysteresis comparator B is connected to the other input terminal of the NOR gate H1.
  • the output terminal of the NOR gate H1 is connected to the input terminal of the driver P2.
  • the driver P1 is connected to the control electrode of the transistor Q1 through the output terminal c01, and is connected to the control electrode of the transistor Q2 through the output terminal c02.
  • the driver P2 is connected to the control electrode of the transistor Q4 through the output terminal c04, and is connected to the control electrode of the transistor Q5 through the output terminal c05.
  • the working principle of the error amplifier EA the structure and working principle of the signal modulator T, the working principle of the driver P1 and the driver P2
  • the specific structure of the Buck control circuit shown in FIG. 9 is schematic, and the specific structure can be adjusted according to the needs of the application scenario, which is not limited here.
  • the transistor Q4 is a Pmos transistor
  • the transistor Q5 is an Nmos transistor
  • the low-level signal output by the output terminal K of the hysteresis comparator is valid
  • the low-level signal output by the output terminal of the signal modulator T is valid
  • the principle is described by taking the transistor Q4 as a Pmos transistor, the transistor Q5 as an Nmos transistor, and a NOR gate as an example.
  • the hysteresis comparator B When the hysteresis comparator B detects that the voltage value of the output port Vout is lower than the reference signal VB, the hysteresis comparator B outputs a high level signal. At this time, no matter what the signal output by the signal modulator T is, it is a low-level signal after NOR with the high-level signal output by the hysteresis comparator B. After the signal is processed by the driver P2, the control transistor Q4 is turned on to supply power. The terminal Vcc provides the output current to the output port Vout through the transistor Q4.
  • the hysteresis comparator B When the hysteresis comparator B detects that the voltage value of the output port Vout is higher than the reference signal VT, the hysteresis comparator B outputs a low-level signal, and the power supply terminal Vcc stops outputting current through the branch where the transistor Q4 is located.
  • the signal output from the output terminal of the NOR gate H1 is controlled by the signal output by the signal modulator T.
  • the transistor Q4, the transistor Q5 and the inductor L1 work as a one-phase buck under the control of the Buck control circuit. In other words, during the period when the supplementary circuit 02 stops supplementing, the power management system 2 uses a two-phase Buck circuit to supply power to the load.
  • one input terminal of the NOR gate H1 receives the second control signal
  • the other input terminal K of the NOR gate H1 receives the first control signal from the compensation circuit 02, so that the NOR gate H1 outputs the third control signal.
  • the third control signal is obtained by performing a NOR operation on the first control signal and the second control signal, and is used to control the transistor Q4.
  • the transistor Q4 is controlled by the third control signal, and can also be regarded as being jointly controlled by the first control signal and the second control signal, and operates based on the control of the first control signal and the second control signal.
  • the Buck circuit shown in this embodiment can also use a small-capacity capacitor (for example, a 23uF capacitor), which can reduce the area occupied by the layout.
  • Imax be the maximum transient current of the load
  • the voltage provided by the power supply terminal Vcc is VBAT
  • L0 is the inductance value of the inductor L0
  • C1 is the capacitance value of the capacitor C1
  • ESR is the resistance value of the parasitic equivalent resistance ESR of the capacitor C1
  • the transistor Q4 The first turn-on time is 0 time
  • Vout is the voltage value of the output port Vout
  • the output port Vout voltage drops after 0 time is ⁇ Vd(t)
  • tm is the time when the output port Vout voltage drops to the lowest point
  • I1( t) is the current flowing through the inductor L1
  • I2(t) is the current flowing through the resistor ESR
  • I3(t) is the current flowing through the load.
  • I2(t) Imax-(VBAT-Vout)/L0 ⁇ t (5)
  • FIG. 11 shows a schematic structural diagram of another embodiment of the power management system 2 shown in FIG. 1.
  • the power management system 2 includes a Buck control circuit, a hysteresis comparator B, a transistor Q1, a transistor Q2, a transistor Q4, a transistor Q5, an inductor L0, an inductor L1, and a capacitor C1.
  • the transistor Q1, the transistor Q2, the inductor L0, and the capacitor C1 belong to a one-phase Buck circuit.
  • the transistor Q4, the transistor Q5, the inductor L1, and the capacitor C1 belong to a one-phase Buck circuit.
  • the power management system 2 further includes a driver P3, a transistor Q6, a transistor Q7, and an inductor L2.
  • the transistor Q6, the transistor Q7, the inductor L2, and the capacitor C1 can belong to a one-phase Buck circuit again. That is, the Buck circuit shown in this embodiment is a three-phase Buck circuit.
  • the control electrode of the transistor Q6 and the control electrode of the transistor Q7 are respectively connected to the output terminal c06 and the control terminal c07 of the Buck control circuit, the first electrode of the transistor Q6 is connected to the power supply terminal Vcc, and the second electrode of the transistor Q7 is connected to the common ground Gnd , The second pole of the transistor Q6, the first pole of the transistor Q7 and one end of the inductor L2 are connected, and the other end of the inductor L2 is connected to the output port Vout.
  • the transistor Q6 and the transistor Q7 have different conduction times.
  • the transistor Q4 and the transistor Q6 are turned on, and the power supply terminal Vcc has two paths (that is, the branch where the inductor L1 is located and the branch where the inductor L2 is located)
  • the electric energy is provided to the output port Vout to supplement the load; when the voltage of the output port Vout is higher than the reference signal VT, the power supply terminal Vcc stops supplementing the electricity.
  • the transistor Q4, the transistor Q5, the inductor L1 and the capacitor C1 work as a one-phase Buck circuit under the control of the Buck control circuit; the transistor Q6, the transistor Q7, the inductor L2 and the capacitor C1 work as a one-phase Buck circuit under the control of the Buck control circuit The circuit works.
  • the specific structure of the Buck control circuit can be as shown in FIG. 12.
  • the Buck control circuit includes an error amplifier EA, a signal modulator T, a driver P1, a driver P2, and a NOR gate H1.
  • EA error amplifier
  • the Buck control circuit shown in this embodiment also includes a driver P3 and a NOR gate H2
  • the signal modulator T also includes a third output terminal.
  • the three output terminals are connected to one of the input terminals of the NOR gate H2, the output terminal K of the hysteresis comparator B is also connected to the other input terminal of the NOR gate H2, and the output terminal of the NOR gate H2 is connected to the input terminal of the driver P3 .
  • the driver P3 is connected to the control electrode of the transistor Q6 through the output terminal c06, and is connected to the control electrode of the transistor Q7 through the output terminal c07. It should be noted here that the NOR gate H2 shown in FIG. 11 can also be replaced by an AND gate.
  • the transistor Q6 when the transistor Q6 is a Pmos transistor, the transistor Q7 is an Nmos transistor, the low-level signal output from the output terminal K of the hysteresis comparator is valid, and the low-level output from the output terminal of the signal modulator T is valid, an AND gate can be used.
  • the implementation is not shown in the figure. It should be noted that the specific structure of the Buck control circuit shown in FIG. 12 is schematic, and the specific structure can be adjusted according to the needs of the application scenario, which is not limited here. In the following, the principle is described by taking the transistor Q6 as a Pmos transistor, the transistor Q7 as an Nmos transistor, and the use of a NOR gate as an example.
  • the hysteresis comparator B When the hysteresis comparator B detects that the voltage value of the output port Vout is lower than the reference signal VT, the hysteresis comparator B outputs a high level signal. At this time, regardless of the signal output by the signal modulator T, it is a low-level signal after performing NOR with the high-level signal output by the hysteresis comparator B. After the signal is processed by the driver P2 and the driver P3, the transistor Q4 is controlled respectively. , The transistor Q6 is turned on, and the power supply terminal Vcc provides the output current to the output port Vout through two paths (that is, the branch where the inductor L1 is located and the branch where the inductor L2 is located) to supplement the load.
  • the hysteresis comparator B When the hysteresis comparator B detects that the voltage value of the output port Vout is higher than the reference signal VT, the hysteresis comparator B outputs a low-level signal. At this time, the signal output from the output terminal of the NOR gate H1 and the NOR gate H2 is controlled by the signal output by the signal modulator T, which is inverse to the signal output by the signal modulator T. During the period when the charging circuit 02 stops charging, the power management system 2 uses a three-phase Buck circuit to supply power to the load.
  • the two-phase Buck circuit can be used as a part of the power supply circuit 02, in the hysteresis comparison Under the control of the device B, the power supply terminal Vcc directly provides output current to the output port Vout through the transistor Q4 and the transistor Q6. Thereby saving the number of transistors.
  • the Buck circuit shown in this embodiment can also use a small-capacity capacitor (for example, a 23uF capacitor), which can reduce the area occupied by the layout.
  • an embodiment of the present application also provides a power management method, which is applied to the power management system shown in any embodiment corresponding to FIG. 1, FIG. 2, FIG. 5, FIG. 8, and FIG. 11.
  • the power management system includes a DC-DC conversion circuit, an input port, an output port, a first control circuit and a power supply circuit.
  • the input port is used to receive input voltage and input current
  • the output port is connected to the load to provide output voltage and output current to the load.
  • the DC-DC conversion circuit is connected between the input port and the output port
  • the first control circuit is connected between the output port and the control end of the power supply circuit
  • the power supply circuit is connected between the input port and the output port.
  • the aforementioned input current may include a first input current and a second input current.
  • FIG. 13 is a flowchart of a power management method 1300 provided by an embodiment of the application.
  • the power management method 1300 specifically includes:
  • step S1301 the DC-DC conversion circuit is configured to obtain a first feedback voltage reflecting the output voltage through the output port, and based on the first feedback voltage and the first reference signal, charge the output port through the input port to adjust the output voltage.
  • the first reference signal is used to control the voltage expected to be output by the current output port, that is, the voltage required by the load to work; it can be the voltage expected to be output, or it can be an adjusted voltage adjusted based on the voltage expected to be output.
  • the second reference signal can be changed, and it changes based on the working conditions of the load.
  • the first reference signal may be the reference signal Vset described in the foregoing embodiments.
  • the first feedback voltage may be the voltage actually output by the output port, or may be the voltage obtained by adjusting the actual output voltage.
  • the first control circuit is configured to obtain the second feedback voltage of the output voltage through the output port, generate a first control signal based on the second feedback voltage and the second reference signal, and provide the first control signal to the supplementary circuit.
  • the second feedback voltage may be the voltage actually output by the output port, or may be the voltage obtained by adjusting the actual output voltage.
  • the second reference signal can be one or two.
  • the second reference signal is used to control the expected output voltage of the current output port, that is, the voltage required by the load to work.
  • the second reference signal includes two, the values of the two second reference signals are different, and the value of one second reference signal is higher than the value of the other second reference signal.
  • the two second reference signals may be, for example, the reference signal VB and the reference signal VT described in the foregoing embodiments.
  • the second reference signal here can be changed, and it changes based on the working conditions of the load.
  • the above-mentioned first control circuit may be a comparator.
  • it can be a single-limit comparator or a double-limit comparator.
  • the comparator When there is one second reference signal, the comparator may be a single-limit comparator.
  • the single-limit comparator usually includes two input terminals, which are used to input the second reference signal and the second feedback voltage, respectively.
  • the comparator may be a double limit comparator.
  • the double-limit comparator is used to compare the second feedback voltage with the two second reference signals respectively, and when detecting that the second feedback voltage is lower than the second reference signal of a lower value, control at least one of the compensation electronic circuits Part of the transistors are turned on, and the input current is converted into a second output current in time and provided to the output port to supplement and regulate the output voltage; when the voltage value of the output port is detected to be higher than the second reference signal with a higher value, the power supply circuit is controlled At least some of the transistors in are turned off to stop generating the second output current.
  • the double limit comparator may be a hysteresis comparator.
  • the hysteresis comparator may be the hysteresis comparator B shown in any one of FIG. 2, FIG. 4A, FIG. 4B, FIG. 5, FIG. 8, and FIG. 11.
  • step S1303 the power supply circuit receives the first control signal, and charges the output port from the input port to the output port based on the first control signal to supplement and adjust the output voltage.
  • the supplementary circuit here can be the supplementary electronic circuit (not shown in the figure) in the supplementary circuit 02 shown in FIG.
  • the circuit other than the hysteresis comparator B in 02 may also include the circuit including the transistor Q4, the transistor Q5 and the inductor L1 in the embodiment shown in FIG. 8, and may also include the circuit including the transistor Q4 in the embodiment shown in FIG. 11 , The circuit including the transistor Q5, the inductor L1, the transistor Q6, the transistor Q7, and the inductor L2.
  • the power supply circuit includes a third transistor, and when the third transistor is turned on, a current path can be formed. Under the control of the control signal output by the first control circuit, when the third transistor is turned on, the input current received by the input port can be provided to the output port to generate a second output current to supplement and regulate the voltage of the output port. When the third transistor is turned off, it stops generating the second output current.
  • the supplementary circuit further includes a fourth transistor and a capacitor.
  • the first control circuit can control the third transistor to turn off and the fourth transistor to turn on. At this time, the input current received by the input port is provided to the capacitor to charge the capacitor.
  • the first control circuit can also control the third transistor to be turned on and the fourth transistor to be turned off.
  • the capacitor is discharged through the third transistor to form a path from the capacitor to the output port. At this time, the second output current is provided to the output port.
  • the DC-DC conversion circuit may include a second control circuit and a power stage circuit.
  • the second control circuit may be the Buck control circuit shown in any one of FIG. 2, FIG. 3, FIG. 5, FIG. 8, FIG. 11, and FIG. 5.
  • the Buck circuit shown in FIGS. 8 and 11 (for example, the circuit composed of the transistor Q1, the transistor Q2, the inductor L0, and the capacitor C1 shown in FIGS. 2, 5, 8 and 11).
  • the second control circuit is used to obtain the first feedback voltage reflecting the output voltage through the output port, and generate at least one second control signal based on the first feedback voltage and the first reference signal; in at least one first power stage circuit
  • Each of the first power stage circuits includes a first transistor, a second transistor, and a first inductor.
  • the first pole of the first transistor is connected to the input port, and the second pole of the first transistor is connected to the first pole of the second transistor,
  • the second pole of the second transistor is connected to the common ground, one end of the first inductor is connected to the second pole of the first transistor, and the other end of the first inductor is connected to the output port;
  • the first transistor (such as Q1, Q4 or Q6) is used Based on at least one second control signal, the second control signal corresponding to the first power stage circuit is charged from the input port to the output port through the first inductor;
  • the second transistor (such as Q2, Q5 or Q7) is used to charge the output port based on the second control signal corresponding to the first power stage.
  • the second control signal of a power stage circuit charges the output port through the first inductor.
  • the first transistor in the second power stage circuit in at least one first power stage circuit is multiplexed by the second power stage circuit and the supplementary circuit; the first transistor in the second power stage circuit
  • the transistor (such as Q1, Q4 or Q6) is specifically used to charge the output port from the input port through the inductor based on the first control signal and the second control signal corresponding to the second power stage circuit.
  • the second control circuit is also used to: obtain the first control signal generated by the first control circuit, and generate the first control signal based on the first control signal and the second control signal corresponding to the second power stage circuit Three control signals; the first transistor (such as Q1, Q4 or Q6) in the second power stage circuit is specifically used to charge the output port from the input port through the inductor based on the third control signal.
  • the power management system further includes a reference signal adjustment circuit; the input end of the reference signal adjustment circuit is connected to the output end of the first control circuit, and the output end of the reference signal adjustment circuit is connected to the DC-DC conversion circuit.
  • the reference signal adjustment circuit is used to adjust the size of the first reference signal based on the control signal output by the first control circuit, and provide the adjusted first reference signal to the DC-DC conversion circuit.
  • FIG. 14 shows a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the electronic device 1400 may be a portable computer (such as a mobile phone), a notebook computer, a wearable electronic device (such as a smart watch), a tablet computer, an augmented reality (AR), a virtual reality (VR) device, or a vehicle-mounted device, etc.
  • the electronic equipment shown in the present application includes the power management system shown in any of the embodiments of FIG. 1, FIG. 2, FIG. 5, FIG. 8, and FIG. 11.
  • the electronic device may also include a power supply component such as a battery, and the power management system can provide the power provided by the power supply component such as the battery to the load, so as to provide the power required for the work of the load.

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Abstract

本申请实施例提供了一种电源管理***和电子设备，电源管理***包直流-直流DC-DC转换电路、第一控制电路、补电电路、输入端口和输出端口；其中，输入端口用于接收输入电压；输出端口用于向负载提供输出电压；DC-DC转换电路，用于通过输入端口向输出端口充电以调节输出电压；第一控制电路，用于通过输出端口获取输出电压的第二反馈电压，基于第二反馈电压以及第二参考信号，生成第一控制信号，并向补电电路提供第一控制信号；补电电路，基于第一控制信号从输入端口向输出端口充电以补充调节输出电压。本申请所示的电源管理***，可以在负载耗电激增时，快速响应负载以为其供电，有利于提高电子设备稳定性和电子设备的续航能力。

Description

电源管理***和电子设备 技术领域
本申请实施例涉及电路技术领域，尤其涉及一种电源管理***和电子设备。
背景技术
随着电子技术的发展，电子设备的性能得到了日益提升，可以为用户提供多样化的功能应用。用于驱动电子设备实现各种功能的处理器等部件的运行速率越来越高。处理器等部件运行速率的提高导致电子设备的功耗也越来越大。为了节省电子设备功耗，电源管理***需要根据处理器等负载的耗电情况对电源管理***的输出电压进行实时的、动态的调节。尤其是在负载功耗激增，导致输出电压瞬间跌落至负载所需电压以下时，电源管理***需要快速响应，以使输出电压稳定在负载所需的电压范围内，避免负载异常掉电。
现有技术中，在输出电压瞬间跌落时，通常需要较长的时间回调至负载所需的电压范围内。如图7(b)所示，其示出了现有技术中输出电压的波形。理想情况下，电源管理***的输出电压稳定在VT～VB范围内。现有技术中，当输出端Vout的输出电压跌落至阈值电压VB之下时，电源管理***需要较长的响应时间(例如2us)，使得输出端Vout的输出电压回调至阈值电压VB。而且响应时间越长，输出电压跌落的幅度越大，回调的时间越长。
综上，现有技术实现动态调节输出电压的方案，当输出电压瞬间跌落至负载所需电压以下时，通常需要较长的时间回调至稳定的电压范围内，从而影响了输出电压的稳定性，进而影响了负载工作的稳定性。
发明内容
本申请提供的电源管理***，可以在保障电能利用率的情况下，在负载耗电激增时，快速响应负载以为其供电，有利于提高电子设备稳定性和电子设备的续航能力。
为达到上述目的，本申请采用如下技术方案：
第一方面，本申请实施例提供一种电源管理***，所述电源管理***包括直流-直流DC-DC转换电路、第一控制电路、补电电路、输入端口和输出端口；其中，所述输入端口用于接收输入电压；所述输出端口连接至负载，用于向负载提供输出电压；所述DC-DC转换电路，连接在所述输入端口和所述输出端口之间，用于通过所述输出端口获取用于反映所述输出电压的第一反馈电压，基于所述第一反馈电压以及第一参考信号，通过所述输入端口向所述输出端口充电以调节所述输出电压；所述第一控制电路，连接在所述输出端口和所述补电电路之间，用于通过所述输出端口获取所述输出电压的第二反馈电压，基于所述第二反馈电压以及第二参考信号，生成第一控制信号，并向所述补电电路提供所述第一控制信号；所述补电电路，连接在所述输入端口和所述输出端口之间，用于：基于所述第一控制信号从所述输入端口向所述输出端口充电以补充调节所述输出电压。
该实现方式中，补电电路例如可以为图1所示的补电电路02中的补电子电路(图中未示出)，也即是说可以为图2、图5任一实施例所示的补电电路02中除迟滞比较器之外的电路，也可以包括图8所示的实施例中晶体管Q4和电感L1在内的电路，也可以包括图11所示的实施例中包括晶体管Q4、电感L1、晶体管Q6以及电感L2在内的电路。第一参考信号例如可以为图2所示的参考信号Vset。
该实现方式中，DC-DC转换电路01对输入端口提供的电压和电流进行动态调节，生成负载工作所需要的电压和电流，以通过输出端口输出给负载。当输出端口的输出电压瞬间跌落至负载所需电压之下时，第一控制电路控制补电电路将输入端口输入的电能提供至输出端口，以为负载补充电能，从而可以抑制输出端口电压的持续跌落，使得手输出端口的电压快速回调至期望的输出电压范围内，有利于提高电源管理***供电的稳定性，进而保障负载工作的稳定性。
在一种可能的实现方式中，所述第一控制电路包括比较器，用于比较所述第二反馈电压和所述第二参考信号以得到所述第一控制信号。
具体的，第一控制电路对第二反馈电压和第二参考信号的比较，在确定出第二反馈电压小于等于第二参考信号时，第一控制信号用于控制补电电路中的晶体管导通，以使补电电路将输入端口提供的电能提供至输出端口，以抑制输出端口电压跌落；第一控制电路确定出第二反馈电压高于第二参考信号时，第一控制信号用于控制补电电路中的晶体管关断，从而停止向输出端口补充电能。由此，将输出端口的输出电压维持在期望输出的电压范围内。
在一种可能的实现方式中，第一控制电路可以为迟滞比较器。
在一种可能的实现方式中，所述第二参考信号包括多个门限信号，用于所述迟滞比较器的迟滞比较。该多个门限信号例如可以包括图2所示的参考信号VT和参考信号VB。
在一种可能的实现方式中，所述DC-DC转换电路包括第二控制电路和至少一个第一功率级电路；所述第二控制电路，用于通过所述输出端口获取用于反映所述输出电压的第一反馈电压，基于所述第一反馈电压以及所述第一参考信号生成至少一个第二控制信号；所述至少一个第一功率级电路中的每个第一功率级电路包括第一晶体管、第二晶体管和电感，所述第一晶体管的第一极连接至所述输入端口，所述第一晶体管的第二极与所述第二晶体管的第一极连接，所述第二晶体管的第二极连接至公共地，所述电感的一端连接至所述第一晶体管的第二极，所述电感的另一端连接至所述输出端口；所述第一晶体管用于基于所述至少一个第二控制信号中对应于所述第一功率级电路的第二控制信号从所述输入端口通过所述电感向所述输出端口充电；所述第二晶体管用于基于所述对应于所述第一功率级电路的第二控制信号通过所述电感向所述输出端口充电。
在该实现方式中，功率级电路例如可以包括但不限于升压-降压式电路或降压电路。DC-DC转换电路可以包括一个功率级电路，也可以包括多个(例如2个或3个)功率级电路。当DC-DC转换电路包括一个功率级电路时，例如图2所示，第一晶体管可以为晶体管Q1，第二晶体管可以为晶体管Q2，电感可以为电感L0，用于控制该功率级电路的控制信号即为Buck控制电路的控制端c01和c02输出的信号。当DC-DC转换电路包括2个功率级电路时，例如图8所示，其中一个功率级电路可以包括晶体管Q1、晶体管Q2和电感L0，另外一个功率级电路可以包括晶体管Q4、晶体管Q5和电感L1。此时，第一晶体 管可以包括晶体管Q1和晶体管Q4，第二晶体管可以包括晶体管Q2和晶体管Q5，电感可以包括电感L0和电感L1。当DC-DC转换电路包括3个功率级电路时，例如图11所示，其中一个功率级电路可以包括晶体管Q1、晶体管Q2和电感L0，其中一个功率级电路可以包括晶体管Q4、晶体管Q5和电感L1，另外一个功率级电路可以包括晶体管Q6、晶体管Q7和电感L2。
基于第一方面，在一种可能的实现方式中，所述补电电路包括第三晶体管；所述第三晶体管的控制极用于接收所述第一控制信号，所述第三晶体管的第一极连接至所述输入端口，所述第三晶体管的第二极连接至所述输出端口，所述第三晶体管用于基于所述第一控制信号从所述输入端口向所述输出端口充电。
在该实现方式中，第三晶体管例如可以为图2所示的晶体管Q4。当第三晶体管导通时，输入端口输入的电能通过第三晶体管提供至输出端口，以提高输出端口的电压；当第三晶体管关断时，停止向输出端口充电。
基于第一方面，在一种可能的实现方式中，所述补电电路包括第三晶体管、第四晶体管和电容；所述第三晶体管的控制极和所述第四晶体管的控制极分别用于接收所述第一控制信号，所述第三晶体管的第一极连接至所述第四晶体管的第二极，所述第三晶体管的第二极连接至所述输出端口，所述第四晶体管的第一极连接至所述输入端口；所述电容的第一极连接至所述第三晶体管的第一极，所述电容的第二极连接至公共地；所述第四晶体管用于基于所述第一控制信号从所述输入端口向所述电容充电；所述第三晶体管用于基于所述第一控制信号从所述电容向所述输出端口充电。
在该实现方式中，第三晶体管例如可以为图5所示的晶体管Q4，第四晶体管例如可以为图5所示的晶体管Q3，电容例如可以为图5所示的电容C2。
第三晶体管导通、第四晶体管关断时，输出端口输入的电压提供至电容，以为电容充电；第三晶体管关断、第四晶体管导通时，电容将存储的电荷提供至输出端口，以向输出端口充电，从而调节输出端口的输出电压。
基于第一方面，在一种可能的实现方式中，所述至少一个第一功率级电路中的第二功率级电路中的所述第一晶体管被所述第二功率级电路和所述补电电路所复用；所述第二功率级电路中的所述第一晶体管具体用于基于所述第一控制信号和对应于所述第二功率级电路的所述第二控制信号，从所述输入端口通过所述电感向所述输出端口充电。
在该实现方式中，当DC-DC转换电路包括多个功率级电路时，其中部分功率级电路中的第一晶体管被该功率级电路和补电电路复用。这里的复用是指，当输出端口输出的电压在期望输出的电压范围内时，该部分功率级电路中的第一晶体管作为DC-DC转换电路的一部分，受控于第二控制信号，向输出端口充电；当输出端口的电压跌落至负载所需电压之下时，该部分功率级电路中的第一晶体管作为补电电路的一部分，受控于第一控制信号，向输出端口充电。
其中，上述第二功率级电路例如可以包括图8所示的晶体管Q4、晶体管Q5和电感L1形成的电路，还可以包括图11所示的晶体管Q6、晶体管Q7和电感L2形成的电路。此时，被复用的第一晶体管可以包括图11所示的晶体管Q4和晶体管Q6。
基于第一方面，在一种可能的实现方式中，所述第二控制电路还用于：获取所述第一控制信号，基于所述第一控制信号和对应于所述第二功率级电路的所述第二控制信号，生 成第三控制信号；所述第二功率级电路中的所述第一晶体管具体用于基于所述第三控制信号，从所述输入端口通过所述电感向所述输出端口充电。
基于第一方面，在一种可能的实现方式中，所述第二控制电路包括误差放大器、信号调制器和至少一个驱动器；所述误差放大器将所述第一反馈电压与所述第一参考信号之间的误差做放大得到放大信号；所述信号调制器用于接收所述放大信号，并生成所述至少一个调制信号；所述至少一个驱动器中每个驱动器，用于接收所述调制信号并生成所述至少一个第二控制信号中的一个第二控制信号。
基于第一方面，在一种可能的实现方式中，所述电源管理***还包括参考信号调节电路，连接在所述第一控制电路和所述DC-DC转换电路之间；所述参考信号调节电路用于：基于所述第一控制信号，调节所述第一参考信号的大小，将调节后的第一参考信号提供至所述DC-DC转换电路。
在某些场景中，由于补电电路通过输出端口向负载补电的结果，使得输出端口的电压升高；而第二控制电路的第一输入端所接收到的输出端口的电压有可能是电压补偿后的值，该值与第二参考信号之间的差值通常较小。这就使得第二控制电路降低供电周期内的供电时长以降低输出电能。此时，如果补电电路不持续供电或者电容放电后所剩的电压不足以支撑负载工作时，通常出现供电不足的情况。
通过设置信号调节电路来调节第一参考信号的大小，可以在补电电路向输出端口提供输出电流时，增大第一参考信号的值，以增大输出端口的电压与第一参考信号之间的差值，避免DC-DC转换电路降低供电周期内的供电时长以减小供电量；在补电电路停止向输出端口提供输出电流时，说明电压回调至期望输出电压的上限，通过减小第一参考信号的值，以减小输出端口的电压与第一参考信号之间的差值，避免DC-DC转换电路保持较高的供电量，造成电能浪费。
第二方面，本申请实施例提供一种电子设备，包括如第一方面任意一种实现方式所述的电源管理***。
第三方面，本申请实施例提供一种电源管理方法，该电源管理方法应用于如第一方面任意一种实现方式所述的电源管理***。该电源管理方法包括：电源管理***中的DC-DC转换电路通过所述输出端口获取用于反映所述输出电压的第一反馈电压，基于所述第一反馈电压以及第一参考信号，通过所述输入端口向所述输出端口充电以调节所述输出电压；电源管理***中的第一控制电路用于通过所述输出端口获取所述输出电压的第二反馈电压，基于所述第二反馈电压以及第二参考信号，生成第一控制信号，并向所述补电电路提供所述第一控制信号；电源管理***中的补电电路基于所述第一控制信号从所述输入端口向所述输出端口充电以补充调节所述输出电压。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的电源管理***的一个应用场景示意图；
图2是本申请实施例提供的电源管理***的一个结构示意图；
图3是本申请实施例提供的Buck控制电路的一个内部结构示意图；
图4A是本申请实施例提供的迟滞比较器的一个内部结构示意图；
图4B是本申请实施例提供的迟滞比较器的又一个内部结构示意图；
图5是本申请实施例提供的电源管理***的又一个结构示意图；
图6是本申请实施例提供的参考信号调节电路的一个结构示意图；
图7是本申请实施例提供的如图5所示的电源管理***输出端与相关技术中电源管理***输出端的波形对比图；
图8是本申请实施例提供的电源管理***的又一个结构示意图；
图9是本申请实施例提供的Buck控制电路的又一个内部结构示意图；
图10是本申请实施例提供的补电电路在补电期间的等效电路图；
图11是本申请实施例提供的电源管理***的又一个结构示意图；
图12是本申请实施例提供的Buck控制电路的又一个内部结构示意图；
图13是本申请实施例提供的电源管理方法的一个流程图；
图14是本申请实施例提供的电子设备的一个结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本文所提及的"第一"、"第二"以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，"一个"或者"一"等类似词语也不表示数量限制，而是表示存在至少一个。"连接"或者"相连"等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的，等同于广义上的耦合或电性联通。
在本文中提及的"模块"通常是指按照逻辑划分的功能性结构，该"模块"可以由纯硬件实现，或者，软硬件的结合实现。在本申请实施中，“和/或”描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示:单独存在A，同时存在A和B，单独存在B这三种情况。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参考图1，其示出了本申请实施例提供的电源管理***的一个应用场景示意图。在 图1所示的应用场景示意图中，包括供电***1、电源管理***2和负载3。供电***1与电源管理***2的输入端口Vin连接，以为电源管理***提供电能。其中，供电***1可以为有源电路，其通常包括电池、有源器件等。供电***1也可以为电网供电传输线和外部电源适配器，电源管理***2通过外部电源适配器与电网供电传输线连接，从而，使得电网通过电源适配器将电能传输至电源管理***2。电源管理***2的输出端口Vout与负载3连接，用于将供电***1提供的电能传输至负载3，以向负载3提供运行所需要的电能。负载3可以为各种处理器或其他类型的器件，例如图像处理器(GPU)，中央处理器(CPU)、运算加速器或各类数字电路和模拟电路等。负载3还可以为各种集成电路芯片，该集成电路芯片包括不限于人工智能芯片、图像处理芯片等。在此不做限定。
如图1所示，电源管理***2包括DC-DC(Direct Current-Direct Current，直流-直流)转换电路01和补电电路02。
其中，DC-DC转换电路01连接至电源管理***2的输入端口Vin和输出端口Vout。在负载3工作过程中，DC-DC转换电路01基于输出端口Vout的电性参数(例如电压值、电流值、功率值)的第一反馈电压和预先设置的第一参考信号，调节输入至负载的电压和电流，以为负载3供电。
第一参考信号用于控制当前输出端口Vout期望输出的电压，也即负载3工作所需要的电压；其可以是期望输出的电压，也可以是基于期望输出的电压而调节的调节后的电压。
第一反馈电压可以是输出端口Vout实际输出的电压，也可以是对实际输出的电压进行调节而得到电压。
在一种可能的实现方式中，DC-DC转换电路01可以包括第一控制电路和功率级电路。其中，第一控制电路可以通过分立器件实现，也可以通过可编程器件实现。可编程器件包括但不限于可编程逻辑控制器(PLC，Programmable Logic Controller)、数字信号处理器(DSP，digital signal processor)、信号发生器等。功率级电路例如包括但不限于：升压-降压(BOOST-BUCK)式电路、或降压(BUCK)电路。具体的，第一控制电路可以基于输出端口Vout的电性参数(例如，电流值、电压值或功率值)和第一参考信号，调节功率级电路中晶体管的占空比，以控制向负载3提供的电能(例如负载运行所需的电压和电流)。
补电电路02同样连接至电源管理***2的输入端口Vin和输出端口Vout。补电电路02基于输出端口Vout的输出电压的第二反馈电压、第二参考信号和第三参考信号，在输出电压低于第二参考信号时，通过输出端口Vout向负载提供输出电流；在输出电压高于第三参考信号时，停止向负载提供输出电流。
第二反馈电压可以是输出端口Vout实际输出的电压，也可以是对实际输出的电压进行调节而得到电压。
第二参考信号和第三参考信号用于控制当前输出端口Vout期望输出的电压，也即负载3工作所需要的电压。第二参考信号和第三参考信号可以相同，也可以不同。当第二参考信号和第三参考信号不同时，第三参考信号的值高于第二参考信号的值。具体的，当第二参考信号和第三参考信号相同时，其可以是期望输出的电压，也可以是基于期望输出的电压而调节的调节后的电压。当第二参考信号和第三参考信号不同时，第二参考信号用于控制输出端口Vout期望输出的电压的下限，第三参考信号用于控制输出端口Vout期望输 出的电压的下限。需要说明的是，第二参考信号和/或第三参考信号是可以变动的，其基于负载3的工作情况而改变。例如，当负载3处于低功耗状态时，负载3工作的电压较低，此时第二参考信号较小；当负载3处于高功耗状态时，负载3工作的电压较高，此时第二参考信号较大。
在一种可能的实现方式中，补电电路02包括第二控制电路和补电子电路。其中，第二控制电路可以通过分立器件实现，也可以通过可编程器件实现。可编程器件包括但不限于PLC、DSP、信号发生器等。第二控制电路在检测到第二反馈电压低于上述第二参考信号时，控制补电子电路中的至少部分晶体管导通，从而将输入端口Vin输入的电流转化为输出电流，及时通过输出端口Vout提供给负载3；第二控制电路在检测到第二反馈电压高于上述第三参考信号时，控制补电子电路中的至少部分晶体管关断，从而停止向负载3提供输出电流。
在一种可能的实现方式中，上述第二控制电路包括比较器。
具体的，当第二参考信号和第三参考信号相同时，该比较器可以为单限比较器。单限比较器通常包括两个输入端，分别用于输入第二参考信号(或第三参考信号)和第二反馈电压。
当第二参考信号和第三参考信号不同时，该比较器可以为双限比较器。
具体的，该双限比较器用于：将第二反馈电压分别与第二参考信号和第三参考信号进行比较，在检测到第二反馈电压低于第二参考信号时，控制补电子电路中的至少部分晶体管导通，及时通过输出端口Vout向负载3补电；在检测到输出端口Vout的电压值高于上述第三参考信号时，控制补电子电路中的至少部分晶体管关断，以停止向负载3补电。
进一步的，该双限比较器可以为迟滞比较器。
本实施例中，在电源管理***2正常运行时，DC-DC转换电路01对输入端口Vin提供的电压和电流进行动态调节，生成负载工作所需要的电压和电流，以通过输出端口Vout输出给负载。在某些场景中，例如，负载3功耗激增、输出电流供给不足时，导致输出端口Vout输出的电压瞬间跌落，其通常会跌落至负载3运行所需要的电压以下。此时，补电电路02从输入端口Vin获取输入电流，并将该输入电流转换成输出电流，及时向负载3补电。也即是说，此时补电电路02提前向负载3提供输出电流，待DC-DC转换电路01响应后，和DC-DC转换电路01采用并联的方式同时向负载3提供输出电流。从而，可以快速提高输出电压的回调时间，有利于提高电源管理***供电的稳定性，进而保障负载工作的稳定性。
下面，以DC-DC转换电路01中的功率级电路为Buck电路、DC-DC转换电路01中的第一控制电路为Buck控制电路为例，以补电电路02中的第二控制电路为迟滞比较器为例，结合图2-图12，对图1所示的电源管理***2的结构以及工作原理进行详细说明。需要说明的是，以下各实施例中，供电端Vcc也即图1所示的输入端口Vin，其与供电***1的输出端连接。为了使得下面各实施例描述更加清楚，图2-图12中，供电端(也即图1所示的输入端口Vin)均由附图标记Vcc表示。
关于图1中的电源管理***2，图2示出了本申请实施例提供的电源管理***的一个结构示意图。如图2所示，电源管理***2包括Buck控制电路、晶体管Q1、晶体管Q2、电感L0、电容C1、补电电路02、供电端Vcc和输出端口Vout。其中，晶体管Q1、晶体 管Q2、电感L0和电容C1作为一相Buck电路工作。
具体的，晶体管Q1的控制极、晶体管Q2的控制极分别连接至Buck控制电路的输出端c01和输出端c02，晶体管Q1的第一极连接至供电端Vcc；晶体管Q2的第二极连接至公共地Gnd；电感L0的一端与晶体管Q1的第二极、晶体管Q2的第一极连接，电感L0的另一端连接至输出端口Vout；电容C1的第一电极连接至输出端Vout，第二电极连接至公共地Gnd。Buck控制电路的输入端Via与输出端口Vout连接，Buck控制电路的输入端Vib用于输入参考信号Vset。这里，参考信号Vset用于控制输出端口Vout期望输出的电压信号。当输出端口Vout的电压值的反馈值低于参考信号Vset时，说明供电不足，需要向负载3提供更多电能；当输出端口Vout的电压值的反馈值高于参考信号Vset时，说明供电过多，需要降低向负载3提供的电能。所述反馈值可以等于输出端口Vout的电压值或者是反映输出端口Vout的电压值的一个其他电压值，如输出端口Vout的电压值的分压值，本实施例对此不限定。需要说明的时，参考信号Vset是可以变动的，其基于负载当前的工作情况以及所需要的电压而改变。这里需要说明的是，晶体管Q1与晶体管Q2的导通时间不同。也即是说，晶体管Q1导通时，晶体管Q2关断；晶体管Q1关断时，晶体管Q2导通。晶体管Q1和晶体管Q2可以为Nmos晶体管，也可以为Pmos晶体管。通常情况下，晶体管Q1为Pmos晶体管，晶体管Q2为Nmos晶体管。当晶体管Q1和晶体管Q2为相同类型的晶体管时，输出端c02与晶体管Q2之间设置有反相器，用于对驱动信号进行反相。电感L0可以为较大容量电感，例如电感容量可以为470nH。
Buck控制电路可以实时获取输出端口Vout的电压值的反馈值，并基于获取到的反馈值与参考信号Vset之间的差值，控制晶体管Q1的导通时长和晶体管Q2的导通时长，以控制供电端Vcc向负载提供的电能。例如，当反馈值小于参考电压值，且二者之差大于预设阈值时，可以控制晶体管Q1在一个供电周期内全导通，控制晶体管Q2在该供电周期内完全关断；再例如，当反馈值小于参考电压值，但二者之间的差值未达到预设阈值时，可以控制晶体管Q1和晶体管Q2在一个供电周期内的导通时间各占百分之五十。下文均以Buck控制电路获取的反馈值就是输出端口Vout的电压值本身为例做说明，但不用于限定。
Buck控制电路的具体结构可以如图3所示。Buck控制电路包括误差放大器EA、信号调制器T以及驱动器P1。其中，误差放大器EA的一个输入端连接至输出端口Vout，另外一个输入端用于输入参考信号Vset，误差放大器EA的输出端连接至信号调制器T的输入端，信号调制器T的输出端连接至驱动器P1的输入端，驱动器P1通过输出端c01与晶体管Q1的控制极连接，驱动器P1通过输出端c02与晶体管Q2的控制极连接。误差放大器EA用于将输出端口Vout的电压值与参考信号Vset进行比较，将二者之间的差值进行放大后提供至信号调制器T。信号调制器T用于将误差信号调制成脉冲信号，以控制晶体管Q1、晶体管Q2导通或关断。信号调制器T既可以为脉冲宽度调制器(PWM，Pulse Width Modulation)，也可以为脉冲频率调制器(PFM，Pulse Frequency Modulation)。当信号调制器T为脉冲宽度调制器时，脉冲宽度调制器基于误差信号的大小调整一个开关周期内高电平与低电平之间的占空比以控制供电时长；当信号调制器T为脉冲频率调制器时，脉冲频率调制器通过固定晶体管Q1的导通时间或晶体管Q2的导通时间，基于误差信号的大小调整开关周期的时长以控制供电时长。驱动器P1用于对信号调制器T输入的 信号进行诸如脉冲幅度提高、对脉冲上升沿和下降沿优化(例如降低脉冲上升时间和下降时间以使晶体管快速导通和关断)等处理，生成驱动信号，以控制晶体管Q1、晶体管Q2导通或关断。需要说明的是，图3所示的Buck控制电路的具体结构为示意性的，其具体结构还可以根据应用场景的需要调整。
继续参考图2，补电电路02包括迟滞比较器B和晶体管Q4。如图2所示的迟滞比较器B包括输入端V1、输入端V2和输入端V3三个输入端。其中，迟滞比较器B的输入端V1与输出端口Vout连接，迟滞比较器B的输入端V2用于输入参考信号VB，迟滞比较器B的输入端V3用于输入参考信号VT。此外，迟滞比较器B的输出端K连接至晶体管Q4的控制极，晶体管Q4的第一极连接至供电端Vcc，晶体管Q4的第二极连接至输出端口Vout。
通常，负载基于特定电压运行，输出端口Vout输出的电压需要稳定在该特定电压上下浮动范围内，以保证负载运行的稳定。上述参考信号VT用于控制输出端口Vout期望输出的电压信号的上限，参考信号VB用于控制输出端口Vout期望输出的电压信号的下限，参考信号VB的值小于参考信号VT的值。
在一种可能的实现方式中，参考信号VT和参考信号VB可以基于参考信号Vset来设置。具体的，参考信号VT可以为参考信号Vset的值与第一偏移量ΔV1之和，参考信号VB可以为参考信号Vset的值与第二偏移量ΔV2之差。第一偏移量ΔV1和第二偏移量ΔV2是预先设置。
在本实施例中，迟滞比较器B可以实时获取输出端口Vout电压值，然后将输出端口Vout电压值与参考信号VT以及参考信号VB进行比较。当输出端口Vout电压值低于参考信号VB时，需要生成输出电流，以使输出端口Vout输出的电压稳定在预设范围内。此时，可以控制晶体管Q4导通，将供电端Vcc提供的输入电流提供至输出端口Vout，作为输出电流提供给负载。当迟滞比较器B检测到输出端口Vout电压值高于参考信号VT时，可以控制晶体管Q4关闭。当迟滞比较器B再一次检测到输出端口Vout电压值低于参考信号VT时，控制晶体管Q4导通。
本实施例中，一种迟滞比较器的电路结构如图4A所示。其中，迟滞比较器B包括集成运放F1、集成运放F2和D触发器。
其中，集成运放F1的同相输入端和集成运放F2的反相输入端分别连接至输出端口Vout。集成运放F1的反相输入端用于输入参考信号VT，集成运放F2的同相输入端用于输入参考信号VB。集成运放F1的输出端与D触发器的复位端Rst连接，集成运放F2的输出端与D触发器的时钟信号端CP连接。D触发器的输出端Q为迟滞比较器B的输出端K，用于输出控制信号。
以D触发器的时钟信号端CP由低电平向高电平跳变时、输入端D输入高电平信号为例，复位端Rst高电平信号有效为例，以及晶体管Q4为Nmos晶体管为例，对包括图4A所示的迟滞比较器B的补电电路02的工作原理描述。
当输出端口Vout的电压高于参考信号VT时，集成运放F1输出高电平信号，集成运放F2输出低电平信号，此时D触发器输出低电平信号，晶体管Q4截止。当输出端口Vout的电压由高于参考信号VT逐渐降低至低于参考信号VB时，集成运放F1输出低电平信号，集成运放F2输出的信号由低电平跳变为高电平，此时D触发器导通，D触发器将输 入端D输入的高电平信号传输至输出端Q，晶体管Q4导通。当输出端口Vout的电压回调至参考信号VB时，D触发器的输出端Q保持输出高电平信号不变。当输出端口Vout的电压由低于参考信号VB逐渐调高至高于参考信号VT时，集成运放F1输出的信号由低电平跳变为高电平、集成运放F2输出的信号为低电平，此时D触发器复位，D触发器的输出端Q输出低电平信号，晶体管Q4截止。
本实施例中，一种迟滞比较器的电路结构还可以如图4B所示。与图4A所示的迟滞比较器的电路结构不同的是，图4B所示的迟滞比较器的电路结构包括两个输入端。其通过调节输入的参考电压信号Vref来产生参考信号VT和参考信号VB。具体的，图4A所示的迟滞比较器B包括集成运放、电阻R1、电阻R2。集成运放的反相输入端与输出端口Vout连接，集成运放的正向输入端与电阻R1的一端连接，电阻R1的另一端用于输入参考电压信号Vref，电阻R2所在的支路作为反馈通路设置于集成运放的正向输入端和输出端之间，集成运放的输出端K与晶体管Q4连接。
其中，迟滞比较器B的参数设置满足以下等式(1)、(2)：
Vref×R2/(R1+R2)＝VB             (1)
Vcc×R1/(R1+R2)+Vref×R2/(R1+R2)＝VT    (2)
这里，参考信号VT和参考信号VB是基于负载运行功率、负载运行所需要的电压来确定的，Vcc为外部供电***的电压值，通过调节电阻R1、电阻R2的阻值即可确定出参考电压信号Vref的电压值。当参考电压信号Vref确定后，如图4B所示的迟滞比较器B即可产生参考信号VT和参考信号VB。此外，由于参考信号VT和参考信号VB需要基于负载运行所需要的电压动态可调，此时通过调节电阻R1、电阻R2的阻值，即可改变参考电压信号Vref的电压值大小，从而调节参考信号VT和参考信号VB的大小。
需要说明的是，图4A、图4B所示的迟滞比较器B的具体结构为示意性的，其具体结构还可以根据应用场景的需要调整。
传统技术中的电源管理***通常不设置补电电路02，在输出端口Vout的输出电压瞬态跌落时，其通过提高晶体管Q1、晶体管Q2的开关频率来提高瞬态响应时间。Buck电路通常基于供电周期向负载供电，当负载电量过耗时，Buck电路需要在当前供电周期执行完毕后，在下一供电周期更改控制信号的占空比以提高晶体管Q1导通时长，进而增大供电量从而使得输出电压回调。传统技术中，通常通过降低供电周期时长、提高晶体管Q1、晶体管Q2的开关频率来提高瞬态响应时间。例如，将开关率由2MHz提高为4MHz。晶体管Q1、晶体管Q2是耗能元件，由于其自身寄生电阻的存在，随着其开通或关断时间增多，其能量耗损越大。可见，通过提高晶体管Q1、晶体管Q2的开关频率的方式换取Buck电路的瞬态响应，大大降低了能量转换效率。传统技术中的电源管理***还通过降低电感L0的电感量来提高瞬态响应时间。电感为储能元件，由于电感L0上电流不能突变，在外部供电***停止供电后，电感上存储的能量可以将电能提供给负载以为负载供电。电感量越大，在一个开关周期内其所能存储的能量越多。当降低电感L0的电感量时，也即降低了一个供电周期内所能存储的能量。当向负载提供相同的能量时，需要提高参考信号Vset的值以增大供电端提供的能量。这样一来，当负载消耗能量小于Buck电路输入的能量时，造成电能浪费，降低了能量使用率。而本申请通过设置补电电路02，能够在负载能耗过大以将输出端口Vout的电压拉低的瞬间及时向负载补电，在输出端口Vout的电压回升后停 止补电，避免负载由于供电不足导致异常断电等情况。与传统技术相比，本申请实施例所示的Buck电路，可以减少晶体管Q1、晶体管Q2的开关频率，也不需要降低电感L0的能量值，从而保证了电能使用效率。此外，本申请实施例中，可以减少Buck电路中的电容C1的容量(例如本实施例中可以采用23uF的电容，而传统Buck电路中需要采用60uF的电容)，有利于简化版图面积。
请继续参考图5，其示出了如图1所示的电源管理***2的又一个实施例的结构示意图。在图5中，电源管理***2包括DC-DC转换电路01和补电电路02。DC-DC转换电路01包括Buck控制电路、晶体管Q1、晶体管Q2、电感L0、电容C1，补电电路02包括迟滞比较器B和晶体管Q4。其中，Buck控制电路的内部结构参考图3所示的相关描述，迟滞比较器B的内部结构可以参考图4A或者图4B所示的相关描述，电路与元件之间的连接关系可以参考图2所示的实施例的相关描述，在此不再赘述。
与图2所示的电源管理***2不同的是，本实施例中，补电电路02还包括晶体管Q3以及电容C2。其中，晶体管Q3的控制极连接至迟滞比较器B的输出端K，晶体管Q4的第一极与晶体管Q3的第二极以及电容C2的一端连接，晶体管Q4的第二极连接至输出端口Vout，电容C2的另一端连接至公共地Gnd。这里，晶体管Q3和晶体管Q4具有不同得导通时间。当晶体管Q3导通时，晶体管Q4关闭；晶体管Q4导通时，晶体管Q3关闭。晶体管Q3和晶体管Q4可以为相同类型的晶体管(例如Pmos晶体管或Nmos晶体管)，也可以为不同类型的晶体管。当二者为相同类型的晶体管时，在输出端K与晶体管Q3或者晶体管Q4之间设置有反相器。
在本实施例中，迟滞比较器B可以实时获取输出端口Vout电压值，然后将输出端口Vout电压值与参考信号VT以及参考信号VB进行比较。当输出端口Vout电压值高于参考信号VT时，控制晶体管Q3导通、控制晶体管Q4关闭。此时，外部供电***通过晶体管Q3给电容C2充电；当迟滞比较器B检测到输出端口Vout电压值低于参考信号VB时，需要生成输出电流，以使输出端口Vout输出的电压稳定在预设范围内。此时，可以控制晶体管Q3关闭，控制晶体管Q4导通，电容C2通过晶体管Q4向负载快速补电。当迟滞比较器B再一次检测到输出端口Vout电压值高于参考信号VT时，控制晶体管Q3导通、控制晶体管Q4关闭，以向电容C2充电。
从图5所示的电源管理***2可以看出，与图2所示的电源管理***2不同的是，在输出端口Vout的电压低于参考信号VB时，没有利用供电端Vcc直接向输出端口Vout提供输出电流，而是通过外部供电***对电容C2预充电，在输出端口Vout的电压低于参考信号VB时，通过电容C2放电来生成输出电流。
在某些场景中，由于补电电路02向输出端口Vout提供输出电流的结果，使得输出端口Vout的电压升高；而Buck控制电路的输入端Via所接收到的输出端口Vout的电压有可能是电压补偿后的值，该值与参考信号Vset之间的差值通常较小。这就使得Buck控制电路降低供电周期内的供电时长以降低输出电能(降低输出电流或输出电压)。此时，如果补电电路02不持续供电或者电容C2放电后所剩的电压不足以支撑负载工作时，通常出现供电不足的情况。
为了消除补电电路02对Buck电路的影响，在本实施例一些可选的实现方式中，还可以设置有参考信号调节电路03。具体的，参考信号调节电路03的输入端连接至迟滞比较 器B的输出端K，参考信号调节电路03的输出端连接至Bcuk控制电路的输入端Vib。参考信号调节电路03用于在补电电路02补电期间，提高输入至Buck控制电路中的参考信号Vset的值。其中，参考信号Vset的值提高的时长大于等于Buck控制电路响应负载电能过耗的时间。
通过设置信号调节电路03来调节参考信号Vset的大小，可以在补电电路02向输出端口Vout提供输出电流时，增大参考信号Vset的值，以增大输出端口Vout的电压与参考信号Vset之间的差值，避免DC-DC转换电路01降低供电周期内的供电时长以减小供电量；在补电电路02停止向输出端口Vout提供输出电流时，说明电压回调至期望输出电压的上限，通过减小参考信号Vset的值，以减小输出端口Vout的电压与参考信号Vset之间的差值，避免DC-DC转换电路01保持较高的供电量，造成电能浪费。
参考信号调节电路03的具体结构可以参考图6。参考信号调节电路03可以包括D触发器、计数器、参考信号寄存器A1、参考信号寄存器A2以及参考电压分压网络。其中，D触发器的时钟信号端CP与迟滞比较器B的输出端K连接，D触发器的输入端D用于输入传输信号，D触发器的复位端Rst与计数器的输出端连接，D触发器的输出端Q输出的信号用于控制参考信号寄存器A1或者参考信号寄存器A2连接至参考电压分压网络的输入端；参考电压分压网络的输出端连接至Buck控制电路的输入端Vib。计数器的控制端Gate连接至D触发器的输出端Q，计数器的时钟信号端Clk用于输入时钟信号。
D触发器为边沿触发器，当D触发器的时钟信号端CP输入的信号从无效变为有效时(例如由低电平转向高电平时)，也即输入信号出现上升沿时，D触发器将输入端D输入的信号提供至输出端Q，以从输出端Q输出。当D触发器的复位端Rst接收到复位信号时，D触发器复位，输出端Q输出初始设置信号。具体的，当D触发器复位使得输出端Q输出初始设置信号逻辑“1”时，D触发器的输入端D用于输入逻辑“0”；当D触发器复位使得输出端Q输出初始设置信号逻辑“0”时，D触发器的输入端D用于输入逻辑“1”。图6中示意性的示出了D触发器的输入端D输入逻辑“1”、D触发器复位使得输出端Q输出初始设置信号逻辑“0的情况。
基于图6所示的参考信号调节电路03的结构，迟滞比较器B的输出端K输出的信号从低电平向高电平跳变时，触发晶体管Q4导通，此时晶体管Q4为Nmos晶体管；当晶体管Q4为Pmos晶体管时，可以在迟滞比较器B的输出端与晶体管Q4之间设置反相器。D触发器的输入端D输入高电平信号或者“逻辑1”信号。当D触发器复位时，D触发器的输出端Q输出“逻辑0”。
参考信号寄存器A1存储有参考信号Vset的第一电压值，参考信号寄存器A2存储有参考信号Vset的第二电压值。其中第一电压值高于第二电压值，所高出的数值基于输出端口Vout在补电期间所抬高的电压而定。
参考电压分压网络用于将第一电压值或者第二电压值转换为模拟信号。这里的参考电压分压网络可以为数模转换电路。具体的，参考电压分压网络可以包括稳压芯片、单路输入多路输出的选择器和分压排阻。其中，稳压芯片用于输出特定大小(例如3V)的电压。稳压芯片的输出端与选择器的输入端连接。第一电压信号或第二电压信号可以控制选择器，以使选择器的输入端与分压排阻的其中一个分压端连接，通过分压排阻的分压得到相应的模拟电压信号。
在迟滞比较器B的输出端输出的信号由低电平转向高电平时，D触发器的输入端D输入“逻辑1”。在“逻辑1”的控制下，参考信号寄存器A1与参考电压分压网络连接，参考电压分压网络对参考信号寄存器A1存储的第一电压值进行处理后生成模拟电压信号提供至Buck控制电路的输入端Vib；同时，计数器开始计时。待计数器计时到ΔT时间时，向D触发器发送复位信号。D触发器在接收到复位信号后，输出端Q输出“逻辑0”。此时，参考信号寄存器A2与参考电压分压网络连接，参考电压分压网络对参考信号寄存器A2存储的第二电压值进行处理后生成模拟电压信号提供至Buck控制电路的输入端Vib。这里ΔT时间大于等于Buck控制电路响应负载电能过耗的时间。
图7中的(a)示出了设置补电电路02后输出端口Vout输出的电压波形，图7中的(b)示出了未设置补电电路02时输出端口Vout输出的电压波形。其中，VB是参考信号Vset与偏移量ΔV2之差；VT是参考信号Vset与偏移量ΔV1之和。从图7中可以看出，未设置补电电路02时，输出端口Vout输出的电压波形在某一瞬间远远跌落至VB以下，而输出端口Vout的电压恢复至VB以上需要较长的时间，例如2us。在设置补电电路02之后，在输出端口Vout的电压达到电压下限VB时，迟滞比较器B控制晶体管Q4导通，从而补电电路02输出端口Vout提供输出电流，输出端口Vout电压回升；在输出端口Vout的电压达到VT时，迟滞比较器B控制晶体管Q4关断，补电电路02停止输出电流。由此，输出端口Vout输出的电压被稳定的限制在VB-VT范围内。提高输出端口Vout输出电压的稳定性。
请继续参考图8，其示出了如图1所示的电源管理***2的又一个实施例的结构示意图。在图8中，电源管理***2包括Buck控制电路、迟滞比较器B、晶体管Q1、晶体管Q2、晶体管Q4、晶体管Q5、电感L0、电感L1和电容C1。其中，晶体管Q1、晶体管Q2、电感L0和电容C1属于一相Buck电路。在本实施例中，与图2、图5所示的电源管理***2不同的是，晶体管Q4、晶体管Q5、电感L1和电容C1可以属于另外一相Buck电路。也即本实施例所示的Buck电路为双相Buck电路。补电电路02和DC-DC转换电路01复用晶体管Q4、晶体管Q5和电感L1。
具体的，迟滞比较器B的输出端K连接至Buck控制电路的输入端Vic，晶体管Q4的控制极连接至Buck控制电路的输出端c04，晶体管Q5的控制极连接至Buck控制电路的输出端c05，晶体管Q4的第一极连接至供电端Vcc，晶体管Q5的第二极连接至公共地Gnd，晶体管Q4的第二极、晶体管Q5的第一极连接至电感L1的其中一端，电感L1的另一端连接至输出端口Vout。迟滞比较器B的内部结构可以参考图4A或图4B所示的内部结构。晶体管Q4和晶体管Q5具有不同得导通时间。
从图8中可以看出，与上述各实施例不同的是，本实施例中迟滞比较器B的输出端K没有直接与晶体管Q4、晶体管Q5的控制端连接，而是通过Buck控制电路与晶体管Q4、晶体管Q5的控制端连接。从而，当输出端口Vout的电压低于参考信号VB时，晶体管Q4导通，补电电路02向输出端口Vout提供输出电流；当输出端口Vout的电压高于参考信号VT时，晶体管Q4关闭，补电电路02停止提供电流，此时，晶体管Q4、晶体管Q5和电感L1在Buck控制电路的控制下作为一相Buck工作。
基于图8所示的电源管理***2，Buck控制电路的具体结构可以如图9所示。在图9中，Buck控制电路包括误差放大器EA、信号调制器T、驱动器P1、驱动器P2以及或非 门H1。其中，误差放大器EA的一个输入端连接至输出端口Vout，另外一个输入端用于输入参考信号Vset，误差放大器EA的输出端连接至信号调制器T的输入端，信号调制器T的其中一个输出端连接至驱动器P1的输入端，信号调制器T的另外一个输出端连接至或非门H1的其中一个输入端，迟滞比较器B的输出端K连接至或非门H1的另外一个输入端，或非门H1的输出端连接至驱动器P2的输入端。驱动器P1通过输出端c01与晶体管Q1的控制极连接，通过输出端c02与晶体管Q2的控制极连接。驱动器P2通过输出端c04与晶体管Q4的控制极连接，通过输出端c05与晶体管Q5的控制极连接。其中误差放大器EA的工作原理、信号调制器T的结构以及工作原理、驱动器P1和驱动器P2的工作原理可以参考图3所示的相关描述，在此不再赘述。需要说明的是，图9所示的Buck控制电路的具体结构为示意性的，其具体结构可以根据应用场景的需要调整，在此不做限定。这里需要说明的是，当晶体管Q4为Pmos晶体管、晶体管Q5为Nmos晶体管、迟滞比较器的输出端K输出的低电平信号有效、信号调制器T的输出端输出的低电平有效时，可以采用与门。下面以晶体管Q4为Pmos晶体管、晶体管Q5为Nmos晶体管、采用或非门为例，进行原理描述。
当迟滞比较器B检测出输出端口Vout电压值低于参考信号VB时，迟滞比较器B输出高电平信号。此时无论信号调制器T输出的信号如何，与迟滞比较器B输出的高电平信号进行或非后，均为低电平信号，该信号经过驱动器P2处理后，控制晶体管Q4导通，供电端Vcc通过晶体管Q4将输出电流提供至输出端口Vout。当迟滞比较器B检测到输出端口Vout电压值高于参考信号VT时，迟滞比较器B输出低电平信号，供电端Vcc停止通过晶体管Q4所在的支路输出电流。或非门H1输出端输出的信号受信号调制器T输出的信号的控制，此时晶体管Q4、晶体管Q5和电感L1在Buck控制电路的控制下作为一相buck工作。也即是说，在补电电路02停止补电期间，电源管理***2采用双相Buck电路为负载供电。也即是说，或非门H1的一个输入端接收第二控制信号，或非门H1的另外一个输入端K接收来自补电电路02的第一控制信号，从而该或非门H1输出第三控制信号，该第三控制信号是对第一控制信号和第二控制信号进行或非运算得到的，用来进行晶体管Q4的控制。晶体管Q4受到该第三控制信号的控制，也可以认为是受到第一控制信号和第二控制信号的共同控制，并基于第一控制信号和第二控制信号的控制来工作。
从本实施例中可以看出，在电源管理***2采用两相Buck电路为负载供电的场景下，当负载电能过耗时，其中一相Buck电路可以作为补电电路02的一部分，在迟滞比较器B的控制下，供电端Vcc直接通过晶体管Q4向输出端口Vout提供电能。从而节省了晶体管的数目。此外，本实施例所示的Buck电路还可以采用小容量电容(例如23uF电容)，可以降低版图占用面积。
在本实施例中，由于电感L1的存在，供电端Vcc通过晶体管Q4向输出端口Vout提供电能的起始阶段，输出端口Vout电压会继续下跌，其所下跌的幅度ΔVd与电感感值L1、及电容C1的ESR有关，其中ESR为电容寄生等效电阻。
下面，通过图10所示的补电电路02在供电期间的等效电路图以及公式(3)-公式(11)，对电感L1的参数配置对图8所示的电路的影响进行说明。
记Imax为负载最大瞬态电流，供电端Vcc提供的电压为VBAT，L0为电感L0的感值，C1为电容C1的容值，ESR为电容C1的寄生等效电阻ESR的阻值，晶体管Q4刚开 始导通时间点为0时刻，Vout为输出端口Vout电压值，输出端口Vout电压在0时刻之后跌落电压为ΔVd(t),tm为输出端口Vout电压跌落至最低点时的时间，I1(t)为流过电感L1的电流，I2(t)为流过电阻ESR的电流，I3(t)为流过负载电流。
则I3(t)＝Imax            (3)
I1(t)＝(VBAT-Vout)/L0×t        (4)
I2(t)＝Imax-(VBAT-Vout)/L0×t         (5)
由公式(3)-公式(5)可以看出，随着I1(t)逐渐增加，I2(t)逐渐减小；
记S＝(VBAT-Vout)/L0         (6)
当晶体管Q4导通的瞬间，Vout继续跌落；
ΔVd(t)＝S×ESR×t-(Imax-S/2×t)×t/C1
＝S/2/C1×t^2+(S×ESR-Imax/C1)×t       (7)
对ΔVd(t)求导：ΔVd’(t)＝S/C1×t+(S×ESR-Imax/C1)     (8)
令ΔVd’(t)＝0           (9)
即求得晶体管Q4导通后跌落持续时间：tm＝Imax×/S-ESR×C1     (10)
ΔVd＝S/2/C1×tm^2+(S×ESR-Imax/C1)×tm       (11)
由公式(3)-公式(11)可以看出，电感L1的感值越小，输出端口Vout电压跌落至最低点时的时间tm越短，输出端口Vout电压跌落至最低点的幅度ΔVd越小。从而，可以根据ΔVd的需求来设置电感L1感值。
请继续参考图11，其示出了如图1所示的电源管理***2的又一个实施例的结构示意图。在图11中，电源管理***2包括Buck控制电路、迟滞比较器B、晶体管Q1、晶体管Q2、晶体管Q4、晶体管Q5、电感L0、电感L1和电容C1。其中，晶体管Q1、晶体管Q2、电感L0和电容C1属于一相Buck电路，在未补电期间，晶体管Q4、晶体管Q5、电感L1和电容C1属于一相Buck电路。Buck控制电路与各元件的连接关系、各元件之间的连接关系、迟滞比较器B与各元件之间的连接关系、迟滞比较器内部结构具体可以参考图8所示的实施例的相关描述。与图8所示的电源管理***2不同的是，在本实施例中，电源管理***2还包括驱动器P3、晶体管Q6、晶体管Q7和电感L2，其中，晶体管Q6、晶体管Q7、电感L2和电容C1又可以属于一相Buck电路。也即，本实施例所示的Buck电路为三相Buck电路。晶体管Q6的控制极和晶体管Q7的控制极分别连接至Buck控制电路的输出端c06和控制的端c07，晶体管Q6的第一极连接至供电端Vcc，晶体管Q7的第二极连接至公共地Gnd，晶体管Q6的第二极、晶体管Q7的第一极和电感L2的其中一端连接，电感L2的另一端连接至输出端口Vout。晶体管Q6和晶体管Q7具有不同的导通时间。
在本实施例中，当输出端口Vout的电压低于参考信号VB时，晶体管Q4和晶体管Q6导通，供电端Vcc由两路通路(即电感L1所在的支路和电感L2所在的支路)将电能提供至输出端口Vout以向负载补电；当输出端口Vout的电压高于参考信号VT时，供电端Vcc停止补电。此时，晶体管Q4、晶体管Q5、电感L1和电容C1在Buck控制电路的控制下作为一相Buck电路工作；晶体管Q6、晶体管Q7、电感L2和电容C1在Buck控制电路的控制下作为一相Buck电路工作。
基于图11所示的电源管理***2，Buck控制电路的具体结构可以如图12所示。在图 12中，Buck控制电路包括误差放大器EA、信号调制器T、驱动器P1、驱动器P2、或非门H1，各器件之间的连接关系以及工作原理可以参考图3和图9所示的Buck控制电路的相关描述，在此不再赘述。与图9所示的Buck控制电路不同的是，本实施例所示的Buck控制电路还包括驱动器P3和或非门H2，信号调制器T还包括第三输出端，其中信号调制器T的第三输出端连接至或非门H2的其中一个输入端，迟滞比较器B的输出端K还连接至或非门H2的另外一个输入端，或非门H2的输出端连接至驱动器P3的输入端。驱动器P3通过输出端c06与晶体管Q6的控制极连接，通过输出端c07与晶体管Q7的控制极连接。这里需要说明的是，图11所示的或非门H2也可以由与门替代。具体的，当晶体管Q6为Pmos晶体管、晶体管Q7为Nmos晶体管、迟滞比较器的输出端K输出的低电平信号有效、信号调制器T的输出端输出的低电平有效时，可以采用与门，图中未示出该实现方式。需要说明的是，图12所示的Buck控制电路的具体结构为示意性的，其具体结构可以根据应用场景的需要调整，在此不做限定。下面以晶体管Q6为Pmos晶体管、晶体管Q7为Nmos晶体管、采用或非门为例，进行原理描述。
当迟滞比较器B检测出输出端口Vout电压值低于参考信号VT时，迟滞比较器B输出高电平信号。此时无论信号调制器T输出的信号如何，与迟滞比较器B输出的高电平信号进行或非后，均为低电平信号，该信号经过驱动器P2、驱动器P3处理后，分别控制晶体管Q4、晶体管Q6导通，供电端Vcc由两路通路(即电感L1所在的支路和电感L2所在的支路)将输出电流提供至输出端口Vout以向负载补电。当迟滞比较器B检测到输出端口Vout电压值高于参考信号VT时，迟滞比较器B输出低电平信号。此时，或非门H1、或非门H2输出端输出的信号受信号调制器T输出的信号的控制，其与信号调制器T输出的信号反相。在补电电路02停止补电期间，电源管理***2采用三相Buck电路为负载供电。
本实施例中电感L1、电感L2的参数的选择可以参考图8所示的实施例的相关描述，在此不再赘述。从本实施例中可以看出，在电源管理***2采用三相Buck电路为负载供电的场景下，当负载电能过耗时，其中两相Buck电路可以作为补电电路02的一部分，在迟滞比较器B的控制下，供电端Vcc直接通过晶体管Q4、晶体管Q6向输出端口Vout提供输出电流。从而节省了晶体管的数目。此外，本实施例所示的Buck电路还可以采用小容量电容(例如23uF电容)，可以降低版图占用面积。
另外，本申请实施例还提供了一种电源管理方法，该电源管理方法应用于图1、图2、图5、图8、图11对应的任意实施例所示的电源管理***。电源管理***包括DC-DC转换电路、输入端口、输出端口、第一控制电路和补电电路。其中，输入端口用于接收输入电压和输入电流，输出端口与负载连接，用于向负载提供输出电压和输出电流。DC-DC转换电路，连接在输入端口和输出端口之间，第一控制电路连接在输出端口和补电电路的控制端之间，补电电路连接在输入端口和输出端口之间。上述输入电流可以包括第一输入电流和第二输入电流。
其中，图13为本申请实施例提供的电源管理方法1300的流程图。该电源管理方法1300具体包括：
步骤S1301，DC-DC转换电路用于通过输出端口获取用于反映输出电压的第一反馈电压，基于第一反馈电压以及第一参考信号，通过输入端口向输出端口充电以调节输出电压。
其中，第一参考信号用于控制当前输出端口期望输出的电压，也即负载工作所需要的电压；其可以是期望输出的电压，也可以是基于期望输出的电压而调节的调节后的电压。第二参考信号是可以变动的，其基于负载的工作情况而改变。第一参考信号可以为上述各实施例中所述的参考信号Vset。
第一反馈电压可以是输出端口实际输出的电压，也可以是对实际输出的电压进行调节而得到电压。
步骤S1302，第一控制电路用于通过输出端口获取输出电压的第二反馈电压，基于第二反馈电压以及第二参考信号，生成第一控制信号，并提供至补电电路。
第二反馈电压可以是输出端口实际输出的电压，也可以是对实际输出的电压进行调节而得到电压。
第二参考信号可以是一个，也可以是二个。第二参考信号用于控制当前输出端口期望输出的电压，也即负载工作所需要的电压。当第二参考信号包括二个时，该两个第二参考信号的值不同，其中一个第二参考信号的值高于另外一个第二参考信号的值。具体的，该两个第二参考信号例如可以为上述各实施例所述的参考信号VB和参考信号VT。这里的第二参考信号是可以变动的，其基于负载的工作情况而改变。
上述第一控制电路可以为比较器。例如，可以为单限比较器，也可以为双限比较器。当上述第二参考信号为一个时，该比较器可以为单限比较器。单限比较器通常包括两个输入端，分别用于输入第二参考信号和第二反馈电压。
当第二参考信号包括两个时，该比较器可以为双限比较器。该双限比较器用于：将第二反馈电压分别与该两个第二参考信号进行比较，在检测到第二反馈电压低于较低值的第二参考信号时，控制补电子电路中的至少部分晶体管导通，及时将输入电流转换成第二输出电流提供至输出端口，以补充调节输出电压；在检测到输出端口的电压值高于较高值的第二参考信号时，控制补电电路中的至少部分晶体管关断，以停止生成第二输出电流。
进一步的，该双限比较器可以为迟滞比较器。该迟滞比较器可以为图2、图4A、图4B、图5、图8、图11任一图所示的迟滞比较器B。
步骤S1303，补电电路接收第一控制信号，基于第一控制信号从输入端口向输出端口充电以补充调节输出电压。
这里的补电电路可以为图1所示的补电电路02中的补电子电路(图中未示出)，也即是说可以为图2、图5任一实施例所示的补电电路02中除迟滞比较器B之外的电路，也可以包括图8所示的实施例中晶体管Q4、晶体管Q5和电感L1在内的电路，也可以包括图11所示的实施例中包括晶体管Q4、晶体管Q5、电感L1、晶体管Q6、晶体管Q7以及电感L2在内的电路。
具体的，补电电路中包括第三晶体管，该第三晶体管导通时，可以形成电流通路。在第一控制电路输出的控制信号的控制下，当第三晶体管导通时，可以将输入端口接收的输入电流提供至输出端口，生成第二输出电流，以补充调节输出端口的电压。当第三晶体管关断时，停止生成第二输出电流。
在一种可能的设计中，补电电路还包括第四晶体管和电容。第一控制电路可以控制第三晶体管关断、第四晶体管导通，此时，输入端口接收到的输入电流提供至电容，以为电容充电。第一控制电路还可以控制第三晶体管导通、第四晶体管关断，电容通过第三晶体 管放电以形成从电容至输出端口的通路，此时将第二输出电流提供至输出端口。
在一种可能的设计中，DC-DC转换电路可以包括第二控制电路和功率级电路。具体的，第二控制电路可以为图2、图3、图5、图8、图9、图11以及图12中的任意一图所示的Buck控制电路，功率级电路可以为图2、图5、图8以及图11中所示的Buck电路(例如，图2、图5、图8以及图11中所示的晶体管Q1、晶体管Q2、电感L0和电容C1组成的电路)。
其中，第二控制电路，用于通过输出端口获取用于反映输出电压的第一反馈电压，基于第一反馈电压以及第一参考信号生成至少一个第二控制信号；至少一个第一功率级电路中的每个第一功率级电路包括第一晶体管、第二晶体管和第一电感，第一晶体管的第一极连接至输入端口，第一晶体管的第二极与第二晶体管的第一极连接，第二晶体管的第二极连接至公共地，第一电感的一端连接至第一晶体管的第二极，第一电感的另一端连接至输出端口；第一晶体管(如Q1、Q4或Q6)用于基于至少一个第二控制信号中对应于第一功率级电路的第二控制信号从输入端口通过第一电感向输出端口充电；第二晶体管(如Q2、Q5或Q7)用于基于对应于第一功率级电路的第二控制信号通过第一电感向输出端口充电。
在一种可能的设计中，至少一个第一功率级电路中的第二功率级电路中的第一晶体管被第二功率级电路和补电电路所复用；第二功率级电路中的第一晶体管(如Q1、Q4或Q6)具体用于基于第一控制信号和对应于第二功率级电路的第二控制信号，从输入端口通过电感向输出端口充电。
在一种可能的设计中，第二控制电路还用于：获取第一控制电路生成的第一控制信号，基于该第一控制信号和对应于第二功率级电路的第二控制信号，生成第三控制信号；该第二功率级电路中的第一晶体管(如Q1、Q4或Q6)具体用于基于第三控制信号，从输入端口通过电感向输出端口充电。
在一种可能的设计中，电源管理***还包括参考信号调节电路；参考信号调节电路的输入端连接至第一控制电路的输出端，参考信号调节电路的输出端连接至DC-DC转换电路的其中一个输入端；参考信号调节电路用于：基于第一控制电路输出的控制信号，调节第一参考信号的大小，将调节后的第一参考信号提供至所述DC-DC转换电路。其中，参考信号调节电路的具体结构以及方法实现可以参考图6对应实施例的相关描述。
本申请实施例还提供了一种电子设备，如图14所示，图14示出了本申请实施例提供的一种电子设备的结构示意图。电子设备1400可以为便携式计算机(如手机)、笔记本电脑、可穿戴电子设备(如智能手表)、平板电脑、增强现实(augmentedreality，AR)、虚拟现实(virtual reality，VR)设备或车载设备等。具体的，本申请所示的电子设备包括如图1、图2、图5、图8、图11任意实施例所示的电源管理***。电子设备还可以包括诸如电池等供部件，电源管理***可以将电池等供电部件提供的电能提供给负载，以为负载提供工作所需电能。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (12)

  1. 一种电源管理***，其特征在于，所述电源管理***包括直流-直流DC-DC转换电路、第一控制电路、补电电路、输入端口和输出端口；其中，
    所述输入端口用于接收输入电压；
    所述输出端口连接至负载，用于向负载提供输出电压；
    所述DC-DC转换电路，连接在所述输入端口和所述输出端口之间，用于通过所述输出端口获取用于反映所述输出电压的第一反馈电压，基于所述第一反馈电压以及第一参考信号，通过所述输入端口向所述输出端口充电以调节所述输出电压；
    所述第一控制电路，连接在所述输出端口和所述补电电路之间，用于通过所述输出端口获取所述输出电压的第二反馈电压，基于所述第二反馈电压以及第二参考信号，生成第一控制信号，并向所述补电电路提供所述第一控制信号；
    所述补电电路，连接在所述输入端口和所述输出端口之间，用于基于所述第一控制信号从所述输入端口向所述输出端口充电以补充调节所述输出电压。
  2. 根据权利要求1所述的电源管理***，其特征在于，所述第一控制电路包括比较器，用于比较所述第二反馈电压和所述第二参考信号以得到所述第一控制信号。
  3. 根据权利要求2所述的电源管理***，其特征在于，所述比较器为迟滞比较器。
  4. 根据权利要求3所述的电源管理***，其特征在于，所述第二参考信号包括多个门限信号，用于所述迟滞比较器的迟滞比较。
  5. 根据权利要求1-4任一项所述的电源管理***，其特征在于，所述DC-DC转换电路包括第二控制电路和至少一个第一功率级电路；
    所述第二控制电路，用于通过所述输出端口获取用于反映所述输出电压的第一反馈电压，基于所述第一反馈电压以及所述第一参考信号生成至少一个第二控制信号；
    所述至少一个第一功率级电路中的每个第一功率级电路包括第一晶体管、第二晶体管和电感，所述第一晶体管的第一极连接至所述输入端口，所述第一晶体管的第二极与所述第二晶体管的第一极连接，所述第二晶体管的第二极连接至公共地，所述电感的一端连接至所述第一晶体管的第二极，所述电感的另一端连接至所述输出端口；
    所述第一晶体管用于基于所述至少一个第二控制信号中对应于所述第一功率级电路的第二控制信号从所述输入端口通过所述电感向所述输出端口充电；
    所述第二晶体管用于基于所述对应于所述第一功率级电路的第二控制信号通过所述电感向所述输出端口充电。
  6. 根据权利要求1-5任一项所述的电源管理***，其特征在于，所述补电电路包括第三晶体管；
    所述第三晶体管的控制极用于接收所述第一控制信号，所述第三晶体管的第一极连接至所述输入端口，所述第三晶体管的第二极连接至所述输出端口，所述第三晶体管用于基于所述第一控制信号从所述输入端口向所述输出端口充电。
  7. 根据权利要求1-5任一项所述的电源管理***，其特征在于，所述补电电路包括第三晶体管、第四晶体管和电容；
    所述第三晶体管的控制极和所述第四晶体管的控制极分别用于接收所述第一控制信 号，所述第三晶体管的第一极连接至所述第四晶体管的第二极，所述第三晶体管的第二极连接至所述输出端口，所述第四晶体管的第一极连接至所述输入端口；
    所述电容的第一极连接至所述第三晶体管的第一极，所述电容的第二极连接至公共地；
    所述第四晶体管用于基于所述第一控制信号从所述输入端口向所述电容充电；
    所述第三晶体管用于基于所述第一控制信号从所述电容向所述输出端口充电。
  8. 根据权利要求5所述的电源管理***，其特征在于，所述至少一个第一功率级电路中的第二功率级电路中的所述第一晶体管被所述第二功率级电路和所述补电电路所复用；
    所述第二功率级电路中的所述第一晶体管具体用于基于所述第一控制信号和对应于所述第二功率级电路的所述第二控制信号，从所述输入端口通过所述电感向所述输出端口充电。
  9. 根据权利要求8所述的电源管理***，其特征在于，所述第二控制电路还用于：获取所述第一控制信号，基于所述第一控制信号和对应于所述第二功率级电路的所述第二控制信号，生成第三控制信号；
    所述第二功率级电路中的所述第一晶体管具体用于基于所述第三控制信号，从所述输入端口通过所述电感向所述输出端口充电。
  10. 根据权利要求5、8或9所述的电源管理***，其特征在于，所述第二控制电路包括误差放大器、信号调制器和至少一个驱动器；
    所述误差放大器将所述第一反馈电压与所述第一参考信号之间的误差做放大得到放大信号；
    所述信号调制器用于接收所述放大信号，并生成所述至少一个调制信号；
    所述至少一个驱动器中每个驱动器，用于接收所述调制信号并生成所述至少一个第二控制信号中的一个第二控制信号。
  11. 根据权利要求1-10任一项所述的电源管理***，其特征在于，所述电源管理***还包括参考信号调节电路，连接在所述第一控制电路和所述DC-DC转换电路之间；
    所述参考信号调节电路用于：基于所述第一控制信号，调节所述第一参考信号的大小，将调节后的第一参考信号提供至所述DC-DC转换电路。
  12. 一种电子设备，其特征在于，包括如权利要求1-11任一项所述的电源管理***。
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