WO2021143381A1 - Method for manufacturing three-dimensional circuit and electronic element - Google Patents
Method for manufacturing three-dimensional circuit and electronic element Download PDFInfo
- Publication number
- WO2021143381A1 WO2021143381A1 PCT/CN2020/133111 CN2020133111W WO2021143381A1 WO 2021143381 A1 WO2021143381 A1 WO 2021143381A1 CN 2020133111 W CN2020133111 W CN 2020133111W WO 2021143381 A1 WO2021143381 A1 WO 2021143381A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- metal
- insulating material
- layer
- manufacturing
- laser
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 72
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 claims abstract description 81
- 239000002184 metal Substances 0.000 claims abstract description 81
- 239000010949 copper Substances 0.000 claims abstract description 62
- 229910052802 copper Inorganic materials 0.000 claims abstract description 57
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 55
- 239000000463 material Substances 0.000 claims abstract description 24
- 238000009713 electroplating Methods 0.000 claims abstract description 21
- 238000007733 ion plating Methods 0.000 claims abstract description 20
- 238000005240 physical vapour deposition Methods 0.000 claims abstract description 19
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000012545 processing Methods 0.000 claims abstract description 8
- 239000011810 insulating material Substances 0.000 claims description 81
- 230000008569 process Effects 0.000 claims description 43
- 238000002347 injection Methods 0.000 claims description 21
- 239000007924 injection Substances 0.000 claims description 21
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 15
- 230000008021 deposition Effects 0.000 claims description 15
- 239000002923 metal particle Substances 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 229910052718 tin Inorganic materials 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 7
- 229910045601 alloy Inorganic materials 0.000 claims description 7
- 238000001746 injection moulding Methods 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 5
- 239000004332 silver Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 4
- 150000002739 metals Chemical class 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 3
- 238000012805 post-processing Methods 0.000 claims description 3
- 239000004677 Nylon Substances 0.000 claims description 2
- 229920000122 acrylonitrile butadiene styrene Polymers 0.000 claims description 2
- 230000003064 anti-oxidating effect Effects 0.000 claims description 2
- 239000003365 glass fiber Substances 0.000 claims description 2
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 2
- 229920001778 nylon Polymers 0.000 claims description 2
- 239000004810 polytetrafluoroethylene Substances 0.000 claims description 2
- 229920001343 polytetrafluoroethylene Polymers 0.000 claims description 2
- 238000007654 immersion Methods 0.000 claims 3
- 238000001465 metallisation Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 120
- 238000007747 plating Methods 0.000 description 12
- 239000011241 protective layer Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 239000007769 metal material Substances 0.000 description 8
- 238000011282 treatment Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 238000004891 communication Methods 0.000 description 4
- 238000003780 insertion Methods 0.000 description 4
- 230000037431 insertion Effects 0.000 description 4
- 239000002699 waste material Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 238000005265 energy consumption Methods 0.000 description 3
- 230000007613 environmental effect Effects 0.000 description 3
- 238000001914 filtration Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000000608 laser ablation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- 229920003023 plastic Polymers 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 238000005488 sandblasting Methods 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 238000005507 spraying Methods 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- KCXVZYZYPLLWCC-UHFFFAOYSA-N EDTA Chemical compound OC(=O)CN(CC(O)=O)CCN(CC(O)=O)CC(O)=O KCXVZYZYPLLWCC-UHFFFAOYSA-N 0.000 description 2
- 229910004349 Ti-Al Inorganic materials 0.000 description 2
- 229910004692 Ti—Al Inorganic materials 0.000 description 2
- 238000002679 ablation Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- WSFSSNUMVMOOMR-NJFSPNSNSA-N methanone Chemical compound O=[14CH2] WSFSSNUMVMOOMR-NJFSPNSNSA-N 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- 239000013077 target material Substances 0.000 description 2
- 239000002351 wastewater Substances 0.000 description 2
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- LEKPFOXEZRZPGW-UHFFFAOYSA-N copper;dicyanide Chemical compound [Cu+2].N#[C-].N#[C-] LEKPFOXEZRZPGW-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- XPPKVPWEQAFLFU-UHFFFAOYSA-J diphosphate(4-) Chemical compound [O-]P([O-])(=O)OP([O-])([O-])=O XPPKVPWEQAFLFU-UHFFFAOYSA-J 0.000 description 1
- 235000011180 diphosphates Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000001247 metal acetylides Chemical class 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002991 molded plastic Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/119—Details of rigid insulating substrates therefor, e.g. three-dimensional details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
- H05K2203/107—Using laser light
Definitions
- the present invention relates to a method for manufacturing a circuit, in particular to a method for manufacturing a three-dimensional circuit, and an electronic component provided with the three-dimensional circuit.
- the three-dimensional circuit can be applied to electronic components such as mobile phone antennas, base station antennas, radar antennas or automobile wireless anti-collision components.
- the present invention has the following advantages:
- the insulating material of the injection molded casing does not contain metal particles, so it is not doped with metal particles in the insulating material like the LDS process, which damages the dielectric properties of the material and increases the electromagnetic loss.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The present invention relates to a method for manufacturing a three-dimensional circuit, comprising: forming a metal base layer (21) on a surface (11) of an insulating shell (10) by means of PVD ion plating; using a three-dimensional laser device to irradiate laser between a graphic region (12) and a non-graphic region (13) on the surface (11) to remove the metal base layer (21) at the boundary, to form an insulating isolation belt (14); electroplating a copper layer (25) in the graphic region (12); and etching the metal base layer (21) in the non-graphic region (13). The method can realize smooth or low-roughness metallization of a material interface and higher binding force at the same time, without changing dielectric properties of materials or increasing electromagnetic loss, and is also more environmentally friendly, and facilitates improving the processing capacity of fine-pitch line graphics of the three-dimensional circuit. The present invention also relates to an electronic element, comprising an insulating shell and the three-dimensional circuit prepared on the shell by means of the method. The electronic element is a mobile phone antenna, a base station antenna, a radar antenna or an automotive wireless anti-collision component.
Description
本发明涉及一种电路的制作方法，尤其是三维电路的制作方法，以及具备该三维电路的电子元件。该三维电路可以应用于手机天线、基站天线、雷达天线或汽车无线防撞组件等电子元件中。The present invention relates to a method for manufacturing a circuit, in particular to a method for manufacturing a three-dimensional circuit, and an electronic component provided with the three-dimensional circuit. The three-dimensional circuit can be applied to electronic components such as mobile phone antennas, base station antennas, radar antennas or automobile wireless anti-collision components.
三维电路又称三维立体电路，是指三维成型的塑料、玻璃或陶瓷等绝缘材料上的互连器件或电子组件，主要是指模塑成型的塑料壳体表面上的三维模塑互连器件(亦称3D-MID，Three dimensional Molded Interconnect Device)。3D-MID技术已被广泛地应用于通讯、汽车电子、计算机、机电设备、医疗器械等领域中。例如，以FPC印刷电路板作为手机收发天线现在已不复使用，在智能手机的壳体内部或背面直接制作金属化天线图形的3D立体电路是目前的主要解决方案，如图1(a)中所示。立体电路能够使手机的GPS天线、主天线、Wi-Fi天线、5G基站天线振子或其他射频器件等同时集成在手机外壳上，从而减小天线尺寸并提高集成度，节约设计空间，减少组件数量并降低制造成本。下一代5G移动通信***将移到毫米波频段，以便获得更大的通信带宽。这将对天线和射频前端模组的设计带来一系列的变化，尤其适合使用3D立体电路。Three-dimensional circuit, also known as three-dimensional circuit, refers to three-dimensionally molded interconnection devices or electronic components on insulating materials such as plastic, glass or ceramics, and mainly refers to the three-dimensional molded interconnection device on the surface of the molded plastic shell ( Also known as 3D-MID, Three dimensional Molded Interconnect Device). 3D-MID technology has been widely used in communications, automotive electronics, computers, electromechanical equipment, medical equipment and other fields. For example, using FPC printed circuit boards as mobile phone transceiver antennas is no longer in use, and 3D stereo circuits with metalized antenna patterns directly produced inside or on the back of the smartphone casing is the current main solution, as shown in Figure 1(a) Shown. The three-dimensional circuit enables the GPS antenna, main antenna, Wi-Fi antenna, 5G base station antenna element or other radio frequency components of the mobile phone to be integrated on the mobile phone shell at the same time, thereby reducing the antenna size and improving the integration, saving design space and reducing the number of components And reduce manufacturing costs. The next-generation 5G mobile communication system will move to the millimeter wave frequency band in order to obtain a larger communication bandwidth. This will bring a series of changes to the design of antennas and RF front-end modules, especially suitable for the use of 3D stereo circuits.
在汽车电子应用方面，传统汽车需要大量的电线或电缆来相互连接，这耗费大量的材料与人工，同时也会降低可靠性。由于3D立体电路能够大大简化电线电缆的配线连接，将电路板的电气互连和支撑功能与塑料壳体的支撑和防护功能结合起来，从而为汽车提供更多可用空间、更轻更小的电器组件，增大设计自由度，减少汽车组装困难并提高可靠性。图1(b)示出了现有技术中的具有三维电路的汽车无线防撞组件。In terms of automotive electronics applications, traditional cars require a large number of wires or cables to connect to each other, which consumes a lot of materials and labor, and also reduces reliability. Because the 3D three-dimensional circuit can greatly simplify the wiring and connection of wires and cables, it combines the electrical interconnection and support functions of the circuit board with the support and protection functions of the plastic shell, thereby providing more usable space, lighter and smaller cars Electrical components increase the design freedom, reduce the difficulty of automobile assembly and improve reliability. Figure 1(b) shows a wireless collision avoidance component for automobiles with a three-dimensional circuit in the prior art.
目前在塑料壳体或其他材料上制作三维电路的工艺主要包括：喷涂或丝印法、LRP(Laser Restructuring Print，激光重构印刷)、LDS(Laser Direct Structuring，激光直接成型)、LAP(Laser Activating plating，激光活化镀)、LAP+等。喷涂或丝印法具有大面积量产、快速、低成本的优点，但其中使用的粘结剂粘度极高，金属粉末容易沉淀，电路易剥离。LRP工艺具有生产成本低、工作效率高的优点，可解决化学镀带来的废液、安全环保问题，但由于银浆的阻值远低于常规的铜、镍，因而难以调试天线。类似喷涂或丝印法，LRP也难以制作复杂图形，目前还没有量产。LDS工艺采用了金属颗粒，因而不仅价格高、工艺成本高，而且还会影响材料介电常数，导致手机天线调试过程变困难，降低生产效率。而且，在 高频材料中掺入金属颗粒将会改变其介电性能和增加电磁损耗，从而严重地制约三维电路在高频材料上的应用。LAP/LAP+工艺在天线调试方面比LDS工艺更容易，成本更低，适合较大尺寸的三维电路，但是都存在化学镀步骤，有废液排放问题。更重要的是，LAP/LAP+工艺需要激光粗化或喷砂化学除胶粗化，形成了蜂窝状材料界面，这将严重影响天线或其他射频器件的插损或者其他电学性能，导致器件能耗增加。At present, the process of making three-dimensional circuits on plastic shells or other materials mainly includes: spraying or silk screen printing, LRP (Laser Restructuring Print), LDS (Laser Direct Structuring, laser direct molding), LAP (Laser Activating plating) , Laser activation plating), LAP+, etc. Spraying or screen printing has the advantages of large-area mass production, fast speed, and low cost, but the adhesive used therein has a very high viscosity, metal powder is easy to precipitate, and the circuit is easy to peel off. The LRP process has the advantages of low production cost and high work efficiency. It can solve the waste, safety and environmental protection problems caused by electroless plating. However, because the resistance of silver paste is much lower than that of conventional copper and nickel, it is difficult to debug the antenna. Similar to spraying or silk screen printing, LRP is also difficult to produce complex graphics, and there is currently no mass production. The LDS process uses metal particles, which not only has a high price and a high process cost, but also affects the dielectric constant of the material, which makes the debugging process of the mobile phone antenna difficult and reduces the production efficiency. Moreover, the incorporation of metal particles in high-frequency materials will change their dielectric properties and increase electromagnetic losses, thereby severely restricting the application of three-dimensional circuits in high-frequency materials. The LAP/LAP+ process is easier to debug than the LDS process in terms of antenna debugging, lower cost, suitable for larger-sized three-dimensional circuits, but there are electroless plating steps, and there is a problem of waste liquid discharge. More importantly, the LAP/LAP+ process requires laser roughening or sandblasting chemical degumming to form a honeycomb material interface, which will seriously affect the insertion loss or other electrical properties of the antenna or other radio frequency devices, resulting in device energy consumption Increase.
发明内容Summary of the invention
本发明是鉴于上述问题做出的，其目的在于，提供一种三维电路的制作方法以及具备这种三维电路的电子元件，这种方法能够避免上述现有工艺中存在的缺陷，能够在不损害材料介电性能和增加电磁损耗的情况下，同时实现材料界面光滑或低粗糙度的金属化和较高的结合力，而且更加环保，有利于提升三维电路的小间距线路图形的加工能力。The present invention was made in view of the above-mentioned problems, and its purpose is to provide a method for manufacturing a three-dimensional circuit and an electronic component equipped with such a three-dimensional circuit. This method can avoid the above-mentioned defects in the prior art and can prevent damage. In the case of material dielectric properties and increased electromagnetic loss, the material interface can be smooth or low-roughness metallization and higher bonding force at the same time, and it is more environmentally friendly, which is beneficial to improve the processing ability of small-pitch circuit patterns of three-dimensional circuits.
根据一方面，本发明提供了一种三维电路的制作方法，包括：通过PVD离子镀，在绝缘材料外壳的表面上形成金属打底层；利用三维激光设备在表面上的图形区域与非图形区域之间照射激光，以去除边界处的金属打底层而形成绝缘隔离带；在图形区域中电镀铜层；以及，蚀刻掉非图形区域中的金属打底层。According to one aspect, the present invention provides a method for manufacturing a three-dimensional circuit, which includes: forming a metal underlayer on the surface of an insulating material shell by PVD ion plating; using a three-dimensional laser device to form a patterned area and a non-patterned area on the surface. The laser is irradiated to remove the metal underlayer at the boundary to form an insulating isolation tape; the copper layer is electroplated in the pattern area; and the metal underlayer in the non-pattern area is etched away.
根据另一方面，本发明提供了另一种三维电路的制作方法，包括：通过PVD离子镀，在绝缘材料外壳的表面上形成金属打底层；利用三维激光设备在表面上的非图形区域上照射激光，以去除非图形区域中的金属打底层；以及，在图形区域中电镀铜层。这种方法尤其适用于外壳上形成的三维电路图形的面积占比较高的情况，能够减少三维电路的制作工序，从而提高生产效率并降低制造成本。According to another aspect, the present invention provides another method for manufacturing a three-dimensional circuit, including: forming a metal underlayer on the surface of an insulating material shell by PVD ion plating; using a three-dimensional laser device to irradiate non-patterned areas on the surface Laser, to remove the metal in the non-patterned area to lay the bottom layer; and, electroplating the copper layer in the patterned area. This method is particularly suitable for situations where the area of the three-dimensional circuit pattern formed on the housing occupies a relatively high area, and can reduce the manufacturing process of the three-dimensional circuit, thereby improving production efficiency and reducing manufacturing costs.
根据又一方面，本发明提供了一种电子元件，其包括绝缘材料外壳、以及通过上述任何一种制作方法在绝缘材料外壳上制备得到的三维电路，该电子元件为手机天线、基站天线、雷达天线或汽车无线防撞组件。According to another aspect, the present invention provides an electronic component, which includes an insulating material shell and a three-dimensional circuit prepared on the insulating material shell by any of the above-mentioned manufacturing methods. The electronic component is a mobile phone antenna, a base station antenna, and a radar. Antenna or car wireless anti-collision components.
与现有技术相比较，本发明具有如下的优点：Compared with the prior art, the present invention has the following advantages:
(1).注塑外壳的绝缘材料不包含金属颗粒，因而不像LDS工艺那样在绝缘材料中掺杂有金属颗粒，从而损害材料介电性能并增加电磁损耗。(1). The insulating material of the injection molded casing does not contain metal particles, so it is not doped with metal particles in the insulating material like the LDS process, which damages the dielectric properties of the material and increases the electromagnetic loss.
(2).PVD离子镀工艺能够在注塑外壳的光滑表面与其上方的金属层之间提供高结合力，因此不需要对外壳表面进行激光粗化或喷砂、化学除胶粗化等，不像LAP、LAP+工艺那样导致材料界面的粗糙度过大，从而严重影响天线或其他射频器件的插损和其他电学性能，导致器件能耗增加。PVD离子镀除了Ni以外，还可以采用Ti、Ti-Al、Al、Cr等其他非磁性金属或合金来保证高结合力，因而具有更高的选择灵活度和更广泛的适用范围。(2) The PVD ion plating process can provide high bonding force between the smooth surface of the injection molded case and the metal layer above it, so there is no need to roughen the surface of the case by laser or sandblasting, chemical degumming, etc., unlike The LAP and LAP+ processes cause the material interface to be too rough, which seriously affects the insertion loss and other electrical properties of the antenna or other radio frequency devices, resulting in increased device energy consumption. In addition to Ni, PVD ion plating can also use Ti, Ti-Al, Al, Cr and other non-magnetic metals or alloys to ensure high bonding force, so it has higher selection flexibility and wider application range.
(3).在排放废水等环保方面，PVD离子镀比LAP/LAP+中的化学镀镍更加环保，不涉及甲醛、EDTA等废物的排放。(3). In terms of environmental protection such as waste water discharge, PVD ion plating is more environmentally friendly than electroless nickel plating in LAP/LAP+, and does not involve the discharge of formaldehyde, EDTA and other wastes.
(4).PVD离子镀形成的金属打底层的厚度为0.5μm以下，甚至为0.1μm或者0.05μm以下，因而能够将隔离带的宽度缩小至0.5mm甚至0.1mm以下。这有利于提升三维电路的小间距线路图形的加工能力，可大大降低激光烧蚀的强度、能量和时间，最大限度地降低对绝缘材料外壳表面的损伤，保证线路间不渗镀短路。(4) The thickness of the metal primer layer formed by PVD ion plating is less than 0.5 μm, even 0.1 μm or less than 0.05 μm, so the width of the isolation belt can be reduced to 0.5 mm or even less than 0.1 mm. This is conducive to improving the processing ability of small-pitch circuit patterns of three-dimensional circuits, can greatly reduce the intensity, energy and time of laser ablation, minimize damage to the surface of the insulating material shell, and ensure that there is no short circuit between circuits.
(5).通过调整三维激光设备中的机械臂和激光器的相对运动，能够方便地使激光对准所要烧蚀的位置，从而获得精确、复杂的三维电路图形。(5). By adjusting the relative movement of the mechanical arm and the laser in the three-dimensional laser equipment, the laser can be easily aligned to the position to be ablated, thereby obtaining accurate and complex three-dimensional circuit patterns.
在参照附图阅读以下的详细说明后，本领域技术人员将更容易理解本发明的这些及其他的特征、方面和优点。为清楚起见，附图不一定按比例绘制，而是其中有些部分被夸大以示出细节。在所有附图中，相同的参考标号表示相同或相似的部分。After reading the following detailed description with reference to the accompanying drawings, those skilled in the art will more easily understand these and other features, aspects and advantages of the present invention. For clarity, the drawings are not necessarily drawn to scale, but some parts of them are exaggerated to show details. In all the drawings, the same reference numerals indicate the same or similar parts.
图1(a)示出现有技术中的具有三维电路的手机天线，图1(b)示出现有技术中的具有三维电路的汽车无线防撞组件。Fig. 1(a) shows a mobile phone antenna with a three-dimensional circuit in the prior art, and Fig. 1(b) shows a wireless collision avoidance component for an automobile with a three-dimensional circuit in the prior art.
图2(a)至2(f)示出根据第一实施例的三维电路的制作方法的流程示意图。其中，图2(a)示出绝缘材料外壳，图2(b)示出金属打底层，图2(c)示出绝缘隔离带，图2(d)示出图形区域中的电镀铜层，图2(e)示出非图形区域中的金属打底层已被去除，图2(f)示出保护层。2(a) to 2(f) show schematic flow diagrams of a method for manufacturing a three-dimensional circuit according to the first embodiment. Among them, Figure 2(a) shows an insulating material shell, Figure 2(b) shows a metal underlayer, Figure 2(c) shows an insulating isolation tape, and Figure 2(d) shows an electroplated copper layer in the pattern area. Figure 2(e) shows that the metal primer layer in the non-patterned area has been removed, and Figure 2(f) shows the protective layer.
图3(a)至3(f)示出在根据第一实施例的三维电路的制作方法中，绝缘材料外壳表面上的图形区域的剖面的变化过程示意图。其中，图3(a)示出绝缘材料外壳，图3(b)示出注入层，图3(c)示出沉积层，图3(d)示出电镀铜层，图3(e)示出电镀铜层的部分厚度已被去除，图3(f)示出保护层。3(a) to 3(f) show schematic diagrams of the change process of the cross-section of the pattern area on the surface of the insulating material casing in the method for manufacturing a three-dimensional circuit according to the first embodiment. Among them, Figure 3 (a) shows the insulating material shell, Figure 3 (b) shows the injection layer, Figure 3 (c) shows the deposited layer, Figure 3 (d) shows the electroplated copper layer, Figure 3 (e) shows Part of the thickness of the electroplated copper layer has been removed. Figure 3(f) shows the protective layer.
图4(a)至4(e)示出根据第二实施例的三维电路的制作方法的流程示意图。其中，图4(a)示出绝缘材料外壳，图4(b)示出金属打底层，图4(c)示出非图形区域中的金属打底层已被去除，图4(d)示出图形区域中的电镀铜层，图4(e)示出保护层。4(a) to 4(e) show schematic flowcharts of a method for manufacturing a three-dimensional circuit according to a second embodiment. Among them, Figure 4 (a) shows the insulating material shell, Figure 4 (b) shows the metal bottom layer, Figure 4 (c) shows that the metal bottom layer in the non-patterned area has been removed, Figure 4 (d) shows The electroplated copper layer in the pattern area, Figure 4(e) shows the protective layer.
图5(a)至5(e)示出在根据第二实施例的三维电路的制作方法中，绝缘材料外壳表面上的图形区域的剖面的变化过程示意图。其中，图5(a)示出绝缘材料外壳，图5(b)示出注入层，图5(c)示出包括第一和第二沉积层的沉积层，图5(d)示出电镀铜层，图5(e)示出保护层。5(a) to 5(e) show schematic diagrams of the change process of the cross-section of the pattern area on the surface of the insulating material casing in the method for manufacturing a three-dimensional circuit according to the second embodiment. Among them, Figure 5 (a) shows the insulating material shell, Figure 5 (b) shows the injection layer, Figure 5 (c) shows the deposition layer including the first and second deposition layer, Figure 5 (d) shows the electroplating Copper layer, Figure 5(e) shows the protective layer.
附图标记：Reference signs:
1 电子元件1 Electronic components
10 绝缘材料外壳10 Insulating material shell
11 绝缘材料外壳的表面11 The surface of the insulating material shell
12 图形区域12 Graphic area
13 非图形区域13 Non-graphic area
14 绝缘隔离带14 Insulation isolation tape
20 三维电路20 Three-dimensional circuit
21 金属打底层21 Bottom layer of metal
22 注入层22 Injection layer
23、24 沉积层23, 24 Sedimentary layer
25 铜层25 Copper layer
d
1、d
2 铜层的厚度
d 1 , d 2 thickness of copper layer
26 保护层。26 Protection layer.
以下，参照附图详细地说明本发明的实施方式。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
在附图中，图2(a)至2(f)示出根据第一实施例的三维电路的制作方法的流程示意图，图3(a)至3(f)示出在该制作方法中绝缘材料外壳表面上的图形区域的剖面的变化过程示意图。图4(a)至4(e)示出根据第二实施例的三维电路的制作方法的流程示意图，图5(a)至5(e)示出在该制作方法中绝缘材料外壳表面上的图形区域的剖面的变化过程示意图。下面，将参照这些附图来详细地说明根据本发明的三维电路的制作方法、以及通过该方法制备得到的电子元件。In the drawings, Figures 2(a) to 2(f) show a schematic flow diagram of a method for manufacturing a three-dimensional circuit according to the first embodiment, and Figures 3(a) to 3(f) show the insulation in the manufacturing method. Schematic diagram of the change process of the profile of the graphic area on the surface of the material shell. Figures 4(a) to 4(e) show a schematic flow chart of a method for manufacturing a three-dimensional circuit according to a second embodiment, and Figures 5(a) to 5(e) show the surface of the insulating material shell in the method of manufacturing Schematic diagram of the changing process of the profile of the graphic area Hereinafter, the method of manufacturing a three-dimensional circuit according to the present invention and the electronic component manufactured by the method will be described in detail with reference to these drawings.
(第一实施例)(First embodiment)
根据第一实施例的三维电路的制作方法主要包括以下步骤：通过注塑工艺，由不含金属颗粒的绝缘材料形成外壳；通过PVD离子镀，在绝缘材料外壳的表面上形成金属打底层；利用三维激光设备，在外壳表面上的图形区域与非图形区域之间照射激光，以去除边界处的金属打底层，形成绝缘隔离带；通过电镀，在外壳表面上的图形区域中形成铜层；蚀刻掉外壳表面上的非图形区域中的金属打底层，只保留图形区域中的金属打底层和电镀铜层，此时电镀铜层的部分厚度也被去除；以及对电镀铜层进行后处理，例如镀各表面处理，以实现防氧化和可焊性功能。The manufacturing method of the three-dimensional circuit according to the first embodiment mainly includes the following steps: forming a shell from an insulating material containing no metal particles through an injection molding process; forming a metal underlayer on the surface of the insulating material shell through PVD ion plating; The laser device irradiates the laser between the patterned area and the non-patterned area on the surface of the shell to remove the metal bottom layer at the boundary to form an insulating isolation tape; through electroplating, a copper layer is formed in the patterned area on the surface of the shell; etched away The metal underlay in the non-patterned area on the surface of the shell, only the metal underlay and the electroplated copper layer in the pattern area are retained, and part of the thickness of the electroplated copper layer is also removed; Various surface treatments to achieve anti-oxidation and solderability functions.
图2(a)示出绝缘材料外壳10，在该绝缘材料外壳的表面上形成根据本发明的三维电路。绝缘材料外壳是通过将如下绝缘材料中的一种或多种注塑而形成的：LCP、PPS、PTFE、PPE、PPA、PBT、PET、PC、PI、PA、POM、ABS塑料、玻纤、玻璃、陶瓷、耐高温尼 龙。介质陶瓷材料可以包括例如：钨青铜结构的BaO～Ln
2O
3～TiO
2(BLT)系列、CaTiO
3改性系列和改性铅基钙钛矿系列，主要用于低频率范围内的民用移动通信***中作为介质谐振器；以BaTi
4O
9、Ba
2Ti
9O
20和(Zr，Sn)TiO
4等为基础的微波介质陶瓷材和低介电常数物质与CaTiO
3、SrTiO
3等的复合材料，主要用于中等频率范围内的微波军用雷达及通信***中作为介质谐振器件；以及复合钙钛矿结构型材料，主要用于高频率范围内的微波介质陶瓷。除此之外，还可以使用其他绝缘材料，例如各种树脂等。绝缘材料外壳可以根据所要应用的电子元器件或组件的外壳来确定形状，例如可以成型为手机的外壳形状或者汽车无线防撞组件的外壳形状，例如为成型为平板状、圆柱形、圆锥形、阶梯圆盘形、抛物面或球形等。
Fig. 2(a) shows an insulating material housing 10 on which a three-dimensional circuit according to the present invention is formed. The insulating material shell is formed by injection molding one or more of the following insulating materials: LCP, PPS, PTFE, PPE, PPA, PBT, PET, PC, PI, PA, POM, ABS plastic, glass fiber, glass , Ceramics, high temperature resistant nylon. Dielectric ceramic materials can include, for example: BaO～Ln 2 O 3 ～TiO 2 (BLT) series with tungsten bronze structure, CaTiO 3 modified series and modified lead-based perovskite series, which are mainly used for civil mobile in the low frequency range Used as a dielectric resonator in communication systems; microwave dielectric ceramic materials and low dielectric constant materials based on BaTi 4 O 9 , Ba 2 Ti 9 O 20 and (Zr, Sn)TiO 4 and CaTiO 3 , SrTiO 3, etc. Composite materials are mainly used as dielectric resonator devices in microwave military radars and communication systems in the medium frequency range; and composite perovskite structure materials are mainly used in microwave dielectric ceramics in the high frequency range. In addition, other insulating materials, such as various resins, can also be used. The shape of the insulating material shell can be determined according to the shell of the electronic component or component to be applied. For example, it can be shaped into the shape of the shell of a mobile phone or the shape of the shell of a car wireless anti-collision component, for example, into a flat, cylindrical, conical, Stepped disc, parabolic or spherical, etc.
注塑外壳的绝缘材料不包含金属颗粒，因而不像现有技术的LDS工艺那样在绝缘材料中掺杂金属颗粒，从而损害材料介电性能并增加电磁损耗。The insulating material of the injection molded case does not contain metal particles, so it is not doped with metal particles in the insulating material like the LDS process in the prior art, which damages the dielectric properties of the material and increases the electromagnetic loss.
图2(b)示出金属打底层21，该金属打底层是通过PVD离子镀工艺在绝缘材料外壳10的表面上形成的。金属打底层21可以形成在绝缘材料外壳10的整个表面上，或者形成于其中一部分表面上。PVD离子镀工艺主要包括以下步骤：利用等离子体或霍尔源对绝缘材料外壳的表面进行前处理；通过离子注入工艺，将第一金属注入到绝缘材料外壳的表面下方，以形成注入层；以及通过磁过滤等离子体沉积和/或溅射工艺，在绝缘材料外壳的表面上方形成由第二金属组成的沉积层。FIG. 2(b) shows a metal primer layer 21, which is formed on the surface of the insulating material housing 10 through a PVD ion plating process. The metal primer layer 21 may be formed on the entire surface of the insulating material housing 10 or on a part of the surface. The PVD ion plating process mainly includes the following steps: using plasma or a Hall source to pre-treat the surface of the insulating material shell; injecting the first metal under the surface of the insulating material shell through an ion implantation process to form an implanted layer; and Through a magnetic filtered plasma deposition and/or sputtering process, a deposition layer composed of the second metal is formed on the surface of the insulating material shell.
前处理可以包括加热处理，以及等离子体处理或者霍尔源处理。加热处理可以排出绝缘材料外壳的表面和内部的空气和水分，有利于提高金属打底层与绝缘材料之间的结合力。等离子体处理或者霍尔源处理可以根据绝缘材料的具体种类和三维电路的性能要求来调整所用的电压、电流和处理时间等。通过进行等离子体或霍尔源处理，能够清洗掉绝缘材料外壳表面的有机物，提高表面活性，从而有利于提高金属打底层与绝缘材料之间的结合力。The pretreatment may include heating treatment, plasma treatment or Hall source treatment. The heat treatment can exhaust the air and moisture on the surface and inside of the insulating material shell, which is beneficial to improve the bonding force between the metal primer and the insulating material. Plasma treatment or Hall source treatment can adjust the used voltage, current, and treatment time according to the specific types of insulating materials and the performance requirements of the three-dimensional circuit. By performing plasma or Hall source treatment, the organic matter on the surface of the insulating material shell can be cleaned, and the surface activity can be improved, thereby helping to improve the bonding force between the metal primer layer and the insulating material.
在离子注入工艺中，使用第一金属材料作为靶材，在真空环境下通过电弧作用使靶材中的金属材料电离而产生离子，在高电压的电场下使离子加速并获得很高的能量；高能的金属离子以很高的速度撞击到绝缘材料外壳的表面上，并且注入到表面下方达一定深度，形成注入层。在绝缘材料与注入的金属材料离子之间可形成稳定的化学键，例如离子键或共价键，有助于提高形成于绝缘材料外壳表面上的金属层与绝缘材料之间的结合力，并抑制金属层的脱落。可以根据绝缘材料的种类来选择第一金属材料，例如可以使用Ni、Ti、Ai、Cr或它们之间的合金，也可以使用Mo、W、Sn等。除金属材料以外，还可以使用导电氧化物、导电碳化物、导电有机物等作为离子注入用的靶材。可以根据绝缘材料和金属靶材的种类、期望的结合力大小、期望的注入层厚度等因素来确定离子注入工艺的各种工艺参数，包括电 压、电流和处理时间等。例如，通过增大电压，可以增大注入层的厚度；通过增大电流和时间，可以提高注入层中金属离子的浓度。在一个实施例中，离子注入的电压为10kV～30kV，电流为1mA～5mA，处理时间为1～60分钟，由此得到厚度为1～50nm的注入层，例如厚度为10nm、20nm等。In the ion implantation process, the first metal material is used as the target material, and the metal material in the target material is ionized by the arc action in a vacuum environment to generate ions, and the ions are accelerated under a high-voltage electric field to obtain high energy; High-energy metal ions impinge on the surface of the insulating material shell at a very high speed and are injected to a certain depth below the surface to form an injection layer. A stable chemical bond, such as an ionic bond or a covalent bond, can be formed between the insulating material and the implanted metal material ions, which helps to improve the bonding force between the metal layer formed on the surface of the insulating material shell and the insulating material, and suppress The peeling of the metal layer. The first metal material can be selected according to the type of insulating material. For example, Ni, Ti, Ai, Cr or an alloy between them can be used, and Mo, W, Sn, etc. can also be used. In addition to metal materials, conductive oxides, conductive carbides, conductive organics, etc. can also be used as targets for ion implantation. Various process parameters of the ion implantation process, including voltage, current, and processing time, can be determined according to factors such as the type of insulating material and metal target, the desired bonding force, and the desired thickness of the implanted layer. For example, by increasing the voltage, the thickness of the injection layer can be increased; by increasing the current and time, the concentration of metal ions in the injection layer can be increased. In an embodiment, the voltage of ion implantation is 10kV-30kV, the current is 1mA-5mA, and the treatment time is 1-60 minutes, thereby obtaining an implanted layer with a thickness of 1-50nm, for example, a thickness of 10nm, 20nm, etc.
磁过滤等离子体沉积工艺和溅射工艺都是现有技术中常用的薄膜形成方法。本发明利用这些工艺在绝缘材料外壳的表面上方，具体而言在先前形成的注入层的上方，形成由第二金属组成的沉积层。第二金属材料可以根据注入层的材料或者随后形成于其上的导电材料的具体种类来选择。例如，第二金属材料可以与第一金属材料相同，例如为Ni、Ti、Ai、Cr或它们之间的合金以及Mo、W、Sn等，也可以与后续电镀的铜层相同，即Cu。沉积层可以包括一层或多层，例如可以包括磁过滤等离子体沉积的Cu层和溅射的Cu层，或者磁过滤等离子体沉积的仅仅一个Cu层，或者磁过滤等离子体沉积的Ni层和溅射的Ni层，或者磁过滤等离子体沉积的仅仅一个Ni层，等等。沉积层的厚度可以为0.05～0.5μm，优选地低至0.05～0.1μm。Both the magnetic filter plasma deposition process and the sputtering process are commonly used thin film formation methods in the prior art. The present invention utilizes these processes to form a deposition layer composed of a second metal on the surface of the insulating material shell, in particular, on the injection layer previously formed. The second metal material may be selected according to the material of the injection layer or the specific kind of conductive material subsequently formed thereon. For example, the second metal material may be the same as the first metal material, such as Ni, Ti, Ai, Cr or their alloys and Mo, W, Sn, etc., or may be the same as the subsequent electroplated copper layer, namely Cu. The deposition layer may include one or more layers, for example, it may include a Cu layer deposited by magnetic filtration plasma and a sputtered Cu layer, or only one Cu layer deposited by magnetic filtration plasma, or a Ni layer deposited by magnetic filtration plasma and Sputtered Ni layer, or just one Ni layer deposited by magnetic filtered plasma, etc. The thickness of the deposited layer may be 0.05 to 0.5 μm, preferably as low as 0.05 to 0.1 μm.
注塑成型的绝缘材料外壳具有光滑的表面，PVD离子镀工艺能够在该光滑表面与其上方的金属导电层之间提供较高的结合力，例如在0.7-1.5N/mm之间乃至0.8-1.2N/mm之间的结合力。因此，不需要对外壳表面进行激光粗化或者喷砂、化学除胶粗化等，不像LAP、LAP+工艺那样导致材料界面的粗糙度过大，严重影响天线或其他射频器件的插损或其他电学性能，导致器件能耗增加。即，本发明能够同时实现材料界面光滑或低粗糙度(表面粗糙度R
z＜1μm)的金属化和较高的结合力，有利于降低三维天线或基站射频器件的插损并优化其他电学性能，大大降低相关器件的用电能耗。而且，在采用PVD离子镀时，金属打底层的厚度可以从LAP/LAP+工艺的大约0.5μm降低至0.05μm或以下，但仍能保证较高的结合力，能够满足三维电子器件的耐热耐回流焊或其他复杂环境下的高可靠性要求。通常而言，金属打底层的厚度越薄，高频损耗性能越好。进一步，现有的LAP/LAP+工艺必须采用Ni作为打底层，因为其他材料不容易在后续的酸性蚀刻中去除，但是本发明的PVD离子镀除了Ni以外，还可以采用Ti、Ti-Al、Al、Cr等其他非磁性金属或合金来保证高结合力，因而具有更高的选择灵活度和更广泛的适用范围。另外，在排放废水等环保方面，本发明的PVD离子镀比LAP/LAP+中的化学镀镍更加环保，不涉及甲醛、EDTA等废物的排放。
The injection-molded insulating material shell has a smooth surface. The PVD ion plating process can provide a high bonding force between the smooth surface and the metal conductive layer above it, for example, between 0.7-1.5N/mm or even 0.8-1.2N The binding force between /mm. Therefore, there is no need to roughen the shell surface by laser or sandblasting, chemical degumming, etc., unlike the LAP, LAP+ process, which causes the material interface to be too rough, which seriously affects the insertion loss of the antenna or other radio frequency devices or other The electrical performance leads to an increase in the energy consumption of the device. That is, the present invention can simultaneously achieve smooth or low-roughness (surface roughness R z ＜1μm) metallization and high bonding force of the material interface, which is beneficial to reduce the insertion loss of three-dimensional antennas or base station radio frequency devices and optimize other electrical properties. , Which greatly reduces the power consumption of related devices. Moreover, when using PVD ion plating, the thickness of the metal primer can be reduced from about 0.5μm in the LAP/LAP+ process to 0.05μm or less, but still can ensure a high bonding force, which can meet the heat resistance of three-dimensional electronic devices. High reliability requirements under reflow soldering or other complex environments. Generally speaking, the thinner the thickness of the metal bottom layer, the better the high-frequency loss performance. Furthermore, the existing LAP/LAP+ process must use Ni as the underlayer, because other materials are not easy to remove in the subsequent acid etching, but the PVD ion plating of the present invention can also use Ti, Ti-Al, Al in addition to Ni. , Cr and other non-magnetic metals or alloys to ensure high binding force, so it has a higher flexibility of choice and a wider scope of application. In addition, in terms of environmental protection such as waste water discharge, the PVD ion plating of the present invention is more environmentally friendly than the electroless nickel plating in LAP/LAP+, and does not involve the discharge of formaldehyde, EDTA and other wastes.
图2(c)示出绝缘隔离带14，该绝缘隔离带是通过在绝缘材料外壳表面上的图形区域12与非图形区域13之间照射激光以去除边界处的金属打底层21而形成的。在此过程中，将形成有金属打底层21的绝缘材料外壳放置在三维激光设备内，将激光器发射的高强度聚焦激 光束集中在材料界面的焦点处，烧蚀掉图形区域与非图形区域之间的边界处的金属打底层，使表层的金属气化并被排气抽走，从而直接露出底层的绝缘材料。三维激光设备可包括机械臂和激光器，机械臂和激光器中的至少一者能够在三维空间内移动，其中绝缘材料外壳可以由机械臂保持或者放置在设备内部的基座上。激光器可以采用Nd-YAG紫外激光器、CO
2红外激光器、可见光激光器、半导体激光器、光纤激光器等，具有激光晶体以发射波长为193～1064nm的激光束。例如，近红外光激光器可以发射波长为1064nm的激光束。三维激光设备还设置有控制器，用于控制聚焦激光束的投射焦距、投射路径及投射时间等。在一个实施例中，激光器可采用输入电流2～5A、脉冲频率2～25kHz、扫描速度500～2500mm/s的加工参数，并能在边长例如为650mm的立方体空间范围内进行精细的加工。通过调整三维激光设备中的机械臂和激光器的相对运动，能够方便地使激光对准所要烧蚀的部位，从而获得精确、复杂的三维电路图形。
FIG. 2(c) shows the insulating isolation tape 14, which is formed by irradiating a laser between the patterned area 12 and the non-patterned area 13 on the surface of the insulating material shell to remove the metal underlayer 21 at the boundary. In this process, the insulating material shell formed with the metal bottom layer 21 is placed in the three-dimensional laser device, and the high-intensity focused laser beam emitted by the laser is concentrated at the focal point of the material interface, and ablation between the graphic area and the non-graphic area is ablated. The metal at the boundary between the two lays a bottom layer, which vaporizes the metal on the surface and is pumped away by exhaust gas, thereby directly exposing the insulating material of the bottom layer. The three-dimensional laser device may include a robotic arm and a laser, and at least one of the robotic arm and the laser can move in a three-dimensional space, wherein the insulating material housing can be held by the robotic arm or placed on a base inside the device. The laser can be a Nd-YAG ultraviolet laser, CO 2 infrared laser, visible light laser, semiconductor laser, fiber laser, etc., with a laser crystal to emit a laser beam with a wavelength of 193-1064 nm. For example, a near-infrared light laser can emit a laser beam with a wavelength of 1064 nm. The 3D laser equipment is also provided with a controller for controlling the projection focal length, projection path, and projection time of the focused laser beam. In one embodiment, the laser can use processing parameters of 2-5A input current, 2-25kHz pulse frequency, and 500-2500mm/s scanning speed, and can perform fine processing within a cubic space with a side length of, for example, 650mm. By adjusting the relative movement of the mechanical arm and the laser in the three-dimensional laser equipment, the laser can be easily aligned to the position to be ablated, thereby obtaining accurate and complex three-dimensional circuit patterns.
在现有技术的LAP+工艺中，由于作为打底层的Ni太厚(≥0.5um)，所以当利用3D激光烧掉图形区域与非图形区域之间的金属以形成隔离带时，必须烧出宽度为1mm以上的隔离带，才能保证烧蚀干净或者后续不会渗镀短路，这需要耗费很多的能源，而且容易破坏绝缘材料外壳表面并增加粗糙度。相比之下，在本发明的PVD离子镀中，金属打底层的厚度可达到0.5μm以下，甚至为0.1μm或者0.05μm以下，因而能够将隔离带的宽度缩小至0.5mm甚至0.1mm以下。这有利于提升三维电路的小间距线路图形的加工能力，可大大降低激光烧蚀的强度、能量和时间，最大限度地降低对绝缘材料外壳表面的损伤。特别是，本发明能够烧蚀出小于1mm隔离带且能够烧蚀干净，保证线路间不渗镀短路。In the prior art LAP+ process, the Ni used as the bottom layer is too thick (≥0.5um), so when using a 3D laser to burn off the metal between the patterned area and the non-patterned area to form an isolation zone, the width must be burned An isolation tape with a thickness of 1mm or more can ensure clean ablation or no short-circuit in the subsequent infiltration plating, which requires a lot of energy, and is easy to damage the surface of the insulating material shell and increase the roughness. In contrast, in the PVD ion plating of the present invention, the thickness of the metal primer layer can reach 0.5 μm or less, or even 0.1 μm or 0.05 μm or less, so that the width of the isolation belt can be reduced to 0.5 mm or even 0.1 mm. This is conducive to improving the processing ability of the small-pitch circuit pattern of the three-dimensional circuit, can greatly reduce the intensity, energy and time of laser ablation, and minimize the damage to the surface of the insulating material shell. In particular, the present invention can ablate an isolation band less than 1 mm and can ablate cleanly, ensuring that there is no short circuit between lines.
图2(d)示出图形区域中的电镀铜层25，该电镀铜层25是通过仅对图形区域12中的金属打底层21通电并进行电镀而形成的。在电镀过程中，可以根据绝缘材料外壳的尺寸和形状等，适当地选择电镀槽，并且选择氰化镀铜、硫酸盐镀铜、焦磷酸盐镀铜、无氰镀铜等各种工艺，在金属打底层21的表面上进行镀铜。通过调整电镀期间的电流、工作时间等，能够方便且容易地调节电镀铜层的厚度。在一个实施例中，铜层的厚度为8μm以上，例如为10μm、15μm、20μm等。除了铜以外，电镀技术还可以适用于Ni、Sn、Ag以及它们的合金等，用来将这些金属或合金形成于金属打底层21上。此外，还可以代替电镀工艺，采用化学镀、溅射、真空蒸发镀等技术来形成铜层25。FIG. 2(d) shows the electroplated copper layer 25 in the pattern area, and the electroplated copper layer 25 is formed by energizing only the metal underlayer 21 in the pattern area 12 and performing electroplating. In the electroplating process, the electroplating bath can be appropriately selected according to the size and shape of the insulating material shell, and various processes such as cyanide copper plating, sulfate copper plating, pyrophosphate copper plating, and cyanide-free copper plating can be selected. Copper plating is performed on the surface of the metal bottom layer 21. By adjusting the current, working time, etc. during electroplating, the thickness of the electroplated copper layer can be conveniently and easily adjusted. In an embodiment, the thickness of the copper layer is 8 μm or more, for example, 10 μm, 15 μm, 20 μm, etc. In addition to copper, electroplating technology can also be applied to Ni, Sn, Ag and their alloys, etc., to form these metals or alloys on the metal underlayer 21. In addition, instead of the electroplating process, techniques such as electroless plating, sputtering, and vacuum evaporation plating can be used to form the copper layer 25.
图2(e)示出非图形区域中的金属打底层21已被去除，只留下图形区域12中的金属打底层及其上方的铜层25。在此过程中，可以在微蚀槽或蚀刻槽中对绝缘材料外壳的整个表面进行快速蚀刻，以去除非图形区域13中的金属打底层21。此时，图形区域12中的铜层25 的部分厚度也被去除。由于铜层的厚度为8μm以上，而金属打底层的厚度仅为0.05～0.5μm，所以该快速蚀刻过程不会明显地减薄铜层25并影响其后续使用性能。2(e) shows that the metal underlayer 21 in the non-patterned area has been removed, leaving only the metal underlayer in the patterned area 12 and the copper layer 25 above it. In this process, the entire surface of the insulating material shell can be quickly etched in a micro-etching groove or an etching groove to remove the metal underlayer 21 in the non-patterned area 13. At this time, part of the thickness of the copper layer 25 in the pattern area 12 is also removed. Since the thickness of the copper layer is above 8 μm, and the thickness of the metal primer layer is only 0.05-0.5 μm, the rapid etching process will not significantly thin the copper layer 25 and affect its subsequent use performance.
图2(f)示出保护层26，该保护层26形成于图形区域12中的铜层25上方，以实现防氧化和可焊性功能。即，在形成有铜层25的绝缘材料外壳的表面上进行后处理，以防止铜层25被氧化并使得铜层25能够被焊接在其他的电子元器件上。后处理可以包括现有技术中常见的电镀银、电镀锡、化学沉镍金、化学沉银、化学沉锡等方法中的一种或多种。FIG. 2(f) shows a protective layer 26, which is formed on the copper layer 25 in the pattern area 12 to achieve the functions of oxidation prevention and solderability. That is, post-processing is performed on the surface of the insulating material case on which the copper layer 25 is formed to prevent the copper layer 25 from being oxidized and to enable the copper layer 25 to be soldered to other electronic components. The post-treatment may include one or more of the common methods in the prior art such as silver electroplating, tin electroplating, electroless nickel gold, electroless silver, and electroless tin.
图3(a)至3(f)示出在根据第一实施例的三维电路的制作方法中，绝缘材料外壳表面上的图形区域的剖面的变化过程示意图。图3(a)对应于图2(a)，示出注塑成型的绝缘材料外壳10。图3(b)至3(c)对应于形成金属打底层21的图2(b)，分别示出注入层22和沉积层23。其中，注入层22形成于绝缘材料外壳10的表面11下方，并与该表面保持齐平，而沉积层23则形成于绝缘材料外壳10的表面11上方，并与注入层22紧密邻接。图3(d)对应于图2(d)，示出在图形区域12中电镀形成的铜层25，该铜层25具有厚度d
1。图3(e)对应于图2(e)，示出电镀铜层25的部分厚度已被去除，只留下厚度为d
2的铜层25，其中d
2<d
1，减薄后的铜层厚度d
2例如为7μm以上。图3(f)对应于图2(f)，示出了形成于铜层25上方的保护层26。
3(a) to 3(f) show schematic diagrams of the change process of the cross-section of the pattern area on the surface of the insulating material casing in the method for manufacturing a three-dimensional circuit according to the first embodiment. Fig. 3(a) corresponds to Fig. 2(a) and shows an insulating material casing 10 formed by injection molding. 3(b) to 3(c) correspond to FIG. 2(b) in which the metal underlayer 21 is formed, and respectively show the implanted layer 22 and the deposited layer 23. Wherein, the injection layer 22 is formed under the surface 11 of the insulating material shell 10 and remains flush with the surface, and the deposition layer 23 is formed on the surface 11 of the insulating material shell 10 and closely adjacent to the injection layer 22. Fig. 3(d) corresponds to Fig. 2(d) and shows a copper layer 25 formed by electroplating in the pattern area 12, and the copper layer 25 has a thickness d 1 . Figure 3(e) corresponds to Figure 2(e), showing that part of the thickness of the electroplated copper layer 25 has been removed, leaving only the copper layer 25 with a thickness of d 2 , where d 2 <d 1 , the thinned copper The layer thickness d 2 is, for example, 7 μm or more. FIG. 3(f) corresponds to FIG. 2(f) and shows the protective layer 26 formed on the copper layer 25. As shown in FIG.
在图3(a)至3(f)中并没有示出与图2(c)对应的剖视图，因为图2(c)所示的激光烧蚀过程仅仅是针对图形区域12与非图形区域13之间的边界处进行的，以便去除该边界处的金属打底层21，而并未针对图形区域12内的金属打底层21进行。3(a) to 3(f) do not show the cross-sectional view corresponding to FIG. 2(c), because the laser ablation process shown in FIG. 2(c) is only for the graphic area 12 and the non-graphic area 13 It is carried out at the boundary between, in order to remove the metal underlayer 21 at the boundary, but not for the metal underlayer 21 in the graphic area 12.
通过上述第一实施例的制作方法制备得到的电子元件1示出在图2(f)中。该电子元件1包括绝缘材料外壳10和在该绝缘材料外壳10上制作的三维电路20。三维电路20如图3(f)所示包括：具有注入层22和沉积层23的金属打底层21；形成于金属打底层21上方的电镀铜层25；以及形成于电镀铜层25上方的保护层26。其中，注入层22形成于绝缘材料外壳10的表面11下方并与该表面保持齐平，沉积层23形成于绝缘材料外壳10的表面11上方并与注入层22紧密邻接。所形成的电子元件1可以为手机天线、基站天线、雷达天线或汽车无线防撞组件等具有三维电路的各种电子元器件或电子设备。The electronic component 1 manufactured by the manufacturing method of the first embodiment described above is shown in FIG. 2(f). The electronic component 1 includes an insulating material housing 10 and a three-dimensional circuit 20 made on the insulating material housing 10. The three-dimensional circuit 20 as shown in FIG. 3(f) includes: a metal underlay 21 with an injection layer 22 and a deposition layer 23; an electroplated copper layer 25 formed on the metal underlay 21; and a protective layer formed on the electroplated copper layer 25 Layer 26. Wherein, the injection layer 22 is formed below the surface 11 of the insulating material shell 10 and remains flush with the surface, and the deposition layer 23 is formed on the surface 11 of the insulating material shell 10 and is closely adjacent to the injection layer 22. The formed electronic component 1 may be various electronic components or electronic equipment with three-dimensional circuits, such as a mobile phone antenna, a base station antenna, a radar antenna, or an automobile wireless anti-collision component.
(第二实施例)(Second embodiment)
当外壳上形成的三维电路图形的面积占比较高，例如高达70％以上时，适合采用根据本发明的第二实施例的三维电路的制作方法。该制作方法主要包括以下步骤：通过注塑工艺，由不含金属颗粒的绝缘材料形成外壳；通过PVD离子镀，在绝缘材料外壳的表面上形成金属打底层；利用三维激光设备在外壳表面上的非图形区域上照射激光，以去除非图形区域中 的金属打底层；通过电镀，在外壳表面上的图形区域中形成铜层；以及对电镀铜层进行后处理，例如镀各表面处理，以实现防氧化和可焊性功能。与上述第一实施例相比较，第二实施例的区别在于“利用三维激光设备在外壳表面上的非图形区域上照射激光，以去除该非图形区域中的金属打底层”这一步骤，而无需先在外壳表面上的图形区域与非图形区域之间形成绝缘隔离带，然后再蚀刻掉非图形区域中的金属打底层。因此，该方法能够减少三维电路的制作工序，从而提高生产效率并降低制造成本。然而，当外壳表面上的非图形区域占据较大面积时，利用激光烧蚀掉该区域中的金属打底层将会耗费很多的能量，而且也容易损伤绝缘材料外壳的表面，因而不是优选的。When the area of the three-dimensional circuit pattern formed on the housing is relatively high, for example, up to 70% or more, it is suitable to adopt the method for manufacturing the three-dimensional circuit according to the second embodiment of the present invention. The manufacturing method mainly includes the following steps: forming a shell from an insulating material that does not contain metal particles through an injection molding process; forming a metal underlayer on the surface of the insulating material shell through PVD ion plating; The pattern area is irradiated with a laser to remove the metal underlayer in the non-pattern area; the copper layer is formed in the pattern area on the surface of the shell through electroplating; and the electroplated copper layer is post-processed, such as plating various surface treatments, to achieve prevention Oxidation and solderability functions. Compared with the above-mentioned first embodiment, the difference of the second embodiment lies in the step of "using a three-dimensional laser device to irradiate a laser on a non-patterned area on the surface of the housing to remove the metal underlayer in the non-patterned area." It is not necessary to first form an insulating isolation band between the patterned area and the non-patterned area on the surface of the housing, and then etch the metal in the non-patterned area to lay the bottom layer. Therefore, the method can reduce the manufacturing process of the three-dimensional circuit, thereby improving the production efficiency and reducing the manufacturing cost. However, when the non-patterned area on the surface of the housing occupies a large area, using the laser to ablate the metal layer in the area will consume a lot of energy and easily damage the surface of the insulating material housing, which is not preferred.
图4(a)至4(e)示出根据第二实施例的三维电路的制作方法的流程示意图。其中，图4(a)类似于图2(a)，示出将绝缘材料注塑形成的绝缘材料外壳10。图4(b)类似于图2(b)，示出通过PVD离子镀工艺在绝缘材料外壳的表面上形成的金属打底层21。图4(c)示出非图形区域13中的金属打底层21已被去除，仅仅保留了图形区域12中的金属打底层21。图4(d)类似于图2(d)，示出对图形区域12中的金属打底层进行电镀而形成的铜层25。图4(e)类似于图2(f)，示出在电镀铜层25的上方形成的保护层26，以实现防氧化和可焊性功能。第二实施例不包括如第一实施例中所述的“蚀刻掉外壳表面上的非图形区域中的金属打底层”这一步骤，因而也不存在与图2(e)对应的剖视图。4(a) to 4(e) show schematic flowcharts of a method for manufacturing a three-dimensional circuit according to a second embodiment. Wherein, Fig. 4(a) is similar to Fig. 2(a), showing an insulating material casing 10 formed by injection molding of insulating material. Fig. 4(b) is similar to Fig. 2(b), showing a metal primer layer 21 formed on the surface of the insulating material shell by a PVD ion plating process. FIG. 4(c) shows that the metal underlayer 21 in the non-graphic area 13 has been removed, and only the metal underlayer 21 in the graphic area 12 remains. FIG. 4(d) is similar to FIG. 2(d) and shows a copper layer 25 formed by electroplating the metal underlayer in the pattern area 12. Fig. 4(e) is similar to Fig. 2(f) and shows a protective layer 26 formed on the electroplated copper layer 25 to achieve the functions of oxidation prevention and solderability. The second embodiment does not include the step of "etching away the metal underlayer in the non-patterned area on the shell surface" as described in the first embodiment, so there is no cross-sectional view corresponding to FIG. 2(e).
图5(a)至5(e)示出在根据第二实施例的三维电路的制作方法中，绝缘材料外壳表面上的图形区域的剖面的变化过程示意图。图5(a)与图4(a)对应且类似于图3(a)，示出注塑成型的绝缘材料外壳10。图5(b)和5(c)与形成金属打底层21的图4(b)、4(c)相对应，且分别类似于图3(b)和3(c)，示出了注入层22和沉积层23、24。其中，注入层22形成于绝缘材料外壳10的表面11下方，并与该表面保持齐平。沉积层23形成于绝缘材料外壳10的表面11上方，并与注入层22紧密邻接，另一沉积层24附着在沉积层23上方。两个沉积层23、24可以由相同的材料组成，例如Cu或Ni，也可以由不同的材料组成，例如分别由Ni、Cu组成。沉积层的整体厚度可以为0.05～0.5μm，优选地低至0.05～0.1μm。当然，也可以如图3(c)中所示，仅仅形成一层沉积层23。图5(d)与图4(d)对应且类似于图3(d)，示出在图形区域12中电镀形成的铜层25。由于没有第一实施例中对电镀铜层进行快速蚀刻的过程，因而该铜层25的厚度维持不变。图5(e)与图4(e)相对应且类似于图3(f)，示出了形成于铜层25上方的保护层26。5(a) to 5(e) show schematic diagrams of the change process of the cross-section of the pattern area on the surface of the insulating material casing in the method for manufacturing a three-dimensional circuit according to the second embodiment. Fig. 5(a) corresponds to Fig. 4(a) and is similar to Fig. 3(a), showing an insulating material casing 10 formed by injection molding. Figures 5(b) and 5(c) correspond to Figures 4(b) and 4(c) where the metal primer layer 21 is formed, and are similar to Figures 3(b) and 3(c), respectively, showing the injection layer 22 and deposited layers 23, 24. Wherein, the injection layer 22 is formed under the surface 11 of the insulating material casing 10 and is kept flush with the surface. The deposition layer 23 is formed on the surface 11 of the insulating material shell 10 and is closely adjacent to the injection layer 22, and another deposition layer 24 is attached above the deposition layer 23. The two deposition layers 23, 24 may be composed of the same material, such as Cu or Ni, or may be composed of different materials, such as Ni and Cu, respectively. The overall thickness of the deposited layer may be 0.05-0.5 μm, preferably as low as 0.05-0.1 μm. Of course, as shown in FIG. 3(c), only one deposition layer 23 may be formed. FIG. 5(d) corresponds to FIG. 4(d) and is similar to FIG. 3(d), and shows the copper layer 25 formed by electroplating in the pattern area 12. Since there is no rapid etching process for the electroplated copper layer in the first embodiment, the thickness of the copper layer 25 remains unchanged. FIG. 5(e) corresponds to FIG. 4(e) and is similar to FIG. 3(f), showing the protective layer 26 formed on the copper layer 25. As shown in FIG.
通过第二实施例的制作方法制备得到的电子元件1示出在图4(e)中。与图2(f)所示的电子元件1相同，该电子元件1包括绝缘材料外壳10和在绝缘材料外壳上制作的三维电路 20。三维电路20如图5(e)所示，包括：具有注入层22和沉积层23、24的金属打底层21；形成于金属打底层21上方的电镀铜层25；以及形成于电镀铜层25上方的保护层26。该电子元件1可以为手机天线、基站天线、雷达天线或汽车无线防撞组件等具有三维电路的各种电子元器件或电子设备。The electronic component 1 manufactured by the manufacturing method of the second embodiment is shown in FIG. 4(e). Similar to the electronic component 1 shown in Fig. 2(f), the electronic component 1 includes an insulating material casing 10 and a three-dimensional circuit 20 made on the insulating material casing. The three-dimensional circuit 20 is shown in FIG. 5(e), including: a metal underlay 21 with an injection layer 22 and deposited layers 23, 24; an electroplated copper layer 25 formed on the metal underlay 21; and an electroplated copper layer 25上的保护层26。 The upper protective layer 26. The electronic component 1 may be various electronic components or electronic equipment with three-dimensional circuits, such as a mobile phone antenna, a base station antenna, a radar antenna, or an automobile wireless anti-collision component.
上文描述的内容仅仅提及了本发明的特定实施例。然而，本发明并不受限于文中所述的特定实施例。本领域技术人员将容易想到，在不脱离本发明的要旨的范围内，可以对这些实施例进行各种显而易见的修改、调整及替换，以使其适合于特定的情形。实际上，本发明的保护范围是由权利要求限定的，并且可包括本领域技术人员可预想到的其它示例。What has been described above only mentions specific embodiments of the invention. However, the present invention is not limited to the specific embodiments described herein. Those skilled in the art will easily think that various obvious modifications, adjustments and substitutions can be made to these embodiments within the scope not departing from the gist of the present invention to adapt them to specific situations. In fact, the protection scope of the present invention is defined by the claims, and may include other examples that can be expected by those skilled in the art.
Claims (10)
- 一种三维电路的制作方法，包括：A method for manufacturing a three-dimensional circuit, including:通过PVD离子镀，在绝缘材料外壳的表面上形成金属打底层；Through PVD ion plating, a metal base layer is formed on the surface of the insulating material shell;利用三维激光设备在所述表面上的图形区域与非图形区域之间照射激光，以去除边界处的金属打底层而形成绝缘隔离带；Using a three-dimensional laser device to irradiate laser light between the graphic area and the non-graphic area on the surface to remove the metal bottom layer at the boundary to form an insulating isolation tape;在所述图形区域中电镀铜层；以及Electroplating a copper layer in the pattern area; and蚀刻掉所述非图形区域中的金属打底层。The metal in the non-patterned area is etched away for the bottom layer.
- 一种三维电路的制作方法，包括：A method for manufacturing a three-dimensional circuit, including:通过PVD离子镀，在绝缘材料外壳的表面上形成金属打底层；Through PVD ion plating, a metal base layer is formed on the surface of the insulating material shell;利用三维激光设备在所述表面上的非图形区域上照射激光，以去除所述非图形区域中的金属打底层；以及Using a three-dimensional laser device to irradiate a laser on the non-graphic area on the surface to remove the metal underlayer in the non-graphic area; and在所述图形区域中电镀铜层。A copper layer is electroplated in the pattern area.
- 根据权利要求1或2所述的制作方法，其特征在于，所述PVD离子镀包括：The manufacturing method according to claim 1 or 2, wherein the PVD ion plating comprises:利用等离子体或霍尔源对所述绝缘材料外壳的表面进行前处理；Using plasma or a Hall source to pre-treat the surface of the insulating material housing;通过离子注入工艺，将第一金属注入到所述绝缘材料外壳的表面下方以形成注入层；以及通过磁过滤等离子体沉积和/或溅射工艺，在所述绝缘材料外壳的表面上方形成由第二金属组成的沉积层。Through an ion implantation process, a first metal is implanted below the surface of the insulating material shell to form an injection layer; and through a magnetic filtered plasma deposition and/or sputtering process, a first metal is formed above the surface of the insulating material shell. Deposited layer composed of two metals.
- 根据权利要求3所述的制作方法，其特征在于，所述第一金属包括Ni、Ti、Ai、Cr或它们之间的合金，所述第二金属与所述第一金属相同或者包括Cu。The manufacturing method according to claim 3, wherein the first metal includes Ni, Ti, Ai, Cr or an alloy between them, and the second metal is the same as the first metal or includes Cu.
- 根据权利要求3所述的制作方法，其特征在于，所述沉积层的厚度为0.05～0.5μm，优选地0.05～0.1μm，并且电镀形成的所述铜层具有8μm以上的厚度。The manufacturing method according to claim 3, wherein the thickness of the deposited layer is 0.05-0.5 μm, preferably 0.05-0.1 μm, and the copper layer formed by electroplating has a thickness of 8 μm or more.
- 根据权利要求1所述的制作方法，其特征在于，蚀刻掉所述非图形区域中的金属打底层包括：蚀刻整个所述表面，以同时去除所述非图形区域中的全部金属打底层、以及电镀形成的所述铜层的部分厚度。The manufacturing method according to claim 1, wherein etching away the metal underlayer in the non-patterned area comprises: etching the entire surface to remove all the metal underlayer in the non-patterned area at the same time, and Part of the thickness of the copper layer formed by electroplating.
- 根据权利要求1或2所述的制作方法，其特征在于，还包括对所述铜层进行后处理，以实现防氧化和可焊性功能，其中所述后处理包括电镀银、电镀锡、化学沉镍金、化学沉银、化学沉锡中的一种或多种。The manufacturing method according to claim 1 or 2, further comprising post-processing the copper layer to achieve anti-oxidation and solderability functions, wherein the post-processing includes silver electroplating, tin electroplating, chemical One or more of immersion nickel gold, chemical immersion silver, and chemical immersion tin.
- 根据权利要求1或2所述的制作方法，其特征在于，所述绝缘材料外壳不含金属颗粒，并且是通过将如下材料中的一种或多种注塑形成的：LCP、PPS、PTFE、PPE、PPA、PBT、PET、PC、PI、PA、POM、ABS塑料、玻纤、玻璃、陶瓷、耐高温尼龙，成型为平板状、圆柱形、圆锥形、阶梯圆盘形、抛物面或球形。The manufacturing method according to claim 1 or 2, wherein the insulating material shell does not contain metal particles, and is formed by injection molding one or more of the following materials: LCP, PPS, PTFE, PPE , PPA, PBT, PET, PC, PI, PA, POM, ABS plastics, glass fiber, glass, ceramics, high temperature resistant nylon, formed into flat, cylindrical, conical, stepped disc, parabolic or spherical shapes.
- 根据权利要求1或2所述的制作方法，其特征在于，所述三维激光设备包括机械臂和激光器，所述机械臂和/或所述激光器能够在三维空间内移动，以去除所述金属打底层的特定部分，所述激光器发射波长为193～1064nm的激光束，并采用输入电流2～5A、脉冲频率2～25kHz、扫描速度500～2500mm/s的加工参数。The manufacturing method according to claim 1 or 2, wherein the three-dimensional laser equipment includes a mechanical arm and a laser, and the mechanical arm and/or the laser can move in a three-dimensional space to remove the metal In the specific part of the bottom layer, the laser emits a laser beam with a wavelength of 193-1064nm, and adopts processing parameters of input current 2-5A, pulse frequency 2-25kHz, and scanning speed 500-2500mm/s.
- 一种电子元件，包括绝缘材料外壳、以及通过权利要求1-9中任一项所述的制作方法在该绝缘材料外壳上制备得到的三维电路，其中所述电子元件为手机天线、基站天线、雷达天线或汽车无线防撞组件。An electronic component, comprising an insulating material casing and a three-dimensional circuit prepared on the insulating material casing by the manufacturing method of any one of claims 1-9, wherein the electronic component is a mobile phone antenna, a base station antenna, Radar antenna or car wireless anti-collision components.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010047118.5 | 2020-01-16 | ||
| CN202010047118.5A CN113133195A (en) | 2020-01-16 | 2020-01-16 | Method for manufacturing three-dimensional circuit and electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2021143381A1 true WO2021143381A1 (en) | 2021-07-22 |
Family
ID=76771703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/CN2020/133111 WO2021143381A1 (en) | 2020-01-16 | 2020-12-01 | Method for manufacturing three-dimensional circuit and electronic element |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN113133195A (en) |
| WO (1) | WO2021143381A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115320269B (en) * | 2022-09-19 | 2023-06-16 | 广东绿展科技有限公司 | Method for high-precision ink-jet printing antenna |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1796610A (en) * | 2004-12-28 | 2006-07-05 | 比亚迪股份有限公司 | Plating method |
| JP2007173546A (en) * | 2005-12-22 | 2007-07-05 | Matsushita Electric Works Ltd | Process for fabricating three-dimensional circuit board |
| CN103025060A (en) * | 2011-09-27 | 2013-04-03 | 比亚迪股份有限公司 | Preparation method of three-dimensional connecting device |
| US20150060292A1 (en) * | 2013-08-30 | 2015-03-05 | Wei-Lin Liu | Method for Forming Three Dimensional Circuit |
| CN107620051A (en) * | 2017-09-04 | 2018-01-23 | 武汉光谷创元电子有限公司 | Copper-clad plate and its manufacture method |
| CN109348649A (en) * | 2018-09-20 | 2019-02-15 | 武汉光谷创元电子有限公司 | Heat sink composite material plating process and its product |
| CN109638435A (en) * | 2018-11-27 | 2019-04-16 | 深圳市臻鼎盛通讯有限公司 | The manufacturing process and 5G antenna of a kind of non-metallic substrate antenna or route |
| CN110528034A (en) * | 2019-09-10 | 2019-12-03 | 东莞市极瑞电子科技有限公司 | A kind of plasthetics surface part electroplating method |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738568A (en) * | 2011-04-13 | 2012-10-17 | 榕柏科技有限公司 | Method for applying printing and laser engraving to manufacture antenna on curved substrate |
| CN103094126B (en) * | 2013-01-16 | 2016-06-22 | 东莞市凯昶德电子科技股份有限公司 | The preparation method of the trickle three-dimensional conducting wire of ceramic components |
| CN105899003B (en) * | 2015-11-06 | 2019-11-26 | 武汉光谷创元电子有限公司 | Single layer board, multilayer circuit board and their manufacturing method |
| CN106604560B (en) * | 2017-02-22 | 2020-10-02 | 武汉光谷创元电子有限公司 | Circuit board processing method |
| CN107022747B (en) * | 2017-04-05 | 2019-12-31 | 武汉光谷创元电子有限公司 | Microwave dielectric member and method for manufacturing same |
-
2020
- 2020-01-16 CN CN202010047118.5A patent/CN113133195A/en active Pending
- 2020-12-01 WO PCT/CN2020/133111 patent/WO2021143381A1/en active Application Filing
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1796610A (en) * | 2004-12-28 | 2006-07-05 | 比亚迪股份有限公司 | Plating method |
| JP2007173546A (en) * | 2005-12-22 | 2007-07-05 | Matsushita Electric Works Ltd | Process for fabricating three-dimensional circuit board |
| CN103025060A (en) * | 2011-09-27 | 2013-04-03 | 比亚迪股份有限公司 | Preparation method of three-dimensional connecting device |
| US20150060292A1 (en) * | 2013-08-30 | 2015-03-05 | Wei-Lin Liu | Method for Forming Three Dimensional Circuit |
| CN107620051A (en) * | 2017-09-04 | 2018-01-23 | 武汉光谷创元电子有限公司 | Copper-clad plate and its manufacture method |
| CN109348649A (en) * | 2018-09-20 | 2019-02-15 | 武汉光谷创元电子有限公司 | Heat sink composite material plating process and its product |
| CN109638435A (en) * | 2018-11-27 | 2019-04-16 | 深圳市臻鼎盛通讯有限公司 | The manufacturing process and 5G antenna of a kind of non-metallic substrate antenna or route |
| CN110528034A (en) * | 2019-09-10 | 2019-12-03 | 东莞市极瑞电子科技有限公司 | A kind of plasthetics surface part electroplating method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113133195A (en) | 2021-07-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103188877B (en) | The method that the quick high flexibility of a kind of ceramic circuit-board makes | |
| US10982328B2 (en) | Method for formation of electro-conductive traces on polymeric article surface | |
| CN107022747B (en) | Microwave dielectric member and method for manufacturing same | |
| JP4996653B2 (en) | Manufacturing method of molded circuit components | |
| CN104105353B (en) | A kind of manufacture method of high-precision ceramic circuit board | |
| US20070247822A1 (en) | Method for the production of a printed circuit structure as well as a printed circuit structure thus produced | |
| TWI667950B (en) | Method for manufacturing three-dimensional wiring substrate, three-dimensional wiring substrate, and base material for three-dimensional wiring substrate | |
| MX2013010443A (en) | Sheet assembly with aluminum based electrodes. | |
| CN110798988B (en) | Additive process for manufacturing high-frequency antenna packaging substrate and AiP packaging antenna structure | |
| CN114234138A (en) | Method and apparatus for manufacturing electronic device | |
| JP2014533775A (en) | Metal structure embedded in ceramic substrate | |
| RU2543518C1 (en) | Method of production of double-sided printed board | |
| WO2021143381A1 (en) | Method for manufacturing three-dimensional circuit and electronic element | |
| CN103025060B (en) | A kind of preparation method of three-dimensional interface unit | |
| CN111525240A (en) | Method for manufacturing circuit and antenna on surface of three-dimensional material by sputtering and laser etching | |
| CN104955281B (en) | A kind of method for making in three-dimensional polymer surface or repairing stereo circuit | |
| CN108441843B (en) | Laser direct-writing preformed photocatalytic plating preparation method for metal patterns on surface of material | |
| CN115023059B (en) | Manufacturing method of conformal conductive circuit on surface of dielectric material | |
| Wu et al. | Fabrication of polyetheretherketone (PEEK)-based 3D electronics with fine resolution by a hydrophobic treatment assisted hybrid additive manufacturing method | |
| TWI423751B (en) | Method of manufacturing three - dimensional circuit | |
| JP6014792B1 (en) | 3D wiring board manufacturing method, 3D wiring board, 3D wiring board base material | |
| JP3784368B2 (en) | Circuit board and manufacturing method thereof | |
| CN111876759A (en) | Method for manufacturing metal circuit on surface of plastic material | |
| CN113727540A (en) | Method for manufacturing circuit board by selectively electroplating holes, bonding pads and laser-made conductive patterns | |
| JP2011060969A (en) | Manufacturing method for wiring substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 20913694 Country of ref document: EP Kind code of ref document: A1 |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 20913694 Country of ref document: EP Kind code of ref document: A1 |
|
| 32PN | Ep: public notification in the ep bulletin as address of the adressee cannot be established |
Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 04/07/2023) |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 20913694 Country of ref document: EP Kind code of ref document: A1 |