WO2021138839A1

WO2021138839A1 - Capacitor and manufacturing method thereof

Info

Publication number: WO2021138839A1
Application number: PCT/CN2020/070928
Authority: WO
Inventors: 陆斌; 沈健
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2020-01-08
Filing date: 2020-01-08
Publication date: 2021-07-15
Also published as: CN111788649A

Abstract

Provided are a capacitor (100) and a manufacturing method thereof capable of manufacturing a capacitor (100) at low costs. The capacitor (100) comprises: at least one stack structure (120) comprising n electrically-conductive layers and m dielectric layers, the n electrically-conductive layers and the m dielectric layers forming a structure in which the electrically-conductive layers and the dielectric layers are adjacent to one another, all odd-numbered electrically-conductive layers in the n electrically-conductive layers forming at least one first step structure (10), all even-numbered electrically-conductive layers in the n electrically-conductive layers forming at least one second step structure (20), and each of m and n being a positive integer; at least one first external electrode (130) electrically connected to some or all of the odd-numbered electrically-conductive layers in the n electrically-conductive layers by means of a step surface of the first step structure (10); and at least one second external electrode (140) electrically connected to some or all of the even-numbered electrically-conductive layers in the n electrically-conductive layers by means of a step surface of the second step structure (20).

Description

电容器及其制作方法Capacitor and its manufacturing method

技术领域Technical field

本申请涉及电容器领域，并且更具体地，涉及电容器及其制作方法。This application relates to the field of capacitors, and more specifically, to capacitors and methods of making them.

背景技术Background technique

电容器在电路中可以起到旁路、滤波、去耦等作用，是保证电路正常运转的不可或缺的一部分。为了提高电容器的容值密度，通常可以基于高深宽比的三维结构制备硅电容。然而，高深宽比的三维结构本身的加工难度较大，而且在此三维结构上制作共形的、厚度均匀且没有缺陷的导电层、电介质层也需要极高的工艺水准。如何制备小体积、高容量、低成本的电容器，成为一个亟待解决的技术问题。Capacitors can play the role of bypassing, filtering, decoupling, etc. in the circuit, and are an indispensable part of ensuring the normal operation of the circuit. In order to increase the capacitance density of capacitors, silicon capacitors can usually be fabricated based on a three-dimensional structure with a high aspect ratio. However, the high aspect ratio three-dimensional structure itself is difficult to process, and the production of conformal, uniform thickness and defect-free conductive layers and dielectric layers on this three-dimensional structure also requires an extremely high level of technology. How to prepare small-volume, high-capacity, and low-cost capacitors has become an urgent technical problem to be solved.

发明内容Summary of the invention

本申请实施例提供一种电容器及其制作方法，能够在制备小体积、高容值密度的电容器的同时降低电容器的成本。The embodiments of the present application provide a capacitor and a manufacturing method thereof, which can reduce the cost of the capacitor while preparing a capacitor with a small volume and a high capacitance value density.

第一方面，提供了一种电容器，所述电容器包括：In a first aspect, a capacitor is provided, and the capacitor includes:

至少一个叠层结构，所述叠层结构包括n层导电层和m层电介质层，所述n层导电层和所述m层电介质层形成导电层与电介质层彼此相邻的结构，并且所述n层导电层中的所有奇数层导电层形成至少一个第一台阶结构，所述n层导电层中的所有偶数层导电层形成至少一个第二台阶结构，m、n为正整数；At least one laminated structure, the laminated structure includes an n-layer conductive layer and an m-layer dielectric layer, the n-layer conductive layer and the m-layer dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other, and the All odd-numbered conductive layers in the n-layer conductive layer form at least one first step structure, and all even-numbered conductive layers in the n-layer conductive layer form at least one second step structure, and m and n are positive integers;

至少一个第一外接电极，所述第一外接电极通过所述至少一个第一台阶结构的台阶面电连接至所述n层导电层中的部分或者全部奇数层导电层；At least one first external electrode, the first external electrode is electrically connected to a part or all of the odd-numbered conductive layers in the n-layer conductive layer through the step surface of the at least one first stepped structure;

至少一个第二外接电极，所述第二外接电极通过所述至少一个第二台阶结构的台阶面电连接至所述n层导电层中的部分或者全部偶数层导电层。At least one second external electrode, and the second external electrode is electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer through the step surface of the at least one second stepped structure.

在本申请实施例中，叠层结构形成有至少一个第一台阶结构，以露出n层导电层中的所有奇数层导电层，且叠层结构形成有至少一个第二台阶结构，以露出n层导电层中的所有偶数层导电层，第一外接电极通过至少一个第一台阶结构的台阶面电连接至n层导电层中的部分或者全部奇数层导电层，第二外接电极通过至少一个第二台阶结构的台阶面电连接至n层导电层中的部分或者全部偶数层导电层，从而能够制备三维硅电容器，能够在制备小体积、高容值密度的电容器的同时降低电容器的成本。In the embodiment of the present application, the stacked structure is formed with at least one first step structure to expose all odd-numbered conductive layers in the n-layer conductive layer, and the stacked structure is formed with at least one second step structure to expose the n-layer For all the even-numbered conductive layers in the conductive layer, the first external electrode is electrically connected to part or all of the odd-numbered conductive layers in the n-layer conductive layer through the step surface of at least one first step structure, and the second external electrode is connected through at least one second conductive layer. The step surface of the step structure is electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer, so that a three-dimensional silicon capacitor can be prepared, which can reduce the cost of the capacitor while preparing a capacitor with a small volume and a high capacitance value density.

进一步地，能够在平坦的衬底表面制作叠层结构，并利用光刻胶修整工艺使叠层结构上形成至少一个第一台阶结构和至少一个第二台阶结构，避免了由于制备3D结构相关的刻蚀、沉积等昂贵工艺，并且通过光刻胶修整工艺有效减少了光刻次数，降低了电容器的成本。Furthermore, a laminated structure can be fabricated on a flat substrate surface, and at least one first stepped structure and at least one second stepped structure can be formed on the laminated structure by using a photoresist trimming process, thereby avoiding the problems associated with preparing a 3D structure. Expensive processes such as etching and deposition, and the photoresist trimming process effectively reduces the number of photolithography and reduces the cost of the capacitor.

在一些可能的实现方式中，所述至少一个第一台阶结构与所述至少一个第二台阶结构分别位于所述叠层结构的不同侧。In some possible implementations, the at least one first step structure and the at least one second step structure are respectively located on different sides of the laminated structure.

在一些可能的实现方式中，所述至少一个第一台阶结构与所述至少一个第二台阶结构位于所述叠层结构的同一侧。In some possible implementations, the at least one first step structure and the at least one second step structure are located on the same side of the laminated structure.

在一些可能的实现方式中，所述电容器还包括衬底，所述至少一个叠层结构设置于所述衬底的上方。In some possible implementation manners, the capacitor further includes a substrate, and the at least one stacked structure is disposed above the substrate.

在一些可能的实现方式中，所述n层导电层中，与所述衬底的距离越小，在所述衬底上的投影面积越大。In some possible implementation manners, in the n-layer conductive layer, the smaller the distance from the substrate, the larger the projected area on the substrate.

在一些可能的实现方式中，所述电容器还包括：第一导电材料层和第二导电材料层，In some possible implementation manners, the capacitor further includes: a first conductive material layer and a second conductive material layer,

其中，所述第一导电材料层通过所述至少一个第一台阶结构的部分或者全部台阶面电连接所述n层导电层中的部分或者全部奇数层导电层，所述第二导电材料层通过所述至少一个第二台阶结构的部分或者全部台阶面电连接所述n层导电层中的部分或者全部偶数层导电层。Wherein, the first conductive material layer is electrically connected to part or all of the odd-numbered conductive layers in the n-layer conductive layer through part or all of the stepped surfaces of the at least one first stepped structure, and the second conductive material layer passes through Part or all of the step surfaces of the at least one second step structure are electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer.

在一些可能的实现方式中，所述第一导电材料层覆盖所述至少一个第一台阶结构的部分或者全部台阶面，以电连接所述n层导电层中的部分或者全部奇数层导电层，以及所述第二导电材料层覆盖所述至少一个第二台阶结构的部分或者全部台阶面，以电连接所述n层导电层中的部分或者全部偶数层导电层。In some possible implementation manners, the first conductive material layer covers part or all of the step surfaces of the at least one first step structure to electrically connect part or all of the odd-numbered conductive layers in the n-layer conductive layer, And the second conductive material layer covers part or all of the step surfaces of the at least one second step structure to electrically connect part or all of the even-numbered conductive layers in the n-layer conductive layer.

在一些可能的实现方式中，所述电容器还包括：第一导电通孔结构和第二导电通孔结构，In some possible implementations, the capacitor further includes: a first conductive via structure and a second conductive via structure,

其中，所述第一外接电极通过所述第一导电通孔结构电连接至所述第一导电材料层，所述第二外接电极通过所述第二导电通孔结构电连接至所述第二导电材料层。Wherein, the first external electrode is electrically connected to the first conductive material layer through the first conductive via structure, and the second external electrode is electrically connected to the second conductive material layer through the second conductive via structure. Conductive material layer.

在一些可能的实现方式中，所述电容器还包括由绝缘材料形成的边墙结构，其中，所述边墙结构覆盖所述至少一个第一台阶结构的垂直面，用于隔离所述第一导电材料层与所述至少一个第一台阶结构的垂直面，并且所述边墙结构覆盖所述至少一个第二台阶结构的垂直面，用于隔离所述第二导电材料层与所述至少一个第二台阶结构的垂直面。In some possible implementation manners, the capacitor further includes a sidewall structure formed of an insulating material, wherein the sidewall structure covers the vertical surface of the at least one first step structure, and is used to isolate the first conductive material. The material layer is perpendicular to the vertical surface of the at least one first step structure, and the side wall structure covers the vertical surface of the at least one second step structure, and is used to isolate the second conductive material layer from the at least one first step structure. The vertical plane of the two-step structure.

在一些可能的实现方式中，所述电容器还包括：多个第一导电通孔结构和多个第二导电通孔结构，其中，In some possible implementation manners, the capacitor further includes: a plurality of first conductive via structures and a plurality of second conductive via structures, wherein:

所述第一外接电极电连接所述多个第一导电通孔结构，且所述多个第一导电通孔结构通过所述至少一个第一台阶结构的部分或者全部台阶面电连接至所述n层导电层中的部分或者全部奇数层导电层；The first external electrode is electrically connected to the plurality of first conductive via structures, and the plurality of first conductive via structures are electrically connected to the at least one first stepped structure through a part or all of the stepped surfaces Part or all of the odd-numbered conductive layers in the n-layered conductive layer;

所述第二外接电极电连接所述多个第二导电通孔结构，且所述多个第二导电通孔结构通过所述至少一个第二台阶结构的部分或者全部台阶面电连接至所述n层导电层中的部分或者全部偶数层导电层。The second external electrode is electrically connected to the plurality of second conductive via structures, and the plurality of second conductive via structures are electrically connected to the step surface of the at least one second stepped structure. Part or all of the even-numbered conductive layers in the n-layer conductive layer.

在一些可能的实现方式中，所述电容器还包括：刻蚀停止层，所述刻蚀停止层覆盖所述至少一个第一台阶结构和所述至少一个第二台阶结构，所述多个第一导电通孔结构和所述多个第二导电通孔结构贯穿所述刻蚀停止层。In some possible implementation manners, the capacitor further includes: an etch stop layer covering the at least one first step structure and the at least one second step structure, and the plurality of first step structures The conductive via structure and the plurality of second conductive via structures penetrate the etch stop layer.

在一些可能的实现方式中，所述电容器还包括衬底，所述至少一个叠层结构设置于所述衬底的上方，并且所述刻蚀停止层还覆盖所述衬底。In some possible implementation manners, the capacitor further includes a substrate, the at least one stacked structure is disposed above the substrate, and the etch stop layer also covers the substrate.

在一些可能的实现方式中，所述n层导电层中的导电层的厚度范围为5nm～1mm。In some possible implementation manners, the thickness of the conductive layer in the n-layer conductive layer ranges from 5 nm to 1 mm.

在一些可能的实现方式中，所述m层电介质层中的电介质层的厚度范围为1nm～10um。In some possible implementation manners, the thickness of the dielectric layer in the m-layer dielectric layer ranges from 1 nm to 10 um.

在一些可能的实现方式中，所述n层导电层中的导电层的厚度大于所述m层电介质层中的电介质层的厚度。In some possible implementation manners, the thickness of the conductive layer in the n-layer conductive layer is greater than the thickness of the dielectric layer in the m-layer dielectric layer.

在一些可能的实现方式中，所述电容器还包括衬底，所述至少一个叠层结构设置于所述衬底的上方，并且所述第二外接电极还电连接至所述衬底。In some possible implementation manners, the capacitor further includes a substrate, the at least one stacked structure is disposed above the substrate, and the second external electrode is also electrically connected to the substrate.

在一些可能的实现方式中，所述衬底由电阻率小于阈值的材料形成，或者，所述衬底的表面形成有重掺杂的导电层或者重掺杂的导电区域。In some possible implementation manners, the substrate is formed of a material with a resistivity less than a threshold, or a heavily doped conductive layer or a heavily doped conductive region is formed on the surface of the substrate.

在一些可能的实现方式中，所述电容器还包括：电极层，设置于所述叠层结构的上方，所述电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，所述第一导电区域形成所述第一外接电极，所述第二导电区域形成所述第二外接电极。In some possible implementation manners, the capacitor further includes: an electrode layer disposed above the laminated structure, the electrode layer includes at least one first conductive region and at least one second conductive region that are separated from each other, so The first conductive area forms the first external electrode, and the second conductive area forms the second external electrode.

在一些可能的实现方式中，所述至少一个叠层结构中不同叠层结构共用同一个所述第一外接电极，和/或，不同叠层结构共用同一个所述第二外接电极。In some possible implementation manners, different stacked structures in the at least one stacked structure share the same first external electrode, and/or different stacked structures share the same second external electrode.

在一些可能的实现方式中，所述n层导电层中的导电层包括以下中的至少一层：In some possible implementation manners, the conductive layer in the n-layer conductive layer includes at least one of the following:

重掺杂多晶硅层，碳层，铝层，铜层，钨层，钛层，钽层，铂层，镍层，钌层，铱层，铑层，氮化钽层，氮化钛层，氮化钌层。Heavily doped polysilicon layer, carbon layer, aluminum layer, copper layer, tungsten layer, titanium layer, tantalum layer, platinum layer, nickel layer, ruthenium layer, iridium layer, rhodium layer, tantalum nitride layer, titanium nitride layer, nitrogen Ruthenium layer.

在一些可能的实现方式中，所述m层电介质层中的电介质层包括以下中的至少一层：In some possible implementation manners, the dielectric layer in the m-layer dielectric layer includes at least one of the following:

硅的氧化物层，硅的氮化物层，硅的氮氧化物层，金属的氧化物层，金属的氮化物层，金属的氮氧化物层。Silicon oxide layer, silicon nitride layer, silicon oxynitride layer, metal oxide layer, metal nitride layer, metal oxynitride layer.

第二方面，提供了一种电容器的制作方法，包括：In the second aspect, a method for manufacturing a capacitor is provided, including:

在衬底上方制备至少一个叠层结构，所述叠层结构包括n层导电层和m层电介质层，所述n层导电层和所述m层电介质层形成导电层与电介质层彼此相邻的结构，并且所述n层导电层中的所有奇数层导电层形成至少一个第一台阶结构，所述n层导电层中的所有偶数层导电层形成至少一个第二台阶结构，m、n为正整数；At least one laminated structure is prepared over the substrate, the laminated structure includes an n-layer conductive layer and an m-layer dielectric layer, and the n-layer conductive layer and the m-layer dielectric layer form the conductive layer and the dielectric layer adjacent to each other Structure, and all odd-numbered conductive layers in the n-layer conductive layer form at least one first stepped structure, and all even-numbered conductive layers in the n-layer conductive layer form at least one second stepped structure, and m and n are positive Integer

制备至少一个第一外接电极和至少一个第二外接电极，其中，所述第一外接电极通过所述至少一个第一台阶结构的台阶面电连接至所述n层导电层中的部分或者全部奇数层导电层，所述第二外接电极通过所述至少一个第二台阶结构的台阶面电连接至所述n层导电层中的部分或者全部偶数层导电层。At least one first external electrode and at least one second external electrode are prepared, wherein the first external electrode is electrically connected to a part or all of the odd numbers in the n-layer conductive layer through the step surface of the at least one first step structure A conductive layer, and the second external electrode is electrically connected to some or all of the even-numbered conductive layers in the n-layer conductive layer through the step surface of the at least one second stepped structure.

在一些可能的实现方式中，所述在衬底上方制备至少一个叠层结构，包括：In some possible implementation manners, the preparing at least one laminated structure above the substrate includes:

利用光刻胶修整工艺，在所述叠层结构上形成所述至少一个第一台阶结构和所述至少一个第二台阶结构。Using a photoresist trimming process, the at least one first step structure and the at least one second step structure are formed on the stacked structure.

在一些可能的实现方式中，所述方法还包括：In some possible implementation manners, the method further includes:

制备第一导电材料层和第二导电材料层，Preparing the first conductive material layer and the second conductive material layer,

制备第一导电通孔结构和第二导电通孔结构，Preparing a first conductive via structure and a second conductive via structure,

制备由绝缘材料形成的边墙结构，其中，所述边墙结构覆盖所述至少一个第一台阶结构的垂直面，用于隔离所述第一导电材料层与所述至少一个第一台阶结构的垂直面，并且所述边墙结构覆盖所述至少一个第二台阶结构的垂直面，用于隔离所述第二导电材料层与所述至少一个第二台阶结构的垂直面。Prepare a sidewall structure formed of an insulating material, wherein the sidewall structure covers the vertical surface of the at least one first step structure and is used to isolate the first conductive material layer from the at least one first step structure The vertical surface, and the side wall structure covers the vertical surface of the at least one second step structure, and is used to isolate the second conductive material layer from the vertical surface of the at least one second step structure.

制备多个第一导电通孔结构和多个第二导电通孔结构，其中，A plurality of first conductive via structures and a plurality of second conductive via structures are prepared, wherein,

制备刻蚀停止层，所述刻蚀停止层覆盖所述至少一个第一台阶结构和所述至少一个第二台阶结构，所述多个第一导电通孔结构和所述多个第二导电通孔结构贯穿所述刻蚀停止层。An etch stop layer is prepared, the etch stop layer covers the at least one first step structure and the at least one second step structure, the plurality of first conductive via structures and the plurality of second conductive vias The hole structure penetrates the etch stop layer.

在一些可能的实现方式中，所述刻蚀停止层还覆盖所述衬底。In some possible implementations, the etch stop layer also covers the substrate.

在一些可能的实现方式中，所述第二外接电极还电连接至所述衬底。In some possible implementations, the second external electrode is also electrically connected to the substrate.

在一些可能的实现方式中，所述制备至少一个第一外接电极和至少一个第二外接电极，包括：In some possible implementation manners, the preparing at least one first external electrode and at least one second external electrode includes:

在所述叠层结构上方制备电极层，所述电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，所述第一导电区域形成所述第一外接电极，所述第二导电区域形成所述第二外接电极。An electrode layer is prepared above the laminated structure. The electrode layer includes at least one first conductive region and at least one second conductive region that are separated from each other. The first conductive region forms the first external electrode, and the first conductive region forms the first external electrode. Two conductive regions form the second external electrode.

因此，在本申请实施例中，叠层结构形成有至少一个第一台阶结构，以露出n层导电层中的所有奇数层导电层，且叠层结构形成有至少一个第二台阶结构，以露出n层导电层中的所有偶数层导电层，第一外接电极通过至少一个第一台阶结构的台阶面电连接至n层导电层中的部分或者全部奇数层导电层，第二外接电极通过至少一个第二台阶结构的台阶面电连接至n层导电层中的部分或者全部偶数层导电层，从而能够制备三维硅电容器，能够在制备小体积、高容值密度的电容器的同时降低电容器成本。Therefore, in the embodiment of the present application, the stacked structure is formed with at least one first step structure to expose all odd-numbered conductive layers in the n-layer conductive layer, and the stacked structure is formed with at least one second step structure to expose For all the even-numbered conductive layers in the n-layer conductive layer, the first external electrode is electrically connected to some or all of the odd-numbered conductive layers in the n-layer conductive layer through at least one step surface of the first stepped structure, and the second external electrode passes through at least one The step surface of the second step structure is electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer, so that a three-dimensional silicon capacitor can be prepared, which can reduce the cost of the capacitor while preparing a capacitor with a small volume and a high capacitance value density.

附图说明Description of the drawings

图1是本申请提供的一种电容器的示意性结构图。Fig. 1 is a schematic structural diagram of a capacitor provided by the present application.

图2是根据本申请实施例的光刻胶修整工艺的示意图。Fig. 2 is a schematic diagram of a photoresist trimming process according to an embodiment of the present application.

图3是根据本申请实施例的一种外接电极的俯视图。Fig. 3 is a top view of an external electrode according to an embodiment of the present application.

图4是根据本申请实施例的另一种外接电极的俯视图。Fig. 4 is a top view of another external electrode according to an embodiment of the present application.

图5是根据本申请实施例的不同叠层结构的示意性图。Fig. 5 is a schematic diagram of different laminated structures according to an embodiment of the present application.

图6是根据本申请实施例的一种叠层结构的示意性立体结构图。Fig. 6 is a schematic three-dimensional structural diagram of a laminated structure according to an embodiment of the present application.

图7是根据本申请实施例的另一种叠层结构的立体制备流程示意性图。Fig. 7 is a schematic diagram of a three-dimensional preparation process of another laminated structure according to an embodiment of the present application.

图8是根据本申请实施例的另一种电容器的示意性结构图。Fig. 8 is a schematic structural diagram of another capacitor according to an embodiment of the present application.

图9是根据本申请实施例的一种电容器的制作方法的示意性流程图。Fig. 9 is a schematic flowchart of a method for manufacturing a capacitor according to an embodiment of the present application.

图10a至图10p是本申请实施例的一种电容器的制作方法的示意图。10a to 10p are schematic diagrams of a manufacturing method of a capacitor according to an embodiment of the present application.

具体实施方式Detailed ways

下面将结合附图，对本申请实施例中的技术方案进行描述。The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings.

应理解，本申请实施例的电容器在电路中可以起到旁路、滤波、去耦等作用。It should be understood that the capacitors in the embodiments of the present application can perform functions such as bypassing, filtering, and decoupling in the circuit.

借助于先进的半导体加工工艺，制作超薄型、高可靠性的电容器已经成为可能。为了提高容值密度，现有硅电容一般采用多层堆叠的技术方案。通过在高深宽比(High aspect ratio)的三维(3D)结构(例如，凹槽，凸台等)表面制作垂直堆叠的2-3个电容器，再利用金属互联结构将多个电容并联。然而，高深宽比的三维结构本身的加工难度较大，而且在此三维结构上制作共形的、厚度均匀且没有缺陷的导电层、电介质层也需要极高的工艺水准，加工成本因此较为昂贵。With the help of advanced semiconductor processing technology, it has become possible to produce ultra-thin, high-reliability capacitors. In order to increase the capacitance density, existing silicon capacitors generally adopt a multi-layer stacking technical solution. By fabricating vertically stacked 2-3 capacitors on the surface of a high aspect ratio three-dimensional (3D) structure (for example, grooves, bosses, etc.), a metal interconnection structure is used to connect multiple capacitors in parallel. However, the high aspect ratio three-dimensional structure itself is more difficult to process, and the production of conformal, uniform thickness and defect-free conductive layers and dielectric layers on this three-dimensional structure also requires a very high level of technology, and the processing cost is therefore relatively expensive. .

在此背景下，本申请提出了一种新型的电容器的结构和制作方法，通过在平坦的衬底表面制作多个导电薄膜和电介质薄膜的交替叠层，并最终实现奇数导电层的互连和偶数导电层的互连。由于避免了3D结构相关的刻蚀、沉积等昂贵工艺，且通过光刻胶修整(Photoresist Trimming)工艺有效减少了光刻次数，从而能够在制备小体积、高容值密度的电容器的同时降低电容器成本。In this context, this application proposes a new type of capacitor structure and manufacturing method, by fabricating multiple alternating layers of conductive films and dielectric films on a flat substrate surface, and finally realize the interconnection and interconnection of odd-numbered conductive layers. Interconnection of even-numbered conductive layers. Because expensive processes such as etching and deposition related to the 3D structure are avoided, and the photoresist trimming process is used to effectively reduce the number of photolithography, it is possible to reduce the capacitors while preparing small-volume, high-capacitance-density capacitors cost.

以下，结合图1至图8，详细介绍本申请实施例的电容器。Hereinafter, the capacitor of the embodiment of the present application will be described in detail with reference to FIGS. 1 to 8.

应理解，图1和图8中的电容器及电容器中所包括的叠层结构仅仅只是示例，叠层结构的数量以及叠层结构所包括的导电层的数量和电介质层的数量仅仅只是示例，叠层结构所包括的导电层的数量以及电介质层的数量并不局限于图1和图8中的电容器所示，可以根据实际需要灵活设置。It should be understood that the capacitors in FIGS. 1 and 8 and the laminated structure included in the capacitor are merely examples, and the number of laminated structures and the number of conductive layers and the number of dielectric layers included in the laminated structure are merely examples. The number of conductive layers and the number of dielectric layers included in the layer structure are not limited to those shown in the capacitors in FIGS. 1 and 8, and can be flexibly set according to actual needs.

需要说明的是，为便于理解，在以下示出的实施例中，对于不同实施例中示出的结构中，相同的结构采用相同的附图标记，并且为了简洁，省略对相同结构的详细说明。It should be noted that, for ease of understanding, in the embodiments shown below, for the structures shown in different embodiments, the same structures are given the same reference numerals, and for the sake of brevity, detailed descriptions of the same structures are omitted. .

图1是本申请一个实施例的电容器100的一种可能的结构图。如图1所示，该电容器100包括至少一个叠层结构120、至少一个第一外接电极130、至少一个第二外接电极140。FIG. 1 is a possible structural diagram of a capacitor 100 according to an embodiment of the present application. As shown in FIG. 1, the capacitor 100 includes at least one laminated structure 120, at least one first external electrode 130, and at least one second external electrode 140.

具体地，如图1所示，在该电容器100中，该叠层结构120包括n层导电层和m层电介质层，该n层导电层和该m层电介质层形成导电层与电介质层彼此相邻的结构，并且该n层导电层中的所有奇数层导电层形成至少一个第一台阶结构10，该n层导电层中的所有偶数层导电层形成至少一个第二台阶结构20，m、n为正整数；该第一外接电极130通过该至少一个第一台阶结构10的台阶面电连接至该n层导电层中的部分或者全部奇数层导电层；该第二外接电极140通过该至少一个第二台阶结构20的台阶面电连接至该n层导电层中的部分或者全部偶数层导电层。Specifically, as shown in FIG. 1, in the capacitor 100, the laminated structure 120 includes an n-layer conductive layer and an m-layer dielectric layer, and the n-layer conductive layer and the m-layer dielectric layer form a conductive layer and a dielectric layer that are mutually opposite to each other. Adjacent structure, and all odd-numbered conductive layers in the n-layer conductive layer form at least one first stepped structure 10, and all even-numbered conductive layers in the n-layer conductive layer form at least one second stepped structure 20, m, n Is a positive integer; the first external electrode 130 is electrically connected to some or all of the odd-numbered conductive layers in the n-layer conductive layer through the step surface of the at least one first stepped structure 10; the second external electrode 140 is electrically connected through the at least one The step surface of the second step structure 20 is electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer.

在本申请实施例中，叠层结构形成有至少一个第一台阶结构，以露出n层导电层中的所有奇数层导电层，且叠层结构形成有至少一个第二台阶结构，以露出n层导电层中的所有偶数层导电层，第一外接电极通过至少一个第一台阶结构的台阶面电连接至n层导电层中的部分或者全部奇数层导电层，第二外接电极通过至少一个第二台阶结构的台阶面电连接至n层导电层中的部分或者全部偶数层导电层，从而能够制备三维硅电容器，能够在制备小体积、高容值密度的电容器的同时降低电容器成本。In the embodiment of the present application, the stacked structure is formed with at least one first step structure to expose all odd-numbered conductive layers in the n-layer conductive layer, and the stacked structure is formed with at least one second step structure to expose the n-layer For all the even-numbered conductive layers in the conductive layer, the first external electrode is electrically connected to part or all of the odd-numbered conductive layers in the n-layer conductive layer through the step surface of at least one first step structure, and the second external electrode is connected through at least one second conductive layer. The step surface of the step structure is electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer, so that a three-dimensional silicon capacitor can be prepared, which can reduce the cost of the capacitor while preparing a capacitor with a small volume and a high capacitance value density.

需要说明的是，该n层导电层中的所有奇数层导电层错位分布，以形成至少一个第一台阶结构10，以及该n层导电层中的所有偶数层导电层错位分布，以形成至少一个第二台阶结构20。具体地，该n层导电层中的所有奇数层导电层的上表面的部分区域形成该第一台阶结构10的台阶面，以及该n层导电层中的所有奇数层导电层的某一侧面的部分或者全部区域形成该第一台阶结构10的垂直面。同理，该n层导电层中的所有偶数层导电层的上表面的部分区域形成该第二台阶结构20的台阶面，以及该n层导电层中的所有偶数层导电层的某一侧面的部分或者全部区域形成该第二台阶结构20的垂直面。It should be noted that all odd-numbered conductive layers in the n-layer conductive layer are dislocated to form at least one first step structure 10, and all even-numbered conductive layers in the n-layer conductive layer are dislocated to form at least one The second step structure 20. Specifically, a partial area of the upper surface of all odd-numbered conductive layers in the n-layer conductive layer forms the step surface of the first stepped structure 10, and a certain side surface of all odd-numbered conductive layers in the n-layer conductive layer Part or all of the area forms the vertical surface of the first step structure 10. In the same way, a partial area of the upper surface of all even-numbered conductive layers in the n-layer conductive layer forms the step surface of the second stepped structure 20, and a certain side surface of all even-numbered conductive layers in the n-layer conductive layer Part or all of the area forms the vertical surface of the second step structure 20.

应理解，该第一台阶结构10为多个台阶构成的整体，即如图1所示，该第一台阶结构10为4个台阶构成的整体，换句话说，4个由奇数层导电层形成的台阶构成该第一台阶结构10。同理，该第二台阶结构20为多个台阶构成的整体，即如图1所示，该第二台阶结构20为3个台阶构成的整体，换句话说，3个由偶数层导电层形成的台阶构成该第二台阶结构20。It should be understood that the first stepped structure 10 is a whole composed of multiple steps, that is, as shown in FIG. 1, the first stepped structure 10 is a whole composed of 4 steps, in other words, the 4 are formed by odd-numbered conductive layers. The steps constitute the first step structure 10. In the same way, the second step structure 20 is a whole composed of a plurality of steps, that is, as shown in FIG. 1, the second step structure 20 is a whole composed of three steps, in other words, three are formed by even-numbered conductive layers The steps constitute the second step structure 20.

可选地，在本申请实施例中，该电容器100还可以包括衬底110，该至少一个叠层结构120设置于衬底110的上方，如图1所示。Optionally, in the embodiment of the present application, the capacitor 100 may further include a substrate 110, and the at least one stacked structure 120 is disposed above the substrate 110, as shown in FIG. 1.

需要说明的是，本申请实施例中图1是沿着衬底纵向的截面图。It should be noted that FIG. 1 in the embodiment of the present application is a cross-sectional view along the longitudinal direction of the substrate.

在本申请实施例中，该n层导电层中相邻的两个导电层通过电介质层电隔离，以及m和n的具体数值可以根据实际需要灵活配置，只需满足该n层导电层中相邻两个导电层之间电隔离。In the embodiment of the present application, two adjacent conductive layers in the n-layer conductive layer are electrically isolated by a dielectric layer, and the specific values of m and n can be flexibly configured according to actual needs. The two adjacent conductive layers are electrically isolated.

例如，在该衬底110不参与形成电容器100的电极板的情况下，该叠层结构120中的第一层导电层可以直接设置在该衬底110的上表面，即n＝m+1。For example, when the substrate 110 does not participate in forming the electrode plate of the capacitor 100, the first conductive layer in the laminated structure 120 may be directly disposed on the upper surface of the substrate 110, that is, n=m+1.

又例如，在该衬底110参与形成电容器100的电极板的情况下，该叠层结构120中的第一层导电层与该衬底110之间需要设置电介质层，以隔离该第一层导电层和该衬底110，即n＝m。For another example, when the substrate 110 participates in the formation of the electrode plate of the capacitor 100, a dielectric layer needs to be provided between the first conductive layer of the laminated structure 120 and the substrate 110 to isolate the first conductive layer. The layer and the substrate 110, that is, n=m.

可选地，m≥2和/或n≥2。Optionally, m≥2 and/or n≥2.

可选地，该n层导电层中相邻的两个导电层错位分布。Optionally, two adjacent conductive layers in the n-layer conductive layer are dislocated.

应理解，本申请实施例中外接电极也可以称之为焊盘或者外接焊盘。It should be understood that the external electrode in the embodiment of the present application may also be referred to as a pad or an external pad.

还应理解，利用光刻工艺制作有Q个阶梯的台阶结构，需要进行Q次光刻，其加工成本与Q成正比。本申请实施例所采用的光刻胶修整(Photoresist Trimming，PR trimming)工艺是指通过干法刻蚀，横向回退去除部分光刻胶，露出待刻蚀材料表面的工艺。在制作阶梯数量较大的台阶结构时，使用PR trimming工艺和刻蚀(etch)工艺这两步骤交替循环进行，如图2所示，可以有效减少光刻次数，降低制造成本。It should also be understood that the use of a photolithography process to produce a step structure with Q steps requires Q times of photolithography, and the processing cost is proportional to Q. The photoresist trimming (PR trimming) process used in the embodiments of the present application refers to a process in which part of the photoresist is removed laterally by dry etching to expose the surface of the material to be etched. When making a step structure with a large number of steps, the two steps of the PR trimming process and the etch process are used alternately and cyclically, as shown in Figure 2, which can effectively reduce the number of photolithography and reduce the manufacturing cost.

可选地，在本申请实施例中，该衬底110可以为硅晶圆，包括单晶硅、多晶硅、不定形硅。该衬底110也可以是别的半导体衬底，包括绝缘衬底上的硅(Silicon-On-Insulator，SOI)晶圆，碳化硅(SiC)、氮化镓(GaN)、砷化镓(GaAs)等III-V族元素的化合物半导体晶圆；该衬底110也可以是非半导体衬底，例如玻璃衬底，有机聚合物衬底，陶瓷衬底。该衬底110的表面包含外延层、氧化层、掺杂层、键合层、低电阻值区域等。Optionally, in the embodiment of the present application, the substrate 110 may be a silicon wafer, including monocrystalline silicon, polycrystalline silicon, and amorphous silicon. The substrate 110 may also be other semiconductor substrates, including silicon-on-insulator (SOI) wafers, silicon carbide (SiC), gallium nitride (GaN), and gallium arsenide (GaAs) wafers. ) And other compound semiconductor wafers of group III-V elements; the substrate 110 may also be a non-semiconductor substrate, such as a glass substrate, an organic polymer substrate, or a ceramic substrate. The surface of the substrate 110 includes an epitaxial layer, an oxide layer, a doped layer, a bonding layer, a low resistance region, and the like.

需要注意的是，在本申请实施例中，该衬底110的厚度也可以根据实际需要灵活设置，例如，在该衬底110的厚度因太厚而不能满足需求时，可以对该衬底110进行减薄处理，甚至完全去除该衬底110。It should be noted that in the embodiment of the present application, the thickness of the substrate 110 can also be flexibly set according to actual needs. For example, when the thickness of the substrate 110 is too thick to meet the requirements, the substrate 110 can be The thinning process is performed, and even the substrate 110 is completely removed.

可选地，该第一外接电极130和该第二外接电极140的材料可以是金属，例如铜、铝等。该第一外接电极130和该第二外接电极140还可以包含低电阻率的Ti，TiN，Ta，TaN层作为黏附层和/或阻挡层；还可能包含位于外接电极表面的一些金属层，例如Ni、Pd(钯)、Au、Sn(锡)、Ag，用于后续打线或焊接工艺。Optionally, the material of the first external electrode 130 and the second external electrode 140 may be metal, such as copper, aluminum, or the like. The first external electrode 130 and the second external electrode 140 may also include low resistivity Ti, TiN, Ta, TaN layers as adhesion layers and/or barrier layers; they may also include some metal layers on the surface of the external electrodes, such as Ni, Pd (palladium), Au, Sn (tin), Ag are used for subsequent wire bonding or welding processes.

可选地，本申请实施例中，该n层导电层中的导电层包括以下中的至少一层：Optionally, in the embodiment of the present application, the conductive layer in the n-layer conductive layer includes at least one of the following:

也就是说，在该叠层结构120中，该n层导电层中的导电层的材料可以是重掺杂多晶硅，碳，铝(Al)、钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、铂(Pt)、钌(Ru)、铱(Ir)、铑(Rh)、镍(Ni)等金属，氮化钽(TaN)、氮化钛(TiN)、氮化钌(RuN)等低电阻率化合物，或者该n层导电层中的导电层为上述材料的组合、叠层、复合结构。也就是说，该n层导电层中的一个导电层可以是一层或包含多个叠层，该n层导电层中的某一层导电层可以是单一材料形成的单层，也可以是多种材料形成的复合层。That is, in the laminated structure 120, the material of the conductive layer in the n-layer conductive layer may be heavily doped polysilicon, carbon, aluminum (Al), tungsten (W), copper (Cu), titanium (Ti) ), tantalum (Ta), platinum (Pt), ruthenium (Ru), iridium (Ir), rhodium (Rh), nickel (Ni) and other metals, tantalum nitride (TaN), titanium nitride (TiN), nitride Low-resistivity compounds such as ruthenium (RuN), or the conductive layer in the n-layer conductive layer is a combination, laminate, or composite structure of the above-mentioned materials. That is to say, one conductive layer in the n-layer conductive layer may be one layer or multiple stacked layers, and a certain conductive layer in the n-layer conductive layer may be a single layer formed of a single material or multiple layers. A composite layer formed from a variety of materials.

需要注意的是，该n层导电层中的不同导电层的材料、厚度等可以相同，也可以不同。该n层导电层中的导电层的具体导电材料和层厚可根据电容器的容值、频率特性、损耗等需求来调整。当然，该n层导电层中的导电层的还可以包括一些其他的导电材料，本申请实施例对此不作限定。It should be noted that the materials and thicknesses of different conductive layers in the n-layer conductive layer may be the same or different. The specific conductive material and layer thickness of the conductive layer in the n-layer conductive layer can be adjusted according to the capacitance, frequency characteristics, loss and other requirements of the capacitor. Of course, the conductive layer in the n-layer conductive layer may also include some other conductive materials, which is not limited in the embodiment of the present application.

可选地，本申请实施例中，该m层电介质层中的电介质层包括以下中的至少一层：Optionally, in the embodiment of the present application, the dielectric layer in the m-layer dielectric layer includes at least one of the following:

硅的氧化物层，硅的氮化物层，硅的氮氧化物层，金属的氧化物层，金属的氮化物层和金属的氮氧化物层。Silicon oxide layer, silicon nitride layer, silicon oxynitride layer, metal oxide layer, metal nitride layer and metal oxynitride layer.

也就是说，在该叠层结构120中，该m层电介质层中的电介质层的材料可以是硅的氧化物，硅的氮化物，硅的氮氧化物，金属的氧化物，金属的氮化物，金属的氮氧化物。例如SiO ₂，SiN，SiON，或者高介电常数(high-k)材料，包括Al ₂O ₃，HfO ₂，ZrO ₂，TiO ₂，Y ₂O ₃，La ₂O ₃，HfSiO ₄，LaAlO ₃，SrTiO ₃，LaLuO ₃等。该m层电介质层中的一个电介质层可以是一层或包含多个叠层，该m层电介质层中的一个电介质层可以是一种材料或多种材料的组合、混合。 That is, in the stacked structure 120, the material of the dielectric layer in the m-layer dielectric layer may be silicon oxide, silicon nitride, silicon oxynitride, metal oxide, or metal nitride. , Metal oxynitride. For example, SiO ₂ , SiN, SiON, or high-k materials, including Al ₂ O ₃ , HfO ₂ , ZrO ₂ , TiO ₂ , Y ₂ O ₃ , La ₂ O ₃ , HfSiO ₄ , LaAlO ₃ , SrTiO ₃ , LaLuO ₃ and so on. One dielectric layer in the m-layer dielectric layer may be one layer or a plurality of stacked layers, and one dielectric layer in the m-layer dielectric layer may be one material or a combination or mixture of multiple materials.

需要注意的是，该m层电介质层中的不同电介质层的材料、厚度等可以相同，也可以不同。该m层电介质层中的电介质层的具体绝缘材料和层厚可根据电容器的容值、频率特性、损耗等需求来调整。当然，该m层电介质层中的电介质层还可以包括一些其他的绝缘材料，本申请实施例对此不作限定。It should be noted that the materials and thicknesses of different dielectric layers in the m-layer dielectric layer may be the same or different. The specific insulating material and layer thickness of the dielectric layer in the m-layer dielectric layer can be adjusted according to the capacitance, frequency characteristics, loss and other requirements of the capacitor. Of course, the dielectric layer in the m-layer dielectric layer may also include some other insulating materials, which is not limited in the embodiment of the present application.

需要说明的是，在该叠层结构120中，该m层电介质层的顺序是：在衬底110上，与衬底110的距离从小到大的顺序。同理，该n层导电层的顺序是：在衬底110上，与衬底110的距离从小到大的顺序。It should be noted that, in the stacked structure 120, the order of the m-layer dielectric layer is: on the substrate 110, the distance from the substrate 110 is ascending. In the same way, the order of the n-layer conductive layer is: on the substrate 110, the distance from the substrate 110 is ascending order.

可选地，在本申请实施例中，该n层导电层中，与该衬底的距离越小，在该衬底上的投影面积越大，如图1所示。Optionally, in the embodiment of the present application, in the n-layer conductive layer, the smaller the distance from the substrate, the larger the projected area on the substrate, as shown in FIG. 1.

可选地，该n层导电层中的导电层的厚度范围为5nm～1mm。Optionally, the thickness of the conductive layer in the n-layer conductive layer ranges from 5 nm to 1 mm.

可选地，该m层电介质层中的电介质层的厚度范围为1nm～10um。Optionally, the thickness of the dielectric layer in the m-layer dielectric layer ranges from 1 nm to 10 um.

可选地，该n层导电层中的导电层的厚度大于该m层电介质层中的电介质层的厚度。Optionally, the thickness of the conductive layer in the n-layer conductive layer is greater than the thickness of the dielectric layer in the m-layer dielectric layer.

可选地，在本申请实施例中，该至少一个叠层结构120中不同叠层结构共用同一个该第一外接电极130，和/或，不同叠层结构共用同一个该第二外接电极140。Optionally, in the embodiment of the present application, different stacked structures in the at least one stacked structure 120 share the same first external electrode 130, and/or different stacked structures share the same second external electrode 140 .

也就是说，在本申请实施例中，一个第一外接电极130可以电连接至多个叠层结构120中的部分或者全部叠层结构120，同理，一个第二外接电极140也可以电连接至多个叠层结构120中的部分或者全部叠层结构120。That is to say, in the embodiment of the present application, one first external electrode 130 may be electrically connected to some or all of the plurality of stacked structures 120. Similarly, one second external electrode 140 may also be electrically connected to at most A part or all of the stacked structure 120 is a stacked structure 120.

例如，电容器100包括两个叠层结构120、两个第一外接电极130和一个第二外接电极140，两个叠层结构120分别记为叠层结构120a和叠层结构 120b，两个第一外接电极130分别记为第一外接电极130a和第一外接电极130b，其中，第一外接电极130a、第一外接电极130b和第二外接电极140的俯视图可以如图3所示，叠层结构120a和叠层结构120b图3中未示出，第一外接电极130a和第二外接电极140电连接叠层结构120a，第一外接电极130b和第二外接电极140电连接叠层结构120b，即叠层结构120a和叠层结构120b共用一个第二外接电极140。For example, the capacitor 100 includes two stacked structures 120, two first external electrodes 130, and one second external electrode 140. The two stacked structures 120 are respectively denoted as a stacked structure 120a and a stacked structure 120b. The external electrodes 130 are respectively denoted as the first external electrode 130a and the first external electrode 130b, wherein the top view of the first external electrode 130a, the first external electrode 130b, and the second external electrode 140 can be as shown in FIG. 3, the laminated structure 120a And laminated structure 120b not shown in FIG. 3, the first external electrode 130a and the second external electrode 140 are electrically connected to the laminated structure 120a, and the first external electrode 130b and the second external electrode 140 are electrically connected to the laminated structure 120b, namely The layer structure 120a and the stacked structure 120b share a second external electrode 140.

需要说明的是，在如图3所示的电容器100中，若第一外接电极130a和第一外接电极130b之间通过一个额外的电极或者导电线电连接，且通过这一额外的电极或者导电线实现外接，则叠层结构120a和叠层结构120b在共用一个第二外接电极140的同时，也可以共用一个第一外接电极。It should be noted that, in the capacitor 100 shown in FIG. 3, if the first external electrode 130a and the first external electrode 130b are electrically connected through an additional electrode or conductive wire, and through this additional electrode or conductive line When the wires are connected to the outside, the stacked structure 120a and the stacked structure 120b can share one first external electrode while sharing one second external electrode 140.

又例如，电容器100包括两个叠层结构120、一个第一外接电极130和两个第二外接电极140，两个叠层结构120分别记为叠层结构120a和叠层结构120b，两个第二外接电极140分别记为第二外接电极140a和第二外接电极140b，其中，第一外接电极130、第二外接电极140a和第二外接电极140b的俯视图可以如图4所示，叠层结构120a和叠层结构120b图4中未示出，第一外接电极130和第二外接电极140a电连接叠层结构120a，第一外接电极130和第二外接电极140b电连接叠层结构120b，即叠层结构120a和叠层结构120b共用一个第一外接电极130。For another example, the capacitor 100 includes two stacked structures 120, a first external electrode 130, and two second external electrodes 140. The two stacked structures 120 are respectively denoted as a stacked structure 120a and a stacked structure 120b. The two external electrodes 140 are respectively denoted as the second external electrode 140a and the second external electrode 140b. The top view of the first external electrode 130, the second external electrode 140a and the second external electrode 140b can be as shown in FIG. 120a and the laminated structure 120b are not shown in FIG. 4, the first external electrode 130 and the second external electrode 140a are electrically connected to the laminated structure 120a, and the first external electrode 130 and the second external electrode 140b are electrically connected to the laminated structure 120b, namely The stacked structure 120a and the stacked structure 120b share a first external electrode 130.

需要说明的是，在如图4所示的电容器100中，若第二外接电极140a和第二外接电极140b之间通过一个额外的电极或者导电线电连接，且通过这一额外的电极或者导电线实现外接，则叠层结构120a和叠层结构120b在共用一个第一外接电极130的同时，也可以共用一个第二外接电极。It should be noted that, in the capacitor 100 shown in FIG. 4, if the second external electrode 140a and the second external electrode 140b are electrically connected through an additional electrode or conductive wire, and through this additional electrode or conductive wire If the wires are connected to each other, the stacked structure 120a and the stacked structure 120b may share a second external electrode while sharing one first external electrode 130.

在本申请实施例中，在该第一外接电极130电连接至该n层导电层中的所有奇数层导电层，以及该第二外接电极140电连接至该n层导电层中的所有偶数层导电层的情况下，该电容器100的容值最大，也即，在这种情况下可以充分发挥叠层结构增加电容器的容值密度的效果。In the embodiment of the present application, the first external electrode 130 is electrically connected to all odd-numbered conductive layers in the n-layer conductive layer, and the second external electrode 140 is electrically connected to all even-numbered layers in the n-layer conductive layer In the case of the conductive layer, the capacitance of the capacitor 100 is the largest, that is, in this case, the effect of the laminated structure of increasing the capacitance density of the capacitor can be fully exerted.

进一步地，相较于基于凹槽或者凸台而制备的电容器，本申请实施例中的电容器在导电层堆叠的过程中不受凹槽、凸台等3D结构的约束，可以堆叠更多的导电层，从而可以形成具有更高容值密度的电容器。Further, compared to capacitors prepared based on grooves or bosses, the capacitors in the embodiments of the present application are not restricted by 3D structures such as grooves and bosses during the process of stacking conductive layers, and can stack more conductive layers. It is possible to form a capacitor with a higher capacitance density.

需要说明的是，在本申请实施例中，一个电容器可以包括一个叠层结构，也可以包括多个叠层结构。例如，如图5所示，该电容器100包括2个叠层结构120，分别记为叠层结构120a和叠层结构120b，该叠层结构120a和该叠层结构120b为两个在衬底110上有着不同投影位置的独立电容。若仅将第一外接电极130和第二外接电极140电连接至该叠层结构120a，则可以形成电容器A；若仅将第一外接电极130和第二外接电极140电连接至该叠层结构120b，则可以形成电容器B；若将第一外接电极130和第二外接电极140电连接至该叠层结构120a和该叠层结构120b，则可以形成等效电容器C，其中，电容器C的容值为电容器A的容值与电容器B的容值之和。It should be noted that, in the embodiment of the present application, a capacitor may include one laminated structure or multiple laminated structures. For example, as shown in FIG. 5, the capacitor 100 includes two stacked structures 120, which are respectively denoted as stacked structure 120a and stacked structure 120b. The stacked structure 120a and the stacked structure 120b are two on the substrate 110. There are independent capacitors with different projection positions. If only the first external electrode 130 and the second external electrode 140 are electrically connected to the stacked structure 120a, a capacitor A can be formed; if only the first external electrode 130 and the second external electrode 140 are electrically connected to the stacked structure 120b, the capacitor B can be formed; if the first external electrode 130 and the second external electrode 140 are electrically connected to the stacked structure 120a and the stacked structure 120b, an equivalent capacitor C can be formed, wherein the capacitance of the capacitor C The value is the sum of the capacitance of capacitor A and the capacitance of capacitor B.

具体地，如图5所示，该叠层结构120a和该叠层结构120b都包括7个导电层，该叠层结构120a和该叠层结构120b之间存在一个相连的导电层。当然，该叠层结构120a和该叠层结构120b也可以完全隔离。另外，该叠层结构120a和该叠层结构120b具有相同的导电层，从而该叠层结构120a和该叠层结构120b可以采用相同的参数同步制备形成，当然，在制备更多的叠层结构时同样适用。Specifically, as shown in FIG. 5, both the stacked structure 120a and the stacked structure 120b include 7 conductive layers, and there is a connected conductive layer between the stacked structure 120a and the stacked structure 120b. Of course, the stacked structure 120a and the stacked structure 120b can also be completely isolated. In addition, the laminated structure 120a and the laminated structure 120b have the same conductive layer, so that the laminated structure 120a and the laminated structure 120b can be simultaneously prepared and formed using the same parameters. Of course, more laminated structures are being prepared. The same applies when.

另外，该电容器100所包括的至少一个叠层结构120中不同的叠层结构可以具有不同的导电层，本申请实施例对此并不限定。In addition, different laminated structures of the at least one laminated structure 120 included in the capacitor 100 may have different conductive layers, which is not limited in the embodiment of the present application.

可选地，在一些实施例中，该至少一个第一台阶结构10与该至少一个第二台阶结构20分别位于该叠层结构120的不同侧。例如，如图1所示，该至少一个第一台阶结构10与该至少一个第二台阶结构20分别位于该叠层结构120的两侧，另外，该叠层结构120的三维结构可以如图6所示。Optionally, in some embodiments, the at least one first step structure 10 and the at least one second step structure 20 are respectively located on different sides of the laminated structure 120. For example, as shown in FIG. 1, the at least one first stepped structure 10 and the at least one second stepped structure 20 are respectively located on both sides of the stacked structure 120. In addition, the three-dimensional structure of the stacked structure 120 may be as shown in FIG. Shown.

可选地，在一些实施例中，该至少一个第一台阶结构10与该至少一个第二台阶结构20位于该叠层结构120的同一侧，该叠层结构120的三维结构可以基于如图7所示的流程制备。需要说明的是，图7中的掩模层后续可以去除。Optionally, in some embodiments, the at least one first stepped structure 10 and the at least one second stepped structure 20 are located on the same side of the stacked structure 120, and the three-dimensional structure of the stacked structure 120 may be based on FIG. 7 Prepared by the procedure shown. It should be noted that the mask layer in FIG. 7 can be removed later.

可选地，在一些实施例中，该电容器100还包括：第一导电材料层150和第二导电材料层160，其中，该第一导电材料层150通过该至少一个第一台阶结构10的台阶面电连接该n层导电层中的部分或者全部奇数层导电层，该第二导电材料层160通过该至少一个第二台阶结构20的台阶面电连接该n层导电层中的部分或者全部偶数层导电层。Optionally, in some embodiments, the capacitor 100 further includes: a first conductive material layer 150 and a second conductive material layer 160, wherein the first conductive material layer 150 passes through the steps of the at least one first step structure 10 The surface is electrically connected to part or all of the odd-numbered conductive layers in the n-layer conductive layer, and the second conductive material layer 160 is electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer through the step surface of the at least one second step structure 20 Layer conductive layer.

例如，如图1所示，该第一导电材料层150通过该至少一个第一台阶结构10的台阶面电连接该n层导电层中的全部奇数层导电层，该第二导电材料层160通过该至少一个第二台阶结构20的台阶面电连接该n层导电层中的全部偶数层导电层。For example, as shown in FIG. 1, the first conductive material layer 150 is electrically connected to all odd-numbered conductive layers in the n-layer conductive layer through the step surface of the at least one first stepped structure 10, and the second conductive material layer 160 passes through The step surface of the at least one second step structure 20 is electrically connected to all the even-numbered conductive layers in the n-layer conductive layer.

可选地，该第一导电材料层150覆盖该至少一个第一台阶结构10的部分或者全部台阶面，以电连接该n层导电层中的部分或者全部奇数层导电层，以及该第二导电材料层160覆盖该至少一个第二台阶结构20的部分或者全部台阶面，以电连接该n层导电层中的部分或者全部偶数层导电层。Optionally, the first conductive material layer 150 covers part or all of the stepped surfaces of the at least one first stepped structure 10 to electrically connect part or all of the odd-numbered conductive layers in the n-layer conductive layer and the second conductive layer. The material layer 160 covers part or all of the step surface of the at least one second step structure 20 to electrically connect part or all of the even-numbered conductive layers in the n-layer conductive layer.

例如，如图1所示，该第一导电材料层150覆盖该至少一个第一台阶结构10的全部台阶面，以电连接该n层导电层中的全部奇数层导电层，以及该第二导电材料层160覆盖该至少一个第二台阶结构20的全部台阶面，以电连接该n层导电层中的全部偶数层导电层。For example, as shown in FIG. 1, the first conductive material layer 150 covers all the step surfaces of the at least one first step structure 10 to electrically connect all odd-numbered conductive layers in the n-layer conductive layer and the second conductive layer. The material layer 160 covers all the step surfaces of the at least one second step structure 20 to electrically connect all the even-numbered conductive layers in the n-layer conductive layer.

可选地，该电容器100还包括：第一导电通孔结构170和第二导电通孔结构180，其中，该第一外接电极130通过该第一导电通孔结构170电连接至该第一导电材料层150，该第二外接电极140通过该第二导电通孔结构180电连接至该第二导电材料层160，例如，如图1所示。Optionally, the capacitor 100 further includes: a first conductive via structure 170 and a second conductive via structure 180, wherein the first external electrode 130 is electrically connected to the first conductive via structure 170 through the first conductive via structure 170 The material layer 150, the second external electrode 140 is electrically connected to the second conductive material layer 160 through the second conductive via structure 180, for example, as shown in FIG. 1.

可选地，该电容器100还包括由绝缘材料形成的边墙结构190，其中，该边墙结构190覆盖该至少一个第一台阶结构10的垂直面，用于隔离该第一导电材料层150与该至少一个第一台阶结构10的垂直面，并且该边墙结构190覆盖该至少一个第二台阶结构20的垂直面，用于隔离该第二导电材料层160与该至少一个第二台阶结构20的垂直面。Optionally, the capacitor 100 further includes a sidewall structure 190 formed of an insulating material, wherein the sidewall structure 190 covers the vertical surface of the at least one first step structure 10, and is used to isolate the first conductive material layer 150 from The vertical surface of the at least one first step structure 10, and the side wall structure 190 covers the vertical surface of the at least one second step structure 20, and is used to isolate the second conductive material layer 160 from the at least one second step structure 20 The vertical plane.

应理解，一阶台阶可以形成一个台阶面和一个垂直面，台阶面与垂直面可以垂直或者近似垂直。It should be understood that a stepped step may form a step surface and a vertical surface, and the step surface and the vertical surface may be perpendicular or approximately perpendicular.

需要说明的是，该边墙结构190的设置还能够强化相邻导电层之间的电绝缘性。It should be noted that the arrangement of the side wall structure 190 can also strengthen the electrical insulation between adjacent conductive layers.

可选地，在一个实施例中，n＝7，m＝7，即该叠层结构120可以包括7层导电层，例如图1中示出的相邻导电层之间通过电介质层电隔离，该第一导电材料层150覆盖该至少一个第一台阶结构10，以电连接该至少一个第一台阶结构10(4个阶梯的台阶)的台阶面上的所有奇数层导电层，以及该第二导电材料层160覆盖该至少一个第二台阶结构20，以电连接该至少一个第二台阶结构20(3个阶梯的台阶)的台阶面上的所有偶数层导电层。该边墙结构190覆盖该至少一个第一台阶结构10的垂直面，用于隔离该第一导电材料层150与该至少一个第一台阶结构10的垂直面，并且该边墙结构190覆盖该至少一个第二台阶结构20的垂直面，用于隔离该第二导电材料层160 与该至少一个第二台阶结构20的垂直面。Optionally, in an embodiment, n=7 and m=7, that is, the laminated structure 120 may include 7 conductive layers, for example, adjacent conductive layers shown in FIG. 1 are electrically isolated by a dielectric layer, The first conductive material layer 150 covers the at least one first stepped structure 10 to electrically connect all odd-numbered conductive layers on the step surface of the at least one first stepped structure 10 (four stepped steps), and the second The conductive material layer 160 covers the at least one second step structure 20 to electrically connect all the even-numbered conductive layers on the step surface of the at least one second step structure 20 (three steps of steps). The side wall structure 190 covers the vertical surface of the at least one first stepped structure 10 to isolate the first conductive material layer 150 from the vertical surface of the at least one first stepped structure 10, and the side wall structure 190 covers the at least one vertical surface. The vertical surface of a second step structure 20 is used to isolate the second conductive material layer 160 from the vertical surface of the at least one second step structure 20.

可选地，在一些实施例中，该电容器100还包括：多个第一导电通孔结构170和多个第二导电通孔结构180，其中，Optionally, in some embodiments, the capacitor 100 further includes: a plurality of first conductive via structures 170 and a plurality of second conductive via structures 180, wherein,

该第一外接电极130电连接该多个第一导电通孔结构170，且该多个第一导电通孔结构170通过该至少一个第一台阶结构10的部分或者全部台阶面电连接至该n层导电层中的部分或者全部奇数层导电层；The first external electrode 130 is electrically connected to the plurality of first conductive via structures 170, and the plurality of first conductive via structures 170 are electrically connected to the n through a part or all of the step surfaces of the at least one first step structure 10 Part or all of the odd-numbered conductive layers in the conductive layers;

该第二外接电极140电连接该多个第二导电通孔结构180，且该多个第二导电通孔结构180通过该至少一个第二台阶结构20的部分或者全部台阶面电连接至该n层导电层中的部分或者全部偶数层导电层。The second external electrode 140 is electrically connected to the plurality of second conductive via structures 180, and the plurality of second conductive via structures 180 are electrically connected to the n through a part or all of the step surfaces of the at least one second step structure 20 Part or all of the even-numbered conductive layers in the conductive layer.

可选地，该电容器100还包括：刻蚀停止层200，该刻蚀停止层200覆盖该至少一个第一台阶结构10和该至少一个第二台阶结构20，该多个第一导电通孔结构170和该多个第二导电通孔结构180贯穿该刻蚀停止层200。Optionally, the capacitor 100 further includes an etch stop layer 200 covering the at least one first step structure 10 and the at least one second step structure 20, and the plurality of first conductive via structures 170 and the plurality of second conductive via structures 180 penetrate the etch stop layer 200.

可选地，该刻蚀停止层200还覆盖该衬底110。Optionally, the etching stop layer 200 also covers the substrate 110.

需要说明的是，该刻蚀停止层200的设置还能够强化相邻导电层之间的电绝缘性。另外，在该刻蚀停止层200覆盖该衬底110时，该刻蚀停止层200还能够强化叠层结构120与衬底110之间的电绝缘性。It should be noted that the arrangement of the etch stop layer 200 can also strengthen the electrical insulation between adjacent conductive layers. In addition, when the etch stop layer 200 covers the substrate 110, the etch stop layer 200 can also strengthen the electrical insulation between the laminated structure 120 and the substrate 110.

应理解，该刻蚀停止层200相对于叠层结构120中的导电层和电介质层更耐刻蚀，在刻蚀导电通孔结构时，可以将导电通孔结构的底部停留在该刻蚀停止层200上，然后，通过其他工艺处理该刻蚀停止层200，以使导电通孔结构连接导电层的同时，不破坏导电层的完整性。It should be understood that the etch stop layer 200 is more resistant to etching than the conductive layer and the dielectric layer in the stacked structure 120. When the conductive via structure is etched, the bottom of the conductive via structure can stay at the etch stop. On the layer 200, then, the etch stop layer 200 is processed by other processes, so that the conductive via structure is connected to the conductive layer without destroying the integrity of the conductive layer.

换句话说，该刻蚀停止结构200能够有效防止第一导电通孔结构170和第二导电通孔结构180破坏导电层的完整性，从而可以防止因第一导电通孔结构170和第二导电通孔结构180设置而影响电容器100的性能。In other words, the etch stop structure 200 can effectively prevent the first conductive via structure 170 and the second conductive via structure 180 from damaging the integrity of the conductive layer, thereby preventing the first conductive via structure 170 and the second conductive via structure 170 from damaging the integrity of the conductive layer. The arrangement of the via structure 180 affects the performance of the capacitor 100.

可选地，该刻蚀停止层200可以是化学气相淀积(Chemical Vapor Deposition，CVD)工艺沉积的氧化硅、氮化硅、含硅玻璃(未掺杂硅玻璃(Undoped Silicon Glass，USG)、硼硅玻璃(boro-silicate glass，BSG)、磷硅玻璃(phospho-silicateglass，PSG)、硼磷硅玻璃(boro-phospho-silicateglass，BPSG))；还可以是原子层沉积(Atomic layer deposition，ALD)沉积的氧化铝；或者是喷涂、旋涂的旋转涂布玻璃(Spin on glass，SOG)、聚酰亚胺(Polyimide)等；还可以是上述材料的组合。Optionally, the etching stop layer 200 may be silicon oxide, silicon nitride, silicon-containing glass (Undoped Silicon Glass (Undoped Silicon Glass, USG), Borosilicate glass (BSG), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG)); it can also be atomic layer deposition (ALD) ) Deposited alumina; or sprayed or spin-coated spin-on glass (SOG), polyimide (Polyimide), etc.; it can also be a combination of the above materials.

可选地，在一个实施例中，n＝7，m＝7，即该叠层结构120可以包括7 层导电层，例如图8中示出的相邻导电层之间通过电介质层电隔离，4个第一导电通孔结构170分别电连接该至少一个第一台阶结构10(4个阶梯的台阶)的台阶面上的所有奇数层导电层，以及3个第二导电通孔结构180分别电连接该至少一个第二台阶结构20(3个阶梯的台阶)的台阶面上的所有偶数层导电层。该刻蚀停止层200覆盖该至少一个第一台阶结构10和该至少一个第二台阶结构20，该多个第一导电通孔结构170和该多个第二导电通孔结构180贯穿该刻蚀停止层200。Optionally, in an embodiment, n=7 and m=7, that is, the laminated structure 120 may include 7 conductive layers, for example, adjacent conductive layers shown in FIG. 8 are electrically isolated by a dielectric layer, The four first conductive via structures 170 are respectively electrically connected to all the odd-numbered conductive layers on the step surface of the at least one first step structure 10 (four stepped steps), and the three second conductive via structures 180 are respectively electrically connected All the even-numbered conductive layers on the step surface of the at least one second step structure 20 (3 stepped steps) are connected. The etch stop layer 200 covers the at least one first step structure 10 and the at least one second step structure 20, and the plurality of first conductive via structures 170 and the plurality of second conductive via structures 180 penetrate the etch Stop layer 200.

可选地，在本申请实施例中，该衬底110由电阻率小于阈值的材料设置，或者，该衬底110的表面设置有重掺杂的电阻率小于阈值的导电层或者重掺杂的导电区域。也即，该衬底110导电，或者，该衬底110中与该叠层结构120接触的区域导电。Optionally, in the embodiment of the present application, the substrate 110 is made of a material with a resistivity less than a threshold, or the surface of the substrate 110 is provided with a heavily doped conductive layer or a heavily doped conductive layer with a resistivity less than the threshold. Conductive area. That is, the substrate 110 is conductive, or the area of the substrate 110 in contact with the laminated structure 120 is conductive.

需要说明的是，电阻率小于阈值的材料即可认为是导电材料。It should be noted that a material with a resistivity less than the threshold value can be regarded as a conductive material.

例如，该衬底110为重掺杂衬底，For example, the substrate 110 is a heavily doped substrate,

又例如，也可以对该衬底110进行掺杂，形成p++型或n++型的低电阻率导电层或导电区域。For another example, the substrate 110 may also be doped to form a p++-type or n++-type low-resistivity conductive layer or conductive region.

再例如，在该衬底110的表面沉积低电阻率导电材料，如用PVD或ALD工艺沉积TiN和/或TaN和/或Pt等金属，或者用CVD工艺，沉积重掺杂多晶硅、金属钨、碳材料。For another example, a low-resistivity conductive material is deposited on the surface of the substrate 110, such as using a PVD or ALD process to deposit TiN and/or TaN and/or Pt and other metals, or using a CVD process to deposit heavily doped polysilicon, metal tungsten, Carbon material.

需要说明的是，该衬底110由电阻率小于阈值的材料形成即可认为该衬底110为重掺杂低电阻率衬底；该衬底110的表面形成有重掺杂的电阻率小于阈值的导电层即可认为该衬底110的表面形成有重掺杂低电阻率导电层；该衬底110的表面形成有重掺杂的电阻率小于阈值的导电区域即可认为该衬底110的表面形成有重掺杂低电阻率导电区域。It should be noted that if the substrate 110 is formed of a material with a resistivity less than the threshold, it can be considered that the substrate 110 is a heavily doped low-resistivity substrate; the surface of the substrate 110 is formed with a heavily doped resistivity less than the threshold. The conductive layer of the substrate 110 can be considered to be a heavily doped low-resistivity conductive layer formed on the surface of the substrate 110; the surface of the substrate 110 is formed with a heavily doped conductive region with a resistivity less than the threshold, which can be considered to be the substrate 110 A heavily doped low-resistivity conductive area is formed on the surface.

可选地，在本申请实施例中，该第二外接电极140还可以电连接至该衬底110。例如，该第二导电材料层160除了覆盖该至少一个第二台阶结构20之外，还覆盖该衬底110，以电连接该至少一个第二台阶结构20的台阶面上的所有偶数层导电层和该衬底110，该第二外接电极140通过该第二导电通孔结构180电连接至该第二导电材料层160，从而实现该第二外接电极140电连接所有偶数层导电层和该衬底110的目的。又例如，该第二外接电极140还可以通过一个连通该衬底110的第二导电通孔结构180电连接至该衬底110。Optionally, in the embodiment of the present application, the second external electrode 140 may also be electrically connected to the substrate 110. For example, in addition to covering the at least one second step structure 20, the second conductive material layer 160 also covers the substrate 110 to electrically connect all the even-numbered conductive layers on the step surface of the at least one second step structure 20 And the substrate 110, the second external electrode 140 is electrically connected to the second conductive material layer 160 through the second conductive via structure 180, so that the second external electrode 140 is electrically connected to all even-numbered conductive layers and the substrate. The purpose of the bottom 110. For another example, the second external electrode 140 may also be electrically connected to the substrate 110 through a second conductive via structure 180 connected to the substrate 110.

可选地，在本申请实施例中，该电容器100还包括至少一层绝缘层210。如图1和图8所示，该至少一层绝缘层210覆盖该叠层结构120，该第一导电通孔结构170和该第二导电通孔结构180贯穿该至少一层绝缘层210。Optionally, in the embodiment of the present application, the capacitor 100 further includes at least one insulating layer 210. As shown in FIGS. 1 and 8, the at least one insulating layer 210 covers the laminated structure 120, and the first conductive via structure 170 and the second conductive via structure 180 penetrate the at least one insulating layer 210.

需要说明的是，该至少一层绝缘层210也可以称之为金属间介质层(IMD)或者层间介质层(ILD)。该第一导电通孔结构170和该第二导电通孔结构180也可以称之为导电通道。It should be noted that the at least one insulating layer 210 may also be referred to as an intermetal dielectric layer (IMD) or an interlayer dielectric layer (ILD). The first conductive via structure 170 and the second conductive via structure 180 may also be referred to as conductive channels.

可选地，该至少一层绝缘层210包覆该叠层结构120，以及该至少一层绝缘层210可以填充该叠层结构120上表面形成的空腔或者空隙，以提升电容器的结构完整性和机械稳定性。Optionally, the at least one insulating layer 210 covers the laminated structure 120, and the at least one insulating layer 210 can fill a cavity or gap formed on the upper surface of the laminated structure 120 to improve the structural integrity of the capacitor And mechanical stability.

可选地，该至少一层绝缘层210的材料和制备工艺可以与上述刻蚀停止层200一致，为了简洁，在此不再赘述。Optionally, the material and preparation process of the at least one insulating layer 210 may be the same as the above-mentioned etch stop layer 200, and for the sake of brevity, it will not be repeated here.

可选地，该第一导电通孔结构170和该第二导电通孔结构180的材料可以由低电阻率导电材料构成，例如重掺杂多晶硅，钨，Ti，TiN，Ta，TaN。Optionally, the material of the first conductive via structure 170 and the second conductive via structure 180 may be made of a low-resistivity conductive material, such as heavily doped polysilicon, tungsten, Ti, TiN, Ta, TaN.

应理解，该第一导电通孔结构170和该第二导电通孔结构180的形状可以根据该电容器100的制作工艺具体确定，本申请实施例对此不作限定。It should be understood that the shapes of the first conductive via structure 170 and the second conductive via structure 180 may be specifically determined according to the manufacturing process of the capacitor 100, which is not limited in the embodiment of the present application.

可选地，在一些实施例中，该至少一个第一外接电极130和该至少一个第二外接电极140设置于该叠层结构120的上方。可选地，该电容器100还包括：电极层，设置于该叠层结构120的上方，该电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，该第一导电区域形成该第一外接电极130，该第二导电区域形成该第二外接电极140，具体如图1和图8所示。也即，该至少一个第一外接电极130和该至少一个第二外接电极140可以通过一次刻蚀形成，减少了刻蚀步骤。具体地，如图1和图8所示，该电极层设置于该至少一层绝缘层210的上方。Optionally, in some embodiments, the at least one first external electrode 130 and the at least one second external electrode 140 are disposed above the laminated structure 120. Optionally, the capacitor 100 further includes: an electrode layer disposed above the laminated structure 120, the electrode layer including at least one first conductive region and at least one second conductive region that are separated from each other, and the first conductive region forms The first external electrode 130 and the second conductive area form the second external electrode 140, as shown in FIGS. 1 and 8 in detail. That is, the at least one first external electrode 130 and the at least one second external electrode 140 can be formed by one etching, which reduces the etching steps. Specifically, as shown in FIGS. 1 and 8, the electrode layer is disposed above the at least one insulating layer 210.

以上描述了本申请实施例的电容器，下面描述本申请实施例的制备电容器的方法。本申请实施例的制备电容器的方法可以制备前述本申请实施例的电容器，下述实施例和前述实施例中的相关描述可以相互参考。The capacitors of the embodiments of the present application are described above, and the method for preparing the capacitors of the embodiments of the present application is described below. The method for preparing a capacitor of the embodiment of the present application can prepare the capacitor of the foregoing embodiment of the present application, and the following embodiment and the related description in the foregoing embodiment can be referred to each other.

以下，结合图9、图10a-10p，详细介绍本申请实施例的电容器的制作方法。Hereinafter, the manufacturing method of the capacitor according to the embodiment of the present application will be described in detail with reference to FIGS. 9 and 10a-10p.

应理解，图9是本申请实施例的电容器的制作方法的示意性流程图，但这些步骤或操作仅是示例，本申请实施例还可以执行其他操作或者图9中的各个操作的变形。It should be understood that FIG. 9 is a schematic flowchart of a method for manufacturing a capacitor in an embodiment of the present application, but these steps or operations are only examples, and the embodiment of the present application may also perform other operations or modifications of each operation in FIG. 9.

图9示出了根据本申请实施例的电容器的制作方法300的示意性流程图。如图9所示，该电容器的制作方法300包括：FIG. 9 shows a schematic flowchart of a method 300 for manufacturing a capacitor according to an embodiment of the present application. As shown in FIG. 9, the manufacturing method 300 of the capacitor includes:

步骤310，在衬底上方制备至少一个叠层结构，该叠层结构包括n层导电层和m层电介质层，该n层导电层和该m层电介质层形成导电层与电介质层彼此相邻的结构，并且该n层导电层中的所有奇数层导电层形成至少一个第一台阶结构，该n层导电层中的所有偶数层导电层形成至少一个第二台阶结构，m、n为正整数；Step 310, prepare at least one laminated structure over the substrate, the laminated structure including an n-layer conductive layer and an m-layer dielectric layer, the n-layer conductive layer and the m-layer dielectric layer form the conductive layer and the dielectric layer adjacent to each other Structure, and all odd-numbered conductive layers in the n-layer conductive layer form at least one first stepped structure, and all even-numbered conductive layers in the n-layer conductive layer form at least one second stepped structure, and m and n are positive integers;

步骤320，制备至少一个第一外接电极和至少一个第二外接电极，其中，该第一外接电极通过该至少一个第一台阶结构的台阶面电连接至该n层导电层中的部分或者全部奇数层导电层，该第二外接电极通过该至少一个第二台阶结构的台阶面电连接至该n层导电层中的部分或者全部偶数层导电层。 Step 320, prepare at least one first external electrode and at least one second external electrode, wherein the first external electrode is electrically connected to a part or all of the odd number of the n-layer conductive layer through the step surface of the at least one first step structure A conductive layer, and the second external electrode is electrically connected to a part or all of the even-numbered conductive layers in the n-layer conductive layer through the step surface of the at least one second stepped structure.

具体地，基于上述步骤310-320可以制备如图1和图8所示的电容器。Specifically, the capacitor as shown in FIG. 1 and FIG. 8 can be prepared based on the above steps 310-320.

应理解，步骤310-320中所述的各材料层的上表面是指该材料层与衬底上表面基本平行的表面。It should be understood that the upper surface of each material layer described in steps 310-320 refers to the surface of the material layer that is substantially parallel to the upper surface of the substrate.

可选地，在一些实施例中，该至少一个第一台阶结构10与该至少一个第二台阶结构20分别位于该叠层结构120的不同侧。Optionally, in some embodiments, the at least one first step structure 10 and the at least one second step structure 20 are respectively located on different sides of the laminated structure 120.

可选地，在一些实施例中，该至少一个第一台阶结构10与该至少一个第二台阶结构20位于该叠层结构120的同一侧。Optionally, in some embodiments, the at least one first step structure 10 and the at least one second step structure 20 are located on the same side of the laminated structure 120.

可选地，该n层导电层中，与该衬底110的距离越小，在该衬底110上的投影面积越大。Optionally, in the n-layer conductive layer, the smaller the distance from the substrate 110, the larger the projected area on the substrate 110.

可选地，在一些实施例中，该第二外接电极140还电连接至该衬底110。也即，该衬底110导电，或者，该衬底110中的一些特定区域导电，从而，该衬底110可以作为该电容器100的一个导电层。Optionally, in some embodiments, the second external electrode 140 is also electrically connected to the substrate 110. That is, the substrate 110 is conductive, or some specific areas in the substrate 110 are conductive, so that the substrate 110 can serve as a conductive layer of the capacitor 100.

可选地，该衬底110由电阻率小于阈值的材料形成，或者，该衬底110的表面形成有重掺杂的导电层或者重掺杂的导电区域。Optionally, the substrate 110 is formed of a material with a resistivity less than a threshold value, or a heavily doped conductive layer or a heavily doped conductive region is formed on the surface of the substrate 110.

可选地，上述步骤310具体可以是：Optionally, the foregoing step 310 may specifically be:

利用光刻胶修整工艺，在该叠层结构120上形成该至少一个第一台阶结构10和该至少一个第二台阶结构20。The at least one first step structure 10 and the at least one second step structure 20 are formed on the laminated structure 120 by using a photoresist trimming process.

可选地，在一些实施例中，该方法300还包括：Optionally, in some embodiments, the method 300 further includes:

制备第一导电材料层150和第二导电材料层160，Preparing the first conductive material layer 150 and the second conductive material layer 160,

其中，该第一导电材料层150通过该至少一个第一台阶结构10的部分或者全部台阶面电连接该n层导电层中的部分或者全部奇数层导电层，该第二导电材料层160通过该至少一个第二台阶结构20的部分或者全部台阶面电连接该n层导电层中的部分或者全部偶数层导电层。Wherein, the first conductive material layer 150 is electrically connected to some or all of the odd-numbered conductive layers in the n-layer conductive layer through part or all of the stepped surfaces of the at least one first stepped structure 10, and the second conductive material layer 160 passes through the Part or all of the step surfaces of the at least one second step structure 20 are electrically connected to some or all of the even-numbered conductive layers in the n-layer conductive layer.

可选地，该方法300还包括：Optionally, the method 300 further includes:

制备第一导电通孔结构170和第二导电通孔结构180，Preparing a first conductive via structure 170 and a second conductive via structure 180,

其中，该第一外接电极130通过该第一导电通孔结构170电连接至该第一导电材料层150，该第二外接电极140通过该第二导电通孔结构180电连接至该第二导电材料层160。Wherein, the first external electrode 130 is electrically connected to the first conductive material layer 150 through the first conductive via structure 170, and the second external electrode 140 is electrically connected to the second conductive material layer through the second conductive via structure 180. Material layer 160.

制备由绝缘材料形成的边墙结构190，其中，该边墙结构190覆盖该至少一个第一台阶结构10的垂直面，用于隔离该第一导电材料层150与该至少一个第一台阶结构10的垂直面，并且该边墙结构190覆盖该至少一个第二台阶结构20的垂直面，用于隔离该第二导电材料层160与该至少一个第二台阶结构20的垂直面。Prepare a sidewall structure 190 formed of an insulating material, wherein the sidewall structure 190 covers the vertical surface of the at least one first step structure 10 and is used to isolate the first conductive material layer 150 from the at least one first step structure 10 The side wall structure 190 covers the vertical surface of the at least one second step structure 20 to isolate the second conductive material layer 160 from the vertical surface of the at least one second step structure 20.

制备多个第一导电通孔结构170和多个第二导电通孔结构180，其中，A plurality of first conductive via structures 170 and a plurality of second conductive via structures 180 are prepared, wherein,

制备刻蚀停止层200，该刻蚀停止层200覆盖该至少一个第一台阶结构10和该至少一个第二台阶结构20，该多个第一导电通孔结构170和该多个第二导电通孔结构180贯穿该刻蚀停止层200。An etch stop layer 200 is prepared, the etch stop layer 200 covers the at least one first step structure 10 and the at least one second step structure 20, the plurality of first conductive via structures 170 and the plurality of second conductive vias The hole structure 180 penetrates the etch stop layer 200.

可选地，该刻蚀停止层200还覆盖该衬底110。Optionally, the etch stop layer 200 also covers the substrate 110.

可选地，上述步骤320具体可以是：Optionally, the foregoing step 320 may specifically be:

在该叠层结构120上方制备电极层，该电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，该第一导电区域形成该第一外接电极130，该第二导电区域形成该第二外接电极140。An electrode layer is prepared above the laminated structure 120. The electrode layer includes at least one first conductive region and at least one second conductive region that are separated from each other. The first conductive region forms the first external electrode 130, and the second conductive region The second external electrode 140 is formed.

可选地，在一些实施例中，该至少一个叠层结构120中不同叠层结构共用同一个该第一外接电极130，和/或，不同叠层结构共用同一个该第二外接电极140。Optionally, in some embodiments, different stacked structures in the at least one stacked structure 120 share the same first external electrode 130, and/or different stacked structures share the same second external electrode 140.

可选地，在一个实施例中，假设m＝7，n＝7，即该叠层结构120包括7层导电层和7层电介质层。在这一实施例中，上述步骤310和步骤320具体可以是如步骤a至步骤l(图10a-10p)所示的制备流程，可以制备如图1所示的电容器100。另外，也可以制备如图8所示的电容器100，其可以参考如步骤a至步骤l(图10a-10p)所示的电容器制备流程，为了简洁，在此不再赘述。Optionally, in an embodiment, it is assumed that m=7 and n=7, that is, the laminated structure 120 includes 7 conductive layers and 7 dielectric layers. In this embodiment, the above-mentioned steps 310 and 320 may specifically be the preparation process shown in step a to step 1 (FIGS. 10a-10p), and the capacitor 100 shown in FIG. 1 may be prepared. In addition, the capacitor 100 as shown in FIG. 8 can also be prepared, which can refer to the capacitor preparation process shown in step a to step 1 (FIGS. 10a-10p). For the sake of brevity, the details are not repeated here.

步骤a，选取衬底110，并在衬底110的上表面沉积7层导电层和7层电介质层的交替叠层，如图10a所示；Step a, select the substrate 110, and deposit an alternating stack of 7 conductive layers and 7 dielectric layers on the upper surface of the substrate 110, as shown in FIG. 10a;

步骤b，利用光刻结合刻蚀工艺，对最外层的导电层进行图形化，在部分区域露出该最外层的导电层的下一层导电层，如图10b所示；Step b, using photolithography combined with an etching process to pattern the outermost conductive layer to expose the next conductive layer of the outermost conductive layer in a part of the area, as shown in FIG. 10b;

步骤c，在如图10b所示的结构表面涂覆一层光刻胶，曝光、显影后得到如10c图所示的光刻胶图案；Step c, coating a layer of photoresist on the surface of the structure as shown in FIG. 10b, and obtaining a photoresist pattern as shown in FIG. 10c after exposure and development;

步骤d，以光刻胶作为掩模，进行干法刻蚀，去除2层导电层和2层电介质层，如图10d所示；Step d, dry etching is performed using photoresist as a mask to remove two conductive layers and two dielectric layers, as shown in FIG. 10d;

步骤e，利用光刻胶修整工艺，横向回退去除部分光刻胶，如图10e所示，接着，干法刻蚀去除2层导电层和2层电介质层，如图10f所示；Step e, using a photoresist trimming process to remove part of the photoresist by lateral retreat, as shown in FIG. 10e, and then dry etching to remove two conductive layers and two dielectric layers, as shown in FIG. 10f;

步骤f，利用光刻胶修整工艺，横向回退去除部分光刻胶，如图10g所示；接着，干法刻蚀去除2层导电层和2层电介质层，露出衬底110和第1层导电层(与衬底110接触的导电层)，如图10h所示；Step f, using a photoresist trimming process to remove part of the photoresist by laterally retracting, as shown in FIG. 10g; then, dry etching removes two conductive layers and two dielectric layers, exposing the substrate 110 and the first layer The conductive layer (the conductive layer in contact with the substrate 110), as shown in FIG. 10h;

步骤g，去除剩余光刻胶，得到第一台阶结构10和第二台阶结构20，第一台阶结构10上露出所有奇数层导电层，以及第二台阶结构20上露出所有偶数层导电层，如图10i所示；In step g, the remaining photoresist is removed to obtain a first step structure 10 and a second step structure 20. All odd-numbered conductive layers are exposed on the first stepped structure 10, and all even-numbered conductive layers are exposed on the second stepped structure 20, such as As shown in Figure 10i;

步骤h，利用CVD或者ALD工艺在如图10i所示的结构表面(包括台阶的垂直面)沉积一层绝缘材料，如图10j所示，该绝缘材料可以是氧化硅、氮化硅、氧化铝中的一种或多种；接着，利用干法刻蚀去除水平表面的绝缘材料，在台阶的垂直面上形成绝缘的边墙(spacer)190，如图10k所示；Step h, using a CVD or ALD process to deposit a layer of insulating material on the surface of the structure (including the vertical surface of the step) as shown in FIG. 10i, as shown in FIG. 10j, the insulating material may be silicon oxide, silicon nitride, or aluminum oxide. One or more of; then, dry etching is used to remove the insulating material on the horizontal surface, and an insulating spacer 190 is formed on the vertical surface of the step, as shown in FIG. 10k;

步骤i，在如图10k所示的结构上沉积一层导电材料，并图形化形成第一导电材料层150和第二导电材料层160，如图10l所示；Step i, depositing a layer of conductive material on the structure shown in FIG. 10k, and patterning the first conductive material layer 150 and the second conductive material layer 160, as shown in FIG. 10l;

步骤j，在如图10l所示的结构上沉积一层绝缘材料并平坦化，形成一层绝缘层210(或者层间介质层(ILD))，如图10m所示；Step j, deposit a layer of insulating material on the structure shown in FIG. 10l and planarize it to form an insulating layer 210 (or an interlayer dielectric layer (ILD)), as shown in FIG. 10m;

步骤k，利用光刻结合刻蚀工艺，在绝缘层210中形成两个通孔，该两个通孔的底部分别露出第一导电材料层150和第二导电材料层160，如图10n所示；Step k, using photolithography combined with an etching process to form two through holes in the insulating layer 210, and the bottoms of the two through holes respectively expose the first conductive material layer 150 and the second conductive material layer 160, as shown in FIG. 10n ；

步骤l，在该两个通孔中填充导电材料，形成第一导电通孔结构170和第二导电通孔结构180，并制备第一外接电极130和第二外接电极140，从而制备如图10o或者图10p所示的电容器。Step 1. Fill the two through holes with conductive material to form a first conductive through hole structure 170 and a second conductive through hole structure 180, and prepare the first external electrode 130 and the second external electrode 140, so as to prepare as shown in FIG. 10o Or the capacitor shown in Figure 10p.

具体地，可以通过如下方式1和方式2，填充导电材料和制作电极。Specifically, the following method 1 and method 2 can be used to fill conductive materials and fabricate electrodes.

方式1，通孔尺寸较大时，可以直接使用PVD工艺，在通孔侧壁和ILD表面形成金属层；最后，利用光刻将ILD表面的金属层图形化，得到一个个独立的电极，如图10o所示。即该第一导电通孔结构170和该第二导电通孔结构180可以与该第一外接电极130和该第二外接电极140具有相同的材料。Method 1, when the size of the through hole is large, you can directly use the PVD process to form a metal layer on the sidewall of the through hole and the surface of the ILD; finally, use photolithography to pattern the metal layer on the surface of the ILD to obtain independent electrodes, such as Shown in Figure 10o. That is, the first conductive via structure 170 and the second conductive via structure 180 may have the same material as the first external electrode 130 and the second external electrode 140.

方式2，通孔尺寸较小时，先用PVD在通孔侧壁沉积一层或多层Ti/TiN/TaN作为黏附层和/或阻挡层，再用CVD方式将孔填满金属钨。然后，使用回刻(etch back)工艺或者表面平坦化工艺，将ILD层表面多余的导电材料去除。最后，利用PVD工艺在ILD表层再次沉积Ti/TiN和金属，光刻图形化得到一个个独立的电极，如图10p所示。即该第一导电通孔结构170和该第二导电通孔结构180可以与该第一外接电极130和该第二外接电极140具有不同的材料。Method 2, when the size of the through hole is small, first use PVD to deposit one or more layers of Ti/TiN/TaN as the adhesion layer and/or barrier layer on the sidewall of the through hole, and then fill the hole with metal tungsten by CVD. Then, an etchback process or a surface planarization process is used to remove the excess conductive material on the surface of the ILD layer. Finally, the PVD process is used to deposit Ti/TiN and metal again on the surface of the ILD, and then patterned by photolithography to obtain individual electrodes, as shown in Figure 10p. That is, the first conductive via structure 170 and the second conductive via structure 180 may have different materials from the first external electrode 130 and the second external electrode 140.

因此，在本申请实施例中，叠层结构形成有至少一个第一台阶结构，以露出n层导电层中的所有奇数层导电层，且叠层结构形成有至少一个第二台阶结构，以露出n层导电层中的所有偶数层导电层，第一外接电极通过至少一个第一台阶结构电连接n层导电层中的部分或者全部奇数层导电层，第二外接电极通过至少一个第二台阶结构的台阶面电连接n层导电层中的部分或者全部偶数层导电层，从而能够制备三维硅电容器，能够在制备小体积、高容值密度的电容器的同时降低电容器成本。Therefore, in the embodiment of the present application, the stacked structure is formed with at least one first step structure to expose all odd-numbered conductive layers in the n-layer conductive layer, and the stacked structure is formed with at least one second step structure to expose All the even-numbered conductive layers in the n-layer conductive layer, the first external electrode is electrically connected to part or all of the odd-numbered conductive layers in the n-layer conductive layer through at least one first step structure, and the second external electrode is through at least one second step structure The step surface is electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer, so that a three-dimensional silicon capacitor can be prepared, which can reduce the cost of the capacitor while preparing a capacitor with a small volume and a high capacitance value density.

本领域普通技术人员可以意识到，以上结合附图详细描述了本申请的优选实施方式，但是，本申请并不限于上述实施方式中的具体细节，在本申请的技术构思范围内，可以对本申请的技术方案进行多种简单变型，这些简单变型均属于本申请的保护范围。Those of ordinary skill in the art can realize that the preferred embodiments of the application are described in detail above with reference to the accompanying drawings. However, the application is not limited to the specific details in the foregoing embodiments. Within the scope of the technical concept of the application, the application can be The technical solution of ”is subject to a variety of simple modifications, and these simple modifications all fall within the protection scope of this application.

另外需要说明的是，在上述具体实施方式中所描述的各个具体技术特征，在不矛盾的情况下，可以通过任何合适的方式进行组合，为了避免不必要的重复，本申请对各种可能的组合方式不再另行说明。In addition, it should be noted that the various specific technical features described in the above-mentioned specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this application provides various possible combinations. The combination method will not be explained separately.

此外，本申请的各种不同的实施方式之间也可以进行任意组合，只要其不违背本申请的思想，其同样应当视为本申请所申请的内容。In addition, various different implementations of this application can also be combined arbitrarily, as long as they do not violate the idea of this application, they should also be regarded as the content applied for in this application.

Claims

一种电容器，其特征在于，所述电容器包括：A capacitor, characterized in that, the capacitor comprises:

至少一个叠层结构，所述叠层结构包括n层导电层和m层电介质层，所述n层导电层和所述m层电介质层形成导电层与电介质层彼此相邻的结构，并且所述n层导电层中的所有奇数层导电层形成至少一个第一台阶结构，所述n层导电层中的所有偶数层导电层形成至少一个第二台阶结构，m、n为正整数；At least one laminated structure, the laminated structure includes an n-layer conductive layer and an m-layer dielectric layer, the n-layer conductive layer and the m-layer dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other, and the All odd-numbered conductive layers in the n-layer conductive layer form at least one first step structure, and all even-numbered conductive layers in the n-layer conductive layer form at least one second step structure, and m and n are positive integers;

至少一个第一外接电极，所述第一外接电极通过所述至少一个第一台阶结构的台阶面电连接至所述n层导电层中的部分或者全部奇数层导电层；At least one first external electrode, the first external electrode is electrically connected to a part or all of the odd-numbered conductive layers in the n-layer conductive layer through the step surface of the at least one first stepped structure;

至少一个第二外接电极，所述第二外接电极通过所述至少一个第二台阶结构的台阶面电连接至所述n层导电层中的部分或者全部偶数层导电层。At least one second external electrode, and the second external electrode is electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer through the step surface of the at least one second stepped structure.
根据权利要求1所述的电容器，其特征在于，所述至少一个第一台阶结构与所述至少一个第二台阶结构分别位于所述叠层结构的不同侧。The capacitor according to claim 1, wherein the at least one first step structure and the at least one second step structure are respectively located on different sides of the laminated structure.
根据权利要求1所述的电容器，其特征在于，所述至少一个第一台阶结构与所述至少一个第二台阶结构位于所述叠层结构的同一侧。The capacitor according to claim 1, wherein the at least one first step structure and the at least one second step structure are located on the same side of the laminated structure.
根据权利要求1至3中任一项所述的电容器，其特征在于，所述电容器还包括衬底，所述至少一个叠层结构设置于所述衬底的上方。The capacitor according to any one of claims 1 to 3, wherein the capacitor further comprises a substrate, and the at least one laminated structure is disposed above the substrate.
根据权利要求4所述的电容器，其特征在于，所述n层导电层中，与所述衬底的距离越小，在所述衬底上的投影面积越大。The capacitor according to claim 4, wherein in the n-layer conductive layer, the smaller the distance from the substrate, the larger the projected area on the substrate.
根据权利要求1至5中任一项所述的电容器，其特征在于，所述电容器还包括：第一导电材料层和第二导电材料层，The capacitor according to any one of claims 1 to 5, wherein the capacitor further comprises: a first conductive material layer and a second conductive material layer,

其中，所述第一导电材料层通过所述至少一个第一台阶结构的部分或者全部台阶面电连接所述n层导电层中的部分或者全部奇数层导电层，所述第二导电材料层通过所述至少一个第二台阶结构的部分或者全部台阶面电连接所述n层导电层中的部分或者全部偶数层导电层。Wherein, the first conductive material layer is electrically connected to part or all of the odd-numbered conductive layers in the n-layer conductive layer through part or all of the stepped surfaces of the at least one first stepped structure, and the second conductive material layer passes through Part or all of the step surfaces of the at least one second step structure are electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer.
根据权利要求6所述的电容器，其特征在于，所述第一导电材料层覆盖所述至少一个第一台阶结构的部分或者全部台阶面，以电连接所述n层导电层中的部分或者全部奇数层导电层，以及所述第二导电材料层覆盖所述至少一个第二台阶结构的部分或者全部台阶面，以电连接所述n层导电层中的部分或者全部偶数层导电层。The capacitor according to claim 6, wherein the first conductive material layer covers part or all of the step surface of the at least one first step structure to electrically connect part or all of the n-layer conductive layer The odd-numbered conductive layers and the second conductive material layer cover part or all of the stepped surfaces of the at least one second stepped structure to electrically connect part or all of the even-numbered conductive layers in the n-layered conductive layer.
根据权利要求6或7所述的电容器，其特征在于，所述电容器还包括：第一导电通孔结构和第二导电通孔结构，The capacitor according to claim 6 or 7, wherein the capacitor further comprises: a first conductive via structure and a second conductive via structure,

其中，所述第一外接电极通过所述第一导电通孔结构电连接至所述第一导电材料层，所述第二外接电极通过所述第二导电通孔结构电连接至所述第二导电材料层。Wherein, the first external electrode is electrically connected to the first conductive material layer through the first conductive via structure, and the second external electrode is electrically connected to the second conductive material layer through the second conductive via structure. Conductive material layer.
根据权利要求6至8中任一项所述的电容器，其特征在于，所述电容器还包括由绝缘材料形成的边墙结构，其中，所述边墙结构覆盖所述至少一个第一台阶结构的垂直面，用于隔离所述第一导电材料层与所述至少一个第一台阶结构的垂直面，并且所述边墙结构覆盖所述至少一个第二台阶结构的垂直面，用于隔离所述第二导电材料层与所述至少一个第二台阶结构的垂直面。The capacitor according to any one of claims 6 to 8, wherein the capacitor further comprises a side wall structure formed of an insulating material, wherein the side wall structure covers the at least one first step structure The vertical surface is used to isolate the first conductive material layer from the vertical surface of the at least one first stepped structure, and the side wall structure covers the vertical surface of the at least one second stepped structure and is used to isolate the vertical surface of the at least one second stepped structure. A vertical surface of the second conductive material layer and the at least one second step structure.
根据权利要求1至5中任一项所述的电容器，其特征在于，所述电容器还包括：多个第一导电通孔结构和多个第二导电通孔结构，其中，The capacitor according to any one of claims 1 to 5, wherein the capacitor further comprises: a plurality of first conductive via structures and a plurality of second conductive via structures, wherein,

所述第一外接电极电连接所述多个第一导电通孔结构，且所述多个第一导电通孔结构通过所述至少一个第一台阶结构的部分或者全部台阶面电连接至所述n层导电层中的部分或者全部奇数层导电层；The first external electrode is electrically connected to the plurality of first conductive via structures, and the plurality of first conductive via structures are electrically connected to the at least one first stepped structure through a part or all of the stepped surfaces Part or all of the odd-numbered conductive layers in the n-layered conductive layer;

所述第二外接电极电连接所述多个第二导电通孔结构，且所述多个第二导电通孔结构通过所述至少一个第二台阶结构的部分或者全部台阶面电连接至所述n层导电层中的部分或者全部偶数层导电层。The second external electrode is electrically connected to the plurality of second conductive via structures, and the plurality of second conductive via structures are electrically connected to the step surface of the at least one second stepped structure. Part or all of the even-numbered conductive layers in the n-layer conductive layer.
根据权利要求10所述的电容器，其特征在于，所述电容器还包括：刻蚀停止层，所述刻蚀停止层覆盖所述至少一个第一台阶结构和所述至少一个第二台阶结构，所述多个第一导电通孔结构和所述多个第二导电通孔结构贯穿所述刻蚀停止层。The capacitor according to claim 10, wherein the capacitor further comprises: an etch stop layer, the etch stop layer covering the at least one first step structure and the at least one second step structure, so The plurality of first conductive via structures and the plurality of second conductive via structures penetrate the etch stop layer.
根据权利要求11所述的电容器，其特征在于，所述电容器还包括衬底，所述至少一个叠层结构设置于所述衬底的上方，并且所述刻蚀停止层还覆盖所述衬底。The capacitor according to claim 11, wherein the capacitor further comprises a substrate, the at least one stacked structure is disposed above the substrate, and the etch stop layer also covers the substrate .
根据权利要求1至12中任一项所述的电容器，其特征在于，所述n层导电层中的导电层的厚度范围为5nm～1mm。The capacitor according to any one of claims 1 to 12, wherein the thickness of the conductive layer in the n-layer conductive layer is in the range of 5 nm to 1 mm.
根据权利要求1至13中任一项所述的电容器，其特征在于，所述m层电介质层中的电介质层的厚度范围为1nm～10um。The capacitor according to any one of claims 1 to 13, wherein the thickness of the dielectric layer in the m-layer dielectric layer is in the range of 1 nm to 10 um.
根据权利要求1至14中任一项所述的电容器，其特征在于，所述n层导电层中的导电层的厚度大于所述m层电介质层中的电介质层的厚度。The capacitor according to any one of claims 1 to 14, wherein the thickness of the conductive layer in the n-layer conductive layer is greater than the thickness of the dielectric layer in the m-layer dielectric layer.
根据权利要求1至15中任一项所述的电容器，其特征在于，所述电容器还包括衬底，所述至少一个叠层结构设置于所述衬底的上方，并且所述第二外接电极还电连接至所述衬底。The capacitor according to any one of claims 1 to 15, wherein the capacitor further comprises a substrate, the at least one laminated structure is disposed above the substrate, and the second external electrode It is also electrically connected to the substrate.
根据权利要求16所述的电容器，其特征在于，所述衬底由电阻率小于阈值的材料形成，或者，所述衬底的表面形成有重掺杂的导电层或者重掺杂的导电区域。The capacitor according to claim 16, wherein the substrate is formed of a material with a resistivity less than a threshold value, or a heavily doped conductive layer or a heavily doped conductive region is formed on the surface of the substrate.
根据权利要求1至17中任一项所述的电容器，其特征在于，所述电容器还包括：电极层，设置于所述叠层结构的上方，所述电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，所述第一导电区域形成所述第一外接电极，所述第二导电区域形成所述第二外接电极。The capacitor according to any one of claims 1 to 17, wherein the capacitor further comprises: an electrode layer disposed above the laminated structure, and the electrode layer includes at least one first layer separated from each other. A conductive region and at least one second conductive region, the first conductive region forms the first external electrode, and the second conductive region forms the second external electrode.
根据权利要求1至18中任一项所述的电容器，其特征在于，所述至少一个叠层结构中不同叠层结构共用同一个所述第一外接电极，和/或，不同叠层结构共用同一个所述第二外接电极。The capacitor according to any one of claims 1 to 18, wherein different stacked structures in the at least one stacked structure share the same first external electrode, and/or, different stacked structures share the same first external electrode The same second external electrode.
根据权利要求1至19中任一项所述的电容器，其特征在于，所述n层导电层中的导电层包括以下中的至少一层：The capacitor according to any one of claims 1 to 19, wherein the conductive layer in the n-layer conductive layer includes at least one of the following:

重掺杂多晶硅层，碳层，铝层，铜层，钨层，钛层，钽层，铂层，镍层，钌层，铱层，铑层，氮化钽层，氮化钛层，氮化钌层。Heavily doped polysilicon layer, carbon layer, aluminum layer, copper layer, tungsten layer, titanium layer, tantalum layer, platinum layer, nickel layer, ruthenium layer, iridium layer, rhodium layer, tantalum nitride layer, titanium nitride layer, nitrogen Ruthenium layer.
根据权利要求1至20中任一项所述的电容器，其特征在于，所述m层电介质层中的电介质层包括以下中的至少一层：The capacitor according to any one of claims 1 to 20, wherein the dielectric layer in the m-layer dielectric layer includes at least one of the following:

硅的氧化物层，硅的氮化物层，硅的氮氧化物层，金属的氧化物层，金属的氮化物层，金属的氮氧化物层。Silicon oxide layer, silicon nitride layer, silicon oxynitride layer, metal oxide layer, metal nitride layer, metal oxynitride layer.
一种电容器的制作方法，其特征在于，包括：A method for manufacturing a capacitor, which is characterized in that it comprises:

在衬底上方制备至少一个叠层结构，所述叠层结构包括n层导电层和m层电介质层，所述n层导电层和所述m层电介质层形成导电层与电介质层彼此相邻的结构，并且所述n层导电层中的所有奇数层导电层形成至少一个第一台阶结构，所述n层导电层中的所有偶数层导电层形成至少一个第二台阶结构，m、n为正整数；At least one laminated structure is prepared over the substrate, the laminated structure includes an n-layer conductive layer and an m-layer dielectric layer, and the n-layer conductive layer and the m-layer dielectric layer form the conductive layer and the dielectric layer adjacent to each other Structure, and all odd-numbered conductive layers in the n-layer conductive layer form at least one first stepped structure, and all even-numbered conductive layers in the n-layer conductive layer form at least one second stepped structure, and m and n are positive Integer

制备至少一个第一外接电极和至少一个第二外接电极，其中，所述第一外接电极通过所述至少一个第一台阶结构的台阶面电连接至所述n层导电层中的部分或者全部奇数层导电层，所述第二外接电极通过所述至少一个第二台阶结构的台阶面电连接至所述n层导电层中的部分或者全部偶数层导电层。At least one first external electrode and at least one second external electrode are prepared, wherein the first external electrode is electrically connected to a part or all of the odd numbers in the n-layer conductive layer through the step surface of the at least one first step structure A conductive layer, and the second external electrode is electrically connected to some or all of the even-numbered conductive layers in the n-layer conductive layer through the step surface of the at least one second stepped structure.
根据权利要求22所述的方法，其特征在于，所述在衬底上方制备至少一个叠层结构，包括：The method according to claim 22, wherein the preparing at least one laminated structure over the substrate comprises:

利用光刻胶修整工艺，在所述叠层结构上形成所述至少一个第一台阶结构和所述至少一个第二台阶结构。Using a photoresist trimming process, the at least one first step structure and the at least one second step structure are formed on the stacked structure.
根据权利要求22或23所述的方法，其特征在于，所述至少一个第一台阶结构与所述至少一个第二台阶结构分别位于所述叠层结构的不同侧。The method according to claim 22 or 23, wherein the at least one first step structure and the at least one second step structure are respectively located on different sides of the laminated structure.
根据权利要求22或23所述的方法，其特征在于，所述至少一个第一台阶结构与所述至少一个第二台阶结构位于所述叠层结构的同一侧。The method according to claim 22 or 23, wherein the at least one first step structure and the at least one second step structure are located on the same side of the laminated structure.
根据权利要求22至25中任一项所述的方法，其特征在于，所述n层导电层中，与所述衬底的距离越小，在所述衬底上的投影面积越大。The method according to any one of claims 22 to 25, wherein in the n-layer conductive layer, the smaller the distance from the substrate, the larger the projected area on the substrate.
根据权利要求22至26中任一项所述的方法，其特征在于，所述方法还包括：The method according to any one of claims 22 to 26, wherein the method further comprises:

制备第一导电材料层和第二导电材料层，Preparing the first conductive material layer and the second conductive material layer,

其中，所述第一导电材料层通过所述至少一个第一台阶结构的部分或者全部台阶面电连接所述n层导电层中的部分或者全部奇数层导电层，所述第二导电材料层通过所述至少一个第二台阶结构的部分或者全部台阶面电连接所述n层导电层中的部分或者全部偶数层导电层。Wherein, the first conductive material layer is electrically connected to part or all of the odd-numbered conductive layers in the n-layer conductive layer through part or all of the stepped surfaces of the at least one first stepped structure, and the second conductive material layer passes through Part or all of the step surfaces of the at least one second step structure are electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer.
根据权利要求27所述的方法，其特征在于，所述第一导电材料层覆盖所述至少一个第一台阶结构的部分或者全部台阶面，以电连接所述n层导电层中的部分或者全部奇数层导电层，以及所述第二导电材料层覆盖所述至少一个第二台阶结构的部分或者全部台阶面，以电连接所述n层导电层中的部分或者全部偶数层导电层。The method according to claim 27, wherein the first conductive material layer covers part or all of the step surface of the at least one first stepped structure to electrically connect part or all of the n-layer conductive layer The odd-numbered conductive layers and the second conductive material layer cover part or all of the stepped surfaces of the at least one second stepped structure to electrically connect part or all of the even-numbered conductive layers in the n-layered conductive layer.
根据权利要求27或28所述的方法，其特征在于，所述方法还包括：The method according to claim 27 or 28, wherein the method further comprises:

制备第一导电通孔结构和第二导电通孔结构，Preparing a first conductive via structure and a second conductive via structure,

其中，所述第一外接电极通过所述第一导电通孔结构电连接至所述第一导电材料层，所述第二外接电极通过所述第二导电通孔结构电连接至所述第二导电材料层。Wherein, the first external electrode is electrically connected to the first conductive material layer through the first conductive via structure, and the second external electrode is electrically connected to the second conductive material layer through the second conductive via structure. Conductive material layer.
根据权利要求27至29中任一项所述的方法，其特征在于，所述方法还包括：The method according to any one of claims 27 to 29, wherein the method further comprises:

制备由绝缘材料形成的边墙结构，其中，所述边墙结构覆盖所述至少一个第一台阶结构的垂直面，用于隔离所述第一导电材料层与所述至少一个第一台阶结构的垂直面，并且所述边墙结构覆盖所述至少一个第二台阶结构的垂直面，用于隔离所述第二导电材料层与所述至少一个第二台阶结构的垂直面。Prepare a sidewall structure formed of an insulating material, wherein the sidewall structure covers the vertical surface of the at least one first step structure and is used to isolate the first conductive material layer from the at least one first step structure The vertical surface, and the side wall structure covers the vertical surface of the at least one second step structure, and is used to isolate the second conductive material layer from the vertical surface of the at least one second step structure.
根据权利要求22至26中任一项所述的方法，其特征在于，所述方法还包括：The method according to any one of claims 22 to 26, wherein the method further comprises:

制备多个第一导电通孔结构和多个第二导电通孔结构，其中，A plurality of first conductive via structures and a plurality of second conductive via structures are prepared, wherein,

所述第一外接电极电连接所述多个第一导电通孔结构，且所述多个第一导电通孔结构通过所述至少一个第一台阶结构的部分或者全部台阶面电连接至所述n层导电层中的部分或者全部奇数层导电层；The first external electrode is electrically connected to the plurality of first conductive via structures, and the plurality of first conductive via structures are electrically connected to the at least one first stepped structure through a part or all of the stepped surfaces Part or all of the odd-numbered conductive layers in the n-layered conductive layer;

所述第二外接电极电连接所述多个第二导电通孔结构，且所述多个第二导电通孔结构通过所述至少一个第二台阶结构的部分或者全部台阶面电连接至所述n层导电层中的部分或者全部偶数层导电层。The second external electrode is electrically connected to the plurality of second conductive via structures, and the plurality of second conductive via structures are electrically connected to the step surface of the at least one second stepped structure. Part or all of the even-numbered conductive layers in the n-layer conductive layer.
根据权利要求31所述的方法，其特征在于，所述方法还包括：The method according to claim 31, wherein the method further comprises:

制备刻蚀停止层，所述刻蚀停止层覆盖所述至少一个第一台阶结构和所述至少一个第二台阶结构，所述多个第一导电通孔结构和所述多个第二导电通孔结构贯穿所述刻蚀停止层。An etch stop layer is prepared, the etch stop layer covers the at least one first step structure and the at least one second step structure, the plurality of first conductive via structures and the plurality of second conductive vias The hole structure penetrates the etch stop layer.
根据权利要求32所述的方法，其特征在于，所述刻蚀停止层还覆盖所述衬底。The method of claim 32, wherein the etch stop layer also covers the substrate.
根据权利要求22至33中任一项所述的方法，其特征在于，所述n层导电层中的导电层的厚度范围为5nm～1mm。The method according to any one of claims 22 to 33, wherein the thickness of the conductive layer in the n-layer conductive layer is in the range of 5 nm to 1 mm.
根据权利要求22至34中任一项所述的方法，其特征在于，所述m层电介质层中的电介质层的厚度范围为1nm～10um。The method according to any one of claims 22 to 34, wherein the thickness of the dielectric layer in the m-layer dielectric layer ranges from 1 nm to 10 um.
根据权利要求22至35中任一项所述的方法，其特征在于，所述n层导电层中的导电层的厚度大于所述m层电介质层中的电介质层的厚度。The method according to any one of claims 22 to 35, wherein the thickness of the conductive layer in the n-layer conductive layer is greater than the thickness of the dielectric layer in the m-layer dielectric layer.
根据权利要求22至36中任一项所述的方法，其特征在于，所述第二外接电极还电连接至所述衬底。The method according to any one of claims 22 to 36, wherein the second external electrode is also electrically connected to the substrate.
根据权利要求37所述的方法，其特征在于，所述衬底由电阻率小于阈值的材料形成，或者，所述衬底的表面形成有重掺杂的导电层或者重掺杂的导电区域。The method according to claim 37, wherein the substrate is formed of a material with a resistivity less than a threshold, or a heavily doped conductive layer or a heavily doped conductive region is formed on the surface of the substrate.
根据权利要求22至38中任一项所述的方法，其特征在于，所述制备至少一个第一外接电极和至少一个第二外接电极，包括：The method according to any one of claims 22 to 38, wherein the preparing at least one first external electrode and at least one second external electrode comprises:

在所述叠层结构上方制备电极层，所述电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，所述第一导电区域形成所述第一外接电极，所述第二导电区域形成所述第二外接电极。An electrode layer is prepared above the laminated structure. The electrode layer includes at least one first conductive region and at least one second conductive region that are separated from each other. The first conductive region forms the first external electrode, and the first conductive region forms the first external electrode. Two conductive regions form the second external electrode.
根据权利要求22至39中任一项所述的方法，其特征在于，所述至少一个叠层结构中不同叠层结构共用同一个所述第一外接电极，和/或，不同叠层结构共用同一个所述第二外接电极。The method according to any one of claims 22 to 39, wherein different stacked structures in the at least one stacked structure share the same first external electrode, and/or, different stacked structures share the same first external electrode The same second external electrode.