WO2021136221A1 - GaN功率器件的保护电路 - Google Patents

GaN功率器件的保护电路 Download PDF

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Publication number
WO2021136221A1
WO2021136221A1 PCT/CN2020/140519 CN2020140519W WO2021136221A1 WO 2021136221 A1 WO2021136221 A1 WO 2021136221A1 CN 2020140519 W CN2020140519 W CN 2020140519W WO 2021136221 A1 WO2021136221 A1 WO 2021136221A1
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WIPO (PCT)
Prior art keywords
gate
voltage
power device
subunit
gan power
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PCT/CN2020/140519
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English (en)
French (fr)
Inventor
雷文平
张静静
俞利光
高衡
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三维通信股份有限公司
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Publication of WO2021136221A1 publication Critical patent/WO2021136221A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement

Definitions

  • This application relates to the field of communication technology, and in particular to a protection circuit for GaN power devices.
  • LDMOS Laterally-Diffused Metal-Oxide Semiconductor
  • GaN power devices are affected by their characteristics, and their gate voltage and drain voltage power-on and power-off sequences are extremely demanding, otherwise the GaN power device will be burned out and cannot work.
  • the application of GaN power devices is not mature enough, especially the timing protection circuit of GaN power devices still has not formed effective protection.
  • the protection circuit of the GaN power device in the related art provides protection for the GaN power device when the power supply is stable; however, the protection circuit of the GaN power device has an unstable power supply or the protection circuit of the GaN power device is powered down. If the gate voltage of the GaN power device drops to zero before the drain voltage, the GaN power device will be burned out.
  • a protection circuit for a GaN power device includes a negative voltage generating unit, a gate voltage switching unit, and a drain voltage switching unit;
  • the unit, the gate voltage switching unit, and the drain voltage switching unit are respectively connected to the first power supply of the protection circuit of the GaN power device;
  • the negative voltage generating unit includes a negative voltage conversion subunit and a negative voltage comparison A subunit, the negative voltage conversion subunit is used to convert the first power supply into a gate protection voltage, and provide the gate protection voltage to the gate voltage switching unit;
  • the negative voltage comparator The unit is used to output a drain voltage turn-off signal when the amplitude of the gate protection voltage is lower than the preset amplitude;
  • the drain voltage switching unit includes a push-pull circuit sub-unit, wherein the push-pull circuit The pull circuit subunit is respectively connected to the output terminal, the common terminal of the negative voltage comparison subunit, the drain of the GaN power device, and the second power supply of the drain of
  • the drain voltage switching unit further includes: a logic gate subunit connected to one of the output terminal of the negative voltage comparison subunit and the input terminal of the push-pull circuit subunit
  • the logic gate subunit is used to generate a first control signal according to the drain voltage turn-off signal, and the first control signal is used to control the push-pull circuit subunit to connect the drain of the GaN power device with The common terminal is turned on.
  • the push-pull circuit sub-unit is further used to reduce the drain of the GaN power device according to a second control signal when the amplitude of the gate protection voltage is higher than a preset amplitude. Power-on or power-off; the logic gate subunit is also used to generate the second control signal according to the enable signal when the amplitude of the gate protection voltage is higher than the preset amplitude, and the second control signal
  • the two control signals are used to control the push-pull circuit subunit to power up or power down the drain of the GaN power device.
  • the logic gate subunit includes a first switch tube, a second switch tube, a logic AND gate, a logic NOT gate, a first resistor, a second resistor, and a third resistor, wherein the first switch The input terminal of the tube, the first input terminal of the logic AND gate and the input terminal of the logic NOT gate are all connected to the first power supply through the first resistor; the input terminal of the second switch tube passes through The second resistor is connected to the first power supply, the input terminal of the second switch tube is also connected to the first input terminal of the push-pull circuit subunit; the control terminal of the first switch tube passes through the The third resistor is connected to the negative voltage comparison subunit; the output terminal of the first switch tube and the output terminal of the second switch tube are both connected to the common terminal; the output terminal of the logic NOT gate is connected to the common terminal.
  • the second input terminal of the push-pull circuit subunit; the second input terminal of the logic AND gate is used to receive the enable signal, and the output terminal of the logic AND gate is connected
  • the push-pull circuit subunit includes a fourth resistor, a fifth resistor, a sixth resistor, and two third and fourth switching tubes with opposite polarities, wherein the third The input terminal of the switch tube is connected to the second power supply, the control terminal of the third switch tube is connected to the first input terminal of the push-pull circuit subunit; the fourth resistor is connected to the third switch Between the control terminal of the tube and the second power supply; the fifth resistor is connected between the second input terminal of the push-pull circuit subunit and the control terminal of the fourth switch tube; the third The output terminal of the switching tube and the input terminal of the fourth switching tube are both connected to the drain of the GaN power device; the output terminal of the fourth switching tube is connected to the common terminal through the sixth resistor, and the first The substrate of the four-switch tube is connected to the common terminal.
  • the gate voltage switching unit is powered by the first power supply and the gate protection voltage dual power supply;
  • the gate voltage switching unit includes a gate driving voltage input terminal, a gate protection A voltage input terminal, an enable signal input terminal, and a gate voltage output terminal;
  • the gate drive voltage input terminal is connected to the output terminal of the gate drive unit, and the gate protection voltage input terminal is connected to the negative voltage conversion subunit Output terminal,
  • the enable signal input terminal is used to receive an enable signal
  • the gate voltage output terminal is connected to the gate of the GaN power device;
  • the gate voltage switching unit is used to switch The gate driving voltage generated by the gate driving unit or the gate protection voltage generated by the negative voltage conversion subunit is provided to the gate of the GaN power device.
  • the protection circuit of the GaN power device further includes: a gate driving unit for generating a gate driving voltage of the GaN power device.
  • the gate driving unit includes a gate driving sub-unit and an adder sub-unit, and the adder sub-unit is powered by the first power supply and the gate protection voltage dual power supply; wherein , The gate driving sub-unit is used to generate a gate control voltage; the adder sub-unit is used to accumulate the gate protection voltage output by the negative voltage conversion sub-unit and the gate control voltage to obtain the Gate drive voltage.
  • the adder subunit includes: a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and an operational amplifier, wherein the output terminal of the operational amplifier is connected to the gate voltage Switching unit, the output terminal of the operational amplifier is also connected to the common terminal through the tenth resistor and the ninth resistor; the inverting input terminal of the operational amplifier is connected to the tenth resistor and the ninth resistor
  • the connection node of the operational amplifier the positive-phase input terminal of the operational amplifier is connected to the gate drive subunit through the seventh resistor, and is connected to the output terminal of the negative voltage conversion subunit through the eighth resistor;
  • the positive power terminal of the operational amplifier is connected to the first power supply, and the negative power terminal of the operational amplifier is connected to the output terminal of the negative voltage conversion subunit.
  • the GaN power device includes: an enhancement mode GaN high electron mobility transistor or a depletion mode GaN high electron mobility transistor.
  • the negative pressure generating unit includes: LTC 1261 series chips from Arnold Semiconductor.
  • the protection circuit of the GaN power device includes a negative voltage generating unit, a gate voltage switching unit, and a drain voltage switching unit; the negative voltage generating unit, the gate voltage switching unit, and the drain voltage switching unit are respectively connected with the first part of the protection circuit of the GaN power device.
  • the negative voltage generation unit includes a negative voltage conversion sub-unit and a negative voltage comparison sub-unit, the negative voltage conversion sub-unit is used to convert the first power supply into a gate protection voltage and provide the gate protection voltage to the gate Polar voltage switching unit; the negative voltage comparison subunit is used to output a drain voltage turn-off signal when the amplitude of the gate protection voltage is lower than the preset amplitude;
  • the drain voltage switching unit includes: a push-pull circuit subunit, Among them, the push-pull circuit subunit is respectively connected to the output terminal, the common terminal, the drain of the GaN power device and the second power supply of the drain of the GaN power device of the negative voltage comparison subunit, and the push-pull circuit subunit is used according to the drain The extreme voltage turn-off signal connects the drain and the common terminal of the GaN power device.
  • the protection circuit of the GaN power device provided by the present application solves the problem that the GaN power device is easily burned out due to the power failure of the protection circuit of the GaN power device in the related art, and avoids the GaN power device caused by the power failure of the protection circuit of the GaN power device Damage.
  • FIG. 1 is a structural block diagram of a protection circuit of a GaN power device according to an embodiment of the present application.
  • Fig. 2 is a block diagram 1 of a preferred structure of a protection circuit for a GaN power device according to an embodiment of the present application.
  • FIG. 3 is a preferred circuit topology diagram of a logic gate subunit 22 according to an embodiment of the present application.
  • FIG. 4 is a preferred circuit topology diagram of a push-pull circuit subunit 21 according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a gate voltage switching unit 30 according to an embodiment of the present application.
  • FIG. 6 is a second preferred structural block diagram of a protection circuit of a GaN power device according to an embodiment of the present application.
  • FIG. 7 is a third block diagram of a preferred structure of a protection circuit of a GaN power device according to an embodiment of the present application.
  • FIG. 8 is a circuit topology diagram of an adder subunit 52 according to an embodiment of the present application.
  • FIG. 9 is a circuit topology diagram of a protection circuit of a GaN power device according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of the change curve of the GaN gate voltage and the drain voltage when the protection circuit of the GaN power device of the embodiment of the present application is powered off.
  • a protection circuit for the GaN power device 40 is provided.
  • 1 is a structural block diagram of a protection circuit of a GaN power device 40 according to an embodiment of the present application.
  • the protection circuit of the GaN power device 40 includes: a negative voltage generating unit 10, a gate voltage switching unit 30, and a drain voltage switching unit 20
  • the negative voltage generating unit 10, the gate voltage switching unit 30, and the drain voltage switching unit 20 are respectively connected to the first power supply of the protection circuit of the GaN power device 40;
  • the negative voltage generating unit 10 includes a negative voltage conversion subunit 12 and a negative
  • the voltage comparison subunit 11, the negative voltage conversion subunit 12 is connected to the negative voltage comparison subunit 11, and the negative voltage conversion subunit 12 is used to convert the power supply into a gate protection voltage and provide the gate protection voltage to the gate voltage Switching unit 30;
  • Negative voltage comparison sub-unit 11 for outputting a drain voltage turn-off signal when the amplitude of the gate protection voltage is lower than the preset amplitude;
  • the push-pull circuit subunit 21 is respectively connected to the output terminal, the common terminal of the negative voltage comparison subunit 11, the drain of the GaN power device 40 and the second power supply of the drain of the GaN power device 40, and the push-pull circuit The subunit 21 is used for connecting the drain of the GaN power device 40 with the common terminal according to the drain voltage turn-off signal.
  • the push-pull circuit subunit 21 is connected to the output terminal, the common terminal of the negative voltage comparison subunit 11, the drain of the GaN power device 40, and the power supply of the drain of the GaN power device 40, respectively, and
  • the negative voltage comparison subunit 11 detects that the amplitude of the gate protection voltage is lower than the preset amplitude, it outputs a drain voltage turn-off signal, and then the push-pull circuit subunit 21 turns the GaN off according to the drain voltage turn-off signal.
  • the drain of the power device 40 is connected to the common terminal, so that when the protection circuit of the GaN power device 40 is powered off, the drain of the GaN power device 40 is connected to the common terminal, so that the drain discharges quickly, thereby ensuring that the GaN power device 40 is discharged quickly.
  • the drain voltage of the power device 40 drops to zero before the gate voltage, which protects the GaN power device 40 from being burnt out.
  • the voltage level of the first power supply of the protection circuit of the GaN power device 40 is determined according to the requirements of the circuit design, and may generally be 5V to 5.8V.
  • the negative pressure generating unit 10 may be, but not limited to, the LTC 1261 series of chips from Arnold Semiconductor.
  • it can be LTC 1261CS8.
  • the OUT pin of the aforementioned chip is the output terminal of the negative voltage conversion sub-unit 12
  • the REG pin is the output terminal of the negative voltage comparison sub-unit 11.
  • the REG pin can output a high level when the amplitude of the negative voltage output by the negative voltage conversion subunit 12 is less than the preset amplitude (that is, the drain voltage of the above embodiment is turned off).
  • the use of the above-mentioned chip in this embodiment can provide reliable timing for the power-on and power-off of the GaN power device 40, and ensure that the GaN power device 40 is not burnt out.
  • the drain The pole voltage switching unit 20 in order to convert the drain voltage turn-off signal into a control signal of the push-pull circuit subunit 21, the drain The pole voltage switching unit 20 further includes a logic gate sub-unit 22.
  • the logic gate sub-unit 22 is connected between the output terminal of the negative voltage comparison sub-unit 11 and the input terminal of the push-pull circuit sub-unit; the logic gate sub-unit 22 is used to generate a first control signal according to the drain voltage turn-off signal.
  • the control signal is used to control the push-pull circuit subunit 21 to conduct the drain of the GaN power device with the common terminal, thereby realizing rapid discharge of the drain.
  • the push-pull circuit sub-unit 21 is also used to, when the amplitude of the gate protection voltage is higher than the preset amplitude, according to the second
  • the control signal powers up or powers down the drain of the GaN power device 40
  • the logic gate subunit 22 is also used to generate a second control signal according to the enable signal when the amplitude of the gate protection voltage is higher than the preset amplitude
  • the second control signal is used to control the push-pull circuit subunit 21 to power up or power down the drain of the GaN power device 40.
  • the logic gate subunit 22 generates a second control signal for controlling the push-pull circuit subunit 21 according to the enable signal when the amplitude of the gate protection voltage is higher than the preset amplitude, thereby achieving In this way, the enable signal is used to actively control the power up and down of the drain of the GaN power device 40.
  • the high level of the enable signal is used to control the push-pull circuit subunit 21 to power up the drain of the GaN power device 40, that is, to connect the second power supply to the drain of the GaN power device 40; the low power of the enable signal The level is used to control the push-pull circuit subunit 21 to power down the drain of the GaN power device 40, that is, to disconnect the second power supply from the drain of the GaN power device 40.
  • FIG. 3 is a preferred circuit topology diagram of a logic gate subunit 22 according to an embodiment of the present application.
  • the logic gate subunit 22 includes a first switch tube T1, a second switch tube T2, a logic AND gate, and a logic inverter.
  • the control terminal of the first switch tube T1 is connected to the negative voltage comparison subunit 11 through the third resistor R3; the output terminal of the first switch tube T1 and the output terminal of the second switch tube T2 are both connected to the common terminal GND;
  • the output terminal of is connected to the second input terminal of the push-pull circuit subunit 21; the second input terminal of the logic AND gate is used to receive the enable signal, and the output terminal of the logic AND gate is connected to the control terminal of the second switch tube T2.
  • the drain voltage turn-off signal be converted into the first control signal for controlling the push-pull circuit sub-unit 21 to connect the drain of the GaN power device to the common terminal, but also
  • the enable signal is generated to control the push-pull circuit subunit 21 to connect the GaN power device 40
  • the second control signal for powering up or powering down the drain.
  • the switch tube in the embodiment of the present application includes but is not limited to a triode or a MOS tube.
  • those skilled in the art can easily think of modifying the circuit topology diagrams disclosed in this application to a circuit topology diagram compatible with the selection of the switching tube according to the specific selection of the switching tube. Therefore, regardless of the switching tube Whether it is an NPN type or a PNP type can implement the present application, which is not limited in the embodiments of the present application.
  • the push-pull circuit subunit 21 includes a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6.
  • the third switching tube T3 is a P-MOS tube
  • the fourth switching tube T4 is an N-MOS tube.
  • the P-MOS tube is used as the upper tube of the push-pull circuit sub-unit 21
  • the N-MOS tube is used as the lower tube of the push-pull circuit sub-unit 21, which simplifies the circuit structure of the push-pull circuit sub-unit 21.
  • the push-pull circuit sub-units 21 provided in the above embodiment are turned on in turn under the control of the control signal, and keep the drain of the GaN power device connected to the common terminal when the amplitude of the gate protection voltage is lower than the preset amplitude.
  • the drain of the GaN power device is controlled to be powered on or off according to the enable signal.
  • the power-on and power-off protection of the GaN power device can be achieved through the above-mentioned push-pull circuit subunit 21.
  • the lower tube of the aforementioned push-pull circuit subunit 21 is turned on, thereby connecting the drain of the GaN power device to the common terminal to achieve rapid discharge of the drain, ensuring GaN power
  • the drain voltage of the device drops to zero before the gate voltage of the GaN power device, which prevents the GaN power device from being burnt out.
  • the gate voltage switching unit 30 is powered by a dual power supply of a first power supply V1 and a gate protection voltage V3; the gate voltage switching unit 30 includes The gate drive voltage input terminal Vg, the gate protection voltage input terminal Vp, the enable signal input terminal enable, and the gate voltage output terminal Vgs; the gate drive voltage input terminal Vg is connected to the output terminal of the gate drive unit, and the gate protection voltage
  • the input terminal Vp is connected to the output terminal of the negative voltage conversion subunit 12, the enable signal input terminal enable is used to receive the enable signal, and the gate voltage output terminal Vgs is connected to the gate of the GaN power device; the gate voltage switching unit 30 is used to The enable signal provides the gate driving voltage generated by the gate driving unit or the gate protection voltage generated by the negative voltage conversion subunit 12 to the gate of the GaN power device.
  • the above-mentioned gate voltage switching unit 30 is powered by a dual power supply, which ensures that the GaN power device has
  • the enable signal received by the enable signal input terminal enable is used to control the switching of the gate voltage switching unit 30.
  • the rising edge of the enable signal represents power-on of the GaN power device.
  • the gate voltage of the GaN power device is switched to the gate driving voltage by the gate voltage switching unit 30; the falling edge of the enable signal represents the power-off of the GaN power device.
  • the gate voltage of the GaN power device is switched to the gate protection voltage by the gate voltage switching unit 30, so as to ensure that the gate of the GaN power device has a gate voltage that can protect the GaN power device from being burned during the power-on and power-off process.
  • the gate driving unit in the above embodiment may be any driving unit capable of generating a gate driving voltage.
  • the GaN power device protection circuit further includes a gate drive unit 50 connected to The gate voltage switching unit 30 is used to generate the gate driving voltage of the GaN power device.
  • FIG. 7 is a third block diagram of a preferred structure of a protection circuit for a GaN power device according to an embodiment of the present application.
  • the gate driving unit 50 includes a gate driving subunit 51 and an adder subunit 52.
  • the output terminal of the driving unit 50 is connected to the input terminal of the adder subunit 52.
  • the adder subunit 52 is powered by a dual power supply of the first power supply V1 and the gate protection voltage V3; wherein, the gate driving subunit 51 is used to generate the gate control voltage; the adder subunit 52 is used to convert the negative voltage
  • the gate protection voltage output by the subunit 12 and the gate control voltage are accumulated to obtain the gate driving voltage.
  • the gate drive unit 50 provided in this embodiment accumulates the gate protection voltage output by the negative voltage conversion sub-unit 12 and the gate control voltage through the adder sub-unit 52 to obtain the gate drive voltage, so that the gate drive voltage in the gate drive sub-unit 51 When the output voltage is zero, the gate driving unit 50 can still output a gate voltage capable of protecting the GaN power device (at this time, the output of the gate driving unit 50 is the same as the gate protection voltage).
  • the adder subunit 52 of this embodiment is preferably an in-phase adder.
  • 8 is a circuit topology diagram of an adder subunit 52 according to an embodiment of the present application.
  • the adder subunit 52 includes: a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and an operational amplifier A1.
  • the output terminal of the operational amplifier A1 is connected to the gate voltage switching unit 30, the output terminal of the operational amplifier A1 is also connected to the common terminal GND through the tenth resistor R10 and the ninth resistor R9; the inverting input terminal of the operational amplifier A1 is connected To the connection node of the tenth resistor R10 and the ninth resistor R9; the positive phase input terminal of the operational amplifier A1 is connected to the gate driving subunit 51 through the seventh resistor R7, and to the negative voltage conversion subunit through the eighth resistor R8 12 output terminal; the positive power terminal of the operational amplifier A1 is connected to the first power supply V1, and the negative power terminal of the operational amplifier A1 is connected to the output terminal of the negative voltage conversion subunit 12.
  • the operational amplifier A1 mentioned above can be implemented by the LM7321MF chip or other chips with similar functions.
  • the above-mentioned adder subunit 52 can also reduce the output impedance of the gate voltage driving unit 50 to prevent voltage fluctuations due to current changes, thereby providing a stable gate voltage for the GaN power device.
  • the gate driving subunit 51 includes a digital-to-analog converter, preferably a digital chip with a digital-to-analog conversion function.
  • the analog signal output by the gate driving subunit 51 is preferably a voltage signal, and the corresponding voltage range is 0 to 3.3V.
  • the enable signal can be, but is not limited to, the transistor-transistor logic provided by the digital board.
  • the (Transistor-Transistor Logic, TTL for short) level can be either a high level or a low level.
  • the GaN power device includes but is not limited to one of the following: an enhancement mode GaN high electron mobility transistor or a depletion mode GaN high electron mobility transistor.
  • the circuit includes: a negative voltage generating unit 10 composed of an LTC1261 chip of Arnold Semiconductor, a gate voltage switching unit 30, The gate driving unit 50 and the drain voltage switching unit 20.
  • the gate driving unit 50 includes a gate voltage driving sub-unit 51 and an adder sub-unit 52.
  • the adder sub-unit 52 is powered by a dual power supply of a first power supply V1 and a gate protection voltage V3;
  • the drain voltage switching unit 20 includes The logic gate subunit 22 and the push-pull circuit subunit 21;
  • the gate voltage switching unit 30 includes a single-pole double-throw switch powered by a dual power supply of a first power supply V1 and a gate protection voltage V3.
  • the LTC1261 chip in this embodiment generates an adjustable negative pressure output through the OUT pin and a negative pressure detection indication signal through the REG pin, where the negative pressure detection indication signal can be high level Or low level, and the negative pressure detection indication signal is input to the logic gate subunit 22, wherein the first stage NPN transistor and the second stage NPN transistor in the logic gate subunit 22 are used to enhance its output load capacity so as to
  • the PMOS tube in the push-pull circuit subunit 21 is driven, and the adjustable negative voltage output by the LTC1261 chip is adjusted to the maximum output negative voltage, which is used to provide negative voltage to the adder subunit 52 and the single-pole double-throw switch powered by the dual power supply.
  • the operational amplifier in the adder subunit 52 is powered by dual power supplies, and the inverting and non-inverting input signals of the operational amplifier are respectively provided by the 0 ⁇ 3.3V voltage provided by the digital-to-analog converter and the -5V voltage output by the OUT pin of the LTC1261 chip Among them, by adjusting the output voltage of the digital-to-analog converter, a suitable gate voltage Vg can be provided for the GaN power device 40.
  • the two input signals of the dual-power SPDT switch are the gate voltage Vg and the -5V voltage output by the OUT pin.
  • the control terminal of the dual-power SPDT switch is connected to the enable signal, and the dual-power SPDT switch has an enable signal.
  • the output signal of the throw switch is connected to the gate of the GaN power device 40.
  • the enable signal controls the double power supply single-pole double-throw switch to turn on the adder unit or the OUT pin of the LTC1261 chip, thereby controlling the gate of the GaN power device 40 Turn on the adder subunit 52 or the OUT pin of the LTC1261 series chip.
  • the output terminal of the push-pull circuit subunit 21 is connected to the drain of the GaN power device 40 to provide the GaN power device 40 with a normal working drain voltage under the working state, and to make the GaN power device 40 powered off or on.
  • the drain of the power device 40 is connected to the common terminal, so as to ensure that the drain of the GaN power device 40 will not be burnt out.
  • the enable signal in the logic gate subunit 22 and the single pole double throw switch powered by the dual power supply can be provided by the TTL level of the digital board, and the enable signal and the negative pressure detection indicator signal are output through the logic gate subunit 22
  • Two complementary timing signals control the PMOS tube and the NMOS tube in the push circuit subunit.
  • the PMOS tube can be controlled to be turned on while the NMOS tube is turned off, so as to ensure that the voltage of the drain of the GaN power device 40 is loaded normally, and the GaN power device 40 is powered on or off.
  • the PMOS tube can also be controlled to be turned off while the NMOS tube is turned on, so as to ensure that the voltage of the drain of the GaN power device 40 is quickly discharged to the ground through the NMOS.
  • the LTC1261 can set the magnitude of the negative voltage output by the OUT pin by adjusting the resistors R1 and R2. At the same time, it can also output a negative pressure detection indicator signal.
  • the negative pressure detection indicator signal can output the negative voltage at the OUT pin. Before reaching 95% of the preset amplitude, maintain the high level until the negative voltage output by the OUT pin reaches 95% of the preset amplitude, the negative pressure detection indicator signal will flip from high to low Level.
  • the negative voltage detection indication signal will generate a high level internally at the moment of power-on.
  • the power supply VDD of the push-pull circuit subunit 21 has been turned on, but through the logic gate power supply with the first-stage NPN-type transistor and the second-stage NPN-type transistor to control the switch PMOS transistor of the drain of the GaN power device 40 to be in an off state, Therefore, there is no voltage at the drain of the GaN power device 40 at this time.
  • the negative pressure detection indication signal maintains a high level for about 250us. Therefore, during the power-on sequence, the protection circuit of the GaN power device 40 protects the GaN power. The device 40 is not burned out.
  • the level of the negative voltage detection indication signal is immediately pulled from 0 to the high level. Since the gate voltage switching unit is controlled only by the enable signal, it still maintains the state before power off. And the switch PMOS tube of the drain voltage of the GaN power device 40 is controlled by the logic sub-gate unit to turn off the PMOS tube and also powered off. At the same time, the logic gate sub-unit 22 controls the NMOS tube to turn on, so that the drain of the GaN power device 40 is connected.
  • the common terminal so that the voltage of the drain of the GaN power device 40 is released to the ground, the voltage of the gate of the GaN power device 40 gradually drops from the voltage before the power-off to 0, and the GaN power is lowered to 0 before the gate voltage drops to 0.
  • the drain voltage of the device 40 has already reached zero, thereby ensuring that the GaN power device 40 will not be burned out during the power-off process.
  • the enable signal is also the control signal of the dual power single pole double throw switch.
  • the dual-power single-pole double-throw switch When the enable signal is at a high level, the dual-power single-pole double-throw switch is controlled to turn to the end connected to the output terminal of the adder subunit 52; when the enable signal is at a low level, the dual-power single-pole double-throw switch is controlled to turn toward One end connected to the -5V terminal of the pin output, the response speed of the dual power single-pole double-throw switch is within 100ns.
  • the reasonable cooperation between the above enable signal and the push-pull circuit subunit 21, the logic gate subunit 22 and the dual power single pole double throw switch can safely ensure that the gate voltage of the GaN power device 40 has been loaded before the leakage voltage is loaded and will not be damaged.
  • Safety negative pressure of GaN power device 40 As shown in Fig. 10, at t0, the protection circuit of the GaN power device 40 starts to lose power, and the drain voltage of the GaN power device is connected to the common terminal instantaneously, so that the drain voltage is released instantaneously, and the gate voltage is slowly reduced, and remains at The safety negative pressure of the GaN power device is not damaged, and the protection circuit of the GaN power device 40 protects the GaN power device 40 when the power is off.
  • the dual-power single-pole double-throw switch ensures that the gate voltage of the GaN power device 40 is between the normal set value of the gate voltage and -5V under any circumstances, and it can also ensure that the gate voltage of the GaN power device 40 is between the normal setting value of the gate voltage and -5V under any circumstances.
  • the GaN power device 40 will not be burned out.
  • the protection function can be realized in the case of the GaN power device being powered on or off or the protection circuit of the GaN power device is powered off;
  • the protection circuit of GaN power devices users do not need to care about the power-on sequence of the gate and drain of the GaN power device, but directly use the enable signal to control the power-on and power-off operations of the GaN power device.
  • the protection circuit of the GaN power device provided by the application embodiment can make the power-on and power-off operations of the GaN power device the same as the power-on and power-off operations of a traditional LDMOS tube.

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Abstract

GaN功率器件的保护电路，包括负压生成单元、栅极电压切换单元和漏极电压切换单元；负压转换子单元用于将供电电源转换为栅极保护电压；负压比较子单元用于在栅极保护电压的幅值低于预设幅值的情况下输出漏极电压关断信号；将漏极电压切换单元的推挽电路子单元分别连接至负压比较子单元的输出端、公共端、GaN功率器件的漏极以及GaN功率器件的漏极的供电电源，推挽电路子单元用于根据漏极电压关断信号将GaN功率器件的漏极与公共端导通。

Description

GaN功率器件的保护电路
相关申请
本申请要求2019年12月31日申请的，申请号为201911413201.3，发明名称为“GaN功率器件的保护电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，特别是涉及一种GaN功率器件的保护电路。
背景技术
目前随着通信技术的不断更新换代，对信号的处理能力也越来越高，传统的横向扩散金属氧化物半导体(Laterally-Diffused Metal-Oxide Semiconductor，简称LDMOS)管已经无法满足新一代的通信技术要求了，氮化镓(Gallium Nitride，简称GaN)功率器件的高密度、超带宽、高效率、高频率范围等特性正是为新一代通信技术量身打造的。
LDMOS管栅极电压和漏极电压不存在上电和掉电顺序，即栅压和漏压可以任意上电或者断电LDMOS管都不会损坏。而GaN功率器件受其特性影响，其栅极电压和漏极电压的上电和掉电顺序的要求极为苛刻，否则GaN功率器件就会被烧毁无法工作。
目前GaN功率器件的应用不够成熟，特别是GaN功率器件的时序保护电路仍然没有形成有效的保护。例如，相关技术中GaN功率器件的保护电路在供电稳定的情况下为GaN功率器件提供保护；然而，在GaN功率器件的保护电路自身供电电源不稳定或者GaN功率器件的保护电路掉电的情况下，若GaN功率器件的栅极电压先于漏极电压掉到零，则GaN功率器件将被烧坏。
相关技术中针对GaN功率器件的保护电路掉电导致GaN功率器件容易被烧坏的问题，尚未提出有效的解决方案。
发明内容
根据本申请的各种实施例，提供一种GaN功率器件的保护电路，所述GaN功率器件的保护电路包括负压生成单元、栅极电压切换单元和漏极电压切换单元；所述负压生成单元、所述栅极电压切换单元和所述漏极电压切换单元分别与所述GaN功率器件的保护电路的第一供电电源连接；所述负压生成单元包括负压转换子单元和负压比较子单元，所述负压转换子 单元用于将所述第一供电电源转换为栅极保护电压，并将所述栅极保护电压提供给所述栅极电压切换单元；所述负压比较子单元用于在所述栅极保护电压的幅值低于预设幅值的情况下输出漏极电压关断信号；所述漏极电压切换单元包括：推挽电路子单元，其中，所述推挽电路子单元分别连接至所述负压比较子单元的输出端、公共端、所述GaN功率器件的漏极以及所述GaN功率器件的漏极的第二供电电源；所述推挽电路子单元用于根据所述漏极电压关断信号将所述GaN功率器件的漏极与所述公共端导通。
在其中一些实施例中，所述漏极电压切换单元还包括：逻辑门子单元，所述逻辑门子单元连接至所述负压比较子单元的输出端和所述推挽电路子单元的输入端之间；所述逻辑门子单元用于根据所述漏极电压关断信号生成第一控制信号，所述第一控制信号用于控制所述推挽电路子单元将所述GaN功率器件的漏极与所述公共端导通。
在其中一些实施例中，所述推挽电路子单元还用于在所述栅极保护电压的幅值高于预设幅值的情况下，根据第二控制信号将所述GaN功率器件的漏极上电或者下电；所述逻辑门子单元还用于在所述栅极保护电压的幅值高于预设幅值的情况下，根据使能信号生成所述第二控制信号，所述第二控制信号用于控制所述推挽电路子单元将所述GaN功率器件的漏极上电或下电。
在其中一些实施例中，所述逻辑门子单元包括第一开关管、第二开关管、逻辑与门、逻辑非门、第一电阻、第二电阻和第三电阻，其中，所述第一开关管的输入端、所述逻辑与门的第一输入端和所述逻辑非门的输入端均通过所述第一电阻连接至所述第一供电电源；所述第二开关管的输入端通过所述第二电阻连接至所述第一供电电源，所述第二开关管的输入端还连接至所述推挽电路子单元的第一输入端；所述第一开关管的控制端通过所述第三电阻连接至所述负压比较子单元；所述第一开关管的输出端、所述第二开关管的输出端均连接至公共端；所述逻辑非门的输出端连接至所述推挽电路子单元的第二输入端；所述逻辑与门的第二输入端用于接收所述使能信号，所述逻辑与门的输出端连接至所述第二开关管的控制端。
在其中一些实施例中，所述推挽电路子单元包括第四电阻、第五电阻、第六电阻、以及两个极性相反的第三开关管和第四开关管，其中，所述第三开关管的输入端连接至所述第二供电电源，所述第三开关管的控制端连接至所述推挽电路子单元的第一输入端；所述第四电阻连接在所述第三开关管的控制端和所述第二供电电源之间；所述第五电阻连接在所述推挽电路子单元的第二输入端和所述第四开关管的控制端之间；所述第三开关管的输出端和所述第四开关管的输入端均连接至所述GaN功率器件的漏极；所述第四开关管的输出端通过所述第六电阻连接公共端，且所述第四开关管的衬底连接公共端。
在其中一些实施例中，所述栅极电压切换单元由所述第一供电电源和所述栅极保护电 压双电源供电；所述栅极电压切换单元包括栅极驱动电压输入端、栅极保护电压输入端、使能信号输入端和栅极电压输出端；所述栅极驱动电压输入端连接栅极驱动单元的输出端，所述栅极保护电压输入端连接所述负压转换子单元的输出端，所述使能信号输入端用于接收使能信号，所述栅极电压输出端连接所述GaN功率器件的栅极；所述栅极电压切换单元用于根据所述使能信号将所述栅极驱动单元生成的栅极驱动电压或者所述负压转换子单元生成的所述栅极保护电压提供给所述GaN功率器件的栅极。
在其中一些实施例中，所述GaN功率器件的保护电路还包括：栅极驱动单元，所述栅极驱动单元用于生成所述GaN功率器件的栅极驱动电压。
在其中一些实施例中，所述栅极驱动单元包括栅极驱动子单元和加法器子单元，所述加法器子单元由所述第一供电电源和所述栅极保护电压双电源供电；其中，所述栅极驱动子单元用于生成栅极控制电压；所述加法器子单元用于将所述负压转换子单元输出的栅极保护电压与所述栅极控制电压累加，得到所述栅极驱动电压。
在其中一些实施例中，所述加法器子单元包括：第七电阻、第八电阻、第九电阻、第十电阻和运算放大器，其中，所述运算放大器的输出端连接至所述栅极电压切换单元，所述运算放大器的输出端还通过所述第十电阻和所述第九电阻连接至公共端；所述运算放大器的反相输入端连接至所述第十电阻和所述第九电阻的连接结点；所述运算放大器的正相输入端通过所述第七电阻连接至所述栅极驱动子单元，以及通过所述第八电阻连接至所述负压转换子单元的输出端；所述运算放大器的正电源端连接至所述第一供电电源，所述运算放大器的负电源端连接至所述负压转换子单元的输出端。
在其中一些实施例中，所述GaN功率器件包括：增强型GaN高电子迁移率晶体管或耗尽型GaN高电子迁移率晶体管。
在其中一些实施例中，所述负压生成单元包括：亚诺德半导体公司的LTC 1261系列芯片。
上述GaN功率器件的保护电路具有以下优点：
GaN功率器件的保护电路包括负压生成单元、栅极电压切换单元和漏极电压切换单元；负压生成单元、栅极电压切换单元和漏极电压切换单元分别与GaN功率器件的保护电路的第一供电电源连接；负压生成单元包括负压转换子单元和负压比较子单元，负压转换子单元用于将第一供电电源转换为栅极保护电压，并将栅极保护电压提供给栅极电压切换单元；负压比较子单元用于在栅极保护电压的幅值低于预设幅值的情况下输出漏极电压关断信号；漏极电压切换单元包括：推挽电路子单元，其中，推挽电路子单元分别连接至负压比较子单元的输出端、公共端、GaN功率器件的漏极以及GaN功率器件的漏极的第二供电电源，推挽电路 子单元用于根据漏极电压关断信号将GaN功率器件的漏极与公共端导通。通过本申请提供的GaN功率器件的保护电路解决了相关技术中GaN功率器件的保护电路掉电导致GaN功率器件容易被烧坏的问题，避免了GaN功率器件的保护电路掉电导致的GaN功率器件的损坏。
附图说明
为了更好地描述和说明这里公开的那些申请的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的申请、目前描述的实施例和/或示例以及目前理解的这些申请的最佳模式中的任何一者的范围的限制。
图1是本申请实施例的GaN功率器件的保护电路的结构框图。
图2是本申请实施例的一种GaN功率器件的保护电路的优选结构框图一。
图3是本申请实施例的一种逻辑门子单元22的优选电路拓扑图。
图4是本申请实施例的一种推挽电路子单元21的优选电路拓扑图。
图5是本申请实施例的一种栅极电压切换单元30的结构示意图。
图6是本申请实施例的一种GaN功率器件的保护电路的优选结构框图二。
图7是本申请实施例的一种GaN功率器件的保护电路的优选结构框图三。
图8是本申请实施例的一种加法器子单元52的电路拓扑图。
图9是本申请实施例的一种GaN功率器件的保护电路的电路拓扑图。
图10是本申请实施例的GaN功率器件的保护电路掉电时GaN栅极电压和漏极电压的变化曲线示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。基于本申请中的实例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实例，都属于本申请保护的范围。
显而易见地，下面描述中的附图仅仅是本申请的一些示例或实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图将本申请应用于其他类似情景。此外，还可以理解的是，虽然这种开发过程中所作出的努力可能是复杂并且冗长的，然而对于与本申请公开的内容相关的本领域的普通技术人员而言，在本申请揭露的技术内容的基础上进行的一些设计，制造或者生产等变更只是常规的技术手段，不应当理解为本申请公开的内容不充分。
在本申请中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
除非另作定义，权利要求书和说明书中使用的技术术语或者科学术语应当为本申请所属技术领域内具有一般技能的人士所理解的通常意义。本申请专利申请说明书以及权利要求书中使用的“一”、“一个”、“一种”、“该”等类似词语并不表示数量限制，可表示单数或复数。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同元件，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电气的连接，不管是直接的还是间接的。本申请专利申请说明书以及权利要求书中使用的“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
在本实施例中提供了一种GaN功率器件40的保护电路。图1是本申请实施例的一种GaN功率器件40的保护电路的结构框图，该GaN功率器件40的保护电路包括：负压生成单元10、栅极电压切换单元30和漏极电压切换单元20；负压生成单元10、栅极电压切换单元30和漏极电压切换单元20分别与GaN功率器件40的保护电路的第一供电电源连接；负压生成单元10包括负压转换子单元12和负压比较子单元11，负压转换子单元12与负压比较子单元11连接，负压转换子单元12用于将供电电源转换为栅极保护电压，并将栅极保护电压提供给栅极电压切换单元30；负压比较子单元11用于在栅极保护电压的幅值低于预设幅值的情况下输出漏极电压关断信号；漏极电压切换单元20包括：推挽电路子单元21，其中，推挽电路子单元21分别连接至负压比较子单元11的输出端、公共端、GaN功率器件40的漏极以及GaN功率器件40的漏极的第二供电电源，推挽电路子单元21用于根据漏极电压关断信号将GaN功率器件40的漏极与公共端导通。
在本实施例中，通过将推挽电路子单元21分别连接至负压比较子单元11的输出端、公共端、GaN功率器件40的漏极以及GaN功率器件40的漏极的供电电源，并在负压比较子单元11检测到栅极保护电压的幅值低于预设幅值的情况下输出漏极电压关断信号，然后推挽电路子单元21根据该漏极电压关断信号将GaN功率器件40的漏极与公共端导通的方式，使得GaN功率器件40的保护电路在掉电时，GaN功率器件40的漏极连接到公共端，从而使得漏极迅速放电，从而保证了GaN功率器件40的漏极电压先于栅极电压掉到零，保护了GaN 功率器件40不被烧坏。
在本实施例中，GaN功率器件40的保护电路的第一供电电源的电压等级根据电路设计的需要而确定，通常可以为5V至5.8V。
在本实施例中，负压生成单元10可以是但不限于亚诺德半导体公司的LTC 1261系列芯片。例如，可以为LTC 1261CS8。其中，上述芯片的OUT引脚为负压转换子单元12的输出端，REG引脚为负压比较子单元11的输出端。采用本实施例提供的LTC 1261系列芯片，REG引脚能够在负压转换子单元12输出的负电压的幅值小于预设幅值时输出高电平(即上述实施例的漏极电压关断信号)；以及在负压转换子单元12输出的负电压的幅值高于预设幅值时输出低电平。在本实施例中使用上述芯片，可以为GaN功率器件40的上电和下电提供可靠的时序，保证GaN功率器件40的不被烧坏。
图2是本申请实施例的一种GaN功率器件的保护电路的优选结构框图一，在其中一些实施例中，为了将漏极电压关断信号转换为推挽电路子单元21的控制信号，漏极电压切换单元20还包括逻辑门子单元22。该逻辑门子单元22连接至负压比较子单元11的输出端和推挽电路子单元的输入端之间；逻辑门子单元22用于根据漏极电压关断信号生成第一控制信号，该第一控制信号用于控制推挽电路子单元21将GaN功率器件的漏极与公共端导通，从而实现漏极的快速放电。
在其中一些实施例中，为了便于控制GaN功率器件40的漏极上下电，推挽电路子单元21还用于在栅极保护电压的幅值高于预设幅值的情况下，根据第二控制信号将GaN功率器件40的漏极上电或者下电；逻辑门子单元22还用于在栅极保护电压的幅值高于预设幅值的情况下，根据使能信号生成第二控制信号，该第二控制信号用于控制推挽电路子单元21将GaN功率器件40的漏极上电或下电。在本实施例中，逻辑门子单元22在栅极保护电压的幅值高于预设幅值的情况下，根据使能信号生成用于控制推挽电路子单元21的第二控制信号，从而实现了采用使能信号主动控制GaN功率器件40的漏极上下电。通常，使能信号的高电平用于控制推挽电路子单元21将GaN功率器件40的漏极上电，即将第二供电电源接入GaN功率器件40的漏极；使能信号的低电平用于控制推挽电路子单元21将GaN功率器件40的漏极下电，即将第二供电电源与GaN功率器件40的漏极断开。
图3是本申请实施例的一种逻辑门子单元22的优选电路拓扑图，在其中一些实施例中该逻辑门子单元22包括第一开关管T1、第二开关管T2、逻辑与门、逻辑非门、第一电阻R1、第二电阻R2和第三电阻R3，其中，第一开关管T1的输入端、逻辑与门的第一输入端和逻辑非门的输入端均通过第一电阻R1连接至第一供电电源V1；第二开关管T2的输入端通过第二电阻R2连接至第一供电电源V1，第二开关管T2的输入端还连接至推挽电路子单 元21的第一输入端；第一开关管T1的控制端通过第三电阻R3连接至负压比较子单元11；第一开关管T1的输出端、第二开关管T2的输出端均连接至公共端GND；逻辑非门的输出端连接至推挽电路子单元21的第二输入端；逻辑与门的第二输入端用于接收使能信号，逻辑与门的输出端连接至第二开关管T2的控制端。
通过上述的漏极电压切换单元，不仅能够将漏极电压关断信号转换为用于控制推挽电路子单元21将GaN功率器件的漏极与公共端导通的第一控制信号，还能够在栅极保护电压的幅值高于预设幅值(第一开关管T1的控制端为低电平)的情况下根据使能信号生成用于控制推挽电路子单元21将GaN功率器件40的漏极上电或下电的第二控制信号。
需要说明的是，在本申请实施例中的开关管包括但不限于三极管或者MOS管。并且，根据本申请披露的内容，本领域技术人员容易想到根据开关管的具体选型将本申请披露的各电路拓扑图修改为与开关管选型相适应的电路拓扑图，因此，无论开关管为NPN型还是PNP型均可以实现本申请，在本申请实施例中并不作限定。
图4是本申请实施例的一种推挽电路子单元21的优选电路拓扑图，在其中一些实施例中，推挽电路子单元21包括第四电阻R4、第五电阻R5、第六电阻R6、以及两个极性相反的第三开关管T3和第四开关管T4，其中，第三开关管T3的输入端连接至第二供电电源V2，第三开关管T3的控制端连接至推挽电路子单元21的第一输入端；第四电阻R4连接在第三开关管T3的控制端和第二供电电源V2之间；第五电阻R5连接在推挽电路子单元21的第二输入端和第四开关管T4的控制端之间；第三开关管T3的输出端和第四开关管T4的输入端均连接至GaN功率器件40的漏极；第四开关管T4的输出端通过第六电阻R6连接公共端GND，且第四开关管T4的衬底连接公共端GND。
较优地，上述第三开关管T3为P-MOS管，上述第四开关管T4为N-MOS管。由P-MOS管作为推挽电路子单元21的上管，N-MOS管作为推挽电路子单元21的下管，简化了推挽电路子单元21的电路结构。
上述实施例提供的推挽电路子单元21在控制信号的控制下轮流导通，在栅极保护电压的幅值低于预设幅值的情况下保持GaN功率器件的漏极连接公共端，在栅极保护电压的幅值高于预设幅值的情况下根据使能信号控制GaN功率器件的漏极上电或下电。通过上述的推挽电路子单元21可以GaN功率器件的上电和下电保护。此外，当GaN功率器件的保护电路掉电时，上述的推挽电路子单元21的下管导通，从而将GaN功率器件的漏极连接到公共端实现漏极的快速放电，保证了GaN功率器件的漏极电压先于GaN功率器件的栅极电压掉到零，避免了GaN功率器件被烧坏。
图5是本申请实施例的一种栅极电压切换单元30的结构示意图，该栅极电压切换单 元30由第一供电电源V1和栅极保护电压V3双电源供电；栅极电压切换单元30包括栅极驱动电压输入端Vg、栅极保护电压输入端Vp、使能信号输入端enable和栅极电压输出端Vgs；栅极驱动电压输入端Vg连接栅极驱动单元的输出端，栅极保护电压输入端Vp连接负压转换子单元12的输出端，使能信号输入端enable用于接收使能信号，栅极电压输出端Vgs连接GaN功率器件的栅极；栅极电压切换单元30用于根据使能信号将栅极驱动单元生成的栅极驱动电压或者负压转换子单元12生成的栅极保护电压提供给GaN功率器件的栅极。上述的栅极电压切换单元30通过双电源供电，保证了GaN功率器件在上下电过程中具有能够保护GaN功率器件不被烧坏的栅压。
在其中一些实施例中，使能信号输入端enable接收的使能信号用于控制栅极电压切换单元30的切换。通常，使能信号的上升沿代表GaN功率器件上电，此时GaN功率器件的栅极电压被栅极电压切换单元30切换到栅极驱动电压；使能信号为下降沿代表GaN功率器件下电，此时GaN功率器件的栅极电压被栅极电压切换单元30切换到栅极保护电压，从而保证GaN功率器件的栅极在上下电过程中具有能够保护GaN功率器件不被烧坏的栅压。
在上述实施例中的栅极驱动单元可以为能够生成栅极驱动电压的任意驱动单元。
图6是本申请实施例的一种GaN功率器件的保护电路的优选结构框图二，在其中一些实施例中，GaN功率器件的保护电路还包括栅极驱动单元50，该栅极驱动单元50连接至栅极电压切换单元30，用于生成GaN功率器件的栅极驱动电压。
图7是本申请实施例的一种GaN功率器件的保护电路的优选结构框图三，在其中一些实施例中，栅极驱动单元50包括栅极驱动子单元51和加法器子单元52，栅极驱动单元50的输出端连接至加法器子单元52的输入端。其中，加法器子单元52由第一供电电源V1和栅极保护电压V3双电源供电；其中，栅极驱动子单元51用于生成栅极控制电压；加法器子单元52用于将负压转换子单元12输出的栅极保护电压与栅极控制电压累加，得到栅极驱动电压。
本实施例提供的栅极驱动单元50通过加法器子单元52将负压转换子单元12输出的栅极保护电压与栅极控制电压累加得到栅极驱动电压，使得在栅极驱动子单元51的输出电压为零的情况下，栅极驱动单元50仍可以输出能够保护GaN功率器件的栅极电压(此时栅极驱动单元50的输出与栅极保护电压的电压相同)。
本实施例的加法器子单元52优选为同相加法器。图8是本申请实施例的一种加法器子单元52的电路拓扑图，加法器子单元52包括：第七电阻R7、第八电阻R8、第九电阻R9、第十电阻R10和运算放大器A1，其中，运算放大器A1的输出端连接至栅极电压切换单元30，运算放大器A1的输出端还通过第十电阻R10和第九电阻R9连接至公共端GND；运算放大 器A1的反相输入端连接至第十电阻R10和第九电阻R9的连接结点；运算放大器A1的正相输入端通过第七电阻R7连接至栅极驱动子单元51，以及通过第八电阻R8连接至负压转换子单元12的输出端；运算放大器A1的正电源端连接至第一供电电源V1，运算放大器A1的负电源端连接至负压转换子单元12的输出端。上述的运算放大器A1可以由LM7321MF芯片或者其他具有类似功能的芯片实现。上述的加法器子单元52还能够降低栅压驱动单元50的输出阻抗，防止由于电流变化造成电压波动，从而给GaN功率器件提供稳定的栅压。
在本实施例中，栅极驱动子单元51包括数模转换器，优选为具有数模转换功能的数字芯片。栅极驱动子单元51输出的模拟信号优选为电压信号，其对应的电压范围为0至3.3V。
在上述实施例中，使能信号可以是但不限于由数字板提供的晶体管-晶体管逻辑
(Transistor-Transistor Logic，简称TTL)电平，可以是高电平也可以是低电平。
在本申请实施例中，GaN功率器件包括但不限于以下之一：增强型GaN高电子迁移率晶体管或耗尽型GaN高电子迁移率晶体管。
需要说明的是，在本申请上述实施例中描述的GaN功率器件的保护电路的各个单元或者子单元、模块仅表示本申请实施例的可能的一种或者多种实现方式。对于本领域技术人员而言，根据上述实施例披露的内容进行的不脱离本申请实质的变形均应在本申请所要求保护的范围内。
下面以优选的实施例和附图来对本发明实施例进行描述和说明。
本优选实施例中叙述的是一种适用于GaN功率器件40的保护电路。图9是本申请优选实施例的一种GaN功率器件的保护电路的电路拓扑图，该电路包括：由亚诺德半导体公司的LTC1261芯片组成的负压生成单元10，栅极电压切换单元30，栅极驱动单元50以及漏极电压切换单元20。其中，栅极驱动单元50包括栅极电压驱动子单元51和加法器子单元52，加法器子单元52由第一供电电源V1和栅极保护电压V3双电源供电；漏极电压切换单元20包括逻辑门子单元22和推挽电路子单元21；栅极电压切换单元30包括由第一供电电源V1和栅极保护电压V3双电源供电的单刀双掷开关。
如图9所示，本实施例中的LTC1261芯片通过OUT引脚产生一个可调负压输出和通过REG引脚产生一个负压检测指示信号，其中，该负压检测指示信号可以是高电平或低电平，且该负压检测指示信号输入到逻辑门子单元22，其中，逻辑门子单元22中的第一级NPN型三极管和第二级NPN型三极管用于增强其输出带负载能力以便能够驱动推挽电路子单元21中的PMOS管，且LTC1261芯片输出的可调负压调整到最大输出负压，用来给加法器子单元52和双电源供电的单刀双掷开关提供负电压。
该加法器子单元52中的运算放大器为双电源供电，且运算放大器的反相和正相输入 信号分别由数模转换器提供的0～3.3V电压以及LTC1261芯片的OUT引脚输出的-5V电压，其中，通过调整数模转换器的输出电压就能够为GaN功率器件40提供合适的栅压Vg。
双电源供电的单刀双掷开关的两路输入信号分别是栅压Vg和OUT引脚输出的-5V电压，双电源供电的单刀双掷开关的控制端接使能信号，双电源供电的单刀双掷开关的输出信号接GaN功率器件40的栅极，该使能信号控制双电源供电的单刀双掷开关的接通加法器单元或LTC1261芯片的OUT引脚，从而控制GaN功率器件40的栅极接通加法器子单元52或LTC1261系列芯片的OUT引脚。
推挽电路子单元21的输出端接GaN功率器件40的漏极，为GaN功率器件40在工作状态下提供正常工作的漏极电压，以及在GaN功率器件40下电或上电的时候使得GaN功率器件40的漏极连接公共端，从而确保GaN功率器件40的漏极不会被烧坏。
如图9所示，逻辑门子单元22和双电源供电的单刀双掷开关中的使能信号可以由数字板提供的TTL电平，该使能信号与负压检测指示信号通过逻辑门子单元22输出两路互补的时序信号来控制推电路子单元中的PMOS管和NMOS管。例如，在GaN功率器件40正常工作时，可以控制PMOS管导通的同时控制NMOS管断开，从而确保GaN功率器件40的漏极的电压加载正常，以及在GaN功率器件40上电或下电时，还可以控制PMOS管截止的同时控制NMOS管导通，从而确保GaN功率器件40的漏极的电压压通过NMOS对地快速放电。
LTC1261可通过调整电阻R1和R2来设置OUT引脚输出的负电压的大小，同时还能够输出一个负压检测指示信号，该负压检测指示信号可以在OUT引脚输出的负电压的幅值未达到预设幅值的95％之前，维持高电平，直到OUT引脚输出的负电压的幅值达到了预设幅值的95％时，负压检测指示信号会从高电平翻转到低电平。
对于GaN功率器件40的上电时序而言，当GaN功率器件40上电时，负压检测指示信号在刚上电瞬间会在内部产生一个高电平，此时即使GaN功率器件40的漏极已经接通推挽电路子单元21的电源VDD，但是经过具有第一级NPN型三极管和第二级NPN型三极管的逻辑门子电源，来控制GaN功率器件40漏极的开关PMOS管处于截止状态，所以此时GaN功率器件40的漏极没有电压，其中，负压检测指示信号维持高电平的时间约为250us，所以在上电时序过程，该GaN功率器件40的保护电路起到了保护GaN功率器件40不被烧坏。
当GaN功率器件40下电时，负压检测指示信号的电平从0立刻拉到高电平，由于栅极电压切换单元的控制只受使能信号的控制，仍然保持下电前的状态，且GaN功率器件40的漏极电压的开关PMOS管，经过逻辑子门单元控制该PMOS管处于截止状态也下电，同时逻辑门子单元22控制NMOS管导通，让GaN功率器件40的漏极连接公共端，从而使得GaN 功率器件40的漏极的电压释放到地面，GaN功率器件40的栅极的电压从掉电前的电压逐渐降到0，且在栅极电压降到0之前该GaN功率器件40的漏极电压早已到0了，从而确保了在掉电过程中GaN功率器件40也不会被烧坏。
使能信号也是双电源单刀双掷开关的控制信号。当使能信号为高电平时，控制该双电源单刀双掷开关打向与加法器子单元52输出端连接的一端，当使能信号为低电平时，控制该双电源单刀双掷开关打向与引脚输出的-5V端连接的一端，双电源单刀双掷开关的响应速度在100ns以内。上述使能信号与推挽电路子单元21、逻辑门子单元22和双电源单刀双掷开关之间的合理配合，能够安全确保GaN功率器件40在漏压加载之前栅极电压已经加载了，不损坏GaN功率器件40的安全负压。如图10所示，在t0时刻GaN功率器件40的保护电路开始掉电，其GaN功率器件的漏极电压瞬间连接公共端，使得漏极电压瞬间释放，而栅极电压缓慢降低，且仍然为不损坏GaN功率器件的安全负压，实现了GaN功率器件40的保护电路在掉电时对GaN功率器件40的保护。并且在本实施例中双电源单刀双掷开关确保GaN功率器件40的栅极电压无论在任何情况下都在正常的设置值栅压和-5V之间，还能够保证在误操作的情况下也不会烧坏GaN功率器件40。
综上所述，通过本申请提供的GaN功率器件的保护电路，在GaN功率器件上下电或者GaN功率器件的保护电路掉电的情况下，都能够实现保护功能；并且，采用本申请实施例的GaN功率器件的保护电路，用户无需关心GaN功率器件的栅极和漏极的上电顺序，而直接使用使能信号来控制GaN功率器件的上下电操作，因此从用户的角度来看，采用本申请实施例提供的GaN功率器件的保护电路可以使得GaN功率器件的上下电操作与传统的LDMOS管的上下电操作相同。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (11)

  1. 一种GaN功率器件的保护电路，所述GaN功率器件的保护电路包括负压生成单元、栅极电压切换单元和漏极电压切换单元；所述负压生成单元、所述栅极电压切换单元和所述漏极电压切换单元分别与所述GaN功率器件的保护电路的第一供电电源连接；所述负压生成单元包括负压转换子单元和负压比较子单元，所述负压转换子单元用于将所述第一供电电源转换为栅极保护电压，并将所述栅极保护电压提供给所述栅极电压切换单元；所述负压比较子单元用于在所述栅极保护电压的幅值低于预设幅值的情况下输出漏极电压关断信号；其特征在于，所述漏极电压切换单元包括：推挽电路子单元，其中，所述推挽电路子单元分别连接至所述负压比较子单元的输出端、公共端、所述GaN功率器件的漏极以及所述GaN功率器件的漏极的第二供电电源；所述推挽电路子单元用于根据所述漏极电压关断信号将所述GaN功率器件的漏极与所述公共端导通。
  2. 根据权利要求1所述的GaN功率器件的保护电路，其特征在于，所述漏极电压切换单元还包括：逻辑门子单元，所述逻辑门子单元连接至所述负压比较子单元的输出端和所述推挽电路子单元的输入端之间；所述逻辑门子单元用于根据所述漏极电压关断信号生成第一控制信号，所述第一控制信号用于控制所述推挽电路子单元将所述GaN功率器件的漏极与所述公共端导通。
  3. 根据权利要求2所述的GaN功率器件的保护电路，其特征在于，所述推挽电路子单元还用于在所述栅极保护电压的幅值高于预设幅值的情况下，根据第二控制信号将所述GaN功率器件的漏极上电或者下电；所述逻辑门子单元还用于在所述栅极保护电压的幅值高于预设幅值的情况下，根据使能信号生成所述第二控制信号，所述第二控制信号用于控制所述推挽电路子单元将所述GaN功率器件的漏极上电或下电。
  4. 根据权利要求3所述的GaN功率器件的保护电路，其特征在于，所述逻辑门子单元包括第一开关管、第二开关管、逻辑与门、逻辑非门、第一电阻、第二电阻和第三电阻，其中，所述第一开关管的输入端、所述逻辑与门的第一输入端和所述逻辑非门的输入端均通过所述第一电阻连接至所述第一供电电源；所述第二开关管的输入端通过所述第二电阻连接至所述第一供电电源，所述第二开关管的输入端还连接至所述推挽电路子单元的第一输入端；所述第一开关管的控制端通过所述第三电阻连接至所述负压比较子单元；所述第一开关管的输出端、所述第二开关管的输出端均连接至公共端；所述逻辑非门的输出端连接至所述推挽电路子单元的第二输入端；所述逻辑与门的第二输入端用于接收所述使能信号，所述逻辑与门的输出端连接至所述第二开关管的控制端。
  5. 根据权利要求1所述的GaN功率器件的保护电路，其特征在于，所述推挽电路子单元 包括第四电阻、第五电阻、第六电阻、以及两个极性相反的第三开关管和第四开关管，其中，所述第三开关管的输入端连接至所述第二供电电源，所述第三开关管的控制端连接至所述推挽电路子单元的第一输入端；所述第四电阻连接在所述第三开关管的控制端和所述第二供电电源之间；所述第五电阻连接在所述推挽电路子单元的第二输入端和所述第四开关管的控制端之间；所述第三开关管的输出端和所述第四开关管的输入端均连接至所述GaN功率器件的漏极；所述第四开关管的输出端通过所述第六电阻连接公共端，且所述第四开关管的衬底连接公共端。
  6. 根据权利要求1所述的GaN功率器件的保护电路，其特征在于，所述栅极电压切换单元由所述第一供电电源和所述栅极保护电压双电源供电；所述栅极电压切换单元包括栅极驱动电压输入端、栅极保护电压输入端、使能信号输入端和栅极电压输出端；所述栅极驱动电压输入端连接栅极驱动单元的输出端，所述栅极保护电压输入端连接所述负压转换子单元的输出端，所述使能信号输入端用于接收使能信号，所述栅极电压输出端连接所述GaN功率器件的栅极；所述栅极电压切换单元用于根据所述使能信号将所述栅极驱动单元生成的栅极驱动电压或者所述负压转换子单元生成的所述栅极保护电压提供给所述GaN功率器件的栅极。
  7. 根据权利要求1所述的GaN功率器件的保护电路，其特征在于，所述GaN功率器件的保护电路还包括：栅极驱动单元，所述栅极驱动单元用于生成所述GaN功率器件的栅极驱动电压。
  8. 根据权利要求7所述的GaN功率器件的保护电路，其特征在于，所述栅极驱动单元包括栅极驱动子单元和加法器子单元，所述加法器子单元由所述第一供电电源和所述栅极保护电压双电源供电；其中，所述栅极驱动子单元用于生成栅极控制电压；所述加法器子单元用于将所述负压转换子单元输出的栅极保护电压与所述栅极控制电压累加，得到所述栅极驱动电压。
  9. 根据权利要求8所述的GaN功率器件的保护电路，其特征在于，所述加法器子单元包括：第七电阻、第八电阻、第九电阻、第十电阻和运算放大器，其中，所述运算放大器的输出端连接至所述栅极电压切换单元，所述运算放大器的输出端还通过所述第十电阻和所述第九电阻连接至公共端；所述运算放大器的反相输入端连接至所述第十电阻和所述第九电阻的连接结点；所述运算放大器的正相输入端通过所述第七电阻连接至所述栅极驱动子单元，以及通过所述第八电阻连接至所述负压转换子单元的输出端；所述运算放大器的正电源端连接至所述第一供电电源，所述运算放大器的负电源端连接至所述负压转换子单元的输出端。
  10. 根据权利要求1至9中任一项所述的GaN功率器件的保护电路，其特征在于，所述GaN功率器件包括：增强型GaN高电子迁移率晶体管或耗尽型GaN高电子迁移率晶体管。
  11. 根据权利要求1至9中任一项所述的GaN功率器件的保护电路，其特征在于，所述负压生成单元包括：LTC 1261系列芯片。
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