WO2021134527A1

WO2021134527A1 - Rate adjustment device and method

Info

Publication number: WO2021134527A1
Application number: PCT/CN2019/130666
Authority: WO
Inventors: 巫上清
Original assignee: 华为技术有限公司
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2021-07-08
Also published as: CN114762274A; CN114762274B

Abstract

Disclosed are a rate adjustment device and method, which relate to the field of communications, and are used to reduce the fluctuation of a data transmission rate during the process of rate adjustment. The rate adjustment device comprises: a first input memory, a first idle code block processing core and a first control core, wherein the first input memory is used for receiving a first data stream and a second data stream successively; the first idle code block processing core is used for adding or deleting idle code blocks with a first number of bits in the first data stream according to a first cache occupancy amount sent by the first control core; the first control core is used for obtaining a second cache occupancy amount according to the first cache occupancy amount, a payload bandwidth of the second data stream at an input port, a payload bandwidth of the second data stream at an output port, and the first number of bits; and the first idle code block processing core is further used for adding or deleting idle code blocks in the second data stream according to the second cache occupancy amount.

Description

速率调节装置和方法Rate adjustment device and method

技术领域Technical field

本申请涉及通信领域，尤其涉及一种速率调节装置和方法。This application relates to the field of communications, and in particular to a rate adjustment device and method.

背景技术Background technique

随着通信网络中存在越来越多的分布式***，需要多个通信设备实现时间同步。为了实现高精度时间同步，1588协议标准(网络测量和控制***的精密时钟同步协议标准)应运而生，可以实现以太网(Ethernet)或灵活以太网(flex Ethernet，FLEXE)中的通信装置之间的时钟的亚微秒级同步。As more and more distributed systems exist in communication networks, multiple communication devices are required to achieve time synchronization. In order to achieve high-precision time synchronization, the 1588 protocol standard (precision clock synchronization protocol standard for network measurement and control systems) came into being, which can realize communication between communication devices in Ethernet (Ethernet) or flexible Ethernet (FLEXE) The sub-microsecond synchronization of the clock.

如图1所示，采用1588协议通信的双方分别是第一通信装置11和第二通信装置12，第一通信装置11与第二通信装置12通过在数据包中打入时间戳信息，并根据接收到来自对端的时间戳信息来计算传输时延，进而实现时钟同步。在第一通信装置11与第二通信装置12之间常常要经过速率调节装置13，速率调节装置13可以通过增删空闲(idle)码块的方式对网络中数据的传输速率进行调节。在调节过程中会造成数据传输速率产生波动，使得时间戳信息传输时延产生波动，从而降低了第一通信装置11与第二通信装置12之间的时钟同步精度。As shown in Figure 1, the two parties that use the 1588 protocol to communicate are the first communication device 11 and the second communication device 12 respectively. The first communication device 11 and the second communication device 12 enter the time stamp information in the data packet, and according to Receive the time stamp information from the opposite end to calculate the transmission delay, and then realize the clock synchronization. The rate adjustment device 13 is often passed between the first communication device 11 and the second communication device 12, and the rate adjustment device 13 can adjust the data transmission rate in the network by adding and deleting idle code blocks. During the adjustment process, the data transmission rate will fluctuate, and the time-stamp information transmission delay will fluctuate, thereby reducing the accuracy of clock synchronization between the first communication device 11 and the second communication device 12.

发明内容Summary of the invention

本申请实施例提供一种速率调节装置和方法，用于减少速率调节过程中数据传输速率的波动。The embodiments of the present application provide a rate adjustment device and method, which are used to reduce the fluctuation of the data transmission rate during the rate adjustment process.

为达到上述目的，本申请的实施例采用如下技术方案：In order to achieve the foregoing objectives, the following technical solutions are adopted in the embodiments of the present application:

第一方面，提供了一种速率调节装置，包括：第一输入存储器、第一空闲码块处理核和第一控制核，第一输入存储器，用于先后接收第一数据流和第二数据流；第一空闲码块处理核，用于根据第一控制核发送的第一缓存占用量，在第一数据流中增加或删除第一比特数的空闲码块；第一控制核，用于根据第一缓存占用量、第二数据流在输入端口的净荷带宽、第二数据流在输出端口的净荷带宽、第一比特数，获得第二缓存占用量；第一空闲码块处理核，还用于根据第二缓存占用量，在第二数据流中增加或删除空闲码块。In a first aspect, a rate adjustment device is provided, including: a first input memory, a first idle code block processing core, and a first control core, and the first input memory is configured to sequentially receive a first data stream and a second data stream The first idle code block processing core is used to add or delete the idle code block of the first number of bits in the first data stream according to the first buffer occupancy sent by the first control core; the first control core is used to add or delete idle code blocks of the first number of bits in the first data stream according to the The first buffer occupancy, the payload bandwidth of the second data stream at the input port, the payload bandwidth of the second data stream at the output port, and the first number of bits to obtain the second cache occupancy; the first idle code block processing core, It is also used to add or delete idle code blocks in the second data stream according to the occupancy of the second buffer.

本申请实施例提供的速率调节装置，根据第一数据流的缓存占用量、第二数据流在输入端口的净荷带宽、第二数据流在输出端口的净荷带宽、第一空闲码块处理核增加或删除的空闲码块的比特数，获得第二缓存占用量。根据第二缓存占用量增加或删除空闲码块。也就是说，通过负反馈机制，以比特位的精度来精确地对空闲码块进行增加或删除，从而精确调节数据流的传输速率，减少数据流传输的抖动，提高时钟同步的精度。该速率调节方式不受可以抵消数据流中对FEC、AM进行增加或删除，或者，其他数据流调度引入的延迟抖动的影响。The rate adjustment device provided by the embodiment of the present application processes according to the buffer occupancy of the first data stream, the payload bandwidth of the second data stream at the input port, the payload bandwidth of the second data stream at the output port, and the first free code block processing The number of bits of the idle code block added or deleted by the core obtains the second buffer occupancy. Increase or delete free code blocks according to the second buffer occupancy. That is to say, through the negative feedback mechanism, the idle code blocks are accurately added or deleted with the accuracy of the bits, so as to accurately adjust the transmission rate of the data stream, reduce the jitter of the data stream transmission, and improve the accuracy of clock synchronization. This rate adjustment method is not affected by the addition or deletion of FEC and AM in the data stream, or the delay jitter introduced by other data stream scheduling.

在一种可能的实施方式中，第一控制核包括：第一速率匹配子核，用于获取第二数据流在输入端口的总带宽，并根据第二数据流在输入端口的总带宽确定第二数据流在输入端口的净荷带宽。由于AM、FEC在以太协议中是固定间隔***的，其带宽与总带宽的比例是固定，使得去除AM、FEC后净荷带宽与总带宽的比例也是固定的，所以可以根据总带宽和该比例来计算净荷带宽。In a possible implementation manner, the first control core includes: a first rate matching sub-core, which is used to obtain the total bandwidth of the second data stream at the input port, and determine the second data stream according to the total bandwidth of the second data stream at the input port. The payload bandwidth of the two data streams at the input port. Since AM and FEC are inserted at fixed intervals in the Ethernet protocol, the ratio of their bandwidth to the total bandwidth is fixed, so that after removing AM and FEC, the ratio of the payload bandwidth to the total bandwidth is also fixed, so it can be based on the total bandwidth and the ratio To calculate the payload bandwidth.

在一种可能的实施方式中，第一控制核包括：第二速率匹配子核，用于获取第二数据流在输出端口的总带宽，并根据第二数据流在输出端口的总带宽确定第二数据流在输出端口的净荷带宽。由于AM、FEC在以太协议中是固定间隔***的，其带宽与总带宽的比例是固定，使得去除AM、FEC后净荷带宽与总带宽的比例也是固定的，所以可以根据总带宽和该比例来计算净荷带宽。In a possible implementation, the first control core includes: a second rate matching sub-core, which is used to obtain the total bandwidth of the second data stream at the output port, and determine the second data stream according to the total bandwidth of the second data stream at the output port. The payload bandwidth of the two data streams at the output port. Since AM and FEC are inserted at fixed intervals in the Ethernet protocol, the ratio of their bandwidth to the total bandwidth is fixed, so that after removing AM and FEC, the ratio of the payload bandwidth to the total bandwidth is also fixed, so it can be based on the total bandwidth and the ratio To calculate the payload bandwidth.

在一种可能的实施方式中，第一控制核还包括第三速率匹配子核，用于根据以太网带宽与FLEXE带宽之间的比例对第二数据流在输出端口的净荷带宽进行修正。由于以太网带宽与FLEXE带宽的带宽不同，通过修正可以将FLEXE带宽统一为以太网带宽。In a possible implementation manner, the first control core further includes a third rate matching sub-core for correcting the payload bandwidth of the second data stream at the output port according to the ratio between the Ethernet bandwidth and the FLEXE bandwidth. Since the Ethernet bandwidth is different from the FLEXE bandwidth, the FLEXE bandwidth can be unified into the Ethernet bandwidth through correction.

在一种可能的实施方式中，还包括：第二输入存储器、第二空闲码块处理核和第二控制核，第二输入存储器，用于先后接收第三数据流和第四数据流；第二空闲码块处理核，用于根据第二控制核发送的第三缓存占用量，在第三数据流中增加或删除第二比特数的空闲码块；第二控制核，用于根据第三缓存占用量、第四数据流在输入端口的净荷带宽、第四数据流在输出端口的净荷带宽、第二比特数，获得第四缓存占用量；第二空闲码块处理核，还用于根据第四缓存占用量，在第四数据流中增加或删除空闲码块；其中，第三数据流和第四数据流的流向与第一数据流和第二数据流的流向相反。即可以对双向数据流进行速率调节。In a possible implementation manner, it further includes: a second input memory, a second idle code block processing core, and a second control core. The second input memory is configured to sequentially receive the third data stream and the fourth data stream; Two idle code block processing cores are used to add or delete idle code blocks with the second number of bits in the third data stream according to the third buffer occupancy sent by the second control core; the second control core is used to add or delete idle code blocks with the second number of bits in the third data stream; Cache occupancy, the payload bandwidth of the fourth data stream at the input port, the payload bandwidth of the fourth data stream at the output port, and the second number of bits to obtain the fourth cache occupancy; the second free code block processing core also uses According to the fourth buffer occupancy, idle code blocks are added or deleted in the fourth data stream; wherein, the flow directions of the third data stream and the fourth data stream are opposite to the flow directions of the first data stream and the second data stream. That is, the rate of the two-way data stream can be adjusted.

在一种可能的实施方式中，第二控制核包括：第四速率匹配子核，用于获取第四数据流在输入端口的总带宽，并根据第四数据流在输入端口的总带宽确定第四数据流在输入端口的净荷带宽。由于AM、FEC在以太协议中是固定间隔***的，其带宽与总带宽的比例是固定，使得去除AM、FEC后净荷带宽与总带宽的比例也是固定的，所以可以根据总带宽和该比例来计算净荷带宽。In a possible implementation manner, the second control core includes: a fourth rate matching sub-core, which is used to obtain the total bandwidth of the fourth data stream at the input port, and determine the second control core according to the total bandwidth of the fourth data stream at the input port. The payload bandwidth of the four data streams at the input port. Since AM and FEC are inserted at fixed intervals in the Ethernet protocol, the ratio of their bandwidth to the total bandwidth is fixed, so that after removing AM and FEC, the ratio of the payload bandwidth to the total bandwidth is also fixed, so it can be based on the total bandwidth and the ratio To calculate the payload bandwidth.

在一种可能的实施方式中，第二控制核包括：第五速率匹配子核，用于获取第四数据流在输出端口的总带宽，并根据第四数据流在输出端口的总带宽确定第四数据流在输出端口的净荷带宽。由于AM、FEC在以太协议中是固定间隔***的，其带宽与总带宽的比例是固定，使得去除AM、FEC后净荷带宽与总带宽的比例也是固定的，所以可以根据总带宽和该比例来计算净荷带宽。In a possible implementation manner, the second control core includes: a fifth rate matching sub-core, which is used to obtain the total bandwidth of the fourth data stream at the output port, and determine the second control core according to the total bandwidth of the fourth data stream at the output port. The payload bandwidth of the four data streams at the output port. Since AM and FEC are inserted at fixed intervals in the Ethernet protocol, the ratio of their bandwidth to the total bandwidth is fixed, so that after removing AM and FEC, the ratio of the payload bandwidth to the total bandwidth is also fixed, so it can be based on the total bandwidth and the ratio To calculate the payload bandwidth.

在一种可能的实施方式中，第二控制核还包括第六速率匹配子核，用于根据以太网带宽与FLEXE带宽之间的比例对第四数据流在输入端口的净荷带宽进行修正。由于以太网带宽与FLEXE带宽的带宽不同，通过修正可以将FLEXE带宽统一为以太网带宽。In a possible implementation manner, the second control core further includes a sixth rate matching sub-core for correcting the payload bandwidth of the fourth data stream at the input port according to the ratio between the Ethernet bandwidth and the FLEXE bandwidth. Since the Ethernet bandwidth is different from the FLEXE bandwidth, the FLEXE bandwidth can be unified into the Ethernet bandwidth through correction.

第二方面，提供了一种速率调节方法，其特征在于，包括：先后接收第一数据流和第二数据流；根据第一缓存占用量，在第一数据流中增加或删除第一比特数的空闲码块；根据第一缓存占用量、第二数据流在输入端口的净荷带宽、第二数据流在输出端口的净荷带宽、第一比特数，获得第二缓存占用量；根据第二缓存占用量，在第二数据流中增加或删除空闲码块。In a second aspect, a rate adjustment method is provided, which is characterized in that it includes: sequentially receiving a first data stream and a second data stream; adding or deleting the first bit number in the first data stream according to the occupancy of the first buffer According to the idle code block of the first buffer, the payload bandwidth of the second data stream at the input port, the payload bandwidth of the second data stream at the output port, and the first number of bits, the second buffer occupancy is obtained; according to the first Second, the amount of buffer occupation, adding or deleting free code blocks in the second data stream.

在一种可能的实施方式中，该方法还包括：获取第二数据流在输入端口的总带宽，并根据第二数据流在输入端口的总带宽确定第二数据流在输入端口的净荷带宽。In a possible implementation manner, the method further includes: obtaining the total bandwidth of the second data stream at the input port, and determining the payload bandwidth of the second data stream at the input port according to the total bandwidth of the second data stream at the input port .

在一种可能的实施方式中，该方法还包括：获取第二数据流在输出端口的总带宽，并根据第二数据流在输出端口的总带宽确定第二数据流在输出端口的净荷带宽。In a possible implementation manner, the method further includes: obtaining the total bandwidth of the second data stream at the output port, and determining the payload bandwidth of the second data stream at the output port according to the total bandwidth of the second data stream at the output port .

在一种可能的实施方式中，该方法还包括：根据以太网带宽与FLEXE带宽之间的比例对第二数据流在输出端口的净荷带宽进行修正。In a possible implementation manner, the method further includes: correcting the payload bandwidth of the second data stream at the output port according to the ratio between the Ethernet bandwidth and the FLEXE bandwidth.

在一种可能的实施方式中，该方法还包括：先后接收第三数据流和第四数据流；根据第三缓存占用量，在第三数据流中增加或删除第二比特数的空闲码块；根据第三缓存占用量、第四数据流在输入端口的净荷带宽、第四数据流在输出端口的净荷带宽、第二比特数，获得第四缓存占用量；根据第四缓存占用量，在第四数据流中增加或删除空闲码块；其中，第三数据流和第四数据流的流向与第一数据流和第二数据流的流向相反。In a possible implementation manner, the method further includes: successively receiving a third data stream and a fourth data stream; according to the third buffer occupancy, adding or deleting idle code blocks with the second number of bits in the third data stream ; According to the third buffer occupancy, the fourth data stream's payload bandwidth at the input port, the fourth data stream's payload bandwidth at the output port, and the second number of bits, obtain the fourth cache occupancy; according to the fourth cache occupancy , Add or delete idle code blocks in the fourth data stream; wherein, the flow directions of the third data stream and the fourth data stream are opposite to those of the first data stream and the second data stream.

在一种可能的实施方式中，该方法还包括：获取第四数据流在输入端口的总带宽，并根据第四数据流在输入端口的总带宽确定第四数据流在输入端口的净荷带宽。In a possible implementation manner, the method further includes: obtaining the total bandwidth of the fourth data stream at the input port, and determining the payload bandwidth of the fourth data stream at the input port according to the total bandwidth of the fourth data stream at the input port .

在一种可能的实施方式中，该方法还包括：获取第四数据流在输出端口的总带宽，并根据第四数据流在输出端口的总带宽确定第四数据流在输出端口的净荷带宽。In a possible implementation manner, the method further includes: obtaining the total bandwidth of the fourth data stream at the output port, and determining the payload bandwidth of the fourth data stream at the output port according to the total bandwidth of the fourth data stream at the output port .

在一种可能的实施方式中，该方法还包括：根据以太网带宽与FLEXE带宽之间的比例对第四数据流在输入端口的净荷带宽进行修正。In a possible implementation manner, the method further includes: correcting the payload bandwidth of the fourth data stream at the input port according to the ratio between the Ethernet bandwidth and the FLEXE bandwidth.

第二方面及其任一实施方式的技术效果可以参照第一方面及其任一实施方式的技术效果。For the technical effects of the second aspect and any of its embodiments, reference may be made to the technical effects of the first aspect and any of its embodiments.

附图说明Description of the drawings

图1为本申请实施例提供的一种通信***的架构示意图；FIG. 1 is a schematic diagram of the architecture of a communication system provided by an embodiment of this application;

图2为本申请实施例提供的一种根据1588协议进行时钟同步的过程的示意图；2 is a schematic diagram of a process of clock synchronization according to the 1588 protocol provided by an embodiment of the application;

图3为本申请实施例提供的一种速率调节装置的结构示意图；FIG. 3 is a schematic structural diagram of a rate adjustment device provided by an embodiment of the application;

图4为本申请实施例提供的另一种速率调节装置的结构示意图；4 is a schematic structural diagram of another rate adjustment device provided by an embodiment of the application;

图5为本申请实施例提供的一种速率调节方法的流程示意图；FIG. 5 is a schematic flowchart of a rate adjustment method provided by an embodiment of this application;

图6为本申请实施例提供的又一种速率调节装置的结构示意图。FIG. 6 is a schematic structural diagram of another rate adjustment device provided by an embodiment of the application.

具体实施方式Detailed ways

如本申请所使用的，术语“组件”、“模块”、“***”等等旨在指代计算机相关实体，该计算机相关实体可以是硬件、固件、硬件和软件的结合、软件或者运行中的软件。例如，组件可以是，但不限于是：在处理器上运行的处理、处理器、对象、可执行文件、执行中的线程、程序和/或计算机。作为示例，在计算设备上运行的应用和该计算设备都可以是组件。一个或多个组件可以存在于执行中的过程和/或线程中，并且组件可以位于一个计算机中以及/或者分布在两个或更多个计算机之间。此外，这些组件能够从在其上具有各种数据结构的各种计算机可读介质中执行。这些组件可以通过诸如根据具有一个或多个数据分组(例如，来自一个组件的数据，该组件与本地***、分布式***中的另一个组件进行交互和/或以信号的方式通过诸如互联网之类的网络与其它***进行交互)的信号，以本地和/或远程过程的方式进行通信。As used in this application, the terms "component", "module", "system", etc. are intended to refer to a computer-related entity, which can be hardware, firmware, a combination of hardware and software, software, or running software. software. For example, a component may be, but is not limited to: a process running on a processor, a processor, an object, an executable file, an executing thread, a program, and/or a computer. As an example, both an application running on a computing device and the computing device may be components. One or more components may exist in an executing process and/or thread, and the components may be located in one computer and/or distributed between two or more computers. In addition, these components can execute from various computer-readable media having various data structures thereon. These components can be based on, for example, having one or more data packets (for example, data from a component that interacts with another component in a local system, a distributed system, and/or via signals such as the Internet). The network interacts with other systems) signals to communicate in a local and/or remote process.

本申请将围绕可包括多个设备、组件、模块等的***来呈现各个方面、实施例或特征。应当理解和明白的是，各个***可以包括另外的设备、组件、模块等，并且/或者可以并不包括结合附图讨论的所有设备、组件、模块等。此外，还可以使用这些方案的组合。This application will present various aspects, embodiments, or features around a system that may include multiple devices, components, modules, and the like. It should be understood and understood that each system may include additional devices, components, modules, etc., and/or may not include all the devices, components, modules, etc. discussed in conjunction with the accompanying drawings. In addition, a combination of these schemes can also be used.

另外，在本申请实施例中，“示例的”一词用于表示作例子、例证或说明。本申请中被描述为“示例”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用示例的一词旨在以具体方式呈现概念。In addition, in the embodiments of the present application, the word "exemplary" is used to mean serving as an example, illustration, or illustration. Any embodiment or design solution described as an "example" in this application should not be construed as being more preferable or advantageous than other embodiments or design solutions. Rather, the term example is used to present the concept in a concrete way.

本申请实施例中，信息(information)，信号(signal)，消息(message)，信道(channel)有时可以混用，应当指出的是，在不强调其区别时，其所要表达的含义是一致的。“的(of)”，“相应的(corresponding，relevant)”和“对应的(corresponding)”有时可以混用，应当指出的是，在不强调其区别时，其所要表达的含义是一致的。In the embodiments of the present application, information, signal, message, and channel can sometimes be used together. It should be noted that the meanings to be expressed are the same when the differences are not emphasized. "的 (of)", "corresponding (relevant)" and "corresponding (corresponding)" can sometimes be used together. It should be pointed out that the meanings to be expressed are the same when the difference is not emphasized.

本申请实施例描述的网络架构以及业务场景是为了更加清楚的说明本申请实施例的技术方案，并不构成对于本申请实施例提供的技术方案的限定，本领域普通技术人员可知，随着网络架构的演变和新业务场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。The network architecture and business scenarios described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. Those of ordinary skill in the art will know that with the network With the evolution of architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

本申请实施例提供了一种通信***，该通信***可以应用于不同以太网中的通信装置之间的速率调节和时钟同步，也可以应用于以太网中的通信装置与灵活以太网(flex Ethernet，FLEXE)中的通信装置之间的速率调节和时钟同步。The embodiments of the present application provide a communication system, which can be applied to rate adjustment and clock synchronization between communication devices in different Ethernets, and can also be applied to communication devices in Ethernet and flexible Ethernet (flex Ethernet). , FLEXE) rate adjustment and clock synchronization between communication devices.

如图1所示，该通信***包括：第一通信装置11、第二通信装置12和速率调节装置13。As shown in FIG. 1, the communication system includes: a first communication device 11, a second communication device 12 and a rate adjustment device 13.

示例性的，第一通信装置11可以为第一以太网中的通信装置，第二通信装置12可以为第二以太网中的通信装置。或者，第一通信装置11可以为以太网中的通信装置，第二通信装置12可以为FLEXE中的通信装置。或者，第一通信装置11可以为FLEXE中的通信装置，第二通信装置12可以为以太网的通信装置。对于后面两种情况，速率调节装置13可以将传输的数据中的以太网端口映射为FLEXE接口，或者，将传输的数据中的FLEXE接口映射为以太网端口。Exemplarily, the first communication device 11 may be a communication device in a first Ethernet, and the second communication device 12 may be a communication device in a second Ethernet. Alternatively, the first communication device 11 may be a communication device in Ethernet, and the second communication device 12 may be a communication device in FLEXE. Alternatively, the first communication device 11 may be a communication device in FLEXE, and the second communication device 12 may be an Ethernet communication device. For the latter two cases, the rate adjusting device 13 may map the Ethernet port in the transmitted data to the FLEXE interface, or map the FLEXE interface in the transmitted data to the Ethernet port.

本申请实施例中，第一通信装置11也可以表示第一通信装置中的芯片(例如line chip)，第二通信装置12也可以表示第二通信装置中的芯片(例如host chip)，速率调节装置13也可以表示速率调节装置中的调制解调芯片(例如mux/demux chip)，本申请不作限定。In the embodiment of the present application, the first communication device 11 may also refer to a chip in the first communication device (for example, a line chip), and the second communication device 12 may also indicate a chip in a second communication device (for example, a host chip), and the rate is adjusted. The device 13 may also represent a modem chip (such as a mux/demux chip) in a rate adjustment device, which is not limited in this application.

第一通信装置11和第二通信装置可以根据时钟同步协议(例如1588协议)进行时钟同步。速率调节装置13可以通过增删空闲(idle)码块的方式，调节第一通信装置11和第二通信装置之间传输的数据的传输速率，使该传输速率保持恒定。由于时钟同步协议的时间戳也是通过携带在数据中的，所以数据的传输速率恒定可以提高第一通信装置11和第二通信装置之间时钟同步的精度。The first communication device 11 and the second communication device may perform clock synchronization according to a clock synchronization protocol (for example, the 1588 protocol). The rate adjustment device 13 can adjust the transmission rate of the data transmitted between the first communication device 11 and the second communication device by adding or deleting idle code blocks, so that the transmission rate is kept constant. Since the time stamp of the clock synchronization protocol is also carried in the data, a constant data transmission rate can improve the accuracy of clock synchronization between the first communication device 11 and the second communication device.

本申请以1588协议为例对时钟同步的过程进行说明：This application uses the 1588 protocol as an example to describe the clock synchronization process:

在根据1588协议进行时钟同步的通信***中包括主通信设备和从通信设备，主通信设备周期性发布时间戳信息，从通信设备接收时间戳信息后，根据时间戳信息计算出主通信设备与从通信设备之间的传输时延以及时间差，并根据该时间差调整从通信设备的时钟，实现主通信设备与从通信设备之间的时钟同步。A communication system that performs clock synchronization according to the 1588 protocol includes a master communication device and a slave communication device. The master communication device periodically publishes time stamp information. After receiving the time stamp information from the communication device, the master communication device and the slave communication device are calculated based on the time stamp information. The transmission time delay and time difference between the communication devices, and the clock of the slave communication device is adjusted according to the time difference, so as to realize the clock synchronization between the master communication device and the slave communication device.

假设从主通信设备至从通信设备之间的传输时延与从通信设备至主通信装置之间的传输时延相同，如图2所示，根据1588协议进行时钟同步的过程包括：Assuming that the transmission delay from the master communication device to the slave communication device is the same as the transmission delay between the slave communication device and the master communication device, as shown in Figure 2, the process of clock synchronization according to the 1588 protocol includes:

S201、主通信设备向从通信设备发送同步(Sync)报文，并记录发送同步报文的时间戳T1。S201: The master communication device sends a synchronization (Sync) message to the slave communication device, and records the time stamp T1 of sending the synchronization message.

S202、从通信设备接收到同步报文，并记录接收到同步报文的时间戳T2。S202. Receive a synchronization message from the communication device, and record the time stamp T2 of the received synchronization message.

S203、主通信设备向从通信设备发送跟随(Follow_Up)报文，跟随(Follow_Up)报文中携带时间戳T1。S203: The master communication device sends a follow (Follow_Up) message to the slave communication device, and the follow (Follow_Up) message carries a timestamp T1.

S204、从通信设备向主通信设备发送延时请求(Delay_Req)报文，延时请求报文中携带时间戳T3。S204. The slave communication device sends a delay request (Delay_Req) message to the master communication device, and the delay request message carries a time stamp T3.

时间戳T3为从通信设备发送延时请求报文的时间。The time stamp T3 is the time when the delay request message is sent from the communication device.

S205、主通信设备接收到延时请求报文，并记录接收到延时请求报文的时间戳T4。S205: The master communication device receives the delay request message, and records the time stamp T4 of the delay request message received.

S206、主通信设备向从通信设备发送延时应答(Delay_Resp)报文，延时应答报文中携带时间戳T4。S206: The master communication device sends a delay response (Delay_Resp) message to the slave communication device, and the delay response message carries a time stamp T4.

时间戳T4为主通信设备接收到延时请求报文的时间。The time stamp T4 is the time when the main communication device receives the delay request message.

S207、从通信设备计算主通信设备与从通信设备之间(即从通信设备与主通信设备之间)的传输时延和时间差。S207. The slave communication device calculates the transmission delay and time difference between the master communication device and the slave communication device (that is, between the slave communication device and the master communication device).

主通信设备与从通信设备之间(即从通信设备与主通信设备之间)的传输时延为：The transmission delay between the master communication device and the slave communication device (that is, between the slave communication device and the master communication device) is:

主通信设备与从通信设备之间(即从通信设备与主通信设备之间)的时间差为：The time difference between the master communication device and the slave communication device (that is, between the slave communication device and the master communication device) is:

Offset＝T ₂-T ₁-Delay 公式2 Offset=T ₂ -T ₁ -Delay Formula 2

根据上述传输时延和时间差，从通信装置可以修正本地时钟，从而实现与主通信装置之间的时钟同步。According to the above-mentioned transmission delay and time difference, the slave communication device can correct the local clock, thereby achieving clock synchronization with the master communication device.

示例性的，对于第一通信装置11为以太网中的主通信装置，第二通信装置12为FLEXE中的从通信装置来说，主通信装置的芯片(例如line chip)可以通过媒体访问控制(media access control，MAC)端口或物理介质连接(physical medium attachment，PMA)端口向传输的数据中打时间戳T1和T4。从通信装置的芯片(例如host chip)可以通过FLEXE接口向传输的数据中打时间戳T2和T3。Exemplarily, for the first communication device 11 as the master communication device in the Ethernet, and the second communication device 12 as the slave communication device in FLEXE, the chip of the master communication device (such as line chip) can be controlled through media access ( The media access control (MAC) port or the physical medium attachment (PMA) port timestamps T1 and T4 in the transmitted data. The chip of the slave communication device (such as the host chip) can time stamp T2 and T3 into the transmitted data through the FLEXE interface.

在本申请实施例中，涉及到串行器/解串器(serializer/deserializer，SERDES)、FLEXE、空闲码块、前向纠错(forward error correction，FEC)、对齐码块(alignment marker，AM)、开销(overhead，OH)等概念。下面对这些概念予以解释说明，但并不意在限定于此。In the embodiments of this application, serializer/deserializer (SERDES), FLEXE, idle code block, forward error correction (FEC), alignment marker (AM) are involved. ), overhead (OH) and other concepts. These concepts are explained below, but they are not intended to be limited thereto.

SERDES是一种主流的时分复用(time-division multiplexing，TDM)、点对点(point to point，P2P)的串行通信技术。即在发送端将多路低速并行信号转换成高速串行信号，经过传输媒体(光缆或铜线)，最后在接收端将高速串行信号重新转换成低速并行信号。这种串行通信技术充分利用传输媒体的信道容量，减少传输信道数量和器件引脚数量，提升数据的传输速度，大大降低通信成本。SERDES is a mainstream time-division multiplexing (TDM) and point-to-point (P2P) serial communication technology. That is, the multiple low-speed parallel signals are converted into high-speed serial signals at the transmitting end, and the high-speed serial signals are converted into low-speed parallel signals again at the receiving end through the transmission medium (optical cable or copper wire). This serial communication technology makes full use of the channel capacity of the transmission medium, reduces the number of transmission channels and the number of device pins, increases the data transmission speed, and greatly reduces the communication cost.

FLEXE是在以太网技术基础上，为满足调整传输、带宽配置灵活等需求而发展的技术。其与以太网相比具有以下特点：多粒度速率灵活可变，即相比于IEEE 802.3标准所确定的10-25-40-50-100-200-400GE的阶梯型速率体系，可提供更加灵活的带宽颗粒度。与光传输能力解耦，由于高速以太网接口组网时，经常受制于光传输能力，通过与光传输能力解耦，最大限度利用现有光传输网络实现对超大带宽以太网接口的传输和承载。IP与光融合组网，即可以通过将以太网与光传输网络之间的简单映射，简化网络，提高灵活性。面向多业务承载的增强服务质量(quality of service，QOS)能力，即在物理层接口上提供通道化的硬件隔离功能，在物理层保证业务基于不同分片的隔离，实现层次化QOS调度。FLEXE is a technology developed on the basis of Ethernet technology to meet the needs of adjusting transmission and flexible bandwidth configuration. Compared with Ethernet, it has the following characteristics: Multi-granularity rate is flexible and variable, that is, compared with the 10-25-40-50-100-200-400GE stepped rate system determined by the IEEE 802.3 standard, it can provide more flexibility The bandwidth granularity. Decoupling from the optical transmission capacity, because the high-speed Ethernet interface is often constrained by the optical transmission capacity when networking, through decoupling from the optical transmission capacity, the existing optical transmission network can be used to the maximum to realize the transmission and bearer of the ultra-large bandwidth Ethernet interface . The integration of IP and optical networking means that the network can be simplified and flexibility can be improved through simple mapping between Ethernet and optical transmission networks. The enhanced quality of service (QOS) capability for multi-service bearers means that channelized hardware isolation functions are provided on the physical layer interface, and the physical layer ensures the isolation of services based on different fragments to achieve hierarchical QOS scheduling.

以太网中的通信装置可以和FLEXE中的通信装置进行通信。由于以太网带宽相对于FLEXE带宽较小，一路FLEXE可以同时接入多路以太网，此时也可以称为散列场景，每个以太端口作为FLEXE的客户端(client)，对应FLEXE接口中承载的业务。从以太网至FLEXE的传输方向可以称为上行方向，从FLEXE至以太网的传输方向可以称为下行方向。The communication device in the Ethernet can communicate with the communication device in FLEXE. Since the Ethernet bandwidth is relatively small compared to the FLEXE bandwidth, one FLEXE can be connected to multiple Ethernet at the same time. At this time, it can also be called a hash scenario. Each Ethernet port acts as a FLEXE client (client), which corresponds to the FLEXE interface bearer Business. The transmission direction from Ethernet to FLEXE can be referred to as the upstream direction, and the transmission direction from FLEXE to Ethernet can be referred to as the downstream direction.

空闲码块指在有效数据之间填充的无实义的非有效数据。为了灵活调节有效数据的传输速率而不必增加或删除传输的有效数据，可以在有效数据之间添加或删除无实义的空闲码块。Idle code blocks refer to non-valid data with no real meaning filled between valid data. In order to flexibly adjust the transmission rate of valid data without having to increase or delete the transmitted valid data, idle code blocks with no meaning can be added or deleted between valid data.

FEC是一种差错控制技术，在信号被送入传输信道之前预先按一定的算法进行编码处理，加入带有信号本身特征的冗码，在接收端按照相应算法对接收到的信号进行解码，从而找出在传输过程中产生的错误码并将其纠正。FEC is an error control technology. Before the signal is sent to the transmission channel, the signal is encoded according to a certain algorithm, and the redundant code with the characteristics of the signal itself is added, and the received signal is decoded according to the corresponding algorithm at the receiving end. Find out the error code generated during the transmission and correct it.

AM。在多通道分发数据时，由于传输时延不同会造成数据乱序或偏差，可以通过添加AM来纠正这种偏差。在25G以太网中也可以称为码字码块(code word marker，CWM)。AM. When distributing data in multiple channels, the data will be out of order or deviation due to different transmission delays. This deviation can be corrected by adding AM. In 25G Ethernet, it can also be called a code word marker (CWM).

OH用于在FLEXE中传输管理信息，实现对接的两个FLEXE接口之间配置信息的预先协商、握手等。OH is used to transmit management information in FLEXE to realize pre-negotiation and handshake of configuration information between the two connected FLEXE interfaces.

净荷带宽指从总带宽中除去AM、OH、FEC之后的剩余带宽。Payload bandwidth refers to the remaining bandwidth after removing AM, OH, and FEC from the total bandwidth.

如图3所示，本申请实施例提供了一种速率调节装置13，可以支持双向通信链路的速率调节，即支持从第一通信装置11至第二通信装置12方向上的速率调节，以及，从第二通信装置12至第一通信装置11方向上的速率调节。As shown in FIG. 3, an embodiment of the present application provides a rate adjustment device 13 that can support rate adjustment of a two-way communication link, that is, support rate adjustment in the direction from the first communication device 11 to the second communication device 12, and , The rate adjustment in the direction from the second communication device 12 to the first communication device 11.

从第一通信装置11至第二通信装置12方向上，速率调节装置13包括:第一删除核301、第一增加核302、第一空闲码块处理核303、第一输入存储器304、第一输出存储器305、第一速率匹配(rate adpation，RA)存储器306和第一RA控制核307。From the first communication device 11 to the second communication device 12, the rate adjustment device 13 includes: a first deletion core 301, a first addition core 302, a first idle code block processing core 303, a first input memory 304, a first The output memory 305, the first rate adpation (RA) memory 306, and the first RA control core 307.

从第二通信装置12至第一通信装置11方向上，速率调节装置13包括：第二删除核311、第二增加核312、第二空闲码块处理核313、第二输入存储器314、第二输出存储器315、第二RA存储器316和第二RA控制核317。From the second communication device 12 to the first communication device 11, the rate adjustment device 13 includes: a second deletion core 311, a second addition core 312, a second idle code block processing core 313, a second input memory 314, and a second The output memory 315, the second RA memory 316, and the second RA control core 317.

第一删除核301、第一空闲码块处理核303和第一增加核302依次对第一数据流和第二数据流进行处理。第一输入存储器304用于先后接收并缓存第一数据流和第二数据流。第一输出存储器305用于对先后输出的第一数据流和第二数据流进行缓存。第一RA存储器306用于对第一空闲码块处理核303的处理结果进行缓存。其中，第一数据流和第二数据流指从第一通信装置11流向第二通信装置12的数据流。第一数据流和第二数据流可以为SERDES数据流。The first deleting core 301, the first free code block processing core 303, and the first adding core 302 process the first data stream and the second data stream in sequence. The first input memory 304 is used to sequentially receive and buffer the first data stream and the second data stream. The first output memory 305 is used for buffering the first data stream and the second data stream that are output successively. The first RA memory 306 is used to cache the processing result of the first free code block processing core 303. Among them, the first data stream and the second data stream refer to data streams flowing from the first communication device 11 to the second communication device 12. The first data stream and the second data stream may be SERDES data streams.

具体的，速率调节装置13从第一输入端口A接收到第一数据流和第二数据流后，缓存至第一输入存储器304。第一删除核301对第一输入存储器304中缓存的第一数据流删除FEC和AM以得第一数据流的净荷，对第二数据流删除FEC和AM以得第二数据流的净荷。Specifically, after the rate adjusting device 13 receives the first data stream and the second data stream from the first input port A, they buffer them in the first input memory 304. The first deletion core 301 deletes FEC and AM for the first data stream buffered in the first input memory 304 to obtain the payload of the first data stream, and deletes FEC and AM for the second data stream to obtain the payload of the second data stream .

第一空闲码块处理核303根据第一RA控制核307的第一控制指令对第一数据流的净荷增加或删除空闲码块，并将处理结果缓存至第一RA存储器306，其中，第一控制指令用于指示第一数据流的净荷以及空闲码块数之和。The first idle code block processing core 303 adds or deletes idle code blocks to the payload of the first data stream according to the first control instruction of the first RA control core 307, and caches the processing result in the first RA memory 306. A control instruction is used to indicate the sum of the payload of the first data stream and the number of free code blocks.

第一RA控制核307根据第一RA存储器306中缓存的处理结果生成第二控制指令，第二控制指令用于指示第二数据流的净荷以及空闲码块数之和。第一空闲码块处理核303根据第二控制指令对第二数据流的净荷增加或删除空闲码块，并将处理结果缓存至第一RA存储器306。The first RA control core 307 generates a second control instruction according to the processing result buffered in the first RA memory 306, and the second control instruction is used to indicate the sum of the payload of the second data stream and the number of free code blocks. The first idle code block processing core 303 adds or deletes idle code blocks to the payload of the second data stream according to the second control instruction, and caches the processing result in the first RA memory 306.

第一增加核302用于对第一RA存储器306中的第一数据流和第二数据流增加FEC和AM，将处理结果缓存至第一输出存储器305，最后通过第一输出端口B将第一数据流和第二数据流发送出去。The first adding core 302 is used to add FEC and AM to the first data stream and the second data stream in the first RA memory 306, buffer the processing result to the first output memory 305, and finally transfer the first data stream through the first output port B. The data stream and the second data stream are sent out.

第二删除核311、第二空闲码块处理核313和第二增加核312依次对第三数据流和第四数据流进行处理。第二输入存储器314用于先后接收并缓存第三数据流和第四数据流。第二输出存储器315用于对先后输出的第三数据流和第四数据流进行缓存。第二RA存储器316用于对第二空闲码块处理核313的处理结果进行缓存。其中，第三数据流和第四数据流指从第二通信装置12流向第一通信装置11的数据流。也就是说，第三数据流和第四数据流的流向与第一数据流和第二数据流的流向相反。第二数据流可以为SERDES数据流。The second deleting core 311, the second free code block processing core 313, and the second adding core 312 sequentially process the third data stream and the fourth data stream. The second input memory 314 is used to sequentially receive and buffer the third data stream and the fourth data stream. The second output memory 315 is used for buffering the third data stream and the fourth data stream that are output successively. The second RA memory 316 is used to cache the processing result of the second free code block processing core 313. Among them, the third data stream and the fourth data stream refer to data streams flowing from the second communication device 12 to the first communication device 11. That is, the flow directions of the third data flow and the fourth data flow are opposite to the flow directions of the first data flow and the second data flow. The second data stream may be a SERDES data stream.

具体的，速率调节装置13从第二输入端口C接收到第二数据流和第四数据流后，缓存至第二输入存储器314。第二删除核311用于对第二输入存储器314中缓存的第三数据流删除FEC和AM以得第三数据流的净荷，对第四数据流删除FEC和AM以得第四数据流的净荷。Specifically, after the rate adjusting device 13 receives the second data stream and the fourth data stream from the second input port C, they buffer them in the second input memory 314. The second deletion core 311 is used to delete FEC and AM for the third data stream buffered in the second input memory 314 to obtain the payload of the third data stream, and delete FEC and AM for the fourth data stream to obtain the fourth data stream. Payload.

第二空闲码块处理核313根据第二RA控制核317的第三控制指令对第三数据流的净荷增加或删除空闲码块，并将处理结果缓存至第二RA存储器316，其中，第三控制指令用于指示第二数据流的净荷以及空闲码块数之和。The second idle code block processing core 313 adds or deletes idle code blocks to the payload of the third data stream according to the third control instruction of the second RA control core 317, and caches the processing result in the second RA memory 316. The three control instructions are used to indicate the sum of the payload of the second data stream and the number of free code blocks.

第二RA控制核317根据第二RA存储器316中缓存的处理结果生成第四控制指令，第四控制指令用于指示第四数据流的净荷以及空闲码块数之和。第二空闲码块处理核313根据第四控制指令对第四数据流的净荷增加或删除空闲码块，并将处理结果缓存至第二RA存储器316。The second RA control core 317 generates a fourth control instruction according to the processing result buffered in the second RA memory 316, and the fourth control instruction is used to indicate the sum of the payload of the fourth data stream and the number of free code blocks. The second idle code block processing core 313 adds or deletes idle code blocks to the payload of the fourth data stream according to the fourth control instruction, and caches the processing result in the second RA memory 316.

第二增加核312用于对第二RA存储器316中的第二数据流和第四数据流增加FEC和AM，将处理结果缓存至第二输出存储器315，最后通过第二输出端口D将第二数据流和第四数据流发送出去。The second increase core 312 is used to add FEC and AM to the second data stream and the fourth data stream in the second RA memory 316, buffer the processing result to the second output memory 315, and finally transfer the second data stream through the second output port D. The data stream and the fourth data stream are sent out.

从中可以看出，第一RA控制核307或第二RA控制核317在根据RA存储器中增加或删除的空闲码块生成控制指令时，由于RA存储器中增加或删除的空闲码块是以码块为单位计量的，每次增加或删除空闲码块所占比特位都是上百比特位，使得生成的控制指令指示的数据流的净荷以及空闲码块数之和的变化幅度很大，使得空闲码块处理核的控制精度也较低，会造成数据流的严重抖动，进而影响1588协议时钟同步的精度。It can be seen from this that when the first RA control core 307 or the second RA control core 317 generates a control instruction according to the free code block added or deleted in the RA memory, the free code block added or deleted in the RA memory is a code block. Measured in units, the number of bits occupied by free code blocks is hundreds of bits each time you add or delete free code blocks, so that the payload of the data stream indicated by the generated control instructions and the sum of the number of free code blocks vary greatly, making The control accuracy of the idle code block processing core is also low, which will cause serious jitter in the data stream, and further affect the accuracy of the 1588 protocol clock synchronization.

本申请实施例中，速率调节装置根据比特位精度的净荷带宽来确定增加或删除空闲码块，从而实现对数据的传输速率进行调节，具体的，速率调节装置可以根据输入的净荷带宽、输出的净荷带宽、已经增加和删除的空闲码块的数量来确定进一步增加或删除空闲码块，通过负反馈机制可以以比特位精度对空闲码块进行增加或删除，从而精确调节数据的传输速率，提高时钟同步的精度。In the embodiment of the present application, the rate adjustment device determines to add or delete idle code blocks according to the payload bandwidth with bit accuracy, so as to adjust the data transmission rate. Specifically, the rate adjustment device can adjust the data transmission rate according to the input payload bandwidth, The output payload bandwidth and the number of idle code blocks that have been added and deleted are used to determine the further addition or deletion of idle code blocks. Through the negative feedback mechanism, idle code blocks can be added or deleted with bit precision to precisely adjust data transmission. Speed, improve the accuracy of clock synchronization.

具体的，本申请实施例提供了另一种速率调节装置，可以应用于不同以太网中的通信装置之间的速率调节。Specifically, the embodiment of the present application provides another rate adjustment device, which can be applied to rate adjustment between communication devices in different Ethernets.

如图4所示，在图3的基础上，该速率调节装置13还包括：第一控制核308和第二控制核318。As shown in FIG. 4, on the basis of FIG. 3, the rate adjusting device 13 further includes: a first control core 308 and a second control core 318.

第一控制核308与第一RA控制核307可以通过选择开关选择生效其中一个，或者，可以只有第一控制核308而没有第一RA控制核307和第一RA存储器306，即第一RA控制核307和第一RA存储器306是可选的。The first control core 308 and the first RA control core 307 can be selected to take effect through the selector switch, or there can be only the first control core 308 without the first RA control core 307 and the first RA memory 306, that is, the first RA control The core 307 and the first RA memory 306 are optional.

同理，第二控制核318与第二RA控制核317可以通过选择开关选择生效其中一个，或者，可以只有第二控制核318而没有第二RA控制核317和第二RA存储器316，即第二RA控制核317和第二RA存储器316是可选的。In the same way, the second control core 318 and the second RA control core 317 can be selected to take effect through the selector switch, or there can be only the second control core 318 without the second RA control core 317 and the second RA memory 316, that is, the first The second RA control core 317 and the second RA memory 316 are optional.

下面对第一输入存储器304、第一控制核308和第一空闲码块处理核303的工作过程进行详细描述。The working processes of the first input memory 304, the first control core 308, and the first idle code block processing core 303 will be described in detail below.

具体的，第一输入存储器304、第一控制核308和第一空闲码块处理核303用于执行如图5所示的速率调节方法，其中，第一输入存储器304用于执行步骤S501、第一控制核308用于执行步骤S503，第一空闲码块处理核303用于执行步骤S502和S504：Specifically, the first input memory 304, the first control core 308, and the first idle code block processing core 303 are used to perform the rate adjustment method shown in FIG. 5, wherein the first input memory 304 is used to perform steps S501 and S501. A control core 308 is used to perform step S503, and the first free code block processing core 303 is used to perform steps S502 and S504:

S501、先后接收第一数据流和第二数据流。S501: Receive a first data stream and a second data stream successively.

关于第一数据流和第二数据流见前文描述，在此不再重复。Regarding the first data stream and the second data stream, see the foregoing description, and will not be repeated here.

S502、根据第一控制核308发送的第一缓存占用量，在第一数据流中增加或删除第一比特数的空闲码块。S502: Add or delete idle code blocks of the first number of bits in the first data stream according to the first buffer occupancy sent by the first control core 308.

第一缓存占用量可以为比特位的数目。The first buffer occupancy may be the number of bits.

第一空闲码块处理核303对第一数据流的处理方式可以参照后面步骤S504中对第二数据流的处理方式。For the processing manner of the first free code block processing core 303 on the first data stream, reference may be made to the processing manner on the second data stream in the following step S504.

S503、根据第一缓存占用量，第二数据流在输入端口的净荷带宽、第二数据流在输出端口的净荷带宽、第一比特数，获得第二缓存占用量。S503. Obtain the second buffer occupancy based on the first buffer occupancy, the payload bandwidth of the second data stream at the input port, the second data stream's payload bandwidth at the output port, and the first bit number.

具体的，如图4所示，第一控制核308可以包括第一速率匹配子核3081、第二速率匹配子核3082和第一计算子核3083。Specifically, as shown in FIG. 4, the first control core 308 may include a first rate matching sub-core 3081, a second rate matching sub-core 3082 and a first calculation sub-core 3083.

第一速率匹配子核3081可以通过第一输入存储器304获取第二数据流在输入端口A的总带宽，并根据第二数据流在输入端口的总带宽确定第二数据流在输入端口A的净荷带宽RX_A。由于AM、FEC在以太协议中是固定间隔***的，其带宽与总带宽的比例是固定，使得去除AM、FEC后净荷带宽与总带宽的比例也是固定的，第一速率匹配子核3081可以根据第二数据流在输入端口A的总带宽以及净荷带宽与总带宽的比例来得到第二数据流在输入端口A的净荷带宽RX_A。对于第二数据流为SERDES 数据流来说，该净荷带宽RX_A可以对应在输入端口A的串行转并行之后去除AM、FEC后的净荷带宽。The first rate matching sub-core 3081 can obtain the total bandwidth of the second data stream at the input port A through the first input memory 304, and determine the net bandwidth of the second data stream at the input port A according to the total bandwidth of the second data stream at the input port. Load bandwidth RX_A. Since AM and FEC are inserted at fixed intervals in the Ethernet protocol, the ratio of their bandwidth to the total bandwidth is fixed, so that the ratio of the payload bandwidth to the total bandwidth after AM and FEC is removed is also fixed. The first rate matching sub-core 3081 can The payload bandwidth RX_A of the second data stream at the input port A is obtained according to the total bandwidth of the second data stream at the input port A and the ratio of the payload bandwidth to the total bandwidth. For the second data stream being the SERDES data stream, the payload bandwidth RX_A may correspond to the payload bandwidth after the serial conversion of the input port A to parallelize the AM and FEC.

第二速率匹配子核3082可以通过第一输出存储器305获取第二数据流在输出端口B的总带宽，并根据第二数据流在输出端口的总带宽确定第二数据流在输出端口B的净荷带宽TX_B。即第二速率匹配子核3082可以根据第二数据流在输出端口B的总带宽以及净荷带宽与总带宽的比例来得到第二数据流在输出端口B的净荷带宽TX_B。对于第二数据流为SERDES数据流来说，该净荷带宽可以对应在输出端口B的并行转串行之前去除AM、FEC后的净荷带宽。The second rate matching sub-core 3082 can obtain the total bandwidth of the second data stream at the output port B through the first output memory 305, and determine the net bandwidth of the second data stream at the output port B according to the total bandwidth of the second data stream at the output port. Load bandwidth TX_B. That is, the second rate matching sub-core 3082 can obtain the payload bandwidth TX_B of the second data stream at the output port B according to the total bandwidth of the second data stream at the output port B and the ratio of the payload bandwidth to the total bandwidth. For the second data stream being the SERDES data stream, the payload bandwidth may correspond to the payload bandwidth after AM and FEC are removed before the parallel conversion of the output port B.

第一空闲码块处理核303每次增加完空闲码块后，可以向第一计算子核3083发送增加的空闲码块的比特数ADD_CNT1；第一空闲码块处理核303每次删除完空闲码块后，可以向第一计算子核3083发送删除的空闲码块的比特数DEL_CNT1。也就是说，第一比特数可以通过增加的空闲码块的比特数ADD_CNT1和删除的空闲码块的比特数DEL_CNT1分别表示。The first free code block processing core 303 can send the number of bits ADD_CNT1 of the added free code block to the first computing sub-core 3083 each time after adding free code blocks; the first free code block processing core 303 deletes free codes each time After the block, the number of bits of the deleted free code block DEL_CNT1 can be sent to the first computing sub-core 3083. That is to say, the first number of bits can be respectively represented by the number of bits of the added free code block ADD_CNT1 and the number of bits of the deleted free code block DEL_CNT1.

具体的，第一计算子核3083可以根据第一缓存占用量BIT_ACC1(n-1)、第二数据流在输入端口A的净荷带宽RX_A、第二数据流在输出端口B的净荷带宽TX_B、第一空闲码块处理核303增加的空闲码块的比特数ADD_CNT1以及删除的空闲码块的比特数DEL_CNT1，获得第二缓存占用量BIT_ACC1(n)，并将第二缓存占用量BIT_ACC1(n)发送给第一空闲码块处理核303。Specifically, the first computing sub-core 3083 may be based on the first buffer occupancy BIT_ACC1(n-1), the payload bandwidth RX_A of the second data stream at the input port A, and the payload bandwidth TX_B of the second data stream at the output port B. , The first free code block processing core 303 increases the number of bits of the free code block ADD_CNT1 and the number of bits of the deleted free code block DEL_CNT1 to obtain the second buffer occupancy BIT_ACC1(n), and the second buffer occupancy BIT_ACC1(n ) Is sent to the first idle code block processing core 303.

具体的，第一计算子核3083可以根据公式3来计算第二缓存占用量BIT_ACC1(n)：Specifically, the first calculation sub-core 3083 may calculate the second cache occupancy BIT_ACC1(n) according to formula 3:

BIT_ACC1(n)＝BIT_ACC1(n-1)+RX_A-TX_B+ADD_CNT1-DEL_CNT1 公式3BIT_ACC1(n)=BIT_ACC1(n-1)+RX_A-TX_B+ADD_CNT1-DEL_CNT1 Formula 3

其中，n为正整数，表示计算次数。第一缓存占用量BIT_ACC1(n-1)的初始值为BASE_ACC1，BASE_ACC1表示第一基准水线，其取值可以为固定值或浮动值。第一基准水线也就是负反馈的基准值，其本质含义为：当数据的传输速率高于该基准值一定比例时，通过增加空闲码块来降低数据的传输速率，当数据的传输速率低于该基准值一定比例时，通过删除空闲码块来降低数据的传输速率，当数据的传输速率在围绕该基准值一定范围内时，不增加或删除空闲码块。Among them, n is a positive integer, indicating the number of calculations. The initial value of the first buffer occupancy BIT_ACC1(n-1) is BASE_ACC1, BASE_ACC1 represents the first baseline waterline, and its value can be a fixed value or a floating value. The first reference waterline is the reference value of negative feedback, and its essential meaning is: when the data transmission rate is higher than a certain percentage of the reference value, the data transmission rate is reduced by increasing the idle code block. When the data transmission rate is low At a certain percentage of the reference value, the data transmission rate is reduced by deleting idle code blocks. When the data transmission rate is within a certain range around the reference value, the idle code blocks are not added or deleted.

S504、根据第二缓存占用量，在第二数据流中增加或删除空闲码块。S504: Add or delete idle code blocks in the second data stream according to the occupancy of the second buffer.

第一空闲码块处理核303接收到第一缓存占用量后，并不一定立即对第二数据流增加或删除空闲码块，要等待第二数据流的帧间隙位置增加或者删除空闲码块。在完成增加或者删除空闲码块后，第一空闲码块处理核303可以向第一控制核308发送第一指示信息，该第一指示信息指示本次增加的空闲码块的比特数ADD_CNT1或删除的空闲码块的比特数DEL_CNT1。或者，第一空闲码块处理核303可以向第一控制核308发送第二指示信息和第三指示信息，第二指示信息用于指示增加或删除空闲码块，第三指示信息用于指示增加或删除空闲码块的具体数目。上述指示信息供第一控制核308在下一调节过程中重新根据步骤S503计算第二缓存占用量。After the first idle code block processing core 303 receives the first buffer occupancy, it does not necessarily add or delete idle code blocks to the second data stream immediately, but waits for the frame gap position of the second data stream to increase or delete idle code blocks. After completing the addition or deletion of idle code blocks, the first idle code block processing core 303 may send first indication information to the first control core 308, the first indication information indicating the number of bits of the idle code block added this time ADD_CNT1 or deletion The number of bits in the free code block DEL_CNT1. Alternatively, the first idle code block processing core 303 may send second indication information and third indication information to the first control core 308, the second indication information is used to indicate the addition or deletion of idle code blocks, and the third indication information is used to indicate addition Or delete the specific number of free code blocks. The above-mentioned indication information is used by the first control core 308 to calculate the second buffer occupancy again according to step S503 in the next adjustment process.

第一空闲码块处理核303根据第二缓存占用量对第二数据流增加或删除空闲码块时，增加或删除空闲码块的数量可以遵从协议规定，或者由厂商或用户自定义，本申请不作限定。When the first free code block processing core 303 adds or deletes free code blocks to the second data stream according to the second buffer occupancy, the number of added or deleted free code blocks can comply with the provisions of the agreement or be customized by the manufacturer or user. Not limited.

示例性的，如果第二缓存占用量BIT_ACC1(n)大于或等于第一水线L1(第一水线为第一基准水线BASE_ACC1上浮一定比例)，则说明净荷的接收速率大于发送速率，可以通过删除空闲码块来增加净荷的发送速率，删除的空闲码块数目可以大于或等于(BIT_ACC1(n)-L1)/每码块比特数。Exemplarily, if the second buffer occupancy BIT_ACC1(n) is greater than or equal to the first waterline L1 (the first waterline is the first reference waterline BASE_ACC1 rises by a certain percentage), it means that the receiving rate of the payload is greater than the sending rate, The transmission rate of the payload can be increased by deleting idle code blocks. The number of deleted idle code blocks can be greater than or equal to (BIT_ACC1(n)-L1)/bits per code block.

如果第二缓存占用量BIT_ACC1(n)小于或等于第二水线L2(第二水线为第一基准水线BASE_ACC1下调一定比例)，则说明净荷的接收速率小于发送速率，可以通过增加空闲码块来减小净荷的发送速率，增加的空闲码块数目可以大于或等于(L2-BIT_ACC1(n))/每码块比特数。If the second buffer occupancy BIT_ACC1(n) is less than or equal to the second waterline L2 (the second waterline is the first reference waterline BASE_ACC1 is reduced by a certain percentage), it means that the receiving rate of the payload is less than the sending rate, which can be increased by increasing the idle Code blocks are used to reduce the transmission rate of the payload. The number of free code blocks added can be greater than or equal to (L2-BIT_ACC1(n))/bits per code block.

如果第二缓存占用量BIT_ACC1(n)小于第一水线而大于第二水线，则说明净荷的接收速率与发送速率持平，可以不增加也不删除空闲码块。If the second buffer occupancy BIT_ACC1(n) is less than the first waterline but greater than the second waterline, it means that the receiving rate of the payload is the same as the sending rate, and the idle code blocks may not be increased or deleted.

第一水线和第二水线之间的范围也可以称为磁滞区间。采用第一水线和第二水线作为判断标准，而不是直接采用第一基准水线作为标准，是为了防止针对同一数值进行反向调节造成反复增加和删除空闲码块，使得传输速率围绕第一基准水线反复振荡。The range between the first waterline and the second waterline may also be referred to as a hysteresis interval. The first waterline and the second waterline are used as the judgment criteria, instead of directly using the first reference waterline as the standard, in order to prevent the reverse adjustment of the same value from repeatedly increasing and deleting idle code blocks, so that the transmission rate is around the first reference waterline. A baseline waterline oscillates repeatedly.

需要说明的是，第一空闲码块处理核303经过增加或删除空闲码块后实际缓存占用量并不一定与期望的第二缓存占用量相等，因为数据流中只有在非有效数据的特定窗口才可以进行增加或删除空闲码块，该窗口可能过小，使得无法再增加足够数目的空闲码块，只能等下个窗口再增加或删除空闲码块。It should be noted that after the first free code block processing core 303 adds or deletes free code blocks, the actual cache occupancy is not necessarily equal to the expected second cache occupancy, because there is only a specific window of invalid data in the data stream. Only then can the idle code blocks be added or deleted. The window may be too small, making it impossible to add a sufficient number of idle code blocks, and the idle code blocks can only be added or deleted after the next window.

第三数据流和第四数据流的流向与第一数据流和第二数据流的流向是相反的，速率调节装置13对这两个数据流的处理方式是类似的，因此，本申请前文着重描述了对第一数据流和第二数据流的处理方式，对于第三数据流和第四数据流的处理方式具体细节可以参照对第一数据流和第二数据流的处理方式，后文仅概括性的介绍第二输入存储器314、第二控制核318和第二空闲码块处理核313的基本功能：The flow directions of the third data stream and the fourth data stream are opposite to those of the first data stream and the second data stream, and the rate adjustment device 13 processes these two data streams in a similar manner. Therefore, the previous article of this application focuses on Describes the processing methods of the first data stream and the second data stream. For the details of the processing methods of the third data stream and the fourth data stream, please refer to the processing methods of the first data stream and the second data stream. A general introduction to the basic functions of the second input memory 314, the second control core 318, and the second idle code block processing core 313:

例如，第二输入存储器314可以先后接收第三数据流和第四数据流。For example, the second input memory 314 may sequentially receive the third data stream and the fourth data stream.

第二空闲码块处理核313可以根据第二控制核318发送的第三缓存占用量，在第三数据流中增加或删除第二比特数的空闲码块。The second idle code block processing core 313 may add or delete idle code blocks of the second number of bits in the third data stream according to the third buffer occupancy sent by the second control core 318.

第二控制核318可以根据第三缓存占用量、第四数据流在输入端口C的净荷带宽、第二数据流在输出端口D的净荷带宽、第二比特数，获得第四缓存占用量。The second control core 318 can obtain the fourth buffer occupancy according to the third buffer occupancy, the payload bandwidth of the fourth data stream at the input port C, the second data stream's payload bandwidth at the output port D, and the second number of bits. .

第二空闲码块处理核313可以根据第四缓存占用量，在第四数据流中增加或删除空闲码块。The second idle code block processing core 313 may add or delete idle code blocks in the fourth data stream according to the fourth buffer occupancy.

具体的，第二控制核318可以包括第四速率匹配子核3181、第五速率匹配子核3182和第二计算子核3183。Specifically, the second control core 318 may include a fourth rate matching sub-core 3181, a fifth rate matching sub-core 3182, and a second calculation sub-core 3183.

第四速率匹配子核3181可以通过第二输入存储器314获取第四数据流在输入端口的总带宽，并根据第四数据流在输入端口的总带宽确定第四数据流在输入端口C的净荷带宽RX_C。The fourth rate matching sub-core 3181 can obtain the total bandwidth of the fourth data stream at the input port through the second input memory 314, and determine the payload of the fourth data stream at the input port C according to the total bandwidth of the fourth data stream at the input port. Bandwidth RX_C.

第五速率匹配子核3182可以通过第二输出存储器315获取第四数据流在输出端口的总带宽，并根据第四数据流在输出端口的总带宽确定第四数据流在输出端口D的净荷带宽TX_D。The fifth rate matching sub-core 3182 can obtain the total bandwidth of the fourth data stream at the output port through the second output memory 315, and determine the payload of the fourth data stream at the output port D according to the total bandwidth of the fourth data stream at the output port. Bandwidth TX_D.

第二计算子核3183可以根据第二缓存占用量BIT_ACC2(n-1)、第四数据流在输入端口C的净荷带宽RX_C、第四数据流在输出端口D的净荷带宽TX_D、第二空闲码块处理核313增加的空闲码块的比特数ADD_CNT2以及删除的空闲码块的比特数DEL_CNT2，计算得到第二缓存占用量BIT_ACC2(n)。也就是说，第二比特数可以通过增加的空闲码块的比特数ADD_CNT2和删除的空闲码块的比特数DEL_CNT2分别表示。具体的：The second computing sub-core 3183 can be based on the second buffer occupancy BIT_ACC2(n-1), the payload bandwidth RX_C of the fourth data stream at the input port C, the payload bandwidth TX_D of the fourth data stream at the output port D, and the second The idle code block processing core 313 adds the number of bits ADD_CNT2 of the idle code block and the number of bits DEL_CNT2 of the deleted idle code block, and calculates the second buffer occupancy BIT_ACC2(n). That is to say, the second number of bits can be represented by the number of bits of the added free code block ADD_CNT2 and the number of bits of the deleted free code block DEL_CNT2 respectively. specific:

BIT_ACC2(n)＝BIT_ACC2(n-1)+RX_C-TX_D+ADD_CNT2-DEL_CNT2 公式4BIT_ACC2(n)=BIT_ACC2(n-1)+RX_C-TX_D+ADD_CNT2-DEL_CNT2 Formula 4

对于以上关于第二输入存储器314的具体内容可以参照步骤S501中第一输入存储器304的相关内容。以上关于第二控制核318的具体内容可以参照步骤S503中第一控制核308的相关内容。以上关于第二空闲码块处理核313的具体内容可以参照步骤S502、S504中第一空闲码块处理核303的相关内容。For the above specific content of the second input memory 314, reference may be made to the relevant content of the first input memory 304 in step S501. For the specific content of the second control core 318 above, reference may be made to the related content of the first control core 308 in step S503. For the specific content of the second free code block processing core 313 above, reference may be made to the related content of the first free code block processing core 303 in steps S502 and S504.

通过以上实施方式，本申请实施例提供的速率调节装置可以支持对双向链路的速率进行精确调节，还可以提高双向链路的时钟同步的精度。Through the foregoing implementation manners, the rate adjustment device provided in the embodiments of the present application can support precise adjustment of the rate of the bidirectional link, and can also improve the accuracy of the clock synchronization of the bidirectional link.

本申请实施例提供了另一种速率调节装置，可以应用于以太网与FLEXE之间的速率调节，具体的，可以应用于FLEXE的散列下的每个客户端(即以太网)的速率调节。本申请以第一通信设备11位于以太网，第二通信装置12位于FLEXE为例，但并不限定于此。The embodiment of the application provides another rate adjustment device, which can be applied to the rate adjustment between Ethernet and FLEXE. Specifically, it can be applied to the rate adjustment of each client (ie, Ethernet) under the hash of FLEXE. . In this application, the first communication device 11 is located in the Ethernet and the second communication device 12 is located in FLEXE as an example, but it is not limited to this.

如图6所示，在图4的基础上，速率调节装置13还可以包括：第一码型转换核309、第一映射核300。As shown in FIG. 6, based on FIG. 4, the rate adjusting device 13 may further include: a first code conversion core 309 and a first mapping core 300.

第一码型转换核304可以用于不同网络间码型的转换，例如将第一数据流从以太网66B码型转换为FLEXE 66B码型。The first code type conversion core 304 may be used for code type conversion between different networks, for example, converting the first data stream from the Ethernet 66B code type to the FLEXE 66B code type.

第一映射核300可以用于不同网络间端口的映射，例如将传输第一数据流的以太端口作为FLEXE的客户端，将以太端口映射到FLEXE接口。The first mapping core 300 may be used for port mapping between different networks. For example, the Ethernet port that transmits the first data stream is used as a FLEXE client, and the Ethernet port is mapped to the FLEXE interface.

与图4所示的速率调节装置相比，第一增加核302除了用于增加FEC和AM以外，还可以用于增加FLEXE的OH。第二速率匹配子核3082获得的第一数据流在输出端口的净荷带宽除了去除FM、FEC以外，还去除了OH。Compared with the rate adjustment device shown in FIG. 4, the first increase core 302 can be used to increase the OH of FLEXE in addition to increasing FEC and AM. The payload bandwidth at the output port of the first data stream obtained by the second rate matching sub-core 3082 not only removes FM and FEC, but also removes OH.

第一控制核308还包括第三速率匹配子核3084，可以根据以太网带宽与FLEXE带宽之间的比例对第一数据流在输出端口的净荷带宽进行修正。例如，FLEXE带宽为100G，以太网带宽为25G，则以太网带宽与FLEXE带宽之间的比例为1/4，因此可以将第二速率匹配子核3082获取的第一数据流在输出端口的净荷带宽乘以1/4来进行修正。可以将FLEXE带宽统一为以太网带宽。The first control core 308 also includes a third rate matching sub-core 3084, which can correct the payload bandwidth of the first data stream at the output port according to the ratio between the Ethernet bandwidth and the FLEXE bandwidth. For example, if the FLEXE bandwidth is 100G and the Ethernet bandwidth is 25G, the ratio between the Ethernet bandwidth and the FLEXE bandwidth is 1/4. Therefore, the second rate can be matched to the net output port of the first data stream obtained by the sub-core 3082. Multiply the load bandwidth by 1/4 to correct it. The FLEXE bandwidth can be unified into the Ethernet bandwidth.

对于对第二数据流的处理来说，速率调节装置13还可以包括：第二码型转换核319、第二映射核310。For processing the second data stream, the rate adjustment device 13 may further include: a second code conversion core 319 and a second mapping core 310.

第二码型转换核319可以用于不同网络间码型的转换，例如将第二数据流从FLEXE 66B码型转换为以太网66B码型。The second code type conversion core 319 may be used for code type conversion between different networks, for example, converting the second data stream from the FLEXE 66B code type to the Ethernet 66B code type.

第二映射核310可以用于不同网络间端口的映射，例如从传输第二数据流的FLEXE接口中解映射出FLEXE的客户端(即以太端口)。The second mapping core 310 may be used for port mapping between different networks, for example, demapping the FLEXE client (ie, Ethernet port) from the FLEXE interface for transmitting the second data stream.

与图4所示的速率调节装置相比，第二删除核302除了用于删除FEC和AM以外，还可以用于删除FLEXE的OH。第四速率匹配子核3181获得的第二数据流在输入端口的净荷带宽除了去除FM、FEC以外，还去除了OH。Compared with the rate adjustment device shown in FIG. 4, the second deletion core 302 can be used to delete the OH of FLEXE in addition to deleting FEC and AM. In addition to removing FM and FEC, the payload bandwidth of the second data stream at the input port obtained by the fourth rate matching sub-core 3181 also removes OH.

第二控制核318还包括第六速率匹配子核3184，可以根据以太网带宽与FLEXE带宽之间的比例对第四数据流在输入端口的净荷带宽进行修正。例如，FLEXE带宽为100G，以太网带宽为25G，则以太网带宽与FLEXE带宽之间的比例为1/4，因此可以将第四速率匹配子核3181获取的第四数据流在输入端口的净荷带宽乘以1/4来进行修正。The second control core 318 also includes a sixth rate matching sub-core 3184, which can correct the payload bandwidth of the fourth data stream at the input port according to the ratio between the Ethernet bandwidth and the FLEXE bandwidth. For example, if the FLEXE bandwidth is 100G and the Ethernet bandwidth is 25G, the ratio between the Ethernet bandwidth and the FLEXE bandwidth is 1/4. Therefore, the fourth rate can be matched to the net of the fourth data stream obtained by the sub-core 3181 at the input port. Multiply the load bandwidth by 1/4 to correct it.

本申请实施例提供的速率调节装置，可以实现对以太网与FLEXE之间传输的数据流的速率进行精确调节，提高以太网与FLEXE之间的通信装置的时钟同步的精度。The rate adjustment device provided in the embodiment of the present application can realize the precise adjustment of the rate of the data stream transmitted between the Ethernet and the FLEXE, and improve the accuracy of the clock synchronization of the communication device between the Ethernet and the FLEXE.

应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。It should be understood that in the various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not correspond to the embodiments of the present application. The implementation process constitutes any limitation.

本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。A person of ordinary skill in the art may realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.

所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的***、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。Those skilled in the art can clearly understand that, for the convenience and conciseness of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

在本申请所提供的几个实施例中，应该理解到，所揭露的***、设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个***，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。In the several embodiments provided in this application, it should be understood that the disclosed system, device, and method may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or It can be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection between devices or units through some interfaces, and may be in electrical, mechanical or other forms.

所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

另外，在本申请各个实施例中的各功能单元可以集成在一个处理核中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。In addition, the functional units in the various embodiments of the present application may be integrated into one processing core, or each unit may exist alone physically, or two or more units may be integrated into one unit.

在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件程序实现时，可以全部或部分地以计算机程序产品的形式来实现。该计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或者数据中心通过有线(例如同轴电缆、光纤、数字用户线(Digital Subscriber Line，DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可以用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)，光介质(例如，DVD)、或者半导体介质(例如固态硬盘(Solid State Disk，SSD))等。In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it can be implemented in the form of a computer program product in whole or in part. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center. Transmission to another website, computer, server or data center via wired (such as coaxial cable, optical fiber, Digital Subscriber Line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer or includes one or more data storage devices such as servers, data centers, etc. that can be integrated with the medium. The usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, and a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)).

以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application. Should be covered within the scope of protection of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

一种速率调节装置，其特征在于，包括：第一输入存储器、第一空闲码块处理核和第一控制核，A rate adjustment device, characterized by comprising: a first input memory, a first idle code block processing core, and a first control core,

所述第一输入存储器，用于先后接收第一数据流和第二数据流；The first input memory is configured to sequentially receive a first data stream and a second data stream;

所述第一空闲码块处理核，用于根据所述第一控制核发送的第一缓存占用量，在所述第一数据流中增加或删除第一比特数的空闲码块；The first idle code block processing core is configured to add or delete idle code blocks of the first number of bits in the first data stream according to the first buffer occupancy sent by the first control core;

所述第一控制核，用于根据所述第一缓存占用量、所述第二数据流在输入端口的净荷带宽、所述第二数据流在输出端口的净荷带宽、所述第一比特数，获得第二缓存占用量；The first control core is configured to use the first buffer occupancy, the payload bandwidth of the second data stream at the input port, the payload bandwidth of the second data stream at the output port, and the first The number of bits to obtain the second buffer occupancy;

所述第一空闲码块处理核，还用于根据所述第二缓存占用量，在所述第二数据流中增加或删除空闲码块。The first idle code block processing core is further configured to add or delete idle code blocks in the second data stream according to the second buffer occupancy.
根据权利要求1所述的速率调节装置，其特征在于，所述第一控制核包括：第一速率匹配子核，用于获取所述第二数据流在输入端口的总带宽，并根据所述第二数据流在输入端口的总带宽确定所述第二数据流在输入端口的净荷带宽。The rate adjustment device according to claim 1, wherein the first control core comprises: a first rate matching sub-core for obtaining the total bandwidth of the second data stream at the input port, and according to the The total bandwidth of the second data stream at the input port determines the payload bandwidth of the second data stream at the input port.
根据权利要求1-2任一项所述的速率调节装置，其特征在于，所述第一控制核包括：第二速率匹配子核，用于获取所述第二数据流在输出端口的总带宽，并根据所述第二数据流在输出端口的总带宽确定所述第二数据流在输出端口的净荷带宽。The rate adjustment device according to any one of claims 1-2, wherein the first control core comprises: a second rate matching sub-core for obtaining the total bandwidth of the second data stream at the output port , And determine the payload bandwidth of the second data stream at the output port according to the total bandwidth of the second data stream at the output port.
根据权利要求3所述的速率调节装置，其特征在于，所述第一控制核还包括第三速率匹配子核，用于根据以太网带宽与FLEXE带宽之间的比例对所述第二数据流在输出端口的净荷带宽进行修正。The rate adjustment device according to claim 3, wherein the first control core further comprises a third rate matching sub-core, configured to compare the second data stream according to the ratio between the Ethernet bandwidth and the FLEXE bandwidth The payload bandwidth of the output port is corrected.
根据权利要求1-4任一项所述的速率调节装置，其特征在于，还包括：第二输入存储器、第二空闲码块处理核和第二控制核，The rate adjustment device according to any one of claims 1 to 4, further comprising: a second input memory, a second idle code block processing core, and a second control core,

所述第二输入存储器，用于先后接收第三数据流和第四数据流；The second input memory is configured to sequentially receive a third data stream and a fourth data stream;

所述第二空闲码块处理核，用于根据所述第二控制核发送的第三缓存占用量，在所述第三数据流中增加或删除第二比特数的空闲码块；The second idle code block processing core is configured to add or delete idle code blocks with a second number of bits in the third data stream according to the third buffer occupancy sent by the second control core;

所述第二控制核，用于根据所述第三缓存占用量、所述第四数据流在输入端口的净荷带宽、所述第四数据流在输出端口的净荷带宽、所述第二比特数，获得第四缓存占用量；The second control core is configured to use the third buffer occupancy, the payload bandwidth of the fourth data stream at the input port, the payload bandwidth of the fourth data stream at the output port, and the second The number of bits to obtain the fourth buffer occupancy;

所述第二空闲码块处理核，还用于根据所述第四缓存占用量，在所述第四数据流中增加或删除空闲码块；The second idle code block processing core is further configured to add or delete idle code blocks in the fourth data stream according to the fourth buffer occupancy;

其中，所述第三数据流和所述第四数据流的流向与所述第一数据流和所述第二数据流的流向相反。Wherein, the flow directions of the third data flow and the fourth data flow are opposite to the flow directions of the first data flow and the second data flow.
根据权利要求5所述的速率调节装置，其特征在于，所述第二控制核包括：第四速率匹配子核，用于获取所述第四数据流在输入端口的总带宽，并根据所述第四数据流在输入端口的总带宽确定所述第四数据流在输入端口的净荷带宽。The rate adjustment device according to claim 5, wherein the second control core comprises: a fourth rate matching sub-core for obtaining the total bandwidth of the fourth data stream at the input port, and according to the The total bandwidth of the fourth data stream at the input port determines the payload bandwidth of the fourth data stream at the input port.
根据权利要求5-6任一项所述的速率调节装置，其特征在于，所述第二控制核包括：第五速率匹配子核，用于获取所述第四数据流在输出端口的总带宽，并根据所述第四数据流在输出端口的总带宽确定所述第四数据流在输出端口的净荷带宽。The rate adjustment device according to any one of claims 5-6, wherein the second control core comprises: a fifth rate matching sub-core, configured to obtain the total bandwidth of the fourth data stream at the output port , And determine the payload bandwidth of the fourth data stream at the output port according to the total bandwidth of the fourth data stream at the output port.
根据权利要求6所述的速率调节装置，其特征在于，所述第二控制核还包括第六速率匹配子核，用于根据以太网带宽与FLEXE带宽之间的比例对所述第四数据流在输入端口的净荷带宽进行修正。The rate adjustment device according to claim 6, wherein the second control core further comprises a sixth rate matching sub-core, configured to compare the fourth data stream according to the ratio between the Ethernet bandwidth and the FLEXE bandwidth The payload bandwidth of the input port is corrected.
一种速率调节方法，其特征在于，包括：A method for rate adjustment, characterized in that it comprises:

先后接收第一数据流和第二数据流；Receive the first data stream and the second data stream successively;

根据第一缓存占用量，在所述第一数据流中增加或删除第一比特数的空闲码块；Adding or deleting idle code blocks of the first number of bits in the first data stream according to the occupancy of the first buffer;

根据所述第一缓存占用量、所述第二数据流在输入端口的净荷带宽、所述第二数据流在输出端口的净荷带宽、所述第一比特数，获得第二缓存占用量；According to the first buffer occupancy, the payload bandwidth of the second data stream at the input port, the payload bandwidth of the second data stream at the output port, and the first number of bits, the second buffer occupancy is obtained ；

根据所述第二缓存占用量，在所述第二数据流中增加或删除空闲码块。According to the second buffer occupancy, free code blocks are added or deleted in the second data stream.
根据权利要求9所述的速率调节方法，其特征在于，所述方法还包括：The rate adjustment method according to claim 9, wherein the method further comprises:

获取所述第二数据流在输入端口的总带宽，并根据所述第二数据流在输入端口的总带宽确定所述第二数据流在输入端口的净荷带宽。Obtain the total bandwidth of the second data stream at the input port, and determine the payload bandwidth of the second data stream at the input port according to the total bandwidth of the second data stream at the input port.
根据权利要求9-10任一项所述的速率调节方法，其特征在于，所述方法还包括：The rate adjustment method according to any one of claims 9-10, wherein the method further comprises:

获取所述第二数据流在输出端口的总带宽，并根据所述第二数据流在输出端口的总带宽确定所述第二数据流在输出端口的净荷带宽。Obtain the total bandwidth of the second data stream at the output port, and determine the payload bandwidth of the second data stream at the output port according to the total bandwidth of the second data stream at the output port.
根据权利要求11所述的速率调节方法，其特征在于，所述方法还包括：The rate adjustment method according to claim 11, wherein the method further comprises:

根据以太网带宽与FLEXE带宽之间的比例对所述第二数据流在输出端口的净荷带宽进行修正。The payload bandwidth of the second data stream at the output port is corrected according to the ratio between the Ethernet bandwidth and the FLEXE bandwidth.
根据权利要求9-12任一项所述的速率调节方法，其特征在于，所述方法还包括：The rate adjustment method according to any one of claims 9-12, wherein the method further comprises:

先后接收第三数据流和第四数据流；Receive the third data stream and the fourth data stream successively;

根据第三缓存占用量，在所述第三数据流中增加或删除第二比特数的空闲码块；Adding or deleting idle code blocks of the second number of bits in the third data stream according to the third buffer occupancy;

根据所述第三缓存占用量、所述第四数据流在输入端口的净荷带宽、所述第四数据流在输出端口的净荷带宽、所述第二比特数，获得第四缓存占用量；According to the third buffer occupancy, the payload bandwidth of the fourth data stream at the input port, the fourth data stream's payload bandwidth at the output port, and the second number of bits, the fourth buffer occupancy is obtained ；

根据所述第四缓存占用量，在所述第四数据流中增加或删除空闲码块；Adding or deleting idle code blocks in the fourth data stream according to the fourth buffer occupancy;

其中，所述第三数据流和所述第四数据流的流向与所述第一数据流和所述第二数据流的流向相反。Wherein, the flow directions of the third data flow and the fourth data flow are opposite to the flow directions of the first data flow and the second data flow.
根据权利要求13所述的速率调节方法，其特征在于，所述方法还包括：The rate adjustment method according to claim 13, wherein the method further comprises:

获取所述第四数据流在输入端口的总带宽，并根据所述第四数据流在输入端口的总带宽确定所述第四数据流在输入端口的净荷带宽。Obtain the total bandwidth of the fourth data stream at the input port, and determine the payload bandwidth of the fourth data stream at the input port according to the total bandwidth of the fourth data stream at the input port.
根据权利要求13-14任一项所述的速率调节方法，其特征在于，所述方法还包括：The rate adjustment method according to any one of claims 13-14, wherein the method further comprises:

获取所述第四数据流在输出端口的总带宽，并根据所述第四数据流在输出端口的总带宽确定所述第四数据流在输出端口的净荷带宽。Obtain the total bandwidth of the fourth data stream at the output port, and determine the payload bandwidth of the fourth data stream at the output port according to the total bandwidth of the fourth data stream at the output port.
根据权利要求14所述的速率调节方法，其特征在于，所述方法还包括：The rate adjustment method according to claim 14, wherein the method further comprises:

根据以太网带宽与FLEXE带宽之间的比例对所述第四数据流在输入端口的净荷带宽进行修正。The payload bandwidth of the fourth data stream at the input port is corrected according to the ratio between the Ethernet bandwidth and the FLEXE bandwidth.