WO2021119906A1 - 一种发光二极管 - Google Patents

一种发光二极管 Download PDF

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Publication number
WO2021119906A1
WO2021119906A1 PCT/CN2019/125580 CN2019125580W WO2021119906A1 WO 2021119906 A1 WO2021119906 A1 WO 2021119906A1 CN 2019125580 W CN2019125580 W CN 2019125580W WO 2021119906 A1 WO2021119906 A1 WO 2021119906A1
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Prior art keywords
layer
emitting diode
light emitting
light
insulating dielectric
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PCT/CN2019/125580
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English (en)
French (fr)
Inventor
王庆
马全扬
陈大钟
洪灵愿
彭康伟
林素慧
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厦门三安光电有限公司
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Priority to CN201980006009.4A priority Critical patent/CN111433921B/zh
Priority to PCT/CN2019/125580 priority patent/WO2021119906A1/zh
Priority to US17/303,153 priority patent/US20210280743A1/en
Publication of WO2021119906A1 publication Critical patent/WO2021119906A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape

Definitions

  • the present invention relates to the field of semiconductor optoelectronic technology, and more specifically, to a light emitting diode.
  • LED Light Emitting Diode
  • LEDs have the advantages of high luminous intensity, high efficiency, small size, long service life, etc., and is considered to be one of the most promising light sources at present.
  • LEDs have been widely used in daily life, such as lighting, signal display, backlights, car lights, and large-screen displays. At the same time, these applications also put forward higher requirements for the brightness and luminous efficiency of LEDs.
  • the front-mounted LED has high thermal resistance and poor heat dissipation due to the substrate, which limits its application under high currents.
  • flip chip came into being.
  • the structure of the traditional flip chip uses Ag mirror as the reflective layer material. Because Ag has strong activity, it is prone to migration.
  • the area of the silver mirror is smaller than the pGaN area of the light-emitting area, and a part of the sacrificed light-emitting area is used to prepare a protective layer to cover the Ag mirror reflection layer.
  • the reflectivity of Ag can only reach about 95%. Therefore, at present, the area and reflectivity of the highly reflective area on the front of the Ag-based flip-chip structure are relatively low, which affects the extraction of light and is not conducive to the increase of light efficiency.
  • This hollow DBR structure has a reflectivity of more than 99%, and at the same time, it can cover the entire front surface of the chip, which can greatly improve the reflection efficiency of the front surface of the chip, increase the light extraction efficiency of the chip, and thereby increase the light efficiency.
  • the present invention provides a light emitting diode, which includes a transparent substrate with a first surface; a semiconductor barrier crystal stack including a first conductivity type sequentially stacked on the first surface of the transparent substrate A semiconductor layer, an active layer, and a second conductive semiconductor layer; a DBR reflective layer, covering the top surface and sidewalls of the semiconductor barrier crystal stack, and having a first opening and a second opening; a first electrode and a second electrode, respectively
  • the first conductive type semiconductor layer and the second conductive type semiconductor layer are electrically connected through the first opening and the second opening; the DBR reflective layer contains a cavity structure.
  • the DBR reflective layer is composed of an insulating dielectric layer.
  • the DBR reflective layer is formed by alternately stacking N groups of first insulating dielectric layers and second insulating dielectric layers, where N ranges from 3 to 50, and the refractive index of the first insulating dielectric layer is smaller than that of the first insulating dielectric layer.
  • the refractive index of the second insulating medium layer is wet-etched by etching the first insulating medium layer without etching the second insulating medium layer to form the cavity.
  • the material of the first insulating dielectric layer is SiO 2 , SiONx, and SiNx
  • the material of the second insulating dielectric layer is TiO 2 , NB 2 O 5 , and Ta 2 O 5 .
  • the physical thickness of the first insulating dielectric layer is greater than the thickness of the second insulating dielectric layer.
  • the DBR reflective layer further includes a third insulating medium layer, which is located on the bottom and top layers of the DBR reflective layer, and has a refractive index lower than that of the second insulating medium layer.
  • An insulating dielectric layer is etched, and the second and third insulating dielectric layers are not etched to form the cavity.
  • the cavity is located in the first insulating dielectric layer, and the cavity is partially nested in the first insulating dielectric layer.
  • the cavity is partially located in the opening of the DBR reflective layer, and the opening is used to fill the electrode.
  • the holes are micron holes, and the size of the holes is 1 ⁇ m-50 ⁇ m.
  • the material of the third insulating dielectric layer is Al 2 O 3 .
  • the DBR reflective layer is formed by alternately stacking N groups of first insulating dielectric layers and second insulating dielectric layers, where N ranges from 3 to 50, and the first The refractive index of the insulating medium layer is smaller than the refractive index of the second insulating medium layer, the cavity is located in the first insulating medium layer, and the cavity is evenly nested in the first insulating medium layer, and the cavity is adjusted by the evaporation parameters get.
  • the cavity is a nano cavity, and the size of the cavity is 1 nm to 10 nm.
  • the transparent substrate includes a second surface opposite to the first surface, and the second surface is the main light-emitting surface.
  • the light emitting diode further includes a contact electrode formed on the second conductivity type semiconductor layer, and the DBR reflective layer covers the surface of the contact electrode.
  • the present invention also provides a light emitting diode package including a mounting substrate and at least one light emitting diode mounted on the mounting substrate, characterized in that at least one or more or all of the light emitting diodes are the aforementioned light emitting diodes.
  • the present invention also provides a light emitting diode module including a mounting substrate and multiple rows and multiple columns of light emitting diodes mounted on the mounting substrate, characterized in that at least one or more or all of the light emitting diodes are the aforementioned A light-emitting diode.
  • the multiple rows of light emitting diodes in the light emitting diode module include at least one row of red light emitting diodes, one row of green light emitting diodes, and one row of blue light emitting diodes.
  • the multiple rows and multiple columns of light-emitting diodes in the light-emitting diode module are all blue light-emitting diodes.
  • the present invention also provides an RGB display device, which includes a plurality of the aforementioned light-emitting diode modules spliced together.
  • the present invention also provides a backlight display screen, which includes a plurality of the aforementioned light-emitting diode modules spliced together to form a backlight light source.
  • the light-emitting diode designed by the present invention includes the following beneficial effects:
  • the refractive index difference between the DBR stacks becomes larger.
  • the hollow structure is mainly air medium, the refractive index difference of the medium in the DBR reflective layer becomes larger, and the reflectivity of the DBR reflective layer increases.
  • the DBR reflective layer can cover the entire surface of the semiconductor barrier crystal stack, and the area of the highly reflective area is increased, which increases the light extraction efficiency of the chip, thereby improving the luminous efficiency.
  • FIG. 1 is a schematic cross-sectional view of the light-emitting diode mentioned in Embodiment 1 of the present invention.
  • FIG. 2 is a schematic diagram of the distribution of the first opening and the second opening in the light emitting diode mentioned in Embodiment 1 of the present invention.
  • FIG. 3 is a graph of theoretical calculations of the angle-weighted reflectance inside the light-emitting diode (DBR cavity structure) and conventional LED (DBR cavity-free structure) chips mentioned in Embodiment 1 of the present invention.
  • FIG. 4 is a schematic cross-sectional view of the light-emitting diode mentioned in Embodiment 2 of the present invention.
  • FIG. 5 is a graph of theoretical calculations of angle-weighted reflectance inside the light-emitting diode (DBR cavity structure) and conventional LED (DBR cavity-free structure) chips involved in Embodiment 2 of the present invention.
  • 6 to 12 are structural schematic diagrams of the manufacturing process flow of the light-emitting diode mentioned in Embodiment 5 of the present invention.
  • FIG. 13 is a schematic cross-sectional view of the package structure mentioned in the seventh embodiment.
  • diagrams provided in this embodiment only illustrate the basic idea of the present invention in a schematic manner, so the diagrams only show the components related to the present invention instead of the number, shape, and shape of the components in actual implementation.
  • the type, quantity, and proportion of each component can be changed at will during actual implementation, and the component layout type may also be more complicated.
  • This embodiment provides the following light emitting diode, as shown in the schematic cross-sectional view of FIG. 1, which includes: 101: a transparent substrate; 102: a first conductivity type semiconductor layer; 103: an active layer; 104: a second conductivity type semiconductor layer 105: contact electrode; 106: DBR reflective layer; 107: first opening; 108: second opening, 109: first electrode; 110: second electrode.
  • the transparent substrate 101 may be an insulating substrate or a conductive substrate.
  • the transparent substrate 101 may be a growth substrate for growing the semiconductor barrier crystal stack, or the semiconductor barrier crystal stack may be bonded to the transparent substrate 101 through a transparent bonding layer.
  • the transparent substrate may include a sapphire substrate, a silicon carbide substrate, a silicon substrate, a gallium nitride substrate, an aluminum nitride substrate, and the like.
  • the transparent substrate 101 includes a first surface, a second surface, and sidewalls, wherein the first surface and the second surface are opposite.
  • the transparent substrate 101 may include a plurality of protrusions formed on at least a partial area on the first surface.
  • the plurality of protrusions of the transparent substrate 101 may be formed in regular and/or irregular patterns.
  • the transparent substrate 101 may be a patterned sapphire substrate.
  • the thickness of the transparent substrate 101 is between 40 and 300 microns. In the case of thicker, the thickness of the transparent substrate is 80 to 300 microns. In the case of thinner, the thickness of the transparent substrate is such as 40 microns or more and 80 microns. Below or thinner, 40 microns or more and 60 microns or less.
  • the second surface of the transparent substrate 101 is the light-emitting surface of the light-emitting diode, and is the main light-emitting surface.
  • the semiconductor barrier layer stack includes a first conductivity type semiconductor layer 102, an active layer 103, and a second conductivity type semiconductor layer 103 that are sequentially stacked on the first surface of the transparent substrate 101.
  • the first conductive type semiconductor layer 102 may be composed of a III-V group or II-VI group compound semiconductor, and may be doped with a first dopant.
  • the first conductivity type semiconductor layer 102 may be composed of a semiconductor material having the chemical formula In X1 Al Y1 Ga 1-X1-Y1 N (0 ⁇ X1 ⁇ 1, 0 ⁇ Y1 ⁇ 1, 0 ⁇ X1+Y1 ⁇ 1), such as GaN , AlGaN, In GaN, InAlGaN, etc.
  • the first dopant may be an n-type dopant, such as Si, Ge, Sn, Se, and Te.
  • the first conductive type semiconductor layer doped with the first dopant is an n-type semiconductor layer.
  • the active layer 103 is provided between the first conductivity type semiconductor layer 102 and the second conductivity type semiconductor layer 104.
  • the active layer 103 is a layer in which electrons (or holes) injected through the first conductivity type semiconductor layer and holes (or electrons) injected through the second conductivity type semiconductor layer are combined.
  • the active layer may have, but is not limited to, any of a single-well structure, a multi-well structure, a single quantum well structure, and a multiple quantum well structure.
  • the active layer includes a well layer and a barrier layer, wherein the barrier layer has a larger band gap than the well layer.
  • the second conductive type semiconductor layer 104 is formed on the active layer 103, and may be composed of a group III-V or group II-VI compound semiconductor.
  • the second conductivity type semiconductor layer may also be doped with a second dopant.
  • the second conductivity type semiconductor layer 104 may be composed of a semiconductor material having the chemical formula In X2 Al Y2 Ga 1-X2-Y2 N (0 ⁇ X2 ⁇ 1, 0 ⁇ Y2 ⁇ 1, 0 ⁇ X2+Y2 ⁇ 1), or selected from Materials of AlInN, AlGaAs, GaP, GaAs, GaAsP and AlGaInP.
  • the second dopant is a P-type dopant, such as Mg, Zn, Ca, Sr, and Ba
  • the second conductive type semiconductor layer doped with the second dopant is a P-type semiconductor layer.
  • the semiconductor barrier layer stack may include at least one hole that penetrates the active layer 103 and the second conductivity type semiconductor layer 104 at least partially to expose the first conductivity type semiconductor layer 102.
  • the hole partially exposes the first conductive type semiconductor layer 102, and the side surface of the hole can be surrounded by the light emitting layer 103 and the second conductive type semiconductor layer 104.
  • the semiconductor barrier layer stack may include several mesas, the mesas including the active layer 103 and the second conductivity type semiconductor layer 104.
  • the mesa is located on a part of the surface of the first conductivity type semiconductor layer 102.
  • the semiconductor barrier layer preferably includes a mesa, and the mesa includes an active layer 103 and a second conductivity type semiconductor layer 104.
  • a contact electrode 105 is located on the second conductivity type semiconductor layer 104.
  • the contact electrode 105 may form an ohmic contact with the second conductive type semiconductor layer 104.
  • the contact electrode 105 may include a transparent electrode.
  • the transparent electrode may include, for example, indium tin oxide, zinc oxide, zinc indium tin oxide, indium zinc oxide, zinc tin oxide, gallium indium tin oxide, indium gallium oxide, zinc gallium oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide At least one of a transparent conductive oxide such as Ni/Au and a transparent metal layer such as Ni/Au.
  • the conductive oxide may further include various dopants.
  • the ohmic contact efficiency between the contact electrode 105 containing a light-transmitting conductive oxide and the second conductive type semiconductor layer 104 is high.
  • the contact resistance between a conductive oxide such as ITO or ZnO and the second conductive semiconductor layer 104 is lower than the contact resistance between a metallic electrode and the second conductive semiconductor layer 104. Therefore, the contact electrode 105 including a conductive oxide is used.
  • Vf forward voltage
  • the probability of the conductive oxide being peeled off from the nitride-based semiconductor layer is lower. Therefore, the light emitting diode having the contact electrode 105 including the conductive oxide has higher reliability.
  • the DBR reflective layer covers the top surface and sidewalls of the semiconductor barrier crystal stack. Specifically, when the contact electrode 105 is present, the top surface and sidewalls of the contact electrode 105 and the semiconductor barrier crystal stack not covered by the contact electrode 105 are all covered by the DBR reflective layer 106.
  • the DBR reflective layer 106 covers one surface and sidewalls of the semiconductor barrier crystal stack.
  • the DBR reflective layer 106 covers one surface and sidewalls of the semiconductor barrier crystal stack.
  • the contact electrode 105 When the light radiated by the active layer reaches the surface of the DBR reflective layer 106 through the contact electrode 105, most of the light can be reflected back to the DBR reflective layer 106 through the DBR reflective layer 106.
  • part of the light exits to the second surface side of the transparent substrate 101, which reduces light passing through the surface and sidewalls of the semiconductor barrier crystal stack and causes light loss.
  • the DBR reflective layer 106 is formed by alternately stacking N groups of first insulating dielectric layers 106a and second insulating dielectric layers 106b, wherein the range of N is 3-50.
  • the refractive index of the first insulating medium layer 106a is smaller than the refractive index of the second insulating medium layer 106b.
  • the material of the first insulating dielectric layer 106a is SiO 2 , SiONx, and SiNx
  • the material of the second insulating dielectric layer 106 b is TiO 2 , NB 2 O 5 , and Ta 2 O 5 .
  • the DBR reflective layer 106 may alternately deposit TiO 2 layers/SiO 2 layers.
  • the DBR reflective layer 106 covers at least the top surface of the second conductive semiconductor layer, and reflects at least 80% or further at least 90% of the light that reaches the surface of the active layer.
  • the thickness of the layer 106a is greater than the thickness of the second insulating dielectric layer 106b.
  • the DBR reflective layer 106 has at least a first opening 107 and a second opening 108, and the first electrode 109 and the second electrode 110 are respectively electrically connected to the first conductive semiconductor layer 102 and the second opening through the first opening 107 and the second opening 108 filled with the DBR.
  • a two-conductivity semiconductor layer 104 As shown in FIG. 2, there may be multiple first openings and second openings. Preferably, the number of first openings and second openings are both greater than or equal to 3, for example, the first openings and/or the second openings There are more than 5 or more than 10, and the distribution between the first opening and the second opening and/or between the first opening and the first opening and/or the second opening and the second opening is equally spaced.
  • the cavity 106d is formed by wet etching by etching the first insulating dielectric layer without etching the second insulating dielectric layer.
  • the cavity 106d is partially nested in the first insulating dielectric layer 106a.
  • the cavity 106d is a micron cavity, and the size of the cavity is preferably 1 ⁇ m to 50 ⁇ m.
  • the first and last layers of the DBR reflective layer can be composed of a third insulating dielectric layer, wherein The refractive index of the third insulating medium layer is lower than that of the second insulating medium layer, and the material of the third insulating medium layer is preferably Al 2 O 3 .
  • the refractive index n1 of the first insulating dielectric layer material SiO 2 is 1.46
  • the refractive index n2 of the second insulating dielectric layer material TiO 2 is 2.5.
  • a cavity is introduced into the DBR reflective layer, and the cavity is an air medium. The refractive index is 1. As shown in Figure 3, through software simulation and calculation, a cavity structure is introduced into the DBR reflective layer, the refractive index difference between the DBR stacks becomes larger, and the reflectivity is improved.
  • the reflectivity of the blue band can be increased by 2 ⁇ 3%, the reflectivity of the red light segment can be increased by 5 to 6%.
  • the DBR reflective layer can completely cover the front surface of the light-emitting diode, and the area of the highly reflective area is increased, which increases the light extraction efficiency of the chip, thereby improving the luminous efficiency.
  • the first electrode 109 and the second electrode 110 are formed on the surface of the DBR reflective layer 106.
  • the first electrode 109 is electrically connected to the first conductive type semiconductor layer 102 through the first opening 107
  • the second electrode 110 is electrically connected to the contact electrode 105 on the surface of the second conductive type semiconductor layer 104 through the second opening 108.
  • the resistance between the second electrode 110 and the second conductivity type semiconductor layer 104 is higher than the resistance between the contact electrode 105 and the second conductivity type semiconductor layer 104, so as to minimize the current directly between the second electrode 110 and the second conductivity type semiconductor layer 104.
  • the contact position of the semiconductor layer 104 is crowded.
  • the cavity in embodiment 1 is partially nested in the first insulating dielectric layer and is obtained by wet etching; and this embodiment is used as another alternative to embodiment 1, as shown in FIG. 4
  • the cavities are uniformly distributed in the first insulating dielectric layer and are prepared by adjusting the evaporation parameters.
  • This cavity is a nano cavity.
  • the size of the cavity is 1 nm to 10 nm.
  • the voids 106d are evenly distributed in the first insulating dielectric layer.
  • the void ratio reaches 50%, it is calculated by software simulation, as shown in FIG. 5, the blue light segment reflectivity It can increase by 1 to 2%, and the reflectivity of the red light segment can be increased by 2 to 3%.
  • a transparent substrate 101 is first provided, and a semiconductor barrier crystal stack is formed on the transparent substrate 101.
  • the semiconductor barrier crystal stack includes a first conductive semiconductor layer 102 and a light emitting layer stacked in sequence. 103 and a second conductivity type semiconductor layer 104.
  • masking is performed through a photomask to etch part of the second conductivity type semiconductor layer 104 and the active layer 103, exposing part of the first conductivity type semiconductor layer 102 and forming several mesas, which include the light-emitting layer 103 and The second conductivity type semiconductor layer 104.
  • an evaporation or sputtering process is used to form the contact electrode 105, such as a transparent conductive layer of ITO.
  • the DBR reflective layer 106 As shown in FIG. 9, an evaporation or sputtering process is used to form the DBR reflective layer 106, and the DBR reflective layer covers the contact electrode 105 and the exposed surface and sidewalls of the semiconductor barrier layer stack.
  • the DBR is preferably deposited alternately with SiO 2 and TiO 2 .
  • the first and last layers of the DBR reflective layer can be made of a third insulating dielectric layer
  • the material of the third insulating dielectric layer is preferably Al 2 O 3 .
  • At least a first opening 107 and a second opening 108 are formed in the DBR reflective layer 106 by dry etching.
  • a wet etching method is used to make the solution enter the opening, and the first insulating dielectric layer in the DBR structure is etched sideways, and the second insulating dielectric layer is not etched to form a cavity-containing DBR stack.
  • the first insulating dielectric layer is SiO 2 , and a cavity is formed around the opening of the DBR reflective layer by wet etching.
  • a first electrode 109 and a second electrode 110 are respectively formed on the surface of the DBR reflective layer 106.
  • the first electrode 109 is electrically connected to the first conductive semiconductor layer 102 through the first opening 107, and the second electrode 110 passes through
  • the second opening 108 is electrically connected to the second conductivity type semiconductor layer 104.
  • the first electrode 109 and the second electrode 110 include a contact layer and a eutectic layer, and the contact layer and the eutectic layer are made of metal.
  • the semiconductor barrier crystal stack includes a first conductive semiconductor layer 102, a light emitting layer 103, and a second conductive semiconductor layer 104 stacked in sequence .
  • contact electrode 105 such as a transparent conductive layer of ITO.
  • the DBR reflective layer 106 is formed by vapor deposition, and the DBR reflective layer covers the contact electrode 105 and the exposed surface and sidewalls of the semiconductor barrier crystal stack.
  • the first insulating dielectric layer is SiO 2 , and by adjusting the evaporation parameters, uniformly distributed cavities are formed in the first insulating dielectric layer.
  • the size of the hole is a nano-hole, and the size of the hole is 1 nm to 10 nm.
  • At least the first opening 107 and the second opening 108 are formed in the DBR reflective layer 106 by dry etching.
  • a first electrode 109 and a second electrode 110 are respectively formed on the surface of the DBR reflective layer 106.
  • the first electrode 109 is electrically connected to the first conductivity type semiconductor layer 102 through the first opening 107
  • the second electrode 110 is connected to the second electrode through the second opening 108.
  • the two-conductivity semiconductor layer 104 is electrically connected.
  • the first electrode 109 and the second electrode 110 include a contact layer and a eutectic layer, and the contact layer and the eutectic layer are made of metal.
  • the light-emitting diode provided by the present invention can be widely used in display or backlight packaging or applications, and can especially meet the high-brightness requirements of backlight products.
  • this embodiment provides a package as shown in FIG. 12.
  • At least one light-emitting diode in Embodiment 1 or 2 is mounted on a mounting substrate 30, which is an insulating substrate, such as a packaging mold for RGB display screens.
  • a mounting substrate 30 For a group substrate or a module substrate for backlight display, one surface of the mounting substrate 30 has a first electrode terminal 301 and a second electrode terminal 302 that are electrically isolated.
  • the light emitting diode is located on a surface of the mounting substrate 30, and the first electrode 109 and the second electrode 110 of the light emitting diode are connected to the first electrode terminal 301 and the second electrode terminal 302 through the first coupling portion 303 and the second coupling portion 304, respectively.
  • the first bonding portion 303 and the second bonding portion 304 include but are not limited to solder, such as eutectic solder or reflow solder.

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Abstract

本发明提供如下发光二极管，其包括：透明衬底，该透明衬底具备第一表面；半导体垒晶叠层，包括在透明衬底的第一表面依次堆叠的第一导电型半导体层、活性层和第二导电型半导体层；DBR反射层，覆盖所述半导体垒晶叠层的顶表面以及侧壁，具有第一开口和第二开口；第一电极和第二电极，分别通过所述第一开口和第二开口与所述第一导电型半导体层和第二导电型半导体层电连接；DBR反射层中含有空洞。本发明通过在DBR反射层中引入空洞使DBR叠层之间具有更大的折射率差，使反射率得到了提升，从而提高发光效率。

Description

一种发光二极管 技术领域
本发明涉及半导体光电技术领域，更具体地说，涉及的是一种发光二极管。
背景技术
发光二极管(Light Emitting Diode，简称LED)具有发光强度大、效率高、体积小、使用寿命长等优点，被认为是当前最具有潜力的光源之一。近年来，LED已在日常生活中得到广泛应用，例如照明、信号显示、背光源、车灯和大屏幕显示等领域，同时这些应用也对LED的亮度、发光效率提出了更高的要求。
发光二极管主要有三种方式：倒装、正装及垂直。其中正装LED由于衬底的热阻较高，散热差，限制了其在大电流下的应用。为了解决这一难题，倒装芯片应运而生。传统倒装芯片的结构，使用Ag镜为反射层材料。由于Ag具有很强的活性，容易发生迁移。在实际设计中，银镜的面积小于发光区的pGaN面积，这牺牲的一部分发光区用来制备保护层覆盖Ag镜反射层。另外，Ag的反射率只能达到95％左右。因此，目前Ag基倒装结构正面的高反射区域面积及其反射率都较低，从而影响光的萃取，不利于光效的增加。
发明概述
技术问题
问题的解决方案
技术解决方案
为了解决以上的问题，我们引入一种空洞型DBR结构取代Ag镜反射层应用于倒装芯片中。这种空洞型DBR结构具有99％以上的反射率，同时其可以覆盖整个芯片正面，可以极大的提高芯片正面的反射效率，增加芯片的光萃取效率，从而增加光效。
为实现上述目的，本发明提供一种发光二极管，其包括透明衬底，该透明衬底具备第一表面；半导体垒晶叠层，包括在透明衬底的第一表面依次堆叠的第一导电型半导体层、活性层和第二导电型半导体层；DBR反射层，覆盖所述半导 体垒晶叠层的顶表面以及侧壁，具有第一开口和第二开口；第一电极和第二电极，分别通过所述第一开口和第二开口与所述第一导电型半导体层和第二导电型半导体层电连接；所述DBR反射层中含有空洞结构。
优选地，所述DBR反射层由绝缘介质层组成。
优选地，所述DBR反射层由N组第一绝缘介质层和第二绝缘介质层交替堆叠而成，其中N的范围为3～50，所述第一绝缘介质层的折射率小于所述第二绝缘介质层的折射率，采用湿法蚀刻通过对第一绝缘介质层蚀刻，对第二绝缘介质层不蚀刻形成所述空洞。
优选地，所述第一绝缘介质层的材料为SiO 2、SiONx、SiNx，所述第二绝缘介质层的材料为TiO 2、NB 2O 5、Ta 2O 5。
优选地，所述第一绝缘介质层的物理厚度大于第二绝缘介质层的厚度。
更优选地，所述DBR反射层还包括第三绝缘介质层，位于所述DBR反射层的底层和顶层，折射率低于所述第二绝缘介质层的折射率，采用湿法蚀刻通过对第一绝缘介质层蚀刻，对第二和第三绝缘介质层不蚀刻形成所述空洞。
优选地，所述空洞位于第一绝缘介质层中，且空洞局部嵌套在第一绝缘介质层中。
更优选地，所述空洞局部地位于DBR反射层的开口中，该开口用于填充电极。
优选地，所述孔洞为微米空洞，空洞大小为1μm～50μm。
优选地，所述第三绝缘介质层的材料为Al 2O 3。
作为本发明的另一种实施方式，优选地，所述DBR反射层由N组第一绝缘介质层和第二绝缘介质层交替堆叠而成，其中N的范围为3～50，所述第一绝缘介质层的折射率小于所述第二绝缘介质层的折射率，所述空洞位于第一绝缘介质层中，且空洞均匀的嵌套在第一绝缘介质层中，该空洞通过调整蒸镀参数得到。
优选地，所述空洞为纳米空洞，空洞大小为1nm～10nm。
优选地，所述透明衬底包括与第一表面相对的第二表面，第二表面为主要出光面。
优选地，所述发光二极管还包括接触电极，形成于所述第二导电型半导体层上，所述DBR反射层覆盖该接触电极的表面。
本发明同时提供一种发光二极管封装体，包括安装基板和安装在所述安装基板上的至少一个发光二极管，其特征在于，所述发光二极管至少一个或多个或全部为前述的发光二极管。
本发明同时还提供一种发光二极管模组，包括安装基板和安装在所述安装基板上的多行和多列发光二极管，其特征在于，所述发光二极管至少一个或多个或全部为前述的一种发光二极管。
优选地，所述发光二极管模组中的多列发光二极管至少包括一列红光发光二极管、一列绿光发光二极管和一列蓝光发光二极管。
优选地，所述发光二极管模组中的多行以及多列发光二极管都是蓝光发光二极管。
本发明同时还提供一种RGB显示装置，包括多个前述的发光二极管模组拼接在一起。
本发明同时还提供一种背光显示屏，包括多个前述的发光二极管模组拼接在一起形成背光光源。
发明的有益效果
有益效果
如上所述，本发明设计的发光二极管，包括如下有益效果：
1)通过在DBR反射层中引入空洞结构，DBR叠层间的折射率差变大，空洞结构中主要是空气介质，DBR反射层中介质的折射率差异变大，DBR反射层的反射率增大，从而提高发光效率；2)DBR反射层可覆盖半导体垒晶叠层的整个表面，高反射区域面积增大，增加芯片的光萃取效率，从而提高发光效率。
对附图的简要说明
附图说明
图1为本发明实施例1中提到的发光二极管的剖面示意图。
图2为本发明实施例1中所提到的发光二极管中第一开口和第二开口的分布示意图。
图3为本发明实施例1提到的发光二极管(DBR空洞结构)和常规LED(DBR无空洞结构)芯片内部各个角度加权反射率理论计算的曲线图。
图4为本发明实施例2中提到的发光二极管的剖面示意图。
图5为本发明实施例2涉及的发光二极管(DBR空洞结构)和常规LED(DBR无空洞结构)芯片内部各个角度加权反射率理论计算的曲线图。
图6～图12为本发明实施例5中所提及的发光二极管的制作工艺流程的结构示意图。
图13为实施例7中所提及的封装结构的剖面示意图。
图中元件标号说明：
101                透明衬底
102                第一导电型半导体层
103                活性层
104                第二导电型半导体层
105                接触电极
106                DBR反射层
107                第一开口
108                第二开口
109                第一电极
110                第二电极
30                 安装基板
301                第一电极端子
302                第二电极端子
303                第一结合部
304                第二结合部
10                 发光二极管
106a               第一绝缘介质层
106b               第二绝缘介质层
106c               第三绝缘介质层
106d               空洞
发明实施例
本发明的实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明 书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例1
本实施例提供如下一种发光二极管，如图1所示的剖面示意图，其包括：101：透明衬底；102：第一导电型半导体层；103：活性层；104：第二导电型半导体层；105：接触电极；106：DBR反射层；107：第一开口；108：第二开口，109：第一电极；110：第二电极。
透明衬底101可为绝缘性基板或导电性基板。透明衬底101可为用以使半导体垒晶叠层生长的生长基板，也可以是半导体垒晶叠层通过透明键合层键合在透明衬底101上。透明衬底可包括蓝宝石基板、碳化硅基板、硅基板、氮化镓基板、氮化铝基板等。透明衬底101包括第一表面、第二表面以及侧壁，其中第一表面和第二表面相对。透明衬底101可包括形成在第一表面上的至少一部分区域的多个突出。透明衬底101的多个突出可形成为规则和/或不规则的图案。在本实施例中，所述透明衬底101可为经图案化的蓝宝石基板。
透明衬底101的厚度介于40～300微米之间，较厚的情况下，透明衬底的厚度为80～300微米，较薄的情况下，透明衬底的厚度如40微米以上、80微米以下或者更薄的情况40微米以上、60微米以下。
所述透明衬底101的第二表面为发光二极管的出光面，且为主要的出光面。
半导体垒晶叠层包括依次堆叠在透明衬底101的第一表面的第一导电型半导体层102、活性层103和第二导电型半导体层103。
第一导电型半导体层102可以由III-V族或II-VI族化合物半导体组成，并且可以掺杂有第一掺杂剂。第一导电型半导体层102可以由具有化学式In X1Al Y1Ga 1-X1-Y1N(0≤X1≤1，0≤Y1≤1，0≤X1+Y1≤1)的半导体材料组成，例如GaN，AlGaN，In GaN，InAlGaN等。另外，第一掺杂剂可以是n型掺杂剂，例如Si，Ge，Sn，Se和Te。当第一掺杂剂是n型掺杂剂时，掺杂有第一掺杂剂的第一导电型半导体层为n型半导体层。
活性层103设置在第一导电型半导体层102和第二导电型半导体层104之间。活性层103为通过第一导电型半导体层注入的电子(或空穴)与通过第二导电型半导体层注入的空穴(或电子)结合的层。活性层可以具有但不限于单阱结构，多阱结构，单量子阱结构，多量子阱结构中的任何一种结构。活性层包含阱层和垒层，其中垒层具有比阱层更大的带隙。
第二导电型半导体层104形成在活性层103上，并且可以由III-V族或II-VI族化合物半导体组成。第二导电型半导体层也可以掺杂第二掺杂剂。第二导电型半导体层104可由具有化学式In X2Al Y2Ga 1-X2-Y2N(0≤X2≤1，0≤Y2≤1，0≤X2+Y2≤1)的半导体材料组成，或选自AlInN，AlGaAs，GaP，GaAs，GaAsP和AlGaInP的材料。当第二掺杂剂是P型掺杂剂，例如Mg，Zn，Ca，Sr和Ba时，掺杂第二掺杂剂的第二导电型半导体层为P型半导体层。
半导体垒晶叠层可包括至少局部地贯通活性层103及第二导电型半导体层104而露出第一导电型半导体层102的至少一个孔。孔使第一导电型半导体层102局部地露出，孔的侧面可由发光层103及第二导电型半导体层104包围。或者，半导体垒晶叠层可包括数个台面，所述台面包括活性层103及第二导电型半导体层104。台面位于第一导电型半导体层102的部分表面上。本实施例中，如图所示，优选半导体垒晶叠层包括台面，台面包括活性层103和第二导电型半导体层104。
为了在第二电极108与第二导电型半导体层104之间形成电性连接，一接触电极105位于第二导电型半导体层104上。接触电极105可与第二导电型半导体层104形成欧姆接触。接触电极105可包括透明电极。该透明电极可包括如氧化铟锡、氧化锌、氧化锌铟锡、氧化铟锌、氧化锌锡、氧化镓铟锡、氧化铟镓、氧化锌镓、铝掺杂氧化锌、氟掺杂氧化锡等的透光性导电氧化物、及如Ni/Au等的透光性金属层中的至少一种。所述导电性氧化物还可包括各种掺杂剂。尤其，包含透光性导电氧化物的接触电极105与第二导电型半导体层104的欧姆接触效率较 高。例如ITO或ZnO等的导电性氧化物与第二导电型半导体层104的接触电阻低于金属性电极与第二导电型半导体层104的接触电阻，因此通过应用包括导电性氧化物的接触电极105，可减少发光二极管芯片的正向电压(Vf)而提高发光效率。并且，与金属性电极相比，导电性氧化物从氮化物类半导体层剥离的概率较低，因此具有包括导电性氧化物的接触电极105的发光二极管具有较高的可靠性。
DBR反射层覆盖所述半导体垒晶叠层的顶表面和侧壁。具体的，当存在接触电极105时，接触电极105以及未被接触电极105覆盖的半导体垒晶叠层的顶表面和侧壁均被DBR反射层106覆盖。
通过DBR反射层106覆盖半导体垒晶叠层的一表面和侧壁，当活性层辐射的光通过接触电极105到达DBR反射层106的表面时，可通过DBR反射层106反射大部分的光返回至半导体垒晶叠层中，并且部分光线至透明衬底101的第二表面侧出光，减少光从半导体垒晶叠层的表面以及侧壁穿出导致光损失。
DBR反射层106由N组第一绝缘介质层106a、第二绝缘介质层106b交替堆叠而成，其中N的范围为3～50。所述第一绝缘介质层106a的折射率小于所述第二绝缘介质层106b的折射率。所述第一绝缘介质层106a材料为SiO 2、SiONx、SiNx，第二绝缘介质层106b材料为TiO 2、NB 2O 5、Ta 2O 5。在一些实施例中，DBR反射层106可呈交替地沉积TiO 2层/SiO 2层。
理论上，DBR反射层106至少覆盖在第二导电型半导体层的顶表面，对所述活性层辐射波段到达其表面的至少80％或者进一步的至少90％比例的光进行反射，第一绝缘介质层106a的厚度大于第二绝缘介质层106b的厚度。
DBR反射层106具有至少第一开口107和第二开口108，第一电极109和第二电极110通过填充DBR的第一开口107和第二开口108分别电连接第一导电型半导体层102和第二导电型半导体层104。如图2所示，第一开口和第二开口可以是多个的，优选地，第一开口和第二开口的个数均为大于等于3个，例如其中第一开口和/或第二开口为5个以上或者10个以上，且第一开口和第二开口之间和/或者第一开口与第一开口之间和/或第二开口与第二开口之间为等间距的分布。采用湿法蚀刻通过对第一绝缘介质层蚀刻，对第二绝缘介质层不蚀刻形成所述空洞106d。 该空洞106d局部嵌套在第一绝缘介质层106a中。该空洞106d为微米空洞，空洞大小优选为1μm～50μm。通过第一开口和第二开口的这种分布，可以实现发光二极管整个面上的反射率的提升，从而改善发光二极管的发光效率。
为了将空洞完全包覆在DBR结构内部，提高整个器件在高温高湿环境中的可靠性，以及保证整体DBR结构的绝缘性，优选DBR反射层的首末层可由第三绝缘介质层组成，其中第三绝缘介质层的折射率低于第二绝缘介质层，优选第三绝缘介质层材料为Al 2O 3。
通过湿法蚀刻方式在DBR反射层106中引入空洞106d，可使DBR反射叠层间的折射率差变大，DBR反射层106的反射率增大，发光二极管的取光效率也跟着增大。在本实施例中，第一绝缘介质层材料SiO 2的折射率n1为1.46，第二绝缘介质层材料TiO 2的折射率n2为2.5，在DBR反射层中引入空洞，空洞处为空气介质，折射率为1，如图3所示，通过软件模拟计算，在DBR反射层中引入空洞结构，DBR叠层间的折射率差变大，反射率得到提升，其中蓝光段反射率可增加2～3％、红光段反射率可增加5～6％。同时，DBR反射层可完全覆盖发光二极管的正面，高反射区域面积增大，增加芯片的光萃取效率，从而提高发光效率。
第一电极109和第二电极110形成在DBR反射层106的表面上。第一电极109通过第一开口107与第一导电型半导体层102形成电连接，第二电极110通过第二开口108与第二导电型半导体层104表面的接触电极105形成电连接。优选的是第二电极110与第二导电型半导体层104之间的电阻高于接触电极105与第二导电型半导体层104的电阻，以尽量减少电流直接在第二电极110与第二导电型半导体层104接触的位置拥挤。
实施例2
与实施例1的区别在于，实施例1中的空洞局部嵌套在第一绝缘介质层中，通过湿法蚀刻方式获得；而本实施例作为实施例1的另外一种替换方式，如图4所示，所述空洞均匀分布在第一绝缘介质层中，通过调整蒸镀参数制备得到。该空洞为纳米空洞。优选地，该空洞大小为1nm～10nm。
通过调整蒸镀参数在DBR反射层106中引入空洞，该空洞106d均匀分布在第一绝缘介质层中，当空洞率达到50％时，通过软件模拟计算，如图5所示，蓝光段 反射率可增加1～2％、红光段反射率可增加2～3％。
实施例3
下面对上述实施例1的发光二极管的制作工艺进行详细的说明。
如图6所示，首先提供一透明衬底101，于所述透明衬底101上形成半导体垒晶叠层，所述半导体垒晶叠层包括依次层叠的第一导电性半导体层102、发光层103以及第二导电型半导体层104。
如图7所示，通过光罩进行掩膜，蚀刻部分第二导电型半导体层104、活性层103，露出部分第一导电型半导体层102并形成数个台面，数个台面包括发光层103和第二导电型半导体层104。
如图8所示，采用蒸镀或溅镀工艺形成接触电极105，如ITO透明导电层。
如图9所示，采用蒸镀或溅镀工艺形成DBR反射层106，该DBR反射层覆盖在接触电极105上以及暴露的半导体垒晶叠层的表面、侧壁。本实施例中，DBR优选为交替沉积SiO 2和TiO 2。为了将空洞完全包覆在DBR结构内部，提高整个器件在高温高湿环境中的可靠性，以及保证整体DBR结构的绝缘性，更优选地，DBR反射层的首末层可由第三绝缘介质层组成，在本实施例中，优选第三绝缘介质层材料为Al 2O 3。
如图10所示，通过干法蚀刻，在DBR反射层106中至少形成第一开口107和第二开口108。
如图11所示，使用湿法蚀刻方法，使溶液进入所述开口，侧向蚀刻DBR结构中的第一绝缘介质层，不蚀刻第二绝缘介质层使其形成含空洞的DBR叠层。本实施例中，第一绝缘介质层为SiO 2，通过湿法蚀刻的方式，在DBR反射层的开口周围形成空洞。
如图12所示，在DBR反射层106的表面分别制作第一电极109和第二电极110，第一电极109通过第一开口107与第一导电型半导体层102电连接，第二电极110通过第二开口108与第二导电型半导体层104电连接。第一电极109和第二电极110包括接触层和共晶层，该接触层和共晶层为金属材质。
实施例4
下面对上述实施例2的发光二极管的制作工艺进行详细的说明。
首先提供一衬底101，于所述衬底上形成半导体垒晶叠层，所述半导体垒晶叠层包括依次层叠的第一导电性半导体层102、发光层103以及第二导电型半导体层104。
通过光罩进行掩膜，蚀刻部分第二导电型半导体层104、活性层103，露出部分第一导电型半导体层102并形成数个台面，数个台面包括发光层103和第二导电型半导体层104。
采用蒸镀或溅镀工艺形成接触电极105，如ITO透明导电层。
采用蒸镀形成DBR反射层106，该DBR反射层覆盖在接触电极105上以及暴露的半导体垒晶叠层的表面、侧壁。通过调试镀膜过程中的镀膜参数，在镀第一绝缘介质层时，形成不致密的结构，在其中引入一些小气孔。在本实施例中，第一绝缘介质层为SiO 2，通过调整蒸镀参数，在第一绝缘介质层形成均匀分布的空洞。该空洞大小为纳米空洞，空洞大小为1nm～10nm。
通过干法蚀刻在DBR反射层106中至少形成第一开口107和第二开口108。
在DBR反射层106的表面分别制作第一电极109和第二电极110，第一电极109通过第一开口107与第一导电型半导体层102电连接，第二电极110通过第二开口108与第二导电型半导体层104电连接。第一电极109和第二电极110包括接触层和共晶层，该接触层和共晶层为金属材质。
实施例5
本发明提供的发光二极管可以广泛运用于显示或背光的封装体或应用上，尤其可以满足背光产品的高亮度需求。
具体地，本实施例提供如图12所示的封装体，至少实施例1或2中的一个发光二极管安装到安装基板30上，安装基板30为绝缘性基板，如RGB显示屏用的封装模组基板或背光显示用的模组基板，安装基板30的一表面具有电隔离的第一电极端子301和第二电极端子302。发光二极管位于安装基板30的一表面上，发光二极管的第一电极109和第二电极110分别通过第一结合部303和第二结合部304与第一电极端子301和第二电极端子302连接。第一结合部303和第二结合部304包括但不限于是焊料，如共晶焊或回流焊料。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何 熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，这样的修改和变型均落入由所附权利要求所限定的范围之内。

Claims (20)

  1. 一种发光二极管，其特征在于，包括：
    透明衬底，该透明衬底具备第一表面；
    半导体垒晶叠层，包括在透明衬底的第一表面依次堆叠的第一导电型半导体层、活性层和第二导电型半导体层；
    DBR反射层，覆盖所述半导体垒晶叠层的顶表面以及侧壁，具有第一开口和第二开口；
    第一电极和第二电极，分别通过所述第一开口和第二开口与所述第一导电型半导体层和第二导电型半导体层电连接；
    所述DBR反射层中含有空洞。
  2. 根据权利要求1所述的一种发光二极管，其特征在于，所述DBR反射层由绝缘介质层组成。
  3. 根据权利要求2所述的一种发光二极管，其特征在于，所述DBR反射层由N组第一绝缘介质层和第二绝缘介质层交替堆叠而成，其中N的范围为3～50，所述第一绝缘介质层的折射率小于所述第二绝缘介质层的折射率，采用湿法蚀刻通过对第一绝缘介质层蚀刻，对第二绝缘介质层不蚀刻形成所述空洞。
  4. 根据权利要求3所述的一种发光二极管，其特征在于，所述第一绝缘介质层的材料为SiO 2、SiONx、SiNx，所述第二绝缘介质层的材料为TiO 2、NB 2O 5、Ta 2O 5。
  5. 根据权利要求3所述的一种发光二极管，其特征在于，所述第一绝缘介质层的物理厚度大于第二绝缘介质层的厚度。
  6. 根据权利要求3所述的一种发光二极管，所述DBR反射层还包括第三绝缘介质层，位于所述DBR反射层的底层和顶层，折射率低于所述第二绝缘介质层的折射率，采用湿法蚀刻通过对第一绝缘介质层蚀刻，对第二和第三绝缘介质层不蚀刻形成所述空洞。
  7. 根据权利要求3或6所述的一种发光二极管，其特征在于，所述空洞位于第一绝缘介质层中，且空洞局部嵌套在第一绝缘介质层中 。
  8. 根据权利要求7所述的一种发光二极管，其特征在于，所述空洞局部地分布在DBR反射层的开口处，该DBR开口用于填充电极。
  9. 根据权利要求7所述的一种发光二极管，其特征在于，所述空洞为微米空洞，空洞大小为1μm～50μm。
  10. 根据权利要求6所述的一种发光二极管，所述第三绝缘介质层的材料为Al 2O 3。
  11. 根据权利要求1所述的一种发光二极管，所述DBR反射层由N组第一绝缘介质层和第二绝缘介质层交替堆叠而成，其中N的范围为3～50，所述第一绝缘介质层的折射率小于所述第二绝缘介质层的折射率，所述空洞位于第一绝缘介质层中，且空洞均匀的嵌套在第一绝缘介质层中，该空洞通过调整蒸镀参数得到。
  12. 根据权利要求11所述的一种发光二极管，所述空洞为纳米空洞，空洞大小为1nm～10nm。
  13. 根据权利要求1所述的一种发光二极管，其特征在于，所述透明衬底包括与第一表面相对的第二表面，第二表面为主要出光面。
  14. 根据权利要求1所述的一种发光二极管，还包括接触电极，形成于所述第二导电型半导体层上，所述DBR反射层覆盖该接触电极的表面。
  15. 一种发光二极管封装体，包括安装基板和安装在所述安装基板上的至少一个发光二极管，其特征在于，所述发光二极管至少一个或多个或全部为权利要求1～14中任一项所述的发光二极管。
  16. 一种发光二极管模组，包括安装基板和安装在所述安装基板上的多行和多列发光二极管，其特征在于，所述发光二极管至少一个或多个或全部为权利要求1～14中任一项所述的发光二极管。
  17. 根据权利要求所16所述的一种发光二极管模组，其特征在于，所述多列发光二极管至少包括一列红光发光二极管、一列绿光发光二极管和一列蓝光发光二极管。
  18. 根据权利要求16所述的一种发光二极管模组，其特征在于，所述的多行以及多列发光二极管都是蓝光发光二极管。
  19. 一种RGB显示装置，其特征在于，包括多个权利要求16～17任一项中所述的发光二极管模组拼接在一起。
  20. 一种背光显示屏，其特征在于，包括多个权利要求16～18任一项中所述的发光二极管模组拼接在一起形成背光光源。
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