WO2021105966A1 - Integrated circuit configured to operate in the quantum hall effect regime for obtaining a predetermined standard of resistance - Google Patents

Integrated circuit configured to operate in the quantum hall effect regime for obtaining a predetermined standard of resistance Download PDF

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Publication number
WO2021105966A1
WO2021105966A1 PCT/IB2020/061268 IB2020061268W WO2021105966A1 WO 2021105966 A1 WO2021105966 A1 WO 2021105966A1 IB 2020061268 W IB2020061268 W IB 2020061268W WO 2021105966 A1 WO2021105966 A1 WO 2021105966A1
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WIPO (PCT)
Prior art keywords
potential
integrated circuit
channel region
edge
field effect
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Application number
PCT/IB2020/061268
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French (fr)
Inventor
Stefan Heun
Stefano RODDARO
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Cnr - Consiglio Nazionale Delle Ricerche
Universita' Di Pisa
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Publication of WO2021105966A1 publication Critical patent/WO2021105966A1/en

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
    • G01R35/005—Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references
    • G01R35/007—Standards or reference devices, e.g. voltage or resistance standards, "golden references"
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/14—Measuring resistance by measuring current or voltage obtained from a reference source
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only

Definitions

  • the present invention relates to an electronic circuit configured to operate in the quantum Hall regime for obtaining a standard of resistance, in particular for calibrating electronic apparatuses of different type.
  • the QHARS have many drawbacks. At first, the number of circuital elements required to obtain the desired value of resistance with a certain accuracy does not scale favourably. More precisely, in order to obtain (N/M)xR K an array of N * M Hall bars is normally necessary, with a good homogeneity of parameters. Furthermore, the QHARS comprise many interconnections with ohmic contacts crossed by finite currents. For this reason, the QHARS are affected by systematic errors due to the spurious potential drops that occur at the ohmic contacts. Therefore, the QHARS have important practical limitations in order to provide a sample of metrological level .
  • the QHARS are structures that cannot be configured, therefore, to provide a certain quantum of resistance, it is necessary to provide a customized circuit.
  • an object of the present invention to provide an electronic circuit for obtaining a standard of resistance having a complexity, which scales logarithmically with the quantum accuracy.
  • the integrated circuit configured to operate in the quantum Hall effect regime to obtain a predetermined standard of resistance (R*), in particular to carry out the calibration of standard electrical resistance, said integrated circuit comprising:
  • At least a layer of conductor, or semiconductor, material configured to confine a two-dimensional gas of electrons (2DEG) in such a way to generate a two- dimensional channel region delimited between an external edge and at least a internal edge;
  • a plurality of field effect transistors positioned on said layer of conductor, or semiconductor, material, said plurality of field effect transistors being configured to generate in said two-dimensional channel region a plurality of barriers of potential having a respective edge, said two-dimensional channel region being configured to generate persistent currents, in particular due to the quantum Hall effect regime, at the external edge, of at least said internal edge and said edge of each barrier of potential;
  • a plurality of field effect transistors positioned on said at least a layer of conductor, or semiconductor, material, said plurality of field effect transistors being configured to generate in said two-dimensional channel region a plurality of barriers of potential having a respective edge, said two-dimensional channel region being arranged to generate persistent currents at said external edge, of at least said internal edge and of said edge of each barrier of potential;
  • a plurality of ohmic contacts positioned on said at least a layer of conductor, or semiconductor, material, and comprising:
  • an inlet ohmic contact through which a predetermined current I is arranged to be injected into said two-dimensional channel region, said predetermined current I being arranged to propagate through said two-dimensional channel region at said external edge and at said at least an internal edge to unbalance said persistent currents;
  • a first and a second barrier of potential associate respectively ad a first and a second field effect transistor connected in series with each other in such a way to define a first section;
  • said plurality of ohmic contacts comprises, furthermore, a plurality of equilibration ohmic contacts at which current is not arranged to be injected, or extracted, into/from said two-dimensional channel region, whereby said equilibration ohmic contacts are arranged to balance the potentials of said channel region at said external edge and of said at least an internal edge; and that between two adjacent barriers of potential of said plurality of barriers of potential at least an equilibration ohmic contact positioned at said external edge, and at least an equilibration ohmic contact positioned at said internal edge are provided, in such a way that at a predetermined equilibration ohmic contact of said plurality of equilibration ohmic contacts said pre
  • a method for producing an integrated circuit configured to operate in the quantum Hall effect regime in such a way to obtain a predetermined standard of resistance (R*), in particular to carry out the calibration of standard electrical resistance, comprises the steps of:
  • an inlet ohmic contact through which a predetermined current I is arranged to be injected into said two-dimensional channel region to be propagated through at said external edge and said at least an internal edge, said predetermined current I being arranged to unbalance said persistent currents;
  • a first and a second barrier of potential associate respectively ad a first and a second field effect transistor connected in series with each other in such a way to define a first section;
  • said plurality of ohmic contacts comprises, furthermore, a plurality of equilibration ohmic contacts at which the current is not arranged to be injected, or extracted, into/from said two-dimensional channel region, whereby said equilibration ohmic contacts are arranged to balance the potentials of said channel region at said external edge and said at least an internal edge; and that between two adjacent barriers of potential of said plurality of barriers of potential at least an equilibration ohmic contact positioned at said external edge, and at least an equilibration ohmic contact positioned at said internal edge are provided, in such a way that at a predetermined equilibration ohmic contact of said plurality of equilibration ohmic contacts said predetermined standard
  • the aforementioned inlet ohmic contact and the aforementioned outlet ohmic contact are the only ohmic contacts of said plurality of ohmic contacts configured, respectively, to inject and to extract current into/from said two-dimensional channel region.
  • the integrated circuit is configured in such a way to have only a two-dimensional channel region, in particular the two-dimensional channel region is continuous, that means without interruption as for example ohmic contacts, or metallic wires.
  • At least one between the first and the aforementioned at least a second section can be a reconfigurable section comprising at least three barriers of potential associated to respective field effect transistors connected in series.
  • the reconfigurable section can be configured to selectively and alternatively operate in at least a first and a second operating configuration, in which a field effect transistor of said reconfigurable section is arranged to be selectively turned off, whereby the respective barrier of potential is deactivated, whilst the other two field effect transistors are turned on, whereby the respective barriers of potential are activated.
  • each field effect transistor is a high electron mobility transistor, or HEMT.
  • a system for obtaining standard of resistance comprises:
  • a magnetic field source configured to generate a magnetic field such that said integrated circuit operates in the quantum Hall effect regime.
  • a system for calibrating an electronic measurement apparatus comprises:
  • a magnetic field source configured to generate a magnetic field such that said integrated circuit operates in the quantum Hall effect regime
  • connection element configured to connect said integrated circuit to an electronic measurement apparatus in such a way to calibrate said electronic measurement apparatus.
  • FIG. 1 diagrammatically shows a first embodiment of an integrated circuit, according to the invention, operating in the quantum Hall effect regime for obtaining a predetermined standard of resistance;
  • FIG. 2 diagrammatically shows a simplified scheme for explaining the principle of functioning of the integrated circuit 1 of figure 1;
  • FIG. 3A and 3B diagrammatically show two different operating configurations of an alternative embodiment of the integrated circuit of figure 1;
  • FIG. 4A and 4B diagrammatically show two different operating configurations of another alternative embodiment according to the invention of the integrated circuit of figure 1;
  • FIG. 5 diagrammatically shows a system comprising the circuit of figure 1 used for calibrating a measurement electronic apparatus.
  • FIG 1 a first embodiment of an integrated circuit 1, according to the present invention, is diagrammatically shown configured to operate in the quantum Hall effect regime, in particular with temperatures close to the absolute zero temperature, advantageously less than 1 K, and subject to a strong magnetic field (B), of about 1 Tesla, for obtaining a predetermined standard of resistance R*.
  • B strong magnetic field
  • the integrated circuit 1 comprises at least a layer of conductor, or semiconductor, material, configured to confine a two-dimensional gas of electrons (2DEG).
  • a layer of conductor, or semiconductor, material configured to confine a two-dimensional gas of electrons (2DEG).
  • 2DEG two-dimensional gas of electrons
  • some layers of GaAs, AlGaAs can be provided in such a way to form, as it is known, a GaAs/AlGaAs heterostructure.
  • the, or all the, layers of conductor, or semiconductor material are such that they generate a two-dimensional channel region 30 delimited between an external edge 31 and at least an internal edge 32, as diagrammatically shown in figure 1.
  • the aforementioned two-dimensional channel region 30 can be a continuous region, in particular, without interruption such as, for example, ohmic contacts, or metallic wires.
  • the integrated circuit 1 comprises, furthermore, a plurality of field effect transistors positioned on the layer, or layers, of conductor, or semiconductor material.
  • the aforementioned plurality of field effect transistors is configured to generate in the two- dimensional channel region 30 a plurality of barriers of potential 20 having a respective edge 21, for example 4 barriers of potential 20a, 20'a, 20b and 20'b, as diagrammatically shown in figure 1, each of which associated to a respective gate electrode of a respective field effect transistor.
  • the two- dimensional channel region 30 is arranged to generate persistent currents at, or near, the external edge 31, of the internal edge 32, and the edge 21 of each barrier of potential 20a, 20'a, 20b and 20'b.
  • the aforementioned plurality of ohmic contacts 5 comprises an inlet ohmic contact 5in through which a predetermined current I is arranged to be injected into the aforementioned two-dimensional channel region 30.
  • the aforementioned predetermined current I is arranged to propagate through the integrated circuit 1 at, or near to, the external edge 31 and the internal edge 32 to unbalance the aforementioned persistent currents. It is, furthermore, provided an outlet ohmic contact 5out through which the aforementioned predetermined current I is arranged to be extracted from the two-dimensional channel region 30.
  • the integrated circuit 1 comprises a first and a second barrier of potential 20a and 20'a associated, respectively, to a first and a second field effect transistor connected in series with each other in such a way to define a first section 10a, and at least a third and a fourth barrier of potential 20b, and 20'b associated, respectively, to a third and a fourth field effect transistor connected in series with each other, in such a way to define a second section 10b. More in detail, the first and the at least a second section 10a, and 10b are connected in series with each other.
  • the aforementioned plurality of ohmic contacts 5 comprises, furthermore, a plurality of equilibration ohmic contacts 5.
  • the equilibration ohmic contacts 5 in figure 1 the 10 ohmic contacts 5a-51, current is not arranged to be injected, or extracted, into/from the two- dimensional channel region 30.
  • the equilibration ohmic contacts 5 are arranged to balance the potentials of the channel region 30 at the external edge 31 and the internal edge 32.
  • At least an equilibration ohmic contact 5 are provided positioned at the external edge 31, in the embodiment of figure 1 the equilibration ohmic contacts 5b and 5e, and at least an equilibration ohmic contact 5 positioned at the internal edge 32, in figure 1 the equilibration ohmic contacts 5g- 51.
  • the predetermined standard of resistance R* is obtained at a predetermined equilibration ohmic contact 5* of the aforementioned plurality of equilibration ohmic contacts 5 the predetermined standard of resistance R* is obtained.
  • the integrated circuit 1 is configured in such a way to operate with a predetermined integer first filling factor u.
  • the edge state deflection in the presence of a barrier of potential, in particular that one generated by a field effect transistor, and the edge state equilibration at an equilibration ohmic contact are High Electron Mobility Transistors also known as HEMT, or HFET (Heterostructure Field Effect Transistor) .
  • HEMT High Electron Mobility Transistors
  • HFET Heterostructure Field Effect Transistor
  • circuit 2 which is diagrammatically shown in figure 2, corresponding to the simple case of a Hall bar obtained from a multilayer semiconductor device, which confines, at one of its junctions, a two-dimensional gas (2DEG) of free charges with high mobility, in particular free-electron charges, and a control gate, or barrier of potential 20, practically the schemati zation of a high electron mobility transistor, or HEMT.
  • 2DEG two-dimensional gas
  • u two edge states are obtained at the edge of the conductive channel (indicated only in the central zone of figure 2).
  • the aforementioned replacement allows new voltages available which are equal to the average between those of the contacts of the previous iteration.
  • the new voltage Ve is obtained at the ohmic contact 5e of circuit 1 intermediate between the ohmic contacts 5d and 5f.
  • the section 10b is a reconfigurable section. More precisely, the reconfigurable section 10b can comprise, advantageously, at least three field effect transistors associated to respective barriers of potential 20b, 20'b and 20"b, and connected in series.
  • the reconfigurable section 10b and, therefore, the circuit 1, is arranged to selectively and alternatively operate in at least a first operating configuration (figure 3A) in which a field effect transistor of the aforementioned field effect transistors is turned off, whereby the barrier of potential 20b associated to it of the reconfigurable section 10b is deactivated, or neutralized, (block 20b a hatched line), whilst the other two field effect transistors of the same section 10b are turned on and, therefore, the barriers of potential 20'b and 20"b associated to them are activated, and at least a second operating configuration, in which another field effect transistor of the reconfigurable section 10b is turned off and, therefore, the barrier of potential 20"b associated to it is deactivated, whilst the other two field effect transistors are turned on and, therefore, the respective barriers of potential 20b and 20'b are activated (see figure 3B).
  • the aforementioned field effect transistors associated to the barriers of potential 20b and 20"b can be arranged in ON condition
  • the first operating configuration of circuit 1 that is shown in figure 3A, allows to obtain the voltage Vd at the ohmic contact 5d.
  • the two configurations allows to select one, or the other semi-interval (upper, or lower) of the voltage interval which goes from Va to Vc. More in particular, the first semi-interval goes from Va to (Va+Vc)/2, whilst the second goes from (Va+Vc)/2 to Vc.
  • the aforementioned principle can be repeated iteratively in order to obtain, substantially by a "bisection" sequence, any binary fraction of the starting voltages Va and Vc.
  • the circuit scheme (geometry of the electrodes of gate, of the channels and of the contacts) can be easily derived using the replacement scheme indicated above, does not provide interconnections which introduce spurious potential drops, and has a complexity which scales linearly with the number of bisections and, therefore, only logarithmically with the accuracy of the resulting binary fraction.
  • the number n of bisection stages therefore, increases only logarithmically with the denominator 2 n and the value of k can be freely chosen between 0 and 2 n -l.
  • a system 100 for obtaining a predetermined standard of resistance (R*) comprises an integrated circuit 1, as described above with reference to the figure 1, 3A-4B, and a magnetic field source 50 configured to produce a magnetic field B such to generate a quantum Hall regime in the aforementioned integrated circuit 1.
  • the aforementioned system 100 can be used for calibrating an electronic measurement apparatus 200. Therefore, in this case a connection element 150 can be provided configured to connect the integrated circuit 1 to an electronic measurement apparatus 200.

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Abstract

An integrated circuit (1) configured to operate in the quantum Hall effect regime to obtain a predetermined standard of resistance (R*), in particular to carry out the calibration of standard electrical resistance. The integrated circuit (1) comprises at least a layer of conductor, or semiconductor, material, configured to confine a two-dimensional gas of electrons, in such a way to generate a two- dimensional channel region (30) delimited between an external edge (31) and at least an internal edge (32). The integrated circuit (1) comprises, furthermore, a plurality of field effect transistors associated to respective barriers of potential (20a,20'a,20b,20'b) and to a plurality of ohmic contacts (5) positioned on the layer of conductor, or semiconductor, material. The barriers of potential comprise a first and a second barrier of potential (20a,20'a) associated, respectively, to a first and a second field effect transistor connected in series with each other in such a way to define a first section (10a) and at least a third and a fourth barrier of potential (20b,20'b) associated, respectively, to a third and a fourth field effect transistors connected in series with each other, in such a way to define a second section (10b). The first and the at least second section (10a,10b) are connected in series with each other.

Description

TITLE
INTEGRATED CIRCUIT CONFIGURED TO OPERATE IN THE QUANTUM HALL EFFECT REGIME FOR OBTAINING A PREDETERMINED STANDARD
OF RESISTANCE DESCRIPTION
Field of the invention
The present invention relates to an electronic circuit configured to operate in the quantum Hall regime for obtaining a standard of resistance, in particular for calibrating electronic apparatuses of different type.
Background of the invention
As it is known, various techniques have been proposed to obtain quantum of resistance of arbitrary values, for directly calibrate resistances of different values and to encounter the market needs of calibration.
In particular, many architectures have been proposed of integrated circuits comprising a large number of quantum Hall elements, known as QHARS "Quantum Hall Array Resistance Standards", which allow to obtain integer fractions of the von Klitzing constant RK.
However, the QHARS have many drawbacks. At first, the number of circuital elements required to obtain the desired value of resistance with a certain accuracy does not scale favourably. More precisely, in order to obtain (N/M)xRK an array of N*M Hall bars is normally necessary, with a good homogeneity of parameters. Furthermore, the QHARS comprise many interconnections with ohmic contacts crossed by finite currents. For this reason, the QHARS are affected by systematic errors due to the spurious potential drops that occur at the ohmic contacts. Therefore, the QHARS have important practical limitations in order to provide a sample of metrological level .
In addition to the above, the QHARS are structures that cannot be configured, therefore, to provide a certain quantum of resistance, it is necessary to provide a customized circuit.
In order to attempt to overcome the aforementioned drawbacks in M. Marzano et al. "On the synthesis of quantum Hall array resistance standards" , Metrologia 52,31 (2015) networks of Hall bars have been proposed with a complex connectivity and not easy from a computational point of view to be determined. Even though this type of solution allows to scale more favourably than the QHARS in order to obtain the desired value of resistance, however, also this solution has the drawback to produce spurious potential drops at the ohmic contacts. Furthermore, also the networks of Hall bars cannot be configured and also in this case, in order to obtain a determined value, a specific network of Hall bars has to be made.
Another document which discloses a solution to the aforementioned problem is J.Hu et al. "Towards epitaxial graphene p-n junctions as electrically programmable quantum resistance standards ", Scientific Reports 8,
15018 (2018). In particular, in this document is underlined how an appropriate routing, i.e. a readdressing, or remixing of the edge states followed by an equilibration can be used to obtain quantum of resistance different from the "standard". This approach does not require that the current exits at any contact besides those used for injecting the current (1+ and I-) and, therefore, it is not affected by systematic errors due to the residual contact resistances. In the document it is assumed that is possible to provide a circuit that can be reconfigured, that, however, requires a number of circuital elements (junctions p-n) which scales linearly with the requested accuracy. Furthermore, the proposed circuit, even though can be reconfigured, however, provides interconnections which are affected by the aforementioned disadvantages of spurious potential drops and, therefore, does not allow to provide a four contacts measure without spurious effects.
Summary of the invention
It is, therefore, an object of the present invention to provide an electronic circuit for obtaining a standard of resistance having a complexity, which scales logarithmically with the quantum accuracy.
It is another object of the present invention to provide an electronic circuit for obtaining a standard of resistance very accurately and that does not introduce any spurious potential drop due to internal connections crossed by current.
It is a further object of the present invention to provide an electronic circuit for obtaining a standard of resistance which can be easily reconfigured in such a way that is possible to obtain different values of voltage from which derives different values of resistance without compromising the accuracy of the measurement. These and other objects are achieved by the integrated circuit, according to the invention, configured to operate in the quantum Hall effect regime to obtain a predetermined standard of resistance (R*), in particular to carry out the calibration of standard electrical resistance, said integrated circuit comprising:
— at least a layer of conductor, or semiconductor, material, configured to confine a two-dimensional gas of electrons (2DEG) in such a way to generate a two- dimensional channel region delimited between an external edge and at least a internal edge;
— a plurality of field effect transistors positioned on said layer of conductor, or semiconductor, material, said plurality of field effect transistors being configured to generate in said two-dimensional channel region a plurality of barriers of potential having a respective edge, said two-dimensional channel region being configured to generate persistent currents, in particular due to the quantum Hall effect regime, at the external edge, of at least said internal edge and said edge of each barrier of potential;
— a plurality of field effect transistors positioned on said at least a layer of conductor, or semiconductor, material, said plurality of field effect transistors being configured to generate in said two-dimensional channel region a plurality of barriers of potential having a respective edge, said two-dimensional channel region being arranged to generate persistent currents at said external edge, of at least said internal edge and of said edge of each barrier of potential;
— a plurality of ohmic contacts positioned on said at least a layer of conductor, or semiconductor, material, and comprising:
— an inlet ohmic contact through which a predetermined current I is arranged to be injected into said two-dimensional channel region, said predetermined current I being arranged to propagate through said two-dimensional channel region at said external edge and at said at least an internal edge to unbalance said persistent currents;
— an outlet ohmic contact through which said predetermined current I is arranged to be extracted from said channel region; whose main characteristic of said integrated circuit is that said plurality of barriers of potential comprises:
— a first and a second barrier of potential associate respectively ad a first and a second field effect transistor connected in series with each other in such a way to define a first section;
— at least a third and a fourth barrier of potential associated, respectively, to a third and a fourth field effect transistor connected in series with each other in such a way to define a second section, said first and said at least a second section being connected in series with each other; that said plurality of ohmic contacts comprises, furthermore, a plurality of equilibration ohmic contacts at which current is not arranged to be injected, or extracted, into/from said two-dimensional channel region, whereby said equilibration ohmic contacts are arranged to balance the potentials of said channel region at said external edge and of said at least an internal edge; and that between two adjacent barriers of potential of said plurality of barriers of potential at least an equilibration ohmic contact positioned at said external edge, and at least an equilibration ohmic contact positioned at said internal edge are provided, in such a way that at a predetermined equilibration ohmic contact of said plurality of equilibration ohmic contacts said predetermined standard of resistance (R*) is obtained.
According to another aspect of the invention, a method for producing an integrated circuit configured to operate in the quantum Hall effect regime in such a way to obtain a predetermined standard of resistance (R*), in particular to carry out the calibration of standard electrical resistance, comprises the steps of:
— providing at least a layer of conductor, or semiconductor, material, configured to confine a two- dimensional gas of electrons in such a way to generate a two-dimensional channel region, said two-dimensional channel region being delimited between an external edge and at least an internal edge;
— positioning on said at least a layer of conductor material of a plurality of field effect transistors configured to generate a plurality of barriers of potential having a respective edge, said two- dimensional channel region being arranged to generate persistent currents at said external edge, of at least said internal edge and of said edge of each barrier of potential;
— positioning on said at least a layer of conductor material a plurality of ohmic contacts comprising:
— an inlet ohmic contact through which a predetermined current I is arranged to be injected into said two-dimensional channel region to be propagated through at said external edge and said at least an internal edge, said predetermined current I being arranged to unbalance said persistent currents;
— an outlet ohmic contact through which said predetermined current I is arranged to be extracted form said channel region; whose main characteristic is that said plurality of barriers of potential comprises:
— a first and a second barrier of potential associate respectively ad a first and a second field effect transistor connected in series with each other in such a way to define a first section;
— at least a third and a fourth barrier of potential associate respectively ad a third and a fourth field effect transistor connected in series, in such a way to define a second section, said prima and said at least a second section being connected in series with each other; that said plurality of ohmic contacts comprises, furthermore, a plurality of equilibration ohmic contacts at which the current is not arranged to be injected, or extracted, into/from said two-dimensional channel region, whereby said equilibration ohmic contacts are arranged to balance the potentials of said channel region at said external edge and said at least an internal edge; and that between two adjacent barriers of potential of said plurality of barriers of potential at least an equilibration ohmic contact positioned at said external edge, and at least an equilibration ohmic contact positioned at said internal edge are provided, in such a way that at a predetermined equilibration ohmic contact of said plurality of equilibration ohmic contacts said predetermined standard of resistance (R*) is obtained.
Other features of the present invention and related embodiments are set out in the dependent claims.
In particular, the aforementioned inlet ohmic contact and the aforementioned outlet ohmic contact are the only ohmic contacts of said plurality of ohmic contacts configured, respectively, to inject and to extract current into/from said two-dimensional channel region.
According to a preferred embodiment, the integrated circuit, according to the invention, is configured in such a way to have only a two-dimensional channel region, in particular the two-dimensional channel region is continuous, that means without interruption as for example ohmic contacts, or metallic wires.
In particular, at least one between the first and the aforementioned at least a second section can be a reconfigurable section comprising at least three barriers of potential associated to respective field effect transistors connected in series. More in particular, the reconfigurable section can be configured to selectively and alternatively operate in at least a first and a second operating configuration, in which a field effect transistor of said reconfigurable section is arranged to be selectively turned off, whereby the respective barrier of potential is deactivated, whilst the other two field effect transistors are turned on, whereby the respective barriers of potential are activated.
Advantageously, each field effect transistor is a high electron mobility transistor, or HEMT.
According to a further aspect of the invention, a system for obtaining standard of resistance comprises:
— an integrated circuit as described above;
— a magnetic field source configured to generate a magnetic field such that said integrated circuit operates in the quantum Hall effect regime.
According to still another aspect of the invention, a system for calibrating an electronic measurement apparatus comprises:
— an integrated circuit as described above;
— a magnetic field source configured to generate a magnetic field such that said integrated circuit operates in the quantum Hall effect regime;
— a connection element configured to connect said integrated circuit to an electronic measurement apparatus in such a way to calibrate said electronic measurement apparatus.
Brief description of the drawings
The invention will be now illustrated with the following description of an exemplary embodiment thereof, exemplifying but not limitative, with reference to the attached drawings wherein:
- Fig. 1 diagrammatically shows a first embodiment of an integrated circuit, according to the invention, operating in the quantum Hall effect regime for obtaining a predetermined standard of resistance;
- Fig. 2 diagrammatically shows a simplified scheme for explaining the principle of functioning of the integrated circuit 1 of figure 1;
- Figures 3A and 3B diagrammatically show two different operating configurations of an alternative embodiment of the integrated circuit of figure 1;
- Figures 4A and 4B diagrammatically show two different operating configurations of another alternative embodiment according to the invention of the integrated circuit of figure 1;
- Fig. 5 diagrammatically shows a system comprising the circuit of figure 1 used for calibrating a measurement electronic apparatus.
Detailed description of some exemplary embodiments of the invention
In figure 1 a first embodiment of an integrated circuit 1, according to the present invention, is diagrammatically shown configured to operate in the quantum Hall effect regime, in particular with temperatures close to the absolute zero temperature, advantageously less than 1 K, and subject to a strong magnetic field (B), of about 1 Tesla, for obtaining a predetermined standard of resistance R*.
More in detail, the integrated circuit 1 comprises at least a layer of conductor, or semiconductor, material, configured to confine a two-dimensional gas of electrons (2DEG). For example, some layers of GaAs, AlGaAs can be provided in such a way to form, as it is known, a GaAs/AlGaAs heterostructure. More in particular, the, or all the, layers of conductor, or semiconductor material, are such that they generate a two-dimensional channel region 30 delimited between an external edge 31 and at least an internal edge 32, as diagrammatically shown in figure 1.
Advantageously, the aforementioned two-dimensional channel region 30 (2DEG) can be a continuous region, in particular, without interruption such as, for example, ohmic contacts, or metallic wires.
The integrated circuit 1 comprises, furthermore, a plurality of field effect transistors positioned on the layer, or layers, of conductor, or semiconductor material. In particular, the aforementioned plurality of field effect transistors is configured to generate in the two- dimensional channel region 30 a plurality of barriers of potential 20 having a respective edge 21, for example 4 barriers of potential 20a, 20'a, 20b and 20'b, as diagrammatically shown in figure 1, each of which associated to a respective gate electrode of a respective field effect transistor. More in particular, the two- dimensional channel region 30 is arranged to generate persistent currents at, or near, the external edge 31, of the internal edge 32, and the edge 21 of each barrier of potential 20a, 20'a, 20b and 20'b.
It is, then, provided a plurality of ohmic contacts 5, that means of metal-semiconductor junctions positioned on the layer of conductor, or semiconductor, material. More in particular the ohmic contacts 5 are arranged to allow the current to move in both the directions, apart from the difference between their potentials. More precisely, the aforementioned plurality of ohmic contacts 5 comprises an inlet ohmic contact 5in through which a predetermined current I is arranged to be injected into the aforementioned two-dimensional channel region 30. In particular, the aforementioned predetermined current I is arranged to propagate through the integrated circuit 1 at, or near to, the external edge 31 and the internal edge 32 to unbalance the aforementioned persistent currents. It is, furthermore, provided an outlet ohmic contact 5out through which the aforementioned predetermined current I is arranged to be extracted from the two-dimensional channel region 30.
More precisely, according to the present invention, the integrated circuit 1 comprises a first and a second barrier of potential 20a and 20'a associated, respectively, to a first and a second field effect transistor connected in series with each other in such a way to define a first section 10a, and at least a third and a fourth barrier of potential 20b, and 20'b associated, respectively, to a third and a fourth field effect transistor connected in series with each other, in such a way to define a second section 10b. More in detail, the first and the at least a second section 10a, and 10b are connected in series with each other.
According to the present invention, the aforementioned plurality of ohmic contacts 5 comprises, furthermore, a plurality of equilibration ohmic contacts 5. In particular, at the equilibration ohmic contacts 5, in figure 1 the 10 ohmic contacts 5a-51, current is not arranged to be injected, or extracted, into/from the two- dimensional channel region 30. More in particular, the equilibration ohmic contacts 5 are arranged to balance the potentials of the channel region 30 at the external edge 31 and the internal edge 32.
More in detail, between two following, or adjacent, barriers of potential 20a, 20'a, 20b and 20'b at least an equilibration ohmic contact 5 are provided positioned at the external edge 31, in the embodiment of figure 1 the equilibration ohmic contacts 5b and 5e, and at least an equilibration ohmic contact 5 positioned at the internal edge 32, in figure 1 the equilibration ohmic contacts 5g- 51. In this way, at a predetermined equilibration ohmic contact 5* of the aforementioned plurality of equilibration ohmic contacts 5 the predetermined standard of resistance R* is obtained.
Preferably, the integrated circuit 1 is configured in such a way to operate with a predetermined integer first filling factor u. Advantageously, each field effect transistor associated to a respective barrier of potential 20a, 20'a, 20b, 20'b can be configured to reduce at the respective barrier of potential the aforementioned first predetermined value of the filling factor u to a value u,=u/2 also this integer, but less than the filling factor u, for example u=2 and u,=l.
In this way, at a predetermined ohmic contact 5* of the aforementioned plurality is possible to obtain the aforementioned predetermined desired standard of resistance. More precisely, it has been demonstrated that if the voltage at the ohmic contact 5f is Vf and the voltage at the ohmic contact 5d is Vd, then the voltage at the ohmic contact 5e is equal to the arithmetic average between Vf and Vd, i.e. Ve= (Vd+Vf)/2. Once that the voltage Ve at the ohmic contact 5e has been obtained it is, therefore, possible, using known equations, to obtain the desired resistance standard R*.
The aforementioned result is obtained, in particular, thanks to two known fundamental physical principles of the quantum Hall effect regime. At first, the edge state deflection in the presence of a barrier of potential, in particular that one generated by a field effect transistor, and the edge state equilibration at an equilibration ohmic contact. Preferably, the aforementioned field effect transistors associated to the barriers of potential 20a, 20'a, 20b and 20'b are High Electron Mobility Transistors also known as HEMT, or HFET (Heterostructure Field Effect Transistor) .
What has been disclosed above will be understood more easily with reference to the circuit 2 which is diagrammatically shown in figure 2, corresponding to the simple case of a Hall bar obtained from a multilayer semiconductor device, which confines, at one of its junctions, a two-dimensional gas (2DEG) of free charges with high mobility, in particular free-electron charges, and a control gate, or barrier of potential 20, practically the schemati zation of a high electron mobility transistor, or HEMT. If the aforementioned integrated circuit is taken to be in the quantum Hall regime with a filling factor u=2, two edge states are obtained at the edge of the conductive channel (indicated only in the central zone of figure 2). The electrode gate 20 is used for reducing the density of charge up to reaching a filling factor u=l at the gate of the field effect transistor 20. In this configuration, one of the edge channels is reflected back by the electrode gate 20 and equilibrates the contact 5f, which is brought to a voltage Vf, which is exactly, with the accuracy guaranteed by the quantum Hall regime, and by the accuracy of equilibration of a ohmic contact, equal to the average between the voltage Va of contact 5a and the voltage Vd of contact 5d, i.e. Vf= (Va+Vd)/2. Analogously, the voltage Vc at contact 5c is equal to the average between the voltage Va of contact 5a and the voltage Vd of contact 5d, i.e. also for Vc of the circuit of figure 1 is Vc= (Va+Vd)/2.
Therefore, as will be demonstrated below there is an equivalence between the single field effect transistor associated to the barrier of potential 20 of figure 2 and the integrated circuit 1 of figure 1 comprising a system "double-parallel-double-serial" of four field effect transistors associated to respective barriers of potential 20a, 20'a, 20b, 20'b as described above with reference to figure 1. More in detail, it has been observed that once the input voltages Va and Vd at the ohmic contacts 5a and 5d are set, the ohmic contacts 5c and 5f equilibrate to the same voltages Vc and Vf which are obtained in the case of the single barrier of figure 2. Furthermore, it has been observed that the input and output currents of circuit 1 of figure 1 are the same of circuit 2 of figure 2. This, therefore, demonstrates that the aforementioned replacement does not affect in any way the voltages and the currents in the rest of the circuit. For the single ohmic contacts it is possible to apply a set of known linear equations, and precisely: V5g=V5b=(V5a+V5h)/2, V5h=V5c=(V5b+V5i)/2, V5f=V51= (V5g+V5e)/2, and V5e=V5i= (V51+V5d)/2. Assuming that the voltages Ve and Vi are equal to each other because they emerge from the same barrier of potential 20'b, and analogously for the voltages Vg and Vb, the linear equations indicated above lead to Vf=Vl=Vh=Vc. Therefore, very simple algebra equations lead to the aforementioned equation Vf=Vc= (Va+Vd)/2. The conclusion is therefore that the output voltages Vf and Vc of circuit 1 of figure 1 coincide with those obtained for circuit 2 of figure 2, and that the voltage at the ohmic contact 5e positioned between the ohmic contacts 5d and 5f is equal to half of their voltages, i.e. as disclosed above Ve= (Vf+Vd)/2.
Therefore, in general, the aforementioned replacement allows new voltages available which are equal to the average between those of the contacts of the previous iteration. In particular, in the case shown in figure 1, as anticipated above, the new voltage Ve is obtained at the ohmic contact 5e of circuit 1 intermediate between the ohmic contacts 5d and 5f.
As diagrammatically shown in the figures 3A and 3B, according to an alternative embodiment of the invention, at least one between the first and the second sections 10a and 10b of circuit 1, in the case of figures 3A and 3B, the section 10b, is a reconfigurable section. More precisely, the reconfigurable section 10b can comprise, advantageously, at least three field effect transistors associated to respective barriers of potential 20b, 20'b and 20"b, and connected in series. More in detail, the reconfigurable section 10b, and, therefore, the circuit 1, is arranged to selectively and alternatively operate in at least a first operating configuration (figure 3A) in which a field effect transistor of the aforementioned field effect transistors is turned off, whereby the barrier of potential 20b associated to it of the reconfigurable section 10b is deactivated, or neutralized, (block 20b a hatched line), whilst the other two field effect transistors of the same section 10b are turned on and, therefore, the barriers of potential 20'b and 20"b associated to them are activated, and at least a second operating configuration, in which another field effect transistor of the reconfigurable section 10b is turned off and, therefore, the barrier of potential 20"b associated to it is deactivated, whilst the other two field effect transistors are turned on and, therefore, the respective barriers of potential 20b and 20'b are activated (see figure 3B). In particular, the aforementioned field effect transistors associated to the barriers of potential 20b and 20"b can be arranged in ON condition (ON) or, alternatively, in OFF condition (OFF), by a control unit 300 operatively connected to them.
In particular, if Va and Vc are the starting voltages entering the stage, respectively at the ohmic contacts 5a and 5c, and Vd and Vg the voltages exiting the same stage, respectively at the ohmic contacts 5d and 5g, the first operating configuration of circuit 1 that is shown in figure 3A, allows to obtain the voltage Vd at the ohmic contact 5d. This is equal to the average of voltage Vg of ohmic contact 5g, or voltage Va of ohmic contact 5a ad esso uguale (i.e. Vg=Vc), and voltage Vc of ohmic contact 5c, i.e. Vd= (Va+Vc)/2.
Analogously, the second operating configuration of circuit 1, instead, diagrammatically shown in figure 3B, allows to obtain at the ohmic contact 5d a voltage Vc (i.e. Vd=Vc), whilst at the ohmic contact 5g a voltage Vg is obtained that is equal to the average of the voltages Vd=Vc and Va respectively of the ohmic contacts 5d and 5a, i.e. Vg= (Va+Vc)/2. In particular, the two configurations allows to select one, or the other semi-interval (upper, or lower) of the voltage interval which goes from Va to Vc. More in particular, the first semi-interval goes from Va to (Va+Vc)/2, whilst the second goes from (Va+Vc)/2 to Vc.
According to the present invention, the aforementioned principle can be repeated iteratively in order to obtain, substantially by a "bisection" sequence, any binary fraction of the starting voltages Va and Vc. This results in a bisection between the four- wire resistance that can be obtained from the circuit (the total current is fixed and does not change). The bisection scheme is in itself a useful innovation because it allows to easily design a circuit which provides a binary fraction of RK, i.e. the known Klitzing resistance =h/e2=25.8128074434 (84) kW. The circuit scheme (geometry of the electrodes of gate, of the channels and of the contacts) can be easily derived using the replacement scheme indicated above, does not provide interconnections which introduce spurious potential drops, and has a complexity which scales linearly with the number of bisections and, therefore, only logarithmically with the accuracy of the resulting binary fraction.
In particular, with reference to the figures 4A and 4B, the aforementioned bisection circuit 1 shown with reference to the figures 3A and 3B, can be seen as the nth stage of a larger bisection circuit 1'. Therefore, indicating with 5R,n and 5L,n the ohmic contacts of the nth stage, with 5R,n+l and 5L,n+l the ohmic contacts or stage n+1 and with VR,n and VL,n, VR,n+l and VL,n+l the respective voltages, in the case that is diagrammatically shown in figure 4A, where is the field effect transistor 20n+l to be neutralized, it is: VL,n+i=VL,n and VR,n+i=VR,n-AVn/2, dove AVn=VR,n-VL,n, whilst in the case that is diagrammatically shown in figure 4B, wherein is the field effect transistor 20"n+l to be neutralized, it is: VL n+i=VL n+AVn/2 and VR n+i=VR n. In both the cases a new (n+l)th interval of reduced voltage AVn+i=AVn/2 is obtained. The aforementioned scheme can be, therefore, repeated in such a way to obtain any binary fraction between two starting voltages VL 0 and VR,o, for example VL n=VLo+AVoxk/2n=VLo+AVn xk, where k is a determined integer number of the configurations chosen for each bisection stage.
The number n of bisection stages, therefore, increases only logarithmically with the denominator 2n and the value of k can be freely chosen between 0 and 2n-l.
As diagrammatically shown in figure 5, according to another aspect of the invention, a system 100 for obtaining a predetermined standard of resistance (R*) comprises an integrated circuit 1, as described above with reference to the figure 1, 3A-4B, and a magnetic field source 50 configured to produce a magnetic field B such to generate a quantum Hall regime in the aforementioned integrated circuit 1. According to a particular application of the invention, the aforementioned system 100 can be used for calibrating an electronic measurement apparatus 200. Therefore, in this case a connection element 150 can be provided configured to connect the integrated circuit 1 to an electronic measurement apparatus 200.
The foregoing description of a specific embodiment will so fully reveal the invention according to the conceptual point of view, so that others, by applying current knowledge, will be able to modify and/or adapt for various applications such an embodiment without further research and without parting from the invention, and it is therefore to be understood that such adaptations and modifications will have to be considered as equivalent to the specific embodiment. The means and the materials to realise the different functions described herein could have a different nature without, for this reason, departing from the field of the invention. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation.

Claims

1. An integrated circuit (1) configured to operate in the quantum Hall effect regime in order to obtain a predetermined standard of resistance (R*), in particular to carry out the calibration of standard electrical resistance, said integrated circuit (1) comprising:
— at least a layer of conductor, or semiconductor, material, configured to confine a two-dimensional gas of electrons (2DEG), in such a way to generate a two- dimensional channel region (30) delimited between an external edge (31) and at least an internal edge (32);
— a plurality of field effect transistors arranged on said layer of conductor, or semiconductor, material, said plurality of field effect transistors being configured to produce within said two- dimensional channel region (30) a plurality of barriers of potential (20) having a respective edge (21), said two-dimensional channel region (30) being arranged to generate persistent currents at said external edge (31), of said, or each, internal edge (32) of said two-dimensional channel region (30) and of said edge (21) of each barrier of potential (20);
— a plurality of ohmic contacts positioned on said layer of conductor, or semiconductor, material and comprising:
— an inlet ohmic contact (5in) through which a predetermined current I is arranged to be injected into said two-dimensional channel region (30), said predetermined current I being arranged to propagate at said external edge (31) and at said, or each, internal edge (32) to unbalance said persistent currents;
— an outlet ohmic contact (5out) through which said predetermined current I is arranged to exit said two-dimensional channel region (30); said integrated circuit (1) being characterized in that said plurality of barriers of potential (20) comprises:
— a first and a second barrier of potential (20a,20'a) associated, respectively, to a first and a second field effect transistor connected in series with each other in such a way to define a first section (10a);
— at least a third and a fourth barrier of potential (20b,20'b) associated, respectively, to a third and a fourth field effect transistor connected in series, in such a way to define a second section (10b), said first and said at least a second section (10a,10b) being connected in series with each other; in that said plurality of ohmic contacts (5) comprises, furthermore, a plurality of equilibration ohmic contacts (5) at which the current is not arranged to be injected into, or extracted from said two-dimensional channel region (30), whereby said equilibration ohmic contacts (5) are arranged to balance the potentials of said two-dimensional channel region (30) at said external edge (31) and said at least an internal edge (32); and in that between two adjacent barriers of potential (20) of said plurality of barriers of potential (20) an equilibration ohmic contact (5) positioned at said external edge (31), and at least an equilibration ohmic contact (5) positioned at said internal edge (32) are provided, in such a way that at a predetermined equilibration ohmic contact (5*) of said plurality of equilibration ohmic contacts (5) said predetermined standard of resistance (R*) is obtained.
2 . Integrated circuit (1), according to claim 1, wherein said inlet ohmic contact (5in) and said outlet ohmic contact (5out) are the only ohmic contacts of said plurality of ohmic contacts (5) configured, respectively, to inject and to extract current into/from said two-dimensional channel region (30).
3. Integrated circuit (1), according to any of the previous claims, configured in such a way that only a continuous two-dimensional channel region (30) is provided.
4 . Integrated circuit (1), according to any of the previous claims, wherein at least one between said first and second sections (10a,10b) is a reconfigurable section comprising at least three barriers of potential (20b,20'b,20"b) associated to respective field effect transistors connected in series, and wherein said reconfigurable section is configured selectively and alternatively operate in at least a first and a second operating configuration, in which a field effect transistor of said reconfigurable section (10a,10b) is arranged to be selectively turned off, whereby the respective barrier of potential (20b;20"b) is deactivated, whilst the other two field effect transistors are turned on, whereby the respective barriers of potential (20'b,20"b; 20b,20'b) are activated.
5 . Integrated circuit (1), according to any of the previous claims, wherein each field effect transistor of said plurality is a high electron mobility transistor, or HEMT.
6. Integrated circuit (1) according to any of the previous claims configured to operate with a first predetermined filling factor, or filling factor, u and wherein each said barrier of potential (20a, 20'a, 20b, 20'b) is configured to bring said predetermined first filling factor, or filling factor, to a value u =u/2.
7 . Integrated circuit (1) according to any of the previous claims configured to operate with a first predetermined filling factor, or filling factor, u=2, and wherein each said barrier of potential (20a, 20'a,
20b, 20'b) is configured to bring said predetermined first filling factor, or filling factor, to a value u'=1.
8. A system for obtaining a predetermined standard of resistance (R*) characterized in that it comprises:
— an integrated circuit (1) according to any claim from 1 to 7; — a magnetic field source (50) configured to generate a magnetic field such that said integrated circuit (1) operates in the quantum Hall effect regime.
9. A system for calibrating an electronic measurement apparatus characterized in that it comprises:
— an integrated circuit (1) according to any claim from 1 to 7;
— a magnetic field source (50) configured to generate a magnetic field such that said integrated circuit (1) opera in the quantum Hall effect regime;
— a connection element (150) configured to connect said integrated circuit to an electronic measurement apparatus (200) in such a way to calibrate said electronic measurement apparatus (200).
10. Sistema, according to claim 8, or 9 wherein a control unit (300) is, furthermore, provided configured to turn on, or turn off, determined field effect transistors of said predetermined plurality and, therefore, to activate, or deactivate, the respective barriers of potential (20), in such a way to reconfigure in a predetermined way said integrated circuit (1) and to obtain a corresponding determined standard of resistance (R*).
11. Method for producing an integrated circuit (1) configured to operate in the quantum Hall effect regime in such a way to obtain a predetermined standard of resistance (R*), in particular to carry out the calibration of standard electrical resistance, said method comprising the steps of: — providing at least a layer of conductor, or semiconductor, material, configured to confine a two- dimensional gas of electrons in such a way to generate a two-dimensional channel region (30), said two- dimensional channel region (30) being delimited between an external edge (31) and at least an internal edge (32);
— positioning on said at least a layer of conductor material a plurality of field effect transistors configured to generate in said two-dimensional channel region (30) a plurality of barriers of potential (20) having a respective edge (21), said two-dimensional channel region (30) being arranged to generate persistent currents at said external edge (31), and at least said internal edge (32) and of said edge (21) of each barrier of potential (20);
— positioning on said at least a layer of conductor material a plurality of ohmic contacts (5) comprising:
— an inlet ohmic contact (5in) through which a predetermined current I is arranged to be injected into said two-dimensional channel region (30) to propagate at said external edge (31) and said at least an internal edge (32), said predetermined current I being arranged to unbalance said persistent currents;
— un outlet ohmic contact (5out) through which said predetermined current I is arranged to be extracted from said channel region (30); said method being characterized in that said plurality of barriers of potential (20) comprises:
— a first and a second barrier of potential (20a,20'a) associated, respectively, to a first and a second field effect transistor connected in series with each other in such a way to define a first section (10a);
— at least a third and a fourth barrier of potential (20b,20'b) associated, respectively, to a third and a fourth field effect transistor connected in series with each other, in such a way to define a second section (10b), said first and said at least a second section (10a,10b) being connected in series with each other; in that said plurality of ohmic contacts (5) comprises, furthermore, a plurality of equilibration ohmic contacts (5) at which no current is arranged to be injected, or extracted, into/from said two- dimensional channel region (30), per cui said equilibration ohmic contacts (5) are arranged to balance the potentials of said channel region (30) at said external edge (31) and of said at least an internal edge (32); and in that between two adjacent barriers of potential (20) of said plurality of barriers of potential (20) an equilibration ohmic contact (5) positioned at said external edge (31), and at least a equilibration ohmic contact (5) positioned at said internal edge (32) are provided, in such a way that at a predetermined equilibration ohmic contact (5*) of said plurality of equilibration ohmic contacts (5) said predetermined standard of resistance (R*) is obtained.
12 . Method for calibrating an electronic measurement apparatus characterized in that it comprises the steps of:
— providing an integrated circuit (1) produced according to the method of claim 11; — generating by a magnetic field source (50) a magnetic field such that said integrated circuit (1) opera in the quantum Hall effect regime;
— connecting (150) said integrated circuit to said electronic measurement apparatus (200) in such a way to calibrate said electronic measurement apparatus (200).
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