WO2021102683A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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WO2021102683A1
WO2021102683A1 PCT/CN2019/120951 CN2019120951W WO2021102683A1 WO 2021102683 A1 WO2021102683 A1 WO 2021102683A1 CN 2019120951 W CN2019120951 W CN 2019120951W WO 2021102683 A1 WO2021102683 A1 WO 2021102683A1
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layer
semiconductor structure
gate
type semiconductor
heterojunction
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PCT/CN2019/120951
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English (en)
French (fr)
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程凯
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苏州晶湛半导体有限公司
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Priority to US17/276,809 priority Critical patent/US20220069113A1/en
Priority to CN201980101639.XA priority patent/CN114616678A/zh
Priority to PCT/CN2019/120951 priority patent/WO2021102683A1/zh
Priority to TW109141244A priority patent/TW202121697A/zh
Publication of WO2021102683A1 publication Critical patent/WO2021102683A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors

Definitions

  • This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof.
  • the wide-gap semiconductor material group III nitride has the excellent characteristics of large forbidden bandwidth, high pressure resistance, high temperature resistance, high electron saturation speed and drift speed, and easy formation of high-quality heterostructures. Very suitable for manufacturing high temperature, high frequency, high power electronic devices.
  • Enhanced devices have a very wide range of applications in the field of power electronics due to their normally-off characteristics. There are many ways to implement enhanced devices, such as depleting the two-dimensional electron gas by arranging a p-type semiconductor at the gate.
  • the inventor of the present application found that the enhanced device realized by arranging a p-type semiconductor at the gate has a lower threshold voltage, and this method needs to etch the p-type semiconductor outside the gate area, but the etching inevitably leads to etching. Eclipse loss.
  • one aspect of the present invention provides a semiconductor structure, including:
  • the p-type semiconductor layer in the gate region on the transition layer does not fill the groove.
  • the semiconductor structure further includes: a gate located on the p-type semiconductor layer; and a source and a drain located on both sides of the gate.
  • the heterojunction includes a channel layer and a barrier layer from bottom to top.
  • the heterojunction includes a GaN-based material.
  • the material of the in-situ insulating layer includes: at least one of SiN and SiAlN; and/or the material of the transition layer includes: at least one of AlN, SiAlN, and AlGaN.
  • the non-gate region on the transition layer also has the p-type semiconductor layer.
  • the heterojunction includes a channel layer and a barrier layer from bottom to top, and the source and drain are in contact with the channel layer or the barrier layer.
  • Another aspect of the present invention provides a method for manufacturing a semiconductor structure, including:
  • a transition layer and a p-type semiconductor layer are formed in the groove and on the in-situ insulating layer, and the p-type semiconductor layer does not fill the groove.
  • the method further includes: forming a gate on the p-type semiconductor layer in the gate region; and forming a source and a drain on both sides of the gate.
  • the heterojunction includes a channel layer and a barrier layer from bottom to top.
  • the heterojunction includes a GaN-based material.
  • the material of the in-situ insulating layer includes: at least one of SiN and SiAlN; and/or the material of the transition layer includes: at least one of AlN, SiAlN, and AlGaN.
  • the p-type semiconductor layer is also patterned, leaving the p-type semiconductor layer in the gate region.
  • the heterojunction includes a channel layer and a barrier layer from bottom to top, and the source and drain are in contact with the channel layer or the barrier layer.
  • the present invention has the following beneficial effects:
  • an in-situ insulating layer is formed on the heterojunction, a groove is provided in the in-situ insulating layer, a transition layer is provided in the groove and on the in-situ insulating layer, and the gate region on the transition layer A p-type semiconductor layer is formed.
  • the transition layer facilitates the formation of the p-type semiconductor layer outside the groove during the process.
  • the in-situ insulating layer and the transition layer can reduce the gate leakage current formed by the channel leakage to the gate in the device, so the thickness of the barrier layer in the heterojunction can be smaller, which can increase the threshold voltage; in addition, due to the in-situ
  • the arrangement of the insulating layer can reduce the square resistance, increase the concentration of the two-dimensional electron gas, improve the control ability of the gate to the channel, and increase the working current.
  • the arrangement of the transition layer can prevent the selective growth of p-type semiconductor on the in-situ insulating layer on the one hand, thereby improving the quality of the p-type semiconductor layer, and on the other hand, it can also prevent atoms (such as Si atoms) in the in-situ insulating layer. Diffusion into the p-type semiconductor layer affects the p-type semiconductor layer.
  • the heterojunction includes a channel layer and a barrier layer from bottom to top.
  • the channel layer and the barrier layer may each have one layer; or b) the channel layer and the barrier layer may each have multiple layers and are alternately distributed; or c) one layer of channel layer and two layers or More than two barrier layers to meet different functional requirements.
  • the heterojunction includes a GaN-based material.
  • the GaN-based material may include any one or a combination of GaN, AlGaN, and AlInGaN.
  • the semiconductor structure of the present invention has strong compatibility with existing HEMT devices.
  • the p-type semiconductor layer includes a GaN-based material.
  • the material of the transition layer includes: at least one of AlN, SiAlN, and AlGaN.
  • the GaN-based material may include any one or a combination of GaN, AlGaN, and AlInGaN.
  • the transition layer is formed by in-situ growth process, which can improve the quality of subsequent p-type semiconductor layers.
  • the non-gate region on the transition layer also has a p-type semiconductor layer.
  • the p-type semiconductor layer on the transition layer can be patterned, leaving only the p-type semiconductor layer in the gate area, consuming the excess two-dimensional electron gas under the gate.
  • the p-type semiconductor channel in the pole region may not be patterned, and the p-type semiconductor layer in the gate region and the non-gate region remain in the semiconductor structure.
  • the source and drain are in contact with the channel layer or the barrier layer to meet the requirements of different semiconductor structures.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure according to a first embodiment of the present invention
  • FIG. 2 is a flowchart of a manufacturing method of a semiconductor structure according to the first embodiment of the present invention
  • 3 to 5 are schematic diagrams of intermediate structures corresponding to the process in FIG. 2;
  • FIG. 6 is a schematic structural diagram of a semiconductor structure according to a second embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a semiconductor structure according to a third embodiment of the present invention.
  • FIG. 8 is a flowchart of a manufacturing method of a semiconductor structure according to a third embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a semiconductor structure according to a fourth embodiment of the present invention.
  • FIG. 10 is a flowchart of a manufacturing method of a semiconductor structure according to a fourth embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure according to a first embodiment of the present invention.
  • the semiconductor structure 1 includes:
  • the semiconductor substrate 10 may be sapphire, silicon carbide, silicon, GaN, or diamond.
  • the heterojunction 11 may include a channel layer 11a and a barrier layer 11b from bottom to top.
  • a two-dimensional electron gas may be formed at the interface between the channel layer 11a and the barrier layer 11b.
  • the channel layer 11a is an intrinsic GaN layer
  • the barrier layer 11b is an n-type AlGaN layer.
  • the combination of the channel layer 11a and the barrier layer 11b may also be GaN/AlN, GaN/InN, GaN/InAlGaN, GaAs/AlGaAs, GaN/InAlN or InN/InAlN.
  • the channel layer 11a and the barrier layer 11b shown in FIG. 1 having one layer respectively; the channel layer 11a and the barrier layer 11b may also have multiple layers respectively, which are alternately distributed; or one layer of the channel layer 11a And two or more barrier layers 11b to form a multi-barrier structure.
  • the material of the nucleation layer may be, for example, AlN, AlGaN, etc.
  • the material of the buffer layer may include AlN, GaN, AlGaN. , At least one of AlInGaN.
  • the nucleation layer can alleviate the epitaxial growth of the semiconductor layer, for example, the channel layer 11a in the heterojunction 11 and the semiconductor substrate 10 can alleviate the problem of lattice mismatch and thermal mismatch, and the buffer layer can reduce the epitaxial growth of the semiconductor. The dislocation density and defect density of the layer improve the crystal quality.
  • the in-situ insulating layer 12 is an insulating layer formed by an in-situ growth process.
  • One of the functions of the in-situ insulating layer 12 is to electrically insulate the gate 15b and the barrier layer 11b outside the groove 13.
  • the in-situ insulating layer 12 can also suppress the current collapse effect.
  • the in-situ insulating layer 12 has a single-layer structure, and the material of the single-layer structure includes one or a mixture of SiN and SiAlN.
  • the in-situ insulating layer 12 is a laminated structure, and the laminated structure from bottom to top may include: SiN layer and SiAlN layer, SiAlN layer and SiN layer, or SiN layer, SiAlN layer and SiN layer, etc. .
  • the transition layer 14 may be formed by an in-situ growth process.
  • the transition layer 14 has a single-layer structure, and the material of the single-layer structure may include: one or a mixture of AlN, SiAlN, and AlGaN.
  • the transition layer 14 has a laminated structure, and the laminated structure may include at least two layers of an AlN layer, a SiAlN layer, and an AlGaN layer.
  • the transition layer 14 of the above-mentioned material can solve the problem that the p-type GaN-based material cannot grow on the in-situ insulating layer 12, so the p-type semiconductor layer 15a can be formed outside the groove 13.
  • the p-type semiconductor layer 15a may be a GaN-based material, for example, at least one of AlN, GaN, AlGaN, and AlInGaN, and the p-type doping ions may be magnesium ions to deplete the two-dimensional electron gas under the gate region. To form an enhanced device.
  • the source electrode 16 and the drain electrode 17 are in contact with the barrier layer 11b, and an ohmic contact is formed between the two; an ohmic contact is also formed between the gate 15b and the p-type semiconductor layer 15a.
  • the source electrode 16, the drain electrode 17, and the gate electrode 15b can be made of metal, doped polysilicon and other existing conductive materials.
  • the in-situ insulating layer 12 and the transition layer 14 reduce the gate leakage current formed by the channel leaking to the gate 15b, so the thickness of the barrier layer 11b in the heterojunction 11 can be small, so that Lower the threshold voltage; in addition, due to the in-situ insulating layer 12, the surface resistance can be reduced, and the concentration of the two-dimensional electron gas can be increased, thereby improving the gate's ability to control the channel and increasing the operating current.
  • the arrangement of the transition layer 14 can prevent the selective growth of the p-type semiconductor layer 15a on the in-situ insulating layer 12 on the one hand, thereby improving the quality of the p-type semiconductor layer; on the other hand, it can also prevent the atoms in the in-situ insulating layer 12 (For example, Si atoms) diffuse into the p-type semiconductor layer and affect the p-type semiconductor layer.
  • the sheet resistance (area resistance) between the source 16 and the drain 17 can be reduced from 2300 ⁇ / ⁇ to 325 ⁇ / ⁇ , and the two-dimensional electron gas concentration in the heterojunction 11 can be reduced from 2.4E12/cm 2 increased to 1.03E13/cm 2 .
  • the thickness of the barrier layer 11b is 15 nm-25 nm to ensure the generation of a sufficient concentration of two-dimensional electron gas.
  • the thickness of the barrier layer 11b ranges from 1 nm to 15 nm, a sufficient concentration of two-dimensional electron gas can be generated; preferably, the thickness of the barrier layer 11b can be controlled below 10 nm.
  • FIG. 2 is a flowchart of a method for manufacturing a semiconductor structure according to the first embodiment of the present invention
  • FIGS. 3 to 5 are schematic diagrams of intermediate structures corresponding to the flow in FIG. 2.
  • a semiconductor substrate 10 is provided, and a heterojunction 11 is formed on the semiconductor substrate 10.
  • the semiconductor substrate 10 may be sapphire, silicon carbide, silicon, GaN, or diamond.
  • the heterojunction 11 may include a channel layer 11a and a barrier layer 11b from bottom to top.
  • the channel layer 11a is an intrinsic GaN layer
  • the barrier layer 11b is an n-type AlGaN layer.
  • the combination of the channel layer 11a and the barrier layer 11b can also be GaN/AlN, GaN/InN, GaN/InAlGaN, GaAs/AlGaAs, GaN/InAlN or InN/InAlN.
  • the formation process of the channel layer 11a and the barrier layer 11b may include: atomic layer deposition (ALD, Atomic Layer Deposition), or chemical vapor deposition (CVD, Chemical Vapor Deposition), or molecular beam epitaxial growth (MBE, Molecular Beam Epitaxy, or Plasma Enhanced Chemical Vapor Deposition (PECVD), or Low Pressure Chemical Vapor Deposition (LPCVD), or Metal Organic Chemical Vapor Deposition (MOCVD, Metal -Organic Chemical Vapor Deposition), or a combination thereof.
  • ALD Atomic Layer Deposition
  • CVD chemical vapor deposition
  • MBE molecular beam epitaxial growth
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • MOCVD Metal Organic Chemical Vapor Deposition
  • the channel layer 11a and the barrier layer 11b shown in FIG. 1 each having one layer; the channel layer 11a and the barrier layer 11b may also have multiple layers, and alternately distributed; or a layer of channel layer 11a and two One layer or two or more barrier layers 11b to form a multi-barrier structure.
  • a nucleation layer and a buffer layer may be formed in sequence.
  • the material of the nucleation layer may be, for example, AlN, AlGaN, etc., and the material of the buffer layer may include AlN. , At least one of GaN, AlGaN, AlInGaN.
  • the method of forming the buffer layer may be the same as the method of forming the heterojunction 11.
  • the nucleation layer can alleviate the epitaxial growth of the semiconductor layer, for example, the channel layer 11a in the heterojunction 11 and the semiconductor substrate 10 can alleviate the problem of lattice mismatch and thermal mismatch, and the buffer layer can reduce the epitaxial growth of the semiconductor.
  • the dislocation density and defect density of the layer improve the crystal quality.
  • an in-situ insulating layer 12 is formed on the heterojunction 11.
  • the in-situ insulating layer 12 is an insulating layer formed by an in-situ growth process.
  • the in-situ insulating layer 12 has a single-layer structure, and the material of the single-layer structure includes one or a mixture of SiN and SiAlN.
  • the in-situ insulating layer 12 is a laminated structure, which from bottom to top may include: SiN layer and SiAlN layer, SiAlN layer and SiN layer, or SiN layer, SiAlN layer and SiN layer, etc. .
  • step S3 in FIG. 2 and as shown in FIG. 4 a groove 13 penetrating the in-situ insulating layer 12 is formed.
  • the groove 13 can be formed by dry etching or wet etching. Specifically, a patterned mask layer is formed on the in-situ insulating layer 12 first.
  • the mask layer may be a photoresist layer, which is patterned by a process of exposure first and then development.
  • the dry etching gas can be CF4, C3F8, etc., and the wet etching solution can be hot phosphoric acid.
  • a transition layer 14 and a p-type semiconductor layer 15a are sequentially formed in the groove 13 and on the in-situ insulating layer 12; referring to FIG. 1, the p-type semiconductor layer is patterned In the layer 15a, the p-type semiconductor layer 15a in the gate region is reserved; the gate 15b is formed on the p-type semiconductor layer 15a in the gate region; the source 16 and the drain 17 are formed on both sides of the gate 15b.
  • the transition layer 14 may be formed by an in-situ growth process.
  • the transition layer 14 has a single-layer structure, and the material of the single-layer structure may include: one or a mixture of AlN, SiAlN, and AlGaN.
  • the transition layer 14 has a laminated structure, and the laminated structure may include at least two layers of an AlN layer, a SiAlN layer, and an AlGaN layer.
  • the p-type semiconductor layer 15a includes a GaN-based material, for example, at least one of GaN, AlGaN, and AlInGaN, and the p-type dopant ions therein may be magnesium ions.
  • the formation process of the p-type semiconductor layer 15a can refer to the formation process of the channel layer 11a and the barrier layer 11b.
  • the patterned p-type semiconductor layer 15a can be implemented by dry etching or wet etching. Compared with the scheme of patterning the p-type semiconductor layer 15a directly formed on the barrier layer 11b, the in-situ insulating layer 12 and the transition layer 14 can prevent the barrier layer 11b from being damaged by over-etching during the patterning process.
  • the source electrode 16, the drain electrode 17, and the gate electrode 15b can be made of existing conductive materials such as metal, doped polysilicon, etc., which are formed by physical vapor deposition or chemical vapor deposition.
  • FIG. 6 is a schematic structural diagram of a semiconductor structure according to a second embodiment of the present invention.
  • the semiconductor structure 2 of the second embodiment is substantially the same as the semiconductor structure 1 of the first embodiment, except that the source 16 and the drain 17 contact the channel layer 11a.
  • An ohmic contact is formed between the source electrode 16 and the channel layer 11a, and between the drain electrode 17 and the channel layer 11a.
  • the manufacturing method of the semiconductor structure 2 of the second embodiment is substantially the same as the manufacturing method of the semiconductor structure 1 of the first embodiment, except that in step S4, a source 16 and a drain 17 are formed on both sides of the gate 15b.
  • the p-type semiconductor layer 15a, the transition layer 14, the in-situ insulating layer 12, and the barrier layer 11b in the source region and the drain region are removed, and the channel layer 11a is exposed.
  • FIG. 7 is a schematic structural diagram of a semiconductor structure according to a third embodiment of the present invention.
  • FIG. 8 is a flowchart of a manufacturing method of a semiconductor structure according to a third embodiment of the present invention.
  • the semiconductor structure 3 of the third embodiment is substantially the same as the semiconductor structures 1 and 2 of the first and second embodiments. The only difference is: on the transition layer 14, outside the gate region The non-gate region also has a p-type semiconductor layer 15a.
  • step S4' the step of patterning the p-type semiconductor layer 15a is omitted.
  • step S4' includes: forming a transition layer 14 and a p-type semiconductor layer 15a in the groove 13 and on the in-situ insulating layer 12; forming a gate 15b on the p-type semiconductor layer 15a in the gate region; A source 16 and a drain 17 are formed on both sides of 15b.
  • FIG. 9 is a schematic structural diagram of a semiconductor structure according to a fourth embodiment of the present invention.
  • FIG. 10 is a flowchart of a manufacturing method of a semiconductor structure according to a fourth embodiment of the present invention.
  • the semiconductor structure 4 of the fourth embodiment is substantially the same as the semiconductor structure 1 of the first embodiment. The only difference is that the semiconductor structure 4 is an intermediate semiconductor structure, and the gate 15b, source 16 and Drain 17.
  • the manufacturing method of the semiconductor structure 4 of the fourth embodiment is substantially the same as the manufacturing method of the semiconductor structure 1 of the first embodiment. The only difference is that in step S4", the manufacturing of the gate is omitted. 15b. In the step of the source electrode 16 and the drain electrode 17, the p-type semiconductor layer 15a does not fill the groove 13.
  • the semiconductor structure 4 can also be produced and sold as a semi-finished product.

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Abstract

本申请提供了一种半导体结构及其制作方法，半导体结构中，异质结上形成有原位绝缘层，原位绝缘层中具有凹槽，在凹槽内以及原位绝缘层上具有过渡层，过渡层上的栅极区域形成有p型半导体层。过渡层利于工艺中p型半导体层在凹槽外形成。原位绝缘层与过渡层可以减小器件中沟道泄漏到栅极形成的栅泄漏电流，因而异质结中的势垒层的厚度可以较小，从而可以提高阈值电压；此外，由于原位绝缘层的设置，可减小方块电阻，增加二维电子气的浓度，提高了栅极对沟道的控制能力，提升工作电流。

Description

半导体结构及其制作方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及其制作方法。
背景技术
宽禁带半导体材料III族氮化物作为第三代半导体材料的典型代表，具有禁带宽带大、耐高压、耐高温、电子饱和速度和漂移速度高、容易形成高质量异质结构的优异特性，非常适合制造高温、高频、大功率电子器件。
例如AlGaN/GaN异质结由于较强的自发极化和压电极化，在AlGaN/GaN界面处存在高浓度的二维电子气(2DEG)，广泛应用于诸如高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)等半导体结构中。
增强型器件由于其常关的特性，在电力电子领域具有非常广泛应用。增强型器件的实现方式有很多种，例如在栅极处通过设置p型半导体耗尽二维电子气。
发明内容
然而本申请发明人发现：通过栅极处设置p型半导体实现的增强型器件，阈值电压较小，且该种方法需要刻蚀栅极区域以外的p型半导体，但刻蚀不可避免带来刻蚀损失。
为解决上述问题，本发明一方面提供一种半导体结构，包括：
自下而上分布的半导体衬底、异质结以及原位绝缘层；
贯穿所述原位绝缘层的凹槽；位于所述凹槽内以及所述原位绝缘层上的过渡层；
位于所述过渡层上的栅极区域的p型半导体层，所述p型半导体层未填满所述凹槽。
可选地，所述半导体结构还包括：位于所述p型半导体层上的栅极；以及位于所述栅极两侧的源极与漏极。
可选地，所述异质结自下而上包括沟道层与势垒层。
可选地，所述异质结包括GaN基材料。
可选地，所述原位绝缘层的材料包括：SiN、SiAlN中的至少一种；和/或所述过渡层的材料包括：AlN、SiAlN、AlGaN中的至少一种。
可选地，所述过渡层上的非栅极区域也具有所述p型半导体层。
可选地，所述异质结自下而上包括沟道层与势垒层，所述源极与漏极接触所述沟道层或所述势垒层。
本发明另一方面提供一种半导体结构的制作方法，包括：
提供半导体衬底，在所述半导体衬底上形成异质结；
在所述异质结上形成原位绝缘层；
形成贯穿所述原位绝缘层的凹槽；
在所述凹槽内以及所述原位绝缘层上形成过渡层与p型半导体层，所述p型半导体层未填满所述凹槽。
可选地，还包括：在栅极区域的p型半导体层上形成栅极；在所述栅极两侧形成源极与漏极。
可选地，所述异质结自下而上包括沟道层与势垒层。
可选地，所述异质结包括GaN基材料。
可选地，所述原位绝缘层的材料包括：SiN、SiAlN中的至少一种；和/或所述过渡层的材料包括：AlN、SiAlN、AlGaN中的至少一种。
可选地，还图形化所述p型半导体层，保留所述栅极区域的p型半导体层。
可选地，所述异质结自下而上包括沟道层与势垒层，所述源极与漏极接触所述沟道层或所述势垒层。
与现有技术相比，本发明的有益效果在于：
1)本发明的半导体结构中，异质结上形成有原位绝缘层，原位绝缘层中具有凹槽，在凹槽内以及原位绝缘层上具有过渡层，过渡层上的栅极区域形成有p型半导体层。过渡层利于工艺中p型半导体层在凹槽外形成。原位绝缘层与过渡层可以减小器件中沟道泄漏到栅极形成的栅泄漏电流，因而异质结中的势垒层的厚度可以较小，从而可以提高阈值电压；此外，由于原位绝缘层的设置，可减小方块电阻，增加二维电子气的浓度，提高了栅极对沟道的控制能力，提升工作电流。
过渡层的设置，一方面可避免p型半导体在原位绝缘层上的选择性生长，从而可以提高p型半导体层的质量，另一方面还可以防止原位绝缘层中原子(例如Si原子)扩散到p型半导体层中，对p型半导体层造成影响。
2)可选方案中，异质结自下而上包括沟道层与势垒层。具体地，a)沟道层与势垒层可以分别具有一层；或b)沟道层与势垒层可以分别具有多层，且交替分布；或c)一层沟道层与两层或两层以上的势垒层，以满足不同功能需求。
3)可选方案中，异质结包括GaN基材料。GaN基材料可以包括GaN、AlGaN、AlInGaN中的任一种或组合。本发明的半导体结构与现有HEMT器件兼容性强。
4)可选方案中，p型半导体层包括GaN基材料。过渡层的材料包括： AlN、SiAlN、AlGaN中的至少一种。GaN基材料可以包括GaN、AlGaN、AlInGaN中的任一种或组合。过渡层采用原位生长工艺形成，可以提升后续p型半导体层的质量。
5)可选方案中，过渡层上的非栅极区域也具有p型半导体层。换言之，过渡层上的p型半导体层可以经图形化，仅保留栅极区域的p型半导体层，消耗栅极下方的多余二维电子气，由于原位绝缘层和过渡层的存在，非栅极区域的p型半导体沟道也可以不经图形化，栅极区域与非栅极区域的p型半导体层都保留在半导体结构中。
6)可选方案中，源极与漏极接触沟道层或势垒层，满足不同半导体结构的需求。
附图说明
图1是本发明第一实施例的半导体结构的结构示意图；
图2是本发明第一实施例的半导体结构的制作方法的流程图；
图3至图5是图2中的流程对应的中间结构示意图；
图6是本发明第二实施例的半导体结构的结构示意图；
图7是本发明第三实施例的半导体结构的结构示意图；
图8是本发明第三实施例的半导体结构的制作方法的流程图；
图9是本发明第四实施例的半导体结构的结构示意图；
图10是本发明第四实施例的半导体结构的制作方法的流程图。
为方便理解本发明，以下列出本发明中出现的所有附图标记：
半导体结构1、2、3、4     [45]半导体衬底10
异质结11                   [47]原位绝缘层12
凹槽13                     [49]过渡层14
p型半导体层15a             [51]栅极15b
源极16                     [53]漏极17
沟道层11a                  [55]势垒层11b
具体实施方式
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1是本发明第一实施例的半导体结构的结构示意图。
参照图1所示，半导体结构1包括：
自下而上分布的半导体衬底10、异质结11以及原位绝缘层12；
贯穿原位绝缘层12的凹槽13；位于凹槽13内以及原位绝缘层12上的过渡层14；
位于过渡层14上的栅极区域的p型半导体层15a与栅极15b，以及位于栅极15b两侧的源极16与漏极17。
半导体衬底10可以为蓝宝石、碳化硅、硅、GaN或金刚石。
异质结11自下而上可以包括沟道层11a与势垒层11b。沟道层11a与势垒层11b的界面处可形成二维电子气。一个可选方案中，沟道层11a为本征GaN层，势垒层11b为n型AlGaN层。其它可选方案中，沟道层11a与势垒层11b组合还可以为GaN/AlN、GaN/InN、GaN/InAlGaN、GaAs/AlGaAs、GaN/InAlN或InN/InAlN。此外，除了图1所示的沟道层11a与势垒层11b分别具有一层外；沟道层11a与势垒层11b还可以分别具有多层，且交替分布； 或一层沟道层11a与两层或两层以上的势垒层11b，以形成多势垒结构。
异质结11与半导体衬底10之间还可以具有成核层及缓冲层(未图示)，成核层的材质可以例如为AlN、AlGaN等，缓冲层的材质可以包括AlN、GaN、AlGaN、AlInGaN中的至少一种。成核层可以缓解外延生长的半导体层，例如异质结11中的沟道层11a与半导体衬底10之间的缓解晶格失配和热失配的问题，缓冲层可以降低外延生长的半导体层的位错密度和缺陷密度，提升晶体质量。
原位绝缘层12是通过原位生长工艺形成的绝缘层。原位绝缘层12的作用之一在于：电绝缘凹槽13外的栅极15b与势垒层11b。HEMT结构中，原位绝缘层12还可以抑制电流崩塌效应。
一个可选方案中，原位绝缘层12为单层结构，该单层结构的材料包括：SiN、SiAlN中的一种或多种的混合物。另一个可选方案中，原位绝缘层12为叠层结构，该叠层结构自下而上可以包括：SiN层与SiAlN层，SiAlN层与SiN层，或SiN层、SiAlN层与SiN层等。
过渡层14可以采用原位生长工艺形成。一个可选方案中，过渡层14为单层结构，该单层结构的材料可以包括：AlN、SiAlN、AlGaN中的一种或多种的混合物。另一个可选方案中，过渡层14为叠层结构，该叠层结构可以包括：AlN层、SiAlN层、AlGaN层中的至少两层。上述材质的过渡层14能解决p型GaN基材料无法在原位绝缘层12上生长的问题，因而可以在凹槽13外形成p型半导体层15a。
p型半导体层15a可以为GaN基材料，例如为AlN、GaN、AlGaN、AlInGaN中的至少一种，其中的p型掺杂离子可以为镁离子，以耗尽栅极区域下方的二维电子气以形成增强型器件。
图1中，源极16与漏极17接触势垒层11b，且两者之间形成欧姆接触；栅极15b与p型半导体层15a之间也形成欧姆接触。源极16、漏极17、栅极 15b的材质可以为金属、掺杂多晶硅等现有的导电材质。
上述半导体结构1中，原位绝缘层12与过渡层14减小了沟道泄漏到栅极15b形成的栅泄漏电流，因而异质结11中的势垒层11b的厚度可以较小，从而可以降低阈值电压；此外，由于原位绝缘层12的设置，可降低面电阻，增加二维电子气的浓度，从而提高了栅极对沟道的控制能力，提升工作电流。
过渡层14的设置，一方面可避免p型半导体层15a在原位绝缘层12上的选择性生长，从而可以提高p型半导体层的质量；另一方面还可以防止原位绝缘层12中原子(例如Si原子)扩散到p型半导体层中，对p型半导体层造成影响。
为验证本发明的技术效果，以势垒层11b的厚度都为5nm为例，5nm Al0.25GaN势垒层/GaN沟道层半导体结构与5nm原位SiN层/5nm Al0.25GaN势垒层/GaN沟道层半导体结构进行对比，发现：源极16与漏极17之间的方块电阻(面电阻)可以从2300Ω/□降低到325Ω/□，异质结11中二维电子气浓度可以从2.4E12/cm 2增加到1.03E13/cm 2。
此外，现有的AlGaN势垒层/GaN沟道层的HEMT结构中，势垒层11b的厚度为15nm～25nm才能保证有足够浓度的二维电子气产生。而本申请中，势垒层11b的厚度范围为1nm～15nm时，就能产生足够浓度的二维电子气；较佳地，可将势垒层11b的厚度控制在10nm以下。
图2是本发明第一实施例的半导体结构的制作方法的流程图；图3至图5是图2中的流程对应的中间结构示意图。
首先，参照图2中的步骤S1与图3所示，提供半导体衬底10，在半导体衬底10上形成异质结11。
半导体衬底10可以为蓝宝石、碳化硅、硅、GaN或金刚石。
异质结11自下而上可以包括沟道层11a与势垒层11b。一个可选方案中，沟道层11a为本征GaN层，势垒层11b为n型AlGaN层。其它可选方案 中，沟道层11a与势垒层11b组合还可以为GaN/AlN、GaN/InN、GaN/InAlGaN、GaAs/AlGaAs、GaN/InAlN或InN/InAlN。沟道层11a与势垒层11b的形成工艺可以包括：原子层沉积法(ALD，Atomic layer deposition)、或化学气相沉积法(CVD，Chemical Vapor Deposition)、或分子束外延生长法(MBE，Molecular Beam Epitaxy)、或等离子体增强化学气相沉积法(PECVD，Plasma Enhanced Chemical Vapor Deposition)、或低压化学蒸发沉积法(LPCVD，Low Pressure Chemical Vapor Deposition)，或金属有机化合物化学气相沉积法(MOCVD，Metal-Organic Chemical Vapor Deposition)、或其组合方式。
除了图1所示的沟道层11a与势垒层11b分别具有一层外；沟道层11a与势垒层11b还可以分别具有多层，且交替分布；或一层沟道层11a与两层或两层以上的势垒层11b，以形成多势垒结构。
在半导体衬底10上形成异质结11之前，还可以先依次形成成核层及缓冲层(未图示)，成核层的材质可以例如为AlN、AlGaN等，缓冲层的材质可以包括AlN、GaN、AlGaN、AlInGaN中的至少一种。缓冲层的形成方法可以与异质结11的形成方法相同。成核层可以缓解外延生长的半导体层，例如异质结11中的沟道层11a与半导体衬底10之间的缓解晶格失配和热失配的问题，缓冲层可以降低外延生长的半导体层的位错密度和缺陷密度，提升晶体质量。
测试图3所示示例结构的方块电阻(面电阻)，大小为2300Ω/□。
接着，参照图2中的步骤S2与图4所示，在异质结11上形成原位绝缘层12。
原位绝缘层12是通过原位生长工艺形成的绝缘层。一个可选方案中，原位绝缘层12为单层结构，该单层结构的材料包括：SiN、SiAlN中的一种或多种的混合物。另一个可选方案中，原位绝缘层12为叠层结构，该叠层结构自下而上可以包括：SiN层与SiAlN层，SiAlN层与SiN层，或SiN层、SiAlN 层与SiN层等。
之后，参照图2中的步骤S3与图4所示，形成贯穿原位绝缘层12的凹槽13。
凹槽13可以采用干法刻蚀或湿法刻蚀形成。具体地，先在原位绝缘层12上形成图形化掩膜层。掩膜层可以为光刻胶层，采用先曝光、后显影工艺进行图形化。干法刻蚀气体可以为CF4、C3F8等，湿法刻蚀溶液可以为热磷酸。
测试图4所示示例结构的方块电阻(面电阻)，大小为325Ω/□。
接着，参照图2中的步骤S4与图5所示，在凹槽13内以及原位绝缘层12上依次形成过渡层14与p型半导体层15a；参照图1所示，图形化p型半导体层15a，保留栅极区域的p型半导体层15a；在栅极区域的p型半导体层15a上形成栅极15b；在栅极15b两侧形成源极16与漏极17。
过渡层14可以采用原位生长工艺形成。一个可选方案中，过渡层14为单层结构，该单层结构的材料可以包括：AlN、SiAlN、AlGaN中的一种或多种的混合物。另一个可选方案中，过渡层14为叠层结构，该叠层结构可以包括：AlN层、SiAlN层、AlGaN层中的至少两层。
p型半导体层15a包括GaN基材料，例如为GaN、AlGaN、AlInGaN中的至少一种，其中的p型掺杂离子可以为镁离子。p型半导体层15a的形成工艺可以参照沟道层11a与势垒层11b的形成工艺。
图形化p型半导体层15a可以采用干法刻蚀或湿法刻蚀实现。相对于对直接形成在势垒层11b上的p型半导体层15a进行图形化的方案，原位绝缘层12与过渡层14可防止图形化工艺中的过刻蚀损伤势垒层11b。
源极16、漏极17、栅极15b的材质可以为金属、掺杂多晶硅等现有的导电材质，对应采用物理气相沉积法或化学气相沉积法形成。
图6是本发明第二实施例的半导体结构的结构示意图。
参照图6与图1所示，本实施例二的半导体结构2与实施例一的半导体结构1大致相同，区别仅在于：源极16与漏极17接触沟道层11a。
源极16与沟道层11a之间、漏极17与沟道层11a之间都形成欧姆接触。
对应地，本实施例二的半导体结构2的制作方法与实施例一的半导体结构1的制作方法大致相同，区别仅在于：步骤S4中，在栅极15b两侧形成源极16与漏极17时，去除源极区域与漏极区域的p型半导体层15a、过渡层14、原位绝缘层12以及势垒层11b，暴露沟道层11a。
图7是本发明第三实施例的半导体结构的结构示意图。图8是本发明第三实施例的半导体结构的制作方法的流程图。
参照图7、图1与图6所示，本实施例三的半导体结构3与实施例一、实施例二的半导体结构1、2大致相同，区别仅在于：过渡层14上，栅极区域以外的非栅极区域也具有p型半导体层15a。
对应地，参照图8与图2所示，本实施例三的半导体结构3的制作方法与实施例一、实施例二的半导体结构1、2的制作方法大致相同，区别仅在于：步骤S4'中，省略图形化p型半导体层15a的步骤。换言之，步骤S4'包括：在凹槽13内以及原位绝缘层12上依次形成过渡层14与p型半导体层15a；在栅极区域的p型半导体层15a上形成栅极15b；在栅极15b两侧形成源极16与漏极17。
图9是本发明第四实施例的半导体结构的结构示意图。图10是本发明第四实施例的半导体结构的制作方法的流程图。参照图9与图1所示，本实施例四的半导体结构4与实施例一的半导体结构1大致相同，区别仅在于：半导体结构4为中间半导体结构，未制作栅极15b、源极16与漏极17。
对应地，参照图10与图2所示，本实施例四的半导体结构4的制作方法与实施例一的半导体结构1的制作方法大致相同，区别仅在于：步骤S4"中，省略制作栅极15b、源极16与漏极17的步骤，p型半导体层15a未填满 凹槽13。
半导体结构4也可以作为半成品生产与销售。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (14)

  1. 一种半导体结构，其特征在于，包括：
    自下而上分布的半导体衬底(10)、异质结(11)以及原位绝缘层(12)；
    贯穿所述原位绝缘层(12)的凹槽(13)；位于所述凹槽(13)内以及所述原位绝缘层(12)上的过渡层(14)；
    位于所述过渡层(14)上的栅极区域的p型半导体层(15a)，所述p型半导体层(15a)未填满所述凹槽(13)。
  2. 根据权利要求1所述的半导体结构，其特征在于，所述半导体结构还包括：位于所述p型半导体层(15a)上的栅极(15b)；以及位于所述栅极(15b)两侧的源极(16)与漏极(17)。
  3. 根据权利要求1或2所述的半导体结构，其特征在于，所述异质结(11)自下而上包括沟道层(11a)与势垒层(11b)。
  4. 根据权利要求1或2所述的半导体结构，其特征在于，所述异质结(11)包括GaN基材料。
  5. 根据权利要求1或2所述的半导体结构，其特征在于，所述原位绝缘层(12)的材料包括：SiN、SiAlN中的至少一种；和/或所述过渡层(14)的材料包括：AlN、SiAlN、AlGaN中的至少一种。
  6. 根据权利要求1或2所述的半导体结构，其特征在于，所述过渡层(14)上的非栅极区域也具有所述p型半导体层(15a)。
  7. 根据权利要求2所述的半导体结构，其特征在于，所述异质结(11)自下而上包括沟道层(11a)与势垒层(11b)，所述源极(16)与漏极(17)接触所述沟道层(11a)或所述势垒层(11b)。
  8. 一种半导体结构的制作方法，其特征在于，包括：
    提供半导体衬底(10)，在所述半导体衬底(10)上形成异质结(11)；
    在所述异质结(11)上形成原位绝缘层(12)；
    形成贯穿所述原位绝缘层(12)的凹槽(13)；
    在所述凹槽(13)内以及所述原位绝缘层(12)上形成过渡层(14)与p型半导体层(15a)，所述p型半导体层(15a)未填满所述凹槽(13)。
  9. 根据权利要求8所述的半导体结构的制作方法，其特征在于，还包括：在栅极区域的p型半导体层(15a)上形成栅极(15b)；在所述栅极(15b)两侧形成源极(16)与漏极(17)。
  10. 根据权利要求8或9所述的半导体结构的制作方法，其特征在于，所述异质结(11)自下而上包括沟道层(11a)与势垒层(11b)。
  11. 根据权利要求8或9所述的半导体结构的制作方法，其特征在于，所述异质结(11)包括GaN基材料。
  12. 根据权利要求8或9所述的半导体结构的制作方法，其特征在于，所述原位绝缘层(12)的材料包括：SiN、SiAlN中的至少一种；和/或所述过渡层(14)的材料包括：AlN、SiAlN、AlGaN中的至少一种。
  13. 根据权利要求8或9所述的半导体结构的制作方法，其特征在于，还图形化所述p型半导体层(15a)，保留所述栅极区域的p型半导体层(15a)。
  14. 根据权利要求9所述的半导体结构的制作方法，其特征在于，所述异质结(11)自下而上包括沟道层(11a)与势垒层(11b)，所述源极(16)与漏极(17)接触所述沟道层(11a)或所述势垒层(11b)。
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