WO2021092601A2

WO2021092601A2 - Techniques for calibrating 50% duty cycle differential frequency doubler

Info

Publication number: WO2021092601A2
Application number: PCT/US2020/067195
Authority: WO
Inventors: Timothy MCHUGH; Brian Iehl; Larry Connell
Original assignee: Futurewei Technologies, Inc.
Priority date: 2020-09-25
Filing date: 2020-12-28
Publication date: 2021-05-14
Also published as: CN116806413A; WO2021092601A3

Abstract

A frequency doubler circuit is presented that provides a way to quickly and simply calibrate the phase delay required for a differential 50% output duty cycle frequency doubler in a manner that is low in cost and current drain. A fully differential approach is used, in which the components of a differential input signal are used to generate a differential output signal and a delayed differential output signal. The differential output signal and the delayed differential output signal are combined in the logic circuitry to determine the components of the differential double frequency output signal. Outputs of the logic circuitry are used to adjust the amount of delay in the delayed output signal so that the double frequency output signal has a duty cycle of 50%. In some embodiments, the positive and negative components of the delayed signal can be adjusted independently.

Description

TECHNIQUES FOR CALIBRATING 50% DUTY CYCLE DIFFERENTIAL FREQUENCY DOUBLER PRIORITY [0001] This application claims priority to U.S. Provisional Patent Application No. 63/083,758, entitled “Techniques for Calibrating 50% Duty Cycle Differential Frequency Doubler” and filed September 25, 2020 by McHugh et al., which is incorporated by reference in its entirety. FIELD [0002] This disclosure generally relates to architectures for oscillators for generating clock signals. BACKGROUND [0003] As wireless terminals, such as cellular phones, are developed to communicate at higher frequencies, local oscillator for receivers and transmitters tend to produce a frequency without a stable duty cycle at the needed higher frequency values. SUMMARY [0004] According to one aspect of the present disclosure, a frequency doubler circuit includes a phase delay circuit, logic circuitry, and a control circuit. The phase delay circuit is configured to receive a differential input clock signal, receive one or more control signals, generate a differential output clock signal from the differential input clock signal, and generate a differential delayed output clock signal from the differential input clock signal by delaying the differential output clock signal in response to the one or more control signals. The logic circuitry is configured to receive the differential output clock signal and the differential delayed output clock signal and generate as output a double-frequency differential clock signal from the differential output clock signal and the differential delayed output clock signal. The control circuit configured to receive one or more outputs of the logic circuitry and generate therefrom the one or more control signals. [0005] Optionally, in the preceding aspect, the control circuit comprises: one or more comparators each configured to receive one or more outputs of the logic circuitry a generate corresponding comparator output; and a state machine configured to receive the corresponding output of the one or more comparators and generate therefrom the one or more control signals. [0006] Optionally, in the preceding aspect, the control circuit further comprises a detector circuit, including for each of the one or more of the outputs of the logic circuitry, a corresponding resistor through which the output of the logic circuit is supplied to a corresponding input of one of the comparators and a capacitor connected between the corresponding input and ground. [0007] Optionally, in any of the preceding two aspects, the one or more comparators includes a first comparator configured to receive a first component of the double-frequency differential clock signal at a first input and a second component of the double-frequency differential clock signal at a second input. [0008] Optionally, in any of the preceding three aspects, the differential output clock signal includes a positive component and a negative component and the differential delayed output clock signal includes a positive component and a negative component. The logic circuitry includes: a first NAND gate configured to receive as inputs the negative component of the differential output clock signal and the positive component of the differential delayed output clock signal; and a second NAND gate configured to receive as inputs the positive component of the differential output clock signal and the negative component of the differential delayed output clock signal. The one or more comparators includes: a first comparator configured to receive an output of the first NAND gate and a reference voltage; and a second comparator configured to receive an output of the second NAND gate and the reference voltage. [0009] Optionally, in any of the preceding aspects the logic circuitry includes: a differential input exclusive NOR gate configured to receive the differential output clock signal and the differential delayed output clock signal and provide a positive component of the double-frequency differential clock signal; and a differential input exclusive OR gate configured to receive the differential output clock signal and the differential delayed output clock signal and provide a negative component of the double-frequency differential clock signal. [0010] Optionally, in any of the preceding aspects, the differential input clock signal includes a positive component and a negative component, the differential output clock signal includes a positive component and a negative component, and the differential delayed output clock signal includes a positive component and a negative component, wherein the phase delay circuit includes: a first variable delay circuit configure to receive the positive component of the differential input clock signal and generate the positive component of the differential output clock having phase delay dependent on a first subset of the one or more control signals; and a second variable delay circuit configure to receive the negative component of the differential input clock signal and generate the negative component of the differential output clock having phase delay dependent on a second subset of the one or more control signals, the second subset of the one or more control signals being distinct from the first subset of the one or more control signals. [0011] Optionally, in the preceding aspect, each of first and second variable delay circuits include: a plurality of series connected inverters, one or more of which are of variable gain inverters, the gain of each of the variable gain inverters adjustable in response to one of the corresponding subset of the one or more control signals; and one or more variable capacitances each connected between an output of a corresponding one of the variable gain inverters, the capacitance of each of the variable capacitances adjustable in response to one of the corresponding subset of the one or more control signals. [0012] Optionally, in any of the preceding aspects, the control circuit is further configured to generate the one or more control signals such that a duty cycle of the double-frequency differential clock signal is 50%. [0013] Optionally, in any of the preceding aspects, the phase delay circuit includes: a first invertor configured to receive a positive component of the differential input clock signal and generate therefrom a positive component of the differential output clock signal; and a second invertor configured to receive a negative component of the differential input clock signal and generate therefrom a negative component of the differential output clock signal. [0014] Optionally, in any of the preceding aspects, the differential delayed output clock signal includes a positive component and a negative component, the differential input clock signal includes a positive component and a negative component and the phase delay circuit is further configured to generate the differential delayed output clock signal from the differential input clock signal by independently delaying the positive and negative components of the differential output clock signal in response to the one or more control signals. [0015] Optionally, in any of the preceding aspects, the phase delay circuit, logic circuitry, and control circuit are formed on a single integrated circuit. [0016] Optionally, in any of the preceding aspects, where the control circuit is configured to tune the one or more control signals to optimize the frequency doubler circuit’s operation. [0017] According to another aspect of the present disclosure, a method of generating a double-frequency differential clock signal includes: receiving a differential input clock signal having a positive component and a negative component; generating a differential output clock signal having a positive component and a negative component from the components of the differential input clock signal; and generating a differential delayed output clock signal having a positive component and a negative component by delaying the components of the differential input clock signal in response to one or more control signals. The method also includes: generating a positive component for the double-frequency differential clock signal by a first logical combination of the components of differential output clock signal and the differential delayed output clock signal; generating a negative component for the double- frequency differential clock signal by a second logical combination of the components of differential output clock signal and the differential delayed output clock signal; and determining the one or more control signals from a plurality of outputs from one or both of the first logical combination and the second logical combination. [0018] Optionally, in the preceding aspect, generating the differential delayed output clock includes independently delaying the positive and negative components of the differential output clock signal in response to the one or more control signals. [0019] Optionally, in any of the preceding aspects of a method of generating a double-frequency differential clock signal, the one or more control signals are determined such that a duty cycle of the double-frequency differential clock signal is 50%. [0020] Optionally, in any of the preceding aspects of a method of generating a double-frequency differential clock signal, determining the one or more control signals includes comparing the positive component for the double-frequency differential clock signal with the negative component for the double-frequency differential clock signal. [0021] Optionally, in any of the preceding aspects of a method of generating a double-frequency differential clock signal, determining the one or more control signals includes: comparing a logical NAND of the negative component of the differential output clock signal and the positive component of the differential delayed output clock signal with a reference voltage; and comparing a logical NAND of the positive component of the differential output clock signal and the negative component of the differential delayed output clock with a reference voltage. [0022] Optionally, in any of the preceding aspects of a method of generating a double-frequency differential clock signal, the first logical combination is a differential input exclusive OR and the second logical combination is a differential input exclusive NOR. [0023] Optionally, in any of the preceding aspects of a method of generating a double-frequency differential clock signal, determining the one or more control signals includes tuning the one or more control signals to optimize the frequency doubler circuit's operation. [0024] According to another aspect of the present disclosure, a transceiver includes a local oscillator circuit and a mixer. The local oscillator circuit includes: a digitally controlled oscillator configured to generate a first clock signal of a first frequency and a frequency doubler configured to receive a differential form of the first clock signal and generate therefrom a differential double-frequency clock signal. The frequency doubler includes: a phase delay circuit configured to receive the differential form of the first clock signal and one or more control signals and generate therefrom a differential output clock signal and a differential delayed output clock signal by delaying the differential form of the first clock signal in response to the one or more control signals; logic circuitry configured to receive the differential output clock signal and the differential delayed output clock signal and generate the differential double- frequency clock signal from the differential output clock signal and the differential delayed output clock signal; and a control circuit configured to receive one or more outputs of the logic circuitry and generate therefrom the one or more control signals. The mixer is configured to receive and mix the differential double-frequency clock signal with an input signal to generate an output signal. [0025] Optionally, in the preceding aspect of a transceiver, the local oscillator circuit and mixer are part of a transmitter path, the input signal is a baseband input signal and the output signal is a radio frequency (RF) output signal. [0026] Optionally, in any of the preceding aspects of a transceiver, the local oscillator circuit and mixer are part of a receiver path, the input signal is a radio frequency (RF) input signal and the output signal is a baseband output signal. [0027] Optionally, in any of the preceding aspects of a transceiver, the control circuit comprises: one or more comparators each configured to receive one or more outputs of the logic circuitry and generate a corresponding comparator output; and a state machine configured to receive the corresponding output of the one or more comparators and generate therefrom the one or more control signals. [0028] Optionally, in the preceding aspect, the control circuit further comprises a detector circuit, including for each of the one or more of the outputs of the logic circuitry, a corresponding resistor through which the output of the logic circuit is supplied to a corresponding input of one of the comparators and a capacitor connected between the corresponding input and ground. [0029] Optionally, in any of the preceding two aspects of a transceiver, the one or more comparators includes a first comparator configured to receive a first component of the differential double-frequency clock signal at a first input and a second component of the differential double-frequency clock signal at a second input. [0030] Optionally, in any of the three preceding aspects of a transceiver, the differential output clock signal includes a positive component and a negative component and the differential delayed output clock signal includes a positive component and a negative component. The logic circuitry includes: a first NAND gate configured to receive as inputs the negative component of the differential output clock signal and the positive component of the differential delayed output clock signal; and a second NAND gate configured to receive as inputs the positive component of the differential output clock signal and the negative component of the differential delayed output clock signal. The one or more comparators includes: a first comparator configured to receive the output of the first NAND gate and a reference voltage; and a second comparator configured to receive the output of the second NAND gate and the reference voltage. [0031] Optionally, in any of the four preceding aspects of a transceiver, the logic circuitry includes: a differential input exclusive NOR gate configured to receive the differential output clock signal and the differential delayed output clock signal and provide a positive component of the differential double-frequency clock signal; and a differential input exclusive OR gate configured to receive the differential output clock signal and the differential delayed output clock signal and provide a negative component of the differential double-frequency clock signal. [0032] Optionally, in any of the five preceding aspects of a transceiver, the differential form of the first clock signal includes a positive component and a negative component, the differential output clock signal includes a positive component and a negative component, and the differential delayed output clock signal includes a positive component and a negative component, wherein the phase delay circuit includes: a first variable delay circuit configure to receive the positive component of the differential input clock signal and generate the positive component of the differential output clock having phase delay dependent on a first subset of the one or more control signals; and a second variable delay circuit configure to receive the negative component of the differential input clock signal and generate the negative component of the differential output clock having phase delay dependent on a second subset of the one or more control signals, the second subset of the one or more control signals being distinct from the first subset of the one or more control signals. [0033] Optionally, in the preceding aspect of a transceiver, each of first and second variable delay circuits include: a plurality of series connected inverters, one or more of which are of variable gain inverters, the gain of each of the variable gain inverters adjustable in response to one of the corresponding subset of the one or more control signals; and one or more variable capacitances each connected between an output of a corresponding one of the variable gain inverters, the capacitance of each of the variable capacitances adjustable in response to one of the corresponding subset of the one or more control signals. [0034] Optionally, in any of the preceding aspects of a transceiver, the control circuit is further configured to generate the one or more control signals such that a duty cycle of a differential double-frequency clock signal is 50%. [0035] Optionally, in any of the preceding aspects of a transceiver, the phase delay circuit includes: a first invertor configured to receive a positive component of differential form of the first clock signal and generate therefrom a positive component of the differential output clock signal; and a second invertor configured to receive a negative component of differential form of the first clock signal and generate therefrom a negative component of the differential output clock signal. [0036] Optionally, in any of the preceding aspects of a transceiver, the differential delayed output clock signal includes a positive component and a negative component, the differential input clock signal includes a positive component and a negative component and the phase delay circuit is further configured to generate the differential delayed output clock signal from the differential input clock signal by independently delaying the positive and negative components of the differential output clock signal in response to the one or more control signals. [0037] Optionally, in any of the preceding aspects of a transceiver, the phase delay circuit, logic circuitry, and control circuit are formed on a single integrated circuit. [0038] Optionally, in any of the preceding aspects of a transceiver, the transceiver is component of a cellular telephone. [0039] Optionally, in any of the preceding aspects of a transceiver, the control circuit is configured to tune the one or more control signals to optimize the frequency doubler circuit’s operation. [0040] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all disadvantages noted in the Background. BRIEF DESCRIPTION OF THE DRAWINGS [0041] Aspects of the present disclosure are illustrated by way of example and are not limited by the accompanying figures for which like references indicate elements. [0042] FIG.1 illustrates a wireless network for communicating data. [0043] FIG. 2 is block diagram of a wireless communication system that can be used in a network such as in FIG.1. [0044] FIG.3 shows a common implementation of a differential frequency doubler. [0045] FIG. 4 is a timing diagram for the common implementation of a frequency doubler as illustrated in FIG.3. [0046] FIG.5 is a block diagram of a first embodiment for a differential frequency doubler. [0047] FIG.6 is a diagram of an implementation of the differential input XOR and XNOR logic circuits of FIG.5. [0048] FIG. 7 shows the implementation of the second NAND gate whose inputs are labeled NAND0 and NAND1 in FIG.6. [0049] FIG. 8 is a timing diagram that corresponds to the differential frequency doubler implementation. [0050] FIG. 9 is a block diagram of the 50% Duty Cycle Differential Frequency Doubler showing more detail of the phase delay block. [0051] FIG.10 illustrates an embodiment of a segmented inverter structure where each segment is equally weighted and switched in thermometer fashion. [0052] FIG. 11 illustrates an embodiment of a switchable capacitor bank where capacitors are equally weighted and switched in thermometer fashion. [0053] FIG. 12 illustrates an embodiment of a switchable capacitor bank where capacitors are binary weighted. [0054] FIG.13 is a differential frequency doubler embodiment diagram expanded to show an implementation of the detection and search control circuitry. [0055] FIG.14 is a flowchart of one embodiment for an embodiment of a method of operating the frequency doubler circuitry of embodiments presented in this document. [0056] FIGs. 15 and 16 illustrate a differential frequency doubler shown in a local oscillator transmit and receive path including additional adjustment mechanisms. [0057] FIG. 17 illustrates an alternate embodiment for the detection of the differential frequency doubler phase delay. [0058] FIG. 18 illustrates an embodiment that combines features of the embodiments of FIGs.5 and 17. DETAILED DESCRIPTION [0059] The present disclosure will now be described with reference to the figures, which in general relate to a frequency doubler circuit that can be used to generate an output signal with a calibrated 50% duty cycle whose frequency is twice that of the signal at its input. A fully differential approach is used, in which both the positive and negative components of an input signal are used to generate a differential output signal and a delayed differential output signal. The differential output signal and the delayed differential output signal are combined in the logic circuitry of a differential exclusive NOR gate, to provide a positive component of a double frequency output signal, and a differential exclusive OR gate, to provide a negative component of the double frequency output signal. Outputs of the logic circuitry are used to adjust the amount of delay in the delayed output signal so that the double frequency output signal has a duty cycle of 50%. In some embodiments, the positive and negative components of the delayed signal can be adjusted independently. [0060] It is understood that the present embodiments of the disclosure may be implemented in many different forms and that claims scopes should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the inventive embodiment concepts to those skilled in the art. Indeed, the disclosure is intended to cover alternatives, modifications, and equivalents of these embodiments, which are included within the scope and spirit of the disclosure as defined by the appended claims. Furthermore, in the following detailed description of the present embodiments of the disclosure, numerous specific details are set forth in order to provide a thorough understanding. However, it will be clear to those of ordinary skill in the art that the present embodiments of the disclosure may be practiced without such specific details. [0061] FIG. 1 illustrates a wireless network for communicating data. The communication system 100 includes, for example, user equipment 11A-11C, radio access networks (RANs) 12A-12B, a core network 13, a public switched telephone network (PSTN) 14, the Internet 15, and other networks 16. Additional or alternative networks include private and public data-packet networks including corporate intranets. While certain numbers of these components or elements are shown in the figure, any number of these components or elements may be included in the system 10. [0062] In one embodiment, the wireless network may be a fifth generation (5G) network including at least one 5G base station which employs orthogonal frequency- division multiplexing (OFDM) and/or non-OFDM and a transmission time interval (TTI) shorter than 1 millisecond (ms) (e.g., 100 or 200 microseconds), to communicate with the communication devices. In general, a reference to base station may refer any of the eNB and the 5G base stations (gNB). In addition, the network may further include a network server for processing information received from the communication devices via the at least one eNB or gNB base station. [0063] System 10 enables multiple wireless users to transmit and receive data and other content. The system 10 may implement one or more channel access methods, such as but not limited to code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), or single-carrier FDMA (SC-FDMA). [0064] The user equipment (UE) 11A-11C are configured to operate and/or communicate in the system 10. For example, the user equipment 11A-11C are configured to transmit and/or receive wireless signals or wired signals. Each user equipment 11A-11C represents any suitable end user device and may include such devices (or may be referred to) as a user equipment/device, wireless transmit/receive unit (UE), mobile station, fixed or mobile subscriber unit, pager, cellular telephone, personal digital assistant (PDA), smartphone, laptop, computer, touchpad, wireless sensor, wearable devices or consumer electronics device. [0065] While not shown here, it should be understood that the UEs 11A-11C are also configured to communicate using other communication technologies includes Wireless Local Area Network protocol systems and personal area network systems such as, for example, Bluetooth® and even Radio Frequency Identification systems. The disclosure herein specifically includes using the disclosed innovation for such communications. [0066] In the depicted embodiment, the RANs 12A-12B include one or more base stations 17A, 17B (collectively, base stations 17), respectively. Each of the base stations 17 is configured to wirelessly interface with one or more of the UEs 11A, 11B, 11C to enable access to the core network 13, the PSTN 14, the Internet 15, and/or the other networks 16. For example, the base stations (BSs) 17 may include one or more of several well-known devices, such as a base transceiver station (BTS), a Node-B (NodeB), an evolved NodeB (eNB), a next (fifth) generation (5G) NodeB (gNB), a Home NodeB, a Home eNodeB, a site controller, an access point (AP), or a wireless router, or a server, router, switch, or other processing entity with a wired or wireless network. [0067] In one embodiment, the base station 17A forms part of the RAN 12A, which may include other base stations, elements, and/or devices. Similarly, the base station 17B forms part of the RAN 12B, which may include other base stations, elements, and/or devices. Each of the base stations 17 operates to transmit and/or receive wireless signals within a particular geographic region or area, sometimes referred to as a “cell.” In some embodiments, multiple-input multiple-output (MIMO) technology may be employed having multiple transceivers for each cell. [0068] The base stations 17 communicate with one or more of the user equipment 11A-11C over one or more air interfaces (not shown) using wireless communication links. The air interfaces may utilize any suitable radio access technology. [0069] It is contemplated that the system 10 may use multiple channel access functionality, including for example schemes in which the base stations 17 and user equipment 11A-11C are configured to implement the Long Term Evolution wireless communication standard (LTE), LTE Advanced (LTE-A), and/or LTE Multimedia Broadcast Multicast Service (MBMS). In other embodiments, the base stations 17 and user equipment 11A-11C are configured to implement UMTS, HSPA, or HSPA+ standards and protocols. Of course, other multiple access schemes and wireless protocols may be utilized. [0070] The RANs 12A-12B are in communication with the core network 13 to provide the user equipment 11A-11C with voice, data, application, Voice over Internet Protocol (VoIP), or other services. As appreciated, the RANs 12A-12B and/or the core network 13 may be in direct or indirect communication with one or more other RANs (not shown). The core network 13 may also serve as a gateway access for other networks (such as PSTN 14, Internet 15, and other networks 16). In addition, some or all of the user equipment 11A-11C may include functionality for communicating with different wireless networks over different wireless links using different wireless technologies and/or protocols. [0071] The RANs 12A-12B may also include millimeter and/or microwave access points (APs). The APs may be part of the base stations 17 or may be located remote from the base stations 17. The APs may include, but are not limited to, a connection point (a millimeter wave, or mmW, CP) or a base station 17 capable of mmW communication (e.g., a mmW base station). The mmW APs may transmit and receive signals in a frequency range, for example, from 24 GHz to 100 GHz, but are not required to operate throughout this range. As used herein, the term base station is used to refer to a base station and/or a wireless access point. [0072] Although FIG.1 illustrates one example of a communication system, various changes may be made to FIG. 1. For example, the communication system 10 could include any number of user equipment, base stations, networks, or other components in any suitable configuration. It is also appreciated that the term user equipment may refer to any type of wireless device communicating with a radio network node in a cellular or mobile communication system. Non-limiting examples of user equipment are a target device, device-to-device (D2D) user equipment, machine type user equipment or user equipment capable of machine-to-machine (M2M) communication, laptops, PDA, iPad, Tablet, mobile terminals, smart phones, laptop embedded equipped (LEE), laptop mounted equipment (LME) and USB dongles. [0073] FIG.2 is block diagram of a wireless communication system 100, such as a mobile phone or user equipment 11A-11C or base station 17, showing some of the elements discussed in relation to the following figures. To transmit an output signal from the circuit elements of processor 111, a transmitter (Tx) RF 101 up-converts the output signal from either a baseband or an intermediate frequency (IF) range, and also amplifies and filters an outgoing transmit signal before supplying the transmit signal to the antenna 103. The transmitter (Tx) RF/analog section 101 can also be configured to perform other processes to prepare the outgoing transmit signal. The transmitter section 101 will typically include a local oscillator (LO) 105 for use in generating the output signals. As previously suggested, system 100 may have a plurality of Tx RF blocks 101 and Rx RF blocks 102 to support the various types of communications disclosed herein. [0074] Signals are received by the antenna 103 and supplied to a receiver (Rx) RF 102. Rx section 102 performs any needed or wanted signal processing, such as down- conversion from the radio frequency (RF) range to the intermediate frequency (IF) range and filtering, before passing the signal on to other elements on the device represented at processor 111. The receiver section 102 will typically include a local oscillator (LO) 107 for use in demodulating the input signals. In the following, “transceiver” may be used generally to refer a combined transmitter/receiver, separate transceiver and receiver sections, or an embodiment in which one or more components (e.g., local oscillators) are shared between the transmitter and receiver. Although FIG. 2 shows each of the transmitter section 101 and receiver section 102 having separate local oscillators (105, 107), in some embodiments they can share a single LO. [0075] As wireless terminals, such as a cellular phones, move to higher frequencies it becomes increasingly difficult to for local oscillators to provide a stable output signal with a stable duty cycle. One way to provide a higher local oscillator frequency is by use of a frequency doubler circuit, whose output is a signal whose frequency is twice that of the signal at its input. This approach can have advantages to the design of a system, such as decreased complexity of the signal source that drives the doubler or reduced current drain of the signal source since it runs at a lower frequency. [0076] The general principal of frequency doubler operation is to XOR the input signal with a phase delayed version of the input signal. The phase delay or shift is nominally 90 degrees, resulting in a duty cycle that is nominally 50%. The input and output signals are typically square wave signals. The duty cycle of the frequency doubler output signal is a function of the how close the phase delay is to 90 degrees. The phase delay is typically achieved by a length of transmission line, a series of gates or amplifiers, a capacitive network, a resistor-capacitor network, or a combination of these. The network required to achieve this phase delay is a function of the input frequency. For some systems that operate at a single input frequency or where the accuracy of the duty cycle at the frequency doubler output is not very stringent, no calibration of the phase delay network may be required. However, for those systems that need to operate over a range of input frequencies or where the accuracy of the frequency doubler output duty cycle is critical, calibrating the phase delay can improve performance. [0077] FIG.3 shows a common implementation of a differential frequency doubler. The phase delay circuit of FIG. 3 has two outputs. A first phase delay circuit 301 receives a input clock Clk_in and generates an output clock signal Clk_out signal, which is a duplicate of the Clk_in signal with an arbitrary phase delay, and a delayed output clock signal Clk_dly_out signal, which is a duplicate of Clk_out with a nominal phase delay of 90 degrees with reference to Clk_out. Clk_out and Clk_dly_out are exclusive OR’ed (XOR) in an XOR gate 303 to achieve an output signal, 2x_clk, which has twice the frequency of Clk_in. The complimentary side is a duplicate of the in- phase side, driven with the complimentary Clk_inb signal, from which the phase delay circuit 305 generates Clk_outb and Clk_dly_outb, and which go to XOR gate 307 to output a complimentary 2x_clkb signal. [0078] FIG. 4 is a timing diagram for the common implementation of a frequency doubler as illustrated in FIG.3. In this example, Clk_out is the inverse of Clk_in and Clk_dly_out is delayed by half a cycle relative to the (undelayed) output clock. The XORing of Clk_out and Clk_dly_out then results in the double frequency clock signal at bottom. For clarity, the complementary side is not shown in FIG 4. [0079] In systems which require the frequency doubler phase delay to be calibrated, the question arises as to how best to determine the point at which the phase delay network has been adjusted to its optimum setting. Direct measurement of the frequency and duty cycle at the frequency doubler output, say on an oscilloscope, may not be possible or practical. The following presents techniques for a relatively simple way to determine the optimal adjustment point for a given system. This method is simple enough that it has can be contained on an integrated circuit and then driven by a state machine that can also contained on the same integrated circuit. The method is also fast enough to allow recalibration during blanking periods while in a cellular phone call to compensate for drift due to temperature or power supply voltage. [0080] In particular, the following presents embodiment for a frequency doubler circuit that can quickly and simply calibrate the phase delay required for a differential 50% output duty cycle frequency doubler in a manner that is low in cost and current drain. This method can help to ensure that the optimal setting for best duty cycle and differential phase error is chosen. [0081] FIG. 5 is a high level block diagram of one embodiment for a differential frequency doubler. The positive and negative components of a differential clock signal, Clk_in and its complement, Clk_inb, are input into a phase delay circuit 501. The phase delay circuit 501 outputs four signals: Clk_out is a buffered version of Clk_in with an arbitrary phase delay relative to Clk_in; Clk_outb is a buffered version of Clk_inb, with the same phase delay as Clk_out so that Clk_outb is still the complement of Clk_out; Clk_dly_out is a buffered version of Clk_in which has a nominal phase delay compared to Clk_out of 90 degrees; and Clk_dly_outb is a buffered version of Clk_inb which has a nominal phase delay compared to Clk_outb of 90 degrees. Consequently, note that Clk_out and Clk_outb are complimentary, differential signals and Clk_dly_out and Clk_dly_outb are complimentary, differential signals. [0082] Each of the outputs of the phase delay circuit 501 are inputs to a differential input Exclusive NOR (XNOR) logic gate 551 to produce the output signal, 2x_clk, which has twice the frequency of the Clk_in signal. Each of the outputs of the phase delay circuit 501 are also inputs to a differential input Exclusive OR (XOR) logic gate 553 to produce the output signal, 2x_clkb, which has twice the frequency of the Clk_inb signal and is the complement of 2x_clk. The control, or Detection & Search, circuit 541 takes the 2x_clk and 2x_clkb signals as inputs and outputs one or more control signals that adjusts the phase delay in the proper direction, resulting in 90 degree phase shift and 50% duty cycle for both 2x_clk and 2x_clkb. [0083] Unlike the frequency doubler of FIG.3, in which each of the two components 2x_clk and 2x_clkb of double frequency signal are derived only from Clk_in or Clk_inb, respectively, FIG.5 presents a fully differential approach. The logic circuitry of each of gates 551 and 553 uses both components of the output clock signal and the delayed output clock signal to respectively generate 2x_clk and 2x_clkb. The inputs to the Detection & Search control circuit 541 are also outputs of the differential logic circuit. [0084] FIG.6 is a diagram of one embodiment of the differential input XOR 553 and XNOR 551 gates of FIG. 5. There are various ways that these gates could be implemented. Here they are implemented using a pair of standard two input NAND logic gates which then feeds a final NAND gate where the 2x_clk or 2x_clkb signal is output. For example, if a, ax and b, bx are a pair of differential inputs into the differential input exclusive OR gate 653, a first NAND gate NAND0631 receives ax and b as inputs and second NAND gate NAND1633 receives a and bx as inputs. The outputs of NAND0631 and NAND 633 then serve as inputs to the NAND gate 635 to provide the final output of the differential input XOR gate 653. Relative to FIG. 5, differential input XOR gate 653 can correspond to differential input XOR gate 553 and the inputs a, ax, b, and bx respectively correspond to Clk_out, Clk_outb, Clk_dly_out, and Clk_dly_outb. [0085] Again using a, ax and b, bx as a pair of differential inputs, the embodiment of a differential input exclusive NOR gate 651 includes a first NAND gate NAND0611 that receives a and b as inputs and second NAND gate NAND1613 that receives ax and bx as inputs. The outputs of NAND0611 and NAND 613 then serve as inputs to the NAND gate 615 to provide the final output of the differential input XNOR gate 651. Relative to FIG.5, differential input XOR gate 651 can correspond to differential input XNOR gate 551 and the inputs a, ax, b, and bx respectively correspond to Clk_out, Clk_outb, Clk_dly_out, and Clk_dly_outb. [0086] In using the logic arrangement of FIG.6 for differential XOR gate 553 and XNOR gate 551, the Clk_out, Clk_outb, Clk_dly_out, Clk_dly_outb connections to the first set of NAND gates (631/611 and 633/613) is done such that there is equal loading on Clk_out/Clk_outb and Clk_dly_out/Clk_dly_outb. This is an important consideration so that the positive negative components of the differential/complementary signals remain balanced. This is especially advantageous for high frequency systems. The differential frequency doubler can be implemented in silicon and can run with a nominal output frequency of 15GHz. Note that the only difference between the differential input XOR gate 653 and XNOR gate 651 in the embodiment of FIG.6 is that the input signals of a and ax are flipped. [0087] FIG.7 shows one embodiment of the second NAND gate whose inputs are labeled NAND0 and NAND1 in FIG. 6 (i.e., 635 or 615). In FIG. 7, the inputs are labelled a and b and the output is labelled z. There are two pull down branches in this circuit and the connections are swapped between them. This maintains the differential balance throughout the XNOR/XOR path. More specifically, in a first branch a PMOS 701 is connected between the supply level and the output node and has its control gate connected to receive the b input. The first branch also includes a pair of series connected NMOS switches 703 and 705 that are series connected between the output node and ground and have respective control gate signals a and b. The second branch is structured similarly, but with the a and b inputs swapped, so that PMOS 711 now has a as its input and NMOSs 713 and 715 respectively have input b and a. [0088] FIG.8 is a timing diagram that corresponds to the signals of the differential frequency doubler embodiments. As presented in FIG. 8, the top six rows are the positive side differential signals, followed by their complementary negative side complements, where these can be described with respect to the embodiment of FIG. 5. Clk_in and Clk_inb are the complementary input signals for the phase delay circuit 501. In this embodiment, Clk_out is the complement of Clk_in. Clk_dly_out is a version of Clk_out that has a phase delay of 90 degrees. The frequency doubled output 2x_clk is the signal created by the XNOR 551 from Clk_out and Clk_dly_out, along with their respect complements Clk_outb and Clk_dly_outb. The XNOR/NAND0 and XNOR/NAND1 signals are the intermediate outputs of the first set of NAND gates (611 and 613) in the XNOR gate embodiment of FIG.6. [0089] On the complementary signals, Clk_dly_outb is a version of Clk_outb that has a phase delay of 90 degrees introduced by the phase delay circuit 501. The compliment frequency doubled output 2x_clkb is the signal created by the XOR 553 from Clk_outb and Clk_dly_outb, along with their respect complements Clk_out and Clk_dly_out. 2x_clk and 2x_clkb are the complementary output signals at two times the frequency of Clk_in. The XOR/NAND0 and XOR/NAND1 signals are the outputs of the first set of NAND gates (631 and 633) in the XOR gate embodiment of FIG.6. [0090] FIG. 9 is a block diagram of the 50% duty cycle differential frequency doubler showing more detail of an embodiment of the phase delay circuit 501 of FIG. 5. The logic circuitry of XNOR 951 and XOR 953 and the control block 941 can be as the corresponding elements 551, 553, and 541 in FIG. 5 and their more detailed descriptions as discussed with respect to the others of the figures. In the embodiment of FIG.9, Clk_out and Clk_outb are respectively generated from Clk_in by inverter 903 and from Clk_inb by inverter 923. The phase delay in each can be accomplished by passing the input clock signals through segmented inverters, where a variable number of inverter segments can be turned on to change the drive strength. To generate Clk_dly_out in the Clk_in path, the variable inverters 911 and 915 are connected in series with the inverter 905 and each have a variable capacitance 913 and 917 connected between their respective outputs and ground. To generate Clk_dly_outb in the Clk_inb path, the variable inverters 931 and 935 are connected in series with the inverter 925 and each have a variable capacitance 933 and 937 connected between their respective outputs and ground. [0091] FIG. 10 is an embodiment for a segmented inverter structure 1011 where segments can be switched in parallel to increase the drive strength. In this example three segments controlled by the enable signal pairs en<0>/enb<0>, en<1>/enb<1>, and en<2>/enb<2>. Each segment includes an inverter pair of PMOS 1071/1081/1091 and NMOS 1073/1083/1093 connected to receive the input signal IN. Each NMOS 1073/1083/1093 is connected between the output node OUT and ground through an NMOS 1077/1087/1097 having a gate connected to the corresponding enable signal en<0>/en<1>/en<2>. On the supply side, PMOS 1071/1081/1091 is connected between OUT and the supply level through a PMOS 1075/1085/1095 having a gate connected to the corresponding inverse enable signal enb<0>/enb<1>/enb<2>. By asserting/de-asserting the enable signals, a selected number of the segments can be switched in or out. Each of the segmented inverters drive a bank of capacitors that can be switched in or out to vary the amount of capacitance. [0092] FIGs. 11 and 12 show capacitor banks being driven in “thermometer” and binary fashion, respectively, where three capacitors are shown, although other numbers can be used. In the “thermometer” embodiment of FIG.11, each capacitors 1102/1104/1106 have the same capacitance (1x) and can be selected by turning on a corresponding NMOS switch 1112/1114/1116 by the respective control signal ctrl<0>/ctrl<1>/ctrl<2>. In the binary embodiment of FIG. 12, the capacitors 1202/1204/1206 have capacitances that increase by a factor of 2 (1x, 2x, 4x, …) and can be selected by turning on a corresponding NMOS switch 1212/1214/1216 by the respective control signal ctrl<0>/ctrl<1>/ctrl<2> to select the combination of capacitances determined by the control circuitry. As the segmented inverter drive strength decreases and the amount of capacitance in the capacitor back increases, the propagation delay increases. The objective is then to change the inverter and capacitor settings until the total phase delay between Clk_out and Clk_dly_out is 90 degrees and similarly between Clk_outb and Clk_dly_outb. In the described embodiments of FIGs. 11 and 12, the capacitors are connected in parallel. Accordingly, the selection of a capacitor causes the total capacitance to increase as a sum when two or more capacitors are coupled in parallel. [0093] Since the embodiments for frequency doubler circuit presented here are intended to be usable over a wide range of frequencies with a high degree of accuracy for the 50% duty cycle of the output, they can be calibrated depending on the input frequency. Also, it may be required to recalibrate the phase delay due to temperature and power supply voltage drift, depending on the degree of 50% duty cycle accuracy that is required. FIG. 13 is a block diagram of the 50% Duty Cycle Differential Frequency Doubler of FIG. 5 showing more detail of the control circuitry of the detection and search block. [0094] Some way of measuring the propagation delay between Clk_out and Clk_dly_out is required in order to determine the proper setting of the segmented inverters and capacitor banks. An oscilloscope could be used if the Clk_out and Clk_dly_out signals where available for direct measurement. But in an application, such as an integrated circuit, clock signals may not be available to be measured by lab equipment. Also, in a mobile application or where automatic operation is required, such laboratory equipment is not practical. To solve this, a method of measuring the phase delay and adjusting the inverter and capacitor can be contained on the same integrated circuit as the differential frequency doubler. [0095] FIG.13 is a block diagram of a frequency doubler circuit, similar to FIG.9, but with more detail for an embodiment of a control circuit 1341. The other elements of FIG.13 can be as in FIG.9 and are similarly numbered (i.e., XNOR 951 of FIG.9 corresponds to XNOR 1351 of FIG. 13). In the embodiment of FIG. 13, a detector 1342 samples the outputs 2x_clk and 2x_clkb and output the average value of the signals using a resistor and capacitor pair. The detector of FIG. 13 includes a first resistor 1348, connected to receive 2x_clk and a first capacitor 1346 connected between the ground and the other side of resistor 1348, and a second resistor 1344, connected to receive 2x_clkb and a second capacitor 1342 connected between the ground and the other side of resistor 1344. The outputs of the two resistor/capacitor pairs 1344/1342 and 1348/1346 are then compared to each other using a single differential comparator 1345. The result of the XNOR/XOR gates 1351/1353, each using all four outputs of the differential phase delay circuit, is that as the phase delays of the Clk_out and Clk_outb paths are increased together, the 2x_clk duty cycle will decrease and the 2x_clkb duty cycle will increase. The opposite is also true, when the phase delays of the Clk_out and Clk_outb paths are decrease together, the 2x_clk duty cycle will increase and the 2x_clkb duty cycle will decrease. Therefore, a solution is determined for inverter and capacitor settings that results in 90 phase delay in the Clk_out/Clk_outb paths and equal duty cycles at the 2x_clk/2x_clkb output. In practice, the design contains overlaps in the transfer function expressed as phase delay vs. control so that a solution can always be found within the state machine 1343. [0096] A search routine can be integrated together with the rest of the circuitry as a state machine 1343 that implements a desired search algorithm. When observing the outputs of the detectors, the average value of the 2x_clk signal will be higher or lower than the average value of the 2x_clkb signal indicating that the duty cycle of the 2x_clk signal is higher or lower than duty cycle of the 2x_clkb signal. The comparator 1345 can output a logic 1 or 0 depending on which average value is higher. The state machine 1343 can then use this single bit input to decide how to progress through the search algorithm. A basic binary or thermometer search can be used for each of the adjustable component in the phase delay circuit. In one embodiment, first all inverter segments are adjusted together using a binary search and provide a coarse step in phase delay. The capacitors are divided into coarse and fine units. All capacitor coarse units are adjusted second using another binary search. Finally, the fine units can be adjusted using a thermometer search. Once these three search steps are completed, the resulting state machine 1343 output control word yields optimized settings for achieving 50% duty cycle at the 2x_clk/2x_clkb outputs. [0097] In some embodiments, a state machine portion can be implemented outside the frequency doubler’s integrated circuit or be part of a processor that communicates with the frequency doubler IC. [0098] Once the calibration is finished, it is possible that the temperature can drift in such a way that the calibration result no longer yields the best possible phase delay. To mitigate this and reduce the number of calibrations needed over temperature, a process/temperature dependent voltage supply can be used. The delay through the segmented inverters in the phase delay circuit is a function of temperature. The temperature dependent voltage supply changes in such a way that the delay variation over temperature for the segmented inverters is significantly reduced. [0099] In some embodiments, a windowed comparator could also be used where the same average values are being compared but the comparator determines if the differences are within a specified range of each other or not. This way the phase delay settings are adjusted until the average falls within the specified range which then corresponds to a duty cycle of the doubled frequency that is within an acceptable range around 50%. Also, this has the advantage of constantly monitoring if, due to temperature or power supply voltage drift, the duty cycle has drifted far enough away from 50% to require a re-adjustment of the phase delay settings. [00100] FIG.14 is a flowchart of one embodiment for an embodiment of a method of operating the frequency doubler circuitry of embodiments presented here. Starting at 1401, a differential input clock signal is received. Referring back FIG. 5, for example, this will correspond to the positive and negative components Clk_in and Clk_inb being received by the phase delay circuit 501. The phase delay circuit generates the components Clk_out and Clk_outb of the differential output clock from the differential input clock signal at 1403. For example, referring to the detail in the embodiment of FIG.9, the positive and negative components of the output clock signal are respectively generated from the differential input clock signal by the inverters 903 and 923. [00101] The components of the differential delayed output clock signal are generated at 1405. Referring again to the embodiment of FIG. 9, the positive component of Clk_dly_out is generated by the string of inverters 911, 915, 905 and capacitors 913, 917, where the amount of delay is in response to the one or more control signals provided by the control circuit 941 to the segmented inverters 911, 915 and the variable capacitance capacitors 913, 917 to tune the circuit to optimize its operation. Similarly, on the negative side, Clk_dly_outb is generated by the string of inverters 931, 935, 925 and capacitors 933, 937, where the amount of delay is in response to the one or more control signals provided by the control circuit 941 to the segmented inverters 931, 935 and the variable capacitance capacitors 933, 937. [00102] 1407 and 1409 generate the double frequency output clock signals from the differential output signal Clk_out, Clk_outb and differential delayed output signal Clk_dly_out, Clk_dly_outb by the logic circuitry of the differential XNOR and XOR gates. Referring again to FIG.9, at 1407 the component 2x_clk is generated by the logical combination of these signals by the differential XNOR 951, where FIGs.6 and 7 provide one embodiment for generating this logical combination. At 1409 the component 2x_clkb is generated by the logical combination of these signals by the differential XOR 953, where FIGs.6 and 7 provide one embodiment for generating this logical combination. [00103] The one or more control signals for adjusting the delay values are generated at 1411 from outputs of one or both of the logical combinations of the differential output signal Clk_out, Clk_outb and differential delayed output signal Clk_dly_out, Clk_dly_outb. For example, looking at the embodiment of FIG.13, the control circuitry 1341 of detector 1342, comparator 1345, and state machine 1343 generated the one or more control signals from the 2x_clk and 2x_clkb outputs of logic gates 1351 and 1353, so that the circuit can be tuned to optimize its operation through the control signals. In embodiments presented below (see FIGs.17 and 18), the control signals can alternately or additionally be determined based on intermediate values generated within the XNOR and/or XOR gates. [00104] Returning to FIG.2, this illustrates the incorporation of a local oscillator LO 105 into a transmitter 101 and the incorporation of a local oscillator LO 107 into a receiver 102. The embodiments for presented here for a frequency doubler circuit can be used as part of the local oscillator LO 105 or LO 107. FIGs.15 and 16 illustrate the incorporation of a frequency doubler into a local oscillator such as LO 105 or LO 107. [00105] FIGs. 15 and 16 respectively illustrate the incorporation of a frequency doubler into the transmit path and the receive path of a wireless terminal, such as a cellular phone. Looking that the transmit path of FIG. 15, the RF output signal is generated by receiving a baseband output signal and mixing it in mixer 1503 with the local oscillator signal. Depending on the architecture of the transmitter, the clock signal could have various number of phases. For example, it could be a two-phase differential clock signal, a four-phase differential quadrature clock signal, a 6-phase clock signal, or other number of phases. The example of FIG.15 illustrates a 6-phase (6Φ) clock signal being supplied by way of a capacitor 1517. [00106] To provide the clock signal for the mixer 1503, an initial clock signal can be provided from a transmitter path digitally controlled oscillator Tx DCO 1505 across a capacitor 1511 through an inverter 1513 to a block /n 1507. Block /n 1507 converts a single sided input clock Clk_in into a differential clock signal Clk_in, Clk_inb that passes through the inverter 1515 to provide the differential input clock for the frequency doubler circuit x21501. The frequency doubler circuit x21501 can be as presented in the embodiments described above, or those presented below with respect to FIG.17 or 18. If the transmitter architecture requires a LO clock signal of other than two phases, the double frequency clock signal can then be converted to a double frequency clock signal of the appropriate phase. In the example of FIG. 15, the block /31509 converts the 2-phase, double frequency clock signal 2x_clk, 2x_clkb into a 6-phase, double frequency clock signal 6Φ. [00107] The receiver path of FIG.16 is configured to receive an RF input signal at a mixer 1603, where it is mixed down using the local oscillator clock signal to provide the baseband input signal. With respect to the local oscillator elements of FIG. 16, where these can be as described above with respect to FIG. 15 and are similarly numbered (e.g., Rx DCO is numbered 1605, while Tx DCO is 1505, etc.). [00108] The embodiment of FIGs.15 and 16 include other adjustment mechanisms that can be used to further improve the frequency doubler output duty cycle accuracy. FIGs.15 and 16 illustrate a transmitter and receiver, respectively, local oscillator (LO) path that includes the differential frequency doubler 1501/1601, indicated at x2, which receives a path oscillator signal from a digitally controller oscillator DCO 1505/1605. In addition to features described above, two other error sources and correction points are also shown in FIGs. 15 and 16. The first is labeled DC Adjust 1523/1623 This circuit provides a DC offset at the input of the first inverter 1513/1613 in the path which can be used to ensure the differential clock signal at the input to frequency doubler 1501/1601 has 50% duty cycle. The second is labeled Phase Adjust 1525/1625. This circuit provides an offset in capacitive loading between the differential inputs of the frequency doubler 1501/1601 which can be used to give the negative side of the frequency doubler input clock signal (Clk_inb) is 180º out of phase with the positive side (Clk_in). A low drop-out regulator LDO 1521/1621 be used as a voltage supply regulator of a voltage VLDO to improve temperature and process independence. [00109] The embodiments presented above have the advantage that they can use minimal circuitry to determine the best phase delay settings for the differential frequency doubler. Using a single comparator (i.e., 1345) saves integrated circuit die area and cost. It also avoids errors involved with doing a comparison to a reference voltage rather than comparing the two average values themselves. The single comparator embodiments can provide a phase delay setting is within one least significant bit of the optimal setting to make the duty cycle as close to 50% as possible and the best output differential phase error. [00110] FIG. 17 illustrates another embodiment for the detection of the differential frequency doubler phase delay. Briefly ignoring the control circuit elements 1741 of FIG. 17, FIG.17 repeats the elements of FIG. 13 and numbers these similarly (e.g., differential XNOR logic circuitry 1351 is now 1751). In the embodiment of FIG.17, the intermediate logic NAND0 and NAND1 are also provided from the differential XNOR gate 1751, where the signal can be as shown from the NAND0611 and NAND1613 in FIG. 6. More specifically, NAND0 is (Clk_out NAND Clk_dly_out) and NAND1 is (Clk_outb NAND Clk_dly_outb). [00111] The control circuit elements 1741 of differ from the embodiment FIG.14 in that now the inputs to the detector 1742 are the logical combinations of NAND0 and NAND1. On the other side of detector 1742, NAND0 and NAND1 are respective first inputs to the comparators 1745 and 1747, which each receive a second input of a reference voltage level Vref. The state machine then receives the outputs of the pair of comparators 1745, 1747, from which it then determines the set of control signals to establish the delays. The embodiment of FIG. 17 uses two comparators in order to determine independent phase delay adjustments between the Clk_out path and the Clk_outb path. This approach has an advantage in that when there is a mismatch between the segmented inverters or capacitor banks in the phase delay circuit, each side can be adjusted independently because XNOR/NAND0 is only dependent on the signals Clk_out and Clk_dly_out and XNOR/NAND1 is only dependent on the signals Clk_outb and Clk_dly_outb. In this case, the phase delay is adjusted to make the NAND0 and NAND1 signals have nominal 75% duty cycles. This is done by setting Vref equal to the voltage that corresponds to the average value of the 75% duty NAND0/NAND1 signals. The embodiment of FIG. 17 has an advantage in a circuit which has mismatch between the Clk and Clkb sides of the phase delay circuit, as this embodiment allows for individual settings for each side. [00112] FIG.18 illustrates an embodiment that combines control circuitry features of the embodiments of FIGs.13 and 17. Aside from the control circuitry 1841, FIG.18 repeats the elements of FIGs.13 and 17 and numbers these similarly (e.g., differential XNOR logic circuitry 1351/1751 is now 1851). Within the control circuitry 1841, the embodiment of FIG. 18 includes the elements of both FIG. 13 and FIG. 17, with the detector having as inputs 2x_clk and 2x_clkb, as in FIG.13, and NAND0 and NAND1, as in FIG.17. The features from the embodiment of FIG.17 determines what offset in phase delay settings are required due to the mismatch between Clk_out and Clk_outb sides, then also using features of the embodiment of FIG.17 to adjust both sides equally while keeping the same offset between the Clk_out and Clk_outb sides. [00113] More specifically, 2x_clk is connected to a first input of a comparator 1893 through a resistor 1883, with a capacitor 1884 connected between ground and a node between the resistor 1883 and the first input of the comparator 1893. 2x_clkb is connected to a second input of comparator 1893 through a resistor 1885, with a capacitor 1886 connected between ground and a node between the resistor 1885 and the second input of the comparator 1893. The comparator 1893 consequently compares 2x_clk and 2x_clkb, as described above for comparator 1345 of FIG. 13, and provides its output to the state machine 1843. [00114] NAND0 is connected to a first input of a comparator 1891 through a resistor 1881, with a capacitor 1882 connected between ground and a node between the resistor 1881 and the first input of the comparator 1891. NAND1 is connected to a first input of a comparator 1895 through a resistor 1887, with a capacitor 1888 connected between ground and a node between the resistor 1887 and the first input of the comparator 1895. A second input of each of comparators 1891 and 1895 are connected to Vref and comparators 1891 and 1895 can operate as described above with respect to comparators 1745 and 1747 of FIG.17. The outputs of comparators 1891 and 1895 go to the state machine 1843, which can generate the control signals for setting the delays based on a combinations of the outputs of the comparators 1891, 1893, and 1895. [00115] While the embodiment of FIG.18 requires one more comparator compared to the embodiment of FIG. 17, it allows the benefits of both the embodiments FIG. 5 and FIG.17. In systems that have mismatch between the Clk_out and Clk_outb sides, adjusting each side independently, as in the embodiment FIG. 17, can compensate for the mismatch. Then the phase delay can be adjusted again looking at the comparison of the average values of 2x_clk and 2x_clkb, as in the embodiment of FIG. 5, while keeping the same offset in phase delay settings that was determined in the first step. This has the advantage of knowing that the optimal phase delay setting has been reached while compensating for mismatch. [00116] Relative to the prior art, the embodiments presented here include the combination of the way the XOR and XNOR gates are designed and the adjustment of the phase delay is determined. Phase delay adjustment is done by either comparing the difference between the average values of the 2x_clk and 2x_clkb output or comparing the XNOR/NAND0 and XNOR/NAND1 to a reference voltage corresponding to 75% duty cycle or the combination of the two. Although described in the context of a cellular phone transceiver, it could easily be used anywhere one needed to double the frequency of an input signal and maintain an accurate 50% duty cycle and low output differential phase error. This could be in a microprocessor or other logic circuits or other types of radio frequency circuits. [00117] The technology described herein can be implemented using hardware, firmware, software, or a combination of these. The software or firmware used can be stored on one or more processor readable storage devices to program one or more of the blocks of FIGs. 5-18 to perform the functions described herein. The processor readable storage devices can include computer readable media such as volatile and non-volatile media, removable and non-removable media. By way of example, and not limitation, computer readable media may comprise computer readable storage media and communication media. Computer readable storage media may be implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Examples of computer readable storage media include RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information, and which can be accessed by the components described above. A computer readable medium or media does (do) not include propagated, modulated, or transitory signals. [00118] Communication media typically embodies computer readable instructions, data structures, program modules or other data in a propagated, modulated, or transitory data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term “modulated data signal” means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as RF and other wireless media. Combinations of any of the above are also included within the scope of computer readable media. [00119] In alternative embodiments, some or all of the software or firmware can be replaced by dedicated hardware logic components. For example, and without limitation, illustrative types of hardware logic components that can be used include Field-programmable Gate Arrays (FPGAs), Application-specific Integrated Circuits (ASICs), Application-specific Standard Products (ASSPs), System-on-a-chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), special purpose computers, etc. In one embodiment, software (stored on a storage device) implementing one or more embodiments is used to program one or more processors. The one or more processors can be in communication with one or more computer readable media/ storage devices, peripherals and/or communication interfaces. [00120] It is understood that the present subject matter may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this subject matter will be thorough and complete and will fully convey the disclosure to those skilled in the art. Indeed, the subject matter is intended to cover alternatives, modifications, and equivalents of these embodiments, which are included within the scope and spirit of the subject matter as defined by the appended claims. Furthermore, in the following detailed description of the present subject matter, numerous specific details are set forth in order to provide a thorough understanding of the present subject matter. However, it will be clear to those of ordinary skill in the art that the present subject matter may be practiced without such specific details. [00121] Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatuses (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable instruction execution apparatus, create a mechanism for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. [00122] The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The aspects of the disclosure herein were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure with various modifications as are suited to the particular use contemplated. [00123] For purposes of this document, each process associated with the disclosed technology may be performed continuously and by one or more computing devices. Each step in a process may be performed by the same or different computing devices as those used in other steps, and each step need not necessarily be performed by a single computing device. [00124] Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

CLAIMS What is claimed is: 1. A frequency doubler circuit, comprising: a phase delay circuit configured to: receive a differential input clock signal; receive one or more control signals; generate a differential output clock signal from the differential input clock signal; and generate a differential delayed output clock signal from the differential input clock signal by delaying the differential output clock signal in response to the one or more control signals; logic circuitry configured to receive the differential output clock signal and the differential delayed output clock signal and generate as output a double-frequency differential clock signal from the differential output clock signal and the differential delayed output clock signal; and a control circuit configured to receive one or more outputs of the logic circuitry and generate therefrom the one or more control signals.

2. The frequency doubler circuit of claim 1, wherein the control circuit comprises: one or more comparators each configured to receive one or more outputs of the logic circuitry a generate corresponding comparator output; and a state machine configured to receive the corresponding output of the one or more comparators and generate therefrom the one or more control signals.

3. The frequency doubler circuit of claim 2, wherein the control circuit further comprises: a detector circuit, including for each of the one or more of the outputs of the logic circuitry, a corresponding resistor through which the output of the logic circuit is supplied to a corresponding input of one of the comparators and a capacitor connected between the corresponding input and ground.

4. The frequency doubler circuit of any of claims 2-3, wherein the one or more comparators includes a first comparator configured to receive a first component of the double-frequency differential clock signal at a first input and a second component of the double-frequency differential clock signal at a second input.

5. The frequency doubler circuit of any of claims 2-4, wherein the differential output clock signal includes a positive component and a negative component and the differential delayed output clock signal includes a positive component and a negative component, wherein the logic circuitry includes: a first NAND gate configured to receive as inputs the negative component of the differential output clock signal and the positive component of the differential delayed output clock signal; and a second NAND gate configured to receive as inputs the positive component of the differential output clock signal and the negative component of the differential delayed output clock signal, and wherein the one or more comparators includes: a first comparator configured to receive an output of the first NAND gate and a reference voltage; and a second comparator configured to receive an output of the second NAND gate and the reference voltage.

6. The frequency doubler circuit of any of claims 1-5, wherein the logic circuitry includes: a differential input exclusive NOR gate configured to receive the differential output clock signal and the differential delayed output clock signal and provide a positive component of the double-frequency differential clock signal; and a differential input exclusive OR gate configured to receive the differential output clock signal and the differential delayed output clock signal and provide a negative component of the double-frequency differential clock signal.

7. The frequency doubler circuit of any of claims 1-6, wherein the differential input clock signal includes a positive component and a negative component, the differential output clock signal includes a positive component and a negative component, and the differential delayed output clock signal includes a positive component and a negative component, wherein the phase delay circuit includes: a first variable delay circuit configure to receive the positive component of the differential input clock signal and generate the positive component of the differential output clock having phase delay dependent on a first subset of the one or more control signals; and a second variable delay circuit configure to receive the negative component of the differential input clock signal and generate the negative component of the differential output clock having phase delay dependent on a second subset of the one or more control signals, the second subset of the one or more control signals being distinct from the first subset of the one or more control signals.

8. The frequency doubler circuit of claim 7, wherein each of first and second variable delay circuits include: a plurality of series connected inverters, one or more of which are of variable gain inverters, the gain of each of the variable gain inverters adjustable in response to one of the corresponding subset of the one or more control signals; and one or more variable capacitances each connected between an output of a corresponding one of the variable gain inverters, the capacitance of each of the variable capacitances adjustable in response to one of the corresponding subset of the one or more control signals.

9. The frequency doubler circuit of any of claims 1-8, wherein the control circuit is further configured to generate the one or more control signals such that a duty cycle of the double-frequency differential clock signal is 50%.

10. The frequency doubler circuit of any of claims 1-9, wherein the phase delay circuit includes: a first invertor configured to receive a positive component of the differential input clock signal and generate therefrom a positive component of the differential output clock signal; and a second invertor configured to receive a negative component of the differential input clock signal and generate therefrom a negative component of the differential output clock signal.

11. The frequency doubler circuit of any of claims 1-10, wherein the differential delayed output clock signal includes a positive component and a negative component, the differential input clock signal includes a positive component and a negative component and the phase delay circuit is further configured to generate the differential delayed output clock signal from the differential input clock signal by independently delaying the positive and negative components of the differential output clock signal in response to the one or more control signals.

12. The frequency doubler circuit of any of claims 1-11, wherein the phase delay circuit, logic circuitry, and control circuit are formed on a single integrated circuit.

13. The frequency doubler circuit of any of claims 1-12, where the control circuit is configured to tune the one or more control signals to optimize the frequency doubler circuit’s operation.

14. A method of generating a double-frequency differential clock signal, comprising: receiving a differential input clock signal having a positive component and a negative component; generating a differential output clock signal having a positive component and a negative component from the components of the differential input clock signal; generating a differential delayed output clock signal having a positive component and a negative component by delaying the components of the differential input clock signal in response to one or more control signals; generating a positive component for the double-frequency differential clock signal by a first logical combination of the components of differential output clock signal and the differential delayed output clock signal; generating a negative component for the double-frequency differential clock signal by a second logical combination of the components of differential output clock signal and the differential delayed output clock signal; and determining the one or more control signals from a plurality of outputs from one or both of the first logical combination and the second logical combination.

15. The method of claim 14, wherein generating the differential delayed output clock includes independently delaying the positive and negative components of the differential output clock signal in response to the one or more control signals.

16. The method of any of claims 14-15, wherein the one or more control signals are determined such that a duty cycle of the double-frequency differential clock signal is 50%.

17. The method of any of claims 14-16, wherein determining the one or more control signals includes comparing the positive component for the double-frequency differential clock signal with the negative component for the double-frequency differential clock signal.

18. The method of any of claims 14-17, wherein determining the one or more control signals includes: comparing a logical NAND of the negative component of the differential output clock signal and the positive component of the differential delayed output clock signal with a reference voltage; and comparing a logical NAND of the positive component of the differential output clock signal and the negative component of the differential delayed output clock with a reference voltage.

19. The method of any of claims 14-18, wherein first logical combination is a differential input exclusive OR and the second logical combination is a differential input exclusive NOR.

20. The method of any of claims 14-19, wherein determining the one or more control signals includes tuning the one or more control signals to optimize the frequency doubler circuit’s operation.

21. A transceiver, comprising: a local oscillator circuit, comprising: a digitally controlled oscillator configured to generate a first clock signal of a first frequency; and a frequency doubler configured to receive a differential form of the first clock signal and generate therefrom a differential double-frequency clock signal, the frequency doubler including: a phase delay circuit configured to receive the differential form of the first clock signal and one or more control signals and generate therefrom a differential output clock signal and a differential delayed output clock signal by delaying the differential form of the first clock signal in response to the one or more control signals; logic circuitry configured to receive the differential output clock signal and the differential delayed output clock signal and generate the differential double-frequency clock signal from the differential output clock signal and the differential delayed output clock signal; and a control circuit configured to receive one or more outputs of the logic circuitry and generate therefrom the one or more control signals; and a mixer configured to receive and mix the differential double-frequency clock signal with an input signal to generate an output signal.

22. The transceiver of claim 21, wherein the local oscillator circuit and mixer are part of a transmitter path, the input signal is a baseband input signal and the output signal is a radio frequency (RF) output signal.

23. The transceiver any of of claims 21-22, wherein the local oscillator circuit and mixer are part of a receiver path, the input signal is a radio frequency (RF) input signal and the output signal is a baseband output signal.

24. The transceiver of any of of claims 21-23, wherein the control circuit comprises: one or more comparators each configured to receive one or more outputs of the logic circuitry and generate a corresponding comparator output; and a state machine configured to receive the corresponding output of the one or more comparators and generate therefrom the one or more control signals.

25. The transceiver of claim 24, wherein the control circuit further comprises: a detector circuit, including for each of the one or more of the outputs of the logic circuitry, a corresponding resistor through which the output of the logic circuit is supplied to a corresponding input of one of the comparators and a capacitor connected between the corresponding input and ground.

26. The transceiver of any of claims 24-25, wherein the one or more comparators includes a first comparator configured to receive a first component of the differential double-frequency clock signal at a first input and a second component of the differential double-frequency clock signal at a second input.

27. The transceiver of any of claims 24-26, wherein the differential output clock signal includes a positive component and a negative component and the differential delayed output clock signal includes a positive component and a negative component, wherein the logic circuitry includes: a first NAND gate configured to receive as inputs the negative component of the differential output clock signal and the positive component of the differential delayed output clock signal; and a second NAND gate configured to receive as inputs the positive component of the differential output clock signal and the negative component of the differential delayed output clock signal, and wherein the one or more comparators includes: a first comparator configured to receive the output of the first NAND gate and a reference voltage; and a second comparator configured to receive the output of the second NAND gate and the reference voltage.

28. The transceiver of any of claims 24-27, wherein the logic circuitry includes: a differential input exclusive NOR gate configured to receive the differential output clock signal and the differential delayed output clock signal and provide a positive component of the differential double-frequency clock signal; and a differential input exclusive OR gate configured to receive the differential output clock signal and the differential delayed output clock signal and provide a negative component of the differential double-frequency clock signal.

29. The transceiver any of claims 24-28, wherein the differential form of the first clock signal includes a positive component and a negative component, the differential output clock signal includes a positive component and a negative component, and the differential delayed output clock signal includes a positive component and a negative component, wherein the phase delay circuit includes: a first variable delay circuit configure to receive the positive component of the differential input clock signal and generate the positive component of the differential output clock having phase delay dependent on a first subset of the one or more control signals; and a second variable delay circuit configure to receive the negative component of the differential input clock signal and generate the negative component of the differential output clock having phase delay dependent on a second subset of the one or more control signals, the second subset of the one or more control signals being distinct from the first subset of the one or more control signals.

30. The transceiver of claim 29, wherein each of first and second variable delay circuits include: a plurality of series connected inverters, one or more of which are of variable gain inverters, the gain of each of the variable gain inverters adjustable in response to one of the corresponding subset of the one or more control signals; and one or more variable capacitances each connected between an output of a corresponding one of the variable gain inverters, the capacitance of each of the variable capacitances adjustable in response to one of the corresponding subset of the one or more control signals.

31. The transceiver of any of claims 21-30, wherein the control circuit is further configured to generate the one or more control signals such that a duty cycle of a differential double-frequency clock signal is 50%.

32. The transceiver of any of claims 21-31, wherein the phase delay circuit includes: a first invertor configured to receive a positive component of differential form of the first clock signal and generate therefrom a positive component of the differential output clock signal; and a second invertor configured to receive a negative component of differential form of the first clock signal and generate therefrom a negative component of the differential output clock signal.

33. The transceiver of any of claims 21-32, wherein the differential delayed output clock signal includes a positive component and a negative component, the differential input clock signal includes a positive component and a negative component and the phase delay circuit is further configured to generate the differential delayed output clock signal from the differential input clock signal by independently delaying the positive and negative components of the differential output clock signal in response to the one or more control signals.

34. The transceiver of any of claims 21-33, wherein the phase delay circuit, logic circuitry, and control circuit are formed on a single integrated circuit.

35. The transceiver of any of claims 21-34, wherein the transceiver is component of a cellular telephone.

36. The transceiver of claim of any of claims 21-35, where the control circuit is configured to tune the one or more control signals to optimize the frequency doubler circuit’s operation.