WO2021057182A1 - Trusted update method and apparatus for fpga logic - Google Patents
Trusted update method and apparatus for fpga logic Download PDFInfo
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- WO2021057182A1 WO2021057182A1 PCT/CN2020/100935 CN2020100935W WO2021057182A1 WO 2021057182 A1 WO2021057182 A1 WO 2021057182A1 CN 2020100935 W CN2020100935 W CN 2020100935W WO 2021057182 A1 WO2021057182 A1 WO 2021057182A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/602—Providing cryptographic facilities or services
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/64—Protecting data integrity, e.g. using checksums, certificates or signatures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
Definitions
- One or more embodiments of this specification relate to the field of blockchain technology, and in particular, to a trusted update method and device for FPGA logic.
- Blockchain technology is built on a transmission network (such as a peer-to-peer network).
- the network nodes in the transmission network use chained data structures to verify and store data, and use distributed node consensus algorithms to generate and update data.
- TEE Trusted Execution Environment
- TEE can play the role of a black box in the hardware. Neither the code executed in the TEE nor the data operating system layer can be peeped, and only the pre-defined interface in the code can operate on it.
- plaintext data is calculated in TEE instead of complex cryptographic operations in homomorphic encryption. There is no loss of efficiency in the calculation process. Therefore, the combination with TEE can achieve less performance loss. Under the premise, the security and privacy of the blockchain are greatly improved. At present, the industry is very concerned about the TEE solution.
- TEE solutions including TPM (Trusted Platform Module) in software and Intel SGX (Software Guard Extensions) in hardware. , Software Protection Extension), ARM Trustzone (trust zone) and AMD PSP (Platform Security Processor, platform security processor).
- one or more embodiments of this specification provide a trusted update method and device for FPGA logic.
- a trusted update method of FPGA logic which includes: the FPGA structure receives an encrypted new version of the circuit logic configuration file from a client, the FPGA structure includes an FPGA chip; The FPGA structure reads the encrypted new version of the circuit logic configuration file into the decryption module on the FPGA chip for decryption, and the decryption module is based on the old version of the circuit logic configuration file deployed on the FPGA structure by the FPGA chip. Formed; the FPGA structure is updated and deployed based on the new version of the circuit logic configuration file obtained by decryption, so that the FPGA structure is implemented as a trusted execution environment on the blockchain node to which it belongs.
- a trusted update device for FPGA logic which includes: a receiving unit that enables the FPGA structure to receive the encrypted new version of the circuit logic configuration file from the client.
- the FPGA structure Contains an FPGA chip; a decryption unit that causes the FPGA structure to read the encrypted new version of the circuit logic configuration file into the decryption module on the FPGA chip for decryption, and the decryption module is based on the FPGA structure by the FPGA chip
- the deployed old version of the circuit logic configuration file is formed; the update unit enables the FPGA structure to be updated and deployed based on the new version of the circuit logic configuration file obtained by decryption, so that the FPGA structure is implemented as a trusted blockchain node. Execution environment.
- an electronic device including: a processor; a memory for storing executable instructions of the processor; wherein the processor runs the executable instructions In order to realize the method as described in the first aspect.
- a computer-readable storage medium on which computer instructions are stored, and when the instructions are executed by a processor, the steps of the method described in the first aspect are implemented.
- Fig. 1 is a flowchart of a trusted update method of FPGA logic provided by an exemplary embodiment.
- Fig. 2 is a schematic structural diagram of a blockchain node provided by an exemplary embodiment.
- Fig. 3 is a schematic diagram of forming a functional module on an FPGA chip provided by an exemplary embodiment.
- Fig. 4 is a schematic diagram of newly updateable FPGA board provided by an exemplary embodiment.
- Fig. 5 is a block diagram of a trusted update device for FPGA logic provided by an exemplary embodiment.
- the steps of the corresponding method are not necessarily executed in the order shown and described in this specification.
- the method may include more or fewer steps than described in this specification.
- a single step described in this specification may be decomposed into multiple steps for description in other embodiments; and multiple steps described in this specification may also be combined into a single step in other embodiments. description.
- Blockchain is generally divided into three types: Public Blockchain, Private Blockchain and Consortium Blockchain.
- the public chain is represented by Bitcoin and Ethereum. Participants who join the public chain can read the data records on the chain, participate in transactions, and compete for the accounting rights of new blocks. Moreover, each participant (ie, node) can freely join and exit the network, and perform related operations.
- the private chain is the opposite.
- the write permission of the network is controlled by an organization or institution, and the data read permission is regulated by the organization.
- the private chain can be a weakly centralized system with strict restrictions and few participating nodes.
- This type of blockchain is more suitable for internal use by specific institutions.
- Consortium chain is a block chain between public chain and private chain, which can realize "partial decentralization".
- Each node in the alliance chain usually has a corresponding entity or organization; participants are authorized to join the network and form a stakeholder alliance to jointly maintain the operation of the blockchain.
- the nodes in the blockchain network may use a solution that combines the blockchain and the TEE (Trusted Execution Environment).
- TEE Trusted Execution Environment
- TEE is a secure extension based on CPU hardware and a trusted execution environment that is completely isolated from the outside.
- TEE was first proposed by Global Platform to solve the security isolation of resources on mobile devices, and parallel to the operating system to provide a trusted and secure execution environment for applications.
- ARM's Trust Zone technology is the first to realize the real commercial TEE technology. With the rapid development of the Internet, security requirements are getting higher and higher. Not only mobile devices, cloud devices, and data centers have put forward more demands on TEE.
- TEE has also been rapidly developed and expanded. Compared with the originally proposed concept, the TEE referred to now is a more generalized TEE.
- server chip manufacturers Intel and AMD have successively introduced hardware-assisted TEE and enriched the concepts and features of TEE, which has been widely recognized in the industry.
- the TEE mentioned now usually refers more to this kind of hardware-assisted TEE technology.
- SGX provides an enclave (also known as an enclave), which is an encrypted trusted execution area in the memory, and the CPU protects data from being stolen.
- enclave also known as an enclave
- the CPU protects data from being stolen.
- a part of the area EPC Enclave Page Cache, enclave page cache or enclave page cache
- the encryption engine MEE Memory Encryption Engine
- the first step in using TEE is to confirm the authenticity of TEE.
- the related technology provides a remote certification mechanism for the above-mentioned SGX technology to prove that the SGX platform on the target device and the challenger have deployed the same configuration file.
- the TEE technology in the related technology is implemented by software or a combination of software and hardware, even if the remote attestation method can indicate to a certain extent that the configuration file deployed in the TEE has not been tampered with, the TEE itself depends on the operation The environment cannot be verified.
- a virtual machine for executing smart contracts needs to be configured in the TEE.
- the instructions executed by the virtual machine are not directly executed, but actually executed corresponding X86 instructions (Assuming that the target device adopts the X86 architecture), which poses a certain degree of security risk.
- this specification proposes a hardware TEE technology based on FPGA implementation.
- FPGA implements hardware TEE by loading circuit logic configuration files. Because the content of the circuit logic configuration file can be checked and verified in advance, and the FPGA is configured and operated completely based on the logic recorded in the circuit logic configuration file, it can be ensured that the hardware TEE implemented by the FPGA has relatively higher security.
- the related technology does not provide a corresponding preventive mechanism to avoid intentionally or unintentionally untrusted update operations for the circuit logic configuration files in the FPGA.
- Fig. 1 is a flowchart of a trusted update method of FPGA logic provided by an exemplary embodiment. As shown in Figure 1, the method is applied to the FPGA structure and may include steps 102-106.
- Step 102 The FPGA structure receives the encrypted new version of the circuit logic configuration file from the client, and the FPGA structure includes the FPGA chip.
- the user can provide the encrypted new version of the circuit logic configuration file to the FPGA structure through the client.
- the user can be an individual or a group (such as an enterprise), and this manual does not limit this.
- the client can remotely send the encrypted new version of the circuit logic configuration file to the FPGA structure; or, the client can be located at the same place as the FPGA structure to realize the transmission of the encrypted new version of the circuit logic configuration file locally or in a local area network.
- the client can directly establish a connection with the FPGA structure, and send the encrypted new version of the circuit logic file directly to the FPGA structure.
- the client can establish a connection with the blockchain node to which the FPGA structure belongs (equivalent to the Host host corresponding to the FPGA structure), and send the encrypted new version of the circuit logic file to the blockchain node. Provided to FPGA structure.
- Step 104 The FPGA structure reads the encrypted new version of the circuit logic configuration file into the decryption module on the FPGA chip for decryption.
- the decryption module is based on the old version of the circuit deployed on the FPGA structure by the FPGA chip. Logical configuration files are formed.
- the FPGA chip contains a number of editable hardware logic units. After these hardware logic units are configured via a circuit logic configuration file, they can be implemented as corresponding functional modules to implement corresponding logic functions. Specifically, the circuit logic configuration file can be burned to the FPGA structure based on the form of a bit stream. For example, the above-mentioned decryption module is formed by the old version of the circuit logic configuration file, and by further deploying and forming functional modules for realizing encryption, virtual machine and other logic, the FPGA structure can be configured as a hardware TEE on a blockchain node.
- the old version of the circuit logic configuration file refers to the pre-deployed circuit logic configuration file on the FPGA structure. Compared with the above-mentioned new version of the circuit logic configuration file, since the time when the old version of the circuit logic configuration file is configured in the FPGA structure is relatively earlier, it is distinguished by "new version” and "old version” instead of indicating the corresponding circuit logic configuration The logic or function implemented by the file must achieve version iteration.
- the new version of the circuit logic configuration file can be encrypted by the client based on the configuration file deployment key to obtain the above-mentioned encrypted new version of the circuit logic configuration file.
- the aforementioned decryption module can decrypt the encrypted new version of the circuit logic configuration file based on the configuration file deployment key to obtain the aforementioned new version of the circuit logic configuration file.
- the configuration file deployment key can be generated in advance and then deployed on the client and FPGA structure respectively.
- the configuration file deployment key can be obtained through remote negotiation between the client and the blockchain node, and then the blockchain node transmits the negotiated configuration file deployment key to the FPGA structure, which is maintained by the FPGA structure; Higher security requirements, to prevent the configuration file deployment key from being obtained by the blockchain node, and the FPGA structure can directly negotiate with the client remotely.
- the remote negotiation process can use SM2 or other algorithms, which is not limited in this manual.
- the client and the FPGA structure need to implement at least one information exchange during the negotiation process. For example, the client can generate a key Ka-1 locally, the FPGA structure can generate a key Kb-1 locally, and the client can be based on the secret key.
- the key Ka-1 is calculated to obtain the key agreement information Ka-2
- the FPGA structure can be calculated based on the key Kb-1 to obtain the key agreement information Kb-2
- the client sends the key agreement information Ka-2 to the FPGA structure
- FPGA The structure sends the key agreement information Kb-2 to the client, so that the client can generate a secret value (or master key) based on the key Ka-1 and the key agreement information Kb-2
- the FPGA structure can be based on The key Kb-1 and the key agreement information Ka-2 generate the same secret value.
- the above-mentioned configuration file deployment key can be the secret value; or, the configuration file deployment key can be derived from the above-mentioned secret value by the client and FPGA structure respectively through the Key Derivation Function (KDF) .
- KDF Key Derivation Function
- An authentication root key may be pre-deployed on the FPGA structure, and the authentication root key may be preset in the FPGA structure, or the authentication root key may be deployed into the FPGA structure by the client or other objects in an offline security environment.
- the authentication root key is an asymmetric key. Then, in the process of remotely negotiating the above configuration file deployment key between the client and the FPGA structure, the FPGA structure can use the authentication root key to sign the information sent by itself (such as the above key agreement information Kb-2, etc.). The client can verify the signature to determine whether the received information actually comes from the FPGA structure and has not been tampered with during transmission, and the information that has not passed the signature verification will not be trusted and adopted by the client.
- the public key of the authentication root key can be managed by the authentication server and not made public, then the client can send the received information to the authentication server, and the authentication server can perform signature verification with the maintained public key; then, the authentication The server can provide the client with the verification result, the verification result is signed by the verification server, and the verification result contains the certificate of the verification server or the public key of the verification server can be made public, so that the client can verify the signature to determine the validity of the verification result Sex.
- the public key of the authentication root key can be made public, so that the client can perform signature verification on the information from the FPGA structure based on the public key without going through the authentication server, which can reduce the interactive links in the signature verification process. Thereby improving the efficiency of verification and reducing the security risks caused by more interactive links.
- the above authentication root key can be deployed to the FPGA structure based on the old version of the circuit logic configuration file. Then, especially when the old version of the circuit logic configuration file and the new version of the circuit logic configuration file are not generated and deployed by the same user, the old version of the circuit logic configuration file may be viewed or verified by other users before burning to the FPGA structure, resulting in the old version of the circuit logic
- the authentication root key contained in the configuration file is known to other users, which poses a certain security risk. Therefore, the new version of the circuit logic configuration file can contain the new version of the authentication root key to update the authentication root key deployed on the FPGA structure to ensure that the new version of the authentication root key is only known to the deployed user to eliminate the above Security risks. And, the subsequent configuration file deployment key or other keys can be negotiated with the client based on the new version of the authentication root key, and sufficient security of these keys can be ensured.
- the FPGA structure can avoid taking the authentication root key from the corresponding circuit logic configuration file, so that the FPGA structure can obtain the corresponding authentication root key after loading the circuit logic configuration file to the FPGA chip.
- the FPGA structure can include a key management chip independent of the FPGA chip, and the FPGA structure can take the authentication root key out of the circuit logic configuration file to which it belongs and maintain it in the key management chip, so that only the authentication root key exists In the key management chip, it will no longer appear in the circuit logic configuration file deployed on the FPGA structure to improve the security of the authentication root key.
- Step 106 The FPGA structure is updated and deployed based on the new version of the circuit logic configuration file obtained by decryption, so that the FPGA structure is implemented as a trusted execution environment on the blockchain node to which it belongs.
- the decryption module formed on the FPGA chip based on the old version of the circuit logic configuration file, and the configuration file deployment key maintained on the FPGA structure, so that only users who know the configuration file deployment key can configure the old version of the circuit logic on the FPGA structure
- the file is updated to ensure that the update operation implemented for the old version of the circuit logic configuration file is a trusted update operation.
- the public key or preset certificate corresponding to the client can be deployed on the FPGA structure.
- the client can sign the new version of the circuit logic configuration file and send it to the FPGA structure, so that the FPGA structure can perform signature verification for the received new version of the circuit logic configuration file, and use the signature verification as a condition for allowing the deployment of the new version of the circuit logic configuration file one.
- the public key or certificate corresponding to the client can be deployed in the FPGA structure by the old version of the circuit logic configuration file. Therefore, based on the signature verification of the new version of the circuit logic configuration file, the credibility of the new version of the circuit logic configuration file can be further improved to ensure the credible update of the circuit logic configuration file on the FPGA structure.
- the FPGA structure can read the encrypted new version of the circuit logic configuration file into the verification module on the FPGA chip for signature verification. Similar to the aforementioned decryption module, the verification module can be formed by the FPGA chip based on the old version of the circuit logic configuration file.
- the circuit logic configuration file can be directly read and configured in the FPGA chip.
- the FPGA chip is volatile, and the circuit logic configuration file deployed after the power is off will be lost, so that the client needs to re-deploy the circuit logic configuration file after power on.
- the FPGA structure can further include a memory, which is connected to the FPGA chip, so that the circuit logic configuration file is deployed in the memory, and the FPGA chip reads the circuit logic configuration file from the memory to implement related functions ;
- the memory is non-volatile, even if the power is off, the circuit logic configuration file can still be saved, and after the power is turned on, it is only necessary to read the FPGA chip from the memory again, without the client re-deployment.
- the memory may have various forms, such as a non-volatile memory that can be re-erasable, such as flash memory, and a non-re-erasable memory, such as a fuse memory, which is not limited in this specification. Therefore, when the old version of the circuit logic configuration file is deployed in the memory, the FPGA structure can update the memory based on the new version of the circuit logic configuration file, so that the old version of the circuit logic configuration file deployed in the memory is updated to the new version of the circuit logic configuration file.
- the FPGA structure can generate an authentication result for the new version of the circuit logic configuration file that is updated and deployed, and the authentication result includes content related to the new version of the circuit logic configuration file. Then, the FPGA structure can sign the authentication result based on the new version of the authentication root key that was updated and deployed, and return the signed authentication result to the client.
- the client can verify the signature of the received authentication result, and the client can generate related content based on the new version of the circuit logic file maintained by itself, then: the authentication result has passed the signature verification and the authentication result contains the "and the new version of the circuit logic configuration"
- the client can confirm that the new version of the circuit logic configuration file is successfully deployed on the FPGA structure.
- the foregoing content related to the new version of the circuit logic configuration file may be a hash value of the new version of the circuit logic configuration file or a derivative value of the hash value.
- the FPGA structure can renegotiate the new version of the configuration file deployment key based on the new version of the authentication root key, and the FPGA structure can generate the hash value of the new version of the circuit logic configuration file and the hash value of the new version of the configuration file deployment key.
- the client can determine based on the authentication result: the new version The circuit logic configuration file was successfully deployed on the FPGA structure, and the new version of the configuration file deployment key was successfully negotiated between the client and the FPGA structure.
- Fig. 2 is a schematic structural diagram of a blockchain node provided by an exemplary embodiment.
- an FPGA structure can be added to the blockchain node to implement hardware TEE.
- the FPGA structure can be an FPGA board as shown in FIG. 2.
- the FPGA board can be connected to the blockchain node through the PCIE interface to realize the data interaction between the FPGA board and the blockchain node.
- FPGA boards can include FPGA chips, Flash (flash memory) chips, and dense tube chips; of course, in addition to FPGA chips in some embodiments, they may only include parts of the remaining Flash chips and dense tube chips. , Or may contain more structures, here are just examples.
- no user-defined logic is programmed on the FPGA chip, which is equivalent to the FPGA chip in a blank state.
- Users can burn circuit logic configuration files on the FPGA chip to form corresponding functions or logic on the FPGA chip.
- the FPGA board does not have the capability of security protection, so it usually needs to provide an external security environment.
- users can implement the programming of the circuit logic configuration file in an offline environment to achieve physical security isolation. Instead of implementing remote programming online.
- the corresponding logic code can be formed through FPGA hardware language, and then the logic code can be mirrored to obtain the above-mentioned circuit logic configuration file.
- the user can check the above-mentioned logic code. Especially, when multiple users are involved at the same time, multiple users can check the above logic code separately to ensure that the FPGA board can finally meet the needs of all users and prevent security risks, logic errors, fraud and other abnormalities. problem.
- the user can burn the circuit logic configuration file to the FPGA board in the above-mentioned offline environment.
- the circuit logic configuration file is transferred from the blockchain node to the FPGA board, and then deployed to the Flash chip as shown in Figure 2, so that even if the FPGA board is powered off, the Flash chip can still save the above-mentioned circuit logic. Configuration file.
- Fig. 3 is a schematic diagram of forming a functional module on an FPGA chip provided by an exemplary embodiment.
- the hardware logic unit contained in the FPGA chip can be configured to form corresponding functional modules on the FPGA chip.
- the formed functional modules can include such The key agreement module, decryption verification module, encryption and decryption module, plaintext calculation module, etc. shown in FIG. 3.
- the circuit logic configuration file can also be used to transmit the information that needs to be stored to the FPGA board.
- the preset certificate can be stored on the FPGA chip, and the authentication root key can be stored in the secret tube chip (the authentication root key can also be Stored on the FPGA chip) and so on.
- the FPGA board can realize remote key agreement with the user.
- the key agreement process can use related technologies. Any algorithm or standard can be implemented, and this specification does not limit it.
- the key agreement process can include: the user can generate a key Ka-1 at the local client, the key agreement module can generate a key Kb-1 locally, and the client can generate a key Kb-1 based on the key Ka- 1 Calculate the key agreement information Ka-2, the key agreement module can calculate the key agreement information Kb-2 based on the key Kb-1, and then the client sends the key agreement information Ka-2 to the key agreement module, The key agreement module sends the key agreement information Kb-2 to the client, so that the client can generate a secret value based on the key Ka-1 and the key agreement information Kb-2, and the key agreement module can be based on the key Kb -1 generates the same secret value as the key agreement information Ka-2, and finally the client and the key agreement module respectively derive the same
- the key agreement information Ka-2 and key agreement information Kb-2 are transmitted between the client and the key agreement module via the blockchain node
- the key Ka-1 is controlled by the client
- the key Kb-1 is controlled by the key agreement module, so it can ensure that the blockchain node cannot know the final secret value and the configuration file deployment key, so as to avoid possible security risks.
- the secret value is also used to derive the business secret deployment key; for example, the secret value can be derived as a 32-bit value, the first 16 bits can be used as the configuration file deployment key, and the last 16 bits can be used as the business secret deployment Key.
- the user can deploy the service key to the FPGA board through the service secret deployment key.
- the service key may include the node private key and the service root key.
- the user can use the business secret deployment key on the client to sign, encrypt the node private key or the business root key, and send it to the FPGA board, so that after the FPGA board is decrypted and verified through the decryption verification module, Deploy the obtained node private key or service root key.
- the FPGA board can be implemented as a TEE on the blockchain node to meet privacy requirements. For example, when a blockchain node receives a transaction, if the transaction is a plaintext transaction, the blockchain node can directly process the plaintext transaction, if the transaction is a private transaction, the blockchain node transmits the private transaction to the FPGA The board is processed.
- the transaction content of a plaintext transaction is in plaintext form, and the contract status generated after the transaction is executed is also stored in plaintext form.
- the transaction content of a private transaction is in the form of cipher text, which is obtained by encrypting the content of the transaction in plain text by the transaction initiator, and the contract state generated after the transaction is executed needs to be stored in the form of cipher text to ensure the protection of transaction privacy.
- the transaction initiator can generate a symmetric key randomly or based on other methods.
- the business public key corresponding to the above-mentioned business private key is disclosed, then the transaction initiator can perform transaction content in plaintext based on the symmetric key and the business public key.
- the transaction initiator encrypts the plaintext transaction content with a symmetric key, and encrypts the symmetric key with the business public key.
- the two parts obtained are included in the above-mentioned private transaction; in other words, the private transaction includes Two parts of content: the content of the transaction in plaintext encrypted with a symmetric key, and the symmetric key encrypted with the business public key.
- the encryption and decryption module can use the business private key to decrypt the symmetric key encrypted with the business public key to obtain the symmetric key, and then the encryption and decryption module
- the symmetric key is used to decrypt the plaintext transaction content encrypted with the symmetric key to obtain the plaintext transaction content.
- Private transactions can be used to deploy smart contracts, then the data field of the plaintext transaction content can contain the contract code of the smart contract to be deployed; or, the privacy transaction can be used to call the smart contract, then the to field of the plaintext transaction content can contain the called The contract address of the smart contract, and the FPGA board can retrieve the corresponding contract code based on the contract address.
- the plaintext calculation module formed on the FPGA chip is used to implement virtual machine logic in related technologies, that is, the plaintext calculation module is equivalent to the "hardware virtual machine" on the FPGA board. Therefore, after the contract code is determined based on the foregoing plaintext transaction content, the contract code can be passed into the plaintext calculation module, so that the plaintext calculation module executes the contract code. After the execution is completed, the state of the contract involved in the contract code may be updated.
- the encryption and decryption module can encrypt the updated contract state through the aforementioned business root key or its derivative key, and store the encrypted contract state to ensure privacy
- the transaction-related data is only in the clear text state in the FPGA chip and in the cipher text state outside the FPGA chip, so as to ensure the security of the data.
- the user may want to update the version of the circuit logic configuration file deployed on the FPGA board.
- the authentication root key contained in the circuit logic configuration file may be known by risky users, or the user wants to update the version on the FPGA board.
- the deployed functional modules are upgraded, etc. This manual does not limit this.
- the circuit logic configuration file that has been deployed in the above process can be referred to as the old version of the circuit logic configuration file, and the circuit logic configuration file that needs to be deployed is referred to as the new version of the circuit logic configuration file.
- the user can generate a new version of the circuit logic configuration file through the process of writing code and mirroring. Further, the user can sign the new version of the circuit logic configuration file with his own private key, and then encrypt the signed new version of the circuit logic configuration file with the configuration file deployment key negotiated above to obtain the encrypted new version of the circuit Logical configuration file. In some cases, there may be multiple users at the same time, so the old version of the circuit logic configuration file needs to deploy the preset certificates corresponding to these users to the FPGA board, and these users need to use their own private keys to pair the new version of the circuit. Sign the logical configuration file.
- Fig. 4 is a schematic diagram of newly updateable FPGA board provided by an exemplary embodiment.
- the decryption verification module formed on the FPGA chip in the foregoing process is located on the transmission path between the PCIE interface and the Flash chip, so that the new version of the circuit logic configuration file after encryption must first pass the decryption verification module. After processing, it can be transferred to the Flash chip to achieve a credible update, and the Flash chip cannot be updated directly without bypassing the decryption and verification process.
- the decryption verification module After the decryption verification module receives the encrypted new version of the circuit logic configuration file, it first decrypts it with the configuration file deployment key deployed on the FPGA board. If the decryption is successful, the decryption verification module is further based on the preset certificate deployed on the FPGA chip , To perform signature verification on the decrypted new version of the circuit logic configuration file.
- the decryption and signature verification module will trigger the termination of the update operation; and if the decryption is successful and the signature verification is passed, you can It is determined that the obtained new version of the circuit logic configuration file is from the aforementioned user and has not been tampered with during the transmission process.
- the new version of the circuit logic configuration file can be further transmitted to the Flash chip to update and deploy the old version of the circuit logic configuration file in the Flash chip.
- the above-mentioned key agreement module, decryption and verification module can also be formed on the FPGA chip, and the pre-set certificate and authentication can be stored in the FPGA chip. Root key and other information.
- the formed key agreement module, decryption verification module, etc., the implemented functional logic can be changed and upgraded, and the information stored in the deployed preset certificate, authentication root key and other information may also be different from the information before the update .
- the FPGA board can remotely negotiate with the user to obtain a new configuration file deployment key based on the updated key agreement module, authentication root key, etc., and the configuration file deployment key can be used for the next renewal Update process. Similarly, a reliable update operation for FPGA boards can be continuously implemented accordingly.
- the FPGA board can generate certification results for the new version of the circuit logic configuration file.
- the above-mentioned key agreement module can calculate the hash value of the new version of the circuit logic configuration file and the hash value of the configuration file deployment key negotiated based on the new version of the circuit logic configuration file through an algorithm such as sm3 or other algorithms.
- the calculation result can be used as the above-mentioned authentication result, and the key agreement module sends the authentication result to the user.
- the user can verify the authentication result on the client based on the maintained new version of the circuit logic configuration file and the configuration file deployment key negotiated accordingly. If the verification is successful, it indicates that the new version of the circuit logic configuration file is successful on the FPGA board. Deployed, and the user and the FPGA board successfully negotiated accordingly to obtain a consistent configuration file deployment key, thereby confirming the successful completion of the circuit logic configuration file update deployment.
- Fig. 5 is a schematic structural diagram of a trusted update device for FPGA logic provided by an exemplary embodiment.
- the trusted update device for FPGA logic may include: a receiving unit 501, which enables the FPGA structure to receive the encrypted new version of the circuit logic configuration file from the client, and the FPGA structure includes the FPGA chip; Unit 502, enabling the FPGA structure to read the encrypted new version of the circuit logic configuration file into the decryption module on the FPGA chip for decryption.
- the decryption module is based on the FPGA chip based on the old version deployed on the FPGA structure.
- the circuit logic configuration file is formed; the update unit 503 enables the FPGA structure to be updated and deployed based on the new version of the circuit logic configuration file obtained by decryption, so that the FPGA structure is implemented as a trusted execution environment on the blockchain node to which it belongs.
- a negotiation unit 504 which enables the FPGA structure to perform remote negotiation with the client based on the deployed authentication root key to negotiate a configuration file deployment key; wherein, the encrypted new version of the circuit
- the logic configuration file is decrypted in the decryption module by the FPGA structure based on the configuration file deployment key.
- the deployed authentication root key is deployed to the FPGA structure based on the old version of the circuit logic configuration file.
- the deployed authentication root key is maintained in a key management chip included in the FPGA structure.
- the new version of the circuit logic configuration file includes: a new version of the authentication root key for updating the deployed authentication root key.
- it further includes: a signing unit 505 for enabling the FPGA structure to sign the authentication result through the new version of the authentication root key, the authentication result including content related to the new version of the circuit logic configuration file; a returning unit 506 , Enabling the FPGA structure to return the signed authentication result to the client, so that the client passes the signature verification on the authentication result and the authentication result contains information related to the new version of the circuit logic configuration file In the case of content, it is confirmed that the new version of the circuit logic configuration file is successfully deployed on the FPGA structure.
- a signing unit 505 for enabling the FPGA structure to sign the authentication result through the new version of the authentication root key, the authentication result including content related to the new version of the circuit logic configuration file
- a returning unit 506 Enabling the FPGA structure to return the signed authentication result to the client, so that the client passes the signature verification on the authentication result and the authentication result contains information related to the new version of the circuit logic configuration file In the case of content, it is confirmed that the new version of the circuit logic configuration file is successfully deployed on
- it further includes: a verification unit 507 that enables the FPGA structure to read the encrypted new version of the circuit logic configuration file into the verification module on the FPGA chip for signature verification, and the verification module is used by the FPGA The chip is formed based on the old version of the circuit logic configuration file, and the preset certificate corresponding to the client has been deployed on the FPGA structure; the update unit 503 is specifically configured to: enable the FPGA structure to successfully verify the signature Next, update deployment based on the new version of the circuit logic configuration file.
- the FPGA structure further includes a memory other than the FPGA chip; the update unit 503 is specifically configured to: enable the FPGA structure to update and deploy the memory based on the new version of the circuit logic configuration file.
- a typical implementation device is a computer.
- the specific form of the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email receiving and sending device, and a game control A console, a tablet computer, a wearable device, or a combination of any of these devices.
- the computer includes one or more processors (CPU), input/output interfaces, network interfaces, and memory.
- processors CPU
- input/output interfaces network interfaces
- memory volatile and non-volatile memory
- the memory may include non-permanent memory in a computer readable medium, random access memory (RAM) and/or non-volatile memory, such as read-only memory (ROM) or flash memory (flash RAM). Memory is an example of computer readable media.
- RAM random access memory
- ROM read-only memory
- flash RAM flash memory
- Computer-readable media include permanent and non-permanent, removable and non-removable media, and information storage can be realized by any method or technology.
- the information can be computer-readable instructions, data structures, program modules, or other data.
- Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disc (DVD) or other optical storage, Magnetic cassettes, disk storage, quantum memory, graphene-based storage media or other magnetic storage devices or any other non-transmission media can be used to store information that can be accessed by computing devices. According to the definition in this article, computer-readable media does not include transitory media, such as modulated data signals and carrier waves.
- first, second, third, etc. may be used to describe various information in one or more embodiments of this specification, the information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other.
- first information may also be referred to as second information, and similarly, the second information may also be referred to as first information.
- word “if” as used herein can be interpreted as "when” or “when” or "in response to determination”.
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Abstract
A trusted update method and apparatus for FPGA logic. The method may comprise: an FPGA structure receives an encrypted new version of circuit logic configuration file from a client, the FPGA structure comprising an FPGA chip (102); the FPGA structure reads the encrypted new version of circuit logic configuration file into a decryption module on the FPGA chip for decryption, the decryption module being formed by the FPGA chip on the basis of an old version of circuit logic configuration file deployed on the FPGA structure (104); the FPGA structure performs deployment update on the basis of the decrypted new version of circuit logic configuration file, so that the FPGA structure is implemented as a trusted execution environment on a blockchain node to which the FPGA structure belongs (106).
Description
本说明书一个或多个实施例涉及区块链技术领域,尤其涉及一种FPGA逻辑的可信更新方法及装置。One or more embodiments of this specification relate to the field of blockchain technology, and in particular, to a trusted update method and device for FPGA logic.
区块链技术构建在传输网络(例如点对点网络)之上。传输网络中的网络节点利用链式数据结构来验证与存储数据,并采用分布式节点共识算法来生成和更新数据。Blockchain technology is built on a transmission network (such as a peer-to-peer network). The network nodes in the transmission network use chained data structures to verify and store data, and use distributed node consensus algorithms to generate and update data.
目前企业级的区块链平台技术上最大的两个挑战就是隐私和性能,往往这两个挑战很难同时解决。大多解决方案都是通过损失性能换取隐私,或者不大考虑隐私去追求性能。常见的解决隐私问题的加密技术,如同态加密(Homomorphic encryption)和零知识证明(Zero-knowledge proof)等复杂度高,通用性差,而且还可能带来严重的性能损失。At present, the two biggest challenges in enterprise-level blockchain platform technology are privacy and performance. It is often difficult to solve these two challenges at the same time. Most of the solutions are to lose performance in exchange for privacy, or do not consider privacy to pursue performance. Common encryption technologies that solve privacy problems, such as Homomorphic encryption and Zero-knowledge proof, are highly complex, have poor versatility, and may also cause serious performance losses.
可信执行环境(Trusted Execution Environment,TEE)是另一种解决隐私问题的方式。TEE可以起到硬件中的黑箱作用,在TEE中执行的代码和数据操作***层都无法偷窥,只有代码中预先定义的接口才能对其进行操作。在效率方面,由于TEE的黑箱性质,在TEE中进行运算的是明文数据,而不是同态加密中的复杂密码学运算,计算过程效率没有损失,因此与TEE相结合可以在性能损失较小的前提下很大程度上提升区块链的安全性和隐私性。目前工业界十分关注TEE的方案,几乎所有主流的芯片和软件联盟都有自己的TEE解决方案,包括软件方面的TPM(Trusted Platform Module,可信赖平台模块)以及硬件方面的Intel SGX(Software Guard Extensions,软件保护扩展)、ARM Trustzone(信任区)和AMD PSP(Platform Security Processor,平台安全处理器)。Trusted Execution Environment (TEE) is another way to solve privacy issues. TEE can play the role of a black box in the hardware. Neither the code executed in the TEE nor the data operating system layer can be peeped, and only the pre-defined interface in the code can operate on it. In terms of efficiency, due to the black box nature of TEE, plaintext data is calculated in TEE instead of complex cryptographic operations in homomorphic encryption. There is no loss of efficiency in the calculation process. Therefore, the combination with TEE can achieve less performance loss. Under the premise, the security and privacy of the blockchain are greatly improved. At present, the industry is very concerned about the TEE solution. Almost all mainstream chip and software alliances have their own TEE solutions, including TPM (Trusted Platform Module) in software and Intel SGX (Software Guard Extensions) in hardware. , Software Protection Extension), ARM Trustzone (trust zone) and AMD PSP (Platform Security Processor, platform security processor).
发明内容Summary of the invention
有鉴于此,本说明书一个或多个实施例提供一种FPGA逻辑的可信更新方法及装置。In view of this, one or more embodiments of this specification provide a trusted update method and device for FPGA logic.
为实现上述目的,本说明书一个或多个实施例提供技术方案如下。To achieve the foregoing objectives, one or more embodiments of the present specification provide technical solutions as follows.
根据本说明书一个或多个实施例的第一方面,提出了一种FPGA逻辑的可信更新 方法,包括:FPGA结构接收来自客户端的加密后新版电路逻辑配置文件,所述FPGA结构包含FPGA芯片;所述FPGA结构将所述加密后新版电路逻辑配置文件读入所述FPGA芯片上的解密模块进行解密,所述解密模块由所述FPGA芯片基于所述FPGA结构上已部署的旧版电路逻辑配置文件而形成;所述FPGA结构基于解密得到的新版电路逻辑配置文件进行更新部署,以使所述FPGA结构实现为所属的区块链节点上的可信执行环境。According to the first aspect of one or more embodiments of this specification, a trusted update method of FPGA logic is proposed, which includes: the FPGA structure receives an encrypted new version of the circuit logic configuration file from a client, the FPGA structure includes an FPGA chip; The FPGA structure reads the encrypted new version of the circuit logic configuration file into the decryption module on the FPGA chip for decryption, and the decryption module is based on the old version of the circuit logic configuration file deployed on the FPGA structure by the FPGA chip. Formed; the FPGA structure is updated and deployed based on the new version of the circuit logic configuration file obtained by decryption, so that the FPGA structure is implemented as a trusted execution environment on the blockchain node to which it belongs.
根据本说明书一个或多个实施例的第二方面,提出了一种FPGA逻辑的可信更新装置,包括:接收单元,使FPGA结构接收来自客户端的加密后新版电路逻辑配置文件,所述FPGA结构包含FPGA芯片;解密单元,使所述FPGA结构将所述加密后新版电路逻辑配置文件读入所述FPGA芯片上的解密模块进行解密,所述解密模块由所述FPGA芯片基于所述FPGA结构上已部署的旧版电路逻辑配置文件而形成;更新单元,使所述FPGA结构基于解密得到的新版电路逻辑配置文件进行更新部署,以使所述FPGA结构实现为所属的区块链节点上的可信执行环境。According to the second aspect of one or more embodiments of the present specification, a trusted update device for FPGA logic is proposed, which includes: a receiving unit that enables the FPGA structure to receive the encrypted new version of the circuit logic configuration file from the client. The FPGA structure Contains an FPGA chip; a decryption unit that causes the FPGA structure to read the encrypted new version of the circuit logic configuration file into the decryption module on the FPGA chip for decryption, and the decryption module is based on the FPGA structure by the FPGA chip The deployed old version of the circuit logic configuration file is formed; the update unit enables the FPGA structure to be updated and deployed based on the new version of the circuit logic configuration file obtained by decryption, so that the FPGA structure is implemented as a trusted blockchain node. Execution environment.
根据本说明书一个或多个实施例的第三方面,提出了一种电子设备,包括:处理器;用于存储处理器可执行指令的存储器;其中,所述处理器通过运行所述可执行指令以实现如第一方面所述的方法。According to a third aspect of one or more embodiments of this specification, an electronic device is proposed, including: a processor; a memory for storing executable instructions of the processor; wherein the processor runs the executable instructions In order to realize the method as described in the first aspect.
根据本说明书一个或多个实施例的第四方面,提出了一种计算机可读存储介质,其上存储有计算机指令,该指令被处理器执行时实现如第一方面所述方法的步骤。According to the fourth aspect of one or more embodiments of the present specification, a computer-readable storage medium is provided, on which computer instructions are stored, and when the instructions are executed by a processor, the steps of the method described in the first aspect are implemented.
图1是一示例性实施例提供的一种FPGA逻辑的可信更新方法的流程图。Fig. 1 is a flowchart of a trusted update method of FPGA logic provided by an exemplary embodiment.
图2是一示例性实施例提供的一种区块链节点的结构示意图。Fig. 2 is a schematic structural diagram of a blockchain node provided by an exemplary embodiment.
图3是一示例性实施例提供的一种在FPGA芯片上形成功能模块的示意图。Fig. 3 is a schematic diagram of forming a functional module on an FPGA chip provided by an exemplary embodiment.
图4是一示例性实施例提供的一种对FPGA板卡进行可新更新的示意图。Fig. 4 is a schematic diagram of newly updateable FPGA board provided by an exemplary embodiment.
图5是一示例性实施例提供的一种FPGA逻辑的可信更新装置的框图。Fig. 5 is a block diagram of a trusted update device for FPGA logic provided by an exemplary embodiment.
这里将详细地对示例性实施例进行说明,其示例表示在附图中。下面的描述涉及附图时,除非另有表示,不同附图中的相同数字表示相同或相似的要素。以下示例性实 施例中所描述的实施方式并不代表与本说明书一个或多个实施例相一致的所有实施方式。相反,它们仅是与如所附权利要求书中所详述的、本说明书一个或多个实施例的一些方面相一致的装置和方法的例子。The exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings indicate the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with one or more embodiments of this specification. Rather, they are merely examples of devices and methods consistent with some aspects of one or more embodiments of this specification as detailed in the appended claims.
需要说明的是:在其他实施例中并不一定按照本说明书示出和描述的顺序来执行相应方法的步骤。在一些其他实施例中,其方法所包括的步骤可以比本说明书所描述的更多或更少。此外,本说明书中所描述的单个步骤,在其他实施例中可能被分解为多个步骤进行描述;而本说明书中所描述的多个步骤,在其他实施例中也可能被合并为单个步骤进行描述。It should be noted that in other embodiments, the steps of the corresponding method are not necessarily executed in the order shown and described in this specification. In some other embodiments, the method may include more or fewer steps than described in this specification. In addition, a single step described in this specification may be decomposed into multiple steps for description in other embodiments; and multiple steps described in this specification may also be combined into a single step in other embodiments. description.
区块链一般被划分为三种类型:公有链(Public Blockchain)、私有链(Private Blockchain)和联盟链(Consortium Blockchain)。此外,还有多种类型的结合,比如私有链+联盟链、联盟链+公有链等不同组合形式。其中去中心化程度最高的是公有链。公有链以比特币、以太坊为代表,加入公有链的参与者可以读取链上的数据记录、参与交易以及竞争新区块的记账权等。而且,各参与者(即节点)可自由加入以及退出网络,并进行相关操作。私有链则相反,该网络的写入权限由某个组织或者机构控制,数据读取权限受组织规定。简单来说,私有链可以为一个弱中心化***,参与节点具有严格限制且少。这种类型的区块链更适合于特定机构内部使用。联盟链则是介于公有链以及私有链之间的区块链,可实现“部分去中心化”。联盟链中各个节点通常有与之相对应的实体机构或者组织;参与者通过授权加入网络并组成利益相关联盟,共同维护区块链运行。Blockchain is generally divided into three types: Public Blockchain, Private Blockchain and Consortium Blockchain. In addition, there are many types of combinations, such as private chain + alliance chain, alliance chain + public chain and other different combinations. Among them, the most decentralized one is the public chain. The public chain is represented by Bitcoin and Ethereum. Participants who join the public chain can read the data records on the chain, participate in transactions, and compete for the accounting rights of new blocks. Moreover, each participant (ie, node) can freely join and exit the network, and perform related operations. The private chain is the opposite. The write permission of the network is controlled by an organization or institution, and the data read permission is regulated by the organization. In simple terms, the private chain can be a weakly centralized system with strict restrictions and few participating nodes. This type of blockchain is more suitable for internal use by specific institutions. Consortium chain is a block chain between public chain and private chain, which can realize "partial decentralization". Each node in the alliance chain usually has a corresponding entity or organization; participants are authorized to join the network and form a stakeholder alliance to jointly maintain the operation of the blockchain.
不论是公有链、私有链还是联盟链,区块链网络中的节点出于隐私保护的目的,均可能通过区块链与TEE(Trusted Execution Environment,可信执行环境)相结合的解决方案,在TEE内执行收到的交易。TEE是基于CPU硬件的安全扩展,且与外部完全隔离的可信执行环境。TEE最早是由Global Platform提出的概念,用于解决移动设备上资源的安全隔离,平行于操作***为应用程序提供可信安全的执行环境。ARM的Trust Zone技术最早实现了真正商用的TEE技术。伴随着互联网的高速发展,安全的需求越来越高,不仅限于移动设备,云端设备,数据中心都对TEE提出了更多的需求。TEE的概念也得到了高速的发展和扩充。现在所说的TEE相比与最初提出的概念已经是更加广义的TEE。例如,服务器芯片厂商Intel,AMD等都先后推出了硬件辅助的TEE并丰富了TEE的概念和特性,在工业界得到了广泛的认可。现在提起的TEE通常更多指这类硬件辅助的TEE技术。Regardless of whether it is a public chain, a private chain or a consortium chain, for the purpose of privacy protection, the nodes in the blockchain network may use a solution that combines the blockchain and the TEE (Trusted Execution Environment). Execute received transactions within TEE. TEE is a secure extension based on CPU hardware and a trusted execution environment that is completely isolated from the outside. TEE was first proposed by Global Platform to solve the security isolation of resources on mobile devices, and parallel to the operating system to provide a trusted and secure execution environment for applications. ARM's Trust Zone technology is the first to realize the real commercial TEE technology. With the rapid development of the Internet, security requirements are getting higher and higher. Not only mobile devices, cloud devices, and data centers have put forward more demands on TEE. The concept of TEE has also been rapidly developed and expanded. Compared with the originally proposed concept, the TEE referred to now is a more generalized TEE. For example, server chip manufacturers Intel and AMD have successively introduced hardware-assisted TEE and enriched the concepts and features of TEE, which has been widely recognized in the industry. The TEE mentioned now usually refers more to this kind of hardware-assisted TEE technology.
以Intel SGX技术为例,SGX提供了围圈(enclave,也称为飞地),即内存中一个加密的可信执行区域,由CPU保护数据不被窃取。以第一区块链节点采用支持SGX的CPU为例,利用新增的处理器指令,在内存中可以分配一部分区域EPC(Enclave Page Cache,围圈页面缓存或飞地页面缓存),通过CPU内的加密引擎MEE(Memory Encryption Engine)对其中的数据进行加密。EPC中加密的内容只有进入CPU后才会被解密成明文。因此,在SGX中,用户可以不信任操作***、VMM(Virtual Machine Monitor,虚拟机监控器)、甚至BIOS(Basic Input Output System,基本输入输出***),只需要信任CPU便能确保隐私数据不会泄漏。因此,围圈就相当于SGX技术下产生的TEE。Taking Intel SGX technology as an example, SGX provides an enclave (also known as an enclave), which is an encrypted trusted execution area in the memory, and the CPU protects data from being stolen. Taking the first blockchain node using a CPU that supports SGX as an example, using the newly added processor instructions, a part of the area EPC (Enclave Page Cache, enclave page cache or enclave page cache) can be allocated in the memory, and through the CPU The encryption engine MEE (Memory Encryption Engine) encrypts the data in it. The encrypted content in EPC will be decrypted into plain text only after entering the CPU. Therefore, in SGX, users can distrust the operating system, VMM (Virtual Machine Monitor), and even BIOS (Basic Input Output System). They only need to trust the CPU to ensure that private data will not leakage. Therefore, the enclosure is equivalent to the TEE produced under SGX technology.
不同于移动端,云端访问需要远程访问,终端用户对硬件平台不可见,因此使用TEE的第一步就是要确认TEE的真实可信。例如,相关技术中提供了针对上述SGX技术的远程证明机制,以用于证明目标设备上的SGX平台与挑战方部署了相同的配置文件。但是,由于相关技术中的TEE技术是以软件或软硬件结合的方式实现,使得即便通过远程证明方式可以在一定程度上表明TEE内所部署的配置文件未经篡改,但是TEE本身所依托的运行环境却无法被验证。例如,在需要实现隐私功能的区块链节点上,TEE内需要配置用于执行智能合约的虚拟机,该虚拟机所执行的指令并非直接执行,而是实际上执行了对应的若干条X86指令(假定目标设备采用X86架构),从而造成了一定程度上的安全性风险。Different from the mobile terminal, cloud access requires remote access, and the end user is invisible to the hardware platform. Therefore, the first step in using TEE is to confirm the authenticity of TEE. For example, the related technology provides a remote certification mechanism for the above-mentioned SGX technology to prove that the SGX platform on the target device and the challenger have deployed the same configuration file. However, because the TEE technology in the related technology is implemented by software or a combination of software and hardware, even if the remote attestation method can indicate to a certain extent that the configuration file deployed in the TEE has not been tampered with, the TEE itself depends on the operation The environment cannot be verified. For example, on a blockchain node that needs to implement privacy functions, a virtual machine for executing smart contracts needs to be configured in the TEE. The instructions executed by the virtual machine are not directly executed, but actually executed corresponding X86 instructions (Assuming that the target device adopts the X86 architecture), which poses a certain degree of security risk.
为此,本说明书提出了一种基于FPGA实现的硬件TEE技术,FPGA通过加载电路逻辑配置文件而实现硬件TEE。由于电路逻辑配置文件的内容可以被预先查看与检验,并且FPGA完全基于电路逻辑配置文件中记载的逻辑而配置运行,因而可以确保FPGA所实现的硬件TEE具有相对更高的安全性。但是,相关技术中未提供相应的防范机制,以避免针对FPGA中的电路逻辑配置文件实施有意或无意的不可信更新操作。To this end, this specification proposes a hardware TEE technology based on FPGA implementation. FPGA implements hardware TEE by loading circuit logic configuration files. Because the content of the circuit logic configuration file can be checked and verified in advance, and the FPGA is configured and operated completely based on the logic recorded in the circuit logic configuration file, it can be ensured that the hardware TEE implemented by the FPGA has relatively higher security. However, the related technology does not provide a corresponding preventive mechanism to avoid intentionally or unintentionally untrusted update operations for the circuit logic configuration files in the FPGA.
以下结合实施例说明本说明书提供的一种FPGA逻辑的可信更新方法,以提升安全性。The following describes a trusted update method of FPGA logic provided in this specification in conjunction with embodiments to improve security.
图1是一示例性实施例提供的一种FPGA逻辑的可信更新方法的流程图。如图1所示,该方法应用于FPGA结构,可以包括步骤102-106。Fig. 1 is a flowchart of a trusted update method of FPGA logic provided by an exemplary embodiment. As shown in Figure 1, the method is applied to the FPGA structure and may include steps 102-106.
步骤102,FPGA结构接收来自客户端的加密后新版电路逻辑配置文件,所述FPGA结构包含FPGA芯片。Step 102: The FPGA structure receives the encrypted new version of the circuit logic configuration file from the client, and the FPGA structure includes the FPGA chip.
用户可以通过客户端向FPGA结构提供加密后新版电路逻辑配置文件,该用户具体可以为个人或团体(如企业),本说明书并不对此进行限制。其中,客户端可以远程将加密后新版电路逻辑配置文件发送至FPGA结构;或者,客户端可以与FPGA结构位于同一地点,以在本地或局域网内实现对加密后新版电路逻辑配置文件的传输。The user can provide the encrypted new version of the circuit logic configuration file to the FPGA structure through the client. The user can be an individual or a group (such as an enterprise), and this manual does not limit this. Among them, the client can remotely send the encrypted new version of the circuit logic configuration file to the FPGA structure; or, the client can be located at the same place as the FPGA structure to realize the transmission of the encrypted new version of the circuit logic configuration file locally or in a local area network.
客户端可以直接与FPGA结构建立连接,并将加密后新版电路逻辑文件直接发送至FPGA结构。或者,客户端可以与FPGA结构所属的区块链节点(相当于FPGA结构对应的Host主机)建立连接,并将加密后新版电路逻辑文件发送至该区块链节点后,由该区块链节点提供至FPGA结构。The client can directly establish a connection with the FPGA structure, and send the encrypted new version of the circuit logic file directly to the FPGA structure. Or, the client can establish a connection with the blockchain node to which the FPGA structure belongs (equivalent to the Host host corresponding to the FPGA structure), and send the encrypted new version of the circuit logic file to the blockchain node. Provided to FPGA structure.
步骤104,所述FPGA结构将所述加密后新版电路逻辑配置文件读入所述FPGA芯片上的解密模块进行解密,所述解密模块由所述FPGA芯片基于所述FPGA结构上已部署的旧版电路逻辑配置文件而形成。Step 104: The FPGA structure reads the encrypted new version of the circuit logic configuration file into the decryption module on the FPGA chip for decryption. The decryption module is based on the old version of the circuit deployed on the FPGA structure by the FPGA chip. Logical configuration files are formed.
FPGA芯片上包含若干可编辑的硬件逻辑单元,这些硬件逻辑单元经由电路逻辑配置文件进行配置后,可以实现为相应的功能模块,以用于实现相应的逻辑功能。具体的,该电路逻辑配置文件可以基于比特流的形式被烧录至FPGA结构。例如,上述的解密模块即为通过旧版电路逻辑配置文件而形成,而通过进一步部署形成用于实现加密、虚拟机等逻辑的功能模块,可以将FPGA结构配置为区块链节点上的硬件TEE。由于这些功能模块完全由电路逻辑配置文件进行配置而形成,因而通过检查电路逻辑配置文件即可确定由此配置得到的功能模块所实现的逻辑等各方面的信息,确保功能模块能够按照完全用户的需求而形成和运行。The FPGA chip contains a number of editable hardware logic units. After these hardware logic units are configured via a circuit logic configuration file, they can be implemented as corresponding functional modules to implement corresponding logic functions. Specifically, the circuit logic configuration file can be burned to the FPGA structure based on the form of a bit stream. For example, the above-mentioned decryption module is formed by the old version of the circuit logic configuration file, and by further deploying and forming functional modules for realizing encryption, virtual machine and other logic, the FPGA structure can be configured as a hardware TEE on a blockchain node. Since these functional modules are completely configured by the circuit logic configuration file, it is possible to determine the logic and other aspects of the information realized by the functional module configured by checking the circuit logic configuration file to ensure that the functional module can be configured according to the complete user’s requirements. Needs to be formed and run.
旧版电路逻辑配置文件是指FPGA结构上预先已部署的电路逻辑配置文件。相比于上述的新版电路逻辑配置文件而言,由于旧版电路逻辑配置文件被配置于FPGA结构的时刻相对靠前,因而通过“新版”、“旧版”予以区分,而并非表明相应的电路逻辑配置文件所实现的逻辑或功能上必然实现版本迭代。The old version of the circuit logic configuration file refers to the pre-deployed circuit logic configuration file on the FPGA structure. Compared with the above-mentioned new version of the circuit logic configuration file, since the time when the old version of the circuit logic configuration file is configured in the FPGA structure is relatively earlier, it is distinguished by "new version" and "old version" instead of indicating the corresponding circuit logic configuration The logic or function implemented by the file must achieve version iteration.
新版电路逻辑配置文件可由客户端基于配置文件部署密钥进行加密后,得到上述的加密后新版电路逻辑配置文件。同时,由于FPGA结构维护了该配置文件部署密钥,使得上述的解密模块可以基于该配置文件部署密钥对加密后新版电路逻辑配置文件进行解密,以得到上述的新版电路逻辑配置文件。The new version of the circuit logic configuration file can be encrypted by the client based on the configuration file deployment key to obtain the above-mentioned encrypted new version of the circuit logic configuration file. At the same time, because the FPGA structure maintains the configuration file deployment key, the aforementioned decryption module can decrypt the encrypted new version of the circuit logic configuration file based on the configuration file deployment key to obtain the aforementioned new version of the circuit logic configuration file.
配置文件部署密钥可以预先生成后,被分别部署于客户端和FPGA结构。或者,配置文件部署密钥可由客户端与区块链节点进行远程协商得到,然后由区块链节点将协 商得到的该配置文件部署密钥传输至FPGA结构,由FPGA结构进行维护;而出于更高的安全性需求,避免配置文件部署密钥被区块链节点取得,可由FPGA结构直接与客户端进行远程协商。The configuration file deployment key can be generated in advance and then deployed on the client and FPGA structure respectively. Alternatively, the configuration file deployment key can be obtained through remote negotiation between the client and the blockchain node, and then the blockchain node transmits the negotiated configuration file deployment key to the FPGA structure, which is maintained by the FPGA structure; Higher security requirements, to prevent the configuration file deployment key from being obtained by the blockchain node, and the FPGA structure can directly negotiate with the client remotely.
以FPGA结构与客户端进行远程协商上述的配置文件部署密钥为例。远程协商过程至可以采用诸如SM2或其他算法,本说明书并不对此进行限制。客户端与FPGA结构需要在协商过程中实施至少一次信息交互,例如:客户端可以在本地生成一密钥Ka-1、FPGA结构可以在本地生成一密钥Kb-1,且客户端可以基于密钥Ka-1计算得到密钥协商信息Ka-2、FPGA结构可以基于密钥Kb-1计算得到密钥协商信息Kb-2,然后客户端将密钥协商信息Ka-2发送至FPGA结构、FPGA结构将密钥协商信息Kb-2发送至客户端,使得客户端可以基于密钥Ka-1与密钥协商信息Kb-2生成一秘密值(或称,主密钥),而FPGA结构可以基于密钥Kb-1与密钥协商信息Ka-2生成相同的秘密值。那么,上述的配置文件部署密钥可以为该秘密值;或者,该配置文件部署密钥可由客户端与FPGA结构分别通过密钥导出函数(Key Derivation Function,简称KDF)从上述的秘密值导出得到。Take the configuration file deployment key mentioned above for remote negotiation between the FPGA structure and the client as an example. The remote negotiation process can use SM2 or other algorithms, which is not limited in this manual. The client and the FPGA structure need to implement at least one information exchange during the negotiation process. For example, the client can generate a key Ka-1 locally, the FPGA structure can generate a key Kb-1 locally, and the client can be based on the secret key. The key Ka-1 is calculated to obtain the key agreement information Ka-2, and the FPGA structure can be calculated based on the key Kb-1 to obtain the key agreement information Kb-2, and then the client sends the key agreement information Ka-2 to the FPGA structure, FPGA The structure sends the key agreement information Kb-2 to the client, so that the client can generate a secret value (or master key) based on the key Ka-1 and the key agreement information Kb-2, and the FPGA structure can be based on The key Kb-1 and the key agreement information Ka-2 generate the same secret value. Then, the above-mentioned configuration file deployment key can be the secret value; or, the configuration file deployment key can be derived from the above-mentioned secret value by the client and FPGA structure respectively through the Key Derivation Function (KDF) .
FPGA结构上可以预先部署有认证根密钥,该认证根密钥可以被预置于FPGA结构中,或者该认证根密钥可由客户端或其他对象在离线安全环境下部署至FPGA结构中。该认证根密钥属于非对称密钥。那么,在客户端与FPGA结构远程协商上述配置文件部署密钥的过程中,FPGA结构可以采用认证根密钥对自身所发送的信息(比如上述的密钥协商信息Kb-2等)进行签名,而客户端可以通过验证签名而确定收到的信息是否确实来自于FPGA结构且传输过程中未经篡改,而未通过签名验证的信息将不会被客户端信任和采纳。其中,认证根密钥的公钥可以由认证服务器管理且不公开,那么客户端可以通过将收到的信息发送至该认证服务器,由该认证服务器通过维护的公钥进行签名验证;然后,认证服务器可以向客户端提供验证结果,该验证结果由认证服务器进行签名,且该验证结果包含认证服务器的证书或者该认证服务器的公钥可以被公开,使得客户端可以验签以确定验证结果的有效性。或者,认证根密钥的公钥可以被公开,使得客户端可以自行基于该公钥对来自FPGA结构的信息进行签名验证,而无需经由认证服务器,这样可以减少签名验证过程所经历的交互环节,从而提升验证效率、降低更多交互环节所导致的安全性风险。An authentication root key may be pre-deployed on the FPGA structure, and the authentication root key may be preset in the FPGA structure, or the authentication root key may be deployed into the FPGA structure by the client or other objects in an offline security environment. The authentication root key is an asymmetric key. Then, in the process of remotely negotiating the above configuration file deployment key between the client and the FPGA structure, the FPGA structure can use the authentication root key to sign the information sent by itself (such as the above key agreement information Kb-2, etc.). The client can verify the signature to determine whether the received information actually comes from the FPGA structure and has not been tampered with during transmission, and the information that has not passed the signature verification will not be trusted and adopted by the client. Among them, the public key of the authentication root key can be managed by the authentication server and not made public, then the client can send the received information to the authentication server, and the authentication server can perform signature verification with the maintained public key; then, the authentication The server can provide the client with the verification result, the verification result is signed by the verification server, and the verification result contains the certificate of the verification server or the public key of the verification server can be made public, so that the client can verify the signature to determine the validity of the verification result Sex. Alternatively, the public key of the authentication root key can be made public, so that the client can perform signature verification on the information from the FPGA structure based on the public key without going through the authentication server, which can reduce the interactive links in the signature verification process. Thereby improving the efficiency of verification and reducing the security risks caused by more interactive links.
上述的认证根密钥可以被基于旧版电路逻辑配置文件部署至FPGA结构。那么,尤其是在旧版电路逻辑配置文件与新版电路逻辑配置文件并非同一用户生成和部署的 情况下,旧版电路逻辑配置文件在烧录至FPGA结构之前可能被其他用户查看或检验,导致旧版电路逻辑配置文件所含的认证根密钥被其他用户获知,存在一定的安全性风险。因此,新版电路逻辑配置文件中可以包含新版认证根密钥,以用于对FPGA结构上已部署的认证根密钥进行更新,确保该新版认证根密钥仅有部署的用户获知,以消除上述的安全性风险。以及,后续可以基于该新版认证根密钥与客户端协商配置文件部署密钥或其他密钥,并且可以确保这些密钥具有足够的安全性。The above authentication root key can be deployed to the FPGA structure based on the old version of the circuit logic configuration file. Then, especially when the old version of the circuit logic configuration file and the new version of the circuit logic configuration file are not generated and deployed by the same user, the old version of the circuit logic configuration file may be viewed or verified by other users before burning to the FPGA structure, resulting in the old version of the circuit logic The authentication root key contained in the configuration file is known to other users, which poses a certain security risk. Therefore, the new version of the circuit logic configuration file can contain the new version of the authentication root key to update the authentication root key deployed on the FPGA structure to ensure that the new version of the authentication root key is only known to the deployed user to eliminate the above Security risks. And, the subsequent configuration file deployment key or other keys can be negotiated with the client based on the new version of the authentication root key, and sufficient security of these keys can be ensured.
FPGA结构可以避免将认证根密钥从相应的电路逻辑配置文件中取出,使得FPGA结构在将该电路逻辑配置文件加载至FPGA芯片后,可以获知相应的认证根密钥。或者,FPGA结构可以包含独立于FPGA芯片的密钥管理芯片,且FPGA结构可以将认证根密钥从所属的电路逻辑配置文件中取出后维护于密钥管理芯片中,使得认证根密钥仅存在于密钥管理芯片中,而不会再出现于FPGA结构上部署的电路逻辑配置文件中,以提升认证根密钥的安全性。The FPGA structure can avoid taking the authentication root key from the corresponding circuit logic configuration file, so that the FPGA structure can obtain the corresponding authentication root key after loading the circuit logic configuration file to the FPGA chip. Alternatively, the FPGA structure can include a key management chip independent of the FPGA chip, and the FPGA structure can take the authentication root key out of the circuit logic configuration file to which it belongs and maintain it in the key management chip, so that only the authentication root key exists In the key management chip, it will no longer appear in the circuit logic configuration file deployed on the FPGA structure to improve the security of the authentication root key.
步骤106,所述FPGA结构基于解密得到的新版电路逻辑配置文件进行更新部署,以使所述FPGA结构实现为所属的区块链节点上的可信执行环境。Step 106: The FPGA structure is updated and deployed based on the new version of the circuit logic configuration file obtained by decryption, so that the FPGA structure is implemented as a trusted execution environment on the blockchain node to which it belongs.
基于旧版电路逻辑配置文件在FPGA芯片上形成的解密模块,以及FPGA结构上维护的上述配置文件部署密钥,使得只有获知该配置文件部署密钥的用户才能够针对FPGA结构上的旧版电路逻辑配置文件进行更新,以确保针对该旧版电路逻辑配置文件所实施的更新操作为可信更新操作。The decryption module formed on the FPGA chip based on the old version of the circuit logic configuration file, and the configuration file deployment key maintained on the FPGA structure, so that only users who know the configuration file deployment key can configure the old version of the circuit logic on the FPGA structure The file is updated to ensure that the update operation implemented for the old version of the circuit logic configuration file is a trusted update operation.
FPGA结构上可以部署有客户端对应的公钥或者预置证书。客户端可以针对新版电路逻辑配置文件进行签名后发送至FPGA结构,使得FPGA结构可以针对收到的新版电路逻辑配置文件进行签名验证,并将签名通过验证作为允许部署该新版电路逻辑配置文件的条件之一。其中,客户端对应的公钥或证书可由旧版电路逻辑配置文件部署于FPGA结构。因此,基于对新版电路逻辑配置文件进行签名验证,可以进一步提升新版电路逻辑配置文件的可信度,以确保对FPGA结构上的电路逻辑配置文件实现可信更新。其中,FPGA结构可以将加密后新版电路逻辑配置文件读入FPGA芯片上的验签模块进行签名验证。与前述解密模块相类似的,该验签模块可由FPGA芯片基于旧版电路逻辑配置文件而形成。The public key or preset certificate corresponding to the client can be deployed on the FPGA structure. The client can sign the new version of the circuit logic configuration file and send it to the FPGA structure, so that the FPGA structure can perform signature verification for the received new version of the circuit logic configuration file, and use the signature verification as a condition for allowing the deployment of the new version of the circuit logic configuration file one. Among them, the public key or certificate corresponding to the client can be deployed in the FPGA structure by the old version of the circuit logic configuration file. Therefore, based on the signature verification of the new version of the circuit logic configuration file, the credibility of the new version of the circuit logic configuration file can be further improved to ensure the credible update of the circuit logic configuration file on the FPGA structure. Among them, the FPGA structure can read the encrypted new version of the circuit logic configuration file into the verification module on the FPGA chip for signature verification. Similar to the aforementioned decryption module, the verification module can be formed by the FPGA chip based on the old version of the circuit logic configuration file.
FPGA结构在部署电路逻辑配置文件时,可以将电路逻辑配置文件直接读取并配置于FPGA芯片内。但是,FPGA芯片具有易失性,断电后部署的电路逻辑配置文件就会丢失,使得重新上电后需要客户端重新部署电路逻辑配置文件。因此,为了减少客户端 的部署次数,FPGA结构可以进一步包含存储器,该存储器与FPGA芯片相连,使得电路逻辑配置文件被部署于存储器中,且FPGA芯片从存储器中读取电路逻辑配置文件以实现相关功能;其中,存储器具有非易失性,即便断电仍然可以保存电路逻辑配置文件,而重新上电后只需重新从存储器读入FPGA芯片即可,无需客户端重新部署。存储器可以具有多种形式,比如闪存等可重复擦写的非易失性存储器,再比如熔丝存储器等不可重复擦写的存储器等,本说明书并不对此进行限制。因此,当旧版电路逻辑配置文件被部署于存储器时,FPGA结构可以基于新版电路逻辑配置文件对该存储器进行更新部署,使得存储器中已部署的旧版电路逻辑配置文件被更新为新版电路逻辑配置文件。When the FPGA structure deploys the circuit logic configuration file, the circuit logic configuration file can be directly read and configured in the FPGA chip. However, the FPGA chip is volatile, and the circuit logic configuration file deployed after the power is off will be lost, so that the client needs to re-deploy the circuit logic configuration file after power on. Therefore, in order to reduce the number of deployments of the client, the FPGA structure can further include a memory, which is connected to the FPGA chip, so that the circuit logic configuration file is deployed in the memory, and the FPGA chip reads the circuit logic configuration file from the memory to implement related functions ; Among them, the memory is non-volatile, even if the power is off, the circuit logic configuration file can still be saved, and after the power is turned on, it is only necessary to read the FPGA chip from the memory again, without the client re-deployment. The memory may have various forms, such as a non-volatile memory that can be re-erasable, such as flash memory, and a non-re-erasable memory, such as a fuse memory, which is not limited in this specification. Therefore, when the old version of the circuit logic configuration file is deployed in the memory, the FPGA structure can update the memory based on the new version of the circuit logic configuration file, so that the old version of the circuit logic configuration file deployed in the memory is updated to the new version of the circuit logic configuration file.
FPGA结构可以针对更新部署的新版电路逻辑配置文件生成认证结果,该认证结果包含与新版电路逻辑配置文件相关的内容。然后,FPGA结构可以基于前述更新部署的新版认证根密钥对认证结果进行签名,并将签名后的认证结果返回客户端。客户端可以针对收到的认证结果进行签名验证,以及客户端可以基于自身维护的新版电路逻辑文件生成相关的内容,那么:在认证结果通过签名验证且认证结果中包含的“与新版电路逻辑配置文件相关的内容”与客户端生成的内容一致的情况下,客户端可以确认新版电路逻辑配置文件在FPGA结构上部署成功。其中,上述与新版电路逻辑配置文件相关的内容可以为新版电路逻辑配置文件的哈希值或该哈希值的衍生值。例如,FPGA结构可以基于新版认证根密钥与客户端重新协商得到新版配置文件部署密钥,而FPGA结构可以分别生成新版电路逻辑配置文件的哈希值、新版配置文件部署密钥的哈希值,并通过诸如sm3算法或其他算法对这两个哈希值进行计算,得到的计算结果可以被作为上述与新版电路逻辑配置文件相关的内容;相应地,基于认证结果可使客户端确定:新版电路逻辑配置文件在FPGA结构上成功部署,且客户端与FPGA结构之间成功协商得到了新版配置文件部署密钥。The FPGA structure can generate an authentication result for the new version of the circuit logic configuration file that is updated and deployed, and the authentication result includes content related to the new version of the circuit logic configuration file. Then, the FPGA structure can sign the authentication result based on the new version of the authentication root key that was updated and deployed, and return the signed authentication result to the client. The client can verify the signature of the received authentication result, and the client can generate related content based on the new version of the circuit logic file maintained by itself, then: the authentication result has passed the signature verification and the authentication result contains the "and the new version of the circuit logic configuration" When the “file-related content” is consistent with the content generated by the client, the client can confirm that the new version of the circuit logic configuration file is successfully deployed on the FPGA structure. Wherein, the foregoing content related to the new version of the circuit logic configuration file may be a hash value of the new version of the circuit logic configuration file or a derivative value of the hash value. For example, the FPGA structure can renegotiate the new version of the configuration file deployment key based on the new version of the authentication root key, and the FPGA structure can generate the hash value of the new version of the circuit logic configuration file and the hash value of the new version of the configuration file deployment key. , And calculate the two hash values through algorithms such as sm3 or other algorithms, and the calculated result can be used as the content related to the new version of the circuit logic configuration file; accordingly, the client can determine based on the authentication result: the new version The circuit logic configuration file was successfully deployed on the FPGA structure, and the new version of the configuration file deployment key was successfully negotiated between the client and the FPGA structure.
图2是一示例性实施例提供的一种区块链节点的结构示意图。基于本说明书的技术方案,可以在区块链节点上添加FPGA结构以实现硬件TEE,譬如该FPGA结构可以为如图2所示的FPGA板卡。FPGA板卡可以通过PCIE接口连接至区块链节点上,以实现FPGA板卡与区块链节点之间的数据交互。FPGA板卡可以包括FPGA芯片、Flash(闪存)芯片和密管芯片等结构;当然,在一些实施例中除了包含FPGA芯片之外,可能仅包含剩余的Flash芯片和密管芯片等中的部分结构,或者可能包含更多结构,此处仅用于举例。Fig. 2 is a schematic structural diagram of a blockchain node provided by an exemplary embodiment. Based on the technical solution in this specification, an FPGA structure can be added to the blockchain node to implement hardware TEE. For example, the FPGA structure can be an FPGA board as shown in FIG. 2. The FPGA board can be connected to the blockchain node through the PCIE interface to realize the data interaction between the FPGA board and the blockchain node. FPGA boards can include FPGA chips, Flash (flash memory) chips, and dense tube chips; of course, in addition to FPGA chips in some embodiments, they may only include parts of the remaining Flash chips and dense tube chips. , Or may contain more structures, here are just examples.
在初始阶段,FPGA芯片上并未烧录用户定义的任何逻辑,相当于FPGA芯片处于 空白状态。用户可以通过向FPGA芯片上烧录电路逻辑配置文件,以在FPGA芯片上形成相应的功能或逻辑。在首次烧录电路逻辑配置文件时,FPGA板卡不具有安全防护的能力,因而通常需要外部提供安全环境,比如用户可以在离线环境下实施对电路逻辑配置文件的烧录以实现物理安全隔离,而非在线上实施远程烧录。In the initial stage, no user-defined logic is programmed on the FPGA chip, which is equivalent to the FPGA chip in a blank state. Users can burn circuit logic configuration files on the FPGA chip to form corresponding functions or logic on the FPGA chip. When programming the circuit logic configuration file for the first time, the FPGA board does not have the capability of security protection, so it usually needs to provide an external security environment. For example, users can implement the programming of the circuit logic configuration file in an offline environment to achieve physical security isolation. Instead of implementing remote programming online.
针对用户所需实现的功能或逻辑,可以通过FPGA硬件语言形成相应的逻辑代码,并进而对该逻辑代码进行镜像化处理,即可得到上述的电路逻辑配置文件。在烧录至FPGA板卡之前,用户可以针对上述的逻辑代码进行检查。尤其是,当同时涉及到多个用户时,多个用户可以分别对上述的逻辑代码进行检查,以确保FPGA板卡最终能够满足所有用户的需求,防止出现安全性风险、逻辑错误、欺诈等异常问题。For the function or logic that the user needs to implement, the corresponding logic code can be formed through FPGA hardware language, and then the logic code can be mirrored to obtain the above-mentioned circuit logic configuration file. Before programming to the FPGA board, the user can check the above-mentioned logic code. Especially, when multiple users are involved at the same time, multiple users can check the above logic code separately to ensure that the FPGA board can finally meet the needs of all users and prevent security risks, logic errors, fraud and other abnormalities. problem.
在确定代码无误后,用户可以在上述的离线环境下,将电路逻辑配置文件烧录至FPGA板卡上。具体的,电路逻辑配置文件被从区块链节点传入FPGA板卡,进而部署至如图2所示的Flash芯片中,使得即便FPGA板卡发生掉电,Flash芯片仍然能够保存上述的电路逻辑配置文件。After confirming that the code is correct, the user can burn the circuit logic configuration file to the FPGA board in the above-mentioned offline environment. Specifically, the circuit logic configuration file is transferred from the blockchain node to the FPGA board, and then deployed to the Flash chip as shown in Figure 2, so that even if the FPGA board is powered off, the Flash chip can still save the above-mentioned circuit logic. Configuration file.
图3是一示例性实施例提供的一种在FPGA芯片上形成功能模块的示意图。通过将Flash芯片中所部署的电路逻辑配置文件加载至FPGA芯片,可以对FPGA芯片所含的硬件逻辑单元进行配置,从而在FPGA芯片上形成相应的功能模块,譬如所形成的功能模块可以包括如图3所示的密钥协商模块、解密验签模块、加解密模块、明文计算模块等。同时,电路逻辑配置文件还可以用于向FPGA板卡传输需要存储的信息,比如可以将预置证书存储于FPGA芯片上、将认证根密钥存储于密管芯片中(认证根密钥也可以存储于FPGA芯片上)等。Fig. 3 is a schematic diagram of forming a functional module on an FPGA chip provided by an exemplary embodiment. By loading the circuit logic configuration file deployed in the Flash chip to the FPGA chip, the hardware logic unit contained in the FPGA chip can be configured to form corresponding functional modules on the FPGA chip. For example, the formed functional modules can include such The key agreement module, decryption verification module, encryption and decryption module, plaintext calculation module, etc. shown in FIG. 3. At the same time, the circuit logic configuration file can also be used to transmit the information that needs to be stored to the FPGA board. For example, the preset certificate can be stored on the FPGA chip, and the authentication root key can be stored in the secret tube chip (the authentication root key can also be Stored on the FPGA chip) and so on.
基于FPGA芯片上所形成的密钥协商模块,以及部署于FPGA板卡上的认证根密钥,使得FPGA板卡可以与用户实现远程的密钥协商,该密钥协商过程可以采用相关技术中的任意算法或标准来实现,本说明书并不对此进行限制。举例而言,密钥协商过程可以包括:用户可以在本地的客户端生成一密钥Ka-1、密钥协商模块可以在本地生成一密钥Kb-1,且客户端可以基于密钥Ka-1计算得到密钥协商信息Ka-2、密钥协商模块可以基于密钥Kb-1计算得到密钥协商信息Kb-2,然后客户端将密钥协商信息Ka-2发送至密钥协商模块、密钥协商模块将密钥协商信息Kb-2发送至客户端,使得客户端可以基于密钥Ka-1与密钥协商信息Kb-2生成一秘密值,而密钥协商模块可以基于密钥Kb-1与密钥协商信息Ka-2生成相同的秘密值,最后由客户端、密钥协商模块分别基于密钥导出函数从该相同的秘密值导出相同的配置文件部署密钥,该配置文件部署密钥可以存 在FPGA芯片或密管芯片。在上述过程中,虽然密钥协商信息Ka-2、密钥协商信息Kb-2是经由区块链节点在客户端与密钥协商模块之间传输,但是由于密钥Ka-1由客户端掌握、密钥Kb-1由密钥协商模块掌握,因而可以确保区块链节点无法获知最终得到的秘密值和配置文件部署密钥,避免可能造成的安全性风险。Based on the key agreement module formed on the FPGA chip and the authentication root key deployed on the FPGA board, the FPGA board can realize remote key agreement with the user. The key agreement process can use related technologies. Any algorithm or standard can be implemented, and this specification does not limit it. For example, the key agreement process can include: the user can generate a key Ka-1 at the local client, the key agreement module can generate a key Kb-1 locally, and the client can generate a key Kb-1 based on the key Ka- 1 Calculate the key agreement information Ka-2, the key agreement module can calculate the key agreement information Kb-2 based on the key Kb-1, and then the client sends the key agreement information Ka-2 to the key agreement module, The key agreement module sends the key agreement information Kb-2 to the client, so that the client can generate a secret value based on the key Ka-1 and the key agreement information Kb-2, and the key agreement module can be based on the key Kb -1 generates the same secret value as the key agreement information Ka-2, and finally the client and the key agreement module respectively derive the same configuration file deployment key from the same secret value based on the key derivation function, and the configuration file deployment The key can be stored in the FPGA chip or the secret management chip. In the above process, although the key agreement information Ka-2 and key agreement information Kb-2 are transmitted between the client and the key agreement module via the blockchain node, the key Ka-1 is controlled by the client , The key Kb-1 is controlled by the key agreement module, so it can ensure that the blockchain node cannot know the final secret value and the configuration file deployment key, so as to avoid possible security risks.
除了配置文件部署密钥之外,秘密值还用于导出业务秘密部署密钥;例如,秘密值可以导出32位数值,可以将前16位作为配置文件部署密钥、后16位作为业务秘密部署密钥。用户可以通过业务秘密部署密钥向FPGA板卡部署业务密钥,譬如该业务密钥可以包括节点私钥和业务根密钥。例如,用户可以在客户端上采用业务秘密部署密钥对节点私钥或业务根密钥进行签名、加密并发送至FPGA板卡,使得FPGA板卡通过解密验签模块进行解密、验签后,对得到的节点私钥或业务根密钥进行部署。In addition to the configuration file deployment key, the secret value is also used to derive the business secret deployment key; for example, the secret value can be derived as a 32-bit value, the first 16 bits can be used as the configuration file deployment key, and the last 16 bits can be used as the business secret deployment Key. The user can deploy the service key to the FPGA board through the service secret deployment key. For example, the service key may include the node private key and the service root key. For example, the user can use the business secret deployment key on the client to sign, encrypt the node private key or the business root key, and send it to the FPGA board, so that after the FPGA board is decrypted and verified through the decryption verification module, Deploy the obtained node private key or service root key.
基于部署的节点密钥、业务根密钥和FPGA芯片上的加解密模块、明文计算模块,使得FPGA板卡可以实现为区块链节点上的TEE,以满足隐私需求。例如,当区块链节点收到一笔交易时,如果该交易为明文交易,区块链节点可以直接处理该明文交易,如果该交易为隐私交易,区块链节点将该隐私交易传入FPGA板卡进行处理。Based on the deployed node key, service root key, encryption and decryption module and plaintext calculation module on the FPGA chip, the FPGA board can be implemented as a TEE on the blockchain node to meet privacy requirements. For example, when a blockchain node receives a transaction, if the transaction is a plaintext transaction, the blockchain node can directly process the plaintext transaction, if the transaction is a private transaction, the blockchain node transmits the private transaction to the FPGA The board is processed.
明文交易的交易内容为明文形式,并且交易执行后所产生的合约状态等同样采用明文形式进行存储。隐私交易的交易内容为密文形式,由交易发起方对明文交易内容进行加密而得到,且交易执行后产生的合约状态等需要采用密文形式进行存储,从而确保交易隐私保护。例如,交易发起方可以随机或基于其他方式生成一对称密钥,同样上述的业务私钥对应的业务公钥被公开,那么交易发起方可以基于该对称密钥和业务公钥对明文交易内容进行数字信封加密:交易发起方通过对称密钥加密明文交易内容,并通过业务公钥对该对称密钥进行加密,得到的两部分内容均被包含于上述的隐私交易中;换言之,隐私交易中包含两部分内容:采用对称密钥加密的明文交易内容、采用业务公钥加密的对称密钥。The transaction content of a plaintext transaction is in plaintext form, and the contract status generated after the transaction is executed is also stored in plaintext form. The transaction content of a private transaction is in the form of cipher text, which is obtained by encrypting the content of the transaction in plain text by the transaction initiator, and the contract state generated after the transaction is executed needs to be stored in the form of cipher text to ensure the protection of transaction privacy. For example, the transaction initiator can generate a symmetric key randomly or based on other methods. Similarly, the business public key corresponding to the above-mentioned business private key is disclosed, then the transaction initiator can perform transaction content in plaintext based on the symmetric key and the business public key. Digital Envelope Encryption: The transaction initiator encrypts the plaintext transaction content with a symmetric key, and encrypts the symmetric key with the business public key. The two parts obtained are included in the above-mentioned private transaction; in other words, the private transaction includes Two parts of content: the content of the transaction in plaintext encrypted with a symmetric key, and the symmetric key encrypted with the business public key.
因此,FPGA板卡在收到区块链节点传入的隐私交易后,可由加解密模块通过业务私钥对采用业务公钥加密的对称密钥进行解密、得到对称密钥,然后由加解密模块通过对称密钥对采用对称密钥加密的明文交易内容进行解密、得到明文交易内容。隐私交易可以用于部署智能合约,那么明文交易内容的data字段可以包含待部署的智能合约的合约代码;或者,隐私交易可以用于调用智能合约,那么明文交易内容的to字段可以包含被调用的智能合约的合约地址,而FPGA板卡可以基于该合约地址调取相应的合约代码。Therefore, after the FPGA board receives the private transaction from the blockchain node, the encryption and decryption module can use the business private key to decrypt the symmetric key encrypted with the business public key to obtain the symmetric key, and then the encryption and decryption module The symmetric key is used to decrypt the plaintext transaction content encrypted with the symmetric key to obtain the plaintext transaction content. Private transactions can be used to deploy smart contracts, then the data field of the plaintext transaction content can contain the contract code of the smart contract to be deployed; or, the privacy transaction can be used to call the smart contract, then the to field of the plaintext transaction content can contain the called The contract address of the smart contract, and the FPGA board can retrieve the corresponding contract code based on the contract address.
FPGA芯片上形成的明文计算模块用于实现相关技术中的虚拟机逻辑,即明文计算 模块相当于FPGA板卡上的“硬件虚拟机”。因此,基于上述明文交易内容确定出合约代码后,可以将该合约代码传入明文计算模块中,以由该明文计算模块执行该合约代码。执行完毕后,合约代码所涉及的合约状态可能发生更新。如果合约状态需要存储至FPGA芯片之外,那么可由加解密模块通过前述的业务根密钥或其衍生密钥对发生更新的合约状态进行加密,并对加密后合约状态进行存储,以确保与隐私交易相关的数据仅在FPGA芯片内处于明文状态、在FPGA芯片之外均处于密文状态,从而保证数据的安全性。The plaintext calculation module formed on the FPGA chip is used to implement virtual machine logic in related technologies, that is, the plaintext calculation module is equivalent to the "hardware virtual machine" on the FPGA board. Therefore, after the contract code is determined based on the foregoing plaintext transaction content, the contract code can be passed into the plaintext calculation module, so that the plaintext calculation module executes the contract code. After the execution is completed, the state of the contract involved in the contract code may be updated. If the contract state needs to be stored outside the FPGA chip, the encryption and decryption module can encrypt the updated contract state through the aforementioned business root key or its derivative key, and store the encrypted contract state to ensure privacy The transaction-related data is only in the clear text state in the FPGA chip and in the cipher text state outside the FPGA chip, so as to ensure the security of the data.
基于一些原因,用户可能希望对FPGA板卡上部署的电路逻辑配置文件进行版本更新,比如该电路逻辑配置文件所含的认证根密钥可能被风险用户获知、再比如用户希望对FPGA板卡上部署的功能模块进行升级等,本说明书并不对此进行限制。为了便于区分,可以将上述过程中已部署的电路逻辑配置文件称之为旧版电路逻辑配置文件,而将需要部署的电路逻辑配置文件称之为新版电路逻辑配置文件。For some reasons, the user may want to update the version of the circuit logic configuration file deployed on the FPGA board. For example, the authentication root key contained in the circuit logic configuration file may be known by risky users, or the user wants to update the version on the FPGA board. The deployed functional modules are upgraded, etc. This manual does not limit this. In order to facilitate the distinction, the circuit logic configuration file that has been deployed in the above process can be referred to as the old version of the circuit logic configuration file, and the circuit logic configuration file that needs to be deployed is referred to as the new version of the circuit logic configuration file.
与旧版电路逻辑配置文件相类似的,用户可以通过编写代码、镜像化等过程生成新版电路逻辑配置文件。进一步的,用户可以通过自身持有的私钥对新版电路逻辑配置文件进行签名,然后通过上文协商出的配置文件部署密钥对签名后的新版电路逻辑配置文件进行加密,得到加密后新版电路逻辑配置文件。在一些情况下,可能同时存在多名用户,那么旧版电路逻辑配置文件需要将这些用户对应的预置证书均部署至FPGA板卡中,且这些用户需要分别采用自身持有的私钥对新版电路逻辑配置文件进行签名。Similar to the old version of the circuit logic configuration file, the user can generate a new version of the circuit logic configuration file through the process of writing code and mirroring. Further, the user can sign the new version of the circuit logic configuration file with his own private key, and then encrypt the signed new version of the circuit logic configuration file with the configuration file deployment key negotiated above to obtain the encrypted new version of the circuit Logical configuration file. In some cases, there may be multiple users at the same time, so the old version of the circuit logic configuration file needs to deploy the preset certificates corresponding to these users to the FPGA board, and these users need to use their own private keys to pair the new version of the circuit. Sign the logical configuration file.
用户可以通过客户端远程将加密后新版电路逻辑配置文件发送至区块链节点,并由区块链节点进一步将其传入FPGA板卡。图4是一示例性实施例提供的一种对FPGA板卡进行可新更新的示意图。如图4所示,前述过程中在FPGA芯片上形成的解密验签模块位于PCIE接口与Flash芯片之间的传输通路上,使得加密后新版电路逻辑配置文件必然需要优先经过解密验签模块的成功处理后,才能够被传入Flash芯片以实现可信更新,无法绕过解密验签的过程而直接对Flash芯片进行更新。The user can remotely send the encrypted new version of the circuit logic configuration file to the blockchain node through the client, and the blockchain node will further transfer it to the FPGA board. Fig. 4 is a schematic diagram of newly updateable FPGA board provided by an exemplary embodiment. As shown in Figure 4, the decryption verification module formed on the FPGA chip in the foregoing process is located on the transmission path between the PCIE interface and the Flash chip, so that the new version of the circuit logic configuration file after encryption must first pass the decryption verification module. After processing, it can be transferred to the Flash chip to achieve a credible update, and the Flash chip cannot be updated directly without bypassing the decryption and verification process.
解密验签模块在收到加密后新版电路逻辑配置文件后,首先通过FPGA板卡上部署的配置文件部署密钥进行解密,如果解密成功则解密验签模块进一步基于FPGA芯片上部署的预置证书,对解密后的新版电路逻辑配置文件进行签名验证。如果解密失败或者签名验证未通过,则说明收到的文件并非来自上述用户或者遭到篡改,解密验签模块将触发终止本次的更新操作;而在解密成功且验签通过的情况下,可以确定得到的新版电路逻辑配置文件来自上述用户且传输过程中未遭到篡改,可以将该新版电路逻辑配置文件进一步传输至Flash芯片,以针对Flash芯片中的旧版电路逻辑配置文件进行更新 部署。After the decryption verification module receives the encrypted new version of the circuit logic configuration file, it first decrypts it with the configuration file deployment key deployed on the FPGA board. If the decryption is successful, the decryption verification module is further based on the preset certificate deployed on the FPGA chip , To perform signature verification on the decrypted new version of the circuit logic configuration file. If the decryption fails or the signature verification fails, it means that the received file is not from the above-mentioned user or has been tampered with, and the decryption and signature verification module will trigger the termination of the update operation; and if the decryption is successful and the signature verification is passed, you can It is determined that the obtained new version of the circuit logic configuration file is from the aforementioned user and has not been tampered with during the transmission process. The new version of the circuit logic configuration file can be further transmitted to the Flash chip to update and deploy the old version of the circuit logic configuration file in the Flash chip.
新版电路逻辑配置文件被加载至FPGA芯片后,同样可以在该FPGA芯片上形成诸如上述的密钥协商模块、解密验签模块,以及向FPGA芯片存入预置证书、向密管芯片存入认证根密钥等信息。其中,所形成的密钥协商模块、解密验签模块等,所实现的功能逻辑可以发生变化和升级,所存入部署的预置证书、认证根密钥等信息也可能区别于更新前的信息。那么,FPGA板卡可以基于更新后的密钥协商模块、认证根密钥等,与用户进行远程协商得到新的配置文件部署密钥,该配置文件部署密钥可以被用于下一次的可新更新过程。类似地,可以据此不断实现针对FPGA板卡的可信更新操作。After the new version of the circuit logic configuration file is loaded into the FPGA chip, the above-mentioned key agreement module, decryption and verification module can also be formed on the FPGA chip, and the pre-set certificate and authentication can be stored in the FPGA chip. Root key and other information. Among them, the formed key agreement module, decryption verification module, etc., the implemented functional logic can be changed and upgraded, and the information stored in the deployed preset certificate, authentication root key and other information may also be different from the information before the update . Then, the FPGA board can remotely negotiate with the user to obtain a new configuration file deployment key based on the updated key agreement module, authentication root key, etc., and the configuration file deployment key can be used for the next renewal Update process. Similarly, a reliable update operation for FPGA boards can be continuously implemented accordingly.
在完成更新部署后,FPGA板卡可以针对新版电路逻辑配置文件生成认证结果。例如,上述的密钥协商模块可以通过诸如sm3算法或其他算法对新版电路逻辑配置文件的哈希值、基于新版电路逻辑配置文件协商得到的配置文件部署密钥的哈希值进行计算,得到的计算结果可以被作为上述的认证结果,并由密钥协商模块将该认证结果发送至用户。相应地,用户可以在客户端上基于所维护的新版电路逻辑配置文件和据此协商的配置文件部署密钥对认证结果进行验证,如果验证成功则表明新版电路逻辑配置文件在FPGA板卡上成功部署,且用户与FPGA板卡之间据此成功协商得到了一致的配置文件部署密钥,从而确认成功完成了针对电路逻辑配置文件的更新部署。After completing the update deployment, the FPGA board can generate certification results for the new version of the circuit logic configuration file. For example, the above-mentioned key agreement module can calculate the hash value of the new version of the circuit logic configuration file and the hash value of the configuration file deployment key negotiated based on the new version of the circuit logic configuration file through an algorithm such as sm3 or other algorithms. The calculation result can be used as the above-mentioned authentication result, and the key agreement module sends the authentication result to the user. Correspondingly, the user can verify the authentication result on the client based on the maintained new version of the circuit logic configuration file and the configuration file deployment key negotiated accordingly. If the verification is successful, it indicates that the new version of the circuit logic configuration file is successful on the FPGA board. Deployed, and the user and the FPGA board successfully negotiated accordingly to obtain a consistent configuration file deployment key, thereby confirming the successful completion of the circuit logic configuration file update deployment.
图5是一示例性实施例提供的一种FPGA逻辑的可信更新装置的示意结构图。请参考图5,在软件实施方式中,该FPGA逻辑的可信更新装置可以包括:接收单元501,使FPGA结构接收来自客户端的加密后新版电路逻辑配置文件,所述FPGA结构包含FPGA芯片;解密单元502,使所述FPGA结构将所述加密后新版电路逻辑配置文件读入所述FPGA芯片上的解密模块进行解密,所述解密模块由所述FPGA芯片基于所述FPGA结构上已部署的旧版电路逻辑配置文件而形成;更新单元503,使所述FPGA结构基于解密得到的新版电路逻辑配置文件进行更新部署,以使所述FPGA结构实现为所属的区块链节点上的可信执行环境。Fig. 5 is a schematic structural diagram of a trusted update device for FPGA logic provided by an exemplary embodiment. Referring to FIG. 5, in the software implementation, the trusted update device for FPGA logic may include: a receiving unit 501, which enables the FPGA structure to receive the encrypted new version of the circuit logic configuration file from the client, and the FPGA structure includes the FPGA chip; Unit 502, enabling the FPGA structure to read the encrypted new version of the circuit logic configuration file into the decryption module on the FPGA chip for decryption. The decryption module is based on the FPGA chip based on the old version deployed on the FPGA structure. The circuit logic configuration file is formed; the update unit 503 enables the FPGA structure to be updated and deployed based on the new version of the circuit logic configuration file obtained by decryption, so that the FPGA structure is implemented as a trusted execution environment on the blockchain node to which it belongs.
可选的,还包括:协商单元504,使所述FPGA结构基于已部署的认证根密钥与所述客户端进行远程协商,以协商得到配置文件部署密钥;其中,所述加密后新版电路逻辑配置文件被所述FPGA结构基于所述配置文件部署密钥在所述解密模块中进行解密。Optionally, it further includes: a negotiation unit 504, which enables the FPGA structure to perform remote negotiation with the client based on the deployed authentication root key to negotiate a configuration file deployment key; wherein, the encrypted new version of the circuit The logic configuration file is decrypted in the decryption module by the FPGA structure based on the configuration file deployment key.
可选的,所述已部署的认证根密钥被基于所述旧版电路逻辑配置文件部署至所述FPGA结构。Optionally, the deployed authentication root key is deployed to the FPGA structure based on the old version of the circuit logic configuration file.
可选的,所述已部署的认证根密钥被维护于所述FPGA结构包含的密钥管理芯片中。Optionally, the deployed authentication root key is maintained in a key management chip included in the FPGA structure.
可选的,所述新版电路逻辑配置文件中包括:新版认证根密钥,以用于对所述已部署的认证根密钥进行更新。Optionally, the new version of the circuit logic configuration file includes: a new version of the authentication root key for updating the deployed authentication root key.
可选的,还包括:签名单元505,使所述FPGA结构通过所述新版认证根密钥对认证结果进行签名,所述认证结果包含与所述新版电路逻辑配置文件相关的内容;返回单元506,使所述FPGA结构将签名后的所述认证结果返回所述客户端,以使所述客户端在所述认证结果通过签名验证且所述认证结果包含与所述新版电路逻辑配置文件相关的内容的情况下,确认所述新版电路逻辑配置文件在所述FPGA结构上部署成功。Optionally, it further includes: a signing unit 505 for enabling the FPGA structure to sign the authentication result through the new version of the authentication root key, the authentication result including content related to the new version of the circuit logic configuration file; a returning unit 506 , Enabling the FPGA structure to return the signed authentication result to the client, so that the client passes the signature verification on the authentication result and the authentication result contains information related to the new version of the circuit logic configuration file In the case of content, it is confirmed that the new version of the circuit logic configuration file is successfully deployed on the FPGA structure.
可选的,还包括:验证单元507,使所述FPGA结构将所述加密后新版电路逻辑配置文件读入所述FPGA芯片上的验签模块进行签名验证,所述验签模块由所述FPGA芯片基于所述旧版电路逻辑配置文件而形成,且所述FPGA结构上已部署所述客户端对应的预置证书;所述更新单元503具体用于:使所述FPGA结构在签名验证成功的情况下,基于所述新版电路逻辑配置文件进行更新部署。Optionally, it further includes: a verification unit 507 that enables the FPGA structure to read the encrypted new version of the circuit logic configuration file into the verification module on the FPGA chip for signature verification, and the verification module is used by the FPGA The chip is formed based on the old version of the circuit logic configuration file, and the preset certificate corresponding to the client has been deployed on the FPGA structure; the update unit 503 is specifically configured to: enable the FPGA structure to successfully verify the signature Next, update deployment based on the new version of the circuit logic configuration file.
可选的,所述FPGA结构还包含所述FPGA芯片之外的存储器;所述更新单元503具体用于:使所述FPGA结构基于所述新版电路逻辑配置文件对所述存储器进行更新部署。Optionally, the FPGA structure further includes a memory other than the FPGA chip; the update unit 503 is specifically configured to: enable the FPGA structure to update and deploy the memory based on the new version of the circuit logic configuration file.
上述实施例阐明的***、装置、模块或单元,具体可以由计算机芯片或实体实现,或者由具有某种功能的产品来实现。一种典型的实现设备为计算机,计算机的具体形式可以是个人计算机、膝上型计算机、蜂窝电话、相机电话、智能电话、个人数字助理、媒体播放器、导航设备、电子邮件收发设备、游戏控制台、平板计算机、可穿戴设备或者这些设备中的任意几种设备的组合。The systems, devices, modules, or units explained in the above embodiments may be implemented by computer chips or entities, or implemented by products with certain functions. A typical implementation device is a computer. The specific form of the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email receiving and sending device, and a game control A console, a tablet computer, a wearable device, or a combination of any of these devices.
在一个典型的配置中,计算机包括一个或多个处理器(CPU)、输入/输出接口、网络接口和内存。In a typical configuration, the computer includes one or more processors (CPU), input/output interfaces, network interfaces, and memory.
内存可能包括计算机可读介质中的非永久性存储器,随机存取存储器(RAM)和/或非易失性内存等形式,如只读存储器(ROM)或闪存(flash RAM)。内存是计算机可读介质的示例。The memory may include non-permanent memory in a computer readable medium, random access memory (RAM) and/or non-volatile memory, such as read-only memory (ROM) or flash memory (flash RAM). Memory is an example of computer readable media.
计算机可读介质包括永久性和非永久性、可移动和非可移动媒体可以由任何方法或技术来实现信息存储。信息可以是计算机可读指令、数据结构、程序的模块或其他数据。计算机的存储介质的例子包括,但不限于相变内存(PRAM)、静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)、其他类型的随机存取存储器(RAM)、 只读存储器(ROM)、电可擦除可编程只读存储器(EEPROM)、快闪记忆体或其他内存技术、只读光盘只读存储器(CD-ROM)、数字多功能光盘(DVD)或其他光学存储、磁盒式磁带、磁盘存储、量子存储器、基于石墨烯的存储介质或其他磁性存储设备或任何其他非传输介质,可用于存储可以被计算设备访问的信息。按照本文中的界定,计算机可读介质不包括暂存电脑可读媒体(transitory media),如调制的数据信号和载波。Computer-readable media include permanent and non-permanent, removable and non-removable media, and information storage can be realized by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disc (DVD) or other optical storage, Magnetic cassettes, disk storage, quantum memory, graphene-based storage media or other magnetic storage devices or any other non-transmission media can be used to store information that can be accessed by computing devices. According to the definition in this article, computer-readable media does not include transitory media, such as modulated data signals and carrier waves.
还需要说明的是,术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。It should also be noted that the terms "include", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or equipment including a series of elements not only includes those elements, but also includes Other elements that are not explicitly listed, or they also include elements inherent to such processes, methods, commodities, or equipment. If there are no more restrictions, the element defined by the sentence "including a..." does not exclude the existence of other identical elements in the process, method, commodity, or equipment that includes the element.
上述对本说明书特定实施例进行了描述。其它实施例在所附权利要求书的范围内。在一些情况下,在权利要求书中记载的动作或步骤可以按照不同于实施例中的顺序来执行并且仍然可以实现期望的结果。另外,在附图中描绘的过程不一定要求示出的特定顺序或者连续顺序才能实现期望的结果。在某些实施方式中,多任务处理和并行处理也是可以的或者可能是有利的。The foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims may be performed in a different order than in the embodiments and still achieve desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown in order to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
在本说明书一个或多个实施例使用的术语是仅仅出于描述特定实施例的目的,而非旨在限制本说明书一个或多个实施例。在本说明书一个或多个实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式,除非上下文清楚地表示其他含义。还应当理解,本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。The terms used in one or more embodiments of this specification are only for the purpose of describing specific embodiments, and are not intended to limit one or more embodiments of this specification. The singular forms "a", "said" and "the" used in one or more embodiments of this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and/or" as used herein refers to and includes any or all possible combinations of one or more associated listed items.
应当理解,尽管在本说明书一个或多个实施例可能采用术语第一、第二、第三等来描述各种信息,但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如,在不脱离本说明书一个或多个实施例范围的情况下,第一信息也可以被称为第二信息,类似地,第二信息也可以被称为第一信息。取决于语境,如在此所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。It should be understood that, although the terms first, second, third, etc. may be used to describe various information in one or more embodiments of this specification, the information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of one or more embodiments of this specification, the first information may also be referred to as second information, and similarly, the second information may also be referred to as first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "when" or "in response to determination".
以上所述仅为本说明书一个或多个实施例的较佳实施例而已,并不用以限制本说明书一个或多个实施例,凡在本说明书一个或多个实施例的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本说明书一个或多个实施例保护的范围之内。The foregoing descriptions are only preferred embodiments of one or more embodiments of this specification, and are not intended to limit one or more embodiments of this specification. All within the spirit and principle of one or more embodiments of this specification, Any modification, equivalent replacement, improvement, etc. made should be included in the protection scope of one or more embodiments of this specification.
Claims (11)
- 一种FPGA逻辑的可信更新方法,包括:A trusted update method of FPGA logic includes:FPGA结构接收来自客户端的加密后新版电路逻辑配置文件,所述FPGA结构包含FPGA芯片;The FPGA structure receives the encrypted new version of the circuit logic configuration file from the client, where the FPGA structure includes the FPGA chip;所述FPGA结构将所述加密后新版电路逻辑配置文件读入所述FPGA芯片上的解密模块进行解密,所述解密模块由所述FPGA芯片基于所述FPGA结构上已部署的旧版电路逻辑配置文件而形成;The FPGA structure reads the encrypted new version of the circuit logic configuration file into the decryption module on the FPGA chip for decryption, and the decryption module is based on the old version of the circuit logic configuration file deployed on the FPGA structure by the FPGA chip. To form所述FPGA结构基于解密得到的新版电路逻辑配置文件进行更新部署,以使所述FPGA结构实现为所属的区块链节点上的可信执行环境。The FPGA structure is updated and deployed based on the new version of the circuit logic configuration file obtained by decryption, so that the FPGA structure is implemented as a trusted execution environment on the blockchain node to which it belongs.
- 根据权利要求1所述的方法,还包括:The method according to claim 1, further comprising:所述FPGA结构基于已部署的认证根密钥与所述客户端进行远程协商,以协商得到配置文件部署密钥;The FPGA structure performs remote negotiation with the client based on the deployed authentication root key to obtain the configuration file deployment key through negotiation;其中,所述加密后新版电路逻辑配置文件被所述FPGA结构基于所述配置文件部署密钥在所述解密模块中进行解密。Wherein, the encrypted new version of the circuit logic configuration file is decrypted in the decryption module by the FPGA structure based on the configuration file deployment key.
- 根据权利要求2所述的方法,所述已部署的认证根密钥被基于所述旧版电路逻辑配置文件部署至所述FPGA结构。According to the method of claim 2, the deployed authentication root key is deployed to the FPGA structure based on the old version of the circuit logic configuration file.
- 根据权利要求2所述的方法,所述已部署的认证根密钥被维护于所述FPGA结构包含的密钥管理芯片中。According to the method of claim 2, the deployed authentication root key is maintained in a key management chip included in the FPGA structure.
- 根据权利要求2所述的方法,所述新版电路逻辑配置文件中包括:新版认证根密钥,以用于对所述已部署的认证根密钥进行更新。The method according to claim 2, wherein the new version of the circuit logic configuration file includes: a new version of the authentication root key for updating the deployed authentication root key.
- 根据权利要求5所述的方法,还包括:The method according to claim 5, further comprising:所述FPGA结构通过所述新版认证根密钥对认证结果进行签名,所述认证结果包含与所述新版电路逻辑配置文件相关的内容;The FPGA structure signs an authentication result through the new version of the authentication root key, and the authentication result includes content related to the new version of the circuit logic configuration file;所述FPGA结构将签名后的所述认证结果返回所述客户端,以使所述客户端在所述认证结果通过签名验证且所述认证结果包含与所述新版电路逻辑配置文件相关的内容的情况下,确认所述新版电路逻辑配置文件在所述FPGA结构上部署成功。The FPGA structure returns the signed authentication result to the client, so that the client passes the signature verification on the authentication result and the authentication result contains content related to the new version of the circuit logic configuration file In this case, it is confirmed that the new version of the circuit logic configuration file is successfully deployed on the FPGA structure.
- 根据权利要求1所述的方法,According to the method of claim 1,还包括:所述FPGA结构将所述加密后新版电路逻辑配置文件读入所述FPGA芯片上的验签模块进行签名验证,所述验签模块由所述FPGA芯片基于所述旧版电路逻辑配置文件而形成,且所述FPGA结构上已部署所述客户端对应的预置证书;It also includes: the FPGA structure reads the encrypted new version of the circuit logic configuration file into the verification module on the FPGA chip for signature verification, and the verification module is based on the old version of the circuit logic configuration file by the FPGA chip Formed, and the preset certificate corresponding to the client has been deployed on the FPGA structure;所述FPGA结构基于解密得到的新版电路逻辑配置文件进行更新部署,包括:所述 FPGA结构在签名验证成功的情况下,基于所述新版电路逻辑配置文件进行更新部署。The FPGA structure is updated and deployed based on the new version of the circuit logic configuration file obtained by decryption, including: in the case of successful signature verification, the FPGA structure is updated and deployed based on the new version of the circuit logic configuration file.
- 根据权利要求1所述的方法,所述FPGA结构还包含所述FPGA芯片之外的存储器;所述FPGA结构基于解密得到的新版电路逻辑配置文件进行更新部署,包括:The method according to claim 1, wherein the FPGA structure further includes a memory outside the FPGA chip; the FPGA structure is updated and deployed based on the new version of the circuit logic configuration file obtained by decryption, including:所述FPGA结构基于所述新版电路逻辑配置文件对所述存储器进行更新部署。The FPGA structure updates and deploys the memory based on the new version of the circuit logic configuration file.
- 一种FPGA逻辑的可信更新装置,包括:A trusted update device for FPGA logic includes:接收单元,使FPGA结构接收来自客户端的加密后新版电路逻辑配置文件,所述FPGA结构包含FPGA芯片;A receiving unit, enabling the FPGA structure to receive the encrypted new version of the circuit logic configuration file from the client, where the FPGA structure includes the FPGA chip;解密单元,使所述FPGA结构将所述加密后新版电路逻辑配置文件读入所述FPGA芯片上的解密模块进行解密,所述解密模块由所述FPGA芯片基于所述FPGA结构上已部署的旧版电路逻辑配置文件而形成;The decryption unit causes the FPGA structure to read the encrypted new version of the circuit logic configuration file into the decryption module on the FPGA chip for decryption, and the decryption module is based on the old version deployed on the FPGA structure by the FPGA chip The circuit logic configuration file is formed;更新单元,使所述FPGA结构基于解密得到的新版电路逻辑配置文件进行更新部署,以使所述FPGA结构实现为所属的区块链节点上的可信执行环境。The update unit enables the FPGA structure to be updated and deployed based on the new version of the circuit logic configuration file obtained by decryption, so that the FPGA structure is implemented as a trusted execution environment on the blockchain node to which it belongs.
- 一种电子设备,包括:An electronic device including:处理器;processor;用于存储处理器可执行指令的存储器;A memory for storing processor executable instructions;其中,所述处理器通过运行所述可执行指令以实现如权利要求1-8中任一项所述的方法。Wherein, the processor implements the method according to any one of claims 1-8 by running the executable instruction.
- 一种计算机可读存储介质,其上存储有计算机指令,该指令被处理器执行时实现如权利要求1-8中任一项所述方法的步骤。A computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implements the steps of the method according to any one of claims 1-8.
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