WO2021056631A1 - 可自主回复写应答的axi总线传输装置 - Google Patents
可自主回复写应答的axi总线传输装置 Download PDFInfo
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- WO2021056631A1 WO2021056631A1 PCT/CN2019/111413 CN2019111413W WO2021056631A1 WO 2021056631 A1 WO2021056631 A1 WO 2021056631A1 CN 2019111413 W CN2019111413 W CN 2019111413W WO 2021056631 A1 WO2021056631 A1 WO 2021056631A1
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- fifo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3041—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is an input/output interface
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the invention relates to an AXI bus transmission device, in particular, an AXI bus transmission device capable of autonomously replying to write responses, and belongs to the technical field of AXI bus transmission devices.
- the master and slave device modules will shield the influence caused by different bus protocol interfaces when designing, and use their own unique transmission protocol interface, which is called the local interface protocol. Therefore, the master and slave device modules need a bus The protocol is converted to a local interface protocol (bus transmission) module to be connected to different buses.
- bus transmission bus transmission
- the AXI bus protocol is a widely used bus transmission protocol at present.
- the master device module (hardware device) sends a write command and write data to the slave device module (hardware device). After the data transmission is completed, the slave device needs to return a write response. If the slave device returns a write response to the AXI bus, the slave device needs to also support the AXI protocol, specifically the corresponding AXI interface, which will cause the slave device design to be complicated, or to modify the already designed slave device.
- the technical problem to be solved by the present invention is to provide an AXI bus transmission device that can autonomously reply to write responses.
- the device automatically extracts the current command elements and slave device status, generates write responses, and automatically responds, without the need to communicate with The slave device module performs additional interactions, so that the design of the slave device module is not changed.
- an AXI bus transmission device that can autonomously reply a write response.
- the device is connected between the AXI bus and the local bus to replace the slave device to return a write response.
- the device includes FIFO_A, FIFO_B, counting module, comparison module and selector;
- FIFO_A is connected to the AXI bus and used to store the avid and awlen signals in the write command sent by the received AW channel.
- Avid represents the ID of the write command, and each write command has Corresponding ID value, awlen represents the write data transmission length information in the write command;
- the counting module is connected to the AXI bus and is used to count the actual received data and write the recorded actual data transmission length information into FIFO_B;
- the input of FIFO_B is connected to the output of the counting module to store the actual data reception length information;
- the input of the comparison module is connected to the output of -FIFO_A and FIFO_B to compare whether the length values stored in FIFO_A and FIFO_B are equal , If equal, output 0, otherwise output 2, 0 means correct, 2 means transmission error;
- the input end of the selector is connected to the output end of the comparison module and 2 respectively, and the enable end of the selector is connected to lclk_dis and lrst, lclk_dis is the slave Device module clock shutdown signal, effective means that the slave device module clock is turned off, lrst
- the counting module is connected to the write data channel W of the AXI bus.
- the write last signal wlast in the write data channel W determines the working status of the counting module; when the W channel receives valid data and the current wlast is low and invalid, the counting module starts from 0 Start counting. When the W channel receives a valid data and the wlast signal is invalid, the count value is increased by 1. When the wlast is high and valid, the counting module writes the current recorded actual data transmission length information into FIFO_B and clears the counter.
- FIFO_A is connected to the write command channel AW of the AXI bus, and the AW channel receives a valid AXI write command, and stores the avid and awlen signal values in FIFO_A.
- the comparison module reads the values in these two FIFOs at the same time, where the id value stored in FIFO_A is assigned to bid, and the length value stored in the two FIFOs is compared whether Equal, if they are equal, output 0, otherwise output 2.
- FIFO_A can receive multiple AXI write commands continuously or intermittently, and for each write command, the counting module counts once.
- the present invention monitors AXI transmission commands and local device modules, and autonomously responds to the AXI write response according to the actual transmission conditions and the working conditions of the device modules, ensuring the normal operation and performance of the AXI bus system It effectively reflects the current transmission situation of the write command, and does not need to make additional modifications to the original defined local interface.
- Figure 1 is a schematic block diagram of the present invention.
- This embodiment discloses an AXI bus transmission device capable of autonomously replying to a write response.
- the device is connected between the AXI bus and the local bus. Its function is to replace the slave device to return a write response.
- the method to achieve this function is to transmit commands and
- the local slave device monitors (that is, automatically extracts the current command elements and slave device status), and then autonomously responds to the AXI write response according to the actual transmission situation and the working status of the device module to ensure the normal operation of the AXI bus system and effectively reflect the current write command transmission situation , And there is no need to make additional modifications to the original defined local interface.
- the AXI bus transmission device includes FIFO_A, FIFO_B, counting module, comparison module, and a selector.
- FIFO_A is connected to the AXI bus and is used to store the avid and awlen signals in the write command sent by the received AW channel.
- avid represents the ID of the write command
- each write command has a corresponding ID value
- awlen represents the write data in the write command Transmission length information
- the counting module is connected to the AXI bus to count the actual received data and write the recorded actual data transmission length information into FIFO_B
- the input terminal of FIFO_B is connected to the output terminal of the counting module,
- the input ends of the comparison module are respectively connected to the output ends of FIFO_A and FIFO_B to compare whether the length values stored in FIFO_A and FIFO_B are equal, if they are equal, output 0, otherwise output 2, 0 means correct , 2 means transmission error
- the input end of the selector is connected to the output end of the comparison module and 2 respectively, the enable end of the selector is connected to lclk_dis and lrst,
- the counting module is connected to the write data channel W of the AXI bus, and the write last signal wlast in the write data channel W determines the working state of the counting module.
- the counting module starts counting from 0.
- the counting module writes the current recorded actual data transmission length information into FIFO_B and clears the counter.
- FIFO_A is connected to the write command channel AW of the AXI bus, and the AW channel receives a valid AXI write command, and stores the avid and awlen signal values in FIFO_A.
- the comparison module reads the values in the two FIFOs at the same time.
- the id value stored in FIFO_A is assigned to bid, and the length values stored in the two FIFOs are compared if they are equal. If they are equal, output 0, otherwise output 2.
- the AW channel receives a valid AXI write command, and stores the avid and awlen signal values into FIFO_A. Multiple commands can be received continuously and intermittently. For each write command, the counting module counts once. The depth of FIFO_A depends on the number of commands that can be buffered.
- the W channel receives valid write data, and the current wlast signal is invalid, the counter starts counting from 0. Each time a valid data is received and the wlast signal is invalid, the counter value is incremented by 1.
- the comparison module detects that FIFO_A and FIFO_B are not empty, and reads each of the two FIFOs once.
- the id value in FIFO_A is directly assigned to bid. According to the AXI protocol, the write command and the write response id must correspond one-to-one. Compare the length value recorded in FIFO_A and FIFO_B, and output 0 if they are consistent, otherwise output 2.
- the selector chooses to assign the output value or 2 of the comparison module to bresp according to the current lclk_dis and lrst signal values. If either lclk_dis or lrst is valid, assign 2 to bresp; otherwise, output the output value of the comparison module.
- the present invention monitors the status of the slave device through the lclk_dis and lrst signals. According to the provisions of the AXI protocol, any write transfer initiated by the master device module cannot be suspended or cancelled, and the slave device module must give a response, otherwise the master device module will wait forever.
- This embodiment monitors the status of the slave device in real time. If the current slave device module is in the reset state or the local clock is off, and cannot correctly receive the data from the bus, after receiving the write command and the write data, the response 2 is automatically returned. This will not cause the system to freeze.
- a write command contains the write data transmission length information awlen.
- the wlast signal write last signal
- the data transmission length in the received write command is compared with the actual data transmission quantity. If they are inconsistent, a response 2 is returned; otherwise, a response 0 is returned.
- the actual number of data transfers is derived from the wlast count of the write data channel.
- the receiving order of the write command corresponds to the receiving order of the write data one-to-one, and there is no disorder.
- the present invention automatically extracts the current command elements and the slave device state, generates a write response, and automatically responds, without additional interaction with the slave device module, so that the slave device module design is not changed.
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Abstract
Description
Claims (5)
- 可自主回复写应答的AXI总线传输装置,其特征在于:本装置连接于AXI总线与本地总线之间,用于代替从设备返回写应答,本装置包括FIFO_A、FIFO_B、计数模块、对比模块以及选择器;FIFO_A与AXI总线相连,用于存放接收的AW通道发送的写命令中的awid和awlen信号,awid表示写命令的ID,每条写命令都有对应的ID值,awlen表示写命令中的写数据传输长度信息;计数模块与AXI总线相连,用于对实际接收到的有效数据进行计数,并将记录的实际数据传输长度信息写入FIFO_B中;FIFO_B的输入端与计数模块的输出端相连,用于存放实际数据接收长度信息;对比模块的输入端分别与FIFO_A和FIFO_B的输出端相连,用于对比FIFO_A与FIFO_B中存放的长度值是否相等,如果相等,输出0,否则输出2,0表示正确,2表示传输错误;选择器的输入端分别与对比模块的输出端和2相连,选择器的使能端连接lclk_dis和lrst,lclk_dis为从设备模块时钟关断信号,有效表示从设备模块时钟关断,lrst为从设备模块复位信号,有效表示从设备当前处于复位状态,如果当前lclk_dis或lrst有效,则选择输出2,否则输出对比模块的结果;选择器的输出为bresp,FIFO_A中的id值直接赋给bid,bresp和bid为本装置返回的写应答。
- 根据权利要求1所述的可自主回复写应答的AXI总线传输装置,其特征在于:计数模块与AXI总线的写数据通道W相连,写数据通道W中的写最后信号wlast决定计数模块的工作状态;W通道接收到有效数据,且当前wlast低无效时,计数模块从0开始计数,W通道每收到一个有效数据且wlast信号无效,计数值加1,当wlast高有效时,计数模块将当前记录的实际数据传输长度信息写入FIFO_B中,并将计数器清零。
- 根据权利要求1所述的可自主回复写应答的AXI总线传输装置,其特征在于:FIFO_A与AXI总线的写命令通道AW相连,AW通道接收到有效的AXI写命令,将awid、awlen信号值存入FIFO_A中。
- 根据权利要求1所述的可自主回复写应答的AXI总线传输装置,其特征在于:当FIFO_A和FIFO_B都不为空时,对比模块同时读取这两个FIFO中的值一次,其中FIFO_A中存放的id值赋给bid,并且对比这两个FIFO中存放的长度值是否相等,如果相等,输出0,否则输出2。
- 根据权利要求1或3所述的可自主回复写应答的AXI总线传输装置,其特征在于:FIFO_A可以连续或者间断地接收多条AXI写命令,针对每条写命令,计数模块都进行一次计数。
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CN102375797A (zh) * | 2010-08-19 | 2012-03-14 | 索尼公司 | 总线***以及连接总线***和连接设备的桥接器电路 |
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