WO2021051551A1 - Memristor memory chip and operation method therefor - Google Patents

Memristor memory chip and operation method therefor Download PDF

Info

Publication number
WO2021051551A1
WO2021051551A1 PCT/CN2019/117436 CN2019117436W WO2021051551A1 WO 2021051551 A1 WO2021051551 A1 WO 2021051551A1 CN 2019117436 W CN2019117436 W CN 2019117436W WO 2021051551 A1 WO2021051551 A1 WO 2021051551A1
Authority
WO
WIPO (PCT)
Prior art keywords
module
voltage
word line
mos tube
memristor
Prior art date
Application number
PCT/CN2019/117436
Other languages
French (fr)
Chinese (zh)
Inventor
王兴晟
黄恩铭
缪向水
Original Assignee
华中科技大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华中科技大学 filed Critical 华中科技大学
Publication of WO2021051551A1 publication Critical patent/WO2021051551A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0038—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods

Definitions

  • the present invention belongs to the field of memory, and more specifically, relates to a memristor chip and an operation method thereof.
  • the memristive material can switch between high resistance and low resistance.
  • the low resistance state is the state formed by the conductive path, which has a low resistance value, and the opposite is high.
  • the resistance state is a state in which the conductive path is disconnected and has a high resistance value, so data can be stored through high and low resistance.
  • the storage and read operations of the memristor include a variety of voltages with different amplitudes.
  • the most basic operations in the read and write operations of the memristor are set (write 1) and reset (write 0) operations.
  • Various operations need to quickly and accurately apply a voltage to the electrode terminal of the memristor, and the operation of the multi-resistance memristor is to add multiple corresponding set or reset pulse widths to achieve the corresponding resistance state.
  • the adjustment of this voltage requires the close cooperation of the control logic, and the appropriate operating voltage needs to be applied to the selected memory cell of the memristor to realize the storage function. If there is a misalignment in the operating voltage, it will cause the memristor The storage life becomes shorter and the probability of failure becomes higher, making the read data inaccurate.
  • the present invention provides a memristor chip, which can realize stable reading and writing operations.
  • a memristor chip which is characterized in that the chip includes a power management module, a decoding module, a storage module including a plurality of storage arrays, a logic control module, a read-write module, and /O module;
  • the logic control module provides control signals for the chip
  • the decoder module receives the control of the logic control module to perform address selection of the storage array to be operated
  • the read-write module performs address selection according to the logic control after the address selection.
  • the control signal provided by the module performs corresponding operations on the storage array
  • the interface module is used to output the data read by the read-write module
  • the word line decoder of the decoding module is arranged between the storage module There is a word line voltage conversion module. In this way, the voltage input to the gate of the word line transistor in the memory array is the adjusted voltage.
  • the word line voltage conversion circuit sets the gate voltage input to the word line transistor according to the current limit, including the following parameters: memristor memory cell high and low resistance, and the word line transistor parameters include width and length Ratio, process turn-on voltage Vth.
  • the word line voltage conversion circuit is composed of a first MOS tube and a second MOS tube, wherein the input signal to be converted is input to the gates of the first MOS tube and the second MOS tube at the same time, and the drain of the first MOS tube The pole is connected to the source of the second MOS tube, wherein the drain of the second MOS tube is grounded, and the source of the first MOS tube outputs the converted voltage.
  • the word line voltage conversion circuit has a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, and an inverter.
  • the voltage before conversion is simultaneously input to the fifth MOS tube and passes through all
  • the drains of the fifth and sixth MOS transistors are connected to ground at the same time, and the source of the fifth MOS transistor is connected to the drain of the third MOS transistor.
  • the source of the MOS tube is connected to the drain of the fourth MOS tube, and the voltage between the source of the fifth MOS tube and the drain of the third MOS tube is input to the gate of the fourth MOS tube.
  • the source connection voltage of the MOS tube is converted into a reference voltage, and the gate output of the third MOS tube is the converted voltage.
  • the writing circuit in the read-write module includes a first-pole writing circuit voltage selector and a second-pole writing circuit voltage selector, which are used to select the voltage applied by the corresponding operation to form a loop.
  • the read circuit in the read-write module includes a read voltage follower circuit connected to the storage module, and a read voltage conversion circuit connected to the read voltage follower circuit, which also includes a circuit that forms a loop with a ground reference resistor.
  • a reference voltage follower circuit, and a reference voltage conversion circuit connected to the reference voltage follower circuit, the write voltage conversion circuit and the signal output from the reference voltage conversion circuit are converted into a readout signal output by a differential sensitive amplifier.
  • the present invention also provides an operating method of a memristor chip, which is characterized in that the operating method mainly includes the following steps:
  • the corresponding memristor unit is selected and turned on by the logic control module.
  • the power management module outputs the operating voltage
  • the reading and writing module controls the selector to select the voltage according to the control signal of the corresponding operation to form an operating loop, which is input to the word line transistor in the memory array
  • the voltage of the gate is adjusted by the word line voltage conversion module after the column decoder to achieve current limiting.
  • the word line voltage conversion circuit sets the gate voltage input to the word line transistor according to the current limit, including the following parameters: memristor memory cell high and low resistance, and the word line transistor parameters include width Length ratio, process turn-on voltage Vth.
  • the present invention also discloses a word line voltage conversion circuit of a memristor, which is characterized in that the word line voltage conversion circuit uses the switch tube word line transistor in the memristor storage array as a current limiting device at the same time.
  • the word line voltage conversion circuit is arranged between the word line decoder and the word line transistor, and converts the gate voltage input to the word line transistor according to the set current limit.
  • the power supply voltage is fully utilized on the premise of expanding the use of word line transistors, and the circuit structure is further simplified. Set up voltage conversion between to provide current-limiting voltage.
  • Fig. 1 is a schematic diagram of a memory cell of a memory array in a memristor chip implemented according to the present invention
  • FIG. 2 is a schematic diagram of the basic storage architecture corresponding to the memory cells of the memory array in the memristor chip implemented according to the present invention
  • FIG. 3 is a schematic diagram of the memory array architecture in the memristor chip implemented according to the present invention.
  • FIG. 4 is a schematic diagram of the composition structure of a memristor chip implemented according to the present invention.
  • FIG. 5 is a voltage conversion list under the read and write operation of the memristor chip implemented according to the present invention.
  • FIG. 6 is a schematic diagram of a write circuit structure of a memory array of a memristor chip implemented according to the present invention.
  • FIG. 7 is a block diagram of the structure of the read circuit of the memory array of the memristor chip implemented in accordance with the present invention.
  • FIG. 8 is a schematic diagram of a specific structure of a read circuit of a memory array of a memristor chip implemented according to the present invention.
  • FIG. 9 is one of the implementation modes of the specific circuit structure of the word line voltage conversion of the memristor chip according to the present invention.
  • Fig. 11 is a schematic flow chart of voltage conversion steps of a memristor chip implemented according to the present invention.
  • Storage module 2 Decoding module 3: Wordline voltage conversion module 4: Logic control module
  • Read and write module 6 Power management module 7: I/O module 8: First pole write circuit voltage selector 9: Second pole write circuit voltage selector
  • 111 Upper electrode of memristor (TiN) 110: Function layer of memristor (HfOx) 112: Lower electrode of memristor (TiN) 11: Memristor unit in 1T1R structure 13: Word line transistor in 1T1R structure 132 : Transistor source in the 1T1R structure 12: Bit line selection transistor in the memory array 13: Word line selection transistor in the memory array
  • PMOS tube 32 NMOS tube 33: PMOS tube 34: PMOS tube 35: NMOS tube 36: NMOS tube 37: Inverter
  • Reading voltage following circuit 52 Reading voltage conversion circuit 53: Reference voltage following circuit 54: Reference voltage conversion circuit 55: Reference resistance 56: Sensitive differential amplifier
  • Voltage follower amplifier 512 Voltage follow PMOS tube 521: Voltage conversion PMOS tube 531: Reference voltage follower amplifier 532: Reference voltage PMOS tube 541: Reference voltage PMOS tube
  • FIGS. 1 to 7 The embodiments of the present invention will be described in detail in conjunction with FIGS. 1 to 7 as follows:
  • FIG. 1 is a memory cell used in a memristor read-write circuit implemented according to the present invention, and its structure includes three parts, an upper electrode 100, a functional layer 110, and a lower electrode 120. It is a typical sandwich structure.
  • the electrode materials of the upper electrode and the lower electrode are Ti, Ta, TiN, TaN, and the functional layer material is HfOx.
  • the upper electrode material of the memristive memory cell is TiN
  • the functional layer material is HfOx
  • the lower electrode material is Ti.
  • Fig. 2 is a schematic diagram of the basic memory architecture corresponding to the memory cell used in the memristor read-write circuit implemented according to the present invention, which is a traditional 1T1R architecture, that is, 1 transistor and 1 memristor unit.
  • the gate of the transistor is connected to the word line control signal, the drain is connected to the lower electrode of the memristor, and the upper electrode 111 is connected to the source of the selection transistor.
  • FIG. 3 is a schematic diagram of the memory array structure corresponding to the memory cell used in the memristor read-write circuit implemented according to the present invention.
  • the source of the bit selection transistor 300 is connected to the upper electrode of a column of memory cells, and the word selection transistors 320 share the same gate in the same row, thus forming an N ⁇ M memory array.
  • the Yth bit transistor is selected At the time, only the memory cell in the Xth row and Y column will be selected.
  • Figure 4 is a schematic diagram of the structure of the memristor chip implemented in accordance with the present invention, including a block decoder 22, a row decoder 23, and a column decoder 21 to form the memory array of the memory module 1 (the memory array may have multiple , The 4 mentioned in the figure are just one of the implementations), word line voltage conversion 3, power management module 6, logic control module 4, read/write module 5, and I/O module 7.
  • the power management module 6 can be designed by LDO or DC-DC switching power supply.
  • the logic control module 4 is used to provide a control signal for the entire memristor chip, the decoder module 2 receives the control signal to select the corresponding storage unit in the storage array, and the I/O module 7 is used to read the read-write module 5
  • the data is output to other devices, such as display devices, where the read-write module 5 is used to apply the read-write voltage supplied by the power management module 6 to the storage unit in the selected storage array to complete the corresponding read-write operation.
  • the improvement of the invention is that a word line voltage conversion circuit 3 is provided between the row decoder 23 and the memory array. In this way, the voltage input to the gate of the word line transistor in the memory array through the row decoder 23 is adjusted.
  • the main technical reasons are as follows: (1) There are multiple gate loads in the memory array; 2) The voltage selected by the voltage selector does not directly act on the gate of the bit line transistor; (3) The power supply voltage is modularized and solidified, and the logic voltage output of the decoder is the power supply voltage, which cannot be the input word line transistor The current-limiting voltage required by the gate. Based on the above reasons, in order for the chip to achieve stable read and write operations, a word line voltage conversion module needs to be provided between the row decoder 23 and the memory array.
  • FIG. 5 shows the voltage required for the four basic operations of the chip's read and write operations:
  • Forming operation apply the V_forming voltage to the upper electrode of the selected memristor unit, apply the Vw_forming voltage to the word line transistor, ground the source of the word line transistor, and apply a positive ⁇ V_forming voltage to the memristor unit;
  • Set operation (write 1 operation): apply V_set voltage to the upper electrode of the selected memristor unit, apply Vw_set voltage to the word line transistor, and ground the source of the word line transistor to apply a positive ⁇ V_set voltage to the memristor;
  • Reset operation (write 0 operation): ground the upper electrode of the selected memristor unit, apply vdd voltage to the word line transistor, apply V_reset voltage to the source of the word line transistor, and apply a reversed ⁇ V_reset voltage to the memristor;
  • V_read voltage is applied to the upper electrode of the selected memristor unit, Vdd voltage is applied to the word line transistor, and the source of the word line transistor is grounded to achieve a positive ⁇ V_read voltage applied to the memristor.
  • FIGS. 6-8 it is a schematic diagram of the specific structure of the read-write module corresponding to the above-mentioned chip architecture.
  • the row, column, and block decoders will decode one of the 4 memory arrays, and select a bit and word line in the selected memory array. At this time, the memory will be selected. A cell in the array.
  • the power management module 6 provides the corresponding voltage to the read/write module 5.
  • the first pole write circuit voltage selector 8 and the second pole write circuit voltage selector 9 in the read/write module 5 select the corresponding operating voltage to apply to Bit line selection transistor 12 in the memory array;
  • the word line voltage output by the decoding will be Vw_forming, and the power management module 6 will provide corresponding voltages to the read-write module 5 and the word line voltage conversion module 3.
  • the logic control module 4 will control the reading and writing module 5 to perform the forming operation.
  • the first pole writing circuit voltage selector 8 and the second pole writing circuit voltage selector 9 in the read-write module 5 control signals to select V_forming and gnd to be added to the upper and lower ends of the storage array, respectively. Thus performing the forming operation.
  • the Set operation will apply V_set and gnd voltages to the first and second poles of the memory array, and the word line voltage conversion module 3 will apply Vw_set to the array WL.
  • the first pole writing circuit voltage selector 8 and the second pole writing circuit voltage selector 9 in the reading and writing module 5 apply the gnd and V_reset voltages respectively, and the word line voltage conversion module 3 applies the vdd voltage. In this way, the three operations of Forming, Set and Reset are completed.
  • the module mainly includes the following parts, including a read voltage follower circuit 51 connected to the memory array 1, and a read voltage conversion connected to the read voltage follower circuit 51 Circuit 52, and the reference voltage side, which includes a grounded reference resistor 55, a reference voltage follower circuit 53 that forms a loop with the reference resistor 55, and a reference voltage conversion circuit 54 connected to the reference voltage follower circuit 53, to write voltage conversion
  • the signal output by the circuit 52 and the reference voltage conversion circuit 54 is converted into a readout signal and output by the differential sense amplifier 56.
  • the read voltage follower circuit 51 includes an amplifier 511, a PMOS feedback tube 512, and an input terminal of the amplifier 511 is connected to the V_read input, and the output terminal of the amplifier 511 Connect to the gate of the PMOS feedback tube 512,
  • the other input terminal of the amplifier 511 is also connected to the drain of the PMOS feedback tube 512, wherein the source of the PMOS feedback tube 512 is connected to the read voltage conversion circuit 52, and the read voltage conversion circuit 52 is connected to the gate source of the PMOS tube 521 for saturation connection.
  • the output signal is output to the differential sense amplifier 56.
  • the read reference voltage follower circuit 53 includes an amplifier 531 and a PMOS feedback tube 532.
  • One input of the amplifier 531 is connected to the V_read input, the output terminal of the amplifier 531 is connected to the gate of the PMOS feedback tube 512, and the other input terminal of the amplifier 531 is also Connected to the drain of the PMOS feedback tube 512, wherein the source of the PMOS feedback tube 532 is connected to the reference voltage conversion circuit 54, wherein the drain of the PMOS tube 532 is also grounded through the reference resistor 55, and the reference voltage conversion circuit 53 is connected to the gate of the PMOS tube 541
  • the output signal is output to the differential sense amplifier 56 with a diode formed of a pole source.
  • the power management module 6 will provide the read voltage V_read to the read and write module 5, and the logic control module 4 will provide the control signal to the read and write module 5.
  • Three decoders (row, column, block) will select a memory cell in the memory array.
  • the voltage of the word line is converted into vdd by the word line voltage conversion module 3.
  • the amplifier 511 and the PMOS feedback tube 511 will act as a voltage follower to provide a V_read voltage at the upper end of the selected memristor unit corresponding to the memory array 1 to provide a stable and fast voltage, and the lower end of the corresponding selected memristor unit will be grounded.
  • V_read a positive read voltage V_read will be applied to the selected memristor unit.
  • the branch will generate a read current, and a voltage will be generated at one end of the differential sense amplifier 56 through the PMOS tube 521 connected in saturation.
  • a V_read voltage is generated at the end of the reference resistor 55 to obtain a read current, and a reference voltage is generated at the other end of the differential sense amplifier 531 through a diode connected to the PMOS feedback tube 531.
  • the selection of the reference resistor 55 will intervene between the high resistance and the low resistance of the memristor. For example, when the memristor unit is in the low resistance state, the voltage of the PMOS feedback tube 521 will be lower than the voltage of the PMOS feedback tube 541. When the unit is in the high-impedance state, the voltage of the PMOS feedback tube 521 will be less than the voltage of the PMOS feedback tube 541, and the differential sense amplifier 56 will compare and amplify the voltage at both ends to obtain a high (Vdd) or low (0) voltage value, which represents storage Data 1 and 0. Then the data read by the differential sensitive amplifier 56 is output to other external devices through the IO module 7.
  • Vdd high or low (0) voltage value
  • the main function is to convert the voltage.
  • the following two implementation modes are specifically given, one of which is shown in FIG. 9, where PMOS The tube 31 and the NMOS tube 32 are composed of the input signal to be converted into the gates of the PMOS tube 31 and the NMOS tube 32 at the same time.
  • the drain of the PMOS tube 31 is connected to the source of the NMOS tube 32, and the drain of the NMOS tube 32 is grounded.
  • the source output of the PMOS tube 31 is the converted voltage.
  • the above-mentioned circuit includes a PMOS tube 33, a PMOS tube 34, an NMOS tube 35, an NMOS tube 36, and an inverter 37.
  • the voltage before the voltage conversion is simultaneously input to the NMOS transistor 35, and then input to the gate of the NMOS transistor 36 after the inverter 37.
  • the drains of the NMOS transistor 35 and the NMOS transistor 36 are connected to the ground at the same time, and the source of the NMOS transistor 35 is connected to the PMOS transistor 33.
  • the source of the NMOS tube 36 is connected to the drain of the PMOS tube 34, and the voltage between the source of the NMOS tube 35 and the drain of the PMOS tube 33 is input to the gate of the PMOS tube 34, where the PMOS tube 33 and the PMOS tube
  • the source of 34 is connected to the converted reference voltage, and the output of the gate of the PMOS tube 33 is the converted voltage.
  • the present invention also proposes a word line voltage conversion method of a memristor chip, which mainly includes the following working steps:
  • the same memristor unit is selected and turned on by the logic control module 3.
  • the power management module 6 outputs the corresponding supply voltage
  • the reading and writing module 5 controls the selector to select the voltage input to the corresponding control signal according to the influence of the corresponding operation.
  • the memory array forms a corresponding operation loop.
  • the voltage applied to the word line will be output by the voltage conversion circuit after the column decoder 23 and then applied to the gate of the word line transistor to achieve current limiting.
  • a memristor memory chip is provided, and a reasonable reading and writing method and model are provided for the memristor.
  • the magnitude of the voltage conversion is mainly set according to the current limit, including the following parameters: memristor memory cell high and low resistance, word line transistor parameters including aspect ratio, process turn-on voltage Vth is to evaluate the device parameters of the limited loop to design the current limit.
  • the feedback tube is clearly defined as PMOS in this embodiment, but this is not strictly limited.
  • Different MOS tubes can be selected according to the conduction mode in the circuit, and the conduction connection of each pole can be modified and selected.
  • the high-resistance and low-resistance settings correspond to the forward and reverse voltages applied by various operations such as writing, erasing, and reading, and the corresponding read-write circuit settings, which can be set according to the material properties of the memory cell.
  • the current-limiting circuit structure form, and the current-limiting parameters are designed and modified.
  • the corresponding operating circuit can also be set according to each resistance state, and the operating loops corresponding to different resistance states can be set.
  • the corresponding voltage conversion circuit is designed for the current limit.
  • various control signals need to be generated by the controller to realize the selection and read-write control of the memory cell array.
  • the controller is set as a conventional setting for those skilled in the art.
  • the selector circuit structure They are also products such as chips and circuits that can be obtained in the prior art, and their specific structure forms are not repeated here.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Read Only Memory (AREA)

Abstract

A memristor chip and an operation method therefor. The chip comprises a power supply management module (6), a decoding module, a memory module (1), a logic control module (4), a read/write module (5), and an I/O module (7); the read/write module (5) performs a corresponding operation on a memory array after address selection according to a control signal provided by the logic control module (4); an interface module is used for outputting data read by the read/write module (5); a word line voltage conversion module (3) is provided between a row decoder (23) of the decoding module and the memory module (1), and in this way, a voltage input to the gate of a word line transistor in the memory array is an adjusted voltage. According to the bipolar memristor chip and the operation method therefor, the possibility of the memristor memory device failing after current limiting is reduced, the high and low resistance distribution of the device will be more uniform, data reading is stable and the service life of the device is significantly prolonged, and when the invention is applied to a multi-valued memristive device, the resistance state after current limiting will be correspondingly stable.

Description

忆阻器存储芯片及其操作方法Memristor memory chip and its operation method [技术领域][Technical Field]
本发明属于存储器领域，更具体地，涉及一种忆阻器芯片及其操作方法。The present invention belongs to the field of memory, and more specifically, relates to a memristor chip and an operation method thereof.
[背景技术][Background technique]
通过对以忆阻材料为基底的存储器材料施加适当的电压，来使忆阻材料在高阻和低阻之间进行转换，其中低阻态是导电通路形成的状态，具有低阻值，相反高阻态则是导电通路断开的状态，具有高阻值，因此可以通过高低阻来储存数据。同样的，也存在多个阻态的忆阻器，既一个忆阻单元能存储多个值。By applying an appropriate voltage to the memory material based on the memristive material, the memristive material can switch between high resistance and low resistance. The low resistance state is the state formed by the conductive path, which has a low resistance value, and the opposite is high. The resistance state is a state in which the conductive path is disconnected and has a high resistance value, so data can be stored through high and low resistance. Similarly, there are multiple resistive memristors, that is, one memristive unit can store multiple values.
忆阻器的存储和读取操作包括多种幅值大小不同的电压，例如忆阻器读写操作中最基本的操作为set(写1)和reset(写0)操作，对于忆阻器的各种操作，需要快速准确地在忆阻器电极端加上电压，其中多阻态忆阻器的操作则是加多个相应的set或者reset脉宽来达到相应的电阻态。这种电压的调配需要控制逻辑的紧密配合，并且需要在忆阻器相应被选中的存储单元上施加合适的操作电压，从而实现存储功能，如果在操作电压上有失准，会使得忆阻器的存储寿命变短，失效几率变高，使得读出数据失准。The storage and read operations of the memristor include a variety of voltages with different amplitudes. For example, the most basic operations in the read and write operations of the memristor are set (write 1) and reset (write 0) operations. For the memristor Various operations need to quickly and accurately apply a voltage to the electrode terminal of the memristor, and the operation of the multi-resistance memristor is to add multiple corresponding set or reset pulse widths to achieve the corresponding resistance state. The adjustment of this voltage requires the close cooperation of the control logic, and the appropriate operating voltage needs to be applied to the selected memory cell of the memristor to realize the storage function. If there is a misalignment in the operating voltage, it will cause the memristor The storage life becomes shorter and the probability of failure becomes higher, making the read data inaccurate.
[发明内容][Summary of the Invention]
针对现有技术的以上缺陷或改进需求，本发明提供了一种忆阻器芯片，可以实现稳定的读写操作。In view of the above defects or improvement requirements of the prior art, the present invention provides a memristor chip, which can realize stable reading and writing operations.
为实现上述目的，按照本发明，提供一种忆阻器芯片，其特征在于，所述芯片包括电源管理模块，译码模块，包含若干存储阵列的存储模块，逻辑控制模块，读写模块，I/O模块；In order to achieve the above objective, according to the present invention, a memristor chip is provided, which is characterized in that the chip includes a power management module, a decoding module, a storage module including a plurality of storage arrays, a logic control module, a read-write module, and /O module;
所述逻辑控制模块为所述芯片提供控制信号，所述译码器模块接收所述逻辑控制模块的控制对待操作的存储阵列执行选址，所述读写模块在选址后依据所述逻辑控制模块提供的控制信号对存储阵列执行相应的操作，所述接口模块用于将所述读写模块读出的数据输出，所述译码模块的字线译码器与所述存储模块之间设置有字线电压转化模块，以此方式，输入至存储阵列中的字线晶体管栅极的电压是经过调节后的电压。The logic control module provides control signals for the chip, the decoder module receives the control of the logic control module to perform address selection of the storage array to be operated, and the read-write module performs address selection according to the logic control after the address selection. The control signal provided by the module performs corresponding operations on the storage array, the interface module is used to output the data read by the read-write module, and the word line decoder of the decoding module is arranged between the storage module There is a word line voltage conversion module. In this way, the voltage input to the gate of the word line transistor in the memory array is the adjusted voltage.
进一步地，所述字线电压转化电路将输入所述字线晶体管的栅极电压依据限 流大小进行设定，包括如下参数：忆阻器存储单元高低阻，所述字线晶体管参数包括宽长比、工艺导通电压Vth。Further, the word line voltage conversion circuit sets the gate voltage input to the word line transistor according to the current limit, including the following parameters: memristor memory cell high and low resistance, and the word line transistor parameters include width and length Ratio, process turn-on voltage Vth.
进一步地，所述字线电压转化电路由第一MOS管及第二MOS管组成，其中有待转化的输入信号同时输入第一MOS管及第二MOS管的栅极，其中第一MOS管的漏极接第二MOS管的源极，其中第二MOS管的漏极接地，第一MOS管的源极输出为转化后的电压。Further, the word line voltage conversion circuit is composed of a first MOS tube and a second MOS tube, wherein the input signal to be converted is input to the gates of the first MOS tube and the second MOS tube at the same time, and the drain of the first MOS tube The pole is connected to the source of the second MOS tube, wherein the drain of the second MOS tube is grounded, and the source of the first MOS tube outputs the converted voltage.
进一步地，所述字线电压转化电路有第三MOS管、第四MOS管、第五MOS管、第六MOS管，反相器，转化前的电压同时输入至第五MOS管、并经过所述反相器后输入至第六MOS管的栅极，所述第五MOS管、第六MOS管的漏极同时连接接地，第五MOS管源极接第三MOS管的漏极，第六MOS管的源极接第四MOS管的漏极，第五MOS管源极接第三MOS管的漏极之间的电压输入至第四MOS管的栅极，其中第三MOS管与第四MOS管的源极接电压转化参考电压，其中第三MOS管的栅极输出为转化后的电压。Further, the word line voltage conversion circuit has a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, and an inverter. The voltage before conversion is simultaneously input to the fifth MOS tube and passes through all After the inverter is input to the gate of the sixth MOS transistor, the drains of the fifth and sixth MOS transistors are connected to ground at the same time, and the source of the fifth MOS transistor is connected to the drain of the third MOS transistor. The source of the MOS tube is connected to the drain of the fourth MOS tube, and the voltage between the source of the fifth MOS tube and the drain of the third MOS tube is input to the gate of the fourth MOS tube. The source connection voltage of the MOS tube is converted into a reference voltage, and the gate output of the third MOS tube is the converted voltage.
进一步地，所述读写模块中的写电路包括第一极写电路电压选择器及第二极写电路电压选择器，用于选取对应操作所施加的电压从而形成回路。Further, the writing circuit in the read-write module includes a first-pole writing circuit voltage selector and a second-pole writing circuit voltage selector, which are used to select the voltage applied by the corresponding operation to form a loop.
进一步地，所述读写模块中的读电路包括有与所述存储模块连接的读电压跟随电路，以及与读电压跟随电路连接的读电压转化电路，其中还包括有与接地参考电阻形成回路的参考电压跟随电路，以及与所述参考电压跟随电路连接的参考电压转化电路，所述写电压转化电路以及与所述参考电压转化电路输出的信号经过差分灵敏放大器转化为读出信号输出。Further, the read circuit in the read-write module includes a read voltage follower circuit connected to the storage module, and a read voltage conversion circuit connected to the read voltage follower circuit, which also includes a circuit that forms a loop with a ground reference resistor. A reference voltage follower circuit, and a reference voltage conversion circuit connected to the reference voltage follower circuit, the write voltage conversion circuit and the signal output from the reference voltage conversion circuit are converted into a readout signal output by a differential sensitive amplifier.
本发明还提出了一种忆阻器芯片的操作方法，其特征在于，所述操作方法主要包括如下步骤：The present invention also provides an operating method of a memristor chip, which is characterized in that the operating method mainly includes the following steps:
通过逻辑控制模块选中导通相应的忆阻器单元，此时电源管理模块输出操作电压，读写模块根据相应操作的控制信号控制选择器选择电压形成操作回路，输入至存储阵列中的字线晶体管栅极的电压经过列译码器后的字线电压转化模块调节，达到限流的作用。The corresponding memristor unit is selected and turned on by the logic control module. At this time, the power management module outputs the operating voltage, and the reading and writing module controls the selector to select the voltage according to the control signal of the corresponding operation to form an operating loop, which is input to the word line transistor in the memory array The voltage of the gate is adjusted by the word line voltage conversion module after the column decoder to achieve current limiting.
进一步地，所述字线电压转化电路将输入所述字线晶体管的栅极电压依据限流大小来进行设定，包括如下参数：忆阻器存储单元高低阻，所述字线晶体管参数包括宽长比、工艺导通电压Vth。Further, the word line voltage conversion circuit sets the gate voltage input to the word line transistor according to the current limit, including the following parameters: memristor memory cell high and low resistance, and the word line transistor parameters include width Length ratio, process turn-on voltage Vth.
本发明还公开了一种忆阻器的字线电压转化电路，其特征在于，所述字线电压转化电路利用所述忆阻器存储阵列中的开关管字线晶体管同时作为限流器件，所述字线电压转化电路设置于字线译码器及所述字线晶体管之间，将输入所述字线晶体管的栅极电压依据设定限流大小进行转化。The present invention also discloses a word line voltage conversion circuit of a memristor, which is characterized in that the word line voltage conversion circuit uses the switch tube word line transistor in the memristor storage array as a current limiting device at the same time. The word line voltage conversion circuit is arranged between the word line decoder and the word line transistor, and converts the gate voltage input to the word line transistor according to the set current limit.
进一步地，其在工艺实现上与所述存储阵列集成，或设置于***电路中。Further, it is integrated with the memory array in terms of process realization, or is arranged in a peripheral circuit.
总体而言，通过本发明所构思的以上技术方案与现有技术相比，具有以下有益效果：Generally speaking, compared with the prior art, the above technical solutions conceived by the present invention have the following beneficial effects:
(1)本发明提出的忆阻器芯片及操作方法中，对限流电路进行了新的设计，将开关管字线晶体管同时作为限流器件，将开关晶体管的作用进行了扩展，电路结构简单，不需要增加额外设计的电路，不需要额外补充其它的晶体管来进行限流；(1) In the memristor chip and operation method proposed in the present invention, a new design of the current-limiting circuit is carried out, the word line transistor of the switch tube is used as the current-limiting device at the same time, the role of the switch transistor is expanded, and the circuit structure is simple , No need to add additional design circuit, no need to supplement other transistors to limit current;
(2)本发明提出的忆阻器芯片及操作方法中，在扩展字线晶体管的使用作用的前提下，充分利用电源电压，进一步简化电路结构，在字线译码器及字线晶体管栅极之间设置电压转化来提供限流电压。(2) In the memristor chip and operation method proposed in the present invention, the power supply voltage is fully utilized on the premise of expanding the use of word line transistors, and the circuit structure is further simplified. Set up voltage conversion between to provide current-limiting voltage.
(3)按照本发明提出的忆阻器芯片及操作方法，在简化电路结构的同时，也给工艺实现提供了更加可靠的选择，并且采用了限流电路之后，显著提高了忆阻器读出单元的可靠性。(3) According to the memristor chip and operation method proposed in the present invention, while simplifying the circuit structure, it also provides a more reliable choice for process realization, and after the current limiting circuit is adopted, the memristor readout is significantly improved The reliability of the unit.
[附图说明][Explanation of drawings]
图1为按照本发明实现的忆阻器芯片中的存储器阵列的存储单元示意图；Fig. 1 is a schematic diagram of a memory cell of a memory array in a memristor chip implemented according to the present invention;
图2为按照本发明实现的忆阻器芯片中的存储器阵列的存储单元所对应的基础存储构架示意图；2 is a schematic diagram of the basic storage architecture corresponding to the memory cells of the memory array in the memristor chip implemented according to the present invention;
图3为按照本发明实现的忆阻器芯片中的存储器阵列构架示意图；3 is a schematic diagram of the memory array architecture in the memristor chip implemented according to the present invention;
图4为按照本发明实现的忆阻器芯片的组成结构示意图；4 is a schematic diagram of the composition structure of a memristor chip implemented according to the present invention;
图5为按照本发明实现的忆阻器芯片的读写操作下的电压转化列表；FIG. 5 is a voltage conversion list under the read and write operation of the memristor chip implemented according to the present invention;
图6为按照本发明实现的忆阻器芯片的存储阵列的写电路结构示意图；6 is a schematic diagram of a write circuit structure of a memory array of a memristor chip implemented according to the present invention;
图7为按照本发明实现的忆阻器芯片的存储器阵列的读电路框图结构示意图；7 is a block diagram of the structure of the read circuit of the memory array of the memristor chip implemented in accordance with the present invention;
图8为按照本发明实现的忆阻器芯片的存储器阵列的读电路具体结构示意图；8 is a schematic diagram of a specific structure of a read circuit of a memory array of a memristor chip implemented according to the present invention;
图9为按照本发明实现的忆阻器芯片的字线电压转化的具体电路结构的实施方式之一；FIG. 9 is one of the implementation modes of the specific circuit structure of the word line voltage conversion of the memristor chip according to the present invention;
图10为按照本发明实现的忆阻器芯片的字线电压转化的具体电路结构的实施方式之二；10 is the second embodiment of the specific circuit structure of the word line voltage conversion of the memristor chip according to the present invention;
图11为按照本发明实现的忆阻器芯片的电压转化步骤流程示意图。Fig. 11 is a schematic flow chart of voltage conversion steps of a memristor chip implemented according to the present invention.
所有视图中，同一个附图标记表示相同的结构与零件，其中：In all the views, the same reference sign indicates the same structure and parts, among which:
1：存储模块 2：译码模块 3：字线电压转化模块 4：逻辑控制模块1: Storage module 2: Decoding module 3: Wordline voltage conversion module 4: Logic control module
5：读写模块 6：电源管理模块 7：I/O模块 8：第一极写电路电压选择器 9：第二极写电路电压选择器5: Read and write module 6: Power management module 7: I/O module 8: First pole write circuit voltage selector 9: Second pole write circuit voltage selector
111：忆阻器上电极(TiN) 110：忆组器功能层(HfOx) 112：忆组器下电极(TiN) 11：1T1R结构中的忆组器单元 13：1T1R结构中的字线晶体管 132：1T1R结构中的晶体管源极 12：存储阵列中的位线选择晶体管 13：存储阵列中的字线选择晶体管111: Upper electrode of memristor (TiN) 110: Function layer of memristor (HfOx) 112: Lower electrode of memristor (TiN) 11: Memristor unit in 1T1R structure 13: Word line transistor in 1T1R structure 132 : Transistor source in the 1T1R structure 12: Bit line selection transistor in the memory array 13: Word line selection transistor in the memory array
21：列译码器 22：块译码器 23：行译码器21: Column decoder 22: Block decoder 23: Row decoder
31：PMOS管 32：NMOS管 33：PMOS管 34：PMOS管 35：NMOS管 36：NMOS管 37：反向器31: PMOS tube 32: NMOS tube 33: PMOS tube 34: PMOS tube 35: NMOS tube 36: NMOS tube 37: Inverter
51：读电压跟随电路 52：读电压转化电路 53：参考电压跟随电路 54：参考电压转化电路 55：参考电阻 56：灵敏差分放大器51: Reading voltage following circuit 52: Reading voltage conversion circuit 53: Reference voltage following circuit 54: Reference voltage conversion circuit 55: Reference resistance 56: Sensitive differential amplifier
511：电压跟随放大器 512：电压跟随PMOS管 521：电压转化PMOS管 531：参考电压跟随放大器 532：参考电压PMOS管 541：参考电压PMOS管511: Voltage follower amplifier 512: Voltage follow PMOS tube 521: Voltage conversion PMOS tube 531: Reference voltage follower amplifier 532: Reference voltage PMOS tube 541: Reference voltage PMOS tube
[具体实施方式][detailed description]
本发明的实施例将配合图1至图7详述如下：The embodiments of the present invention will be described in detail in conjunction with FIGS. 1 to 7 as follows:
图1为按照本发明实现的忆阻器读写电路所应用的存储单元，其结构包含三个部分，上电极100，功能层110，下电极120。是一种典型的三明治结构，上电极和下电极的电极材料为Ti，Ta，TiN，TaN，功能层材料为HfOx。FIG. 1 is a memory cell used in a memristor read-write circuit implemented according to the present invention, and its structure includes three parts, an upper electrode 100, a functional layer 110, and a lower electrode 120. It is a typical sandwich structure. The electrode materials of the upper electrode and the lower electrode are Ti, Ta, TiN, TaN, and the functional layer material is HfOx.
在本发明所涉及的一种具体实施方式中，忆阻存储单元的上电极材料为TiN，功能层材料为HfOx，下电极材料为Ti。当在上电极加一定的正电压，下电极接0电压时，将执行Set操作，此时将忆阻存储单元置于低阻状态(称为加正向电压)。当在下电极加一定的正电压，上电极接0电压时，将执行Reset操作， 将忆阻器至于高阻状态(称为加反向电压)，具备上述特性的忆阻存储单元属于一种典型的双极型忆阻器，当然，本发明所设计的电路结构适用于双极型忆阻器，上述材料的实施方式只是举例忆阻器领域的典型制备材料。In a specific embodiment of the present invention, the upper electrode material of the memristive memory cell is TiN, the functional layer material is HfOx, and the lower electrode material is Ti. When a certain positive voltage is applied to the upper electrode and the lower electrode is connected to a voltage of 0, the Set operation will be executed. At this time, the memristive memory cell is placed in a low resistance state (referred to as applying a forward voltage). When a certain positive voltage is applied to the lower electrode and 0 voltage is applied to the upper electrode, the Reset operation will be performed to put the memristor in a high resistance state (called reverse voltage). The memristive memory cell with the above characteristics is a typical Of course, the circuit structure designed in the present invention is suitable for bipolar memristors. The above-mentioned material embodiments are only examples of typical materials in the field of memristors.
图2为按照本发明实现的忆阻器读写电路所应用的存储单元所对应的基础存储构架示意图，为传统的1T1R构架，即1个晶体管1个忆阻器单元。其中晶体管的栅极接字线控制信号，漏极接忆阻器的下电极，上电极111接位选择晶体管源极。Fig. 2 is a schematic diagram of the basic memory architecture corresponding to the memory cell used in the memristor read-write circuit implemented according to the present invention, which is a traditional 1T1R architecture, that is, 1 transistor and 1 memristor unit. The gate of the transistor is connected to the word line control signal, the drain is connected to the lower electrode of the memristor, and the upper electrode 111 is connected to the source of the selection transistor.
图3为按照本发明实现的忆阻器读写电路所应用的存储单元所对应的存储阵列构架示意图。位选择晶体管300源极接一列存储单元的上电极，字选择晶体管320同一行共栅极，由此构成一个N×M的存储阵列，当第X个字选择晶体选中，第Y个位晶体管选中时，将只选中第X行Y列的存储单元。FIG. 3 is a schematic diagram of the memory array structure corresponding to the memory cell used in the memristor read-write circuit implemented according to the present invention. The source of the bit selection transistor 300 is connected to the upper electrode of a column of memory cells, and the word selection transistors 320 share the same gate in the same row, thus forming an N×M memory array. When the Xth word selection crystal is selected, the Yth bit transistor is selected At the time, only the memory cell in the Xth row and Y column will be selected.
图4为按照本发明实现的忆阻器芯片的组成结构示意图，包含块译码器22，行译码器23，列译码器21，组成存储模块1的存储阵列(存储阵列可以存在多个，图示中所举出的4个只是其中一种实施方式)，字线电压转化3，电源管理模块6，逻辑控制模块4，读写模块5，I/O模块7。其中电源管理模块6可以由LDO设计也可以使用DC-DC开关电源设计。Figure 4 is a schematic diagram of the structure of the memristor chip implemented in accordance with the present invention, including a block decoder 22, a row decoder 23, and a column decoder 21 to form the memory array of the memory module 1 (the memory array may have multiple , The 4 mentioned in the figure are just one of the implementations), word line voltage conversion 3, power management module 6, logic control module 4, read/write module 5, and I/O module 7. The power management module 6 can be designed by LDO or DC-DC switching power supply.
其中，作为本发明的芯片结构的工作方式：Among them, as the working mode of the chip structure of the present invention:
逻辑控制模块4用于为整个忆阻器芯片提供控制信号，译码器模块2接收控制信号在存储阵列中选中相应的存储单元，其中I/O模块7用于将读写模块5读出的数据输出至其它设备，例如显示设备等，其中读写模块5用于将电源管理模块6供给的读写电压作用于选中的存储阵列中的存储单元从而完成相应的读写操作，其中，作为本发明的改进，在行译码器23与存储阵列之间设置有字线电压转化电路3，以此方式，通过行译码器23输入至存储阵列中的字线晶体管栅极的电压是经过调节后的电压，从而保证忆阻器的工作电压的稳定性，在忆阻器芯片的工作模式中，是通过电源管理模块6输出多个电压，经过选择器输出当前操作对应的电压输出至存储器阵列的位线晶体管栅极，达到限流的作用，但是上述输出的电压直接作用于存储阵列可能存在电压带载不够的问题，主要技术原因如下：(1)存储阵列存在多个栅极负载；(2)经过电压选择器选择出来的电压，并不是直接作用于位线晶体管的栅极；(3)电源电压模块化固化，译码器的逻辑 电压输出为电源电压，不可能是输入字线晶体管栅极所需要的限流电压。基于以上原因，为芯片能实现稳定的读写操作，需要在行译码器23与存储阵列之间设置字线电压转化模块。The logic control module 4 is used to provide a control signal for the entire memristor chip, the decoder module 2 receives the control signal to select the corresponding storage unit in the storage array, and the I/O module 7 is used to read the read-write module 5 The data is output to other devices, such as display devices, where the read-write module 5 is used to apply the read-write voltage supplied by the power management module 6 to the storage unit in the selected storage array to complete the corresponding read-write operation. The improvement of the invention is that a word line voltage conversion circuit 3 is provided between the row decoder 23 and the memory array. In this way, the voltage input to the gate of the word line transistor in the memory array through the row decoder 23 is adjusted. After the voltage, so as to ensure the stability of the working voltage of the memristor, in the working mode of the memristor chip, multiple voltages are output through the power management module 6, and the voltage corresponding to the current operation is output to the memory array through the selector. The gate of the bit line transistor of the bit line reaches the current limit function, but the above-mentioned output voltage directly acts on the memory array, and there may be insufficient voltage load. The main technical reasons are as follows: (1) There are multiple gate loads in the memory array; 2) The voltage selected by the voltage selector does not directly act on the gate of the bit line transistor; (3) The power supply voltage is modularized and solidified, and the logic voltage output of the decoder is the power supply voltage, which cannot be the input word line transistor The current-limiting voltage required by the gate. Based on the above reasons, in order for the chip to achieve stable read and write operations, a word line voltage conversion module needs to be provided between the row decoder 23 and the memory array.
图5为该芯片读写操作基本四个操作所需施加的电压：Figure 5 shows the voltage required for the four basic operations of the chip's read and write operations:
forming操作：在选中的忆阻器单元的上电极施加V_forming电压，字线晶体管施加Vw_forming电压，字线晶体管源极接地，施加正向的ΔV_forming电压于忆阻器单元；Forming operation: apply the V_forming voltage to the upper electrode of the selected memristor unit, apply the Vw_forming voltage to the word line transistor, ground the source of the word line transistor, and apply a positive ΔV_forming voltage to the memristor unit;
Set操作(写1操作)：在选中的忆阻器单元的上电极施加V_set电压，字线晶体管施加Vw_set电压，字线晶体管源极接地，达到施加正向的ΔV_set电压于忆阻器；Set operation (write 1 operation): apply V_set voltage to the upper electrode of the selected memristor unit, apply Vw_set voltage to the word line transistor, and ground the source of the word line transistor to apply a positive ΔV_set voltage to the memristor;
Reset操作(写0操作)：在选中的忆阻器单元的上电极接地，字线晶体管施加vdd电压，字线晶体管源极施加V_reset电压，达到施加反向的ΔV_reset电压于忆阻器；Reset operation (write 0 operation): ground the upper electrode of the selected memristor unit, apply vdd voltage to the word line transistor, apply V_reset voltage to the source of the word line transistor, and apply a reversed ΔV_reset voltage to the memristor;
Read操作：在选中的忆阻器单元的上电极施加V_read电压，字线晶体管施加Vdd电压，字线晶体管源极接地，达到施加正向的ΔV_read电压于忆阻器。Read operation: V_read voltage is applied to the upper electrode of the selected memristor unit, Vdd voltage is applied to the word line transistor, and the source of the word line transistor is grounded to achieve a positive ΔV_read voltage applied to the memristor.
对于上述的芯片架构，如图6-8中所示，为对应于上述芯片架构中的读写模块具体结构示意图。For the above-mentioned chip architecture, as shown in FIGS. 6-8, it is a schematic diagram of the specific structure of the read-write module corresponding to the above-mentioned chip architecture.
如图6中所示，在写操作时，行、列、块译码器将译码4个存储阵列中的一个，并在选中的存储阵列中选中一条位与字线，此时将选中存储阵列中的一个单元。As shown in Figure 6, during the write operation, the row, column, and block decoders will decode one of the 4 memory arrays, and select a bit and word line in the selected memory array. At this time, the memory will be selected. A cell in the array.
其中电源管理模块6提供相应的电压给读写模块5，读写模块5中的第一极写电路电压选择器8和第二极写电路电压选择器9根据控制信号选择相应操作的电压施加于存储阵列中的位线选择晶体管12；The power management module 6 provides the corresponding voltage to the read/write module 5. The first pole write circuit voltage selector 8 and the second pole write circuit voltage selector 9 in the read/write module 5 select the corresponding operating voltage to apply to Bit line selection transistor 12 in the memory array;
进行forming操作时，译码输出的字线电压将为Vw_forming，电源管理模块6将向读写模块5与字线电压转换模块3提供相应电压。逻辑控制模块4将控制读写模块5执行forming操作。读写模块5中的第一极写电路电压选择器8和第二极写电路电压选择器9控制信号分别选择V_forming与gnd加到存储阵列的上端与下端。从而执行forming操作。During the forming operation, the word line voltage output by the decoding will be Vw_forming, and the power management module 6 will provide corresponding voltages to the read-write module 5 and the word line voltage conversion module 3. The logic control module 4 will control the reading and writing module 5 to perform the forming operation. The first pole writing circuit voltage selector 8 and the second pole writing circuit voltage selector 9 in the read-write module 5 control signals to select V_forming and gnd to be added to the upper and lower ends of the storage array, respectively. Thus performing the forming operation.
同理Set操作将在存储阵列的第一极与第二极加上V_set与gnd电压，并且 字线电压转换模块3将在阵列WL上施加Vw_set。而Reset操作则通过读写模块5中的第一极写电路电压选择器8和第二极写电路电压选择器9控制信号分别加gnd与V_reset电压，且字线电压转换模块3施加vdd电压。以此方式完成Forming，Set，Reset三种操作。Similarly, the Set operation will apply V_set and gnd voltages to the first and second poles of the memory array, and the word line voltage conversion module 3 will apply Vw_set to the array WL. In the Reset operation, the first pole writing circuit voltage selector 8 and the second pole writing circuit voltage selector 9 in the reading and writing module 5 apply the gnd and V_reset voltages respectively, and the word line voltage conversion module 3 applies the vdd voltage. In this way, the three operations of Forming, Set and Reset are completed.
如图7中所示，对于上述芯片的读操作而言，其模块主要包括如下部分，其中包括有与存储阵列1连接的读电压跟随电路51，以及与读电压跟随电路51连接的读电压转化电路52，以及参考电压一侧，其中包括有接地的参考电阻55，以及与参考电阻55形成回路的参考电压跟随电路53，以及与参考电压跟随电路53连接的参考电压转化电路54，写电压转化电路52以及与参考电压转化电路54输出的信号经过差分灵敏放大器56转化为读出信号输出。As shown in Figure 7, for the read operation of the above-mentioned chip, the module mainly includes the following parts, including a read voltage follower circuit 51 connected to the memory array 1, and a read voltage conversion connected to the read voltage follower circuit 51 Circuit 52, and the reference voltage side, which includes a grounded reference resistor 55, a reference voltage follower circuit 53 that forms a loop with the reference resistor 55, and a reference voltage conversion circuit 54 connected to the reference voltage follower circuit 53, to write voltage conversion The signal output by the circuit 52 and the reference voltage conversion circuit 54 is converted into a readout signal and output by the differential sense amplifier 56.
如图8中所示，在上述读电路框架结构的基础之上，进一步地，读电压跟随电路51包括放大器511，PMOS反馈管512，其中放大器511一输入端接V_read输入，放大器511的输出端接PMOS反馈管512的栅极，As shown in FIG. 8, on the basis of the above-mentioned read circuit frame structure, further, the read voltage follower circuit 51 includes an amplifier 511, a PMOS feedback tube 512, and an input terminal of the amplifier 511 is connected to the V_read input, and the output terminal of the amplifier 511 Connect to the gate of the PMOS feedback tube 512,
放大器511的另外一输入端还接PMOS反馈管512的漏极，其中PMOS反馈管512的源极接读电压转化电路52，其中读电压转化电路52为连接PMOS管521栅极源极饱和连接而成的二极管，该输出信号输出至差分灵敏放大器56。The other input terminal of the amplifier 511 is also connected to the drain of the PMOS feedback tube 512, wherein the source of the PMOS feedback tube 512 is connected to the read voltage conversion circuit 52, and the read voltage conversion circuit 52 is connected to the gate source of the PMOS tube 521 for saturation connection. The output signal is output to the differential sense amplifier 56.
进一步地，读参考电压跟随电路53包括放大器531，PMOS反馈管532，其中放大器531一输入端接V_read输入，放大器531的输出端接PMOS反馈管512的栅极，放大器531的另外一输入端还接PMOS反馈管512的漏极，其中PMOS反馈管532的源极接参考电压转化电路54，其中PMOS管532的漏极还通过参考电阻55接地，其中参考电压转化电路53为连接PMOS管541栅极源极而成的二极管，该输出信号输出至差分灵敏放大器56。Further, the read reference voltage follower circuit 53 includes an amplifier 531 and a PMOS feedback tube 532. One input of the amplifier 531 is connected to the V_read input, the output terminal of the amplifier 531 is connected to the gate of the PMOS feedback tube 512, and the other input terminal of the amplifier 531 is also Connected to the drain of the PMOS feedback tube 512, wherein the source of the PMOS feedback tube 532 is connected to the reference voltage conversion circuit 54, wherein the drain of the PMOS tube 532 is also grounded through the reference resistor 55, and the reference voltage conversion circuit 53 is connected to the gate of the PMOS tube 541 The output signal is output to the differential sense amplifier 56 with a diode formed of a pole source.
其中，对于上述读电路的过程而言，对于读操作电源管理模块6将为读写模块5提供读电压V_read，逻辑控制模块4将向读写模块5提供控制信号，。3个译码器(行、列、块)将在存储阵列中选中一个存储单元。且字线的电压由字线电压转换模块3的转化后为vdd。放大器511与PMOS反馈管511将作为电压跟随器，在存储阵列1对应选中的忆阻器单元上端提供V_read电压，提供稳定快速的电压，而对应选中的忆阻器单元的下端将接地。此时在选中的忆阻器单元上将会施加一个正向的读电压V_read，此时该条支路会产生读电流，经过饱和连 接的PMOS管521，在差分灵敏放大器56一端产生一个电压。同时在参考电阻55端产生V_read电压，得到读电流，经过二极管连接PMOS反馈管531在差分灵敏放大器531的另一端产生对照电压。Among them, for the above-mentioned reading circuit process, for the reading operation, the power management module 6 will provide the read voltage V_read to the read and write module 5, and the logic control module 4 will provide the control signal to the read and write module 5. Three decoders (row, column, block) will select a memory cell in the memory array. And the voltage of the word line is converted into vdd by the word line voltage conversion module 3. The amplifier 511 and the PMOS feedback tube 511 will act as a voltage follower to provide a V_read voltage at the upper end of the selected memristor unit corresponding to the memory array 1 to provide a stable and fast voltage, and the lower end of the corresponding selected memristor unit will be grounded. At this time, a positive read voltage V_read will be applied to the selected memristor unit. At this time, the branch will generate a read current, and a voltage will be generated at one end of the differential sense amplifier 56 through the PMOS tube 521 connected in saturation. At the same time, a V_read voltage is generated at the end of the reference resistor 55 to obtain a read current, and a reference voltage is generated at the other end of the differential sense amplifier 531 through a diode connected to the PMOS feedback tube 531.
其中参考电阻55的选择将介入忆阻器高阻与低阻之间，例如，当忆阻器单元为低阻状态时，PMOS反馈管521电压将小于PMOS反馈管541的电压，当忆阻器单元为高阻状态时，PMOS反馈管521电压将小于PMOS反馈管541的电压，差分灵敏放大器56将两端电压比较放大，将得到一个高(Vdd)或低(0)电压值，即代表存储数据1与0。然后由差分灵敏放大器56读出的数据经过IO模块7输出给其他外接设备。The selection of the reference resistor 55 will intervene between the high resistance and the low resistance of the memristor. For example, when the memristor unit is in the low resistance state, the voltage of the PMOS feedback tube 521 will be lower than the voltage of the PMOS feedback tube 541. When the unit is in the high-impedance state, the voltage of the PMOS feedback tube 521 will be less than the voltage of the PMOS feedback tube 541, and the differential sense amplifier 56 will compare and amplify the voltage at both ends to obtain a high (Vdd) or low (0) voltage value, which represents storage Data 1 and 0. Then the data read by the differential sensitive amplifier 56 is output to other external devices through the IO module 7.
作为本发明的字线电压转化模块3，主要实现的作用是电压的转化，在具体的电路结构上，具体给出如下两种实施方式，其中之一如图9中所示，其中，由PMOS管31及NMOS管32组成，其中有待转化的输入信号同时输入PMOS管31及NMOS管32的栅极，其中PMOS管31的漏极接NMOS管32的源极，其中NMOS管32的漏极接地，而PMOS管31的源极输出为转化后的电压。As the word line voltage conversion module 3 of the present invention, the main function is to convert the voltage. In the specific circuit structure, the following two implementation modes are specifically given, one of which is shown in FIG. 9, where PMOS The tube 31 and the NMOS tube 32 are composed of the input signal to be converted into the gates of the PMOS tube 31 and the NMOS tube 32 at the same time. The drain of the PMOS tube 31 is connected to the source of the NMOS tube 32, and the drain of the NMOS tube 32 is grounded. , And the source output of the PMOS tube 31 is the converted voltage.
如图10中所示，作为本发明的字线电压转化电路的另外一种实施方式，其中上述电路包括有PMOS管33、PMOS管34、NMOS管35、NMOS管36，反相器37，其中电压转化前的电压同时输入至NMOS管35、经反相器37后输入NMOS管36的栅极，其中NMOS管35、NMOS管36的漏极同时连接接地，NMOS管35源极接PMOS管33的漏极，NMOS管36的源极接PMOS管34的漏极，NMOS管35源极接PMOS管33的漏极之间的电压输入至PMOS管34的栅极，其中PMOS管33与PMOS管34的源极接转化参考电压，其中PMOS管33的栅极输出为转化后的电压。As shown in FIG. 10, as another embodiment of the word line voltage conversion circuit of the present invention, the above-mentioned circuit includes a PMOS tube 33, a PMOS tube 34, an NMOS tube 35, an NMOS tube 36, and an inverter 37. The voltage before the voltage conversion is simultaneously input to the NMOS transistor 35, and then input to the gate of the NMOS transistor 36 after the inverter 37. The drains of the NMOS transistor 35 and the NMOS transistor 36 are connected to the ground at the same time, and the source of the NMOS transistor 35 is connected to the PMOS transistor 33. The source of the NMOS tube 36 is connected to the drain of the PMOS tube 34, and the voltage between the source of the NMOS tube 35 and the drain of the PMOS tube 33 is input to the gate of the PMOS tube 34, where the PMOS tube 33 and the PMOS tube The source of 34 is connected to the converted reference voltage, and the output of the gate of the PMOS tube 33 is the converted voltage.
如图11中所示，本发明还提出了一种忆阻器芯片的字线电压转化方法，主要包括的工作步骤如下：As shown in FIG. 11, the present invention also proposes a word line voltage conversion method of a memristor chip, which mainly includes the following working steps:
通过逻辑控制模块3选中导通相同的忆阻器单元，此时电源管理模块6输出相应的供应电压，在读写模块5根据相应操作的影响控制信号控制其中的选择器选择电压输入至相应的存储阵列，从而形成相应操作的回路，而此时作用于字线的电压会将经过列译码器23后的电压转化电路输出后作用于字线晶体管的栅极，达到限流的作用。The same memristor unit is selected and turned on by the logic control module 3. At this time, the power management module 6 outputs the corresponding supply voltage, and the reading and writing module 5 controls the selector to select the voltage input to the corresponding control signal according to the influence of the corresponding operation. The memory array forms a corresponding operation loop. At this time, the voltage applied to the word line will be output by the voltage conversion circuit after the column decoder 23 and then applied to the gate of the word line transistor to achieve current limiting.
总之，按照本发明提供了一种忆阻器存储芯片，针对忆阻器，提供了合理的 读写方法与模型。In a word, according to the present invention, a memristor memory chip is provided, and a reasonable reading and writing method and model are provided for the memristor.
其中，按照本发明的限流作用的设置，电压转化的大小主要依据限流大小进行设定，包括如下参数：忆阻器存储单元高低阻，字线晶体管参数包括宽长比、工艺导通电压Vth，也即是评估所限回路所具备的器件参数情况来进行限流大小的设计。Among them, according to the setting of the current limiting function of the present invention, the magnitude of the voltage conversion is mainly set according to the current limit, including the following parameters: memristor memory cell high and low resistance, word line transistor parameters including aspect ratio, process turn-on voltage Vth is to evaluate the device parameters of the limited loop to design the current limit.
其中，本实施方式中明确限定反馈管为PMOS，但这并不严格限定，依据在电路中的导通方式选择不同的MOS管，针对各极的导通连接进行改型选择即可。Among them, the feedback tube is clearly defined as PMOS in this embodiment, but this is not strictly limited. Different MOS tubes can be selected according to the conduction mode in the circuit, and the conduction connection of each pole can be modified and selected.
对于不同的双极性存储单元而已，高阻和低阻的设置对应写、擦、读等各种操作所施加的正反向电压及对应的读写电路设置，可依据存储单元材料性质设置对应的限流电路结构形式，并对限流参数进行设计改型，对于多值忆阻器，同样可以根据各个电阻态来设置对应的操作电路，对于不同的电阻态所对应的操作回路，皆可依据本发明的思路对限流大小设计相应电压转化电路。For different bipolar memory cells, the high-resistance and low-resistance settings correspond to the forward and reverse voltages applied by various operations such as writing, erasing, and reading, and the corresponding read-write circuit settings, which can be set according to the material properties of the memory cell. The current-limiting circuit structure form, and the current-limiting parameters are designed and modified. For multi-value memristors, the corresponding operating circuit can also be set according to each resistance state, and the operating loops corresponding to different resistance states can be set. According to the idea of the present invention, the corresponding voltage conversion circuit is designed for the current limit.
按照本发明实现的读写电路，需要由控制器进行各类控制信号的产生实现存储单元阵列的选择及读写控制，该控制器设置为本领域技术人员的常规设置，另外，选择器电路结构也为现有技术能够获得的芯片、电路等产品，在此不再赘述其具体结构形式。According to the read-write circuit implemented in the present invention, various control signals need to be generated by the controller to realize the selection and read-write control of the memory cell array. The controller is set as a conventional setting for those skilled in the art. In addition, the selector circuit structure They are also products such as chips and circuits that can be obtained in the prior art, and their specific structure forms are not repeated here.
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。Those skilled in the art can easily understand that the above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modification, equivalent replacement and improvement, etc. made within the spirit and principle of the present invention, All should be included in the protection scope of the present invention.

Claims (10)

  1. 一种忆阻器芯片，其特征在于，所述芯片包括电源管理模块(6)，译码模块(2)，包含若干存储阵列的存储模块(1)，逻辑控制模块(4)，读写模块(5)，I/O模块(7)；A memristor chip, characterized in that the chip includes a power management module (6), a decoding module (2), a storage module (1) including a number of storage arrays, a logic control module (4), a read-write module (5), I/O module (7);
    所述逻辑控制模块(4)为所述芯片提供控制信号，所述译码器模块(2)接收所述逻辑控制模块(4)的控制对待操作的存储阵列执行选址，所述读写模块(5)在选址后依据所述逻辑控制模块(4)提供的控制信号对存储阵列执行相应的操作，所述接口模块(7)用于将所述读写模块(5)读出的数据输出，所述译码模块(2)的字线译码器(23)与所述存储模块(1)之间设置有字线电压转化模块(3)，以此方式，输入至存储阵列中的字线晶体管(13)栅极的电压是经过调节后的电压。The logic control module (4) provides control signals for the chip, the decoder module (2) receives the logic control module (4) to control the address selection of the storage array to be operated, and the read-write module (5) After site selection, perform corresponding operations on the storage array according to the control signal provided by the logic control module (4), and the interface module (7) is used to read the data read by the read-write module (5) Output, a word line voltage conversion module (3) is arranged between the word line decoder (23) of the decoding module (2) and the storage module (1), and in this way, the word line voltage conversion module (3) is input to the storage array The voltage of the gate of the word line transistor (13) is the adjusted voltage.
  2. 如权利要求1所述的忆阻器芯片，其特征在于，所述字线电压转化电路(3)将输入所述字线晶体管(13)的栅极电压依据限流大小进行设定，包括如下参数：忆阻器存储单元高低阻，所述字线晶体管(13)参数包括宽长比、工艺导通电压Vth。The memristor chip according to claim 1, wherein the word line voltage conversion circuit (3) sets the gate voltage input to the word line transistor (13) according to the current limit, including the following Parameters: the high and low resistance of the memristor memory cell. The parameters of the word line transistor (13) include the aspect ratio and the process turn-on voltage Vth.
  3. 如权利要求1或2中所述的忆阻器芯片，其特征在于，所述字线电压转化电路(3)由第一MOS管(31)及第二MOS管(32)组成，其中有待转化的输入信号同时输入第一MOS管(31)及第二MOS管(32)的栅极，其中第一MOS管(31)的漏极接第二MOS管(32)的源极，其中第二MOS管(32)的漏极接地，第一MOS管(31)的源极输出为转化后的电压。The memristor chip according to claim 1 or 2, characterized in that, the word line voltage conversion circuit (3) is composed of a first MOS tube (31) and a second MOS tube (32), wherein there is a need to be converted The input signal is simultaneously input to the gates of the first MOS tube (31) and the second MOS tube (32), wherein the drain of the first MOS tube (31) is connected to the source of the second MOS tube (32), and the second MOS tube The drain of the MOS tube (32) is grounded, and the source output of the first MOS tube (31) is the converted voltage.
  4. 如权利要求1或2中所述的忆阻器芯片，其特征在于，所述字线电压转化电路(3)有第三MOS管(33)、第四MOS管(34)、第五MOS管(35)、第六MOS管(36)，反相器(37)，转化前的电压同时输入至第五MOS管(35)、并经过所述反相器(37)后输入至第六MOS管(36)的栅极，所述第五MOS管(35)、第六MOS管(36)的漏极同时连接接地，第五MOS管(35)源极接第三MOS管(33)的漏极，第六MOS管(36)的源极接第四MOS管(34)的漏极，第五MOS管(35)源极接第三MOS管(33)的漏极之间的电压输入至第四MOS管的栅极，其中第三MOS管(33)与第四MOS管(34)的源极接电压转化参考电压，其中第三MOS管(33)的栅极输出为转化后的电压。The memristor chip according to claim 1 or 2, wherein the word line voltage conversion circuit (3) has a third MOS tube (33), a fourth MOS tube (34), and a fifth MOS tube (35), the sixth MOS tube (36), the inverter (37), the voltage before conversion is input to the fifth MOS tube (35) at the same time, and is input to the sixth MOS tube after passing through the inverter (37) The gate of the tube (36), the drains of the fifth MOS tube (35) and the sixth MOS tube (36) are connected to ground at the same time, and the source of the fifth MOS tube (35) is connected to the third MOS tube (33). Drain, the source of the sixth MOS tube (36) is connected to the drain of the fourth MOS tube (34), and the source of the fifth MOS tube (35) is connected to the voltage input between the drain of the third MOS tube (33) To the gate of the fourth MOS tube, the source connection voltage of the third MOS tube (33) and the fourth MOS tube (34) is converted into a reference voltage, and the gate output of the third MOS tube (33) is converted Voltage.
  5. 如权利要求1或2中所述的忆阻器芯片，其特征在于，所述读写模块(5)中的写电路包括第一极写电路电压选择器(8)及第二极写电路电压选择器(9)，用于选取对应操作所施加的电压从而形成回路。The memristor chip according to claim 1 or 2, characterized in that, the writing circuit in the reading and writing module (5) includes a first-pole writing circuit voltage selector (8) and a second-pole writing circuit voltage The selector (9) is used to select the voltage applied by the corresponding operation to form a loop.
  6. 如权利要求1或2中所述的忆阻器芯片，其特征在于，所述读写模块(5)中的读电路包括有与所述存储模块(1)连接的读电压跟随电路(51)，以及与读电压跟随电路(51)连接的读电压转化电路(52)，其中还包括与接地参考电阻(55)形成回路的参考电压跟随电路(53)，以及与所述参考电压跟随电路(53)连接的参考电压转化电路(54)，所述写电压转化电路(52)以及与所述参考电压转化电路(54)输出的信号经过差分灵敏放大器(56)转化为读出信号输出。The memristor chip according to claim 1 or 2, characterized in that the reading circuit in the reading and writing module (5) includes a reading voltage follower circuit (51) connected to the storage module (1) , And a read voltage conversion circuit (52) connected to the read voltage follower circuit (51), which also includes a reference voltage follower circuit (53) that forms a loop with a ground reference resistor (55), and a reference voltage follower circuit ( 53) A connected reference voltage conversion circuit (54), the write voltage conversion circuit (52) and the signal output from the reference voltage conversion circuit (54) are converted into a readout signal output by a differential sensitive amplifier (56).
  7. 一种忆阻器芯片的操作方法，其特征在于，所述操作方法主要包括如下步骤：A method for operating a memristor chip, characterized in that the operating method mainly includes the following steps:
    通过逻辑控制模块(3)选中导通相应的忆阻器单元，此时电源管理模块(6)输出操作电压，读写模块(5)根据相应操作的控制信号控制选择器选择电压形成操作回路，输入至存储阵列中的字线晶体管(13)栅极的电压经过列译码器(23)后的字线电压转化模块(3)调节，达到限流的作用。The logic control module (3) selects and turns on the corresponding memristor unit. At this time, the power management module (6) outputs the operating voltage, and the read-write module (5) controls the selector to select the voltage according to the control signal of the corresponding operation to form an operating loop. The voltage input to the gate of the word line transistor (13) in the memory array is adjusted by the word line voltage conversion module (3) after the column decoder (23) to achieve current limiting.
  8. 如权利要求7中所述的操作方法，其特征在于，所述字线电压转化电路(3)将输入所述字线晶体管(13)的栅极电压依据限流大小来进行设定，包括如下参数：忆阻器存储单元高低阻，所述字线晶体管(13)参数包括宽长比、工艺导通电压Vth。The operation method according to claim 7, characterized in that the word line voltage conversion circuit (3) sets the gate voltage input to the word line transistor (13) according to the current limit, including the following Parameters: the high and low resistance of the memristor memory cell. The parameters of the word line transistor (13) include the aspect ratio and the process turn-on voltage Vth.
  9. 一种忆阻器的字线电压转化电路，其特征在于，所述字线电压转化电路利用所述忆阻器存储阵列中的开关管字线晶体管(13)同时作为限流器件，所述字线电压转化电路设置于字线译码器(23)及所述字线晶体管(13)之间，将输入所述字线晶体管(13)的栅极电压依据设定限流大小进行转化。A word line voltage conversion circuit of a memristor, characterized in that the word line voltage conversion circuit uses the switch tube word line transistor (13) in the memristor memory array as a current limiting device at the same time, and the word The line voltage conversion circuit is arranged between the word line decoder (23) and the word line transistor (13), and converts the gate voltage input to the word line transistor (13) according to the set current limit.
  10. 如权利要求9中所述的字线电压转化电路，其特征在于，其在工艺实现上与所述存储阵列集成，或设置于***电路中。9. The word line voltage conversion circuit according to claim 9, characterized in that it is integrated with the memory array in terms of process realization, or is arranged in a peripheral circuit.
PCT/CN2019/117436 2019-09-17 2019-11-12 Memristor memory chip and operation method therefor WO2021051551A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910878020.1 2019-09-17
CN201910878020.1A CN110797063B (en) 2019-09-17 2019-09-17 Memristor memory chip and operation method thereof

Publications (1)

Publication Number Publication Date
WO2021051551A1 true WO2021051551A1 (en) 2021-03-25

Family

ID=69427229

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/117436 WO2021051551A1 (en) 2019-09-17 2019-11-12 Memristor memory chip and operation method therefor

Country Status (2)

Country Link
CN (1) CN110797063B (en)
WO (1) WO2021051551A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111755051B (en) * 2020-06-19 2022-07-26 杭州电子科技大学 2-9 line ternary decoder circuit based on memristor
CN112183739B (en) * 2020-11-02 2022-10-04 中国科学技术大学 Hardware architecture of memristor-based low-power-consumption pulse convolution neural network
CN113707200B (en) * 2021-09-08 2024-03-15 上海集成电路装备材料产业创新中心有限公司 Memory and reading, writing and erasing method thereof
CN117271435B (en) * 2023-11-17 2024-02-13 中国人民解放军国防科技大学 Memristor-based in-memory logic circuit and full-array parallel computing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110235394A1 (en) * 2010-02-25 2011-09-29 Kabushiki Kaisha Toshiba Semiconductor memory device
CN103198860A (en) * 2013-03-15 2013-07-10 清华大学 Resistive random access memory (RRAM) writing circuit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8477555B2 (en) * 2011-06-30 2013-07-02 Intel Corporation Deselect drivers for a memory array
US8937829B2 (en) * 2012-12-02 2015-01-20 Khalifa University of Science, Technology & Research (KUSTAR) System and a method for designing a hybrid memory cell with memristor and complementary metal-oxide semiconductor
US9165647B1 (en) * 2014-06-04 2015-10-20 Intel Corporation Multistage memory cell read
WO2016068918A1 (en) * 2014-10-29 2016-05-06 Hewlett Packard Enterprise Development Lp Storing a discrete analog signal
CN105825885B (en) * 2016-03-21 2018-04-10 华中科技大学 Multilevel memory cell, read/write circuit and its operating method based on memristor
CN106297876B (en) * 2016-08-09 2019-04-16 北京大学 Operating method based on memristor array
TWI733854B (en) * 2016-09-21 2021-07-21 中國大陸商合肥睿科微電子有限公司 Techniques for initializing resistive memory devices
CN108092658B (en) * 2017-12-12 2020-05-19 华中科技大学 Logic circuit operation method
CN109447250B (en) * 2018-09-14 2020-07-10 华中科技大学 Artificial neuron based on battery effect in memristor
CN109495272B (en) * 2018-10-31 2021-04-30 复旦大学 Strong PUF circuit based on memristor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110235394A1 (en) * 2010-02-25 2011-09-29 Kabushiki Kaisha Toshiba Semiconductor memory device
CN103198860A (en) * 2013-03-15 2013-07-10 清华大学 Resistive random access memory (RRAM) writing circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JIAO BIN , DENG NING , CHEN PEIYI: "Progress in Development of Resistive RAM Peripheral Circuit", RESEARCH & PROGRESS OF SSE, vol. 33, no. 4, 25 August 2013 (2013-08-25), pages 363 - 370, XP055792573, ISSN: 1000-3819 *
JIN GANG , WU YUXIN , ZHANG JI , HUANG XIAOHUI , WU JINGANG , LIN YINYIN: "Design and Realization of a 0. 13um 1 Mb Resistive Random Access Memory", RESEARCH & PROGRESS OF SSE, vol. 31, no. 2, 25 April 2011 (2011-04-25), pages 174 - 179, XP055792566, ISSN: 1000-3819 *

Also Published As

Publication number Publication date
CN110797063B (en) 2021-05-25
CN110797063A (en) 2020-02-14

Similar Documents

Publication Publication Date Title
WO2021051551A1 (en) Memristor memory chip and operation method therefor
US7692979B2 (en) Memory readout circuit and phase-change memory device
TWI485705B (en) Memory cells having a row-based read and/or write support circuitry
US9734905B2 (en) Non-volatile memory using bi-directional resistive elements
US9548131B1 (en) Reduced power read sensing for one-time programmable memories
US8238138B2 (en) Semiconductor memory device and its operation method
CN109584932B (en) Memory device and operation method thereof
US8400860B2 (en) Electrical fuse memory
JP2004103174A (en) Semiconductor memory device
WO2021051548A1 (en) Read-write circuit and read-write method for memristor
US9666276B2 (en) Non-volatile memory using bi-directional resistive elements
US8264872B2 (en) Column decoder for non-volatile memory devices, in particular of the phase-change type
JP6102418B2 (en) Nonvolatile memory element, nonvolatile memory cell, and nonvolatile memory
US20230343391A1 (en) Duo-level word line driver
US8446754B2 (en) Semiconductor memory apparatus and method of driving the same
JP2017102993A (en) Resistive random access memory device and sense circuit thereof
JP6107472B2 (en) Nonvolatile memory cell and nonvolatile memory including the nonvolatile memory cell
US11062786B2 (en) One-time programmable memories with low power read operation and novel sensing scheme
US10726914B2 (en) Programmable resistive memories with low power read operation and novel sensing scheme
WO2021051550A1 (en) Anti-overwrite circuit and method for memristor
JP6146178B2 (en) Non-volatile memory
CN113921058A (en) 8T2R nonvolatile SRAM unit circuit
US8264871B2 (en) Phase change memory device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19945719

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19945719

Country of ref document: EP

Kind code of ref document: A1