WO2021036595A1 - 一种数据编码的方法及设备 - Google Patents

一种数据编码的方法及设备 Download PDF

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Publication number
WO2021036595A1
WO2021036595A1 PCT/CN2020/103472 CN2020103472W WO2021036595A1 WO 2021036595 A1 WO2021036595 A1 WO 2021036595A1 CN 2020103472 W CN2020103472 W CN 2020103472W WO 2021036595 A1 WO2021036595 A1 WO 2021036595A1
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Prior art keywords
sequence
generator matrix
bits
sequence numbers
bit
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PCT/CN2020/103472
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English (en)
French (fr)
Inventor
沈晖
李斌
刘凌
顾佳琦
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华为技术有限公司
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Priority to EP20859424.2A priority Critical patent/EP4016850A4/en
Publication of WO2021036595A1 publication Critical patent/WO2021036595A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/136—Reed-Muller [RM] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/31—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining coding for error detection or correction and efficient use of the spectrum
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes

Definitions

  • This application relates to the field of communications, and in particular to a method and device for data encoding.
  • RM codes are widely used in data transmission due to their very small code distance.
  • the construction process of the RM code includes: calculating the weight of the row of the F matrix corresponding to each bit, and then using the corresponding position of the row number in the RM code as the information bit to carry the information that needs to be transmitted.
  • the position corresponding to the smaller row in the RM code is used as a fixed bit, no information is transmitted, and it is usually set to 0.
  • BPSK binary phase shift keying
  • the present application provides a data encoding method and device, which are used to improve the coding and decoding performance under incoherent detection and improve the accuracy of decoding.
  • the first aspect of this application provides an encoding method, including:
  • the column weight and row weight of the generator matrix determine K sequence numbers from the first sequence of the generator matrix, the first sequence includes the sequence numbers of the rows of the generator matrix, and the first sequence does not include columns with odd column weights in the generator matrix
  • the sequence number of; the bit sequence u is determined according to K sequence numbers, u includes information bits and fixed bits, K sequence numbers are used to identify the position of K information bits in u, and the information bits are used to carry information; encode according to u and the generating matrix , Get the coded bits.
  • K sequence numbers are selected from the sequence numbers of the rows where the sequence numbers of the columns with odd column weights are removed, and the information bits in the original bit sequence u are determined according to the K sequence numbers s position. Therefore, the position of the information bit in u corresponds to an even number in the column weight of the column of the generator matrix.
  • the decoding result on the receiving device side is not subject to phase changes, resulting in more accurate decoding results and improved decoding performance.
  • u also includes a check bit, and the bit sequence u is determined according to the K sequence numbers, including:
  • the bit sequence may also include check bits.
  • the check bits may correspond to the columns of the generator matrix whose column weights are odd numbers, and the column weights of the generator matrix corresponding to the information bits are even numbers.
  • encoding according to u and the generator matrix to obtain encoded bits includes:
  • RM coding may be performed on the bit sequence to obtain coded bits.
  • the column weight of the generator matrix corresponding to the information bit is an even number.
  • the encoded bits are sent to the receiving device after corresponding processing, including:
  • the encoded bits can also be modulated and then sent to the receiving device, so that the encoded bits can be accurately sent to the receiving device and reduce the data loss rate.
  • determining K sequence numbers from the first sequence of the generator matrix includes:
  • K serial numbers are determined in descending order.
  • K sequence numbers when determining the sequence number of the information bit in the bit sequence, K sequence numbers can be determined according to the row weight from large to small, so that the column weight of the generator matrix corresponding to the information bit is an even number, and subsequent incoherent detection is performed At this time, the influence of the phase difference can be reduced, a more accurate decoding result can be obtained, and the decoding performance can be improved.
  • the second aspect of the embodiments of the present application provides an encoding device, and the encoding device has the function of implementing the data encoding method in the first aspect.
  • This function can be realized by hardware, or by hardware executing corresponding software.
  • the hardware or software includes one or more modules corresponding to the above-mentioned functions.
  • a third aspect of the embodiments of the present application provides an encoding device, which may include:
  • a processor a memory, a bus, and an input and output interface.
  • the processor, the memory and the input and output interface are connected through the bus; the memory is used to store program codes; the processor executes the application when the program codes in the memory are called The steps of the first aspect or any one of the first aspects.
  • a fourth aspect of the embodiments of the present application provides a chip system that includes a processor for supporting the encoding device to implement the functions involved in the above aspects, for example, processing data and/or information involved in the above methods.
  • the chip system further includes a memory, and the memory is used to store necessary program instructions and data of the network device.
  • the chip system can be composed of chips, and can also include chips and other discrete devices.
  • the processor mentioned in any of the above can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more for controlling the above
  • CPU central processing unit
  • ASIC application-specific integrated circuit
  • the integrated circuit executed by the program of the data encoding method in the first aspect or any one of the embodiments of the first aspect.
  • the fifth aspect of the embodiments of the present application provides a storage medium.
  • the technical solution of the present invention is essentially or the part that contributes to the existing technology, or all or part of the technical solution can be produced by software.
  • the computer software product is stored in a storage medium for storing the computer software instructions used by the above-mentioned equipment, which includes the coding device designed for executing the above-mentioned first aspect or any one of the first aspects. program.
  • the storage medium includes: U disk, mobile hard disk, read-only memory (English abbreviation ROM, English full name: Read-Only Memory), random access memory (English abbreviation: RAM, English full name: Random Access Memory), magnetic disk or CD-ROM Various media that can store program codes.
  • the sixth aspect of the embodiments of the present application provides a computer program product containing instructions, which when run on a computer, causes the computer to execute the method described in the first aspect or any optional implementation manner of the first aspect of the present application.
  • the seventh aspect of the embodiments of the present application provides a device that can be applied to an electronic device.
  • the device is coupled with a memory and is used to read and execute instructions stored in the memory, so that the device implements the first The steps performed by the processor in any embodiment of the aspect.
  • the device is a chip or system-on-chip.
  • K sequence numbers are selected from the sequence numbers of the rows where the sequence numbers of the columns with odd column weights are removed, and the information in the original bit sequence u is determined according to the K sequence numbers
  • the position of the bit Therefore, the position of the information bit in u corresponds to an even number in the column weight of the column of the generator matrix.
  • the decoding result on the receiving device side is not subject to phase changes, resulting in more accurate decoding results and improved decoding performance.
  • FIG. 1A is a schematic diagram of a network architecture to which the data encoding method provided by this application is applied;
  • FIG. 1B is a schematic diagram of another network architecture to which the data encoding method provided in this application is applied;
  • FIG. 2 is a schematic flowchart of a data encoding method provided by this application.
  • Figure 3 is a schematic diagram of the BER change of the decoding result in the existing scheme
  • FIG. 4 is a schematic diagram of a BER change of the decoding result of the data encoding method provided by this application;
  • FIG. 5 is a schematic diagram of another BER change of the decoding result of the data encoding method provided by this application.
  • FIG. 6 is a schematic diagram of a structure of the encoding device provided by this application.
  • FIG. 7 is a schematic diagram of another structure of the encoding device provided by this application.
  • the present application provides a data encoding method and device, which are used to improve the coding and decoding performance under incoherent detection and improve the accuracy of decoding.
  • the data encoding method provided in this application can be applied to various communication systems or communication networks, for example, 5G systems, Long Term Evolution (LTE) systems, Global System for Mobile Communication (GSM) or Code Division Multiple Access (CDMA) network, Wideband Code Division Multiple Access (WCDMA) network, etc., can also be Worldwide Interoperability for Microwave Access (WiMAX) or wireless Other communication networks or communication systems that require data encoding such as Wireless Fidelity (WiFi).
  • 5G systems Long Term Evolution (LTE) systems, Global System for Mobile Communication (GSM) or Code Division Multiple Access (CDMA) network, Wideband Code Division Multiple Access (WCDMA) network, etc.
  • WiMAX Worldwide Interoperability for Microwave Access
  • WiFi Wireless Fidelity
  • the specific application scenario of the embodiment of the present application may be as shown in FIG. 1A or FIG. 1B.
  • the application scenario may include one or more base stations and one or more terminals.
  • a base station can access multiple terminals (for example, terminal 1 and terminal 2 in Figure 1A), that is, a base station can communicate with multiple terminals, and the base station can send encoded Data, the base station can also receive the encoded data sent by the terminal.
  • a terminal can also communicate with multiple base stations (base station 1, base station 2, and base station 3 in Figure 1B). The terminal can either receive encoded data sent by multiple base stations, or it can be a terminal. Send the encoded data to multiple base stations.
  • the encoding method provided in this application may be executed by an encoding device, which may include a base station or terminal, or the encoding device may also be included in equipment such as a base station or terminal.
  • the base station may be various forms of macro base stations, micro base stations (also called small stations), relay stations, access points, and so on. In different communication systems, the name of the base station may also be different.
  • the base station may be a Base Transceiver Station (BTS) in a GSM or CDMA network, an NB (NodeB) in WCDMA, or an LTE system.
  • BTS Base Transceiver Station
  • NB NodeB
  • the long-term evolution node (Evolutional NodeB, eNB or eNodeB) in the 5G network can also be the base station equipment in the 5G network or the communication device in the future evolved Public Land Mobile Network (PLMN) network, for example, the 5G base station ( Next generation NodeB, gNB).
  • the terminal may be a variety of handheld devices including communication functions, wearable devices, computing devices, or other processing devices connected to a wireless modem, and so on.
  • it may be a mobile station (Mobile Station, MS), subscriber unit (subscriber unit), cellular phone (cellular phone), smart phone (smart phone), wireless data card, personal digital assistant (Personal Digital Assistant, abbreviated as PDA) Computer, tablet computer, wireless modem (modem), handheld device (handset), laptop computer (laptop computer), machine type communication (Machine Type Communication, MTC) terminal, etc.
  • MS Mobile Station
  • subscriber unit subscriber unit
  • cellular phone cellular phone
  • smart phone smart phone
  • wireless data card wireless data card
  • PDA Personal digital assistant
  • PDA Personal Digital Assistant
  • tablet computer tablet computer
  • wireless modem modem
  • handheld device handset
  • laptop computer laptop computer
  • machine type communication Machine Type Communication
  • the generator matrix is the matrix corresponding to the encoding.
  • the generator matrix can be a preset generator matrix or a constructed generator matrix.
  • the column weight in the generator matrix can be understood as the number of 1s in the column.
  • the row weight in the generator matrix can be understood as the number of 1s in the row.
  • the generator matrix G may be an 8*8 matrix, for example Calculate the number of 1s in the rows and 1s in the columns of the matrix, and then get the column weights of 1, 2, 2, 4, 2, 3, 4, and 8, and the row weights of 8, 4, 4, 2, 4, 2, 2, 1.
  • a generator matrix can also be constructed.
  • the generator matrix G can be understood as an n*n matrix, among them, It is the n-th Kronecker product of the matrix F, and the addition and multiplication operations involved are all addition and multiplication operations on the binary Galois Field (Galois Field).
  • F can be a matrix of 4*4, 8*8, etc. in addition to a 2*2 matrix, which can be specifically adjusted according to actual application scenarios, which is not limited in this application.
  • the first sequence is first determined, and the first sequence includes the row number of the generator matrix, and the first sequence does not include the sequence number of the column whose column weight is an odd number in the generator matrix.
  • step 202 specifically includes: selecting K serial numbers in descending order according to the row weight of the row corresponding to each serial number in the first sequence.
  • the sequence numbers of the columns from left to right are 0-7, and the sequence numbers of the rows from top to bottom are 0-7.
  • the column weights from left to right are 1, 2, 2, 4, 2, 4, 4, and 8, and the weights from top to bottom are 8, 4, 4, 2, 4, 2, 2, and 1.
  • the sequence number of the column with an odd column weight in the generator matrix is 0, then the sequence number 0 is removed, and the sequence numbers included in the first sequence are 1-7.
  • select K serial numbers from 1-7 to re-select the rows. If the K is 3, the K serial numbers include 1, 2, and 4 in the descending order of row weight.
  • the sequence numbers of the columns from left to right are 0-7, and the sequence numbers of the rows from top to bottom are 0-7.
  • the column weights from left to right are 8, 4, 4, 2, 4, 2, 1, and the weights from top to bottom are 1, 2, 2, 4, 2, 4, 4, and 8.
  • the sequence number of the column whose column weight is an odd number in the generator matrix is 7, then the sequence number 7 is removed, and the sequence numbers included in the first sequence are 0-6.
  • the bit sequence u is determined according to the K serial numbers.
  • the bit sequence includes information bits and fixed bits.
  • the information bit is used to carry information, and the fixed bit does not transmit information, and is usually set to 0.
  • the K sequence numbers are used to identify the positions of K information bits in u.
  • bit sequence u For example, if the length of the bit sequence u is 8 bits, and if the K sequence numbers include 3, 5, and 6, then the positions of the corresponding information bits in the bit sequence u are 0, 1, 2, 4, and 7.
  • bit sequence u After the bit sequence u is determined, coding can be performed according to the bit sequence u and the generator matrix to obtain coded bits (also referred to as coded codewords).
  • G the generator matrix
  • the K sequence numbers can be understood as the index set included in the information bit
  • the fixed bit index set is Complement then
  • the coded bit c can be obtained.
  • the coded bit c can be obtained.
  • the bit sequence u further includes a check bit
  • the check bit is the check data of K information bits, or the check bit is an even number of information among the K information bits.
  • Bit of parity data may be a checksum method, or a parity check, etc., to further improve the accuracy of the decoding result.
  • the specific encoding method is similar to the foregoing encoding method of u that does not include check bits, and will not be repeated here.
  • the number of information bits included may be less than the number of information bits included in the bit sequence u when the bit sequence u does not include check bits. For example, if the bit sequence u does not include a check bit, K may be 4, and when the bit sequence u includes 1 check bit, K may be 3.
  • the coded bits are sent to the receiving device.
  • the coded bits can also be modulated, and the modulated signal can be sent to the receiving device in a wireless or wired manner.
  • the modulated signal may also undergo other processing, such as OFDM modulation, etc., which is not limited in this application.
  • a modulated signal is obtained through a modulated mapping function map(), and the modulated symbol included in the modulated signal is map(c).
  • the mapping function can map 0 or -1 to 0, map 1 to 1, or map 1 to 0, map 0 or -1 to 1, and so on.
  • the specific modulation method may be binary phase shift keying (BPSK or 2PSK) modulation.
  • the modulation method may also be other modulation methods, which are specifically adjusted according to actual application scenarios.
  • the receiving device receives the modulated signal, demodulates and decodes it.
  • the specific decoding method may include: among them, To obtain decoded information bit sequence; u i is a possible information bit sequence, d i is a possible transmission codeword, Z is the received signal, H is the conjugate of the received signal.
  • the receiving device can determine the decoding result by taking the absolute value and the phase difference, and even if the sign is reversed, the accurate decoding result can be obtained.
  • the embodiments of the present application can greatly improve the accuracy of the obtained decoding result.
  • the BER of the RM code constructed in the method provided in this application is better than the BER of the RM code in the existing scheme in the non-coherent scenario, and the decoding result of the Hamming code in the coherent detection scenario The BER is similar to the BER of the RM code in the existing scheme in the coherent detection scenario.
  • K sequence numbers are selected from the sequence numbers of the rows where the sequence numbers of the columns with odd column weights are removed, and the bit sequence u is determined according to the K sequence numbers.
  • the position of the information bit in the corresponds to an even number in the column weight of the column of the generator matrix.
  • the receiving device can also perform incoherent detection. In the case of inaccurate phase information, according to the difference between each bit The phase difference, get accurate decoding results.
  • the codeword constructed in the method provided in this application can greatly improve the decoding performance.
  • the application is described in more detail by taking the construction process of the RM code that does not include the check bit as an example.
  • the index of the information bit Including [1, 2, 4, 5], fixed bit index Including [0, 3, 6, 7].
  • the coded bit c is modulated to obtain a modulated signal map(c), which is sent to the receiving device.
  • AWGN additive white Gaussian noise
  • the receiving device can also adopt a similar decoding method.
  • FHT fast Hadamard transformation
  • the decoding criterion is maximized, and the absolute value of the received signal and the transmitted codeword is used to achieve the decoding of the RM code under non-coherent detection, which greatly improves the accuracy of decoding and improves the interpretation. Code performance.
  • the sequence number of the column whose column weight is an odd number in the G matrix determines the sequence number of the check bit, that is, the sequence number 7.
  • the sequence number of the column whose column weight is odd in the G matrix is removed to obtain the first sequence.
  • the K sequence numbers include Including [3, 5, 6], Including [0, 1, 2, 4].
  • the (K, n) code can be obtained, which is referred to as the RM-like code below.
  • the decoding method of the receiving device is similar to the foregoing example 1, and will not be repeated here.
  • the decoding criterion is maximized, and the absolute value of the received signal and the transmitted codeword is used to achieve the decoding of the RM code under incoherent detection, which greatly improves the accuracy of the decoding and improves the interpretation. Code performance. Even when the parity bit is included, high-performance decoding can be performed.
  • FIG. 6 is a schematic structural diagram of the encoding device provided by the present application.
  • the encoding device includes: a processing unit 601 and a transceiver unit 602;
  • the processing unit 601 is configured to determine the column weight and row weight in the generator matrix
  • the processing unit 601 is further configured to determine K sequence numbers from a first sequence of the generator matrix, the first sequence includes the sequence numbers of the rows of the generator matrix, and the first sequence does not include the sequence numbers of the columns with odd column weights in the generator matrix;
  • the processing unit 601 is further configured to determine a bit sequence u according to K sequence numbers, where u includes information bits and fixed bits, and the K sequence numbers are used to identify the positions of the K information bits at u;
  • the processing unit 601 is further configured to perform encoding according to u and the generator matrix to obtain coded bits, where the K sequence numbers are the positions of the information bits in the bit sequence u, and the bit sequence u includes information bits and fixed bits;
  • the transceiver unit 602 is configured to send coded bits to the receiving device.
  • u also includes a check bit
  • the processing unit 601 is specifically configured to determine u according to the K sequence numbers and the sequence numbers of the columns with odd column weights in the generator matrix, where the sequence numbers of the columns with odd column weights in the generator matrix are used to identify the position of the check bit in u,
  • the parity bit is the parity data of K information bits, or the parity bit is the parity data of an even number of information bits among the K information bits.
  • the processing unit 601 is specifically configured to modulate the coded bits and send the obtained modulated signal to the receiving device, so that the receiving device demodulates and decodes the modulated signal through incoherent detection to obtain the information carried in the coded bits.
  • the processing unit 601 is specifically configured to determine K serial numbers in descending order according to the row weight of the row corresponding to each serial number in the first sequence.
  • the present application also provides an encoding device 700. Please refer to FIG. 7, an embodiment of the data encoding device in the embodiment of the present application.
  • the encoding device may be used to perform the encoding performed by the encoding device in any of the embodiments shown in FIGS. 2-5. For the steps, reference may be made to the relevant descriptions in the above method embodiments.
  • the encoding device 700 includes a processor 701, a memory 702, and an input and output device 703.
  • the processor 701, the memory 702, and the input/output device 703 are respectively connected to a bus, and computer instructions are stored in the memory.
  • the transceiving unit 601 in the foregoing embodiment may be the input/output device 703 in this embodiment, so the implementation of the input/output device 703 will not be described in detail.
  • the processing unit 602 in the foregoing embodiment may be the processor 701 in this embodiment, so the implementation of the processor 701 will not be repeated.
  • the encoding device 700 may include more or less components compared to FIG. 7, which is only an exemplary description in this application, and is not limited.
  • the present application provides a chip system including a processor for supporting the encoding device to implement the functions involved in the above aspects, for example, sending or processing the data and/or information involved in the above methods.
  • the chip system further includes a memory, and the memory is used to store necessary program instructions and data.
  • the chip system can be composed of chips, and can also include chips and other discrete devices.
  • the chip when the chip system is a chip in an encoding device, the chip includes a processing unit and a communication unit.
  • the processing unit may be a processor, for example, and the communication unit may be an input/output, for example. Interface, pin or circuit, etc.
  • the processing unit can execute the computer-executable instructions stored in the storage unit, so that the chip in the encoding device or the like executes the steps of the method executed by the encoding device in any one of the embodiments in FIGS. 2-5.
  • the storage unit is a storage unit in the chip, such as a register, a cache, etc., and the storage unit may also be a storage unit located outside the chip in the encoding device, etc., such as a read-only memory. (read-only memory, ROM) or other types of static storage devices that can store static information and instructions, random access memory (RAM), etc.
  • An embodiment of the present application also provides a processor, which is configured to be coupled with a memory and used to execute the method and function related to the encoding device in any of the foregoing embodiments.
  • the embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a computer, the method flow related to the encoding device in any of the foregoing method embodiments is implemented.
  • the computer may be the aforementioned encoding device.
  • the processor mentioned in the encoding device, chip system, etc. in the above embodiments of the present application, or the processor provided in the above embodiments of the present application may be a central processing unit (CPU) or Other general-purpose processors, digital signal processors (digital signal processors, DSP), application specific integrated circuits (ASICs), ready-made programmable gate arrays (field programmable gate arrays, FPGAs) or other programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, etc.
  • the general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like.
  • the number of processors in the encoding device, chip system, etc. in the above embodiments of the present application may be one or multiple, and may be adjusted according to actual application scenarios. This is only an exemplary description, and Not limited.
  • the number of memories in the embodiment of the present application may be one or multiple, and may be adjusted according to actual application scenarios. This is only an exemplary description and is not limited.
  • the memory or readable storage medium mentioned in the encoding device, chip system, etc. in the above embodiments in the embodiments of the present application may be volatile memory or non-volatile memory, or may include volatile memory. Both non-volatile and non-volatile memory.
  • the non-volatile memory can be read-only memory (ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), and electrically available Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • the volatile memory may be random access memory (RAM), which is used as an external cache.
  • RAM random access memory
  • static random access memory static random access memory
  • dynamic RAM dynamic RAM
  • DRAM dynamic random access memory
  • synchronous dynamic random access memory synchronous DRAM, SDRAM
  • double data rate synchronous dynamic random access memory double data rate SDRAM, DDR SDRAM
  • enhanced synchronous dynamic random access memory enhanced SDRAM, ESDRAM
  • synchronous connection dynamic random access memory serial DRAM, SLDRAM
  • direct rambus RAM direct rambus RAM
  • the encoding device includes a processor (or processing unit) and a memory
  • the processor in this application may be integrated with the memory, or the processor and the memory may be connected through an interface, which can be based on actual conditions.
  • the application scenario adjustment is not limited.
  • the embodiments of the present application also provide a computer program or a computer program product including a computer program.
  • the computer program When the computer program is executed on a computer, the computer will enable the computer to implement the encoding device in any of the above-mentioned method embodiments. Method flow.
  • the computer may be the aforementioned encoding device.
  • all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof.
  • software it can be implemented in the form of a computer program product in whole or in part.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium.
  • the computer instructions may be transmitted from a website, a computer, an encoding device, or data.
  • the center transmits to another website, computer, coding device or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.).
  • wired such as coaxial cable, optical fiber, digital subscriber line (DSL)
  • wireless such as infrared, wireless, microwave, etc.
  • the computer-readable storage medium may be any usable medium that can be stored by a computer or a data storage device such as an encoding device or a data center integrated with one or more usable media.
  • the usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, and a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)).
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are merely illustrative, for example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of this application essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium.
  • the storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program code.
  • the words “if” or “if” as used herein can be interpreted as “when” or “when” or “in response to determination” or “in response to detection”.
  • the phrase “if determined” or “if detected (statement or event)” can be interpreted as “when determined” or “in response to determination” or “when detected (statement or event) )” or “in response to detection (statement or event)”.

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Abstract

一种数据编码的方法及设备，用于提高在非相干检测下的编译码性能，提高译码的准确性。该方法包括：获取生成矩阵的列重以及行重（201）；从生成矩阵的第一序列中确定K个序号（202）；根据K个序号确定比特序列（203）；根据比特序列以及生成矩阵进行编码，得到编码比特（204）；将编码比特发送到接收设备（205）。

Description

一种数据编码的方法及设备
本申请要求于2019年08月29日提交中国专利局、申请号为201910810163.9、申请名称为“一种数据编码的方法及设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，尤其涉及一种数据编码的方法及设备。
背景技术
当前，随着通信领域的发展，对于各种通信场景中的数据传输的时延、可靠性等要求也越来越高。信道编码作为数据传输中最基本的无线接入处理，在数据传输中起着非常重要的作用。
现有方案中，里德-穆勒(Reed-Muller，RM)码因具有非常小的码距，在数据传输中广泛应用。其中，RM码的构造过程包括：计算每个比特对应的F矩阵的行的重量，然后将行重大的行的序号在RM码中对应的位置作为信息比特，用于携带需要传输的信息，行重小的行在RM码中对应的位置作为固定比特，不传输信息，通常设为0。
然而，对于如RM码或Polar码等编码方式，若接收设备采用二进制相移键控(binary phase shift keying，BPSK)调制，因BPSK调制需要使用相位信息，可能导致在非相干检测的场景下，得到的译码结果不准确，出现译码错误，降低译码性能。
发明内容
本申请提供一种数据编码的方法及设备，用于提高在非相干检测下的编译码性能，提高译码的准确性。
有鉴于此，本申请第一方面提供一种编码的方法，包括：
获取生成矩阵的列重以及行重；从生成矩阵的第一序列中确定K个序号，第一序列包括生成矩阵的行的序号，且第一序列中不包括生成矩阵中列重为奇数的列的序号；根据K个序号确定比特序列u，u中包括信息比特与固定比特，K个序号用于标识K个信息比特在u的位置，信息比特用于携带信息；根据u以及生成矩阵进行编码，得到编码比特。
本申请实施例中，在确定生成矩阵的列重之后，然后从去除列重为奇数的列的序号的行的序号中选择K个序号，并根据该K个序号确定原始比特序列u中信息比特的位置。因此，u中信息比特的位置对应在生成矩阵的列的列重为偶数。在非相干检测的场景下，接收设备侧的译码结果不受相位变化，得到更准确的译码效果，提高译码性能。
在一些可能的实施方式中，u中还包括校验比特，根据K个序号确定比特序列u，包括：
根据K个序号以及生成矩阵中列重为奇数的列的序号确定u，其中，生成矩阵中列重为奇数的列的序号用于标识校验比特在u的位置，校验比特为K个信息比特的校验数据，或者，校验比特为K个信息比特中的偶数个信息比特的校验数据。
在本申请实施方式中，比特序列中还可以包括校验比特，校验比特可以与生成矩阵中列重为奇数的列对应，而信息比特对应的生成矩阵的列重为偶数，在后续进行非相干检测 时，可以减少相位差的影响，得到更准确的译码结果，提高译码性能。
在一些可能的实施方式中，根据u以及生成矩阵进行编码，得到编码比特，包括：
根据u以及生成矩阵进行里德-穆勒RM编码，得到编码比特，其中，c＝uG，c为编码比特(或者称为编码码字)，G为生成矩阵。
本申请实施方式中，对比特序列可以进行RM编码，得到编码比特。而信息比特对应的生成矩阵的列重为偶数，在后续进行非相干检测时，可以减少相位差的影响，得到更准确的译码结果，提高译码性能。
在一些可能的实施方式中，将编码比特经过相应的处理后发送至接收设备，包括：
对编码比特(编码码字)进行调制，并将得到的调制信号发送至接收设备(调制信号也有可能经过其他的处理，比如进行OFDM调制等等)，以使接收设备通过非相干检测对调制信号进行解调并译码，得到原始的信息。
本申请实施方式中，还可以对编码比特(编码码字)进行调制之后，再发送至接收设备，以使编码比特可以准确发送到接收设备，降低数据丢失率。
在一些可能的实施方式中，从生成矩阵的第一序列中确定K个序号，包括：
根据第一序列中每个序号对应的行的行重，按照从大到小的顺序确定K个序号。
本申请实施方式中，在确定信息比特在比特序列中的序号时，可以按照行重由大到小确定K个序号，使得信息比特对应的生成矩阵的列重为偶数，在后续进行非相干检测时，可以减少相位差的影响，得到更准确的译码结果，提高译码性能。
本申请实施例第二方面提供了编码装置，该编码装置具有实现上述第一方面数据编码的方法的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的模块。
本申请实施例第三方面提供一种编码装置，可以包括：
处理器、存储器、总线以及输入输出接口，该处理器、该存储器与该输入输出接口通过该总线连接；该存储器，用于存储程序代码；该处理器调用该存储器中的程序代码时执行本申请第一方面或第一方面任一实施方式的步骤。
本申请实施例第四方面提供一种芯片***，该芯片***包括处理器，用于支持编码装置实现上述方面中所涉及的功能，例如，例如处理上述方法中所涉及的数据和/或信息。在一种可能的设计中，所述芯片***还包括存储器，所述存储器，用于保存网络设备必要的程序指令和数据。该芯片***，可以由芯片构成，也可以包括芯片和其他分立器件。
其中，上述任一处提到的处理器，可以是一个通用中央处理器(CPU)，微处理器，特定应用集成电路(application-specific integrated circuit，ASIC)，或一个或多个用于控制上述第一方面或第一方面任一实施方式中数据编码的方法的程序执行的集成电路。
本申请实施例第五方面提供一种存储介质，需要说明的是，本发的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产口的形式体现出来，该计算机软件产品存储在一个存储介质中，用于储存为上述设备所用的计算机软件指令，其包含用于执行上述第一方面或第一方面中任一方面为编码装置所设计的程序。
该存储介质包括：U盘、移动硬盘、只读存储器(英文缩写ROM，英文全称： Read-Only Memory)、随机存取存储器(英文缩写：RAM，英文全称：Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
本申请实施例第六方面提供一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行如本申请第一方面或第一方面任一可选实施方式中所述的方法。
本申请实施例第七方面提供一种装置，该装置可以应用于电子设备中，该装置与存储器耦合，用于读取并执行所述存储器中存储的指令，使得所述装置实现本申请第一方面的任一实施方式中处理器执行的步骤。在一种可能的设计中，该装置为芯片或片上***。
本申请实施例中，在确定生成矩阵中的列重之后，然后从去除列重为奇数的列的序号的行的序号中选择K个序号，并根据该K个序号确定原始比特序列u中信息比特的位置。因此，u中信息比特的位置对应在生成矩阵的列的列重为偶数。在非相干检测的场景下，接收设备侧的译码结果不受相位变化，得到更准确的译码效果，提高译码性能。
附图说明
图1A为本申请提供的数据编码的方法应用的一种网络架构示意图；
图1B为本申请提供的数据编码的方法应用的另一种网络架构示意图；
图2为本申请提供的一种数据编码的方法的流程示意图；
图3为现有方案中译码结果的BER变化示意图；
图4为本申请提供的数据编码的方法的译码结果的一种BER变化示意图；
图5为本申请提供的数据编码的方法的译码结果的另一种BER变化示意图；
图6为本申请提供的编码装置的一种结构示意图；
图7为本申请提供的编码装置的另一种结构示意图。
具体实施方式
本申请提供一种数据编码的方法及设备，用于提高在非相干检测下的编译码性能，提高译码的准确性。
首先本申请提供的数据编码的方法可以应用于各种通信***或通信网络，例如，5G***，长期演进(Long Term Evolution，LTE)***、全球移动通信***(Global System for Mobile Communication，GSM)或码分多址(Code Division Multiple Access，CDMA)网络、宽带码分多址(Wideband Code Division Multiple Access，WCDMA)网络等，还可以是全球微波互联接入(Worldwide Interoperability for Microwave Access，WiMAX)或无线保真(Wireless Fidelity，WiFi)等其他需要进行数据编码的通信网络或通信***。
示例性地，本申请实施例的具体应用场景可以如图1A或图1B所示。具体的，该应用场景可以包括一个或多个基站，以及一个或多个终端。如图1A所示，一个基站可以接入多个终端(例如图1A中的终端1以及终端2)，即一个基站可以与多个终端进行通信，可以由该基站向多个终端发送编码后的数据，基站也可以接收由终端发送的编码后的数据。如图1B所示，一个终端也可以与多个基站(如图1B中的基站1、基站2以及基站3)进行通信，可以是终端接收多个基站发送的编码后的数据，也可以是终端向多个基站发送编码后 的数据。
因此，本申请提供的编码的方法可以由编码装置执行，该编码装置可以包括基站或终端等，或者，也可以是该编码装置包括于基站或终端等设备中。该基站可以是各种形式的宏基站，微基站(也称为小站)，中继站，接入点等。而在不同的通信***中，基站的名称也可能会不同，例如，该基站可以是GSM或CDMA网络中的基站收发信台(Base Transceiver Station，BTS)，WCDMA中的NB(NodeB)，LTE***中的长期演进节点(Evolutional NodeB，eNB或eNodeB)，还可以是5G网络中的基站设备或者未来演进的公共陆地移动网络(Public Land Mobile Network，PLMN)网络中的通信装置，例如，5G基站(Next generation NodeB，gNB)。终端可以是各种包括通信功能的手持设备、可穿戴设备、计算设备或连接到无线调制解调器的其它处理设备等等。例如，可以是移动站(Mobile Station，MS)、用户单元(subscriber unit)、蜂窝电话(cellular phone)、智能电话(smart phone)、无线数据卡、个人数字助理(Personal Digital Assistant，简称：PDA)电脑、平板型电脑、无线调制解调器(modem)、手持设备(handset)、膝上型电脑(laptop computer)、机器类型通信(Machine Type Communication,MTC)终端等等。
下面对本申请提供的编码的方法进行详细说明。
本申请提供的编码的方法的具体流程可以如图2所示，如下所述。
201、获取生成矩阵中的列重以及行重。
其中，生成矩阵为编码对应的矩阵。该生成矩阵可以为预设的生成矩阵，也可以是构造的生成矩阵。
具体地，生成矩阵中的列重可以理解为该列中1的数量。生成矩阵中的行重可以理解为该行中1的数量。
示例性地，其中，生成矩阵G可以为8*8的矩阵，例如
Figure PCTCN2020103472-appb-000001
分别计算该矩阵内行的1的数量以及列的1的数量，然后得到列重分别为1、2、2、4、2、3、4、8，行重分别为8、4、4、2、4、2、2、1。
在一种可选的实施方式中，在步骤201之前，还可以构造生成矩阵。具体地，生成矩阵G可以理解为n*n的矩阵，
Figure PCTCN2020103472-appb-000002
其中，
Figure PCTCN2020103472-appb-000003
为矩阵F的n次克罗内克(Kronecker)积，并且涉及到的加法、乘法操作均为二进制伽罗华域(Galois Field)上的加法、乘法操作。
例如，当
Figure PCTCN2020103472-appb-000004
n＝8时，
Figure PCTCN2020103472-appb-000005
又例如，当
Figure PCTCN2020103472-appb-000006
n＝8时，
Figure PCTCN2020103472-appb-000007
此外，F除了可以是2*2矩阵之外，还可以是4*4、8*8等矩阵，具体可以根据实际应用场景调整，本申请对此不作限定。
202、从生成矩阵的第一序列中确定K个序号。
其中，首先确定第一序列，该第一序列包括生成矩阵的行号，并且，该第一序列中不包括生成矩阵中列重为奇数的列的序号。
在一种可选的实施方式中，步骤202具体包括：根据第一序列中每个序号对应的行的行重，按照从大到小的顺序选择K个序号。
例如，若
Figure PCTCN2020103472-appb-000008
其中，从左到右的列的序号为0-7，从上至下的行的序号为0-7。从左到右列重分别为1、2、2、4、2、4、4、8，从上至下行重分别为8、4、4、2、4、2、2、1。此时，生成矩阵中列重为奇数的列的序号为0，那么，去掉序号0，第一序列中所包括的序号为1-7。然后从1-7重根据行重选择K个序号。如该K为3，则按照行重由大到小的顺序，该K个序号包括1、2、4。
又例如，若
Figure PCTCN2020103472-appb-000009
其中，从左到右的列的序号为0-7，从上至下的行的序号为0-7。从左到右列重分别为8、4、4、2、4、2、2、1，从上至下行重分别为1、2、2、4、2、4、4、8。此时，生成矩阵中列重为奇数的列的序号为7，那么，去掉序号7，第一序列中所包括的序号为0-6。然后从0-6中根据行重选择K个序号。如该K为3，则按照行重由大到小的顺序，该K个序号包括3、5、6。
需要说明的是，当存在多个相同的行重，且无需全部选中时，可以任意选择其中一个或多个，也可以按照从上到小，或者从下到上的顺序选择其中的一个或多个，具体根据实际应用场景调整，本申请对此不作限定。例如，若K为4或5等，在选择了序号3、5、6之后，还需要从1、2、4中选择一个或两个，则此时可以随机选取其中的一个或两个，也可以从小到大，或从大到小的顺序选择一个或两个等。
203、根据K个序号确定行比特序列。
其中，在确定K个序号之后，根据该K个序号确定比特序列u。其中，该比特序列中包括信息比特与固定比特。该信息比特用于携带信息，固定比特不传输信息，通常设为0。该K个序号用于标识K个信息比特在u中的位置。
例如，若比特序列u的长度为8个比特，若K个序号包括3、5、6，则比特序列u中对应的信息比特的位置为0、1、2、4、7。
204、根据比特序列以及生成矩阵进行编码，得到编码比特。
在确定比特序列u之后，即可根据该比特序列u以及生成矩阵进行编码，得到编码比特(也可以称为编码码字)。
具体地，步骤204可以包括：根据u以及生成矩阵进行里德-穆勒RM编码，得到编码比特，其中，c＝uG，c为编码比特，G为生成矩阵。当然，具体的编码方式也可以是与RM编码类似的其他编码方式。
更具体地，该K个序号可以理解为包括于信息比特的索引集合
Figure PCTCN2020103472-appb-000010
固定比特的索引集合为
Figure PCTCN2020103472-appb-000011
的补集
Figure PCTCN2020103472-appb-000012
则
Figure PCTCN2020103472-appb-000013
又例如，若
Figure PCTCN2020103472-appb-000014
Figure PCTCN2020103472-appb-000015
包括[1，2，4，5]，
Figure PCTCN2020103472-appb-000016
包括[0，3，6，7]，则：
Figure PCTCN2020103472-appb-000017
即可得到编码比特c。
又例如，若
Figure PCTCN2020103472-appb-000018
Figure PCTCN2020103472-appb-000019
包括[3、4、5、6]，
Figure PCTCN2020103472-appb-000020
包括[0，1，2，7]，则：
Figure PCTCN2020103472-appb-000021
即可得到编码比特c。
可选地，在一种实现方式中，比特序列u中还包括校验比特，该校验比特为K个信息比特的校验数据，或者，校验比特为K个信息比特中的偶数个信息比特的校验数据。其中，具体的校验方式可以是校验和的方式，或者奇偶校验等等，以进一步提高译码结果的准确性。
其中，在基于包括了校验比特的u进行编码时，具体的编码方式与前述不包括校验比特的u的编码方式类似，此处不再赘述。
通常，当比特序列u中包括校验比特时，所包括的信息比特的数量可以少于该比特序列u中不包括校验比特时，该比特序列u中所包括的信息比特的数量。例如，若比特序列u中不包括校验比特，则K可以为4，当该比特序列u中包括1个校验比特时，则K可以为3。
205、将编码比特发送至接收设备。
其中，在得到编码比特之后，将该编码比特发送至接收设备。
具体地，在得到编码比特之后，还可以对该编码比特进行调制，并将调制信号通过无线或有线等方式发送至接收设备。
此外，调制信号也可以经过其他的处理，比如OFDM调制等等，本申请对此不作限定。
更具体地，在得到编码比特中的c之后，通过调制的映射函数map()，得到调制信号，该调制信号包括的调制后的符号为map(c)。例如，该映射函数可以将0或-1映射为0，将1映射为1，或者，将1映射为0，将0或-1映射为1等等。
其中，具体的调制方式可以是二进制相移键控(binary phase shift keying，BPSK或2PSK)调制，当然，该调制方式也可以是其他调制方式，具体根据实际应用场景调整。
此外，在步骤206之后，接收设备接收调制信号，并进行解调以及译码。其中，具体的译码方式可以包括：
Figure PCTCN2020103472-appb-000022
其中，
Figure PCTCN2020103472-appb-000023
为译码得到信息比特序列；u i为可能的信息比特序列，d i为可能的发送码字，Z为接收信号，H为接收信号的共轭。
因此，接收设备可以通过取绝对值以及相位差确定译码结果，即使出现符号翻转等情况，也可以得到准确的译码结果。相对于直接通过相位信息得到译码结果，本申请实施例可以大大提高得到的译码结果的准确性。
示例性地，以RM码的一些仿真图为例，对本申请提供的数据编码的方法中，编码比特的译码效果进行示例性展示。
请参阅图3，在AWGN信道下，K＝10，N＝16(K可以理解为信息比特长度，N可以理解为码长)的现有方案中的RM码在相干检测与非相关检测场景下的误比特率(bit error ratio，BER)的对比示意图。其中，纵坐标为BER，横坐标为EbNo，也可以表示为Eb/No，Eb表示单位比特的能量，No表示功率谱密度。显然地，非相干检测与相干检测相差较大，在非相干检查场景下，由于相位模糊，在高信噪比下会出现错误平层。
请参阅图4，在AWGN信道下，K＝10，n＝16(K可以理解为信息比特长度，N可以理解为码长)的场景下，本申请提供的方法中构造的RM码在相干检测和非相干检测的情况下，与K＝10，N＝15的汉明(Hamming)码在相干检测场景中的译码结果仿真对比图。其中，本申请提供的方法中构造的RM码在相干检测与非相干检测这两种场景下，BER类似，且优于汉明码的相干检测情况下的BER。
请参阅图5，在AWGN信道下，K＝10，n＝16的情况下，本申请提供的方法中构造的RM码在相干检测与非相干检测场景中的BER曲线，K＝10，N＝15的汉明(Hamming)码在相干检测场景中的译码结果的BER曲线，以及现有方案中RM码在相干检测与非相干检测场景下 的BER曲线的对比图。明显地，本申请提供的方法中构造的RM码的BER，在非相干场景下，优于现有方案中RM码的BER，以及汉明(Hamming)码在相干检测场景中的译码结果的BER，与相干检测场景中的现有方案中的RM码的BER类似。
因此，在本申请实施方式中，在确定生成矩阵中的列重之后，然后从去除列重为奇数的列的序号的行的序号中选择K个序号，并根据该K个序号确定比特序列u中信息比特的位置。因此，u中信息比特的位置对应在生成矩阵的列的列重为偶数。那么，在后续对u以及生成矩阵进行编码并调制发送至接收设备时，若采用的是BPSK调制，接收设备也可以进行非相干检测，在出现相位信息不准确的情况下，根据各个比特之间的相位差，得到准确的译码结果。例如，若出现比特的符号翻转，因对应的列重为偶数，因此，即使出现符号翻转的情况，也可根据相位差，得到准确的译码结果。通过本申请提供的方法中构造的码字，可以大大提高译码性能。
示例性地，以不包括校验比特的RM码的构建流程为例对本申请进行更详细的说明。
示例一：
首先，构建RM码生成矩阵，
Figure PCTCN2020103472-appb-000024
n可以理解为码长，例如，当
Figure PCTCN2020103472-appb-000025
n＝8时，
Figure PCTCN2020103472-appb-000026
然后去掉G矩阵中列重为奇数的列的序号，得到第一序列，然后按照行重从大从第一序列中选择K个行，该K个行的序号对应比特序列u中的信息比特的位置。其中，以K＝4为例。则信息比特的索引
Figure PCTCN2020103472-appb-000027
包括[1，2，4，5]，固定比特的索引
Figure PCTCN2020103472-appb-000028
包括[0，3，6，7]。
Figure PCTCN2020103472-appb-000029
然后对编码比特c进行调制，得到调制信号map(c)，并发送至接收设备。
若接收设备采用相干检测，则经过加性高斯白噪声(additive white Gaussian noise， AWGN)信道之后，接收信号为：y＝map(c)+n，其中，n为噪声。然后对接收信号进行译码。
若接收设备采用非相干检测，则接收信号：Z＝e jθmap(c)+n。然后接收设备进行译码：
Figure PCTCN2020103472-appb-000030
此外，对于采用快速哈达玛变换(fast Hadamard transformation，FHT)构造的RM码，接收设备也可以采用类似的译码方式。
因此，本示例中，通过译码准则变成最大化，以及通过接收信号和发射码字的绝对值，实现非相干检测下的RM码的译码，大大提高了译码的准确性，提高译码性能。
示例二：
首先，构建生成矩阵，
Figure PCTCN2020103472-appb-000031
n可以理解为码长，例如，当
Figure PCTCN2020103472-appb-000032
n＝8时，
Figure PCTCN2020103472-appb-000033
然后确定G矩阵中列重为奇数的列的序号，将该序号作为校验比特的序号，即序号7。并且，去掉G矩阵中列重为奇数的列的序号，得到第一序列。然后按照行重从大从第一序列中选择K个行，该K个行的序号对应比特序列u中的信息比特的位置。其中，以K＝3为例。
按照行重由大到小的顺序，该K个序号包括
Figure PCTCN2020103472-appb-000034
包括[3、5、6]，
Figure PCTCN2020103472-appb-000035
包括[0，1，2，4]。可以得到(K，n)码，以下称为类RM码。
接收设备的译码方式与前述示例一类似，此处不再赘述。
因此，本示例中，通过译码准则变成最大化，以及通过接收信号和发射码字的绝对值，实现非相干检测下的RM码的译码，大大提高了译码的准确性，提高译码性能。即使在包含了了校验比特的情况下，也可以进行高性能的译码。
前述对本申请提供的数据编码的方法进行了详细说明，下面结合前述的数据编码的方法，对本申请提供的编码装置进行说明，请参阅图6，本申请提供的编码装置的一种结构示意图。
该一种编码装置，包括：处理单元601以及收发单元602；
处理单元601，用于确定生成矩阵中的列重以及行重；
处理单元601，还用于从生成矩阵的第一序列中确定K个序号，第一序列包括生成矩阵的行的序号，且第一序列中不包括生成矩阵中列重为奇数的列的序号；
处理单元601，还用于根据K个序号确定比特序列u，u中包括信息比特与固定比特，K个序号用于标识K个信息比特在u的位置；
处理单元601，还用于根据u以及生成矩阵进行编码，得到编码比特，其中，K个序号为比特序列u中信息比特的位置，比特序列u包括信息比特与固定比特；
收发单元602，用于将编码比特发送至接收设备。
可选地，在一些可能的实现方式中，u中还包括校验比特，
处理单元601，具体用于根据K个序号以及生成矩阵中列重为奇数的列的序号确定u，其中，生成矩阵中列重为奇数的列的序号用于标识校验比特在u的位置，校验比特为K个信息比特的校验数据，或者，校验比特为K个信息比特中的偶数个信息比特的校验数据。
可选地，在一些可能的实现方式中，
处理单元601，具体用于根据u以及生成矩阵进行里德-穆勒RM编码，得到编码比特，其中，c＝uG，c为编码比特，G为生成矩阵。
可选地，在一些可能的实现方式中，
处理单元601，具体用于对编码比特进行调制，并将得到的调制信号发送至接收设备，以使接收设备通过非相干检测对调制信号进行解调并译码，得到编码比特中携带的信息。
可选地，在一些可能的实现方式中，
处理单元601，具体用于根据第一序列中每个序号对应的行的行重，按照从大到小的顺序确定K个序号。
本申请还提供一种编码装置700，请参阅图7，本申请实施例中数据编码装置一个实施例，该编码装置可以用于执行图2-5所示的任一实施例中编码装置执行的步骤，可以参考上述方法实施例中的相关描述。
该编码装置700包括：处理器701、存储器702以及输入输出设备703。
一种可能的实现方式中，该处理器701、存储器702、输入输出设备703分别与总线相连，该存储器中存储有计算机指令。
前述实施例中的收发单元601则可以是本实施例中的输入输出设备703，因此该输入输出设备703的实现不再赘述。
前述实施例中的处理单元602可以是本实施例中的处理器701，因此该处理器701的实现不再赘述。
一种实现方式中，编码装置700可以包括相对于图7更多或更少的部件，本申请对此仅仅是示例性说明，并不作限定。
本申请提供了一种芯片***，该芯片***包括处理器，用于支持编码装置实现上述方面中所涉及的功能，例如，例如发送或处理上述方法中所涉及的数据和/或信息。在一种可能的设计中，所述芯片***还包括存储器，所述存储器，用于保存必要的程序指令和数据。该芯片***，可以由芯片构成，也可以包括芯片和其他分立器件。
在另一种可能的设计中，当该芯片***为编码装置内的芯片时，芯片包括：处理单元和通信单元，所述处理单元例如可以是处理器，所述通信单元例如可以是输入/输出接口、管脚或电路等。该处理单元可执行存储单元存储的计算机执行指令，以使该编码装置等内的芯片执行上述图2-5中任一项实施例中编码装置执行的方法的步骤。可选地，所述存储单元为所述芯片内的存储单元，如寄存器、缓存等，所述存储单元还可以是所述编码装置等内的位于所述芯片外部的存储单元，如只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)等。
本申请实施例还提供了一种处理器，用于与存储器耦合，用于执行上述各实施例中任一实施例中涉及编码装置的方法和功能。
本申请实施例还提供了一种计算机可读存储介质，其上存储有计算机程序，该计算机程序被计算机执行时实现上述任一方法实施例中与编码装置相关的方法流程。对应的，该计算机可以为上述编码装置。
应理解，本申请以上实施例中的编码装置、芯片***等中提及的处理器，或者本申请上述实施例提供的处理器，可以是中央处理单元(central processing unit，CPU)，还可以是其他通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现成可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
还应理解，本申请中以上实施例中的编码装置、芯片***等中的处理器的数量可以是一个，也可以是多个，可以根据实际应用场景调整，此处仅仅是示例性说明，并不作限定。本申请实施例中的存储器的数量可以是一个，也可以是多个，可以根据实际应用场景调整，此处仅仅是示例性说明，并不作限定。
还应理解，本申请实施例中以上实施例中的编码装置、芯片***等中提及的存储器或可读存储介质等，可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DRRAM)。
还需要说明的是，当编码装置包括处理器(或处理单元)与存储器时，本申请中的处理器可以是与存储器集成在一起的，也可以是处理器与存储器通过接口连接，可以根据实 际应用场景调整，并不作限定。
本申请实施例还提供了一种计算机程序或包括计算机程序的一种计算机程序产品，该计算机程序在某一计算机上执行时，将会使所述计算机实现上述任一方法实施例中与编码装置的方法流程。对应的，该计算机可以为上述的编码装置。
在上述图2-5中各个实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。
所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、编码装置或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、编码装置或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存储的任何可用介质或者是包含一个或多个可用介质集成的编码装置、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的***，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的***，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个***，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，编码装置，或者其他网络设备等)执行本申请图2至图5中各个实施例所述方法的全部或部分步骤。而该存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各 种可以存储程序代码的介质。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的术语在适当情况下可以互换，这仅仅是描述本申请的实施例中对相同属性的对象在描述时所采用的区分方式。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，以便包含一系列单元的过程、方法、***、产品或设备不必限于那些单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它单元。
本申请各实施例中提供的消息/帧/信息、模块或单元等的名称仅为示例，可以使用其他名称，只要消息/帧/信息、模块或单元等的作用相同即可。
在本申请实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明。在本申请实施例中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，在本申请的描述中，除非另有说明，“/”表示前后关联的对象是一种“或”的关系，例如，A/B可以表示A或B；本申请中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况，其中A,B可以是单数或者复数。
取决于语境，如在此所使用的词语“如果”或“若”可以被解释成为“在……时”或“当……时”或“响应于确定”或“响应于检测”。类似地，取决于语境，短语“如果确定”或“如果检测(陈述的条件或事件)”可以被解释成为“当确定时”或“响应于确定”或“当检测(陈述的条件或事件)时”或“响应于检测(陈述的条件或事件)”。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (12)

  1. 一种数据编码的方法，其特征在于，包括：
    获取生成矩阵的列重以及行重；
    从所述生成矩阵的第一序列中确定K个序号，所述第一序列包括所述生成矩阵的行的序号，且所述第一序列中不包括所述生成矩阵中列重为奇数的列的序号；
    根据所述K个序号确定比特序列u，所述u中包括信息比特与固定比特，所述K个序号用于标识K个信息比特在所述u的位置；
    根据所述u以及所述生成矩阵进行编码，得到编码比特；
    将所述编码比特发送至接收设备。
  2. 根据权利要求1所述的方法，其特征在于，所述u中还包括校验比特，所述根据所述K个序号确定比特序列u，包括：
    根据所述K个序号以及所述生成矩阵中列重为奇数的列的序号确定所述u，其中，所述生成矩阵中列重为奇数的列的序号用于标识所述校验比特在所述u的位置，所述校验比特为所述K个信息比特的校验数据，或者，所述校验比特为所述K个信息比特中的偶数个信息比特的校验数据。
  3. 根据权利要求1所述的方法，其特征在于，所述根据所述u以及所述生成矩阵进行编码，得到所述编码比特，包括：
    根据所述u以及所述生成矩阵进行里德-穆勒RM编码，得到所述编码比特，其中，c＝uG，所述c为所述编码比特，所述G为所述生成矩阵。
  4. 根据权利要求1-3中任一项所述的方法，其特征在于，将所述编码比特发送至接收设备，包括：
    对所述编码比特进行调制，并将得到的调制信号发送至接收设备，以使所述接收设备通过非相干检测对所述调制信号进行解调并译码，得到所述编码比特中携带的信息。
  5. 根据权利要求1-4中任一项所述的方法，其特征在于，所述从所述生成矩阵的第一序列中确定K个序号，包括：
    根据所述第一序列中每个序号对应的行的行重，按照从大到小的顺序确定所述K个序号。
  6. 一种编码装置，其特征在于，包括：处理单元以及收发单元；
    所述处理单元，用于获取生成矩阵的列重以及行重；
    所述处理单元，还用于从所述生成矩阵的第一序列中确定K个序号，所述第一序列包括所述生成矩阵的行的序号，且所述第一序列中不包括所述生成矩阵中列重为奇数的列的序号；
    所述处理单元，还用于根据所述K个序号确定比特序列u，所述u中包括信息比特与固定比特，所述K个序号用于标识K个信息比特在所述u的位置；
    所述处理单元，还用于根据所述u以及所述生成矩阵进行编码，得到所述编码比特；
    所述收发单元，用于将所述编码比特发送至接收设备。
  7. 根据权利要求6所述的编码装置，其特征在于，所述u中还包括校验比特，
    所述处理单元，具体用于根据所述K个序号以及所述生成矩阵中列重为奇数的列的序号确定所述u，其中，所述生成矩阵中列重为奇数的列的序号用于标识所述校验比特在所述u的位置，所述校验比特为所述K个信息比特的校验数据，或者，所述校验比特为所述K个信息比特中的偶数个信息比特的校验数据。
  8. 根据权利要求6所述的编码装置，其特征在于，
    所述处理单元，具体用于根据所述u以及所述生成矩阵进行里德-穆勒RM编码，得到所述编码比特，其中，c＝uG，所述c为所述编码比特，所述G为所述生成矩阵。
  9. 根据权利要求6-8中任一项所述的编码装置，其特征在于，
    所述处理单元，具体用于对所述编码比特进行调制，并将得到的调制信号发送至接收设备，以使所述接收设备通过非相干检测对所述调制信号进行解调并译码，得到所述编码比特中携带的信息。
  10. 根据权利要求6-9中任一项所述的编码装置，其特征在于，
    所述处理单元，具体用于根据所述第一序列中序号对应的行的行重，按照从大到小的顺序确定所述K个序号。
  11. 一种编码装置，其特征在于，包括：
    处理器和存储器；
    所述存储器中存储有程序代码；
    所述处理器调用所述存储器中的程序代码时执行权利要求1-5中任一项所述方法的步骤。
  12. 一种计算机可读存储介质，包括指令，当所述指令在计算机上运行时，使得计算机执行如权利要求1-5中任一项所述的方法。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116644071A (zh) * 2023-06-08 2023-08-25 中国长江三峡集团有限公司 一种物资编码管理方法、装置、计算机设备及存储介质

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115085739A (zh) * 2021-03-10 2022-09-20 华为技术有限公司 一种编译码方法及装置
CN117411563B (zh) * 2023-12-15 2024-03-29 北京邮电大学 基于分阶统计辅助的阶梯译码方法、装置及***

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108599775A (zh) * 2018-05-10 2018-09-28 清华大学 一种混合校验ldpc码的构造方法
CN109327225A (zh) * 2017-06-27 2019-02-12 华为技术有限公司 信息处理的方法、装置和通信设备
US20190097756A1 (en) * 2017-09-08 2019-03-28 Debdeep CHATTERJEE Method and apparatus for channel coding in the fifth generation new radio system
CN109981224A (zh) * 2019-04-04 2019-07-05 西安电子科技大学 一种深空通信信道编译码***及其方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050123336A (ko) * 2004-06-24 2005-12-29 엘지전자 주식회사 Ｌｄｐｃ 코드를 이용한 가변 코드 레이트 적응 부호화 방법
JP4177824B2 (ja) * 2005-03-16 2008-11-05 株式会社東芝 符号化方法、復号化方法および符号化システム
US8225186B2 (en) * 2006-07-14 2012-07-17 Qualcomm Incorporated Ecoding and decoding methods and apparatus for use in a wireless communication system
CN102484484B (zh) * 2009-08-25 2014-08-20 富士通株式会社 发送机、编码装置、接收机以及解码装置
US9203434B1 (en) * 2012-03-09 2015-12-01 Western Digital Technologies, Inc. Systems and methods for improved encoding of data in data storage devices
CN108347297B (zh) * 2017-01-25 2021-06-08 华为技术有限公司 一种编码方法、译码方法、编码装置及译码装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109327225A (zh) * 2017-06-27 2019-02-12 华为技术有限公司 信息处理的方法、装置和通信设备
US20190097756A1 (en) * 2017-09-08 2019-03-28 Debdeep CHATTERJEE Method and apparatus for channel coding in the fifth generation new radio system
CN108599775A (zh) * 2018-05-10 2018-09-28 清华大学 一种混合校验ldpc码的构造方法
CN109981224A (zh) * 2019-04-04 2019-07-05 西安电子科技大学 一种深空通信信道编译码***及其方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4016850A4

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116644071A (zh) * 2023-06-08 2023-08-25 中国长江三峡集团有限公司 一种物资编码管理方法、装置、计算机设备及存储介质
CN116644071B (zh) * 2023-06-08 2024-04-05 中国长江三峡集团有限公司 一种物资编码管理方法、装置、计算机设备及存储介质

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