WO2021004231A1 - 一种闪存设备中的数据存储方法及闪存设备 - Google Patents

一种闪存设备中的数据存储方法及闪存设备 Download PDF

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Publication number
WO2021004231A1
WO2021004231A1 PCT/CN2020/095985 CN2020095985W WO2021004231A1 WO 2021004231 A1 WO2021004231 A1 WO 2021004231A1 CN 2020095985 W CN2020095985 W CN 2020095985W WO 2021004231 A1 WO2021004231 A1 WO 2021004231A1
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Prior art keywords
flash memory
ftl
memory device
write operation
operation request
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PCT/CN2020/095985
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English (en)
French (fr)
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周建华
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华为技术有限公司
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Priority to EP20836504.9A priority Critical patent/EP3992801A4/en
Publication of WO2021004231A1 publication Critical patent/WO2021004231A1/zh
Priority to US17/570,958 priority patent/US20220129189A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0608—Saving storage space on storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7208—Multiple device management, e.g. distributing data over multiple flash devices

Definitions

  • the embodiments of the present application relate to the field of data storage technology, and in particular, to a data storage method in a flash memory device and a flash memory device.
  • a flash translation layer (FTL) is set between the operating system and the flash memory device.
  • FTL flash translation layer
  • the operating system first queries the FTL to determine the data storage location after receiving the access request. Obtain data from the corresponding storage location, and finally respond to the user's access request.
  • the current FTL is mainly stored in the memory space.
  • each FTL mapping unit corresponds to a 512-byte logical address.
  • each FTL mapping unit corresponds to a 512-byte logical address.
  • the above-mentioned finer-grained FTL due to the smaller granularity, results in a smaller mapping ratio between the flash memory device and the memory.
  • the mapping granularity of 512byte as an example, the corresponding mapping ratio is 125, that is, 1GB of memory can only be mapped to 125GB of flash memory. equipment. Therefore, the more fine-grained FTL corresponds to a large memory overhead, and it is difficult to meet the memory requirements of large-capacity flash memory devices. With the rapid development of large-capacity flash memory devices, memory capacity will limit the development of large-capacity flash memory devices.
  • the embodiments of the present application provide a data storage method for a flash memory device and a flash memory device, which can provide a variety of FTLs with different granularities, and flexibly configure the granularity of logical addresses, thereby reducing memory overhead and improving the memory support
  • the capacity space of the flash memory device is maximized.
  • the embodiments of the present application provide a data storage method in a flash memory device.
  • the flash memory device includes a plurality of flash conversion layer FTLs, and each FTL of the plurality of FTLs is used to record the logical address to the physical address of the flash memory.
  • the data storage method includes: firstly, receiving a write operation request; secondly, according to the received write operation request, selecting the target FTL from a variety of FTL; finally, According to the selected target FTL, a physical address is allocated from the flash memory device for the received write operation request.
  • the flash memory device contains a variety of flash translation layer FTLs, each of the multiple FTLs is used to record the mapping of logical addresses to flash physical addresses, and more The granularity of the logical addresses in each FTL is different, and according to the received write operation request, the target FTL is selected from a variety of FTLs, and the physical address is allocated from the flash memory device for the received write operation request based on the selected target FTL.
  • the above-mentioned selection of the target FTL from a variety of FTLs based on the received write operation request may specifically include: input and output IO size based on the write operation request, and information carried by the write operation request At least one of the data type, the service type for sending the write operation request, and the modification frequency of the data in the logical address corresponding to the write operation request, and the target FTL is selected from multiple FTLs.
  • the input and output IO size of the write operation request, the data type carried in the write operation request, the type of service sending the write operation request, and the modification frequency of the data in the logical address corresponding to the write operation request are the targets.
  • the FTL selection basis can more accurately select a suitable target FTL for write operation requests, so as to realize a reasonable allocation of the physical address of the flash memory device and maximize the capacity space of the flash memory device.
  • the IO size of the write operation request is respectively compared with the logical addresses in multiple FTLs Compare the size range of the written data corresponding to the granularity of each FTL.
  • the size range of the written data corresponding to the granularity of the logical address in each FTL is different; the FTL corresponding to the IO size of the write operation request meets the write data size range as the target FTL.
  • the write data size range can be set according to the granularity of the logical address in the FTL, and the granularity is the storage space size.
  • set the write data size range corresponding to the granularity of the logical address in the multiple FTLs and select the target FTL based on the set write data size range, so as to specify the IO based on the write operation request.
  • the size selects the realization method of the target FTL, which can improve the rationality and accuracy of the target FTL.
  • the foregoing allocating physical addresses from the flash memory device according to the target FTL for the write operation request may specifically include: according to the granularity of the flash memory physical address mapped by the target FTL, the write operation request from the flash memory
  • the physical address is allocated in the device.
  • the granularity of the physical address of the flash memory mapped by the target FTL can be fine-grained FTL, such as 512byte, 1KB mapping granularity, or coarse-grained FTL, such as 4KB, 8KB mapping granularity, and the FTL mapping granularity can be sector An integer multiple of the size (typical value is 512bytes).
  • physical addresses are allocated from the flash memory device through FTLs of different granularities, so that FTLs of different granularities are used in the flash memory device to reasonably allocate storage space.
  • the aforementioned data storage method may further include: after allocating a physical address for the write operation request, recording the logical address of the write operation request and the physical address allocated from the flash memory device in the target FTL.
  • Address mapping relationship The logical address may specifically be a logical block address (logic block address, LBA), and the physical address may specifically be a physical page address (physical page address, PPA).
  • LBA logic block address
  • PPA physical page address
  • the mapping relationship between the logical address of the write operation request and the physical address allocated from the flash memory device is recorded in the target FTL, so that the next time an access request to access the logical address is received, it can be quickly inquired Go to the corresponding physical address to quickly respond to the access request.
  • the embodiments of the present application provide a flash memory device.
  • the flash memory device includes a variety of flash conversion layer FTLs, each of the multiple FTLs is used to record the mapping of logical addresses to flash physical addresses, and the multiple FTLs The granularity of the logical addresses is different; the flash memory device includes: a receiving module for receiving a write operation request; a selection module for selecting a target FTL from the multiple FTLs according to the write operation request; a management module , Used to allocate a physical address from the flash memory device according to the target FTL for the write operation request.
  • the component modules of the flash memory device can also execute the steps described in the various possible implementation manners in the foregoing first aspect. For details, see the foregoing description of the first aspect and various possible implementation manners. Description, not repeat them here.
  • the embodiments of the present application provide a computer program product containing instructions, which when run on a computer, cause the computer to execute the method described in the first aspect.
  • an embodiment of the present application provides a computer-readable storage medium having instructions stored in the computer-readable storage medium, which when run on a computer, cause the computer to execute the method described in the first aspect.
  • the embodiments of the present application provide a flash memory device, the flash memory device includes a variety of flash translation layer FTL, each of the multiple FTL is used to record the mapping of logical addresses to flash physical addresses, and a variety of The granularity of logical addresses between FTLs is different; a flash memory device includes a processor and a storage medium, and the processor communicates with the storage medium; the storage medium is used to store operation instructions; the processor is used to call the The operation instruction is to execute the method described in the first aspect and any one of the implementation manners in the first aspect.
  • FIG. 1 is a schematic diagram of an embodiment of a data storage method of a flash memory device in an embodiment of the application
  • FIG. 2 is a schematic diagram of a composition structure of a flash memory device in an embodiment of the application
  • FIG. 3 is a schematic diagram of a composition structure of a flash memory device in an embodiment of the application.
  • the embodiment of the application provides a data storage method of a flash memory device and a flash memory device, which can provide multiple FTLs with different granularities, and flexibly configure the granularity of logical addresses, thereby reducing memory overhead and maximizing the capacity space of the flash memory device that the memory can support ⁇ .
  • the data storage method of the flash memory device in the embodiment of the present application is applicable to flash memory devices, such as NAND flash memory Flash chips, solid state drives (SSD) using NAND flash memory Flash chips as storage media, and other flash memory devices.
  • flash memory devices such as NAND flash memory Flash chips, solid state drives (SSD) using NAND flash memory Flash chips as storage media, and other flash memory devices.
  • SSD solid state drives
  • FIG. 1 is a schematic diagram of an embodiment of a data storage method of a flash memory device in an embodiment of the application.
  • the data storage method of the flash memory device in the embodiment of the present application includes:
  • the flash memory device receives a write operation request.
  • the flash memory device receives the write operation request, and the write operation request may be generated and issued by the operating system based on the user's access request after the user initiates the access request.
  • the flash memory device described in the embodiments of the present application includes multiple flash translation layers (FTL), and each FTL of the multiple FTLs is used to record the mapping of logical addresses to physical addresses of the flash memory.
  • FTL flash translation layers
  • the granularity of the logical address between the FTLs is different, and the multiple FTLs are all located in the memory. It should be understood that the granularity of logical addresses in FTL is the logical block size in FTL.
  • the granularity of the logical address of the FTL is 4KB
  • the size of the logical block corresponding to an FTL mapping unit or FTL mapping item is 4KB
  • one of the FTL mapping items occupies 32 bits (ie 4Bytes) of memory space in the memory
  • the granularity of the logical address of the FTL may also be 512Bytes, 8KB or 16KB, etc.
  • the granularity of the logical address of the FTL in the embodiment of the present application may be an integer multiple of the sector size (512Bytes).
  • the granularity of the logical address of FTL is 4KB and 8KB. If the write data is 16KB, and the FTL with a logical address of 4KB granularity is used, 4 FTL mapping items are required for mapping. Take an FTL mapping item of 32 bits as an example.
  • the corresponding memory space occupied by the written data is 128 bits; the FTL with a logical address of 8KB granularity requires only 2 FTL mapping items for mapping. Take an FTL mapping item with 32 bits as an example.
  • the memory space occupied by the data is 64 bits, which reduces the memory overhead by half.
  • the flash memory device selects a target FTL from multiple FTLs according to the write operation request.
  • the flash memory device selects the target FTL from a variety of FTLs according to the received write operation request.
  • the above-mentioned selection of the target FTL may be based on, but is limited to: the input and output IO size of the write operation request, the data type carried in the write operation request, the service type for sending the write operation request, and the write operation At least one of the frequency of modification of the data in the corresponding logical address is requested, and the target FTL is selected from a plurality of FTLs.
  • the logical address granularity of the first FTL is 512Bytes; the logical address granularity of the second FTL is 4KB, and the logical address granularity of the third FTL is 8KB.
  • the target FTL selection methods can include but are not limited to the following:
  • the first target FTL selection method select the target FTL based on the input and output IO size of the write operation request.
  • the size range of the written data corresponding to the granularity of the logical address in the first FTL is: less than or equal to 512Bytes;
  • the size range of the write data corresponding to the granularity of the logical address in the second FTL is: greater than 512Bytes and less than or Equal to 4KB;
  • the size range of the written data corresponding to the granularity of the logical address in the third FTL is greater than 4KB.
  • the second target FTL selection method select the target FTL based on the data type carried in the write operation request.
  • the modification units corresponding to metadata are generally of small granularity (such as 512byte) and are frequently modified, while user data generally have large modification units (such as 8KB). If the data type is metadata, then the first FTL whose logical address granularity is 512Bytes is selected as the target FTL; if the data type is user data, the third FTL whose logical address granularity is 8KB is selected as the target FTL.
  • the third target FTL selection method select the target FTL based on the type of service sending the write operation request.
  • video recording services generally correspond to large IO such as 1MB
  • log online services generally correspond to small IO such as 512byte
  • online transaction services generally correspond to Larger IO such as 8KB.
  • the third FTL with a logical address granularity of 8KB is selected as the target FTL.
  • the first FTL with a logical address granularity of 512Bytes is selected as the target FTL.
  • the fourth target FTL selection method the target FTL is selected based on the modification frequency of the data in the logical address corresponding to the write operation request.
  • Cold data refers to data whose corresponding data modification frequency is lower than the threshold, and cold data has low data activity; hot data refers to data whose corresponding data modification frequency is higher than the threshold.
  • Data activity is high.
  • the third FTL with a logical address granularity of 8KB can be selected as the target FTL, or the second FTL with a logical address granularity of 4KB can be selected as the target FTL; for data active
  • the first FTL with a logical address of 512Bytes can be selected as the target FTL.
  • the flash memory device allocates a physical address from the flash memory device according to the target FTL for the write operation request.
  • the foregoing allocating physical addresses from the flash memory device for the write operation request according to the target FTL may specifically include, but is not limited to, allocating physical addresses from the flash memory device for the write operation request according to the granularity of the flash memory physical address mapped by the target FTL.
  • the target FTL is the first type of FTL with a logical address granularity of 512Bytes
  • a physical address is allocated for the write operation request based on the mapping relationship of one FTL mapping item to a logical block of 512Bytes
  • the target FTL is a logical address
  • a physical address is allocated for the write operation request based on the mapping relationship between an FTL mapping item corresponding to a 4KB logical block
  • the target FTL is the third FTL with a logical address granularity of 8KB
  • the mapping relationship of an FTL mapping item to an 8KB logical block allocates a physical address for a write operation request.
  • the above-mentioned logical block can be a logical block address (logic block address, LBA), and the physical address can be a physical page address (physical page address, PPA), where LBA is a logical address or logical space in a flash memory device; PPA is a flash memory The physical address or physical space in the device.
  • the above-mentioned flash memory device allocates a physical address from the flash memory device according to the target FTL for the write operation request, specifically: the flash memory device allocates memory space for the write operation request according to the granularity of the logical address of the target FTL, and maps the memory space in the flash memory device Convert LBA to PPA.
  • the flash memory device records the mapping relationship between the logical address of the write operation request and the physical address allocated from the flash memory device in the target FTL.
  • the mapping relationship between the logical address of the write operation request and the physical address allocated from the flash memory device is recorded in the target FTL.
  • the flash memory device adds a new mapping item to the mapping table corresponding to the target FTL, and the newly added mapping item is used to record the correspondence between the LBA and the PPA of the write operation request.
  • multiple flash conversion layer FTLs are provided in the flash memory device, each of the multiple FTLs is used to record the mapping of logical addresses to the physical addresses of the flash memory, and the logical addresses between the multiple FTLs
  • the granularity is different, and according to the received write operation request, the target FTL is selected from multiple FTLs, and the physical address is allocated from the flash memory device for the received write operation request based on the selected target FTL. Therefore, the technical solution of this application can Provides a variety of FTL with different granularities, and flexibly configures the granularity of logical addresses, thereby reducing memory overhead and maximizing the capacity of flash memory devices that the memory can support.
  • multiple FTL access modes of logical addresses with different granularities can be provided at the same time, such as fine-grained mapping area (each FTL mapping item corresponds to 512Byte data logical address) and coarse-grained mapping area (each FTL mapping item corresponds to the logical address of 8KB data), store the data in the fine-grained mapping area, when the actual modification, directly modify the corresponding content, the actual amount of data written and the user
  • the ratio between the amount of data that needs to be written that is, the Write Amplification Factor (WAF) is very small, the actual response speed is very fast, and the wear on the flash memory device is as low as possible, which extends the service life of the flash memory device.
  • WAF Write Amplification Factor
  • User data is stored in the coarse-grained mapping area, which reduces the number of FTL mapping items and saves memory usage space, so that a flash memory device with a larger capacity space can be mapped with a
  • FIG. 2 is a schematic diagram of a composition structure of a flash memory device in an embodiment of this application.
  • the flash memory device 200 includes: a receiving module 201, a selection module 202, and a management module 203; among them, the flash memory device 200 includes multiple flash memory conversion layer FTLs, and each of the multiple FTLs is used to record a logical address to a flash memory physical Address mapping, and the granularity of the logical addresses between the multiple FTLs are different; the receiving module 201 is used to receive write operation requests; the selection module 202 is used to select targets from multiple FTLs according to the received write operation requests FTL; the management module 203 is configured to allocate a physical address from the flash memory device for the received write operation request according to the selected target FTL.
  • the selection module 202 is specifically configured to: based on the input and output IO size of the write operation request, the data type carried in the write operation request, the service type for sending the write operation request, and the logic corresponding to the write operation request At least one item of the frequency of modification of the data in the address, the target FTL is selected from a plurality of FTLs.
  • the selection module 202 is specifically configured to: compare the IO size of the write operation request with the write data size range corresponding to the granularity of the logical address in various FTLs.
  • the size range of the write data corresponding to the granularity of the logical address in the FTL is different; the FTL corresponding to the IO size of the write operation request that meets the size range of the write data is used as the target FTL.
  • the management module 203 is specifically configured to allocate a physical address from the flash memory device for a write operation request according to the granularity of the physical address of the flash memory mapped by the target FTL.
  • the flash memory device 200 further includes a recording module 204; the recording module 204 is configured to record the logical address of the write operation request and the slave flash memory in the target FTL after allocating a physical address for the write operation request The mapping relationship of the physical addresses allocated in the device.
  • An embodiment of the present application further provides a computer storage medium, wherein the computer storage medium stores a program, and the program executes a part or all of the steps recorded in the foregoing method embodiment.
  • FIG. 3 is a schematic diagram of another composition structure of a flash memory device in an embodiment of the application.
  • the flash memory device 300 includes: a processor 301 and a memory 302, where the number of processors 301 may be one or more, and one processor is taken as an example in FIG.
  • the memory 302 may include a read-only memory and a random access memory, and provides instructions and data to the processor 301. A part of the memory 302 may also include a non-volatile random access memory (NVRAM).
  • NVRAM non-volatile random access memory
  • the memory 302 stores operating instructions, executable modules or data structures, or a subset of them, or an extended set of them.
  • the processor 301 controls the operation of the flash memory device, and the processor 301 may also be referred to as a central processing unit (CPU).
  • the various components of the flash memory device are coupled together through a bus system, where the bus system may include a power bus, a control bus, and a status signal bus in addition to a data bus.
  • bus system may include a power bus, a control bus, and a status signal bus in addition to a data bus.
  • various buses are referred to as bus systems in the figure.
  • the method disclosed in the foregoing embodiments of the present application may be applied to the processor 301 or implemented by the processor 301.
  • the processor 301 may be an integrated circuit chip with signal processing capability. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor 301 or instructions in the form of software.
  • the aforementioned processor 301 may be a general-purpose processor, a digital signal processing (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or Other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • DSP digital signal processing
  • ASIC application specific integrated circuit
  • FPGA field-programmable gate array
  • the methods, steps, and logical block diagrams disclosed in the embodiments of the present application can be implemented or executed.
  • the general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed and completed by a hardware decoding processor, or executed and completed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a mature storage medium in the field such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers.
  • the storage medium is located in the memory 302, and the processor 301 reads the information in the memory 302, and completes the steps of the foregoing method in combination with its hardware.
  • the chip includes a processing unit and a communication unit.
  • the processing unit may be, for example, a processor, and the communication unit may be, for example, an input/output interface, a pin, or a circuit.
  • the processing unit can execute the computer-executable instructions stored in the storage unit, so that the chip in the terminal executes the wireless communication method of any one of the foregoing first aspect.
  • the storage unit is a storage unit in the chip, such as a register, a cache, etc., and the storage unit may also be a storage unit in the terminal located outside the chip, such as a read-only memory (read-only memory). -only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (RAM), etc.
  • processor mentioned in any of the foregoing may be a general-purpose central processing unit, microprocessor, ASIC, FPGA, CPLD, or one or more integrated circuits used to control the execution of the program of the foregoing first aspect method.
  • the device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physically separate
  • the physical unit can be located in one place or distributed across multiple network units. Some or all of the modules may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the connection relationship between the modules indicates that they have a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines.
  • this application can be implemented by means of software plus necessary general hardware.
  • it can also be implemented by dedicated hardware including dedicated integrated circuits, dedicated CPUs, dedicated memory, Dedicated components and so on to achieve.
  • all functions completed by computer programs can be easily implemented with corresponding hardware.
  • the specific hardware structure used to achieve the same function can also be diverse, such as analog circuits, digital circuits or dedicated Circuit etc.
  • software program implementation is a better implementation in more cases.
  • the technical solution of this application essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product is stored in a readable storage medium, such as a computer floppy disk. , U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk, etc., including several instructions to make a computer device (which can be a personal computer, server, or network device, etc.) execute the methods described in each embodiment of this application .
  • a computer device which can be a personal computer, server, or network device, etc.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium.
  • the computer instructions may be transmitted from a website, computer, server, or data center. Transmission to another website site, computer, server or data center via wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.).
  • wired such as coaxial cable, optical fiber, digital subscriber line (DSL)
  • wireless such as infrared, wireless, microwave, etc.
  • the computer-readable storage medium may be any available medium that can be stored by a computer or a data storage device such as a server or data center integrated with one or more available media.
  • the usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, and a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)).

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Abstract

一种闪存设备的数据存储方法及闪存设备，可以提供多种不同粒度的FTL，灵活配置逻辑地址的粒度，从而降低内存开销，将内存可支持的闪存设备的容量空间最大化。该闪存设备包含多种闪存转换层FTL，多种FTL中的每一种FTL用于记录逻辑地址到闪存物理地址的映射，并且多种FTL之间的逻辑地址的粒度均不同，该数据存储方法包括：首先，接收写操作请求；其次，根据接收到的写操作请求，从多种FTL中选择目标FTL；最后，根据选择的目标FTL为接收到的写操作请求从闪存设备中分配物理地址。

Description

一种闪存设备中的数据存储方法及闪存设备 技术领域
本申请实施例涉及数据存储技术领域，尤其涉及一种闪存设备中的数据存储方法及闪存设备。
背景技术
由于闪存设备具有特殊的数据读写特性，导致操作***无法直接管理闪存设备。在操作***和闪存设备之间设置闪存转换层(flash translation layer，FTL)，当用户访问闪存设备中的数据时，操作***在接收到访问请求之后，先查询FTL确定数据存储位置，进而在从相应的存储位置中获取数据，最后相应用户的访问请求。为了保证闪存设备的响应速度，当前的FTL主要存放于内存空间中。
通常采用较细粒度的FTL，以512byte的映射粒度为例，即每个FTL映射单元对应512byte的逻辑地址。当用户写入新数据时，可以直接寻找新的物理空间存放，并修改对应FTL映射单元映射至新的物理地址即可。
上述采用较细粒度的FTL，由于粒度较小，导致闪存设备与内存之间的映射比值较小，以512byte的映射粒度为例，相应的映射比值为125，即1GB内存只能映射125GB的闪存设备。因此，较细粒度的FTL对应的内存开销较大，难以满足大容量闪存设备对内存的需求，随着大容量闪存设备的快速发展，内存容量将限制大容量闪存设备的发展。
发明内容
为了解决以上技术问题，本申请实施例提供了一种闪存设备的数据存储方法及闪存设备，可以提供多种不同粒度的FTL，灵活配置逻辑地址的粒度，从而降低内存开销，将内存可支持的闪存设备的容量空间最大化。
第一方面，本申请实施例提供了一种闪存设备中的数据存储方法，该闪存设备包含多种闪存转换层FTL，多种FTL中的每一种FTL用于记录逻辑地址到闪存物理地址的映射，并且多种FTL之间的逻辑地址的粒度均不同，该数据存储方法包括：首先，接收写操作请求；其次，根据接收到的写操作请求，从多种FTL中选择目标FTL；最后，根据选择的目标FTL为接收到的写操作请求从闪存设备中分配物理地址。
从上述第一方面的技术方案中可以看出具有以下优点：该闪存设备包含多种闪存转换层FTL，多种FTL中的每一种FTL用于记录逻辑地址到闪存物理地址的映射，并且多种FTL中的逻辑地址的粒度均不同，并根据接收到的写操作请求，从多种FTL中选择目标FTL，基于选择的目标FTL为接收到的写操作请求从闪存设备中分配物理地址，因此，可以提供多种不同粒度的FTL，灵活配置逻辑地址的粒度，从而降低内存开销，将内存可支持的闪存设备的容量空间最大化。
在第一方面的一些可能的实现方式中，上述的根据接收到的写操作请求，从多种FTL中选择目标FTL，具体可以包括：基于写操作请求的输入输出IO大小、写操作请求携带的数据类型、发送写操作请求的业务类型、写操作请求对应的逻辑地址中的数据的修改频率中的至少一项，从多种FTL中选择目标FTL。在该种可能的实现方式中，将写操作请求的 输入输出IO大小、写操作请求携带的数据类型、发送写操作请求的业务类型、写操作请求对应的逻辑地址中的数据的修改频率作为目标FTL的选择依据，可以更加准确地为写操作请求选择合适的目标FTL，从而实现对闪存设备物理地址的合理分配，最大化闪存设备的容量空间。
在第一方面的一些可能的实现方式中，若基于写操作请求的IO大小实现对目标FTL的选择，则具体可以采用如下方式：将写操作请求的IO大小分别与多种FTL中的逻辑地址的粒度对应的写入数据大小范围进行比较，其中每种FTL中的逻辑地址的粒度对应的写入数据大小范围均不同；将写操作请求的IO大小满足写入数据大小范围对应的FTL作为目标FTL。应理解，写入数据大小范围可以依据FTL中的逻辑地址的粒度进行设置，粒度即为存储空间大小。在该种可能的实现方式中，设置多种FTL中的逻辑地址的粒度对应的写入数据大小范围并基于设置的写入数据大小范围对目标FTL进行选择，以具体化基于写操作请求的IO大小选择目标FTL的实现方式，此种实现方式可以提高目标FTL的合理性以及准确性。
在第一方面的一些可能的实现方式中，上述的根据目标FTL为写操作请求从闪存设备中分配物理地址具体可以包括：根据目标FTL所映射闪存物理地址的粒度为写操作请求从所述闪存设备中分配物理地址。其中目标FTL所映射闪存物理地址的粒度可以是细粒度的FTL，例如512byte、1KB的映射粒度，也可以是粗粒度的FTL，例如4KB、8KB的映射粒度，其FTL的映射粒度可以是扇区大小(典型值为512bytes)的整数倍。在该种可能的实现方式中，通过不同粒度的FTL从闪存设备中分配物理地址，从而实现闪存设备中采用不同粒度的FTL进行存储空间的合理分配。
在第一方面的一些可能的实现方式中，上述的数据存储方法还可以包括：在为写操作请求分配物理地址之后，在目标FTL中记录写操作请求的逻辑地址与从闪存设备中分配的物理地址的映射关系。其中逻辑地址具体可以是逻辑块地址(logic block address，LBA)，物理地址具体可以是物理页地址(physical page address，PPA)。在该种可能的实现方式中，在目标FTL中记录写操作请求的逻辑地址与从闪存设备中分配的物理地址的映射关系，便于下次接收到访问该逻辑地址的访问请求时，可以快速查询到相应的物理地址，实现对访问请求的快速相应。
第二方面，本申请实施例提供了一种闪存设备，闪存设备包含多种闪存转换层FTL，多种FTL中的每一种FTL用于记录逻辑地址到闪存物理地址的映射，并且多种FTL之间的逻辑地址的粒度均不同；该闪存设备包括：接收模块，用于接收写操作请求；选择模块，用于根据所述写操作请求，从所述多种FTL中选择目标FTL；管理模块，用于根据所述目标FTL为所述写操作请求从所述闪存设备中分配物理地址。
在本申请的第二方面中，闪存设备的组成模块还可以执行前述第一方面中各种可能的实现方式中所描述的步骤，详见前述对第一方面以及各种可能的实现方式中的说明，此处不再赘述。
第三方面，本申请实施例提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第一方面所述的方法。
第四方面，本申请实施例提供了一种计算机可读存储介质，所述计算机可读存储介质 中存储有指令，当其在计算机上运行时，使得计算机执行上述第一方面所述的方法。
第五方面，本申请实施例提供了一种闪存设备，该闪存设备包含多种闪存转换层FTL，多种FTL中的每一种FTL用于记录逻辑地址到闪存物理地址的映射，并且多种FTL之间的逻辑地址的粒度均不同；闪存设备包括处理器和存储介质，所述处理器与所述存储介质通信；所述存储介质用于存储操作指令；所述处理器用于通过调用所述操作指令以执行上述第一方面以及第一方面中的任意一种实现方式中所述的方法。
附图说明
图1为本申请实施例中闪存设备的数据存储方法的一个实施例示意图；
图2为本申请实施例中闪存设备的一个组成结构示意图；
图3为本申请实施例中闪存设备的一个组成结构示意图。
具体实施方式
本申请实施例提供了一种闪存设备的数据存储方法及闪存设备，可以提供多种不同粒度的FTL，灵活配置逻辑地址的粒度，从而降低内存开销，将内存可支持的闪存设备的容量空间最大化。
下面结合附图，对本申请的实施例进行描述。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的术语在适当情况下可以互换，这仅仅是描述本申请的实施例中对相同属性的对象在描述时所采用的区分方式。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，以便包含一系列单元的过程、方法、***、产品或设备不必限于那些单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它单元。
本申请实施例中的闪存设备的数据存储方法，适用于闪存设备中，例如NAND闪存Flash芯片、以NAND闪存Flash芯片为存储介质的固态驱动器(solid state drive，SSD)等闪存设备中。
为了便于理解本申请实施例中的数据存储方法，下面将结合具体的实施例进行详细说明。
图1为本申请实施例中闪存设备的数据存储方法的一个实施例示意图。
如图1所示，本申请实施例中闪存设备的数据存储方法包括：
101、闪存设备接收写操作请求。
闪存设备接收写操作请求，该写操作请求可以是由用户发起访问请求后，操作***基于用户的访问请求生成并发出的。
本申请实施例中所述的闪存设备中包括多种闪存转换层(flash translation layer，FTL)，该多种FTL中的每一种FTL用于记录逻辑地址到闪存物理地址的映射，并且该多种FTL之间的逻辑地址的粒度均不同，该多种FTL均位于内存中。应理解，FTL中的逻辑地址的粒度即是FTL中的逻辑块大小。
举例来说，如果FTL的逻辑地址的粒度为4KB，则一个FTL映射单元或者说FTL映射项对应的逻辑块大小为4KB，其中一个FTL映射项占用内存中32比特(即4Bytes)的内存 空间；相应的，FTL的逻辑地址的粒度还可以是512Bytes、8KB或16KB等，本申请实施例中FTL的逻辑地址的粒度可以是扇区大小(512Bytes)的整数倍。
对于不同粒度的逻辑地址的FTL而言，FTL的逻辑地址的粒度越大，逻辑块越大，FTL的项越少，占用的内存空间越小；FTL的逻辑地址的粒度越小，逻辑块越小，FTL的映射项越多，占用的内存空间越大。例如FTL的逻辑地址的粒度为4KB和8KB，若写入数据为16KB，采用4KB粒度的逻辑地址的FTL，则需要4个FTL映射项进行映射，以一个FTL映射项为32比特为例，此时该写入数据对应占用的内存空间为128比特；采用8KB粒度的逻辑地址的FTL，则只需要2个FTL映射项进行映射，以一个FTL映射项为32比特为例，此时该写入数据对应占用的内存空间为64比特，减少了一半的内存开销。
102、闪存设备根据写操作请求，从多种FTL中选择目标FTL。
闪存设备根据接收到的写操作请求，从多种FTL中选择目标FTL。
在本申请实施例的一些实施例方式中，上述的目标FTL的选择可以基于但限于：写操作请求的输入输出IO大小、写操作请求携带的数据类型、发送写操作请求的业务类型、写操作请求对应的逻辑地址中的数据的修改频率中的至少一项，从多种FTL中选择目标FTL。
具体来说，以三种FTL为例，第一种FTL的逻辑地址粒度为512Bytes；第二种FTL的逻辑地址的粒度为4KB，第三种FTL的逻辑地址的粒度为8KB。目标FTL选择方式可以包括但不限于以下几种：
1)、第一种目标FTL选择方式：基于写操作请求的输入输出IO大小选择目标FTL。
将写操作请求的IO大小分别与多种FTL中的逻辑地址的粒度对应的写入数据大小范围进行比较，其中每种FTL中的逻辑地址的粒度对应的写入数据大小范围均不同；将写操作请求的IO大小满足写入数据大小范围对应的FTL作为目标FTL。
例如，第一种FTL中的逻辑地址的粒度对应的写入数据大小范围为：小于或等于512Bytes；第二种FTL中的逻辑地址的粒度对应的写入数据大小范围为：大于512Bytes且小于或等于4KB；第三种FTL中的逻辑地址的粒度对应的写入数据大小范围为：大于4KB。容易理解，当写操作请求的IO大小小于或等于512Bytes时，选择逻辑地址的粒度为512Bytes的第一种FTL作为目标FTL；当写操作请求的IO大小大于512Bytes且小于或等于4KB时，选择逻辑地址的粒度为4KB的第二种FTL作为目标FTL；当写操作请求的IO大小大于4KB时，选择逻辑地址的粒度为8KB的第三种FTL作为目标FTL。
2)、第二种目标FTL选择方式：基于写操作请求携带的数据类型选择目标FTL。
以数据类型为元数据和用户数据，根据经验可知，元数据对应的修改单元一般都是小粒度(如512byte)并且修改频繁，而用户数据一般修改单元较大(如8KB)。若数据类型为元数据，则选择上述逻辑地址的粒度为512Bytes的第一种FTL作为目标FTL；若数据类型为用户数据，则选择上述逻辑地址的粒度为8KB的第三种FTL作为目标FTL。
3)、第三种目标FTL选择方式：基于发送写操作请求的业务类型选择目标FTL。
以视频记录业务、日志在线业务和在线交易业务三种业务类型为例，一般来说，视频记录业务一般对应的大IO如1MB，日志在线业务一般对应的小IO如512byte，在线交易业务一般对应较大IO如8KB。对于视频记录业务和在线交易业务，选择逻辑地址的粒度为8KB的第三种FTL作为目标FTL。对于日志在线业务，选择逻辑地址的粒度为512Bytes的第 一种FTL作为目标FTL。
4)、第四种目标FTL选择方式：基于写操作请求对应的逻辑地址中的数据的修改频率选择目标FTL。
以冷数据和热数据为例，其中冷数据是指对应的数据修改频率低于阈值的数据，冷数据的数据活跃度较低；热数据是指对应的数据修改频率高于阈值的数据，热数据的数据活跃度较高。对于数据活跃度较低的冷数据，可以选择逻辑地址的粒度为8KB的第三种FTL作为目标FTL，或者，也可以选择逻辑地址的粒度为4KB的第二种FTL作为目标FTL；对于数据活跃度较高的热数据，可以选择逻辑地址睥粒度为512Bytes的第一种FTL作为目标FTL。
103、闪存设备根据目标FTL为写操作请求从闪存设备中分配物理地址。
上述的根据目标FTL为写操作请求从闪存设备中分配物理地址具体可以包括但不限于：根据目标FTL所映射闪存物理地址的粒度为写操作请求从所述闪存设备中分配物理地址。
具体来说，若目标FTL为逻辑地址的粒度为512Bytes的第一种FTL，则以一个FTL映射项对应512Bytes大小的逻辑块的映射关系为写操作请求分配物理地址；若目标FTL为逻辑地址的粒度为4KB的第二种FTL，则以一个FTL映射项对应4KB大小的逻辑块的映射关系为写操作请求分配物理地址；若目标FTL为逻辑地址的粒度为8KB的第三种FTL，则以一个FTL映射项对应8KB大小的逻辑块的映射关系为写操作请求分配物理地址。
上述的逻辑块具体可以是逻辑块地址(logic block address，LBA)，物理地址具体可以是物理页地址(physical page address，PPA)，其中LBA为闪存设备中的逻辑地址或逻辑空间；PPA为闪存设备中的物理地址或物理空间。上述的闪存设备根据目标FTL为写操作请求从闪存设备中分配物理地址具体可以是：闪存设备根据目标FTL的逻辑地址的粒度为写操作请求分配内存空间，并在闪存设备中将内存空间映射后的LBA转换PPA。
可选的，104、闪存设备在目标FTL中记录写操作请求的逻辑地址与从闪存设备中分配的物理地址的映射关系。
在为写操作请求分配物理地址之后，在目标FTL中记录写操作请求的逻辑地址与从闪存设备中分配的物理地址的映射关系。具体来说，闪存设备在目标FTL对应的映射表中新增加映射项，新增加的映射项用于记录写操作请求的LBA与PPA之间的对应关系。
在本申请实施例中，通过在闪存设备中设置多种闪存转换层FTL，多种FTL中的每一种FTL用于记录逻辑地址到闪存物理地址的映射，并且多种FTL之间的逻辑地址的粒度均不同，并根据接收到的写操作请求，从多种FTL中选择目标FTL，基于选择的目标FTL为接收到的写操作请求从闪存设备中分配物理地址，因此，本申请技术方案可以提供多种不同粒度的FTL，灵活配置逻辑地址的粒度，从而降低内存开销，将内存可支持的闪存设备的容量空间最大化。
进一步，与现有单一FTL管理粒度相比，本申请实施例中在同一个闪存设备中可以同时提供多种不同粒度的逻辑地址的FTL访问方式，如细粒度映射区(每个FTL映射项对应512Byte数据的逻辑地址)和粗粒度映射区(每个FTL映射项对应8KB数据的逻辑地址)，将数据存放于细粒度映射区，实际修改时，直接修改相应内容，实际写入数据量与用户需 要写入数据量之间的比值即写放大因子(Write Amplification Factor，WAF)非常小，实际响应速度很快，并且对闪存设备的磨损也尽可能低，延长了闪存设备的使用寿命。用户数据存放于粗粒度映射区，减小了FTL映射项数，节约内存的使用空间，从而可以在有限的内存容量下可以映射更大容量空间的闪存设备。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请并不受所描述的动作顺序的限制，因为依据本申请，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例所涉及的动作和模块并不一定是本申请所必须的。
为便于更好的实施本申请实施例的上述方案，下面还提供用于实施上述方案的相关装置。
请参阅图2所示，为本申请实施例中闪存设备的一个组成结构示意图。
闪存设备200包括：接收模块201、选择模块202和管理模块203；其中，闪存设备200中包括多种闪存转换层FTL，所述多种FTL中的每一种FTL用于记录逻辑地址到闪存物理地址的映射，并且所述多种FTL之间的逻辑地址的粒度均不同；接收模块201用于接收写操作请求；选择模块202用于根据接收到的写操作请求，从多种FTL中选择目标FTL；管理模块203用于根据选择的目标FTL为接收到的写操作请求从闪存设备中分配物理地址。
在本申请实施例的一些实施例方式中，选择模块202具体用于：基于写操作请求的输入输出IO大小、写操作请求携带的数据类型、发送写操作请求的业务类型、写操作请求对应逻辑地址中的数据的修改频率中的至少一项，从多种FTL中选择目标FTL。
在本申请实施例的一些实施例方式中，选择模块202具体用于：将写操作请求的IO大小分别与多种FTL中的逻辑地址的粒度对应的写入数据大小范围进行比较，其中每种FTL中的逻辑地址的粒度对应的写入数据大小范围均不同；将写操作请求的IO大小满足写入数据大小范围对应的FTL作为目标FTL。
在本申请实施例的一些实施例方式中，管理模块203具体用于：根据目标FTL所映射闪存物理地址的粒度为写操作请求从所述闪存设备中分配物理地址。
在本申请实施例的一些实施例方式中，闪存设备200还包括记录模块204；记录模块204用于在为写操作请求分配物理地址之后，在目标FTL中记录写操作请求的逻辑地址与从闪存设备中分配的物理地址的映射关系。
需要说明的是，上述方法实施例中闪存设备执行的所有步骤以及操作均可以援引到闪存设备200的各个组成模块中进行执行。本申请实施例中闪存设备200所取得的有益效果与上述方法实施例中所述的有益效果类似，其详细描述可参阅上述方法实施例中相关部分的描述，此处不再赘述。
还需要说明的是，上述装置各模块/单元之间的信息交互、执行过程等内容，由于与本申请方法实施例基于同一构思，其带来的技术效果与本申请方法实施例相同，具体内容可参见本申请前述所示的方法实施例中的叙述，此处不再赘述。
本申请实施例还提供一种计算机存储介质，其中，该计算机存储介质存储有程序，该程序执行包括上述方法实施例中记载的部分或全部步骤。
接下来介绍本申请实施例中提供的另一种结构的闪存设备。
图3为本申请实施例中闪存设备的另一个组成结构示意图。
如图3所示，闪存设备300包括：处理器301和存储器302，其中处理器301的数量可以是一个或多个，图3中以一个处理器为例。
其中存储器302可以包括只读存储器和随机存取存储器，并向处理器301提供指令和数据。存储器302的一部分还可以包括非易失性随机存取存储器(non-volatile random access memory，NVRAM)。存储器302存储有操作指令、可执行模块或者数据结构，或者它们的子集，或者它们的扩展集。
处理器301控制闪存设备的操作，处理器301还可以称为中央处理单元(central processing unit，CPU)。具体的应用中，闪存设备的各个组件通过总线***耦合在一起，其中总线***除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都称为总线***。
上述本申请实施例揭示的方法可以应用于处理器301中，或者由处理器301实现。处理器301可以是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器301中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器301可以是通用处理器、数字信号处理器(digital signal processing，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field-programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器302，处理器301读取存储器302中的信息，结合其硬件完成上述方法的步骤。
在另一种可能的设计中，芯片包括：处理单元和通信单元，所述处理单元例如可以是处理器，所述通信单元例如可以是输入/输出接口、管脚或电路等。该处理单元可执行存储单元存储的计算机执行指令，以使该终端内的芯片执行上述第一方面任意一项的无线通信方法。可选地，所述存储单元为所述芯片内的存储单元，如寄存器、缓存等，所述存储单元还可以是所述终端内的位于所述芯片外部的存储单元，如只读存储器(read-only memory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器(random access memory，RAM)等。
其中，上述任一处提到的处理器，可以是一个通用中央处理器，微处理器，ASIC，FPGA，CPLD或一个或多个用于控制上述第一方面方法的程序执行的集成电路。
另外需说明的是，以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。另外，本申请提供的装 置实施例附图中，模块之间的连接关系表示它们之间具有通信连接，具体可以实现为一条或多条通信总线或信号线。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本申请可借助软件加必需的通用硬件的方式来实现，当然也可以通过专用硬件包括专用集成电路、专用CPU、专用存储器、专用元器件等来实现。一般情况下，凡由计算机程序完成的功能都可以很容易地用相应的硬件来实现，而且，用来实现同一功能的具体硬件结构也可以是多种多样的，例如模拟电路、数字电路或专用电路等。但是，对本申请而言更多情况下软件程序实现是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在可读取的存储介质中，如计算机的软盘、U盘、移动硬盘、ROM、RAM、磁碟或者光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述的方法。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。
所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存储的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘(solid state disk，SSD))等。

Claims (11)

  1. 一种闪存设备中的数据存储方法，其特征在于，所述闪存设备包含多种闪存转换层FTL，所述多种FTL中的每一种FTL用于记录逻辑地址到闪存物理地址的映射，并且所述多种FTL之间的逻辑地址的粒度均不同，所述方法包括：
    接收写操作请求；
    根据所述写操作请求，从所述多种FTL中选择目标FTL；
    根据所述目标FTL为所述写操作请求从所述闪存设备中分配物理地址。
  2. 根据权利要求1所述的方法，其特征在于，所述根据所述写操作请求，从所述多种FTL中选择目标FTL，包括：
    根据所述写操作请求的输入输出IO大小、所述写操作请求携带的数据类型、发送所述写操作请求的业务类型和所述写操作请求对应的逻辑地址中的数据的修改频率中的至少一项，从所述多种FTL中选择所述目标FTL。
  3. 根据权利要求2所述的方法，其特征在于，所述根据所述写操作请求的输入输出IO大小，从所述多种FTL中选择所述目标FTL，包括：
    将所述写操作请求的IO大小在所述多种FTL中的逻辑地址的粒度对应的写入数据大小范围内的FTL确定为所述目标FTL，每种FTL中的逻辑地址的粒度对应的写入数据大小范围均不同。
  4. 根据权利要求1至3中任一项所述的方法，其特征在于，所述根据所述目标FTL为所述写操作请求从所述闪存设备中分配物理地址，包括：
    根据目标FTL所映射闪存物理地址的粒度为所述写操作请求从所述闪存设备中分配物理地址。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，所述方法还包括：
    在所述目标FTL中记录所述写操作请求的逻辑地址与从所述闪存设备中分配的物理地址的映射关系。
  6. 一种闪存设备，其特征在于，所述闪存设备包含多种闪存转换层FTL，所述多种FTL中的每一种FTL用于记录逻辑地址到闪存物理地址的映射，并且所述多种FTL之间的逻辑地址的粒度均不同；所述闪存设备包括：
    接收模块，用于接收写操作请求；
    选择模块，用于根据所述写操作请求，从所述多种FTL中选择目标FTL；
    管理模块，用于根据所述目标FTL为所述写操作请求从所述闪存设备中分配物理地址。
  7. 根据权利要求6所述的闪存设备，其特征在于，所述选择模块具体用于：
    根据所述写操作请求的输入输出IO大小、所述写操作请求携带的数据类型、发送所述写操作请求的业务类型和所述写操作请求对应的逻辑地址中的数据的修改频率中的至少一项，从所述多种FTL中选择所述目标FTL。
  8. 根据权利要求7所述的闪存设备，其特征在于，所述选择模块具体用于：
    将所述所述写操作请求的IO大小在所述多种FTL中的逻辑地址的粒度对应的写入数据 大小范围内的FTL确定为所述目标FTL，每种FTL中的逻辑地址的粒度对应的写入数据大小范围均不同。
  9. 根据权利要求6至8中任一项所述的闪存设备，其特征在于，所述管理单元具体用于：
    根据目标FTL所映射闪存物理地址的粒度为所述写操作请求从所述闪存设备中分配物理地址。
  10. 根据权利要求6至9中任一项所述的闪存设备，其特征在于，所述闪存设备还包括记录模块；
    所述记录模块，用于在所述目标FTL中记录所述写操作请求的逻辑地址与从所述闪存设备中分配的物理地址的映射关系。
  11. 一种闪存设备，其特征在于，所述闪存设备包含多种闪存转换层FTL，所述多种FTL中的每一种FTL用于记录逻辑地址到闪存物理地址的映射，并且所述多种FTL之间的逻辑地址的粒度均不同；所述闪存设备包括处理器和存储介质，所述处理器与所述存储介质通信；所述存储介质用于存储操作指令；所述处理器用于通过调用所述操作指令以执行上述权利要求1至5中任一项所述的方法。
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