WO2020258493A1 - Chip encapsulation method - Google Patents

Chip encapsulation method Download PDF

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Publication number
WO2020258493A1
WO2020258493A1 PCT/CN2019/103036 CN2019103036W WO2020258493A1 WO 2020258493 A1 WO2020258493 A1 WO 2020258493A1 CN 2019103036 W CN2019103036 W CN 2019103036W WO 2020258493 A1 WO2020258493 A1 WO 2020258493A1
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WIPO (PCT)
Prior art keywords
chip packaging
conductive bump
chip
area
packaging method
Prior art date
Application number
PCT/CN2019/103036
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French (fr)
Chinese (zh)
Inventor
张为国
张俊
唐世弋
Original Assignee
上海微电子装备（集团）股份有限公司
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Application filed by 上海微电子装备（集团）股份有限公司 filed Critical 上海微电子装备（集团）股份有限公司
Publication of WO2020258493A1 publication Critical patent/WO2020258493A1/en

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Definitions

  • the soldering process of the conductive bump structure 30 and the pins of the chip 40 can usually form solder balls on the conductive bump structure, and then align the chip 40 on the carrier board, and then reflow soldering. The process melts the solder balls to realize the soldering process.
  • the carrier can be filled with organic materials and dielectric layers to protect the redistribution layer and the chip on the carrier, and finally the chip packaging structure 40 is formed.
  • the height of the copper pillars is usually 5 to 80 um.
  • Fig. 3 is a graph showing the penetration depth of different wavelengths in silicon according to an embodiment of the present invention. Referring to Fig. 3, considering that the thickness of the silicon wafer used in the carrier board is mostly tens to hundreds of microns, in order to ensure the penetration effect of the laser, The wavelength of the pulsed laser can be set to not less than 800nm. At the same time, in order to prevent the laser's penetrating effect from being too high and affecting other structures in the annealing environment, the wavelength of the pulsed laser can be limited to no more than 2 ⁇ m.
  • the conductive bump structure includes a metal conductive pillar structure, and when a metal conductive pillar structure is provided on the redistribution layer, it is usually necessary to ensure a fixed connection between the metal conductive pillar structure and the redistribution layer. Therefore, optionally, an embodiment of the present invention also provides a chip packaging method.
  • FIG. 8 is a flowchart of another chip packaging structure provided by an embodiment of the present invention. Referring to FIG. 8, the chip packaging structure includes:

Abstract

Disclosed are a chip encapsulation method and an encapsulated chip. The chip encapsulation method comprises: providing a carrier; forming a redistribution layer on the carrier; forming a conductive bump structure on the redistribution layer; welding a chip pin to the conductive bump structure, and forming a chip encapsulation structure; and applying uniform pressure to an area where the conductive bump structure is located, and at the same time, carrying out laser annealing on the area where the conductive bump structure is located.

Description

一种芯片封装方法Chip packaging method
本公开要求在2019年06月26日提交中国专利局、申请号为201910560967.8的中国专利申请的优先权，以上申请的全部内容通过引用结合在本公开中。This disclosure claims the priority of a Chinese patent application filed with the Chinese Patent Office with an application number of 201910560967.8 on June 26, 2019, and the entire content of the above application is incorporated into this disclosure by reference.
技术领域Technical field
本发明实施例涉及半导体技术，例如涉及一种芯片封装方法。The embodiments of the present invention relate to semiconductor technology, for example, to a chip packaging method.
背景技术Background technique
芯片封装就是指把芯片上的电路管脚，用导线接引到外部接头处，以便与其它器件连接。封装形式是指安装半导体集成电路芯片用的外壳。它不仅起着安装、固定、密封、保护芯片及增强电热性能等方面的作用，而且还通过芯片上的接点用导线连接到封装外壳的引脚上，这些引脚又通过印刷电路板上的导线与其他器件相连接，从而实现内部芯片与外部电路的连接。Chip packaging refers to connecting the circuit pins on the chip to external connectors with wires to connect with other devices. The package form refers to the housing for mounting semiconductor integrated circuit chips. It not only plays the role of mounting, fixing, sealing, protecting the chip and enhancing the electrothermal performance, but also connects to the pins of the package shell with wires through the contacts on the chip, and these pins pass the wires on the printed circuit board. Connect with other devices to realize the connection between the internal chip and the external circuit.
目前的封装方式通常是将芯片与一载板焊接，其中载板上设置有重布线层以及与芯片焊接的导电凸点，通过将芯片的管脚与导电凸点焊接，再由重布线层将芯片的电路管脚引出。然而，载板中的重布线层形成后，由于后续的封装步骤中存在加热过程，例如焊接时采用的回流焊工艺中，需要将焊锡融化进行焊接，此时重布线层材料在温度升降的过程中容易因热膨胀系数不同，从而在与导电凸点等材料接触的位置发生形变，即引起了重布线层翘曲的问题，导致重布线层及其他结构的位置发生变动，影响了封装芯片中导电结构的接触效果，使得封装芯片质量下降。The current packaging method is usually to solder the chip to a carrier board. The carrier board is provided with a redistribution layer and conductive bumps soldered to the chip. By soldering the pins of the chip to the conductive bumps, the redistribution layer The circuit pins of the chip are led out. However, after the rewiring layer in the carrier is formed, due to the heating process in the subsequent packaging steps, such as the reflow process used during soldering, the solder needs to be melted for soldering. At this time, the temperature of the rewiring layer material rises and falls. Due to the different thermal expansion coefficients, deformation occurs at the contact position with conductive bumps and other materials, which causes the warpage of the redistribution layer, which causes the position of the redistribution layer and other structures to change, which affects the conductivity of the packaged chip. The contact effect of the structure reduces the quality of the packaged chip.
发明内容Summary of the invention
本文提供一种芯片封装方法和封装芯片，以消除或削弱载板上重布线层的翘曲，保证封装芯片的质量。This article provides a chip packaging method and a packaged chip to eliminate or weaken the warpage of the rewiring layer on the carrier and ensure the quality of the packaged chip.
第一方面，本发明实施例提供了一种芯片封装方法，包括：In the first aspect, an embodiment of the present invention provides a chip packaging method, including:
提供一载板；Provide a carrier board;
在所述载板上形成重布线层；Forming a rewiring layer on the carrier board;
在所述重布线层上形成导电凸点结构；Forming a conductive bump structure on the redistribution layer;
将芯片管脚与所述导电凸点结构焊接，并形成芯片封装结构；Welding the chip pins with the conductive bump structure to form a chip packaging structure;
在所述导电凸点结构的所在区域施加均匀压力，同时对所述导电凸点结构 的所在区域进行激光退火。A uniform pressure is applied to the area where the conductive bump structure is located, and laser annealing is performed on the area where the conductive bump structure is located.
第二方面，本发明实施例还提供了一种封装芯片，所述封装芯片为采用如上所述的芯片封装方法制备。In the second aspect, an embodiment of the present invention also provides a packaged chip, which is prepared by using the chip packaging method described above.
附图说明Description of the drawings
图1是本发明实施例提供的一种芯片封装方法的流程图；FIG. 1 is a flowchart of a chip packaging method provided by an embodiment of the present invention;
图2是图1所示芯片封装方法的结构流程图；FIG. 2 is a structural flowchart of the chip packaging method shown in FIG. 1;
图3是本发明实施例提供不同波长在硅内穿透深度的曲线图；FIG. 3 is a graph showing the penetration depth of different wavelengths in silicon according to an embodiment of the present invention;
图4是本发明实施例提供的另一种芯片封装方法的流程图；4 is a flowchart of another chip packaging method provided by an embodiment of the present invention;
图5是图4所示芯片封装方法的结构流程图；FIG. 5 is a structural flowchart of the chip packaging method shown in FIG. 4;
图6是本发明实施例提供的又一种芯片封装方法的流程图；FIG. 6 is a flowchart of another chip packaging method provided by an embodiment of the present invention;
图7是图6所示芯片封装方法的结构流程图；FIG. 7 is a structural flowchart of the chip packaging method shown in FIG. 6;
图8是本发明实施例提供的又一种芯片封装结构的流程图；8 is a flowchart of another chip packaging structure provided by an embodiment of the present invention;
图9是本发明实施例提供的金属吸收系数及导热系数曲线。Fig. 9 is a curve of metal absorption coefficient and thermal conductivity provided by an embodiment of the present invention.
其中，10-载板，20-重布线层，30-导电凸点结构，40-芯片，50-芯片封装结构，60-工作台，70-透明压板，80-供气装置。Among them, 10-carrier board, 20-rewiring layer, 30-conductive bump structure, 40-chip, 50-chip packaging structure, 60-workbench, 70-transparent pressing plate, 80-gas supply device.
具体实施方式Detailed ways
下面结合附图和实施例对本文作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本文，而非对本文的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本文相关的部分而非全部结构。The text will be further described in detail below in conjunction with the drawings and embodiments. It can be understood that the specific embodiments described here are only used to explain the text, but not to limit the text. In addition, it should be noted that, for ease of description, only a part of the structure related to this document is shown in the drawings instead of all of the structure.
图1是本发明实施例提供的一种芯片封装方法的流程图，图2是图1所示芯片封装方法的结构流程图，参考图1和图2，该芯片封装方法包括：Fig. 1 is a flowchart of a chip packaging method provided by an embodiment of the present invention, and Fig. 2 is a structural flowchart of the chip packaging method shown in Fig. 1. Referring to Figs. 1 and 2, the chip packaging method includes:
S110、提供一载板10；S110. Provide a carrier board 10;
参考图2的步骤a)，在倒装芯片结构中，通常需要设置一载板，用以将芯片的电气面键合在载板上，通过载板进行电气线的导出，并利用载板封装和保护芯片。载板通常可选用硅片。Referring to step a) of Figure 2, in the flip-chip structure, a carrier board is usually required to bond the electrical surface of the chip to the carrier board, and the electrical wires are exported through the carrier board, and the carrier board is used for packaging And protection chip. The carrier board usually can choose silicon wafer.
S120、在载板10上形成重布线层20；S120, forming a rewiring layer 20 on the carrier board 10;
参考图2的步骤b)，载板10上的电气结构包括有重布线层20，重布线层20将芯片管脚引出，用以电性连接外界的电子装置。Referring to step b) of FIG. 2, the electrical structure on the carrier 10 includes a rewiring layer 20 that leads out the chip pins for electrical connection to external electronic devices.
S130、在重布线层20上形成导电凸点结构30；S130, forming a conductive bump structure 30 on the redistribution layer 20;
参考图2的步骤c)，重布线层20与芯片焊接时可以在重布线层20上设置用以焊接芯片管脚的导电凸点结构30，常见的导电凸点结构30包括锡铅柱、金球凸块、铜柱、导电胶凸块以及高分子凸块等型态，其中又以铜柱应用最为广泛。Referring to step c) of FIG. 2, when the redistribution layer 20 is soldered to the chip, a conductive bump structure 30 for soldering chip pins can be provided on the redistribution layer 20. Common conductive bump structures 30 include tin-lead pillars, gold Ball bumps, copper pillars, conductive adhesive bumps, and polymer bumps, among which copper pillars are the most widely used.
S140、将芯片40管脚与导电凸点结构30焊接，并形成芯片封装结构50；S140: Weld the pins of the chip 40 and the conductive bump structure 30 to form a chip packaging structure 50;
参考图2的步骤d)，导电凸点结构30与芯片40管脚的焊接过程通常可以在导电凸点结构上形成焊锡球，在将芯片40对位贴片在载板上，然后通过回流焊工艺融化焊锡球从而实现焊接过程。在焊接完芯片后，可以再在载板中填充有机材料以及介质层，以保护载板上的重布线层和芯片，最终形成芯片封装结构40。如图2所示的芯片封装结构40中，铜柱的高度通常为5～80um。Referring to step d) of FIG. 2, the soldering process of the conductive bump structure 30 and the pins of the chip 40 can usually form solder balls on the conductive bump structure, and then align the chip 40 on the carrier board, and then reflow soldering. The process melts the solder balls to realize the soldering process. After the chip is soldered, the carrier can be filled with organic materials and dielectric layers to protect the redistribution layer and the chip on the carrier, and finally the chip packaging structure 40 is formed. In the chip package structure 40 shown in FIG. 2, the height of the copper pillars is usually 5 to 80 um.
S150、在导电凸点结构30的所在区域施加均匀压力，同时对导电凸点结构30的所在区域进行激光退火。S150: Apply uniform pressure to the area where the conductive bump structure 30 is located, and simultaneously perform laser annealing on the area where the conductive bump structure 30 is located.
参考图2的步骤e)，在形成芯片封装结构40的步骤中，例如导电凸点结构30的形成过程以及与芯片40管脚的焊接过程中，会引起温度的上升，或需要进行加热的过程，温度上升和下降的过程会使得重布线层20和导电凸点结构30发生形变，而由于重布线层20与导电凸点结构30材质不同，热膨胀系数不同，使得重布线层20会发生翘曲现象。因此，重布线层20发生翘曲的位置多在导电凸点结构30所在的区域，针对该区域施加一均匀压力，可以平整翘曲的重布线层20，同时再利用激光退火处理该区域，此处的重布线层20则会在吸收和释放激光热量时发生形变，从而释放导致翘曲的应力。并且在均匀的平整压力的作用下，可以改变重布线层20的形态至平整状态，从而削弱甚至消除重布线层20的翘曲现象。Referring to step e) of FIG. 2, in the steps of forming the chip package structure 40, such as the formation process of the conductive bump structure 30 and the soldering process with the pins of the chip 40, the temperature will rise, or the heating process will be required. , The process of temperature rise and fall will cause the redistribution layer 20 and the conductive bump structure 30 to deform, and because the redistribution layer 20 and the conductive bump structure 30 have different materials and different thermal expansion coefficients, the redistribution layer 20 will warp phenomenon. Therefore, the warping position of the redistribution layer 20 is mostly in the area where the conductive bump structure 30 is located. Applying a uniform pressure to this area can smooth the warped redistribution layer 20, and then use laser annealing to process the area. The redistribution layer 20 there will be deformed when it absorbs and releases laser heat, thereby releasing stress that causes warpage. And under the action of uniform flattening pressure, the shape of the redistribution layer 20 can be changed to a flat state, thereby weakening or even eliminating the warpage of the redistribution layer 20.
可理解的是，所述导电凸点结构30的所在区域为所述导电凸点结构30在所述芯片封装结构50上的一区域。在一些实施例中，所述导电凸点结构30的所在区域为所述导电凸点结构30在所述载板10上的一区域。It is understandable that the area where the conductive bump structure 30 is located is an area of the conductive bump structure 30 on the chip package structure 50. In some embodiments, the area where the conductive bump structure 30 is located is an area of the conductive bump structure 30 on the carrier board 10.
本发明实施例提供的芯片封装方法，通过提供一载板，在载板上形成重布线层，并在重布线层上形成导电凸点结构，再将芯片管脚与导电凸点结构焊接，形成芯片封装结构，最后在导电凸点结构所在区域施加均匀压力，并进行激光退火，一方面为形成的芯片封装结构中产生翘曲的重布线层施加平整力，一方面利用激光退火处理对翘曲的重布线层进行应力释放，从而改变重布线层的形态，使翘曲的重布线层恢复平整，解决了现有技术中重布线层容易发生翘曲， 影响芯片封装结构中电气结构的位置，导致芯片质量不良的问题，本发明实施例提供的芯片封装方法，可以改善重布线层的翘曲，避免芯片封装结构中的电气连接不良，保证封装芯片的质量。The chip packaging method provided by the embodiment of the present invention provides a carrier board, forms a rewiring layer on the carrier board, and forms a conductive bump structure on the rewiring layer, and then solders the chip pins and the conductive bump structure to form Chip packaging structure, and finally apply uniform pressure to the area where the conductive bump structure is located, and perform laser annealing. On the one hand, it applies leveling force to the warped redistribution layer in the formed chip packaging structure, and on the other hand, it uses laser annealing to treat the warpage. The redistribution layer of the chip releases stress, thereby changing the shape of the redistribution layer and restoring the warped redistribution layer to flatness, which solves the problem that the redistribution layer in the prior art is prone to warpage and affects the position of the electrical structure in the chip packaging structure. Leading to the problem of poor chip quality, the chip packaging method provided by the embodiment of the present invention can improve the warpage of the rewiring layer, avoid poor electrical connections in the chip packaging structure, and ensure the quality of the packaged chip.
考虑到芯片封装结构已初步完成芯片在结构上的封装，而通过激光退火处理导电凸点结构所在区域的重布线层，通常需要避免激光能量过高而破坏芯片封装结构中其他的电气结构。因此，步骤S150中，可选地，对导电凸点结构的所在区域进行激光退火，包括：采用脉冲激光对导电凸点结构的所在区域进行激光退火。其中脉冲激光相对于连续的激光具有较低的激光能量，可以避免能量较大的激光破坏芯片封装结构中的内部电气结构。可选地，脉冲激光可选择0.01-30W功率范围，以保证在进行脉冲激光退火时可以有效控制激光产生的热量，从而方便对退火效果进行控制。为保证更优的控制效果，可以选择脉冲宽度在1-100ns的范围内，以进一步降低脉冲激光的瞬时能量。Considering that the chip packaging structure has initially completed the structural packaging of the chip, and the redistribution layer in the area where the conductive bump structure is processed by laser annealing, it is usually necessary to avoid excessive laser energy from damaging other electrical structures in the chip packaging structure. Therefore, in step S150, optionally, performing laser annealing on the area where the conductive bump structure is located includes: using a pulsed laser to perform laser annealing on the area where the conductive bump structure is located. The pulsed laser has a lower laser energy than a continuous laser, which can prevent the laser with a larger energy from damaging the internal electrical structure in the chip packaging structure. Optionally, the pulsed laser can choose a power range of 0.01-30W to ensure that the heat generated by the laser can be effectively controlled during pulsed laser annealing, so as to facilitate the control of the annealing effect. In order to ensure a better control effect, the pulse width can be selected in the range of 1-100ns to further reduce the instantaneous energy of the pulsed laser.
在一些实施例中，在进行激光退火时，可以从芯片封装结构的载板一侧提供激光，此时需要激光穿透载板，并作用于重布线层上。图3是本发明实施例提供不同波长在硅内穿透深度的曲线图，参考图3，考虑到载板所用硅片的厚度多在几十到几百微米，为了保证激光的穿透效果，可设置脉冲激光的波长不小于800nm。同时为了避免激光的穿透效果过高，而影响退火环境中的其他结构，可限制脉冲激光的波长不大于2μm。In some embodiments, during laser annealing, laser light may be provided from the side of the carrier board of the chip packaging structure. In this case, the laser light needs to penetrate the carrier board and act on the redistribution layer. Fig. 3 is a graph showing the penetration depth of different wavelengths in silicon according to an embodiment of the present invention. Referring to Fig. 3, considering that the thickness of the silicon wafer used in the carrier board is mostly tens to hundreds of microns, in order to ensure the penetration effect of the laser, The wavelength of the pulsed laser can be set to not less than 800nm. At the same time, in order to prevent the laser's penetrating effect from being too high and affecting other structures in the annealing environment, the wavelength of the pulsed laser can be limited to no more than 2 μm.
为了在激光退火时配合提供一平整力，使翘曲的重布线层变回平整状态，可以对芯片封装结构施加一均匀压力。可选地，该均匀压力产生的压强范围应在100-1000pa的范围内，其中，压强范围小于100pa时，该均匀压力提供的平整力不足以改变翘曲的重布线层的形态，通过设置均匀压力的压强大于100pa，可以实现对翘曲重布线层的有效挤压，驱使重布线层恢复为平整状态。另外考虑到芯片封装结构强度较小，压强超过1000pa时，容易使芯片封装结构受压迫而损坏，故而可设均匀压力的压强不超过1000pa。In order to provide a flattening force during laser annealing to make the warped redistribution layer return to a flat state, a uniform pressure can be applied to the chip packaging structure. Optionally, the pressure range generated by the uniform pressure should be in the range of 100-1000 pa. When the pressure range is less than 100 pa, the flattening force provided by the uniform pressure is not enough to change the shape of the warped redistribution layer. The pressure is stronger than 100pa, which can effectively squeeze the warped redistribution layer and drive the redistribution layer to a flat state. In addition, considering that the strength of the chip packaging structure is relatively small, when the pressure exceeds 1000pa, the chip packaging structure is likely to be damaged by compression, so the uniform pressure can be set to not exceed 1000pa.
本发明实施例提供了两种对芯片封装结构施加压力的方式，可分为刚性结构机械式施压和高气压施压两种。图4是本发明实施例提供的另一种芯片封装方法的流程图，图5是图4所示芯片封装方法的结构流程图，参考图4和图5，该芯片封装方法包括：The embodiment of the present invention provides two ways to apply pressure to the chip packaging structure, which can be divided into two types: rigid structure mechanical pressure and high-pressure pressure. FIG. 4 is a flowchart of another chip packaging method provided by an embodiment of the present invention. FIG. 5 is a structural flowchart of the chip packaging method shown in FIG. 4. Referring to FIG. 4 and FIG. 5, the chip packaging method includes:
S210、提供一载板10；S210. Provide a carrier board 10;
S220、在载板上形成重布线层20；S220, forming a rewiring layer 20 on the carrier board;
S230、在重布线层上形成导电凸点结构30；S230, forming a conductive bump structure 30 on the redistribution layer;
S240、将芯片40管脚与导电凸点结构30焊接，并形成芯片封装结构50；S240. Weld the pins of the chip 40 and the conductive bump structure 30 to form a chip packaging structure 50;
S250、将芯片封装结构50放置于一工作台60上，且芯片封装结构50的载板10背离工作台60；S250. Place the chip packaging structure 50 on a workbench 60, and the carrier 10 of the chip packaging structure 50 is away from the workbench 60;
参考图5中步骤e)，其中，工作台60的表面为一平整表面，并且芯片封装结构50会倒扣在工作台60上，即芯片封装结构50中的芯片贴近工作台，而载板10背离工作台，此时激光退火时可从载板10一侧发射激光，通过激光透射载板10实现激光退火处理。Referring to step e) in FIG. 5, the surface of the workbench 60 is a flat surface, and the chip packaging structure 50 will be upside down on the workbench 60, that is, the chip in the chip packaging structure 50 is close to the workbench, and the carrier board 10 Away from the workbench, the laser can be emitted from the side of the carrier 10 during laser annealing, and laser annealing can be realized by transmitting the laser through the carrier 10.
S260、在载板10背离工作台60的一侧放置一透明压板70；S260. Place a transparent pressing plate 70 on the side of the carrier board 10 away from the workbench 60;
参考图5中步骤f)，其中，透明压板70可以选用刚性的玻璃基板，激光可透过玻璃基板作用在芯片封装结构50上。Referring to step f) in FIG. 5, the transparent pressing plate 70 can be a rigid glass substrate, and the laser can act on the chip packaging structure 50 through the glass substrate.
S270、向透明压板70施加均匀压力，同时对导电凸点结构50的所在区域进行激光退火。S270: Apply uniform pressure to the transparent pressing plate 70, and simultaneously perform laser annealing on the area where the conductive bump structure 50 is located.
参考图5中步骤g)，向透明压板70施压均匀压力可以进一步挤压工作台60上的芯片封装结构50，保证芯片封装结构50存在一平整压力。Referring to step g) in FIG. 5, applying uniform pressure to the transparent pressing plate 70 can further squeeze the chip packaging structure 50 on the worktable 60 to ensure that the chip packaging structure 50 has a level pressure.
图6是本发明实施例提供的又一种芯片封装方法的流程图，图7是图6所示芯片封装方法的结构流程图，参考图6和图7，该芯片封装方法包括：6 is a flowchart of another chip packaging method provided by an embodiment of the present invention. FIG. 7 is a structural flowchart of the chip packaging method shown in FIG. 6. Referring to FIGS. 6 and 7, the chip packaging method includes:
S310、提供一载板10；S310. Provide a carrier board 10;
S320、在载板10上形成重布线层20；S320, forming a rewiring layer 20 on the carrier board 10;
S330、在重布线层20上形成导电凸点结构30；S330, forming a conductive bump structure 30 on the redistribution layer 20;
S340、将芯片40管脚与导电凸点结构30焊接，并形成芯片封装结构50；S340. Weld the pins of the chip 40 and the conductive bump structure 30 to form a chip packaging structure 50;
S350、将芯片封装结构50放置于一工作台60上，且芯片封装结构50的载板10背离工作台60；S350. Place the chip packaging structure 50 on a workbench 60, and the carrier 10 of the chip packaging structure 50 is away from the workbench 60;
S360、通过供气装置80在载板10背离工作台60的一侧，向导电凸点结构30的所在区域施加均匀压力，同时对导电凸点结构30的所在区域进行激光退火。S360: Apply a uniform pressure to the area where the conductive bump structure 30 is located on the side of the carrier board 10 away from the workbench 60 through the air supply device 80, and simultaneously perform laser annealing on the area where the conductive bump structure 30 is located.
参考图7中步骤f)，其中供气装置80设置在工作台60上方，通过气孔或气道向芯片封装结构50施加气压，利用气压压迫芯片封装结构形成一平整压力。相较于采用透明压板接触式施加压力的方式，气压施压的方式，可以方便调节和控制施加的压力，同时可以减少对芯片封装结构的物理破坏，保护芯片封装结构。需要说明的是，图中所示供气装置80的结构以及施加气压的方式仅为示例，本领域技术人员可以根据具体情况进行设计。Referring to step f) in FIG. 7, the air supply device 80 is set above the workbench 60, and air pressure is applied to the chip packaging structure 50 through the air holes or air passages, and the air pressure is used to compress the chip packaging structure to form a flat pressure. Compared with the contact pressure application method using a transparent pressing plate, the air pressure application method can facilitate the adjustment and control of the applied pressure, while reducing the physical damage to the chip packaging structure and protecting the chip packaging structure. It should be noted that the structure of the air supply device 80 shown in the figure and the manner of applying air pressure are only examples, and those skilled in the art can design according to specific conditions.
进一步为了避免芯片封装结构中芯片被激光损伤，可设置工作台具备温度调节功能。可以理解的是，如上所示的两种施压平整力的方式中，均通过将芯片封装结构放置在工作台上，并且芯片封装结构的载板背离工作台，芯片贴近工作台。在进行激光退火的过程中，激光可能穿透载板而作用于芯片上，使芯片升温。此时，可在激光退火时，调节工作台的温度稳定在20-40℃，从而稳定贴近工作台的芯片的温度，避免芯片受激光作用而发生损伤。Furthermore, in order to prevent the chip in the chip packaging structure from being damaged by the laser, the workbench can be set to have a temperature adjustment function. It is understandable that in the two ways of applying a flattening force as shown above, the chip packaging structure is placed on the workbench, and the carrier of the chip packaging structure faces away from the workbench, and the chip is close to the workbench. During the laser annealing process, the laser may penetrate the carrier and act on the chip, causing the chip to heat up. At this time, during laser annealing, the temperature of the worktable can be adjusted to stabilize at 20-40°C, thereby stabilizing the temperature of the chip close to the worktable, and avoiding the chip from being damaged by the laser.
激光退火的过程中，会使得芯片封装结构中重布线层的温度发生变化，而在较高温度下，芯片封装结构中的电气结构容易发生氧化或腐蚀，因此，可在导电凸点结构的所在区域施加均匀压力，同时对导电凸点结构的所在区域进行激光退火之前，将芯片封装结构放置于惰性气体环境中。该惰性气体环境可以是氮气环境等。During the laser annealing process, the temperature of the redistribution layer in the chip package structure will change. At higher temperatures, the electrical structure in the chip package structure is prone to oxidation or corrosion. Therefore, it can be used in the conductive bump structure. Uniform pressure is applied to the area, and the chip packaging structure is placed in an inert gas environment before laser annealing is performed on the area where the conductive bump structure is located. The inert gas environment may be a nitrogen environment or the like.
通常芯片封装结构中，导电凸点结构包括金属导电柱结构，而在重布线层上设置金属导电柱结构时，通常需要保证金属导电柱结构与重布线层的固定连接。因此，可选地，本发明实施例还提供了一种芯片封装方法，图8是本发明实施例提供的又一种芯片封装结构的流程图，参考图8，该芯片封装结构包括：Generally, in the chip packaging structure, the conductive bump structure includes a metal conductive pillar structure, and when a metal conductive pillar structure is provided on the redistribution layer, it is usually necessary to ensure a fixed connection between the metal conductive pillar structure and the redistribution layer. Therefore, optionally, an embodiment of the present invention also provides a chip packaging method. FIG. 8 is a flowchart of another chip packaging structure provided by an embodiment of the present invention. Referring to FIG. 8, the chip packaging structure includes:
S410、提供一载板；S410. Provide a carrier board;
S420、在载板上形成重布线层；S420, forming a rewiring layer on the carrier board;
S430、在重布线层上形成金属种子层图案；S430, forming a metal seed layer pattern on the rewiring layer;
重布线层上形成金属导电柱结构时，金属导电柱结构在重布线层上的粘结力较低，容易发生接触不良，为了更好地固定金属导电柱结构，可以先在重布线层上沉积金属种子层，再在金属种子层上制备形成金属导电柱结构，此时金属导电柱结构通过金属种子层与重布线层具有良好的粘接力，可以避免金属导电柱结构的连接不良。When the metal conductive column structure is formed on the redistribution layer, the adhesion of the metal conductive column structure on the redistribution layer is low, and poor contact is prone to occur. In order to better fix the metal conductive column structure, you can first deposit on the redistribution layer The metal seed layer is then prepared to form a metal conductive column structure on the metal seed layer. At this time, the metal conductive column structure has good adhesion to the redistribution layer through the metal seed layer, which can avoid poor connection of the metal conductive column structure.
S440、对金属种子层图案的所在区域进行初步激光退火；S440: Perform preliminary laser annealing on the area where the metal seed layer pattern is located;
金属种子层制备厚度在2-8μm，在形成金属种子层图案时温度升高，重布线层容易在沉积有金属种子层的位置产生形变应力，从而发生翘曲现象，该初步激光退火步骤可以对重布线层进行处理，帮助重布线层释放应力，减缓翘曲现象。The metal seed layer is prepared with a thickness of 2-8μm. When the metal seed layer pattern is formed, the temperature rises, and the redistribution layer is likely to produce deformation stress at the position where the metal seed layer is deposited, thereby causing warpage. This preliminary laser annealing step can correct The re-wiring layer is processed to help the re-wiring layer release stress and slow down warpage.
可理解的是，所述金属种子层图案的所在区域为所述金属种子层图案在芯片封装结构50上的一区域，在一些实施例中，所述金属种子层图案的所在区域为所述金属种子层图案在载板10上的一区域。It is understandable that the area where the metal seed layer pattern is located is an area of the metal seed layer pattern on the chip packaging structure 50. In some embodiments, the area where the metal seed layer pattern is located is the metal The seed layer pattern is in an area on the carrier board 10.
S450、在金属种子层图案上形成金属导电柱，其中导电凸点结构包括金属导电柱；S450, forming a metal conductive pillar on the metal seed layer pattern, wherein the conductive bump structure includes the metal conductive pillar;
金属导电柱图案(也即，金属导电柱)通常采用电镀工艺形成，高度约为10-100μm。在电镀过程中同样会发生温度的剧烈变化，此时也容易引起重布线层形变应力集中，而发生翘曲现象。The metal conductive post pattern (ie, the metal conductive post) is usually formed by an electroplating process, and the height is about 10-100 μm. In the electroplating process, the temperature will also change drastically. At this time, it is also easy to cause the deformation and stress concentration of the rewiring layer, and warping occurs.
S460、对金属导电柱的所在区域进行初步激光退火；S460. Perform preliminary laser annealing on the area where the metal conductive pillar is located;
此时初步激光退火步骤同样可以释放重布线层在金属导电柱图案制备形成时产生的形变应力，削弱翘曲现象。At this time, the preliminary laser annealing step can also release the deformation stress of the rewiring layer during the preparation and formation of the metal conductive pillar pattern, and weaken the warpage phenomenon.
S470、将芯片管脚与导电凸点结构焊接，并形成芯片封装结构；S470: Weld the chip pins and the conductive bump structure to form a chip packaging structure;
S480、在导电凸点结构的所在区域施加均匀压力，同时对导电凸点结构的所在区域进行激光退火。S480: Apply uniform pressure to the area where the conductive bump structure is located, and simultaneously perform laser annealing on the area where the conductive bump structure is located.
需要说明的是，在重布线层上形成金属种子层图案之后，对金属种子层图案的所在区域进行初步激光退火的步骤，和在金属种子层图案上形成金属导电柱图案之后，对金属导电柱图案的所在区域进行初步激光退火的步骤，本领域技术人员可根据实际的工艺流程需要进行选择添加，示例性地，也可以仅在金属导电柱图案形成之后进行初步激光退火步骤。It should be noted that after the metal seed layer pattern is formed on the redistribution layer, a preliminary laser annealing step is performed on the area where the metal seed layer pattern is located, and after the metal conductive pillar pattern is formed on the metal seed layer pattern, the metal conductive pillar The area where the pattern is located is subjected to a preliminary laser annealing step, and those skilled in the art can select and add according to actual process requirements. Illustratively, the preliminary laser annealing step can also be performed only after the metal conductive pillar pattern is formed.
为了方便对初步激光退火的效果控制，初步激光退火时也可选择脉冲激光。但由于金属种子层图案和金属导电柱图案形成之后才进行芯片的焊接，因此，在对金属种子层图案和金属导电柱图案进行初步激光退火时，不用考虑激光可能对芯片造成损坏，故而可选择连续激光进行退火。在利用连续激光进行退火时同样可以考虑激光有效作用的功率范围，可选地，初步激光退火的激光功率范围为1-300mW。另外需要注意的是，由于金属种子层和金属导电柱均为金属材质，并且通常为铜柱结构。图9是本发明实施例提供的金属吸收系数及导热系数曲线，参考图9，铜的导电材料的波长吸收范围小于1μm，为了避免金属导电柱响应初步激光退火时的激光，可选地，初步激光退火的激光波长范围为1-20μm。此时激光退火不会作用在金属种子层，故而激光退火处理不会影响金属导电柱结构。In order to facilitate the control of the effect of preliminary laser annealing, pulsed laser can also be selected during preliminary laser annealing. However, since the metal seed layer pattern and the metal conductive pillar pattern are formed before the chip welding is performed, when performing the preliminary laser annealing on the metal seed layer pattern and the metal conductive pillar pattern, it is not necessary to consider the laser may damage the chip, so it is optional Continuous laser annealing. When the continuous laser is used for annealing, the effective power range of the laser can also be considered. Optionally, the laser power range of the preliminary laser annealing is 1-300 mW. In addition, it should be noted that the metal seed layer and the metal conductive pillars are both metal materials, and usually have a copper pillar structure. Fig. 9 is a curve of metal absorption coefficient and thermal conductivity provided by an embodiment of the present invention. Referring to Fig. 9, the wavelength absorption range of the conductive material of copper is less than 1 μm. In order to prevent the metal conductive column from responding to the laser during preliminary laser annealing, optionally, preliminary The laser wavelength range of laser annealing is 1-20μm. At this time, the laser annealing will not act on the metal seed layer, so the laser annealing treatment will not affect the metal conductive pillar structure.

Claims (17)

  1. 一种芯片封装方法，包括：A chip packaging method includes:
    提供一载板(10)；Provide a carrier board (10);
    在所述载板(10)上形成重布线层(20)；Forming a rewiring layer (20) on the carrier board (10);
    在所述重布线层(20)上形成导电凸点结构(30)；Forming a conductive bump structure (30) on the redistribution layer (20);
    将芯片(40)管脚与所述导电凸点结构(30)焊接，并形成芯片封装结构(50)；Soldering the pins of the chip (40) to the conductive bump structure (30) to form a chip packaging structure (50);
    在所述导电凸点结构(30)的所在区域施加均匀压力，同时对所述导电凸点结构(30)的所在区域进行激光退火。A uniform pressure is applied to the area where the conductive bump structure (30) is located, and laser annealing is performed on the area where the conductive bump structure (30) is located.
  2. 根据权利要求1所述的芯片封装方法，其中，所述对所述导电凸点结构(30)的所在区域进行激光退火，包括：The chip packaging method according to claim 1, wherein said performing laser annealing on the area where the conductive bump structure (30) is located comprises:
    采用脉冲激光对所述导电凸点结构(30)的所在区域进行激光退火。A pulsed laser is used to perform laser annealing on the area where the conductive bump structure (30) is located.
  3. 根据权利要求2所述的芯片封装方法，其中，所述脉冲激光的波长范围为0.8-2μm。The chip packaging method according to claim 2, wherein the wavelength range of the pulsed laser is 0.8-2 μm.
  4. 根据权利要求2所述的芯片封装方法，其中，所述脉冲激光的功率范围为0.01-30W。The chip packaging method according to claim 2, wherein the power range of the pulsed laser is 0.01-30W.
  5. 根据权利要求2所述的芯片封装方法，其中，所述脉冲激光的脉冲宽度在1-100ns的范围内。3. The chip packaging method of claim 2, wherein the pulse width of the pulsed laser is in the range of 1-100 ns.
  6. 根据权利要求1所述的芯片封装方法，其中，所述对所述导电凸点结构(30)的所在区域进行激光退火，包括：The chip packaging method according to claim 1, wherein said performing laser annealing on the area where the conductive bump structure (30) is located comprises:
    从所述芯片封装结构(50)的载板(10)一侧提供激光，以使得激光穿透载板，并作用于所述重布线层(20)上。A laser is provided from the carrier (10) side of the chip packaging structure (50), so that the laser penetrates the carrier and acts on the redistribution layer (20).
  7. 根据权利要求1所述的芯片封装方法，其中，所述在所述导电凸点结构(30)的所在区域施加均匀压力，包括：The chip packaging method according to claim 1, wherein the applying uniform pressure on the area where the conductive bump structure (30) is located comprises:
    将所述芯片封装结构(50)放置于一工作台(60)上，且所述芯片封装结构(50)的所述载板(10)背离所述工作台(60)；Placing the chip packaging structure (50) on a workbench (60), and the carrier board (10) of the chip packaging structure (50) is away from the workbench (60);
    在所述载板(10)背离所述工作台(60)的一侧放置一透明压板(70)；Place a transparent pressing plate (70) on the side of the carrier board (10) away from the workbench (60);
    向所述透明压板(70)施加均匀压力。Apply uniform pressure to the transparent pressing plate (70).
  8. 根据权利要求1所述的芯片封装方法，其中，所述在所述导电凸点结构(30)的所在区域施加均匀压力，包括：The chip packaging method according to claim 1, wherein the applying uniform pressure on the area where the conductive bump structure (30) is located comprises:
    将所述芯片封装结构(50)放置于一工作台(60)上，且所述芯片封装结构(50)的所述载板(10)背离所述工作台(60)；Placing the chip packaging structure (50) on a workbench (60), and the carrier board (10) of the chip packaging structure (50) is away from the workbench (60);
    通过供气装置(80)在所述载板(10)背离工作台(60)的一侧，向所述导电凸点结构(30)的所在区域施加均匀压力。The air supply device (80) applies uniform pressure to the area where the conductive bump structure (30) is located on the side of the carrier board (10) away from the workbench (60).
  9. 根据权利要求7或8所述的芯片封装方法，其中，所述工作台(60)的温度范围为20-40℃。The chip packaging method according to claim 7 or 8, wherein the temperature range of the workbench (60) is 20-40°C.
  10. 根据权利要求1所述的芯片封装方法，其中，所述均匀压力产生的压强范围为100-1000pa。The chip packaging method according to claim 1, wherein the pressure generated by the uniform pressure is in the range of 100-1000 Pa.
  11. 根据权利要求1所述的芯片封装方法，其中，在所述导电凸点结构(30)的所在区域施加均匀压力，同时对所述导电凸点结构(30)的所在区域进行激光退火之前，还包括：The chip packaging method according to claim 1, wherein a uniform pressure is applied to the area where the conductive bump structure (30) is located, and at the same time, the area where the conductive bump structure (30) is located is subjected to laser annealing. include:
    将所述芯片封装结构(50)放置于惰性气体环境中。The chip packaging structure (50) is placed in an inert gas environment.
  12. 根据权利要求1所述的芯片封装方法，其中，所述导电凸点结构(30)包括金属导电柱；The chip packaging method according to claim 1, wherein the conductive bump structure (30) comprises a metal conductive pillar;
    所述在所述重布线层(20)上形成导电凸点结构(30)，包括：The forming a conductive bump structure (30) on the redistribution layer (20) includes:
    在所述重布线层(20)上形成金属种子层图案；Forming a metal seed layer pattern on the rewiring layer (20);
    在所述金属种子层图案上形成金属导电柱。A metal conductive pillar is formed on the metal seed layer pattern.
  13. 根据权利要求12所述的芯片封装方法，其中，在所述重布线层(20)上形成金属种子层图案之后，还包括：The chip packaging method according to claim 12, wherein after forming a metal seed layer pattern on the rewiring layer (20), the method further comprises:
    对所述金属种子层图案的所在区域进行初步激光退火。Preliminary laser annealing is performed on the area where the metal seed layer pattern is located.
  14. 根据权利要求12或13所述的芯片封装方法，其中，在所述金属种子层图案上形成金属导电柱之后，还包括：The chip packaging method according to claim 12 or 13, wherein after forming metal conductive pillars on the metal seed layer pattern, the method further comprises:
    对所述金属导电柱的所在区域进行初步激光退火。Preliminary laser annealing is performed on the area where the metal conductive pillar is located.
  15. 根据权利要求13或14所述的芯片封装方法，其中，所述初步激光退火的激光波长范围为1-20μm。The chip packaging method according to claim 13 or 14, wherein the laser wavelength range of the preliminary laser annealing is 1-20 μm.
  16. 根据权利要求13或14所述的芯片封装方法，其中，所述初步激光退火的激光功率范围为1-300mW。The chip packaging method according to claim 13 or 14, wherein the laser power range of the preliminary laser annealing is 1-300 mW.
  17. 一种封装芯片，所述封装芯片为采用如权利要求1-16任一项所述的芯片封装方法制备。A packaged chip, which is prepared by the chip packaging method according to any one of claims 1-16.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105374774A (en) * 2014-08-29 2016-03-02 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof, and electronic device
CN107195607A (en) * 2017-07-03 2017-09-22 京东方科技集团股份有限公司 A kind of chip packaging method and chip-packaging structure
TWI603431B (en) * 2014-12-23 2017-10-21 英特爾公司 Formation of solder and copper interconnect structures and associated techniques and configurations
US20190008046A1 (en) * 2017-06-30 2019-01-03 Intel Corporation Microelectronic devices designed with ultra-high-k dielectric capacitors integrated with package substrates

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6495397B2 (en) * 2001-03-28 2002-12-17 Intel Corporation Fluxless flip chip interconnection
JP4692101B2 (en) * 2005-06-27 2011-06-01 ソニー株式会社 Part joining method
KR101165029B1 (en) * 2007-04-24 2012-07-13 삼성테크윈 주식회사 Apparatus for heating chip, flip chip bonder having the same and method for bonding flip chip using the same
JP2012104782A (en) * 2010-11-15 2012-05-31 Elpida Memory Inc Method and apparatus for manufacturing semiconductor device
KR101177292B1 (en) * 2010-11-16 2012-08-30 주식회사 에이에스티젯텍 A bonding method and apparatus for electroinc elements using laser beam
CN104124196B (en) * 2013-04-23 2018-10-23 中芯国际集成电路制造(上海)有限公司 A method of making semiconductor devices
FR3011982B1 (en) * 2013-10-15 2017-05-12 Commissariat Energie Atomique PROCESS FOR PRODUCING A PHOTOVOLTAIC CELL
TWI610411B (en) * 2014-08-14 2018-01-01 艾馬克科技公司 Laser assisted bonding for semiconductor die interconnections
US20170309584A1 (en) * 2014-10-23 2017-10-26 Agency For Science, Technology And Research Method of bonding a first substrate and a second substrate
JP6853186B2 (en) * 2015-04-28 2021-03-31 ネーデルランドセ・オルガニサティ・フォール・トゥーヘパスト−ナトゥールウェテンスハッペライク・オンデルズーク・テーエヌオー Equipment and methods for non-contact transfer and soldering of chips using flash lamps
US9916989B2 (en) * 2016-04-15 2018-03-13 Amkor Technology, Inc. System and method for laser assisted bonding of semiconductor die

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105374774A (en) * 2014-08-29 2016-03-02 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof, and electronic device
TWI603431B (en) * 2014-12-23 2017-10-21 英特爾公司 Formation of solder and copper interconnect structures and associated techniques and configurations
US20190008046A1 (en) * 2017-06-30 2019-01-03 Intel Corporation Microelectronic devices designed with ultra-high-k dielectric capacitors integrated with package substrates
CN107195607A (en) * 2017-07-03 2017-09-22 京东方科技集团股份有限公司 A kind of chip packaging method and chip-packaging structure

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