WO2020249010A1 - 时序控制器控制方法和时序控制器 - Google Patents

时序控制器控制方法和时序控制器 Download PDF

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Publication number
WO2020249010A1
WO2020249010A1 PCT/CN2020/095395 CN2020095395W WO2020249010A1 WO 2020249010 A1 WO2020249010 A1 WO 2020249010A1 CN 2020095395 W CN2020095395 W CN 2020095395W WO 2020249010 A1 WO2020249010 A1 WO 2020249010A1
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Prior art keywords
switch
module
timing controller
control
address
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PCT/CN2020/095395
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English (en)
French (fr)
Inventor
王明良
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北海惠科光电技术有限公司
重庆惠科金渝光电科技有限公司
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Priority to US17/421,280 priority Critical patent/US11631377B2/en
Publication of WO2020249010A1 publication Critical patent/WO2020249010A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G—PHYSICS
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    • G09G2320/0666—Adjustment of display parameters for control of colour parameters, e.g. colour temperature
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    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G—PHYSICS
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    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present invention relates to the field of display technology, in particular to a timing controller control method and a timing controller.
  • the current common LCD panel drive architecture mainly uses the TCON (Timing Controller) on the PCB (Printed Circuit Board) to process the display data, and the PWM IC (Pulse-width Modulation Integrated Circuit). Wide modulation chip) provides driving power, and Gamma IC (Gamma Integrated Circuit, gamma chip) provides gamma voltage for driving the liquid crystal cell.
  • TCON Transmission Controller
  • PWM Pulse-width Modulation Integrated Circuit
  • the current timing controller and gamma chip are connected together through the I2C (Inter-Integrated Circuit) bus, which is convenient for reading any chip by operating I2C, but this connection method is easy to appear
  • I2C Inter-Integrated Circuit
  • the problem is that when the user operates the gamma chip, it will also affect the work of the timing controller, which will cause the internal switch of the timing controller to open by mistake, causing the workload of the timing controller to increase.
  • the output current of the power module connected to the controller suddenly increases and the output voltage fluctuates abnormally, which further causes abnormal chip operation and abnormal display.
  • the embodiments of the present application provide a timing controller control method and a timing controller.
  • an embodiment of the present application provides a timing controller control method, including:
  • the timing controller is powered by a power module, the timing controller includes a plurality of functional modules, and the target functional module is a controlled functional module indicated by a bus signal.
  • the timing controller control method provided by the embodiments of the present application can automatically detect the address of the signal transmitted on the I2C bus, and control the closing of the switch of the target function module corresponding to the address in the timing controller, so as to avoid the use of gamma chips and other components.
  • the timing controller is turned on by mistake, and the output voltage fluctuation of the power supply module caused by all the function modules inside the timing controller are turned on when there is a signal on the I2C bus, which improves the stability of the power supply module and further improves the display effect.
  • an embodiment of the present application provides a timing controller, which is configured to be connected to an I2C bus, and includes: a processor, a memory, a plurality of switches, and a plurality of functional modules; the processor and each functional module are configured to be connected to the power module connection;
  • the memory stores switch control data used to indicate the on-off state of each switch and the working parameters of each functional module
  • the processor is connected to the first access terminal of the memory
  • Each functional module is connected to the second access terminal of the memory through a one-to-one corresponding switch;
  • the processor is configured to execute the processing of the above-mentioned timing controller control method.
  • FIG. 1 is a schematic diagram of a driving structure of a liquid crystal panel
  • FIG. 2 is a schematic diagram of the structure of a driving circuit in an exemplary technology
  • FIG. 3 is a schematic diagram of a waveform of a voltage of a power supply module in an exemplary technology
  • FIG. 4 is a schematic flowchart of a method for controlling a timing controller according to an embodiment
  • FIG. 5 is a schematic flowchart of a switch closing process for controlling a connection with a target function module according to switch control data according to an embodiment
  • FIG. 6 is a schematic flowchart of a switch closing process for controlling a connection with a target function module according to switch control data according to another embodiment
  • FIG. 7 is a schematic structural diagram of a timing controller control device according to an embodiment
  • Fig. 8 is a schematic structural diagram of a timing controller control device according to another embodiment.
  • Fig. 9 is a schematic structural diagram of a timing controller control device according to still another embodiment.
  • FIG. 10 is a schematic diagram of the internal structure of a computer device according to an embodiment
  • FIG. 11 is a schematic diagram of the structure of a timing controller and a driving circuit according to an embodiment
  • FIG. 12 is a schematic diagram of the structure of a timing controller and a driving circuit according to another embodiment
  • FIG. 13 is a schematic structural diagram of a display device according to an embodiment.
  • Fig. 1 is an exemplary driving architecture of a liquid crystal panel.
  • Fig. 2 shows the design architecture of the driving circuit in the exemplary technology.
  • the I2C bus a simple, two-way two-wire synchronous serial bus developed by Philips
  • the internal I2C slave I2C bus slave device interface
  • the OD (Over-actuated) module inside the timing controller ACC (Advanced Color Control, precise color control/automatic color control) Module
  • Dither (jitter) module can read the look-up table (look-up table), this design can open the internal switch early to facilitate the operation of the timing controller.
  • an embodiment of the present application provides a timing controller control method, including:
  • S40 Generate and send a query instruction to the memory according to the address of the target function module, and receive switch control data corresponding to the target function module fed back by the memory;
  • S50 Control the switch connected to the target function module to close according to the switch control data, so that the target function module obtains the working parameters of the target function module stored in the memory through the corresponding switch;
  • the timing controller is powered by the power module, the timing controller includes multiple functional modules, and the target functional module is the controlled functional module indicated by the bus signal.
  • the I2C bus is a simple, bidirectional, two-wire synchronous serial bus developed by Philips. It only needs two wires to transfer information between devices connected to the bus.
  • Each device on the bus has a unique address. According to whether each device is used to transmit data or receive data, each device on the bus can be divided into a master device and a slave device.
  • the master device is used to start the bus to transmit data and generate a clock With an open transmission device, any device addressed at this time is considered a slave device (for example, the controlled functional module in the above-mentioned timing controller).
  • Data information is the data used to instruct the slave device to continue to transmit after the master device has successfully addressed and received the response signal from the corresponding slave device.
  • Determining whether the bus address matches the address of the timing controller can be determining whether the effective bit data except the start bit in the address signal transmitted on the bus is consistent with the address of the timing controller.
  • the target function module is one or more of the function modules in the timing controller, and the target function module is the object to be controlled by the data information in the bus signal.
  • the switch control data is data for instructing and controlling the open/close state of each switch corresponding to each functional module, which corresponds to the address of each target function module one-to-one, and the switch control data is stored in the memory.
  • a query command is generated and sent to the memory according to the obtained address of the target function module, and switch control data corresponding to the target function module is obtained by accessing the memory.
  • the query command may be an command including the address of the target function module.
  • the corresponding switch is controlled to close according to the data, so that the target function module is connected to the memory, and the target function module obtains its working parameters from the memory and enters the working state.
  • the timing controller control method provided by the embodiment of the application firstly performs address matching judgment. When the timing controller is the controlled slave device, the next step is to allocate the internal work of the timing controller according to the target function module in the data information.
  • the power supply module may be a PWM IC (Pulse-width Modulation Integrated Circuit, pulse width modulation chip) power supply.
  • the timing controller control method determines whether the address in the signal transmitted by the I2C bus matches the address of the timing controller, that is, it is determined whether the address is to be sent to the timing controller, and if so, it receives the I2C bus. For the subsequent transmission of data information, perform the next step to obtain the address of the target function module from the data information, and generate query instructions according to the address of the target function module, and find the switch control data corresponding to the target function module in the timing controller by accessing the memory , And then control the switch corresponding to the target function module to close according to the switch control data.
  • the connected switch does not perform the closing operation, only connects the target function module with the memory, and makes the target function module obtain its working parameters from the memory and start working.
  • the timing controller control method provided by the embodiments of the present application can automatically detect the address in the signal transmitted on the I2C bus to control the closing of the switch of the target function module corresponding to the address in the timing controller, so as to avoid damage to other components such as gamma chips.
  • the timing controller is turned on by mistake, and the output voltage fluctuation of the power module caused by all the functional modules inside the timing controller are turned on when there is a signal on the I2C bus, which improves the stability of the power module and further improves the display effect .
  • controlling the closing of the switch connected to the target function module according to the switch control data includes:
  • the switches are controlled to close in turn according to the switch control data. Avoid closing multiple switches at the same time, causing excessive load and causing fluctuations in the output voltage of the power module.
  • timing controller control method when it is detected that the bus address matches the addresses of multiple functional modules in the timing controller, correspondingly, multiple switch control analog signals are obtained from the memory to further reduce multiple The simultaneous opening of functional modules affects the power supply module.
  • the processor controls the corresponding switch to close according to the analog signal of each switch control in a certain order, ensuring that only one switch is closed at the same time, and avoiding unstable power supply voltage caused by excessive instantaneous power consumption , Provide high-quality display devices and display effects.
  • the switch control data is stored in a look-up table, and the look-up table represents the correspondence between the address of each functional module and the switch control data.
  • the switch control data is stored in a lookup table, which is a table that can characterize the correspondence between the address of each functional module and the switch control data.
  • the storage content in the specific table may be a table in which the address of the function module and the switch control data correspond one-to-one, and the query instruction may include the address of the target function module. It can also be a table of one-to-one correspondence between the number of the pre-defined function module and the switch control data.
  • the process of generating the query command according to the address of the target function module can be to first obtain the function module according to the address of the target function module And then generate a query instruction that includes the number information.
  • controlling the closing of the switch connected to the target function module according to the switch control data includes:
  • S53 Send a switch control analog signal to the switch connected to the target function module, and control the switch to close.
  • the switch After receiving the switch control data fed back by the memory, the data is converted into an analog switch control analog signal capable of controlling the switch state, so as to control the corresponding switch to close.
  • the switch can be a MOS tube with a small size.
  • the switch connected to the jitter module can be a MOS tube, the drain is connected to the jitter module, the source is connected to the memory, the gate is used to receive the switch control analog signal, and the gate receives the high level switch control analog signal.
  • the dithering module obtains its corresponding working parameters from the memory and starts to work.
  • the switch may also be other types of electronic switches, such as transistors, and the connection mode is adjusted according to the switch type to ensure that the switch can be closed after receiving the corresponding switch control analog signal.
  • the working parameters of the functional module include the working parameters of the overdrive module, the working parameters of the precise color control module, and the working parameters of the dithering module, and the switch control analog signal includes:
  • the first control signal is set to control the closing of the first switch connected to the overdrive module, so that the overdrive module obtains the working parameters of the overdrive module from the memory;
  • the second control signal is set to control the closing of the second switch connected to the precise color control module, so that the precise color control module obtains the working parameters of the precise color control module from the memory through the second switch;
  • the third control signal is set to control the closing of the third switch connected to the dithering module, so that the dithering module obtains the working parameters of the dithering module from the memory through the third switch;
  • the functional modules include an overdrive module, a precise color control module, and a jitter module.
  • the switches include a first switch, a second switch, and a third switch.
  • the overdrive module is set to modulate the data signal received by the timing controller, and the data signal is a signal for driving the display panel.
  • the data signal modulated by the overdrive module can overdrive the liquid crystal and improve the response speed of the liquid crystal molecules.
  • the precise color control module is a closed-loop negative feedback amplifier circuit, which is set to control the amplitude of the chrominance signal.
  • the precise color control module detects the chroma synchronization signal as a standard for control, controls the amplitude of the chroma signal according to the size of the chroma synchronization signal, automatically changes the gain, and makes the chroma signal reach a stable value.
  • the dithering module can perform random dithering operations, which can improve the image fidelity of the digital display.
  • the switch control analog signal includes a first control signal, a second control signal, and a third control signal, which respectively control the first switch , The second switch and the third switch.
  • the first switch is a switch connected to the overdrive module
  • the second switch is a switch connected to the precise color control module
  • the third switch is a switch connected to the jitter module. If it is determined that the address in the bus signal matches the address of the timing controller, the data information is further received, and the data information is analyzed to obtain the address of the target function module.
  • the switch control data corresponding to the address is obtained from the memory, and the first control signal is generated according to the data, and the first control signal is sent to the first switch to drive the first switch to close ,
  • the overdrive module gets its working data from the memory and starts to work.
  • the objects to be controlled are the precise color control module and the dithering module, the implementation process is the same as the overdrive module.
  • the addresses of three target functional modules are generated according to the data information
  • three switch control data are obtained by querying the memory
  • the first control is generated according to the three switch control analog signals Signal, second control signal and third control signal, and send the first control signal, second control signal and third control signal to the corresponding first switch, second switch and third switch in sequence, and only one switch is closed at the same time .
  • the order of sequential opening can be other order besides the order described in the above example.
  • the query instruction includes the address of the target function module.
  • the query instruction may include the address of the target function module.
  • an embodiment of the present application also provides a timing controller control device, including:
  • the bus address obtaining unit 710 is configured to obtain the bus address in the bus signal transmitted on the I2C bus, and the I2C bus is connected to the timing controller;
  • the data information acquiring unit 720 is configured to acquire the data information in the bus signal when it is determined that the bus address matches the address of the timing controller;
  • the target function module address obtaining unit 730 is configured to obtain the address of the target function module according to the data information
  • the switch control data acquisition unit 740 is configured to generate and send a query command to the memory according to the address of the target function module, and receive switch control data corresponding to the target function module fed back by the memory;
  • the switch control unit 750 is configured to control the closing of the switch connected to the target function module according to the switch control data, so that the target function module obtains the working parameters of the target function module stored in the memory through the corresponding switch;
  • the timing controller is powered by a power module, the timing controller includes a plurality of functional modules, and the target functional module is a controlled functional module indicated by a bus signal.
  • the switch control unit 750 includes:
  • the switch sequence control unit 751 is configured to sequentially control the closing of the switches connected to each target function module according to each switch control data when multiple switch control data are received.
  • the switch control unit 750 further includes:
  • a switch control analog signal generating unit 752 configured to generate a switch control analog signal according to the switch control data
  • the switch control analog signal sending unit 753 is configured to send the switch control analog signal to the switch connected to the target function module to control the switch to close.
  • a computer device is provided.
  • the computer device may be a terminal, and its internal structure diagram may be as shown in FIG. 10.
  • the computer equipment includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus.
  • the processor of the computer device is used to provide calculation and control capabilities.
  • the memory of the computer device includes a non-volatile storage medium and an internal memory.
  • the non-volatile storage medium stores an operating system and a computer program.
  • the internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium.
  • the network interface of the computer device is used to communicate with an external terminal through a network connection.
  • the computer program is executed by the processor to realize a timing controller control method.
  • the display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen
  • the input device of the computer equipment can be a touch layer covered on the display screen, or it can be a button, a trackball or a touchpad set on the housing of the computer equipment , It can also be an external keyboard, touchpad, or mouse.
  • FIG. 10 is only a block diagram of part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied.
  • the specific computer device may Including more or fewer parts than shown in the figure, or combining some parts, or having a different arrangement of parts.
  • a computer device including a memory and a processor, the memory stores a computer program, and the processor implements the following processing when the computer program is executed:
  • S40 Generate and send a query instruction to the memory according to the address of the target function module, and receive switch control data corresponding to the target function module fed back by the memory;
  • S50 Control the switch connected to the target function module to close according to the switch control data, so that the target function module obtains the working parameters of the target function module stored in the memory through the corresponding switch;
  • the timing controller is powered by a power module, the timing controller includes a plurality of functional modules, and the target functional module is a controlled functional module indicated by a bus signal.
  • the computer equipment provided in this application can perform all the processing in the above method embodiments.
  • the computer equipment provided in this application can perform the task assignment of the functional modules after determining that the bus address matches the address of the timing controller to avoid any action on the bus. ,
  • the timing controller malfunctions, causing the output voltage of the power module to fluctuate and improving the display stability.
  • the following processing is implemented:
  • S40 Generate and send a query instruction to the memory according to the address of the target function module, and receive switch control data corresponding to the target function module fed back by the memory;
  • S50 Control the switch connected to the target function module to close according to the switch control data, so that the target function module obtains the working parameters of the target function module stored in the memory through the corresponding switch;
  • the timing controller is powered by a power module, the timing controller includes a plurality of functional modules, and the target functional module is a controlled functional module indicated by a bus signal.
  • the computer program can be stored in a non-volatile computer readable storage.
  • the medium when the computer program is executed, it may include the procedures of the above-mentioned method embodiments.
  • any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and/or volatile memory.
  • the non-volatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory.
  • Volatile memory may include random access memory (RAM) or external cache memory.
  • RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous chain Channel (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.
  • an embodiment of the present application also provides a timing controller 10, including: a processor 100, a memory 200, multiple switches, and multiple functional modules 400; the processor 100 and each functional module 400 are all connected to the power module 40;
  • the memory 200 stores switch control data used to indicate the on and off states of each switch and the working parameters of each functional module 400;
  • the processor 100 is connected to the first access terminal of the memory 200;
  • Each functional module 400 is connected to the second access terminal of the memory 200 through a one-to-one corresponding switch;
  • the processor 100 is used to execute the processing of the control method of the timing controller 10 described above.
  • the definitions of the function module 400, switches, etc. are the same as those in the above-mentioned control method of the timing controller 10, and will not be repeated here.
  • the timing controller 10 provided by the embodiment of the present application can first determine whether the bus address in the bus signal on the bus 20 matches with itself by integrating the processor 100 with other devices, and if it matches, proceed to the next step. Specifically, according to the data information in the bus signal, the address of the target function module 400 is generated, and the query instruction is further generated according to the address of the target function module 400, and by querying the memory 200, the switch control corresponding to the address of the target function module 400 is obtained. According to the switch control data, the switch connected to the target function module 400 is controlled to close, so that the target function module 400 starts to work. The output voltage fluctuation of the power module 40 caused by the false triggering of the timing controller 10 is avoided, and the display stability and quality are improved.
  • the processor 100 is configured to generate a switch control analog signal according to the switch control data, and send the switch control analog signal to the switch connected to the target function module 400 to control the switch to close;
  • the working parameters include the working parameters of the overdrive module 410, the working parameters of the precise color control module 420, and the working parameters of the dithering module 430.
  • the switch control analog signals (C1, C2,..., Cn) include the first control signal C1, The second control signal C2 and the third control signal C3, the switch includes:
  • the first switch K1, the first terminal of the first switch K1 is connected to the second access terminal of the memory 200;
  • the second switch K2 the first terminal of the second switch K2 is connected to the second access terminal of the memory 200;
  • the third switch K3, the first terminal of the third switch K3 is connected to the second access terminal of the memory 200;
  • the overdrive module 410 the input end of the overdrive module 410 is connected to the second end of the first switch K1;
  • the precise color control module 420 the input terminal of the precise color control module 420 is connected to the second terminal of the second switch K2;
  • the dithering module 430, the input end of the dithering module 430 is connected to the second end of the third switch K3;
  • the processor is configured to control the first switch K1 to close according to the first control signal C1, to control the second switch K2 to close according to the second control signal C2, and to control the third switch K3 to close according to the third control signal C3.
  • each control signal (C1, C2,..., Cn) with each switch, the switch state of each switch (K1, K2, K3,..., Kn) can be controlled individually, and when multiple functions are required
  • each functional module can be controlled in turn, and a switch can be closed at the same time, so as to avoid fluctuations in the output voltage of the power supply module 40 caused by the operation of the timing controller and improve the display quality.
  • each switch (K1, K2, K3,..., Kn) is a MOS tube; the drain of the switch is connected to the corresponding functional module; the source of the switch is connected to the memory; the gate of the switch is connected to the processor Connector connection, used to access switch control analog signal.
  • the MOS tube is used as the switch, and the volume is small, which facilitates the realization of the narrow frame design of the display device.
  • a driving circuit as shown in FIGS. 11 and 12, includes: the above-mentioned timing controller 10, and a gamma chip 30, the gamma chip 30 is connected to the I2C bus 20; a power module 40 is connected to the timing controller 10 for Provide the power supply voltage to the timing controller 10.
  • the gamma chip 30 and the timing controller 10 are both connected to the I2C bus 20, and the power module 40 supplies power to the timing controller 10.
  • the internal function modules of the timing controller 10 are all turned on, causing the output voltage of the power module 40 to fluctuate.
  • the timing controller 10 provided in the above embodiment, first determine whether the address in the bus signal matches the address of the timing controller 10, and if it matches, proceed to the next step.
  • the target function module obtains working parameters from the memory 200 and starts working.
  • a display device as shown in FIG. 13, includes: a display panel 2, the above-mentioned driving circuit 1, and the driving circuit 1 is used to drive the display panel 2 to display.
  • the display device provided by the embodiment of the present application has the above-mentioned driving circuit 1, which can ensure that the output voltage of the power supply module 40 is stable without fluctuation when there is an action on the bus, thereby ensuring stable operation of various devices and stable display effect.

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Abstract

公开了一种时序控制器控制方法和时序控制器。时序控制器控制方法，包括：获取I2C总线上传输的总线信号中的总线地址，I2C总线与时序控制器连接（S10）；若判定总线地址与时序控制器的地址匹配，则获取总线信号中的数据信息（S20）；根据数据信息获得目标功能模块的地址（S30）；根据目标功能模块的地址生成并发送查询指令至存储器，且接收存储器反馈的与目标功能模块对应的开关控制数据（S40）；根据开关控制数据控制与目标功能模块连接的开关闭合（S50）。

Description

时序控制器控制方法和时序控制器
相关申请的交叉引用
本申请要求于2019年06月10日提交中国专利局、申请号为2019104950805、发明名称为“时序控制器控制方法、时序控制器和驱动电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，特别是涉及一种时序控制器控制方法和时序控制器。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
液晶电视因其重量轻，厚度薄，功耗小，已被广泛普及。现在常见的液晶面板的驱动架构，主要通过PCB(Printed Circuit Board，印制电路板)上的TCON(Timing Controller，时序控制器)对显示数据进行处理，PWM IC(Pulse-width modulation Integrated Circuit，脉宽调制芯片)提供驱动电源，Gamma IC(Gamma Integrated Circuit，伽马芯片)提供驱动液晶单元的伽马电压。
由于芯片数字化的发展，目前时序控制器和伽马芯片均通过I2C(Inter-Integrated Circuit)总线连接在一起，便于通过操作I2C对任意一个芯片进行相应的读取操作，但这种连接方式容易出现的问题是，当用户对伽马芯片进行操作的时候，也会对时序控制器的工作造成影响，会导致时序控制器内部的开关误打开，造成时序控制器的工作量增大，与该时序控制器连接的电源模块所输出的电流突然变大、输出电压异常波动，进一步造成芯片工作异常、显示异常。
发明内容
基于此，本申请的实施例提供一种时序控制器控制方法和时序控制器。
一方面，本申请实施例提供了一种时序控制器控制方法，包括：
获取I2C总线上传输的总线信号中的总线地址，I2C总线与时序控制器连接；
若判定总线地址与时序控制器的地址匹配，则获取总线信号中的数据信息；
根据数据信息获得目标功能模块的地址；
根据目标功能模块的地址生成并发送查询指令至存储器，且接收存储器反馈的与目标功能模块对应的开关控制数据；
根据开关控制数据控制与目标功能模块连接的开关闭合，使目标功能模块通过对应的开关获取存储器中存储的目标功能模块的工作参数；
其中，时序控制器由电源模块供电，时序控制器包括多个功能模块，目标功能模块是总线信号指示的被控功能模块。
本申请实施例提供的时序控制器控制方法可以通过自动检测I2C总线上传输的信号的地址，控制时序控制器内部对应地址的目标功能模块的开关闭合，避免因对伽马芯片等其他元器件进行操作时，造成的时序控制器误打开，且避免I2C总线上有信号时，时序控制器内部的功能模块全部打开造成的电源模块输出电压波动，提高电源模块的稳定性，进一步提升显示效果。
另一方面，本申请实施例提供了一种时序控制器，设置为连接I2C总线，包括：处理器、存储器、多个开关和多个功能模块；处理器和各功能模块均设置为与电源模块连接；
存储器存储有用于指示控制各开关开闭状态的开关控制数据和各功能模块的工作参数；
所述处理器与所述存储器的第一访问端连接；
各功能模块通过一一对应的开关与存储器的第二访问端连接；
处理器设置为执行上述时序控制器控制方法的处理。
附图说明
图1为液晶面板的驱动架构的示意图；
图2为示例性技术中驱动电路的结构示意图；
图3为示例性技术中电源模块电压的波形示意图；
图4为根据实施例的时序控制器控制方法的流程示意图；
图5为根据实施例的根据开关控制数据控制与目标功能模块连接的开关闭合处理的流程示意图；
图6为根据另一个实施例的根据开关控制数据控制与目标功能模块连接的开关闭合处理的流程示意图；
图7为根据实施例的时序控制器控制装置的结构示意图；
图8为根据另一个实施例的时序控制器控制装置的结构示意图；
图9为根据再一个实施例的时序控制器控制装置的结构示意图；
图10为根据实施例的计算机设备内部结构的示意图；
图11为根据实施例的时序控制器和驱动电路的结构示意图；
图12为根据另一个实施例的时序控制器和驱动电路的结构示意图；
图13为根据实施例的显示装置的结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
需要说明的是，当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件并与之结合为一体，或者可能同时存在居中元件。本文所使用的术语“安装”、“一端”、“另一端”以及类似的表述只是为了说明的目的。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
图1为液晶面板的示例性驱动架构。图2所示示例性技术中驱动电路的设计架构。当I2C总线(是由Philips公司开发的一种简单、双向二线制同步串行总线)上有动作的时候，内部的I2C slave(I2C总线从设备接口)只要检测到有动作，便会启动用于控制各开关的控制信号，将开关K1、K2、K3全部同时打开，这样时序控制器内部的OD(Over-actuated，过驱动)模块、ACC(Advanced Colour Control，精准颜色控制/自动色度控制)模块、Dither(抖动)模块便可以读取look up table(查找表)，这种设计可以提早打开内部开关，方便对时序控制器进行操作。然而，三个模块同时打开，会造成时序控制器内部处理芯片的工作量剧增，消耗的电源VDD的电流便会突然变大，容易造成电源模块输出的电压VDD不稳，造成电源模块工作异常从而出现显示异常。
如图3所示，当用户向伽马芯片输送信号，即I2C有动作的时候，原本很稳定的VDD，由于电流的突然增大，VDD电压便会进入异常波动区。
如图4所示，本申请实施例提供了一种时序控制器控制方法，包括：
S10：获取I2C总线上传输的总线信号中的总线地址，I2C总线与时序控制器连接；
S20：若判定总线地址与时序控制器的地址匹配，则获取总线信号中的数据信息；
S30：根据数据信息获得目标功能模块的地址；
S40：根据目标功能模块的地址生成并发送查询指令至存储器，且接收存储器反馈的与目标功能模块对应的开关控制数据；
S50：根据开关控制数据控制与目标功能模块连接的开关闭合，使目标功能模块通过对应的开关获取存储器中存储的目标功能模块的工作参数；
其中，时序控制器由电源模块供电，时序控制器包括多个功能模块，目标功能模块是总线信号指 示的被控功能模块。
其中，I2C总线是由Philips公司开发的一种简单、双向二线制同步串行总线。它只需要两根线即可在连接于总线上的器件之间传输信息。总线上的每个器件均有唯一的地址，根据各器件是用于传输数据还是接收数据，总线上的各器件可以分为主器件和从器件，主器件用于启动总线传输数据，并产生时钟以开放传输的器件，此时任何被寻址的器件均被认为是从器件(例如上述时序控制器中的被控功能模块)。数据信息是主器件寻址成功并接收相应从器件反馈的应答信号后，继续传输的用于指示从器件工作的数据。判定总线地址与时序控制器的地址是否匹配，可以是判断总线上传输的地址信号中除起始位的有效位数据与时序控制器的地址是否一致。目标功能模块是时序控制器中的功能模块中的其中一个或多个功能模块，目标功能模块是总线信号中的数据信息所要控制的对象。开关控制数据是与各目标功能模块的地址一一对应的、用于指示控制与各个功能模块相对应的各开关的开闭状态的数据，并且开关控制数据存储在存储器中。
具体的，如图2和图4所示，为了避免总线上有动作时，时序控制器误触发，造成电源模块输出电压的波动，先获取I2C总线上传输的总线信号中的总线地址，判断该总线地址是否与时序控制器的地址匹配，若判定地址匹配，说明时序控制器为被寻址的从器件，则进一步获取总线信号中的数据信息部分，并对该部分信息进行解析，获得目标功能模块的地址，解析过程可以是按照每个字节进行分段，然后将每个字节中的8位数据转换为时序控制器内部可识别的地址(例如，与时序控制器中功能模块的地址所采用的进制法一致)。进一步的，根据获得的目标功能模块的地址生成并发送查询指令至存储器，通过访问存储器，获得与目标功能模块对应的开关控制数据，其中，查询指令可以是包括目标功能模块的地址的指令。在接收到存储器反馈的开关控制数据后，根据该数据控制对应的开关闭合，使得目标功能模块与存储器连接，目标功能模块从存储器中获取其工作参数，进入工作状态。本申请实施例提供的时序控制器控制方法，通过先进行地址匹配判断，当时序控制器为被控的从器件时，再进行下一步时序控制器内部工作分配，根据数据信息中的目标功能模块的地址，控制与对应模块连接的开关闭合，控制目标功能模块进入工作状态。通过上述处理，提高与时序控制器连接的电源模块的稳定性，从而提高各芯片工作的稳定，不会因工作电压波动造成的显示异常，显示品质得到提高。其中，电源模块可以是PWM IC(Pulse-width modulation Integrated Circuit，脉宽调制芯片)电源。
本申请实施例提供的时序控制器控制方法，通过判断I2C总线传输的信号中的地址是否与时序控制器的地址相匹配，即判断该地址是否要发送给时序控制器，若是，再接收I2C总线后续传输的数据信息，执行下一步操作，从数据信息得到目标功能模块的地址，并根据目标功能模块的地址，生成查询指令，通过访问存储器，找到时序控制器内部目标功能模块对应的开关控制数据，然后根据该开关控制数据，控制与目标功能模块对应连接的开关闭合。而对于与总线地址不对应的功能模块，其连接 的开关不执行闭合操作，只使得目标功能模块与存储器连接，并使得目标功能模块从存储器中获取其工作参数，开始工作。本申请实施例提供的时序控制器控制方法可以通过自动检测I2C总线上传输的信号中的地址，控制时序控制器内部对应地址的目标功能模块的开关闭合，避免因对伽马芯片等其他元器件进行操作时，造成的时序控制器误打开，且避免当I2C总线上有信号时，时序控制器内部的功能模块全部打开造成的电源模块输出电压波动，提高电源模块的稳定性，进一步提升显示效果。
在其中一个实施例中，如图5所示，根据开关控制数据控制与目标功能模块连接的开关闭合包括：
S51：若接收到多个开关控制数据，则根据各开关控制数据依次控制与各目标功能模块连接的开关闭合。
为进一步减小时序控制器工作时，对电源模块的输出电压造成的影响，当接收到开关控制数据时，即需要控制多个目标功能模块时，则根据各开关控制数据依次控制各开关闭合，避免同时闭合多个开关，造成的负载过大，造成电源模块输出电压波动。
本申请实施例提供的时序控制器控制方法，在检测到总线地址与时序控制器内部的多个功能模块地址匹配时，相应的，从存储器获取多个开关控制模拟信号，为进一步减小多个功能模块同时打开对电源模块造成影响，处理器按照一定的顺序，依次根据各开关控制模拟信号控制对应的开关闭合，保证同一时间只闭合一个开关，避免瞬时功耗过大造成的电源电压不稳，提供高品质的显示装置和显示效果。
在其中一个实施例中，开关控制数据存储在查找表中，查找表表征各功能模块的地址与开关控制数据的对应关系。为方便查询，开关控制数据存储在查找表中，查找表是能够表征各功能模块的地址与开关控制数据对应关系的表格。具体表格中的存储内容，可以是功能模块的地址与开关控制数据一一对应的表格，则查询指令中可以包括目标功能模块的地址。也可以是预先定义的功能模块的编号与开关控制数据之间一一对应的表格，此时，根据目标功能模块的地址生成查询指令的过程可以是，先根据目标功能模块的地址获得该功能模块的编号，然后生成包括该编号信息的查询指令。
在其中一个实施例中，如图6所示，根据开关控制数据控制与目标功能模块连接的开关闭合包括：
S52：根据开关控制数据生成开关控制模拟信号；
S53：发送开关控制模拟信号至与目标功能模块连接的开关，控制开关闭合。
在接收到存储器反馈的开关控制数据后，将该数据转换为能够控制开关状态的模拟量的开关控制模拟信号，以便控制对应开关闭合。其中，开关可以是MOS管，体积小。例如，与抖动模块连接的开关可以是MOS管，漏极与抖动模块连接，源极与存储器连接，栅极用于接收开关控制模拟信号，栅极在接收到高电平的开关控制模拟信号时闭合，抖动模块从存储器中获取其对应的工作参数，开始工作。需要说明的是，开关还可以是其他类型的电子开关，例如晶体管等，连接方式随开关类型适应性调整， 以保证开关在接收到对应的开关控制模拟信号后能够闭合。
在其中一个实施例中，功能模块的工作参数包括过驱动模块的工作参数、精准颜色控制模块的工作参数和抖动模块的工作参数，开关控制模拟信号包括：
第一控制信号，设置为控制与过驱动模块连接的第一开关闭合，使过驱动模块从存储器获取过驱动模块的工作参数；
第二控制信号，设置为控制与精准颜色控制模块连接的第二开关闭合，使精准颜色控制模块通过第二开关从存储器获取精准颜色控制模块的工作参数；
第三控制信号，设置为控制与抖动模块连接的第三开关闭合，使抖动模块通过第三开关从存储器获取抖动模块的工作参数；
功能模块包括过驱动模块、精准颜色控制模块和抖动模块，开关包括第一开关、第二开关和第三开关。
其中，过驱动模块设置为调制时序控制器接收到的数据信号，该数据信号是用于驱动显示面板的信号。经过过驱动模块调制的数据信号能够过驱动液晶，改善液晶分子的响应速度。精准颜色控制模块是闭环的负反馈放大电路，设置为控制色度信号的幅度。精准颜色控制模块检测色度同步信号作为标准来进行控制，根据色度同步信号的大小来控制色度信号的幅度，自动改变增益，使色度信号达到一个稳定值。抖动模块可以执行随机抖动操作，可以改善数字显示器的图像逼真度。
具体的，在其中一个具体实施例中，针对于时序控制器中常用的三个功能模块，开关控制模拟信号包括第一控制信号、第二控制信号和第三控制信号，分别对应控制第一开关、第二开关和第三开关。其中，第一开关是与过驱动模块连接的开关，第二开关是与精准颜色控制模块连接的开关，第三开关是与抖动模块连接的开关。若判定总线信号中的地址与时序控制器的地址匹配，则进一步接收数据信息，对该数据信息进行解析，得到目标功能模块的地址。若该地址为过驱动模块的地址，则从存储器中获取与该地址对应的开关控制数据，并根据该数据生成第一控制信号，发送该第一控制信号至第一开关，驱动第一开关闭合，过驱动模块从存储器获取其工作数据，开始工作。同理，若需要控制的对象为精准颜色控制模块和抖动模块时，实现过程同过驱动模块。若需要控制三个功能模块均进行工作，即根据数据信息生成了三个目标功能模块的地址，则通过查询存储器，获取三个开关控制数据，并根据这三个开关控制模拟信号生成第一控制信号、第二控制信号和第三控制信号，并依次发送第一控制信号、第二控制信号和第三控制信号至对应的第一开关、第二开关和第三开关，同一时间只闭合一个开关，其中，依次打开的顺序除上述例子描述的顺序之外，还可以是其他顺序。
在其中一个实施例中，查询指令包括目标功能模块的地址。查询指令可以包括目标功能模块的地址，当存储器收到该查询指令后，可以获知该查询指令所要查询的是哪个功能模块的地址所对应的开 关控制数据，为查表提供依据。
如图7所示，本申请实施例还提供了一种时序控制器控制装置，包括：
总线地址获取单元710，设置为获取I2C总线上传输的总线信号中的总线地址，I2C总线与时序控制器连接；
数据信息获取单元720，设置为在判定总线地址与时序控制器的地址匹配时，获取总线信号中的数据信息；
目标功能模块地址获取单元730，设置为根据数据信息获得目标功能模块的地址；
开关控制数据获取单元740，设置为根据目标功能模块的地址生成并发送查询指令至存储器，且接收存储器反馈的与目标功能模块对应的开关控制数据；以及
开关控制单元750，设置为根据开关控制数据控制与目标功能模块连接的开关闭合，使目标功能模块通过对应的开关获取存储器中存储的目标功能模块的工作参数；
其中，时序控制器由电源模块供电，时序控制器包括多个功能模块，目标功能模块是总线信号指示的被控功能模块。
其中，功能模块、开关等释义与上述时序控制器控制方法中的释义相同，在此不作赘述。
在其中一个实施例中，如图8所示，开关控制单元750包括：
开关顺序控制单元751，设置为在接收到多个开关控制数据时，根据各开关控制数据依次控制与各目标功能模块连接的开关闭合。
在其中一个实施例中，如图9所示，开关控制单元750还包括：
开关控制模拟信号生成单元752，设置为根据开关控制数据生成开关控制模拟信号；
开关控制模拟信号发送单元753，设置为发送开关控制模拟信号至与目标功能模块连接的开关，以控制开关闭合。
在一个实施例中，提供了一种计算机设备，该计算机设备可以是终端，其内部结构图可以如图10所示。该计算机设备包括通过***总线连接的处理器、存储器、网络接口、显示屏和输入装置。其中，该计算机设备的处理器用于提供计算和控制能力。该计算机设备的存储器包括非易失性存储介质、内存储器。该非易失性存储介质存储有操作***和计算机程序。该内存储器为非易失性存储介质中的操作***和计算机程序的运行提供环境。该计算机设备的网络接口用于与外部的终端通过网络连接通信。该计算机程序被处理器执行时以实现一种时序控制器控制方法。该计算机设备的显示屏可以是液晶显示屏或者电子墨水显示屏，该计算机设备的输入装置可以是显示屏上覆盖的触摸层，也可以是计算机设备外壳上设置的按键、轨迹球或触控板，还可以是外接的键盘、触控板或鼠标等。
本领域技术人员可以理解，图10中示出的结构，仅仅是与本申请方案相关的部分结构的框图，并 不构成对本申请方案所应用于其上的计算机设备的限定，具体的计算机设备可以包括比图中所示更多或更少的部件，或者组合某些部件，或者具有不同的部件布置。
一种计算机设备，包括存储器和处理器，存储器存储有计算机程序，处理器执行计算机程序时实现以下处理：
S10：获取I2C总线上传输的总线信号中的总线地址，I2C总线与时序控制器连接；
S20：若判定总线地址与时序控制器的地址匹配，则获取总线信号中的数据信息；
S30：根据数据信息获得目标功能模块的地址；
S40：根据目标功能模块的地址生成并发送查询指令至存储器，且接收存储器反馈的与目标功能模块对应的开关控制数据；
S50：根据开关控制数据控制与目标功能模块连接的开关闭合，使目标功能模块通过对应的开关获取存储器中存储的目标功能模块的工作参数；
其中，时序控制器由电源模块供电，时序控制器包括多个功能模块，目标功能模块是总线信号指示的被控功能模块。
本申请提供的计算机设备可以执行上述方法实施例中的所有处理，本申请提供的计算机设备可以在判断总线地址与时序控制器的地址匹配后再进行功能模块的工作分配，避免总线上有动作时，时序控制器误动作，造成电源模块输出电压波动，提高显示稳定性。
一种计算机可读存储介质，其上存储有计算机程序，计算机程序被处理器执行时实现以下处理：
S10：获取I2C总线上传输的总线信号中的总线地址，I2C总线与时序控制器连接；
S20：若判定总线地址与时序控制器的地址匹配，则获取总线信号中的数据信息；
S30：根据数据信息获得目标功能模块的地址；
S40：根据目标功能模块的地址生成并发送查询指令至存储器，且接收存储器反馈的与目标功能模块对应的开关控制数据；
S50：根据开关控制数据控制与目标功能模块连接的开关闭合，使目标功能模块通过对应的开关获取存储器中存储的目标功能模块的工作参数；
其中，时序控制器由电源模块供电，时序控制器包括多个功能模块，目标功能模块是总线信号指示的被控功能模块。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一非易失性计算机可读取存储介质中，该计算机程序在执行时，可包括如上述各方法的实施例的流程。其中，本申请所提供的各实施例中所使用的对存储器、存储、数据库或其它介质的任何引用，均可包括非易失性和/或易失性存储器。非易失性存 储器可包括只读存储器(ROM)、可编程ROM(PROM)、电可编程ROM(EPROM)、电可擦除可编程ROM(EEPROM)或闪存。易失性存储器可包括随机存取存储器(RAM)或者外部高速缓冲存储器。作为说明而非局限，RAM以多种形式可得，诸如静态RAM(SRAM)、动态RAM(DRAM)、同步DRAM(SDRAM)、双数据率SDRAM(DDRSDRAM)、增强型SDRAM(ESDRAM)、同步链路(Synchlink)DRAM(SLDRAM)、存储器总线(Rambus)直接RAM(RDRAM)、直接存储器总线动态RAM(DRDRAM)、以及存储器总线动态RAM(RDRAM)等。
另一方面，如图11所示，本申请实施例还提供了一种时序控制器10，包括：处理器100、存储器200、多个开关和多个功能模块400；处理器100和各功能模块400均与电源模块40连接；
存储器200存储有用于指示控制各开关开闭状态的开关控制数据和各功能模块400的工作参数；
处理器100与存储器200的第一访问端连接；
各功能模块400通过一一对应的开关与存储器200的第二访问端连接；
处理器100用于执行上述时序控制器10控制方法的处理。
其中，功能模块400、开关等释义与上述时序控制器10控制方法中的释义相同，在此不作赘述。本申请实施例提供的时序控制器10，通过集成有处理器100与其他器件，能够先判断总线20上的总线信号中的总线地址是否与自身匹配，若匹配再进行下一步工作。具体的，根据总线信号中的数据信息，生成目标功能模块400的地址，并进一步根据该目标功能模块400的地址生成查询指令，通过查询存储器200，得到该目标功能模块400的地址对应的开关控制数据，然后根据开关控制数据控制与目标功能模块400连接的开关闭合，使目标功能模块400开始工作。避免时序控制器10误触发造成的电源模块40输出电压波动，提升显示稳定性和品质。
在其中一个实施例中，如图12所示，处理器100设置为根据开关控制数据生成开关控制模拟信号，并发送开关控制模拟信号至与目标功能模块400连接的开关，控制开关闭合；功能模块的工作参数包括过驱动模块410的工作参数、精准颜色控制模块420的工作参数和抖动模块430的工作参数，开关控制模拟信号(C1、C2、……、Cn)包括第一控制信号C1、第二控制信号C2和第三控制信号C3，开关包括：
第一开关K1，第一开关K1的第一端与存储器200的第二访问端连接；
第二开关K2，第二开关K2的第一端与存储器200的第二访问端连接；
第三开关K3，第三开关K3的第一端与存储器200的第二访问端连接；
功能模块包括：
过驱动模块410，过驱动模块410的输入端与第一开关K1的第二端连接；
精准颜色控制模块420，精准颜色控制模块420的输入端与第二开关K2的第二端连接；
抖动模块430，抖动模块430的输入端与第三开关K3的第二端连接；
处理器设置为根据第一控制信号C1控制第一开关K1闭合，设置为根据第二控制信号C2控制第二开关K2闭合；还设置为根据第三控制信号C3控制第三开关K3闭合。
其中，第一开关K1、第二控制信号等释义与上述方法实施例中相同，在此不做赘述。通过各控制信号(C1、C2、……、Cn)与各开关一一对应的方式，能够单独控制各开关(K1、K2、K3、……、Kn)的开关状态，在需要对多个功能模块进行控制时，可以依次控制各功能模块，同一时间闭合一个开关，避免因时序控制器工作造成的电源模块40输出电压波动，提升显示品质。
在其中一个实施例中，各开关(K1、K2、K3、……、Kn)为MOS管；开关的漏极与对应的功能模块连接；开关的源极与存储器连接；开关的栅极与处理器连接，用于接入开关控制模拟信号。采用MOS管作为开关，体积小，利于实现显示装置的窄边框设计。
一种驱动电路，如图11和图12所示，包括：上述时序控制器10，以及伽马芯片30，伽马芯片30连接I2C总线20；电源模块40，与时序控制器10连接，用于提供电源电压至时序控制器10。
本申请实施例提供的驱动电路，伽马芯片30和时序控制器10均连接I2C总线20，电源模块40为时序控制器10供电，为避免对伽马芯片30进行操作时，时序控制器10误动作，时序控制器10内部功能模块全部打开，造成电源模块40输出电压波动。采用上述实施例中提供的时序控制器10，先判断总线信号中的地址是否与时序控制器10的地址匹配，若匹配再进行下一步工作。根据总线信号中的数据信息得到需要控制的目标功能模块的地址，然后根据该地址，进行查表等，从存储器200中获取目标功能模块对应的开关控制数据，根据该数据控制对应的开关闭合，目标功能模块从存储器200获取工作参数，开始工作。
一种显示装置，如图13所示，包括：显示面板2、上述驱动电路1，驱动电路1用于驱动显示面板2显示。
本申请实施例提供的显示装置具有上述驱动电路1，能够保证在总线上有动作时，电源模块40的输出电压稳定，无波动现象，进而保证各器件稳定工作，显示效果稳定。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (17)

  1. 一种时序控制器控制方法，包括：
    获取I2C总线上传输的总线信号中的总线地址，所述I2C总线与时序控制器连接；
    若判定所述总线地址与时序控制器的地址匹配，则获取所述总线信号中的数据信息；
    根据所述数据信息获得目标功能模块的地址；
    根据所述目标功能模块的地址生成并发送查询指令至存储器，且接收所述存储器反馈的与所述目标功能模块对应的开关控制数据；
    根据所述开关控制数据控制与所述目标功能模块连接的开关闭合，使所述目标功能模块通过对应的开关获取所述存储器中存储的目标功能模块的工作参数；
    其中，所述时序控制器由电源模块供电，所述时序控制器包括多个功能模块，所述目标功能模块是所述总线信号指示的被控功能模块。
  2. 根据权利要求1所述的时序控制器控制方法，其中，判定所述总线地址与所述时序控制器的地址匹配包括：
    判断所述总线上传输的信号中用于寻址的数据中除起始位以外的有效位数据与所述时序控制器的地址对应的数据是否一致。
  3. 根据权利要求1所述的时序控制器控制方法，其中，根据所述数据信息获得目标功能模块的地址包括：
    获取总线信号中的数据信息部分，并对该数据信息部分进行解析，以将所述总线信号转换为所述时序控制器内部可识别的地址。
  4. 根据权利要求1所述的时序控制器控制方法，其中，根据所述开关控制数据控制与所述目标功能模块连接的开关闭合包括：
    若接收到多个所述开关控制数据，则根据各所述开关控制数据依次控制与各所述目标功能模块连接的开关闭合。
  5. 根据权利要求1所述的时序控制器控制方法，其中，所述开关控制数据存储在查找表中，所述查找表表征各功能模块的地址与开关控制数据的对应关系。
  6. 根据权利要求5所述的时序控制器控制方法，其中，所述查找表存储各功能模块的地址与开关控制数据之间的对应关系。
  7. 根据权利要求5所述的时序控制器控制方法，其中，所述查找表存储各功能模块的预先定义的编号与开关控制数据之间的对应关系。
  8. 根据权利要求1所述的时序控制器控制方法，其中，根据所述开关控制数据控制与所述目标功 能模块连接的开关闭合包括：
    根据所述开关控制数据生成开关控制模拟信号；
    发送所述开关控制模拟信号至与所述目标功能模块连接的开关，控制所述开关闭合。
  9. 根据权利要求8所述的时序控制器控制方法，其中，所述功能模块的工作参数包括过驱动模块的工作参数、精准颜色控制模块的工作参数和抖动模块的工作参数，所述开关控制模拟信号包括：
    第一控制信号，设置为控制与过驱动模块连接的第一开关闭合，使过驱动模块从所述存储器获取过驱动模块的工作参数；
    第二控制信号，设置为控制与精准颜色控制模块连接的第二开关闭合，使精准颜色控制模块通过所述第二开关从所述存储器获取精准颜色控制模块的工作参数；以及
    第三控制信号，设置为控制与抖动模块连接的第三开关闭合，使抖动模块通过所述第三开关从所述存储器获取抖动模块的工作参数；
    所述功能模块包括过所述驱动模块、所述精准颜色控制模块和所述抖动模块，所述开关包括所述第一开关、所述第二开关和所述第三开关。
  10. 根据权利要求1所述的时序控制器控制方法，其中，所述查询指令包括所述目标功能模块的地址。
  11. 根据权利要求1所述的时序控制器控制方法，其中，所述开关为MOS管。
  12. 根据权利要求1所述的时序控制器控制方法，其中，所述电源模块是脉宽调制芯片电源。
  13. 一种时序控制器，设置为连接I2C总线，包括：处理器、存储器、多个开关和多个功能模块；所述处理器和各所述功能模块均设置为与电源模块连接；
    所述存储器存储有用于指示控制各开关开闭状态的开关控制数据和各所述功能模块的工作参数；
    所述处理器与所述存储器的第一访问端连接；
    各所述功能模块通过一一对应的开关与所述存储器的第二访问端连接；
    所述处理器设置为执行如下处理：
    获取I2C总线上传输的总线信号中的总线地址，所述I2C总线与时序控制器连接；
    若判定所述总线地址与时序控制器的地址匹配，则获取所述总线信号中的数据信息；
    根据所述数据信息获得目标功能模块的地址；
    根据所述目标功能模块的地址生成并发送查询指令至存储器，且接收所述存储器反馈的与所述目标功能模块对应的开关控制数据；
    根据所述开关控制数据控制与所述目标功能模块连接的开关闭合，使所述目标功能模块通过对应的开关获取所述存储器中存储的目标功能模块的工作参数；
    其中，所述目标功能模块是所述总线信号指示的被控功能模块。
  14. 根据权利要求13所述的时序控制器，其中，所述处理器用于根据所述开关控制数据生成开关控制模拟信号，并发送所述开关控制模拟信号至与所述目标功能模块连接的开关，控制所述开关闭合；所述功能模块的工作参数包括过驱动模块的工作参数、精准颜色控制模块的工作参数和抖动模块的工作参数，所述开关控制模拟信号包括第一控制信号、第二控制信号和第三控制信号，所述开关包括：
    第一开关，所述第一开关的第一端与所述存储器的第二访问端连接；
    第二开关，所述第二开关的第一端与所述存储器的第二访问端连接；
    第三开关，所述第三开关的第一端与所述存储器的第二访问端连接；
    所述功能模块包括：
    过驱动模块，所述过驱动模块的输入端与所述第一开关的第二端连接；
    精准颜色控制模块，所述精准颜色控制模块的输入端与所述第二开关的第二端连接；
    抖动模块，所述抖动模块的输入端与所述第三开关的第二端连接；
    所述处理器设置为根据所述第一控制信号控制所述第一开关闭合，并且设置为根据所述第二控制信号控制所述第二开关闭合；还设置为根据所述第三控制信号控制所述第三开关闭合。
  15. 根据权利要求14所述的时序控制器，其中，各所述开关为MOS管；所述开关的漏极与对应的功能模块连接；所述开关的源极与所述存储器连接；所述开关的栅极与所述处理器连接，设置为接入所述开关控制模拟信号。
  16. 根据权利要求13所述的时序控制器，其中，当接收到多个所述开关控制数据时，所述处理器还设置为执行：根据各所述开关控制数据依次控制与各所述目标功能模块连接的开关闭合。
  17. 根据权利要求13所述的时序控制器，其中，所述存储器还存储有查找表，所述开关控制数据存储在所述查找表中，所述查找表表征各功能模块的地址与开关控制数据的对应关系。
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