WO2020224124A1 - Pixel compensation method and liquid crystal display apparatus - Google Patents

Pixel compensation method and liquid crystal display apparatus Download PDF

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Publication number
WO2020224124A1
WO2020224124A1 PCT/CN2019/103537 CN2019103537W WO2020224124A1 WO 2020224124 A1 WO2020224124 A1 WO 2020224124A1 CN 2019103537 W CN2019103537 W CN 2019103537W WO 2020224124 A1 WO2020224124 A1 WO 2020224124A1
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Prior art keywords
pixel
pixel electrode
gate
source
electrode
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PCT/CN2019/103537
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French (fr)
Chinese (zh)
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文超平
舒强
孙飞翔
黄威
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南京中电熊猫液晶显示科技有限公司
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Publication of WO2020224124A1 publication Critical patent/WO2020224124A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the invention belongs to the technical field of liquid crystal display, and in particular relates to a pixel compensation method and a liquid crystal display device.
  • DeMUX technology is widely used in liquid crystal display panels. It can transmit the scan signal S output by the source driver to n columns of pixels in the form of 1:m, such as 1:2, 1:3, etc. Take 1:2 as an example.
  • the two sets of TFTs are controlled by two clock signals CK1 and CK2 so that the scan signal S output by a source driver is output to the data line D of two columns of pixels in a time-sharing manner, so that the source
  • the data lines output by the driver can be reduced by at least half, and the number of source drivers can also be reduced, thereby reducing the cost of panel design, reducing the width of the lower frame of the panel, and enabling the panel to meet the high specification requirements of a narrower frame.
  • the scanning signal S is transmitted to the data line D in a time-sharing manner. It is necessary to use a thin film transistor TFT as a switch, and also to introduce a clock signal CK to control the TFT switch. Since the clock signal CK is turned off, it will affect the potential of the data line and thus the potential of the charged pixel through the coupling capacitor Ckd, and different clock signals CK have different effects on the feedback voltage of the pixel due to the inconsistent turn-off time.
  • a back channel type TFT as shown in FIG.
  • the panel includes a gate electrode 01, an insulating layer 02, a semiconductor layer 03, a source electrode 04 and a drain electrode 05, and the gate electrode 01 and source electrode 04 of the TFT device.
  • Both the gate 01 and the drain 05 have an overlapping area, and there will be parasitic capacitances Cgs and Cgd.
  • Cgs and Cgd As shown in FIG. 2, due to the existence of the parasitic capacitance, in the demultiplexing circuit part, there will be a relatively large coupling capacitance Ckd between the signal line of the clock signal CK and the data line D. Due to the existence of the coupling capacitor Ckd, when the data line potential reaches a predetermined value, the clock signal CK controls the TFT to turn off.
  • the data line potential will also undergo a certain jump due to the potential jump of the clock signal CK and the coupling capacitor. It can be regarded as the feedback voltage (Feedthrough) of the data line potential caused by the turning off of the clock signal CK. Since the gate of the first charged pixel is still open, the pixel electrode will leak to the data line affected by the feedback voltage of the clock signal, which is indirectly affected by the feedback voltage caused by the clock signal being turned off. The last turned-on pixel may not be affected by the feedback voltage of the clock signal, but only the feedback voltage of the gate Gn. This will cause different pixels to receive different feedback voltages, resulting in poor display such as color shift, horizontal and vertical stripes, and flicker on the display. problem.
  • a solution can form an overlap compensation capacitor by overlapping the signal line and the data line of the extra inverted clock signal CK' opposite to the clock signal CK on the demultiplexing circuit, thereby forming an overlap compensation capacitor.
  • the potential of the pixel electrode is compensated to prevent the transition of the clock signal CK from affecting the pixel electrode potential.
  • this compensation method additionally adds a compensation circuit for compensation, which will inevitably occupy additional design space of the panel, and the additional signal will increase the overall power consumption of the panel.
  • the present invention provides a pixel compensation method and a liquid crystal display device, which are designed for the differential design of the coupling capacitance Cgp between the pixel electrode and the gate in the pixel, in particular, the The coupling capacitor Cgp of the pixel controlled by the first signal is appropriately increased to avoid poor display such as color shift, flicker, horizontal and vertical stripes.
  • the present invention provides a pixel compensation method for a liquid crystal display device using a demultiplexing circuit, and the pixel compensation method includes:
  • the source signal output by the source driver is time-shared and transmitted to the data lines corresponding to the multiple pixel units.
  • Each pixel unit corresponds to a clock signal.
  • the coupling capacitance between the pixel electrode and the gate of each pixel unit makes the total feedback voltage received by the pixel electrode of each pixel unit the same.
  • the total feedback voltage includes the feedback voltage generated by the clock signal to the pixel unit and the gate scan The feedback voltage generated by the signal to the pixel unit;
  • the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the clock signal that is turned on last is larger than the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the other clock signals.
  • the total feedback voltage received by the pixel electrode of each pixel unit satisfies the following relationship:
  • Cgp is the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by other clock signals
  • Cgp' is the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the last clock signal.
  • ⁇ VCK is the equivalent high and low potential difference of the pixels controlled by other clock signals
  • ⁇ VCK' is the equivalent high and low potential difference of the pixels controlled by the last clock signal
  • Cp is the pixel electrode potential and The total capacitance formed between other potentials
  • Cd is the total capacitance formed between the potential of the data line and other potentials of the panel
  • ⁇ VG is the voltage difference of the gate, m>1.
  • the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the clock signal and the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the other clock signals satisfy the following Relationship:
  • the present invention provides a liquid crystal display device, which adopts the pixel compensation method described in the foregoing embodiments, and each pixel unit of the liquid crystal display device includes:
  • a common electrode located on the second insulating layer, the common electrode is provided with a common electrode hole;
  • the pixel electrode located on the third insulating layer, the pixel electrode is electrically connected to the source;
  • the source of the pixel unit controlled by the last clock signal further includes a source extension, the source extension is located above the gate, and the source extension and the gate all overlap .
  • the first hole and the second hole are combined to form an insulating layer hole, and the pixel electrode is electrically connected to the source electrode through the insulating layer hole.
  • the hole diameter of the common electrode hole is larger than the hole diameter of the insulating layer hole, and the third insulating layer covers the side surface of the common electrode hole.
  • the pixel electrode of each pixel unit includes a pixel electrode body; the pixel electrode of the pixel unit controlled by a clock signal that is turned on last also includes a pixel electrode extension part between the pixel electrode extension part and the gate. All overlap.
  • the present invention also provides a liquid crystal display device, which adopts the pixel compensation method described in the foregoing embodiments, and each pixel unit of the liquid crystal display device includes:
  • Drain and source located on the semiconductor layer
  • a common electrode located on the second insulating layer, the common electrode is provided with a common electrode hole;
  • the pixel electrode of the pixel unit controlled by a clock signal last turned on further includes a pixel electrode extension, and the pixel electrode extension and the gate are all overlapped.
  • the pixel electrode extension is received in the common electrode hole.
  • the present invention also provides a liquid crystal display device, including:
  • a demultiplexing circuit for transmitting the source signal output by the source driver to each first data line to the second data line corresponding to the multiple pixel units under the control of multiple clock signals;
  • the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the clock signal is greater than the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the other clock signals, so that the pixels of each pixel unit
  • the total feedback voltage received by the electrodes is the same, and the total feedback voltage includes the feedback voltage generated by the clock signal to the pixel unit and the feedback voltage generated by the gate scan signal to the pixel unit.
  • the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the clock signal and the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the other clock signals satisfy the following Relationship:
  • Cgp' is the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the last clock signal
  • Cgp is the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by other clock signals, x >0.
  • the source of the pixel unit controlled by a clock signal that is turned on last includes a source body and a source extension, and the source body and the gate partially overlap each other. All overlap between the source extension and the gate.
  • the pixel electrode of the pixel unit controlled by a clock signal that is turned on last includes a pixel electrode body and a pixel electrode extension.
  • the pixel electrode body and the gate partially overlap each other.
  • the pixel electrode extension part and the gate are all overlapped.
  • the embodiment of the present invention can make the difference in the feedback voltage of the common gate Gn offset the difference in the feedback voltage caused by different clock signals CK, so that the total feedback voltage of the pixel electrode is equal, thereby avoiding color shift, Flickering, horizontal and vertical stripes, etc. display poorly.
  • FIG. 1 is a schematic diagram of the structure of an existing back-channel type TFT
  • Figure 2 is a schematic diagram of the parasitic capacitance of the existing demultiplexing circuit Mux;
  • FIG. 3 is a schematic circuit diagram of a Mux 1:2 liquid crystal display device according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a first embodiment of a pixel unit in a liquid crystal display device according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of the A-A' cross-sectional structure of the first embodiment of the pixel unit in the liquid crystal display device of the embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a second embodiment of a pixel unit in a liquid crystal display device according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a B-B' cross-sectional structure of a second embodiment of a pixel unit in a liquid crystal display device according to an embodiment of the present invention.
  • the pixel compensation method of the present invention is applied to a liquid crystal display device and includes:
  • the source signal output by the source driver (Source IC) is transmitted to the data line of m columns of pixels in a time-sharing format of 1:m.
  • Each pixel corresponds to a clock signal.
  • the coupling capacitor in each pixel is designed differently to make each pixel
  • the total feedback voltage received by the electrodes is the same.
  • the total feedback voltage includes the feedback voltage generated by the clock signal to the pixel and the feedback voltage generated by the gate scanning signal to the pixel.
  • the coupling capacitance between the gate potential of the pixel controlled by the last clock signal and the pixel electrode potential is larger than the coupling capacitance between the gate potential and the pixel electrode potential of the remaining m-1 pixels, m>1.
  • VfCK Ckd/Cd* ⁇ VCK
  • Vf is the total feedback voltage
  • VfG is the feedback voltage of the gate
  • VfCK is the feedback voltage of the clock signal
  • Cgp is the coupling capacitance between the gate potential and the pixel electrode potential
  • Cp is the formation between the pixel electrode potential and other potentials
  • ⁇ VG is the voltage difference of the gate
  • Ckd is the coupling capacitance between the data line and the clock signal
  • Cd is the total capacitance formed between the data line potential and other potentials of the panel
  • ⁇ VCK is the clock signal to control it The equivalent high and low potential difference affected by the pixel.
  • the total feedback voltage received by the pixel electrode of the pixel controlled by the first m-1 clock signal is the same as the total feedback voltage received by the pixel electrode of the pixel controlled by the last clock signal.
  • Each pixel receives the clock signal and gate scan If the sum of the feedback voltages of the signals is the same, in order to make the above equation hold, the method adopted in the present invention is that the Cgp' of the pixel controlled by the clock signal CKm is different from the Cgp of the pixel controlled by other clock signals.
  • the capacitance Cp, the total capacitance of the data line Cd, the coupling capacitance Ckd between each clock signal CK and the data line are all the same, so the formula is simplified to:
  • the left term of the equation is the total feedback voltage received by the pixel electrode of the pixel controlled by the first m-1 clock signal
  • the right term of the equation is the total feedback voltage received by the pixel electrode of the pixel controlled by the last clock signal CKm
  • Cgp is the coupling capacitance between the gate potential and the pixel electrode potential of the pixel controlled by the m-1 clock signal that is turned on first
  • Cgp' is the coupling capacitance between the gate potential and the pixel electrode potential of the pixel controlled by the last turned on clock signal
  • Coupling capacitor ⁇ VCK is the equivalent high and low potential difference of the pixels controlled by the m-1 channel clock signal that is turned on first
  • ⁇ VCK' is the equivalent high and low potential difference of the pixels controlled by the last turned on clock signal .
  • FIG. 3 is a schematic structural diagram of a Mux 1:2 liquid crystal display device according to an embodiment of the present invention.
  • the liquid crystal display device of the embodiment of the present invention adopts a demultiplexing circuit, and the demultiplexing circuit outputs the source driver to each first data line under the control of a set of clock signals.
  • the source signal is transmitted to the second data line corresponding to the m pixels in a time-sharing format of 1:m.
  • different clock signals in the set of clock signals respectively control a corresponding pixel in the m pixels; the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the last clock signal is larger than the remaining m-1
  • m is an integer greater than 1.
  • the Cgp' of the pixel unit controlled by the last clock signal CKm is the same as the Cgp of other pixels. From the pixel charging curve of the two pixel units charging the same voltage, it can be seen that the final The charging potential is different, and the total feedback voltage of the two pixel units is also different.
  • the above-mentioned pixel compensation method of the present invention is not directed to any pixel structure, and the method of increasing the coupling capacitance Cgp between the gate potential and the display electrode potential is not limited to increasing the overlap area.
  • the following specific examples introduce three schemes. These three methods are just a few of the various S schemes for increasing the overlap area. It is not an exhaustive list. It is explained that any method that helps increase the coupling capacitance Cgp between the gate potential and the display electrode potential can be used as the liquid crystal display device of the present invention.
  • FIGS. 6 and 7 are respectively a schematic structural diagram and a schematic cross-sectional structure diagram of A-A' of the first embodiment of the pixel unit in the liquid crystal display device of the embodiment of the present invention.
  • the liquid crystal display device of this embodiment adopts the above-mentioned pixel compensation method and adopts a demultiplexing circuit.
  • Each pixel of the liquid crystal display device has the following structure: a substrate (not shown), a substrate It can be but not limited to a glass substrate.
  • the gate 1 is formed on the substrate.
  • the material of the gate 1 can be a single metal or a composite metal.
  • the first insulating layer 2 and the first insulating layer 2 are located on the layer where the gate 1 is located.
  • It may include a film layer using SiOx and/or SiNx; a semiconductor layer 3 on the first insulating layer 2, and the semiconductor layer 3 may include a metal oxide semiconductor layer such as IGZO; a drain electrode 4 and a source electrode 5 on the semiconductor layer 3 , The drain 4 and the source 5 are one or more metal layer structures; the second insulating layer 6 located on the layer where the source 4 and the drain 5 are located, the second insulating layer 6 is provided with a first hole 61, The material of the second insulating layer 6 may include SiOx, SiNx or a combination of the two; the common electrode 7 located on the second insulating layer 6 has a common electrode hole 71 on the common electrode 7; the common electrode 7 located on the layer where the common electrode 7 is located The third insulating layer 8 is provided with a second hole 81 on the third insulating layer 8.
  • the third insulating layer 8 may be an organic insulating layer; the pixel electrode 9 located on the third insulating layer 8, the pixel electrode 9 and the source electrode 5 Electrical connection.
  • the data line (not shown in the figure) is connected to the drain 4 and provides a signal.
  • the source 5 of each pixel unit controlled by a clock signal includes a source body 51, which is located on the first insulating layer 2, and a part of the source body 51 overlaps the gate 1. The remaining part does not overlap with the gate 1.
  • the source 5 of the pixel unit controlled by the last clock signal that is turned on further includes a source extension 52.
  • the source extension portion 52 may be an extension portion extending from the source body 51 and is a part of the source body 51.
  • the source extension 52 may also be an independent part relative to the source body 51.
  • the source extension 52 is all located above the gate 1, and the source extension 52 overlaps the gate 1, thus increasing the overlap area between the source and the gate connected to the pixel electrode, thereby increasing The coupling capacitance Cgp between the gate potential and the pixel electrode potential is increased.
  • the first hole 61, the second hole 81 and the common electrode hole 71 are arranged concentrically, and the first hole 61, the second hole 81 and the common electrode hole 71 are all square holes.
  • the first hole 61, the second hole 81 and the common electrode hole 71 may also include other regular-shaped openings such as circular holes.
  • the first hole 61 and the second hole 81 are combined to form an insulating layer hole, and the pixel electrode 9 is in contact with and electrically connected to the source electrode 5 through the insulating layer hole formed by the first hole 61 and the second hole 81.
  • the hole diameter of the common electrode hole 71 is larger than the hole diameter of the insulating layer formed by the first hole 61 and the second hole 81.
  • the third insulating layer 8 is disposed between the pixel electrode 9 and the common electrode 7, and the third insulating layer 8 covers the side surface of the opening of the common electrode hole 71.
  • a source electrode extension is formed, which increases the overlap area between the source electrode and the gate electrode connected to the pixel electrode , whereby increasing the coupling capacitor Cgp, and without adding any additional compensation signal and compensation circuit, the differential design of the coupling capacitor Cgp in the pixel achieves the effect of making the total feedback voltage received by each pixel electrode consistent.
  • FIGS. 8 and 9 are respectively a schematic structural diagram and a B-B' cross-sectional structural schematic diagram of a second embodiment of a pixel unit in a liquid crystal display device of an embodiment of the present invention.
  • the liquid crystal display device of this embodiment adopts the above-mentioned pixel compensation method and adopts a demultiplexing circuit.
  • Each pixel of the liquid crystal display device has the following structure: a substrate (not shown), The substrate can be, but not limited to, a glass substrate.
  • the gate 1 is formed on the substrate.
  • the material of the gate 1 can be a single metal or a composite metal.
  • the first insulating layer 2 on the layer where the gate 1 is located may include a film layer using SiOx and/or SiNx, a semiconductor layer 3 located on the first insulating layer 2, the semiconductor layer 3 may include a metal oxide semiconductor layer such as IGZO, a drain 4 and a source located on the semiconductor layer 3 5.
  • the drain electrode 4 and the source electrode 5 are of one or more metal layer structures.
  • the second insulating layer 6 is located on the layer where the source electrode 4 and the drain electrode 5 are located.
  • the second insulating layer 6 is provided with a first hole 61 ,
  • the material of the second insulating layer 6 can be SiOx, SiNx or a combination of the two; the common electrode 7 on the second insulating layer 6 has a common electrode hole 71 on the common electrode 7; on the layer where the common electrode 7 is located
  • the third insulating layer 8 is provided with a second hole 81 on the third insulating layer 8.
  • the third insulating layer 8 can be an organic insulating layer, the pixel electrode 9 located on the third insulating layer 8, the pixel electrode 9 and the source 5 Electrical connection.
  • the data line (not shown in the figure) is connected to the drain 4 and provides a signal.
  • the first hole 61, the second hole 81 and the common electrode hole 71 are all arranged concentrically.
  • the first hole 61, the second hole 81 and the common electrode hole 71 may be square holes or circular holes and other regular-shaped openings, preferably As shown in FIG. 9, the first hole 61, the second hole 81 and the common electrode hole 71 are all square holes.
  • the first hole 61 and the second hole 81 are combined to form an insulating layer hole, and the pixel electrode 9 is in contact with and electrically connected to the source electrode 5 through the insulating layer hole formed by the first hole 61 and the second hole 81.
  • the hole diameter of the common electrode hole 71 is larger than the hole diameter of the insulating layer formed by the first hole 61 and the second hole 81. There is no contact between the pixel electrode 9 and the common electrode 7, the third insulating layer 8 is disposed between the pixel electrode 9 and the common electrode 7, and the third insulating layer 8 covers the side surface of the opening of the common electrode hole 71.
  • the pixel electrode 9 of the pixel unit controlled by each clock signal includes a pixel electrode body 91, which is located on the third insulating layer 8. A part of the pixel electrode body 91 overlaps the gate electrode 1, and the remaining part overlaps the gate electrode 1. Does not form overlap.
  • the pixel electrode 9 of the pixel controlled by a clock signal that is turned on last also includes a pixel electrode extension 92.
  • the pixel electrode extension 92 is an independent part relative to the pixel electrode body 91, and the area of the pixel electrode extension 92 is smaller than that of the pixel electrode body 91.
  • the pixel electrode extension 92 can also be an extension extending from the pixel electrode body 91.
  • the source 5 of the pixel unit controlled by the last clock signal does not include the source extension.
  • the pixel electrode extension 92 is accommodated in the common electrode hole 71.
  • the opening of the common electrode hole 71 is larger than the existing common electrode hole.
  • the portion 92 is located on the third insulating layer 8, and there is also a third insulating layer 8 between the pixel electrode extension 92 and the common electrode 7.
  • the pixel electrode extension 92 is all located above the gate 1. Below the pixel electrode extension 92 are the third insulating layer 8, the second insulating layer 6, the first insulating layer 2, and the gate 1. The electrode extension 92 completely overlaps the gate electrode 1, thereby increasing the overlapping area between the pixel electrode connected to the source and the gate electrode, thereby increasing the coupling capacitance between the gate electrode potential and the pixel electrode potential Cgp.
  • a second hole may also be provided on the third insulating layer 8 under the pixel electrode extension 92, so that the pixel electrode extension 92 is located in the second hole, thereby Below the pixel electrode extension 92 are the second insulating layer 6, the first insulating layer 2 and the gate 1 in this order, and the third insulating layer 8 is provided between the pixel electrode extension 92 and the common electrode 7.
  • the shape of the pixel electrode of the pixel unit controlled by the last clock signal is extended to form a pixel electrode extension, which increases the overlap area between the pixel electrode and the gate connected to the source. , Thereby increasing the coupling capacitor Cgp, and without adding any additional compensation signal and compensation circuit, the differential design of the coupling capacitor Cgp in the pixel achieves the effect of making the total feedback voltage received by each pixel electrode consistent.
  • the first and second embodiments of the above-mentioned pixel unit can also be implemented in combination, that is, the source 5 of each pixel unit controlled by a clock signal includes a source body 51, which is located at On the first insulating layer 2, a part of the source body 51 overlaps with the gate 1, and the remaining part does not overlap with the gate 1.
  • the pixel electrode 9 of each pixel unit controlled by a clock signal includes a pixel electrode body 91, The pixel electrode body 91 is located on the third insulating layer 8, a part of the pixel electrode body 91 overlaps the gate 1, and the remaining part does not overlap the gate 1.
  • the source 5 of the pixel unit controlled by the last clock signal further includes a source extension 52.
  • the source extension 52 may be an extension extending from the source body 51, or may be opposite to the source body 51.
  • the source extension 52 is all located above the gate 1 and overlaps the gate 1.
  • the pixel electrode 9 of the pixel unit controlled by the clock signal that is turned on at last also includes a pixel electrode extension 92, which is opposite
  • the independent part of the pixel electrode body 91 may also be an extended part extending from the pixel electrode body 91.
  • the pixel electrode extension 92 is all located above the gate 1 and overlaps the gate 1.
  • the other features except for the source electrode 5 and the pixel electrode 9 are the same as those of the first embodiment and the second embodiment, and will not be repeated here.
  • the source extension and the pixel electrode extension are formed, and the source connected to the pixel electrode is enlarged.
  • the differential design of the coupling capacitor Cgp in the pixel achieves the effect of making the total feedback voltage received by each pixel electrode consistent.
  • the liquid crystal display device and the pixel compensation method of the embodiment of the present invention are designed to differentiate the coupling capacitor Cgp between the pixel electrode and the gate in the pixel unit, especially the coupling capacitor Cgp of the pixel unit controlled by the last signal to be turned on. Properly increase so that the difference in the feedback voltage of the common gate Gn they receive can offset the difference in the feedback voltage caused by different clock signals CK, so that the total feedback voltage they receive is equal, and color shift, flicker, horizontal and vertical Display defects such as stripes.

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Abstract

A pixel compensation method and a liquid crystal display apparatus. According to the method, under the control of a plurality of clock signals, a source signal output by a source electrode driver is transmitted, in a time-sharing manner, to data lines of a plurality of pixel units, wherein each of the pixel units corresponds to one clock signal; and the coupling capacitance between a pixel electrode (9) and a gate electrode (1) of each of the plurality of pixel units is differentially designed, such that the total feedthrough on each pixel electrode (9) is the same, wherein the coupling capacitance of a pixel controlled by the clock signal turned on last is greater than the coupling capacitance of pixels controlled by the other clock signals. The coupling capacitance of the pixel units is differentially constructed, such that the total feedthrough on the pixel units is equal. Therefore, the poor display problems of color cast, flicker and transverse and vertical stripes can be avoided.

Description

像素补偿方法及液晶显示装置Pixel compensation method and liquid crystal display device 技术领域Technical field
本发明属于液晶显示的技术领域，尤其涉及一种像素补偿方法及液晶显示装置。The invention belongs to the technical field of liquid crystal display, and in particular relates to a pixel compensation method and a liquid crystal display device.
背景技术Background technique
多路分用电路技术(DeMUX)广泛应用于液晶显示面板，它可以将源极驱动器输出的扫描信号S以1:m，如1:2、1:3等的形式分时传送给n列像素的数据线D，以1:2为例，通过两个时钟信号CK1、CK2控制两组TFT从而将一根源极驱动器输出的扫描信号S分时输出给两列像素的数据线D，使源极驱动器输出的数据线可以至少减少一半，也可以使源极驱动器的数量减少，从而能够减少面板设计的成本，减小面板的下边框宽度，使面板达到更窄边框的高规格要求。DeMUX technology (DeMUX) is widely used in liquid crystal display panels. It can transmit the scan signal S output by the source driver to n columns of pixels in the form of 1:m, such as 1:2, 1:3, etc. Take 1:2 as an example. The two sets of TFTs are controlled by two clock signals CK1 and CK2 so that the scan signal S output by a source driver is output to the data line D of two columns of pixels in a time-sharing manner, so that the source The data lines output by the driver can be reduced by at least half, and the number of source drivers can also be reduced, thereby reducing the cost of panel design, reducing the width of the lower frame of the panel, and enabling the panel to meet the high specification requirements of a narrower frame.
由于采用多路分用电路技术，扫描信号S分时传送给数据线D需要用薄膜晶体管TFT做开关，并且还要引入控制TFT开关的时钟信号CK。由于时钟信号CK关闭会通过耦合电容Ckd影响数据线的电位进而影响充电像素的电位，不同的时钟信号CK由于关闭时刻不一致对像素的反馈电压的影响也不一致。对于例如背沟道型的TFT来说，如图1所示，面板包括栅极01、绝缘层02、半导体层03、源极04以及漏极05，TFT器件的栅极01和源极04、栅极01和漏极05都会有一个交叠面积，会存在寄生电容Cgs和Cgd。如图2所示，由于该寄生电容的存在，在多路分用电路部分，时钟信号CK的信号线和数据线D之间会有一个较大的耦合电容Ckd。由于该耦合电容Ckd的存在，在数据线电位达到预定值，时钟信号CK控制TFT关断，数据线电位受时钟信号CK电位跳变和耦合电容的影响也会出现一定跳变，该跳变可看做是时钟信号CK关闭带来的对数据线电位的回馈电压(Feedthrough)。先充电的像素由于栅极仍然打开，像素电极会向受时钟信号的回馈电压影响的数据线漏电，从而间接也会被时钟信号关闭带来的回馈电压影响。最后开启的像素可能不会受时钟信号回馈电压的影响，只受栅极Gn的回馈电压影响，这样造成不同像素受到的回馈电压不同，在显示上会出现色偏、横竖条纹、闪烁等显示不良问题。Due to the use of the demultiplexing circuit technology, the scanning signal S is transmitted to the data line D in a time-sharing manner. It is necessary to use a thin film transistor TFT as a switch, and also to introduce a clock signal CK to control the TFT switch. Since the clock signal CK is turned off, it will affect the potential of the data line and thus the potential of the charged pixel through the coupling capacitor Ckd, and different clock signals CK have different effects on the feedback voltage of the pixel due to the inconsistent turn-off time. For, for example, a back channel type TFT, as shown in FIG. 1, the panel includes a gate electrode 01, an insulating layer 02, a semiconductor layer 03, a source electrode 04 and a drain electrode 05, and the gate electrode 01 and source electrode 04 of the TFT device. Both the gate 01 and the drain 05 have an overlapping area, and there will be parasitic capacitances Cgs and Cgd. As shown in FIG. 2, due to the existence of the parasitic capacitance, in the demultiplexing circuit part, there will be a relatively large coupling capacitance Ckd between the signal line of the clock signal CK and the data line D. Due to the existence of the coupling capacitor Ckd, when the data line potential reaches a predetermined value, the clock signal CK controls the TFT to turn off. The data line potential will also undergo a certain jump due to the potential jump of the clock signal CK and the coupling capacitor. It can be regarded as the feedback voltage (Feedthrough) of the data line potential caused by the turning off of the clock signal CK. Since the gate of the first charged pixel is still open, the pixel electrode will leak to the data line affected by the feedback voltage of the clock signal, which is indirectly affected by the feedback voltage caused by the clock signal being turned off. The last turned-on pixel may not be affected by the feedback voltage of the clock signal, but only the feedback voltage of the gate Gn. This will cause different pixels to receive different feedback voltages, resulting in poor display such as color shift, horizontal and vertical stripes, and flicker on the display. problem.
针对上述问题，一种方案可以通过在多路分用电路上用额外的与时钟信号CK相反的反向时钟信号CK’的信号线和数据线进行交叠形成交叠补偿电容，从而对数据线的电 位进行补偿，避免时钟信号CK跳变影响像素电极电位。然而，这种补偿方法额外增加补偿电路进行补偿，不可避免的会额外占用面板的设计空间，并且额外增加信号会使面板的整个功耗增大。In view of the above problems, a solution can form an overlap compensation capacitor by overlapping the signal line and the data line of the extra inverted clock signal CK' opposite to the clock signal CK on the demultiplexing circuit, thereby forming an overlap compensation capacitor. The potential of the pixel electrode is compensated to prevent the transition of the clock signal CK from affecting the pixel electrode potential. However, this compensation method additionally adds a compensation circuit for compensation, which will inevitably occupy additional design space of the panel, and the additional signal will increase the overall power consumption of the panel.
发明内容Summary of the invention
为解决现有技术中存在的上述问题，本发明提供一种像素补偿方法及液晶显示装置，针对像素内的像素电极和栅极之间的耦合电容Cgp进行差异化设计，特别是把由最后打开的一路信号控制的像素的耦合电容Cgp进行适当的加大，从而避免出现色偏、闪烁、横竖条纹等显示不良。In order to solve the above-mentioned problems in the prior art, the present invention provides a pixel compensation method and a liquid crystal display device, which are designed for the differential design of the coupling capacitance Cgp between the pixel electrode and the gate in the pixel, in particular, the The coupling capacitor Cgp of the pixel controlled by the first signal is appropriately increased to avoid poor display such as color shift, flicker, horizontal and vertical stripes.
第一方面，本发明提出一种像素补偿方法，用于采用多路分用电路的液晶显示装置，所述像素补偿方法包括：In the first aspect, the present invention provides a pixel compensation method for a liquid crystal display device using a demultiplexing circuit, and the pixel compensation method includes:
在多个时钟信号的控制下，源极驱动器输出的源信号被分时传送给多个像素单元对应连接的数据线，每个像素单元对应一路时钟信号，差异化设计多个所述像素单元中的每个像素单元的像素电极和栅极之间的耦合电容，使各像素单元的像素电极受到的总回馈电压相同，所述总回馈电压包括时钟信号对像素单元产生的回馈电压和栅极扫描信号对像素单元产生的回馈电压；Under the control of multiple clock signals, the source signal output by the source driver is time-shared and transmitted to the data lines corresponding to the multiple pixel units. Each pixel unit corresponds to a clock signal. Differential design of the multiple pixel units The coupling capacitance between the pixel electrode and the gate of each pixel unit makes the total feedback voltage received by the pixel electrode of each pixel unit the same. The total feedback voltage includes the feedback voltage generated by the clock signal to the pixel unit and the gate scan The feedback voltage generated by the signal to the pixel unit;
其中，最后打开的一路时钟信号控制的像素单元的像素电极和栅极之间之间的耦合电容大于其它路时钟信号控制的像素单元的像素电极和栅极之间之间的耦合电容。Wherein, the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the clock signal that is turned on last is larger than the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the other clock signals.
在优选的实施方式中，所述各像素单元的像素电极受到的总回馈电压满足以下关系式：In a preferred embodiment, the total feedback voltage received by the pixel electrode of each pixel unit satisfies the following relationship:
Cgp/Cp*△VG+Ckd/Cd*△VCK＝Cgp’/Cp*△VG+Ckd/Cd*△VCK’；Cgp/Cp*△VG+Ckd/Cd*△VCK=Cgp’/Cp*△VG+Ckd/Cd*△VCK’;
其中，Cgp为其它路时钟信号控制的像素单元的像素电极和栅极之间之间的耦合电容，Cgp’为最后打开的一路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容，△VCK为其它路时钟信号对其控制的像素影响的等效高低电位差，△VCK’为最后打开的一路时钟信号对其控制的像素影响的等效高低电位差，Cp为像素电极电位和其他电位之间形成的总电容，Cd为数据线电位和面板其他电位之间形成的总电容，△VG为栅极的电压差，m>1。Among them, Cgp is the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by other clock signals, and Cgp' is the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the last clock signal. , △VCK is the equivalent high and low potential difference of the pixels controlled by other clock signals, △VCK' is the equivalent high and low potential difference of the pixels controlled by the last clock signal, Cp is the pixel electrode potential and The total capacitance formed between other potentials, Cd is the total capacitance formed between the potential of the data line and other potentials of the panel, △VG is the voltage difference of the gate, m>1.
在优选的实施方式中，最后打开的一路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容与其它路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容满足以下关系式：In a preferred embodiment, the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the clock signal and the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the other clock signals satisfy the following Relationship:
Cgp’＝(1+x)*CgpCgp’=(1+x)*Cgp
其中，x>0。Among them, x>0.
第二方面，本发明提出一种液晶显示装置，采用前述实施方式所述的像素补偿方法，所述液晶显示装置的每个像素单元包括：In a second aspect, the present invention provides a liquid crystal display device, which adopts the pixel compensation method described in the foregoing embodiments, and each pixel unit of the liquid crystal display device includes:
栅极；Grid
位于所述栅极上的第一绝缘层；A first insulating layer on the gate;
位于所述第一绝缘层上的半导体层；A semiconductor layer located on the first insulating layer;
位于所述半导体层上的漏极和源极，所述源极包括源极本体，所述源极本体与栅极之间部分交叠；A drain and a source located on the semiconductor layer, the source includes a source body, and the source body and the gate partially overlap;
位于所述漏极和源极上的第二绝缘层，所述第二绝缘层上设有第一孔；A second insulating layer located on the drain and source, the second insulating layer is provided with a first hole;
位于所述第二绝缘层上的公共电极，所述公共电极上设有公共电极孔；A common electrode located on the second insulating layer, the common electrode is provided with a common electrode hole;
位于所述公共电极上的第三绝缘层，所述第三绝缘层上设有第二孔；A third insulating layer located on the common electrode, the third insulating layer is provided with a second hole;
位于所述第三绝缘层上的所述像素电极，所述像素电极与源极电性连接；The pixel electrode located on the third insulating layer, the pixel electrode is electrically connected to the source;
其中，最后打开的一路时钟信号控制的像素单元的源极还包括源极延长部，所述源极延长部位于所述栅极上方，且所述源极延长部与栅极之间全部交叠。Wherein, the source of the pixel unit controlled by the last clock signal further includes a source extension, the source extension is located above the gate, and the source extension and the gate all overlap .
在优选的实施方式中，所述第一孔和第二孔组合形成绝缘层孔，所述像素电极通过所述绝缘层孔与所述源极电性连接。In a preferred embodiment, the first hole and the second hole are combined to form an insulating layer hole, and the pixel electrode is electrically connected to the source electrode through the insulating layer hole.
在优选的实施方式中，所述公共电极孔的孔径大于所述绝缘层孔的孔径，所述第三绝缘层覆盖所述公共电极孔的侧面。In a preferred embodiment, the hole diameter of the common electrode hole is larger than the hole diameter of the insulating layer hole, and the third insulating layer covers the side surface of the common electrode hole.
在优选的实施方式中，每个像素单元的像素电极包括像素电极本体；最后打开的一路时钟信号控制的像素单元的像素电极还包括像素电极延长部，所述像素电极延长部与栅极之间全部交叠。In a preferred embodiment, the pixel electrode of each pixel unit includes a pixel electrode body; the pixel electrode of the pixel unit controlled by a clock signal that is turned on last also includes a pixel electrode extension part between the pixel electrode extension part and the gate. All overlap.
第三方面，本发明还提出一种液晶显示装置，采用前述实施方式所述的像素补偿方法，所述液晶显示装置的每个像素单元包括：In a third aspect, the present invention also provides a liquid crystal display device, which adopts the pixel compensation method described in the foregoing embodiments, and each pixel unit of the liquid crystal display device includes:
栅极；Grid
位于所述栅极上的第一绝缘层；A first insulating layer on the gate;
位于所述第一绝缘层上的半导体层；A semiconductor layer located on the first insulating layer;
位于所述半导体层上的漏极和源极；Drain and source located on the semiconductor layer;
位于所述漏极和源极上的第二绝缘层，所述第二绝缘层上设有第一孔；A second insulating layer located on the drain and source, the second insulating layer is provided with a first hole;
位于所述第二绝缘层上的公共电极，所述公共电极上设有公共电极孔；A common electrode located on the second insulating layer, the common electrode is provided with a common electrode hole;
位于所述公共电极上的第三绝缘层，所述第三绝缘层上设有第二孔；A third insulating layer located on the common electrode, the third insulating layer is provided with a second hole;
位于所述第三绝缘层上的像素电极，所述像素电极与源极电性连接，所述像素电极包括像素电极本体；A pixel electrode located on the third insulating layer, the pixel electrode is electrically connected to a source electrode, and the pixel electrode includes a pixel electrode body;
其中，最后打开的一路时钟信号控制的像素单元的像素电极还包括像素电极延长部，所述像素电极延长部与栅极之间全部交叠。Wherein, the pixel electrode of the pixel unit controlled by a clock signal last turned on further includes a pixel electrode extension, and the pixel electrode extension and the gate are all overlapped.
在优选的实施方式中，所述像素电极延长部容纳在所述公共电极孔中。In a preferred embodiment, the pixel electrode extension is received in the common electrode hole.
第四方面，本发明还提出一种液晶显示装置，包括：In a fourth aspect, the present invention also provides a liquid crystal display device, including:
多路分用电路，用于在多个时钟信号的控制下，将源极驱动器输出至每一条第一数据线的源信号分时传送给多个像素单元对应连接的第二数据线；A demultiplexing circuit for transmitting the source signal output by the source driver to each first data line to the second data line corresponding to the multiple pixel units under the control of multiple clock signals;
其中，最后打开的一路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容大于其它路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容，使各像素单元的像素电极受到的总回馈电压相同，所述总回馈电压包括时钟信号对像素单元产生的回馈电压和栅极扫描信号对像素单元产生的回馈电压。Among them, the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the clock signal is greater than the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the other clock signals, so that the pixels of each pixel unit The total feedback voltage received by the electrodes is the same, and the total feedback voltage includes the feedback voltage generated by the clock signal to the pixel unit and the feedback voltage generated by the gate scan signal to the pixel unit.
在优选的实施方式中，最后打开的一路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容与其它路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容满足以下关系式：In a preferred embodiment, the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the clock signal and the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the other clock signals satisfy the following Relationship:
Cgp’＝(1+x)*CgpCgp’=(1+x)*Cgp
其中，Cgp’为最后打开的一路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容，Cgp为其它路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容，x>0。Among them, Cgp' is the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the last clock signal, Cgp is the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by other clock signals, x >0.
在优选的实施方式中，所述最后打开的一路时钟信号控制的像素单元的源极包括源极本体和源极延长部，所述源极本体与所述栅极之间部分交叠，所述源极延长部与所述栅极之间全部交叠。In a preferred embodiment, the source of the pixel unit controlled by a clock signal that is turned on last includes a source body and a source extension, and the source body and the gate partially overlap each other. All overlap between the source extension and the gate.
在优选的实施方式中，所述最后打开的一路时钟信号控制的像素单元的像素电极包括像素电极本体和像素电极延长部，所述像素电极本体与所述栅极之间部分交叠，所述像素电极延长部与所述栅极之间全部交叠。In a preferred embodiment, the pixel electrode of the pixel unit controlled by a clock signal that is turned on last includes a pixel electrode body and a pixel electrode extension. The pixel electrode body and the gate partially overlap each other. The pixel electrode extension part and the gate are all overlapped.
与现有技术相比，本发明实施例能够使共同栅极Gn的回馈电压差异抵消不同时钟信号CK带来的回馈电压的差异，从而使像素电极的总回馈电压相等，进而避免出现色偏、闪烁、横竖条纹等显示不良。Compared with the prior art, the embodiment of the present invention can make the difference in the feedback voltage of the common gate Gn offset the difference in the feedback voltage caused by different clock signals CK, so that the total feedback voltage of the pixel electrode is equal, thereby avoiding color shift, Flickering, horizontal and vertical stripes, etc. display poorly.
附图说明Description of the drawings
下面将以明确易懂的方式，结合附图说明优选实施方式，对本发明予以进一步说明。Hereinafter, in a clear and easy-to-understand manner, preferred embodiments are described in conjunction with the accompanying drawings to further illustrate the present invention.
图1为现有背沟道型TFT的结构示意图；FIG. 1 is a schematic diagram of the structure of an existing back-channel type TFT;
图2为现有多路分用电路Mux的寄生电容示意图；Figure 2 is a schematic diagram of the parasitic capacitance of the existing demultiplexing circuit Mux;
图3为本发明实施例的Mux 1:2的液晶显示装置的电路示意图；3 is a schematic circuit diagram of a Mux 1:2 liquid crystal display device according to an embodiment of the present invention;
图4为本发明实施例的液晶显示装置在Mux 1:2,x＝0时的两个像素充电示意图；4 is a schematic diagram of charging two pixels of the liquid crystal display device according to an embodiment of the present invention when Mux 1:2, x=0;
图5为本发明实施例的液晶显示装置在Mux 1:2,x＝0.4时的两个像素充电示意图；5 is a schematic diagram of charging two pixels of the liquid crystal display device according to an embodiment of the present invention when Mux 1:2 and x=0.4;
图6为本发明实施例的液晶显示装置中像素单元的第一实施方式的结构示意图；6 is a schematic structural diagram of a first embodiment of a pixel unit in a liquid crystal display device according to an embodiment of the present invention;
图7为本发明实施例的液晶显示装置中像素单元的第一实施方式的A-A’截面结构示意图；7 is a schematic diagram of the A-A' cross-sectional structure of the first embodiment of the pixel unit in the liquid crystal display device of the embodiment of the present invention;
图8为本发明实施例的液晶显示装置中像素单元的第二实施方式的结构示意图；8 is a schematic structural diagram of a second embodiment of a pixel unit in a liquid crystal display device according to an embodiment of the present invention;
图9为本发明实施例的液晶显示装置中像素单元的第二实施方式的B-B’截面结构示意图。9 is a schematic diagram of a B-B' cross-sectional structure of a second embodiment of a pixel unit in a liquid crystal display device according to an embodiment of the present invention.
具体实施方式Detailed ways
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对照附图说明本发明的具体实施方式。显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，并获得其他的实施方式。In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the specific embodiments of the present invention will be described below with reference to the drawings. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative work, other drawings can be obtained based on these drawings and obtained Other embodiments.
为使图面简洁，各图中只示意性地表示出了与本发明相关的部分，它们并不代表其作为产品的实际结构。另外，以使图面简洁便于理解，在有些图中具有相同结构或功能的部件，仅示意性地绘示了其中的一个，或仅标出了其中的一个。在本文中，“一个”不仅表示“仅此一个”，也可以表示“多于一个”的情形。In order to make the drawings concise, the figures only schematically show the parts related to the present invention, and they do not represent the actual structure of the product. In addition, in order to make the drawings concise and easy to understand, in some drawings, only one of the components with the same structure or function is schematically shown, or only one of them is marked. In this article, "a" not only means "only this one", but can also mean "more than one".
本发明的像素补偿方法用于液晶显示装置，包括：The pixel compensation method of the present invention is applied to a liquid crystal display device and includes:
源极驱动器(Source IC)输出的源信号以1:m的形式分时传送给m列像素的数据线，每个像素对应一路时钟信号，差异化设计每个像素内的耦合电容，使各像素电极受到的总回馈电压一致，总回馈电压包括时钟信号对像素产生的回馈电压和栅极扫描信号对像素产生的回馈电压。其中，最后打开的一路时钟信号控制的像素的栅极电位和像素电极电位之间的耦合电容大于其余m-1个像素的栅极电位和像素电极电位之间的耦合电容，m>1。The source signal output by the source driver (Source IC) is transmitted to the data line of m columns of pixels in a time-sharing format of 1:m. Each pixel corresponds to a clock signal. The coupling capacitor in each pixel is designed differently to make each pixel The total feedback voltage received by the electrodes is the same. The total feedback voltage includes the feedback voltage generated by the clock signal to the pixel and the feedback voltage generated by the gate scanning signal to the pixel. Wherein, the coupling capacitance between the gate potential of the pixel controlled by the last clock signal and the pixel electrode potential is larger than the coupling capacitance between the gate potential and the pixel electrode potential of the remaining m-1 pixels, m>1.
具体地，多路分用电路的大部分像素电极电位会受到时钟信号CK关闭和栅极信号 G关闭带来的回馈电压影响，并且每个像素的总回馈电压是这两者之和，Specifically, most of the pixel electrode potential of the demultiplexing circuit will be affected by the feedback voltage brought by the clock signal CK off and the gate signal G off, and the total feedback voltage of each pixel is the sum of the two,
即Vf＝VfG+VfCKThat is, Vf=VfG+VfCK
由于VfG＝Cgp/Cp*△VGSince VfG=Cgp/Cp*△VG
VfCK＝Ckd/Cd*△VCKVfCK＝Ckd/Cd*△VCK
因此Vf＝Cgp/Cp*△VG+Ckd/Cd*△VCKTherefore Vf=Cgp/Cp*△VG+Ckd/Cd*△VCK
其中，Vf为总回馈电压，VfG为栅极的回馈电压，VfCK为时钟信号的回馈电压，Cgp为栅极电位和像素电极电位之间的耦合电容，Cp为像素电极电位和其他电位之间形成的总电容，△VG为栅极的电压差，Ckd为数据线和时钟信号之间的耦合电容，Cd为数据线电位和面板其他电位之间形成的总电容，△VCK为时钟信号对其控制的像素影响的等效高低电位差。Among them, Vf is the total feedback voltage, VfG is the feedback voltage of the gate, VfCK is the feedback voltage of the clock signal, Cgp is the coupling capacitance between the gate potential and the pixel electrode potential, and Cp is the formation between the pixel electrode potential and other potentials △VG is the voltage difference of the gate, Ckd is the coupling capacitance between the data line and the clock signal, Cd is the total capacitance formed between the data line potential and other potentials of the panel, △VCK is the clock signal to control it The equivalent high and low potential difference affected by the pixel.
由于m个不同像素的总回馈电压要相一致，因此Since the total feedback voltage of m different pixels must be consistent,
Vf1＝Vf2＝……＝Vfm-1＝Vfm，其中m>1Vf1=Vf2=……=Vfm-1=Vfm, where m>1
由于除了各个像素寄生电容Cgpm不一定相等之外，各个像素电极电位的总电容Cpm、各个时钟信号CKm与数据线之间的耦合电容Ckdm、各个数据线电位的总电容Cdm、各个时钟信号电位差△VCKm也并不一定相等，公式展开即Since the parasitic capacitance Cgpm of each pixel is not necessarily equal, the total capacitance Cpm of each pixel electrode potential, the coupling capacitance Ckdm between each clock signal CKm and the data line, the total capacitance Cdm of each data line potential, and the potential difference of each clock signal △VCKm is not necessarily equal, the formula expands
Cgp1/Cp1*△VG+Ckd1/Cd1*△VCK1＝Cgp2/Cp2*△VG+Ckd2/Cd2*△VCK2＝……＝Cgp(m-1)/Cp(m-1)*△VG+Ckd(m-1)/Cd(m-1)*△VCK(m-1)＝Cgpm/Cpm*△VG+Ckdm/Cdm*△VCKmCgp1/Cp1*△VG+Ckd1/Cd1*△VCK1=Cgp2/Cp2*△VG+Ckd2/Cd2*△VCK2=……=Cgp(m-1)/Cp(m-1)*△VG+Ckd( m-1)/Cd(m-1)*△VCK(m-1)=Cgpm/Cpm*△VG+Ckdm/Cdm*△VCKm
先打开的m-1路时钟信号控制的像素的像素电极受到的总回馈电压与最后打开的时钟信号控制的像素的像素电极受到的总回馈电压相同，每个像素受到的时钟信号和栅极扫描信号的回馈电压之和相同，则为了使上述等式成立，本发明采用的方法是，最后打开的一路时钟信号CKm控制的像素的Cgp’与其他时钟信号控制的像素Cgp不同，其他像素电极总电容Cp、数据线总电容Cd、各个时钟信号CK与数据线之间的耦合电容Ckd等参数都相同，因此公式简化为：The total feedback voltage received by the pixel electrode of the pixel controlled by the first m-1 clock signal is the same as the total feedback voltage received by the pixel electrode of the pixel controlled by the last clock signal. Each pixel receives the clock signal and gate scan If the sum of the feedback voltages of the signals is the same, in order to make the above equation hold, the method adopted in the present invention is that the Cgp' of the pixel controlled by the clock signal CKm is different from the Cgp of the pixel controlled by other clock signals. The capacitance Cp, the total capacitance of the data line Cd, the coupling capacitance Ckd between each clock signal CK and the data line are all the same, so the formula is simplified to:
Cgp/Cp*△VG+Ckd/Cd*△VCK＝Cgp’/Cp*△VG+Ckd/Cd*△VCK’Cgp/Cp*△VG+Ckd/Cd*△VCK=Cgp’/Cp*△VG+Ckd/Cd*△VCK’
等式左边项是先打开的m-1路时钟信号控制的像素的像素电极受到的总回馈电压，等式右边项是最后打开的一路时钟信号CKm控制的像素的像素电极受到的总回馈电压；Cgp为先打开的m-1路时钟信号控制的像素的栅极电位和像素电极电位之间的耦合电容，Cgp’为最后打开的时钟信号控制的像素的栅极电位和像素电极电位之间的耦合电容，△VCK为先打开的m-1路的时钟信号对其控制的像素影响的等效高低电位差，△VCK’为 最后打开的时钟信号对其控制的像素影响的等效高低电位差。The left term of the equation is the total feedback voltage received by the pixel electrode of the pixel controlled by the first m-1 clock signal, and the right term of the equation is the total feedback voltage received by the pixel electrode of the pixel controlled by the last clock signal CKm; Cgp is the coupling capacitance between the gate potential and the pixel electrode potential of the pixel controlled by the m-1 clock signal that is turned on first, and Cgp' is the coupling capacitance between the gate potential and the pixel electrode potential of the pixel controlled by the last turned on clock signal Coupling capacitor, △VCK is the equivalent high and low potential difference of the pixels controlled by the m-1 channel clock signal that is turned on first, △VCK' is the equivalent high and low potential difference of the pixels controlled by the last turned on clock signal .
进一步地，由于实际应用中△VCK’≤△VCK，甚至在一些时序下，△VCK’＝0。因此，为了使上述等式成立，则需要增大最后打开的一路时钟信号CKm控制的像素的栅极电位和像素电极电位之间的耦合电容Cgp’，使它的电容变为(1+x)*Cgp，即Cgp’＝(1+x)*Cgp，其中x由具体的电容电压参数以及前述的公式可以大致确定，具体可通过电路仿真精确确定，且x≥0。Furthermore, since △VCK'≤△VCK in practical applications, even under some timings, △VCK'=0. Therefore, in order to make the above equation hold, it is necessary to increase the coupling capacitance Cgp' between the gate potential of the pixel controlled by the last clock signal CKm and the pixel electrode potential, so that its capacitance becomes (1+x) *Cgp, that is, Cgp'=(1+x)*Cgp, where x can be roughly determined by specific capacitor voltage parameters and the aforementioned formula, which can be accurately determined by circuit simulation, and x≥0.
图3为本发明实施例的Mux 1:2的液晶显示装置的结构示意图。如图3所示，本发明实施例的液晶显示装置采用多路分用电路，所述多路分用电路在一组时钟信号的控制下，将源极驱动器输出至每一条第一数据线的源信号以1:m的形式分时传送给m个像素对应的第二数据线。图3中仅示意性地呈现了1:2多路分用电路(m＝2)的实施方式。FIG. 3 is a schematic structural diagram of a Mux 1:2 liquid crystal display device according to an embodiment of the present invention. As shown in FIG. 3, the liquid crystal display device of the embodiment of the present invention adopts a demultiplexing circuit, and the demultiplexing circuit outputs the source driver to each first data line under the control of a set of clock signals. The source signal is transmitted to the second data line corresponding to the m pixels in a time-sharing format of 1:m. FIG. 3 only schematically presents the implementation of the 1:2 demultiplexing circuit (m=2).
其中，所述一组时钟信号中不同时钟信号分别控制m个像素中对应的一个像素；最后打开的一路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容大于其余m-1个时钟信号控制的像素单元的像素电极和栅极之间的耦合电容，m为大于1的整数。Wherein, different clock signals in the set of clock signals respectively control a corresponding pixel in the m pixels; the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the last clock signal is larger than the remaining m-1 For the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the clock signal, m is an integer greater than 1.
图4和图5分别为x＝0和x＝0.4时以1:2多路分用电路为例的两个像素单元的充电示意图。如图4所示，在x＝0时，最后一路时钟信号CKm控制的像素单元的Cgp’与其它像素的Cgp相同，从两个像素单元充同一个电压的像素充电曲线可以看到，最终的充电电位有差异，两个像素单元总的回馈电压也有差异。如图5所示，在x＝0.4时，即最后打开的一路时钟信号CKm控制的像素单元的Cgp’大于其它像素单元的Cgp，从两个像素单元充同一个电压的像素充电曲线可以看出，通过加大最后一路时钟信号控制的像素的Cgp’，两个像素单元最终的充电电位的差异已经很小。在x＝0.7时，即最后打开的一路时钟信号CKm控制的像素的Cgp’大于其他像素的Cgp，通过加大最后一路时钟信号控制的像素单元的Cgp’，两个像素单元最终的充电电位相同，两个像素单元总的回馈电压也相同，从而可以通过统一的公共电极电压Vcom的补偿补回到统一的最高电压。4 and 5 are schematic diagrams of charging two pixel units when x=0 and x=0.4, taking a 1:2 demultiplexing circuit as an example. As shown in Figure 4, when x=0, the Cgp' of the pixel unit controlled by the last clock signal CKm is the same as the Cgp of other pixels. From the pixel charging curve of the two pixel units charging the same voltage, it can be seen that the final The charging potential is different, and the total feedback voltage of the two pixel units is also different. As shown in Figure 5, when x=0.4, the Cgp' of the pixel unit controlled by the last clock signal CKm is greater than the Cgp of other pixel units. It can be seen from the pixel charging curve of the two pixel units charging the same voltage By increasing the Cgp' of the pixel controlled by the last clock signal, the difference in the final charging potential of the two pixel units is already very small. When x=0.7, that is, the Cgp' of the pixel controlled by the last clock signal CKm is greater than the Cgp of other pixels. By increasing the Cgp' of the pixel unit controlled by the last clock signal, the final charging potential of the two pixel units is the same , The total feedback voltage of the two pixel units is also the same, so that the uniform common electrode voltage Vcom can be compensated to return to the uniform highest voltage.
本发明的上述像素补偿方法不针对任何的像素结构，增大栅极电位和显示电极电位之间的耦合电容Cgp的方法也不仅仅局限于增大交叠面积，根据电容计算公式C＝ε*S/d，可知有很多种增大Cgp的方案，下面以具体实施例介绍三种方案，这三种方法只是多种为了加大交叠面积S方案中的几种，并不是穷举，需要说明的是，任何有助于增大栅极电位和显示电极电位之间的耦合电容Cgp方式都可以作为本发明液晶显示装置。The above-mentioned pixel compensation method of the present invention is not directed to any pixel structure, and the method of increasing the coupling capacitance Cgp between the gate potential and the display electrode potential is not limited to increasing the overlap area. According to the capacitance calculation formula C=ε* S/d, it can be seen that there are many schemes for increasing Cgp. The following specific examples introduce three schemes. These three methods are just a few of the various S schemes for increasing the overlap area. It is not an exhaustive list. It is explained that any method that helps increase the coupling capacitance Cgp between the gate potential and the display electrode potential can be used as the liquid crystal display device of the present invention.
下面以具体实施例详细介绍本发明的液晶显示装置中像素单元的技术方案。The technical solution of the pixel unit in the liquid crystal display device of the present invention will be described in detail below with specific embodiments.
图6和图7分别为本发明实施例的液晶显示装置中像素单元的第一实施方式的结构 示意图和A-A’截面结构示意图。如图6和7所示，本实施例的液晶显示装置采用了上述的像素补偿方法并采用多路分用电路，液晶显示装置的每个像素均具有如下结构：基板(图未示)，基板可以但不限于玻璃基板，形成于基板之上的栅极1，栅极1的材料可以为单一金属或复合金属，位于栅极1所在层之上的第一绝缘层2，第一绝缘层2可以包括采用SiOx和/或SiNx的膜层；位于第一绝缘层2上的半导体层3，半导体层3可以包括IGZO等金属氧化物半导体层；位于半导体层3上的漏极4和源极5，漏极4和源极5为一层或多层金属层结构；位于源极4和漏极5所在层上的第二绝缘层6，在第二绝缘层6上设有第一孔61，第二绝缘层6的材料可以包括SiOx、SiNx或二者的组合；位于第二绝缘层6上的公共电极7，在公共电极7上设有公共电极孔71；位于公共电极7所在层上的第三绝缘层8，在第三绝缘层8上设有第二孔81，第三绝缘层8可以是有机绝缘层；位于第三绝缘层8上的像素电极9，像素电极9与源极5电性连接。数据线(图中未示出)连接漏极4并提供信号。6 and 7 are respectively a schematic structural diagram and a schematic cross-sectional structure diagram of A-A' of the first embodiment of the pixel unit in the liquid crystal display device of the embodiment of the present invention. As shown in Figures 6 and 7, the liquid crystal display device of this embodiment adopts the above-mentioned pixel compensation method and adopts a demultiplexing circuit. Each pixel of the liquid crystal display device has the following structure: a substrate (not shown), a substrate It can be but not limited to a glass substrate. The gate 1 is formed on the substrate. The material of the gate 1 can be a single metal or a composite metal. The first insulating layer 2 and the first insulating layer 2 are located on the layer where the gate 1 is located. It may include a film layer using SiOx and/or SiNx; a semiconductor layer 3 on the first insulating layer 2, and the semiconductor layer 3 may include a metal oxide semiconductor layer such as IGZO; a drain electrode 4 and a source electrode 5 on the semiconductor layer 3 , The drain 4 and the source 5 are one or more metal layer structures; the second insulating layer 6 located on the layer where the source 4 and the drain 5 are located, the second insulating layer 6 is provided with a first hole 61, The material of the second insulating layer 6 may include SiOx, SiNx or a combination of the two; the common electrode 7 located on the second insulating layer 6 has a common electrode hole 71 on the common electrode 7; the common electrode 7 located on the layer where the common electrode 7 is located The third insulating layer 8 is provided with a second hole 81 on the third insulating layer 8. The third insulating layer 8 may be an organic insulating layer; the pixel electrode 9 located on the third insulating layer 8, the pixel electrode 9 and the source electrode 5 Electrical connection. The data line (not shown in the figure) is connected to the drain 4 and provides a signal.
如图7所示，每路时钟信号控制的像素单元的源极5包括源极本体51，源极本体51位于第一绝缘层2上，源极本体51的一部分与栅极1形成交叠，其余部分与栅极1不形成交叠。As shown in FIG. 7, the source 5 of each pixel unit controlled by a clock signal includes a source body 51, which is located on the first insulating layer 2, and a part of the source body 51 overlaps the gate 1. The remaining part does not overlap with the gate 1.
其中，最后打开的一路时钟信号控制的像素单元的源极5还包括源极延长部52。如图7所示，源极延长部52可以是从源极本体51延伸出的延长部分，是源极本体51的一部分。在可选的实施方式中，源极延长部52也可以是相对源极本体51的独立部分。源极延长部52全部位于栅极1的上方，源极延长部52全部与栅极1形成交叠，因此增大了与像素电极连接的源极和栅极之间的交叠面积，从而增大了栅极电位和像素电极电位之间的耦合电容Cgp。Wherein, the source 5 of the pixel unit controlled by the last clock signal that is turned on further includes a source extension 52. As shown in FIG. 7, the source extension portion 52 may be an extension portion extending from the source body 51 and is a part of the source body 51. In an alternative embodiment, the source extension 52 may also be an independent part relative to the source body 51. The source extension 52 is all located above the gate 1, and the source extension 52 overlaps the gate 1, thus increasing the overlap area between the source and the gate connected to the pixel electrode, thereby increasing The coupling capacitance Cgp between the gate potential and the pixel electrode potential is increased.
如图7所示，第一孔61、第二孔81以及公共电极孔71为共心设置，第一孔61、第二孔81和公共电极孔71均为方形孔。在可选的实施方式中，第一孔61、第二孔81和公共电极孔71也可以包括圆形孔等其它规则形状的开口。第一孔61和第二孔81组合形成绝缘层孔，像素电极9通过第一孔61和第二孔81形成的绝缘层孔与源极5接触并且电性连接。As shown in FIG. 7, the first hole 61, the second hole 81 and the common electrode hole 71 are arranged concentrically, and the first hole 61, the second hole 81 and the common electrode hole 71 are all square holes. In an alternative embodiment, the first hole 61, the second hole 81 and the common electrode hole 71 may also include other regular-shaped openings such as circular holes. The first hole 61 and the second hole 81 are combined to form an insulating layer hole, and the pixel electrode 9 is in contact with and electrically connected to the source electrode 5 through the insulating layer hole formed by the first hole 61 and the second hole 81.
在可选的实施方式中，如图7所示，公共电极孔71的孔径大于第一孔61和第二孔81形成的绝缘层孔的孔径。像素电极9与公共电极7之间不接触，第三绝缘层8设置在像素电极9与公共电极7之间，并且第三绝缘层8覆盖公共电极孔71开口的侧面。In an alternative embodiment, as shown in FIG. 7, the hole diameter of the common electrode hole 71 is larger than the hole diameter of the insulating layer formed by the first hole 61 and the second hole 81. There is no contact between the pixel electrode 9 and the common electrode 7, the third insulating layer 8 is disposed between the pixel electrode 9 and the common electrode 7, and the third insulating layer 8 covers the side surface of the opening of the common electrode hole 71.
本实施例中，通过延伸了最后打开的一路时钟信号控制的像素单元的源极的形状， 形成了源极延伸部，增大了与像素电极连接的源极和栅极之间的交叠面积，从而增大耦合电容Cgp，在不需要增加任何额外的补偿信号和补偿电路的前提下，差异化的设计像素内的耦合电容Cgp，达到使各像素电极受到的总回馈电压一致的效果。In this embodiment, by extending the shape of the source electrode of the pixel unit controlled by a clock signal that is turned on last, a source electrode extension is formed, which increases the overlap area between the source electrode and the gate electrode connected to the pixel electrode , Thereby increasing the coupling capacitor Cgp, and without adding any additional compensation signal and compensation circuit, the differential design of the coupling capacitor Cgp in the pixel achieves the effect of making the total feedback voltage received by each pixel electrode consistent.
图8和图9分别为本发明实施例的液晶显示装置中像素单元的第二实施方式的结构示意图和B-B’截面结构示意图。如图8和图9所示，本实施例的液晶显示装置采用了上述的像素补偿方法并采用多路分用电路，液晶显示装置的每个像素均具有如下结构：基板(图未示)，基板可以但不限于玻璃基板，形成于基板之上的栅极1，栅极1的材料可以为单一金属或复合金属，位于栅极1所在层之上的第一绝缘层2，第一绝缘层2可以包括采用SiOx和/或SiNx的膜层，位于第一绝缘层2上的半导体层3，半导体层3可以包括IGZO等金属氧化物半导体层，位于半导体层3上的漏极4和源极5，漏极4和源极5为一层或多层金属层结构，位于源极4和漏极5所在层上的第二绝缘层6，在第二绝缘层6上设有第一孔61，第二绝缘层6的材料可以是SiOx、SiNx或二者的组合；位于第二绝缘层6上的公共电极7，在公共电极7上设有公共电极孔71；位于公共电极7所在层上的第三绝缘层8，在第三绝缘层8上设有第二孔81，第三绝缘层8可以是有机绝缘层，位于第三绝缘层8上的像素电极9，像素电极9与源极5电性连接。数据线(图中未示出)连接漏极4并提供信号。8 and 9 are respectively a schematic structural diagram and a B-B' cross-sectional structural schematic diagram of a second embodiment of a pixel unit in a liquid crystal display device of an embodiment of the present invention. As shown in Figures 8 and 9, the liquid crystal display device of this embodiment adopts the above-mentioned pixel compensation method and adopts a demultiplexing circuit. Each pixel of the liquid crystal display device has the following structure: a substrate (not shown), The substrate can be, but not limited to, a glass substrate. The gate 1 is formed on the substrate. The material of the gate 1 can be a single metal or a composite metal. The first insulating layer 2 on the layer where the gate 1 is located, the first insulating layer 2 may include a film layer using SiOx and/or SiNx, a semiconductor layer 3 located on the first insulating layer 2, the semiconductor layer 3 may include a metal oxide semiconductor layer such as IGZO, a drain 4 and a source located on the semiconductor layer 3 5. The drain electrode 4 and the source electrode 5 are of one or more metal layer structures. The second insulating layer 6 is located on the layer where the source electrode 4 and the drain electrode 5 are located. The second insulating layer 6 is provided with a first hole 61 , The material of the second insulating layer 6 can be SiOx, SiNx or a combination of the two; the common electrode 7 on the second insulating layer 6 has a common electrode hole 71 on the common electrode 7; on the layer where the common electrode 7 is located The third insulating layer 8 is provided with a second hole 81 on the third insulating layer 8. The third insulating layer 8 can be an organic insulating layer, the pixel electrode 9 located on the third insulating layer 8, the pixel electrode 9 and the source 5 Electrical connection. The data line (not shown in the figure) is connected to the drain 4 and provides a signal.
第一孔61、第二孔81以及公共电极孔71均为同心设置，第一孔61、第二孔81和公共电极孔71可以是方形孔或圆形孔等其他规则形状的开口，优选地，如图9所示，第一孔61、第二孔81和公共电极孔71均为方形孔。其中，第一孔61和第二孔81组合形成绝缘层孔，像素电极9通过第一孔61和第二孔81形成的绝缘层孔与源极5接触并且电性连接。The first hole 61, the second hole 81 and the common electrode hole 71 are all arranged concentrically. The first hole 61, the second hole 81 and the common electrode hole 71 may be square holes or circular holes and other regular-shaped openings, preferably As shown in FIG. 9, the first hole 61, the second hole 81 and the common electrode hole 71 are all square holes. Wherein, the first hole 61 and the second hole 81 are combined to form an insulating layer hole, and the pixel electrode 9 is in contact with and electrically connected to the source electrode 5 through the insulating layer hole formed by the first hole 61 and the second hole 81.
公共电极孔71的孔径大于第一孔61和第二孔81形成的绝缘层孔的孔径。像素电极9与公共电极7之间不接触，第三绝缘层8设置在像素电极9与公共电极7之间，并且第三绝缘层8覆盖公共电极孔71开口的侧面。The hole diameter of the common electrode hole 71 is larger than the hole diameter of the insulating layer formed by the first hole 61 and the second hole 81. There is no contact between the pixel electrode 9 and the common electrode 7, the third insulating layer 8 is disposed between the pixel electrode 9 and the common electrode 7, and the third insulating layer 8 covers the side surface of the opening of the common electrode hole 71.
每路时钟信号控制的像素单元的像素电极9包括像素电极本体91，像素电极本体91位于第三绝缘层8上，像素电极本体91的一部分与栅极1形成交叠，其余部分与栅极1不形成交叠。The pixel electrode 9 of the pixel unit controlled by each clock signal includes a pixel electrode body 91, which is located on the third insulating layer 8. A part of the pixel electrode body 91 overlaps the gate electrode 1, and the remaining part overlaps the gate electrode 1. Does not form overlap.
其中，最后打开的一路时钟信号控制的像素的像素电极9还包括像素电极延长部92。如图8所示，像素电极延长部92是相对于像素电极本体91的独立部分，并且像素电极延长部92的面积小于像素电极本体91。在可选的实施方式中，像素电极延长部92还可 以是从像素电极本体91延伸出的延长部分。本实施例中，最后打开的一路时钟信号控制的像素单元的源极5不包括源极延长部。Among them, the pixel electrode 9 of the pixel controlled by a clock signal that is turned on last also includes a pixel electrode extension 92. As shown in FIG. 8, the pixel electrode extension 92 is an independent part relative to the pixel electrode body 91, and the area of the pixel electrode extension 92 is smaller than that of the pixel electrode body 91. In an alternative embodiment, the pixel electrode extension 92 can also be an extension extending from the pixel electrode body 91. In this embodiment, the source 5 of the pixel unit controlled by the last clock signal does not include the source extension.
如图8所示，像素电极延长部92容纳在公共电极孔71中，公共电极孔71的开口大于现有的公共电极孔，像素电极延长部92与公共电极7之间不接触，像素电极延长部92位于第三绝缘层8上，且像素电极延长部92与公共电极7之间也有第三绝缘层8。As shown in FIG. 8, the pixel electrode extension 92 is accommodated in the common electrode hole 71. The opening of the common electrode hole 71 is larger than the existing common electrode hole. There is no contact between the pixel electrode extension 92 and the common electrode 7, and the pixel electrode is extended. The portion 92 is located on the third insulating layer 8, and there is also a third insulating layer 8 between the pixel electrode extension 92 and the common electrode 7.
如图9所示，像素电极延长部92全部位于栅极1的上方，像素电极延长部92下方依次是第三绝缘层8、第二绝缘层6、第一绝缘层2和栅极1，像素电极延长部92全部与栅极1形成交叠，因此增大了与源极连接的像素电极和栅极之间的交叠面积，从而增大了栅极电位和像素电极电位之间的耦合电容Cgp。As shown in FIG. 9, the pixel electrode extension 92 is all located above the gate 1. Below the pixel electrode extension 92 are the third insulating layer 8, the second insulating layer 6, the first insulating layer 2, and the gate 1. The electrode extension 92 completely overlaps the gate electrode 1, thereby increasing the overlapping area between the pixel electrode connected to the source and the gate electrode, thereby increasing the coupling capacitance between the gate electrode potential and the pixel electrode potential Cgp.
在可选的实施方式中，在像素电极延长部92下方的第三绝缘层8上也可以设置有第二孔(图中未示出)，使像素电极延长部92位于第二孔中，从而像素电极延长部92下方依次是第二绝缘层6、第一绝缘层2和栅极1，第三绝缘层8设置在像素电极延长部92与公共电极7之间。In an alternative embodiment, a second hole (not shown in the figure) may also be provided on the third insulating layer 8 under the pixel electrode extension 92, so that the pixel electrode extension 92 is located in the second hole, thereby Below the pixel electrode extension 92 are the second insulating layer 6, the first insulating layer 2 and the gate 1 in this order, and the third insulating layer 8 is provided between the pixel electrode extension 92 and the common electrode 7.
本实施例中，通过延伸了最后打开的一路时钟信号控制的像素单元的像素电极的形状，形成了像素电极延伸部，增大了与源极连接的像素电极和栅极之间的交叠面积，从而增大耦合电容Cgp，在不需要增加任何额外的补偿信号和补偿电路的前提下，差异化的设计像素内的耦合电容Cgp，达到使各像素电极受到的总回馈电压一致的效果。In this embodiment, the shape of the pixel electrode of the pixel unit controlled by the last clock signal is extended to form a pixel electrode extension, which increases the overlap area between the pixel electrode and the gate connected to the source. , Thereby increasing the coupling capacitor Cgp, and without adding any additional compensation signal and compensation circuit, the differential design of the coupling capacitor Cgp in the pixel achieves the effect of making the total feedback voltage received by each pixel electrode consistent.
在可选的实施方式中，上述像素单元的第一实施方式和第二实施方式还可以组合实施，即每个时钟信号控制的像素单元的源极5包括源极本体51，源极本体51位于第一绝缘层2上，源极本体51的一部分与栅极1形成交叠，其余部分与栅极1不形成交叠；每路时钟信号控制的像素单元的像素电极9包括像素电极本体91，像素电极本体91位于第三绝缘层8上，像素电极本体91的一部分与栅极1形成交叠，其余部分与栅极1不形成交叠。In an alternative embodiment, the first and second embodiments of the above-mentioned pixel unit can also be implemented in combination, that is, the source 5 of each pixel unit controlled by a clock signal includes a source body 51, which is located at On the first insulating layer 2, a part of the source body 51 overlaps with the gate 1, and the remaining part does not overlap with the gate 1. The pixel electrode 9 of each pixel unit controlled by a clock signal includes a pixel electrode body 91, The pixel electrode body 91 is located on the third insulating layer 8, a part of the pixel electrode body 91 overlaps the gate 1, and the remaining part does not overlap the gate 1.
其中，最后打开的一路时钟信号控制的像素单元的源极5还包括源极延长部52，源极延长部52可以是从源极本体51延伸出的延长部分，也可以是相对源极本体51的独立部分。源极延长部52全部位于栅极1的上方，与栅极1形成交叠；最后打开的一路时钟信号控制的像素单元的像素电极9还包括像素电极延长部92，像素电极延长部92是相对于像素电极本体91的独立部分，也可以是从像素电极本体91延伸出的延长部分。像素电极延长部92全部位于栅极1的上方，与栅极1形成交叠。Wherein, the source 5 of the pixel unit controlled by the last clock signal further includes a source extension 52. The source extension 52 may be an extension extending from the source body 51, or may be opposite to the source body 51. The independent part of. The source extension 52 is all located above the gate 1 and overlaps the gate 1. The pixel electrode 9 of the pixel unit controlled by the clock signal that is turned on at last also includes a pixel electrode extension 92, which is opposite The independent part of the pixel electrode body 91 may also be an extended part extending from the pixel electrode body 91. The pixel electrode extension 92 is all located above the gate 1 and overlaps the gate 1.
本实施例中除源极5和像素电极9以外的其它特征与前述第一实施方式和第二实施 方式相同，在此不再赘述。In this embodiment, the other features except for the source electrode 5 and the pixel electrode 9 are the same as those of the first embodiment and the second embodiment, and will not be repeated here.
本实施例中，通过延伸了最后打开的一路时钟信号控制的像素单元的源极以及像素电极的形状，形成了源极延伸部和像素电极延伸部，同时增大了与像素电极连接的源极和栅极之间的交叠面积以及与源极连接的像素电极和栅极之间的交叠面积，从而增大耦合电容Cgp，在不需要增加任何额外的补偿信号和补偿电路的前提下，差异化的设计像素内的耦合电容Cgp，达到使各像素电极受到的总回馈电压一致的效果。In this embodiment, by extending the source of the pixel unit controlled by the last clock signal and the shape of the pixel electrode, the source extension and the pixel electrode extension are formed, and the source connected to the pixel electrode is enlarged. The overlap area with the gate and the overlap area between the pixel electrode connected to the source and the gate, thereby increasing the coupling capacitance Cgp, without adding any additional compensation signals and compensation circuits, The differential design of the coupling capacitor Cgp in the pixel achieves the effect of making the total feedback voltage received by each pixel electrode consistent.
本发明实施例的液晶显示装置及像素补偿方法针对像素单元内的像素电极和栅极之间的耦合电容Cgp进行差异化设计，特别是把由最后打开的一路信号控制的像素单元的耦合电容Cgp进行适当地加大，使它们受到的共同栅极Gn的反馈电压差异能够抵消不同时钟信号CK带来的回馈电压差异，从而使它们受到的总回馈电压相等，可避免出现色偏、闪烁、横竖条纹等显示不良问题。The liquid crystal display device and the pixel compensation method of the embodiment of the present invention are designed to differentiate the coupling capacitor Cgp between the pixel electrode and the gate in the pixel unit, especially the coupling capacitor Cgp of the pixel unit controlled by the last signal to be turned on. Properly increase so that the difference in the feedback voltage of the common gate Gn they receive can offset the difference in the feedback voltage caused by different clock signals CK, so that the total feedback voltage they receive is equal, and color shift, flicker, horizontal and vertical Display defects such as stripes.
应当说明的是，上述实施例均可根据需要自由组合。以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。It should be noted that the above embodiments can be freely combined as required. The above are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications are also It should be regarded as the protection scope of the present invention.

Claims (13)

  1. 一种像素补偿方法，用于采用多路分用电路的液晶显示装置，其特征在于，所述像素补偿方法包括：A pixel compensation method for a liquid crystal display device using a demultiplexing circuit, characterized in that the pixel compensation method includes:
    在多个时钟信号的控制下，源极驱动器输出的源信号被分时传送给多个像素单元对应连接的数据线，每个像素单元对应一路时钟信号，差异化设计多个所述像素单元中的每个像素单元的像素电极和栅极之间的耦合电容，使各像素单元的像素电极受到的总回馈电压相同，所述总回馈电压包括时钟信号对像素单元产生的回馈电压和栅极扫描信号对像素单元产生的回馈电压；Under the control of multiple clock signals, the source signal output by the source driver is time-shared and transmitted to the data lines corresponding to the multiple pixel units. Each pixel unit corresponds to a clock signal. Differential design of the multiple pixel units The coupling capacitance between the pixel electrode and the gate of each pixel unit makes the total feedback voltage received by the pixel electrode of each pixel unit the same. The total feedback voltage includes the feedback voltage generated by the clock signal to the pixel unit and the gate scan The feedback voltage generated by the signal to the pixel unit;
    其中，最后打开的一路时钟信号控制的像素单元的像素电极和栅极之间之间的耦合电容大于其它路时钟信号控制的像素单元的像素电极和栅极之间之间的耦合电容。Wherein, the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the clock signal that is turned on last is larger than the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the other clock signals.
  2. 根据权利要求1所述的像素补偿方法，其特征在于，各所述像素单元的像素电极受到的总回馈电压满足以下关系式：The pixel compensation method according to claim 1, wherein the total feedback voltage received by the pixel electrode of each pixel unit satisfies the following relationship:
    Cgp/Cp*△VG+Ckd/Cd*△VCK＝Cgp’/Cp*△VG+Ckd/Cd*△VCK’；Cgp/Cp*△VG+Ckd/Cd*△VCK=Cgp’/Cp*△VG+Ckd/Cd*△VCK’;
    其中，Cgp为其它路时钟信号控制的像素单元的像素电极和栅极之间之间的耦合电容，Cgp’为最后打开的一路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容，△VCK为其它路时钟信号对其控制的像素影响的等效高低电位差，△VCK’为最后打开的一路时钟信号对其控制的像素影响的等效高低电位差，Cp为像素电极电位和其他电位之间形成的总电容，Cd为数据线电位和面板其他电位之间形成的总电容，△VG为栅极的电压差。Among them, Cgp is the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by other clock signals, and Cgp' is the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the last clock signal. , △VCK is the equivalent high and low potential difference of the pixels controlled by other clock signals, △VCK' is the equivalent high and low potential difference of the pixels controlled by the last clock signal, Cp is the pixel electrode potential and The total capacitance formed between other potentials, Cd is the total capacitance formed between the data line potential and other potentials of the panel, and ΔVG is the voltage difference of the gate.
  3. 根据权利要求2所述的像素补偿方法，其特征在于，最后打开的一路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容与其它路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容满足以下关系式：The pixel compensation method according to claim 2, wherein the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the clock signal and the pixel electrode and gate of the pixel unit controlled by the other clock signal The coupling capacitance between the poles satisfies the following relationship:
    Cgp’＝(1+x)*CgpCgp’=(1+x)*Cgp
    其中，x>0。Among them, x>0.
  4. 一种液晶显示装置，采用权利要求1-3任一项所述的像素补偿方法，其特征在于，所述液晶显示装置的每个像素单元包括：A liquid crystal display device using the pixel compensation method according to any one of claims 1 to 3, wherein each pixel unit of the liquid crystal display device includes:
    栅极；Grid
    位于所述栅极上的第一绝缘层；A first insulating layer on the gate;
    位于所述第一绝缘层上的半导体层；A semiconductor layer located on the first insulating layer;
    位于所述半导体层上的漏极和源极，所述源极包括源极本体，所述源极本体与栅极 之间部分交叠；A drain and a source located on the semiconductor layer, the source includes a source body, and the source body and the gate partially overlap;
    位于所述漏极和源极上的第二绝缘层，所述第二绝缘层上设有第一孔；A second insulating layer located on the drain and source, the second insulating layer is provided with a first hole;
    位于所述第二绝缘层上的公共电极，所述公共电极上设有公共电极孔；A common electrode located on the second insulating layer, the common electrode is provided with a common electrode hole;
    位于所述公共电极上的第三绝缘层，所述第三绝缘层上设有第二孔；A third insulating layer located on the common electrode, the third insulating layer is provided with a second hole;
    位于所述第三绝缘层上的所述像素电极，所述像素电极与源极电性连接；The pixel electrode located on the third insulating layer, the pixel electrode is electrically connected to the source;
    其中，最后打开的一路时钟信号控制的像素单元的源极还包括源极延长部，所述源极延长部位于所述栅极上方，且所述源极延长部与栅极之间全部交叠。Wherein, the source of the pixel unit controlled by the last clock signal further includes a source extension, the source extension is located above the gate, and the source extension and the gate all overlap .
  5. 根据权利要求4所述的液晶显示装置，其特征在于，所述第一孔和第二孔组合形成绝缘层孔，所述像素电极通过所述绝缘层孔与所述源极电性连接。4. The liquid crystal display device of claim 4, wherein the first hole and the second hole are combined to form an insulating layer hole, and the pixel electrode is electrically connected to the source electrode through the insulating layer hole.
  6. 根据权利要求5所述的液晶显示装置，其特征在于，所述公共电极孔的孔径大于所述绝缘层孔的孔径，所述第三绝缘层覆盖所述公共电极孔的侧面。7. The liquid crystal display device according to claim 5, wherein the aperture of the common electrode hole is larger than the aperture of the insulating layer hole, and the third insulating layer covers the side surface of the common electrode hole.
  7. 根据权利要求4所述的液晶显示装置，其特征在于，每个像素单元的像素电极包括像素电极本体；最后打开的一路时钟信号控制的像素单元的像素电极还包括像素电极延长部，所述像素电极延长部与栅极之间全部交叠。The liquid crystal display device according to claim 4, wherein the pixel electrode of each pixel unit includes a pixel electrode body; the pixel electrode of the pixel unit controlled by a clock signal that is turned on last also includes a pixel electrode extension, and The electrode extension and the gate are all overlapped.
  8. 一种液晶显示装置，采用权利要求1-3任一项所述的像素补偿方法，其特征在于，所述液晶显示装置的每个像素单元包括：A liquid crystal display device using the pixel compensation method according to any one of claims 1 to 3, wherein each pixel unit of the liquid crystal display device includes:
    栅极；Grid
    位于所述栅极上的第一绝缘层；A first insulating layer on the gate;
    位于所述第一绝缘层上的半导体层；A semiconductor layer located on the first insulating layer;
    位于所述半导体层上的漏极和源极；Drain and source located on the semiconductor layer;
    位于所述漏极和源极上的第二绝缘层，所述第二绝缘层上设有第一孔；A second insulating layer located on the drain and source, the second insulating layer is provided with a first hole;
    位于所述第二绝缘层上的公共电极，所述公共电极上设有公共电极孔；A common electrode located on the second insulating layer, the common electrode is provided with a common electrode hole;
    位于所述公共电极上的第三绝缘层，所述第三绝缘层上设有第二孔；A third insulating layer located on the common electrode, the third insulating layer is provided with a second hole;
    位于所述第三绝缘层上的像素电极，所述像素电极与源极电性连接，所述像素电极包括像素电极本体；A pixel electrode located on the third insulating layer, the pixel electrode is electrically connected to a source electrode, and the pixel electrode includes a pixel electrode body;
    其中，最后打开的一路时钟信号控制的像素单元的像素电极还包括像素电极延长部，所述像素电极延长部与栅极之间全部交叠。Wherein, the pixel electrode of the pixel unit controlled by a clock signal last turned on further includes a pixel electrode extension, and the pixel electrode extension and the gate are all overlapped.
  9. 根据权利要求8所述的液晶显示装置，其特征在于，所述像素电极延长部容纳在所述公共电极孔中。8. The liquid crystal display device according to claim 8, wherein the pixel electrode extension is received in the common electrode hole.
  10. 一种液晶显示装置，其特征在于，包括：A liquid crystal display device, characterized in that it comprises:
    多路分用电路，用于在多个时钟信号的控制下，将源极驱动器输出至每一条第一数据线的源信号分时传送给多个像素单元对应连接的第二数据线；A demultiplexing circuit for transmitting the source signal output by the source driver to each first data line to the second data line corresponding to the multiple pixel units under the control of multiple clock signals;
    其中，最后打开的一路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容大于其它路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容，使各像素单元的像素电极受到的总回馈电压相同，所述总回馈电压包括时钟信号对像素单元产生的回馈电压和栅极扫描信号对像素单元产生的回馈电压。Among them, the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the clock signal is greater than the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the other clock signals, so that the pixels of each pixel unit The total feedback voltage received by the electrodes is the same, and the total feedback voltage includes the feedback voltage generated by the clock signal to the pixel unit and the feedback voltage generated by the gate scan signal to the pixel unit.
  11. 根据权利要求10所述的液晶显示装置，其特征在于，最后打开的一路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容与其它路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容满足以下关系式：The liquid crystal display device according to claim 10, wherein the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the clock signal and the pixel electrode and gate of the pixel unit controlled by the other clock signal The coupling capacitance between the poles satisfies the following relationship:
    Cgp’＝(1+x)*CgpCgp’=(1+x)*Cgp
    其中，Cgp’为最后打开的一路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容，Cgp为其它路时钟信号控制的像素单元的像素电极和栅极之间的耦合电容，x>0。Among them, Cgp' is the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by the last clock signal, Cgp is the coupling capacitance between the pixel electrode and the gate of the pixel unit controlled by other clock signals, x >0.
  12. 根据权利要求11所述的液晶显示装置，其特征在于，所述最后打开的一路时钟信号控制的像素单元的源极包括源极本体和源极延长部，所述源极本体与所述栅极之间部分交叠，所述源极延长部与所述栅极之间全部交叠。11. The liquid crystal display device according to claim 11, wherein the source of the pixel unit controlled by the last clock signal comprises a source body and a source extension, the source body and the gate Part of the overlap between the two, the source extension and the gate all overlap.
  13. 根据权利要求11或12所述的液晶显示装置，其特征在于，所述最后打开的一路时钟信号控制的像素单元的像素电极包括像素电极本体和像素电极延长部，所述像素电极本体与所述栅极之间部分交叠，所述像素电极延长部与所述栅极之间全部交叠。The liquid crystal display device according to claim 11 or 12, wherein the pixel electrode of the pixel unit controlled by a clock signal that is turned on last includes a pixel electrode body and a pixel electrode extension, and the pixel electrode body is connected to the pixel electrode. The gates partially overlap, and the pixel electrode extensions and the gates completely overlap.
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