WO2020220407A1 - 显示器驱动装置 - Google Patents

显示器驱动装置 Download PDF

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Publication number
WO2020220407A1
WO2020220407A1 PCT/CN2019/087596 CN2019087596W WO2020220407A1 WO 2020220407 A1 WO2020220407 A1 WO 2020220407A1 CN 2019087596 W CN2019087596 W CN 2019087596W WO 2020220407 A1 WO2020220407 A1 WO 2020220407A1
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WO
WIPO (PCT)
Prior art keywords
timing
adjustment
data multiplexer
blank
sequence
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PCT/CN2019/087596
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English (en)
French (fr)
Inventor
薛景峰
田勇
郑力华
Original Assignee
武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/607,103 priority Critical patent/US20220148487A1/en
Publication of WO2020220407A1 publication Critical patent/WO2020220407A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream

Definitions

  • the present disclosure relates to the field of display technology, in particular to display driving devices.
  • the current monitor frequency is generally 60HZ, that is, the screen of the monitor is refreshed 60 times per second, so that the image seen by the human eye is dynamic and smooth.
  • the display frequency of the display for example, from 60HZ to 30HZ.
  • the frequency of the display needs to be increased, for example: from 60HZ to 90HZ or 120HZ to make the picture smoother. Therefore, in order to be suitable for different scenes, the display needs to change the display frequency, that is, dynamic frame rate display.
  • the charging time of the panel does not change, but simply extends the blank time in the sequence.
  • this method increases the blank time in the timing sequence during low-frequency display, resulting in increased leakage of the display, which is likely to cause the display to appear flickering or crosstalk, which seriously affects the display quality of the display.
  • FIG. 1 and FIG. 2 respectively show the driving timing diagram of the display driving device in the prior art and the pixel circuit diagram in the prior art.
  • the gate, data multiplexer, and source are all turned off.
  • the potential of point S connected to the data line is the voltage on the source when the last data multiplexer is turned off. Since this voltage is uncertain, the Vds voltage difference in the pixel circuit is uncertain. In other words, when the gate is turned off and the Vds voltage difference is large, the leakage current of the pixel circuit will also increase.
  • the present disclosure proposes a display driving method, which can reduce the leakage time of the display, thereby improving the flicker and crosstalk phenomenon of the display.
  • the present disclosure provides a display driving device.
  • the display driving device includes a driving module configured to periodically output driving timing, wherein the driving timing includes execution timing and blank time period timing, and an adjustment module configured to be connected to the driving module.
  • the group outputs an adjustment timing to the driving module in the timing range of the timing of each blank period.
  • the display driving device includes a first data multiplexer configured to output a first multiplexing drive timing, and the first multiplexing drive timing includes a first execution timing and The first blank sequence.
  • the second data multiplexer is configured to output a second multiplex drive timing, and the second multiplex drive timing includes a second execution timing and a second blank timing.
  • the third data multiplexer is configured to output a third multiplexing drive timing, and the third multiplexing drive timing includes a third execution timing and a third blank timing.
  • the first execution timing, the second execution timing, and the third execution timing are output within the timing range of the execution timing, and the first blank timing, the second blank timing, and the third blank timing are different in the blank time period. Timing range output.
  • the driving module further includes a plurality of driving gates, and when the driving module outputs the blank period timing, the plurality of driving gates are turned off.
  • the driving module further includes a plurality of driving gates, and when the driving module outputs the blank time period timing, the driving gates are in a low potential state.
  • the adjustment module includes: a first data multiplexer adjustment unit connected to the first data multiplexer, and the first data multiplexer adjustment unit
  • the first data multiplexer is used to output the first adjustment timing.
  • the second data multiplexer adjustment unit is connected to the second data multiplexer, and the second data multiplexer adjustment unit is used to output a second adjustment timing to the second data multiplexer.
  • the third data multiplexer adjustment unit is connected to the third data multiplexer, and the third data multiplexer adjustment unit is used for outputting a third adjustment timing to the third data multiplexer.
  • the adjustment timing includes the first adjustment timing, the second adjustment timing, and the third adjustment timing.
  • the first adjustment timing is inserted into the first blank timing.
  • the second adjustment sequence is inserted into the second blank sequence, and the third adjustment sequence is inserted into the third blank sequence.
  • the adjustment timing is continuous with the previous execution timing.
  • the adjustment timing is not continuous with the execution timing.
  • the adjustment timing occupies a timing of the blank period.
  • the adjustment module is further configured to be connected to a source voltage adjustment device, the source voltage adjustment device outputs a source voltage adjustment signal, and the adjustment module is based on the source The voltage adjustment signal adjusts the adjustment source voltage of the adjustment sequence.
  • the adjusted source voltage is configured to be the same as the intermediate value voltage of the driving sequence.
  • the first adjustment timing is not continuous with the first execution timing
  • the second adjustment timing is not continuous with the second execution timing
  • the third adjustment timing is not continuous with the The third execution sequence is continuous.
  • the first adjustment timing is continuous with the first execution timing
  • the second adjustment timing is continuous with the second execution timing
  • the third adjustment timing is continuous with the first execution timing.
  • Three execution sequence is continuous.
  • the first adjustment timing occupies the first blank timing
  • the second adjustment timing occupies the second blank timing
  • the third adjustment timing occupies the second blank timing .
  • the present disclosure also provides a display driving device.
  • the display driving device includes a driving module configured to periodically output driving timing, wherein the driving timing includes execution timing and blank time period timing, and an adjustment module configured to be connected to the driving module.
  • the group outputs an adjustment timing to the driving module in the timing range of each blank period timing, and the adjustment timing is continuous with the previous execution timing.
  • the adjustment module is also configured to be connected to a source voltage adjustment device, the source voltage adjustment device is configured to output a source voltage adjustment signal, and the adjustment module adjusts the adjustment according to the source voltage adjustment signal Timing adjustment of source voltage.
  • the present disclosure further provides a display driving device.
  • the display driving device includes a driving module configured to periodically output driving timing, wherein the driving timing includes execution timing and blank time period timing, and an adjustment module configured to be connected to the driving module.
  • the group outputs an adjustment timing to the drive module in the timing range of the timing of each blank period, and the adjustment timing is not continuous with the execution timing.
  • the adjustment module is also configured to be connected to a source voltage adjustment device, the source voltage adjustment device is configured to output a source voltage adjustment signal, and the adjustment module adjusts the adjustment according to the source voltage adjustment signal Timing adjustment of source voltage.
  • the display drive device includes a drive module configured to periodically output drive timing, wherein each cycle of the drive timing includes execution timing and blanking respectively Time period sequence, and an adjustment module configured to be connected to the drive module, the adjustment module outputs an adjustment sequence to the drive module within the time sequence range of the blank period time sequence, by adjusting the timing sequence Reduce the leakage of the display driving device, thereby improving flicker and crosstalk.
  • FIG. 1 shows a schematic diagram of a driving sequence of a display driving device in the prior art.
  • FIG. 2 shows a schematic diagram of a pixel circuit in the prior art.
  • FIG. 3 shows a block diagram of a display driving device according to an embodiment of the present disclosure.
  • FIG. 4 shows a schematic diagram of a driving sequence of a display driving device according to an embodiment of the present disclosure.
  • FIG. 5 shows a schematic diagram of a driving sequence of a display driving device according to an embodiment of the present disclosure.
  • FIG. 6 shows a schematic diagram of a driving sequence of a display driving device according to an embodiment of the present disclosure.
  • FIG. 3 is a block diagram showing a display driving device according to an embodiment of the present disclosure.
  • the present disclosure provides a display driving device 10.
  • the display driving device 10 includes a driving module 100 configured to output a driving timing 101, wherein the driving timing includes an execution timing and a blank period timing, and an adjustment module 200 configured to be connected to the driving module 100.
  • the adjustment module 200 outputs to the driving module 100 an adjustment sequence 201 inserted into the blank period sequence.
  • the driving sequence 101 can be composed of the driving sequence of a plurality of data multiplexers, and the number of the components is determined according to the applicable image complexity and environmental requirements.
  • the following further describes other implementations of the present disclosure in the case of three data multiplexers. example.
  • the first data multiplexer MUXR can be a data multiplexer that outputs a red signal
  • the second data multiplexer MUXG can be a data multiplexer that outputs a green signal
  • the third data multiplexer MUXB can be a data multiplexer that outputs green and blue signals.
  • the display driving device includes a first data multiplexer MUXR configured to output a first multiplexed driving timing, the first A multiplex driving sequence includes a first execution sequence distributed in the execution sequence and a first blank sequence distributed in the blank period sequence.
  • the second data multiplexer MUXB is configured to output a second multiplexing drive timing, the second multiplexing drive timing includes a second execution timing distributed in the execution timing and a second blanking distribution in the blank period timing Timing.
  • the third data multiplexer MUXB is configured to output a third multiplex drive timing, the third multiplex drive timing includes a third execution timing distributed in the execution timing and a third blank distributed in the blank period timing Timing.
  • the first execution timing, the second execution timing, and the third execution timing are output within the timing range of the execution timing, and the first blank timing, the second blank timing, and the third blank timing are different in the blank time period. Timing range output.
  • the driving module further includes a plurality of driving gates.
  • the plurality of driving gates includes a first gate Gate1, which is configured to output the first gate timing.
  • the second gate Gate2 is configured to output the second gate timing.
  • the third gate Gate3 is configured to output the third gate timing.
  • N the number of drive gates, it can be set to N but not limited to 3.
  • the figure also shows the Nth gate Gate( n), is configured to output the Nth gate timing.
  • the plurality of driving gates include the first gate 1, the second gate 2, the third gate Gate3 to the second gate N gate Gate(n) is closed or in a low potential state.
  • the adjustment module includes: a first data multiplexer adjustment unit connected to the first data multiplexer, and the first data multiplexer adjustment unit
  • the first data multiplexer is used to output the first adjustment timing.
  • the second data multiplexer adjustment unit is connected to the second data multiplexer, and the second data multiplexer adjustment unit is used to output a second adjustment timing to the second data multiplexer.
  • the third data multiplexer adjustment unit is connected to the third data multiplexer, and the third data multiplexer adjustment unit is used for outputting a third adjustment timing to the third data multiplexer.
  • the adjustment timing includes the first adjustment timing, the second adjustment timing, and the third adjustment timing.
  • the first adjustment timing is inserted into the first blank timing.
  • the second adjustment sequence is inserted into the second blank sequence, and the third adjustment sequence is inserted into the third blank sequence.
  • FIG. 4 shows a schematic diagram of the driving sequence after receiving the adjusted timing of the display driving device according to an embodiment of the present disclosure. As shown in the figure, it respectively exposes the first gate 1, the second gate, and the second gate.
  • the driving timing F1 of the three gates Gate3 to the Nth gate Gate(n), the first data multiplexer MUXR, the second data multiplexer MUXG, the third data multiplexer MUXB, and the source Source in this embodiment A timing diagram of the blank period timing B1 and the adjustment timing T1.
  • the adjustment timing T1 is not continuous with the execution timing W1. Furthermore, as shown in the figure, the time range of the adjustment timing T1 includes: the first adjustment timing of the first data multiplexer MUXR, the second adjustment timing of the second data multiplexer MUXG, and the third data multiplexer The third adjustment timing of MUXB.
  • the first adjustment timing of the first data multiplexer MUXR is not continuous with the first execution timing
  • the second adjustment timing of the second data multiplexer MUXG is not continuous with the second execution timing
  • the third adjustment timing is not continuous with the third execution timing.
  • the first gate 1, the second gate 2, and the third gate 3 to the Nth gate Gate(n) show steady signals.
  • the first gate 1, the second gate 2 and the third gate 3 to the Nth gate Gate(n) are in a low potential state or closed status.
  • FIG. 5 shows a schematic diagram of the driving sequence of the display driving device according to an embodiment of the present disclosure. As shown in the figure, it respectively exposes the first gate1, the second gate2, the third gate3 to the third gate N gate Gate(n), the first data multiplexer MUXR, the second data multiplexer MUXG, the third data multiplexer MUXB and the source source in this embodiment drive timing F2, blank period timing B2, and Adjust the timing diagram of timing T2.
  • the adjustment timing T2 is continuous with the previous execution timing W2. Furthermore, the time range of the adjustment timing T2 includes the first adjustment timing of the first data multiplexer MUXR, the second adjustment timing of the second data multiplexer MUXG, and the third adjustment of the third data multiplexer MUXB. Timing; in other words, the first adjustment timing of the first data multiplexer MUXR is continuous with the first execution timing, the second adjustment timing of the second data multiplexer MUXG is continuous with the second execution timing, and the third data multiplexer MUXB The third adjustment timing sequence is continuous with the third execution timing. By adding the adjustment timing sequence, the Vds voltage difference in the pixel circuit is reduced, thereby reducing the leakage current of the pixel circuit.
  • FIG. 6 shows a schematic diagram of the driving sequence of the display driving device according to an embodiment of the present disclosure. As shown in the figure, it respectively exposes the first gate1, the second gate2, the third gate3 to the third gate N gate Gate(n), the first data multiplexer MUXR, the second data multiplexer MUXG, the third data multiplexer MUXB and the source source in this embodiment drive timing F3, blank period timing B3 and Adjust the timing diagram of timing T3.
  • the adjustment timing T3 occupies the blank period timing B3, in other words, the adjustment timing T3 is the same as the blank period timing B3, and is continuous with the previous execution timing W3.
  • the time range of the adjustment timing T3 includes: the first adjustment timing of the first data multiplexer MUXR, the second adjustment timing of the second data multiplexer MUXG, and the third adjustment of the third data multiplexer MUXB Timing; in other words, the first adjustment timing of the first data multiplexer MUXR occupies the first blank timing, the second adjustment timing of the second data multiplexer MUXG occupies the second blank timing, the third data multiplexer MUXB The adjustment timing occupies the third blank timing.
  • the Vds voltage difference in the pixel circuit is reduced, thereby reducing the leakage current of the pixel circuit.
  • the adjustment module is further configured to be connected to a source voltage adjustment device, the source voltage adjustment device outputs a source voltage adjustment signal, and the adjustment module is based on the source The voltage adjustment signal adjusts the adjustment source voltage of the adjustment sequence.
  • the adjusted source voltage is configured to be the same as the intermediate value voltage of the driving sequence.
  • the intermediate value voltage is further explained below.
  • the intermediate value voltage is the average of the highest voltage and the lowest voltage in the previous execution sequence.
  • the positive frame of the display device is about 2.5V
  • the negative frame is about -2.5V
  • the middle The value voltage is 0V.
  • the intermediate value voltage is an intermediate value in a positive frame or a negative frame, for example: the positive frame source voltage is 0 ⁇ 5V, the intermediate value voltage is 2.5V; the negative frame voltage It is -5 ⁇ 0V, and the intermediate voltage is -2.5V.
  • the intermediate value voltage is the voltage at the intermediate time point of the previous execution sequence. In an embodiment of the present disclosure, when there are a plurality of data multiplexers, the intermediate value voltage is the average of the highest voltage and the lowest voltage in the previous execution sequence.
  • the intermediate value voltage is the average voltage of each data multiplexer at the intermediate time point of the previous execution sequence.
  • the adjusted source voltage can also be adjusted to a voltage value other than the intermediate voltage according to the display frequency and applicable occasions.
  • the adjustment source voltage is set to be higher than the average of the highest voltage and the lowest voltage in the previous execution sequence, by making the adjustment source The extreme voltage is close to the highest voltage of the previous execution sequence, further reducing the leakage current of the display.
  • the adjustment source voltage is set to be lower than the average of the highest voltage and the lowest voltage in the previous execution sequence, by making the adjustment source The extreme voltage is close to the lowest voltage of the previous execution sequence, so that while further reducing the leakage current of the display, it also achieves the effect of energy saving.
  • the display driving device includes a driving module configured to output a driving timing, wherein the driving timing includes an execution timing and a blank period timing, and is configured to interact with all
  • the adjustment module connected to the drive module, the adjustment module outputs to the drive module the adjustment timing for inserting the blank time period timing.
  • the leakage of the display can be reduced by adjusting the timing, and furthermore, by adjusting The time sequence enables the display to maintain charging when outputting the blank time period sequence, and can also reduce the voltage difference between the blank period sequence and the execution sequence of the display, thereby improving the flicker and crosstalk phenomenon of the display.

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示器驱动装置(10)，显示器驱动装置(10)包括被配置为周期性的输出驱动时序(101)的驱动模组(100)，驱动时序(101)的每一周期包括执行时序(W1,W2,W3)与空白时间段时序(B1,B2,B3)，以及被配置为与驱动模组(100)连接的调整模组(200)，调整模组(200)在空白时间段时序(B1,B2,B3)的时序范围中，对驱动模组(100)输出调整时序(201,T1,T2,T3)，通过调整时序(201)降低显示器驱动装置(10)的漏电。

Description

显示器驱动装置 技术领域
本揭示涉及显示技术领域，具体涉及显示器驱动装置。
 背景技术
目前的显示器频率一般为60HZ，即每秒内显示器的画面刷新60次，使人眼看到的画面是动态流畅的。而在某些应用场景下，为了节省显示器的功耗，需要显示器降频显示，例如：从60HZ降为30HZ。在另外一些场景下，例如：执行高频游戏时，需要提高显示器的频率，例如：从60HZ上升为90HZ或120HZ，从而使画面更为流畅。因此，为了适用于不同的场景，显示器需要变换显示频率，即动态帧频显示。
大部分显示器的显示频率从高频，变换到低频时，其中面板的充电时间并没有改变，只是单纯的延长了时序中的空白时间。
然而，由于此种方式使低频显示时使时序中的空白时间增加，导致显示器的漏电增加，容易使显示器出现画面闪烁或串扰等现象，严重影响显示器的显示品质。
更详细而言，请一并参照图1及图2，其分别显示现有技术的显示器驱动装置的驱动时序示意图及现有技术的像素电路示意图。如图所示，在空白时序内，闸极、数据多工器、源极都是关闭的。
当闸极关闭后，连接数据线的S点电位为最后一个数据多工器关闭时源极上的电压，由于此电压是不确定的，导致像素电路中Vds压差不确定。换言之，当闸极关闭、Vds压差较大时，像素电路的漏电流也会增加。
故，有需要提供一种显示器驱动方法，以解决现有技术存在的问题。
 技术问题
现有显示器的显示频率从高频，变换到低频时，其中面板的充电时间并没有改变，只是单纯的延长了时序中的空白时间，导致显示器的漏电增加，容易使显示器出现画面闪烁或串扰等现象，严重影响显示器的显示品质。
 技术解决方案
为解决上述问题，本揭示提出一种显示器驱动方法，其可降低显示器的漏电时间，进而改善显示器的闪烁和串扰现象。
为达成上述目的，本揭示提供一种显示器驱动装置。所述显示器驱动装置包括被配置为周期性的输出驱动时序的驱动模组，其中驱动时序包含执行时序与空白时间段时序，以及被配置为与驱动模组连接的调整模组，所述调整模组在每一所述空白时间段时序的时序范围中，对所述驱动模组输出调整时序。
于本揭示其中的一实施例中，所述显示器驱动装置包含第一数据多工器，被配置为用于输出第一多工驱动时序，所述第一多工驱动时序包含第一执行时序与第一空白时序。第二数据多工器，被配置为用于输出第二多工驱动时序，所述第二多工驱动时序包含第二执行时序与第二空白时序。第三数据多工器，被配置为用于输出第三多工驱动时序，所述第三多工驱动时序包含第三执行时序与第三空白时序。所述第一执行时序、第二执行时序与第三执行时序在所述执行时序的时序范围输出，所述第一空白时序、第二空白时序与第三空白时序在所述空白时间段时序的时序范围输出。
于本揭示其中的一实施例中，所述驱动模组还包括多个驱动闸极，当所述驱动模组输出所述空白时间段时序时，所述多个驱动闸极关闭。
于本揭示其中的一实施例中，所述驱动模组还包括多个驱动闸极，当所述驱动模组输出所述空白时间段时序时，所述多个驱动闸极处于低电位状态。
于本揭示其中的一实施例中，所述调整模组包含：第一数据多工器调整单元，与所述第一数据多工器连接，所述第一数据多工器调整单元对所述第一数据多工器用于输出第一调整时序。第二数据多工器调整单元，与所述第二数据多工器连接，所述第二数据多工器调整单元对所述第二数据多工器用于输出第二调整时序。第三数据多工器调整单元，与所述第三数据多工器连接，所述第三数据多工器调整单元对所述第三数据多工器用于输出第三调整时序。其中，所述调整时序包含所述第一调整时序、所述第二所述调整时序与所述第三所述调整时序，所述第一调整时序***所述第一空白时序中，所述第二调整时序***所述第二空白时序中，所述第三调整时序***第三空白时序中。
于本揭示其中的一实施例中，所述调整时序与前一所述执行时序连续。
于本揭示其中的一实施例中，所述调整时序不与所述执行时序连续。
于本揭示其中的一实施例中，所述调整时序占据所述空白时间段时序。
于本揭示其中的一实施例中，所述调整模组还被配置为连接有一源极电压调整装置，所述源极电压调整装置输出源极电压调整讯号，所述调整模组根据所述源极电压调整讯号调整所述调整时序的调整源极电压。
于本揭示其中的一实施例中，所述调整源极电压被配置为与所述驱动时序的中间值电压相同。
于本揭示其中的一实施例中，所述第一调整时序不与所述第一执行时序连续，所述第二调整时序不与所述第二执行时序连续，所述第三调整时序不与所述第三执行时序连续。
于本揭示其中的一实施例中，所述第一调整时序与所述第一执行时序连续，所述第二调整时序与所述第二执行时序连续，所述第三调整时序与所述第三执行时序连续。
于本揭示其中的一实施例中，所述第一调整时序占据所述第一空白时序所述第二调整时序占据所述第二空白时序，所述第三调整时序占据所述第二空白时序。
为达成上述目的，本揭示还提供一种显示器驱动装置。所述显示器驱动装置包括被配置为周期性的输出驱动时序的驱动模组，其中驱动时序包含执行时序与空白时间段时序，以及被配置为与驱动模组连接的调整模组，所述调整模组在每一所述空白时间段时序的时序范围中，对所述驱动模组输出调整时序，所述调整时序与前一所述执行时序连续。所述调整模组还被配置为连接有源极电压调整装置，所述源极电压调整装置用于输出源极电压调整讯号，所述调整模组根据所述源极电压调整讯号调整所述调整时序的调整源极电压。
为达成上述目的，本揭示再提供一种显示器驱动装置。所述显示器驱动装置包括被配置为周期性的输出驱动时序的驱动模组，其中驱动时序包含执行时序与空白时间段时序，以及被配置为与驱动模组连接的调整模组，所述调整模组在每一所述空白时间段时序的时序范围中，对所述驱动模组输出调整时序，所述调整时序不与所述执行时序连续。所述调整模组还被配置为连接有源极电压调整装置，所述源极电压调整装置用于输出源极电压调整讯号，所述调整模组根据所述源极电压调整讯号调整所述调整时序的调整源极电压。
 有益效果
相较于现有技术，由于本揭示的显示器驱动装置，所述显示器驱动装置包括被配置为周期性的输出驱动时序的驱动模组，其中所述驱动时序的每一周期分别包含执行时序与空白时间段时序，以及被配置为与所述驱动模组连接的调整模组，所述调整模组在所述空白时间段时序的时序范围中，对所述驱动模组输出调整时序，通过调整时序降低显示器驱动装置的漏电，进而改善闪烁和串扰现象。
 附图说明
图1显示现有技术的显示器驱动装置的驱动时序示意图。
图2显示现有技术的像素电路示意图。
图3显示根据本揭示的一实施例的显示器驱动装置的方块示意图。
图4显示根据本揭示的一实施例的显示器驱动装置的驱动时序示意图。
图5显示根据本揭示的一实施例的显示器驱动装置的驱动时序示意图。
图6显示根据本揭示的一实施例的显示器驱动装置的驱动时序示意图。
 本发明的最佳实施方式
以下实施例的说明是参考附加的图示，用以例示本揭示可用以实施的特定实施例。本揭示所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图示的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。
在图中，结构相似的单元是以相同标号表示。
请参照图3，其是显示根据本揭示的一实施例的显示器驱动装置的方块示意图，如图所示，本揭示提供一种显示器驱动装置10。所述显示器驱动装置10包括被配置为输出驱动时序101的驱动模组100，其中驱动时序包括执行时序与空白时间段时序，以及被配置为与驱动模组100连接的调整模组200，所述调整模组200对所述驱动模组100输出***所述空白时间段时序的调整时序201。
其中，驱动时序101可由复数个数据多工器的驱动时序所构成，其构成数量依照适用的影像复杂程度与环境要求而决定，以下进一步以三个数据多工器的情况说明本揭露的其他实施例。
其中，在下列实施方式中，第一数据多工器MUXR可为输出红色讯号的数据多工器、第二数据多工器MUXG可为输出绿色讯号的数据多工器，第三数据多工器MUXB可为输出绿蓝色讯号的数据多工器。
请进一步搭配参照图4至图6，于本揭示其中的一实施例中，所述显示器驱动装置包括第一数据多工器MUXR，被配置为用于输出第一多工驱动时序，所述第一多工驱动时序包括分布于执行时序的第一执行时序与分布于空白时间段时序的第一空白时序。第二数据多工器MUXB，被配置为用于输出第二多工驱动时序，所述第二多工驱动时序包括分布于执行时序的第二执行时序与分布于空白时间段时序的第二空白时序。第三数据多工器MUXB，被配置为用于输出第三多工驱动时序，所述第三多工驱动时序包括分布于执行时序的第三执行时序与分布于空白时间段时序的第三空白时序。所述第一执行时序、第二执行时序与第三执行时序在所述执行时序的时序范围输出，所述第一空白时序、第二空白时序与第三空白时序在所述空白时间段时序的时序范围输出。
于本揭示其中的一实施例中，所述驱动模组还包括多个驱动闸极。多个驱动闸极包含第一闸极Gate1，被配置为用于输出第一闸极时序。第二闸极Gate2，被配置为用于输出第二闸极时序。第三闸极Gate3，被配置为用于输出第三闸极时序，为描述驱动闸极的设置数量可设置为N个不以3个为限，图中还绘示出第N闸极Gate(n)，被配置为用于输出第N闸极时序。
当所述驱动模组输出所述空白时间段时序时，所述多个驱动闸极包含所述第一闸极Gate1、所述第二闸极Gate2、所述第三闸极Gate3至所述第N闸极Gate(n)关闭或处于低电位状态。
于本揭示其中的一实施例中，所述调整模组包括：第一数据多工器调整单元，与所述第一数据多工器连接，所述第一数据多工器调整单元对所述第一数据多工器用于输出第一调整时序。第二数据多工器调整单元，与所述第二数据多工器连接，所述第二数据多工器调整单元对所述第二数据多工器用于输出第二调整时序。第三数据多工器调整单元，与所述第三数据多工器连接，所述第三数据多工器调整单元对所述第三数据多工器用于输出第三调整时序。其中，所述调整时序包括所述第一调整时序、所述第二所述调整时序与所述第三所述调整时序，所述第一调整时序***所述第一空白时序中，所述第二调整时序***所述第二空白时序中，所述第三调整时序***第三空白时序中。
请进一步参照图4，其显示根据本揭示的一实施例的显示器驱动装置的接收调整时序后的驱动时序示意图，如图所示，其分别揭露第一闸极Gate1、第二闸极Gate2、第三闸极Gate3至第N闸极Gate(n)、第一数据多工器MUXR、第二数据多工器MUXG、第三数据多工器MUXB及源极Source在该实施例的驱动时序F1、空白时间段时序B1以及调整时序T1的时序图。
在图4的实施例中，调整时序T1不与执行时序W1连续。进一步而言，如图所示，调整时序T1的时间范围内包括：第一数据多工器MUXR的第一调整时序，第二数据多工器MUXG的第二调整时序，第三数据多工器MUXB的第三调整时序。换言之，第一数据多工器MUXR的第一调整时序不与第一执行时序连续，第二数据多工器MUXG的第二调整时序不与第二执行时序连续，第三数据多工器MUXB的第三调整时序不与第三执行时序连续，通过加入调整时序，减少像素电路中Vds压差，从而减少像素电路的漏电流。
进一步而言，在空白时间段时序B1时，所述第一闸极Gate1、所述第二闸极Gate2与所述第三闸极Gate3至所述第N闸极Gate(n)显示平稳讯号。换言之，在空白时间段时序B1的时序时间中，第一闸极Gate1、所述第二闸极Gate2与所述第三闸极Gate3至第N闸极Gate(n)，处于低电位状态或关闭状态。
请参照图5，其显示根据本揭示的一实施例的显示器驱动装置的驱动时序示意图，如图所示，其分别揭露第一闸极Gate1、第二闸极Gate2、第三闸极Gate3至第N闸极Gate(n)、第一数据多工器MUXR、第二数据多工器MUXG、第三数据多工器MUXB及源极Source在该实施例的驱动时序F2、空白时间段时序B2以及调整时序T2的时序图。
在该实施例中，调整时序T2与前一执行时序W2连续。进一步而言，调整时序T2的时间范围内包括，第一数据多工器MUXR的第一调整时序，第二数据多工器MUXG的第二调整时序，第三数据多工器MUXB的第三调整时序；换言之，第一数据多工器MUXR的第一调整时序与第一执行时序连续，第二数据多工器MUXG的第二调整时序与第二执行时序连续，第三数据多工器MUXB的第三调整时序与第三执行时序连续，通过加入调整时序，减少像素电路中Vds压差，从而减少像素电路的漏电流。
请参照图6，其显示根据本揭示的一实施例的显示器驱动装置的驱动时序示意图，如图所示，其分别揭露第一闸极Gate1、第二闸极Gate2、第三闸极Gate3至第N闸极Gate(n)、第一数据多工器MUXR、第二数据多工器MUXG、第三数据多工器MUXB及源极Source在该实施例的驱动时序F3、空白时间段时序B3以及调整时序T3的时序图。
在该实施例中，调整时序T3占据空白时间段时序B3，换言之，调整时序T3与空白时间段时序B3的时序时间相同，与前一执行时序W3连续。
进一步而言，调整时序T3的时间范围内包括：第一数据多工器MUXR的第一调整时序，第二数据多工器MUXG的第二调整时序，第三数据多工器MUXB的第三调整时序；换言之，第一数据多工器MUXR的第一调整时序占据第一空白时序，第二数据多工器MUXG的第二调整时序占据第二空白时序，第三数据多工器MUXB的第三调整时序占据第三空白时序，通过加入调整时序，减少像素电路中Vds压差，从而减少像素电路的漏电流。
于本揭示其中的一实施例中，所述调整模组还被配置为连接有源极电压调整装置，所述源极电压调整装置输出源极电压调整讯号，所述调整模组根据所述源极电压调整讯号调整所述调整时序的调整源极电压。
于本揭示其中的一实施例中，所述调整源极电压被配置为与所述驱动时序的中间值电压相同。以下进一步说明所述中间值电压。
于本揭示其中的一实施例中，所述中间值电压为前一执行时序中最高电压与最低电压的平均，例如：显示装置的正帧约为2.5V，负帧约为-2.5V，中间值电压为0V。
于本揭示其中的一实施例中，所述中间值电压为一个正帧或一个负帧内的中间值，例如:正帧源极电压为0~5V，中间值电压为2.5V；负帧电压为-5~0V，中间值电压为-2.5V。
于本揭示其中的一实施例中，所述中间值电压为前一执行时序中间时间点的电压。于本揭示其中的一实施例中，在具有复数个数据多工器的情况下，所述中间值电压为前一执行时序中最高电压与最低电压的平均。
于本揭示其中的一实施例中，在具有复数个数据多工器的情况下，所述中间值电压为前一执行时序中间时间点的各数据多工器执行时序中间时间点的平均电压。
于本揭示其中的一实施例中，所述调整源极电压亦可根据显示器频率与适用场合而调整为非所述中间值电压的其他电压值。
于本揭示其中的一实施例中，当显示器的适用场合为执行高频显示，则所述调整源极电压被设置为较前一执行时序中最高电压与最低电压的平均高，通过使调整源极电压接近前一执行时序的最高电压，进一步降低显示器的漏电流。
于本揭示其中的另一实施例中，当显示器的适用场合为执行低频显示，则所述调整源极电压被设置为较前一执行时序中最高电压与最低电压的平均低，通过使调整源极电压接近前一执行时序的最低电压，使得在进一步降低显示器的漏电流的同时，亦达到兼顾节能的效果。
综上所述，由于本揭示的显示器驱动装置，所述显示器驱动装置包括被配置为输出驱动时序的驱动模组，其中所述驱动时序包括执行时序与空白时间段时序，以及被配置为与所述驱动模组连接的调整模组，所述调整模组对所述驱动模组输出***所述空白时间段时序的调整时序，一方面，可通过调整时序降低显示器的漏电，再者，通过调整时序使显示器在输出空白时间段时序时维持充电，亦可降低显示器在空白时间段时序与执行时序中的电压差，进而改善显示器的闪烁和串扰现象。
尽管已经相对于一个或多个实现方式示出并描述了本揭示，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本揭示包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
以上仅是本揭示的优选实施方式，应当指出，对于本领域普通技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。

Claims (20)

  1. 一种显示器驱动装置，包括:
    驱动模组，被配置为周期性的输出驱动时序，其中所述驱动时序包含执行时序与空白时间段时序；以及
    调整模组，被配置为与所述驱动模组连接，所述调整模组在每一所述空白时间段时序的时序范围中，对所述驱动模组输出调整时序。
  2. 如权利要求1所述的显示器驱动装置，所述驱动模组包括：
    第一数据多工器，被配置为用于输出第一多工驱动时序，所述第一多工驱动时序包括第一执行时序与第一空白时序；
    第二数据多工器，被配置为用于输出第二多工驱动时序，所述第二多工驱动时序包括第二执行时序与第二空白时序；以及
    第三数据多工器，被配置为用于输出第三多工驱动时序，所述第三多工驱动时序包含第三执行时序与第三空白时序；
    其中，所述第一执行时序、所述第二执行时序与所述第三执行时序在所述执行时序的时序范围输出，所述第一空白时序、所述第二空白时序与所述第三空白时序在所述空白时间段时序的所述时序范围输出。
  3. 如权利要求2所述的显示器驱动装置，所述驱动模组还包括多个驱动闸极，当所述驱动模组输出所述空白时间段时序时，所述多个驱动闸极关闭。
  4. 如权利要求2所述的显示器驱动装置，所述驱动模组还包括多个驱动闸极，当所述驱动模组输出所述空白时间段时序时，所述多个驱动闸极处于低电位状态。
  5. 如权利要求2所述的显示器驱动装置，所述调整模组包含：
    第一数据多工器调整单元，与所述第一数据多工器连接，所述第一数据多工器调整单元对所述第一数据多工器用于输出第一调整时序；
    第二数据多工器调整单元，与所述第二数据多工器连接，所述第二数据多工器调整单元对所述第二数据多工器用于输出第二调整时序；
    第三数据多工器调整单元，与所述第三数据多工器连接，所述第三数据多工器调整单元对所述第三数据多工器用于输出第三调整时序；
    其中，所述调整时序包含所述第一调整时序、所述第二所述调整时序与所述第三所述调整时序，所述第一调整时序***所述第一空白时序中，所述第二调整时序***所述第二空白时序中，所述第三调整时序***第三空白时序中。
  6. 如权利要求1所述的显示器驱动装置，所述调整时序与前一所述执行时序连续。
  7. 如权利要求1所述的显示器驱动装置，所述调整时序不与所述执行时序连续。
  8. 如权利要求1所述的显示器驱动装置，所述调整时序占据所述空白时间段时序。
  9. 如权利要求1所述的显示器驱动装置，所述调整模组还被配置为连接有源极电压调整装置，所述源极电压调整装置用于输出源极电压调整讯号，所述调整模组根据所述源极电压调整讯号调整所述调整时序的调整源极电压。
  10. 如权利要求9所述的显示器驱动装置，所述调整源极电压被配置为与所述驱动时序的中间值电压相同。
  11. 如权利要求5所述的显示器驱动装置，其中，所述第一调整时序不与所述第一执行时序连续，所述第二调整时序不与所述第二执行时序连续，所述第三调整时序不与所述第三执行时序连续。
  12. 如权利要求5所述的显示器驱动装置，其中，所述第一调整时序与所述第一执行时序连续，所述第二调整时序与所述第二执行时序连续，所述第三调整时序与所述第三执行时序连续。
  13. 如权利要求5所述的显示器驱动装置，其中，所述第一调整时序占据所述第一空白时序所述第二调整时序占据所述第二空白时序，所述第三调整时序占据所述第二空白时序。
  14. 一种显示器驱动装置，包括:
    驱动模组，被配置为周期性的输出驱动时序，其中所述驱动时序包含执行时序与空白时间段时序；以及
    调整模组，被配置为与所述驱动模组连接，所述调整模组在每一所述空白时间段时序的时序范围中，对所述驱动模组输出调整时序，所述调整时序与前一所述执行时序连续；
    其中，所述调整模组还被配置为连接有源极电压调整装置，所述源极电压调整装置用于输出源极电压调整讯号，所述调整模组根据所述源极电压调整讯号调整所述调整时序的调整源极电压。
  15. 如权利要求14所述的显示器驱动装置，所述驱动模组包括：
    第一数据多工器，被配置为用于输出第一多工驱动时序，所述第一多工驱动时序包括第一执行时序与第一空白时序；
    第二数据多工器，被配置为用于输出第二多工驱动时序，所述第二多工驱动时序包括第二执行时序与第二空白时序；以及
    第三数据多工器，被配置为用于输出第三多工驱动时序，所述第三多工驱动时序包含第三执行时序与第三空白时序；
    其中，所述第一执行时序、所述第二执行时序与所述第三执行时序在所述执行时序的时序范围输出，所述第一空白时序、所述第二空白时序与所述第三空白时序在所述空白时间段时序的所述时序范围输出。
  16. 如权利要求14所述的显示器驱动装置，所述调整模组包含：
    第一数据多工器调整单元，与所述第一数据多工器连接，所述第一数据多工器调整单元对所述第一数据多工器用于输出第一调整时序；
    第二数据多工器调整单元，与所述第二数据多工器连接，所述第二数据多工器调整单元对所述第二数据多工器用于输出第二调整时序；以及
    第三数据多工器调整单元，与所述第三数据多工器连接，所述第三数据多工器调整单元对所述第三数据多工器用于输出第三调整时序。
  17. 如权利要求14所述的显示器驱动装置，所述调整源极电压被配置为与所述驱动时序的中间值电压相同。
  18. 一种显示器驱动装置，包括:
    驱动模组，被配置为周期性的输出驱动时序，其中所述驱动时序包含执行时序与空白时间段时序；以及
    调整模组，被配置为与所述驱动模组连接，所述调整模组在每一所述空白时间段时序的时序范围中，对所述驱动模组输出调整时序，所述调整时序不与所述执行时序连续；
    其中，所述调整模组还被配置为连接有源极电压调整装置，所述源极电压调整装置用于输出源极电压调整讯号，所述调整模组根据所述源极电压调整讯号调整所述调整时序的调整源极电压。
  19. 如权利要求18所述的显示器驱动装置，所述调整模组包含：
    第一数据多工器调整单元，与所述第一数据多工器连接，所述第一数据多工器调整单元对所述第一数据多工器用于输出第一调整时序；
    第二数据多工器调整单元，与所述第二数据多工器连接，所述第二数据多工器调整单元对所述第二数据多工器用于输出第二调整时序；以及
    第三数据多工器调整单元，与所述第三数据多工器连接，所述第三数据多工器调整单元对所述第三数据多工器用于输出第三调整时序。
  20. 如权利要求18所述的显示器驱动装置，所述调整源极电压被配置为与所述驱动时序的中间值电压相同。
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