WO2020215875A1 - Thin film transistor and preparation method therefor, array substrate and display device - Google Patents

Thin film transistor and preparation method therefor, array substrate and display device Download PDF

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Publication number
WO2020215875A1
WO2020215875A1 PCT/CN2020/076258 CN2020076258W WO2020215875A1 WO 2020215875 A1 WO2020215875 A1 WO 2020215875A1 CN 2020076258 W CN2020076258 W CN 2020076258W WO 2020215875 A1 WO2020215875 A1 WO 2020215875A1
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Prior art keywords
thin film
film transistor
pattern
substrate
insulating layer
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PCT/CN2020/076258
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French (fr)
Chinese (zh)
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袁广才
郭康
董学
卢鑫泓
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京东方科技集团股份有限公司
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Publication of WO2020215875A1 publication Critical patent/WO2020215875A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/191—Deposition of organic active material characterised by provisions for the orientation or alignment of the layer to be deposited
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes

Definitions

  • the present disclosure relates to the field of display technology, in particular to a thin film transistor and a preparation method thereof, an array substrate, and a display device.
  • TFTs thin-film transistors
  • LTPS low temperature polysilicon
  • the thin film transistor further includes an insulating layer disposed between the substrate and the active pattern.
  • the insulating layer includes a plurality of grooves. The grooves correspond to the sub-patterns one-to-one, and the orthographic projection of the grooves on the substrate overlaps the orthographic projection of the corresponding sub-patterns on the substrate.
  • the sub-pattern is filled in the corresponding groove.
  • the surface of the sub-pattern on the side close to the substrate is flush with the bottom surface of the corresponding groove.
  • the groove penetrates the insulating layer.
  • the thin film transistor is a bottom-gate thin film transistor; the thin film transistor further includes a gate insulating layer disposed on the substrate, and the gate insulating layer is disposed on a side of the insulating layer close to the substrate, The modification pattern directly contacts the gate insulating layer.
  • the thin film transistor is a top gate thin film transistor or a double gate thin film transistor; the thin film transistor further includes a buffer layer disposed on the substrate, and the buffer layer is disposed near the insulating layer. On one side of the substrate, the modified pattern is in direct contact with the buffer layer.
  • a display device in yet another aspect, includes the array substrate as described in some of the above embodiments.
  • a method for manufacturing a thin film transistor includes:
  • An insulating film is formed on the substrate, and a plurality of grooves extending along the first direction and arranged at intervals are formed in the insulating film to obtain an insulating layer.
  • An active pattern including carbon nanotubes is formed on the side of the insulating layer away from the substrate; the active pattern includes a plurality of sub-patterns arranged at intervals, and the sub-patterns correspond to the grooves one-to-one, And the orthographic projection of the sub-pattern on the substrate overlaps the orthographic projection of the corresponding groove on the substrate.
  • the method for manufacturing the thin film transistor further includes: filling each of the grooves with a modified pattern.
  • Forming the active pattern further includes: forming the corresponding sub-pattern on the surface of the modified pattern facing away from the substrate, the orthographic projection of the modified pattern on the substrate and the corresponding sub-pattern The sub-patterns overlap in orthographic projection on the substrate.
  • the groove penetrates the insulating layer.
  • the thin film transistor is a bottom-gate thin film transistor; before forming the insulating layer, the method for preparing the thin film transistor further includes forming a gate insulating layer on a substrate; the modified pattern is in direct contact with the gate insulating layer.
  • the thin film transistor is a top-gate thin film transistor or a double-gate thin film transistor; before forming the insulating layer, the method for preparing the thin film transistor further includes forming a buffer layer on a substrate; the modified pattern and the The buffer layer is in direct contact.
  • FIG. 1 is a schematic structural diagram of a display device according to some embodiments of the present disclosure
  • FIG. 2 is a schematic top view of a thin film transistor according to some embodiments of the present disclosure
  • FIG. 4 is a schematic structural diagram of a thin film transistor according to some embodiments of the present disclosure.
  • FIG. 5 is a schematic structural diagram of another thin film transistor in some embodiments of the present disclosure.
  • FIG. 6 is a schematic structural diagram of yet another thin film transistor in some embodiments of the present disclosure.
  • FIG. 7 is a schematic structural diagram of yet another thin film transistor in some embodiments of the present disclosure.
  • Fig. 8b is a schematic diagram of an arrangement of carbon nanotubes according to some embodiments of the present disclosure.
  • FIG. 9 is a schematic structural diagram of an insulating layer in some embodiments according to the present disclosure.
  • FIG. 10 is a schematic structural diagram of yet another thin film transistor in some embodiments of the present disclosure.
  • FIG. 11 is a schematic structural diagram of yet another thin film transistor in some embodiments of the present disclosure.
  • FIG. 12 is a schematic structural diagram of another thin film transistor according to some embodiments of the present disclosure.
  • FIG. 14 is a schematic structural diagram of another array substrate according to some embodiments of the present disclosure.
  • FIG. 15 is a schematic structural diagram of another array substrate according to some embodiments of the present disclosure.
  • Fig. 16 is a schematic flow chart of a method for manufacturing a thin film transistor in some embodiments of the present disclosure
  • FIG. 17 is a schematic diagram of a manufacturing process of a thin film transistor in some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content herein.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • the display device can be used as a mobile phone, a tablet computer, a personal digital assistant (PDA), a vehicle-mounted computer, etc. Some embodiments of the present disclosure do not limit the application of the display device.
  • PDA personal digital assistant
  • the display device may include, for example, a frame 1, a display panel 2, a circuit board 3, a cover 4, and other electronic accessories (not shown in the figure) including a camera. .
  • the frame 1 is a U-shaped frame, and the display panel 2 and the circuit board 3 are arranged in the frame 1.
  • the cover plate 4 is arranged on the light emitting side of the display panel 2, and the cover plate 4 is a transparent cover plate, such as a glass cover plate.
  • the circuit board 3 is arranged on the side of the display panel 2 facing away from the cover 4 and is electrically connected to the display panel 2 to control the display of the display panel 2.
  • the embodiment of the present disclosure provides a thin film transistor, which can be used as the thin film transistor in the above-mentioned array substrate 21.
  • the thin film transistor can also be used in other circuit structures of the display device, such as other substrates, which are not limited in the embodiment of the present disclosure.
  • the above-mentioned thin film transistor further includes an insulating layer 14 disposed between the substrate 10 and the active pattern.
  • the insulating layer 14 includes a plurality of grooves 141, and the grooves 141 correspond to the sub-pattern 11 one-to-one, and the orthographic projection of the groove 141 on the substrate 10 and the orthographic projection of the sub-pattern 11 on the substrate 10 completely overlap.
  • the thin film transistor is a double-gate thin film transistor, that is, the thin film transistor includes a gate 15 and an auxiliary gate electrode 19 electrically connected to the gate 15, the gate 15 and The auxiliary gate electrodes 19 are respectively located on the side of the active pattern away from the substrate 10.
  • the double-gate thin film transistor also includes a gate insulating layer 16 disposed between the active pattern and the gate 15 and a layer disposed between the gate 15 and the auxiliary gate electrode 19, the source electrode 12, and the drain electrode 13. Between insulating layer 18.
  • the gate insulating layer 16, the gate 15 and the interlayer insulating layer 18 are located on the side of the source 12 and the drain 13 close to the substrate 10.
  • the carbon nanotubes in the embodiments of the present disclosure are used to make active patterns, the carbon nanotubes used in the embodiments of the present disclosure are semiconductor-type carbon nanotubes.
  • the carbon nanotube raw materials include metallic carbon nanotubes and semiconductor carbon nanotubes.
  • the metallic carbon nanotubes in the carbon nanotube raw materials can be removed by centrifugation or the like to obtain the semiconductor carbon nanotubes.
  • Some embodiments of the present disclosure do not limit the number of sub-patterns 11 in the active pattern.
  • the number of sub-patterns 11 in the active pattern is related to the size of the source electrode 12 and the drain electrode 13 and the width of the cross section of each sub-pattern 11.
  • the cross-section of the sub-pattern 11 is a cross-section along the thickness direction perpendicular to the substrate 10, and the width of the cross-section of the sub-pattern 11 is perpendicular to the first direction.
  • the sizes of the multiple sub-patterns 11 in the active pattern may be the same or different.
  • the embodiment of the present disclosure does not limit the width range of the cross section of the plurality of sub-patterns 11.
  • the width of the cross section of each sub-pattern 11 should be at least greater than or equal to the diameter of one carbon nanotube, and less than the length of the carbon nanotube, so as to facilitate the sequential arrangement of multiple carbon nanotubes.
  • the width range of the cross section of the sub-pattern 11 is greater than or equal to 1 nm and less than 1000 nm.
  • the diameter of the carbon nanotube 111 is about 1 nm and the length is about 1000 nm, the length of the carbon nanotube 111 is much larger than its diameter.
  • the carbon nanotube 111 is limited to a region with a width greater than or equal to 500 nm and less than 1000 nm, so that the angle between each carbon nanotube 111 and the first direction is small, and more The angle between the two carbon nanotubes 111 is negligible, thereby improving the mobility of the thin film transistor.
  • each sub-pattern 11 is not limited to a stripe shape, and other shapes that are convenient for manufacturing and facilitate the sequential arrangement of carbon nanotubes and the neat arrangement of the sub-patterns 11 are also acceptable.
  • the material of the source electrode 12 and the drain electrode 13 includes metal materials such as molybdenum (Mo), copper (Cu), molybdenum-niobium alloy (MoNb), and aluminum (Al).
  • the material of the source electrode 12 and the drain electrode 13 includes transparent conductive materials such as indium tin oxide (ITO).
  • the material of the gate 15 includes metal materials such as Mo, Cu, MoNb, and Al. In other embodiments, the material of the gate 15 includes transparent conductive materials such as ITO.
  • the source electrode 12, the drain electrode 13, and the gate electrode 15 may have a single-layer structure or a multilayer structure.
  • the source electrode 12, the drain electrode 13, and the gate electrode 15 include a metal layer, and the material is copper; or, the source electrode 12, the drain electrode 13, and the gate electrode 15 include two stacked metal layers, one of which is a metal layer.
  • the material of the layer is chromium (Cr), and the material of the other metal layer is gold (Au).
  • the carbon nanotubes 111 are usually arranged in disorder. If a plurality of carbon nanotubes 111 in the active pattern obtained by using carbon nanotubes are arranged disorderly, the mobility of the thin film transistor is likely to be lower.
  • the active pattern includes a plurality of sub-patterns 11 arranged at intervals, so that each sub-pattern 11 includes one or more carbon nanotubes 111.
  • the carbon nanotubes 111 in each sub-pattern 11 are limited to the area where the sub-pattern 11 is located, which can limit the arrangement of the carbon nanotubes 111 in one sub-pattern 11.
  • the area where each sub-pattern 11 is located in the embodiment of the present disclosure is much smaller.
  • the regions where the active patterns are located are arranged in any direction, and the angle between the extending direction of the carbon nanotubes 111 and the first direction in the embodiment of the present disclosure is small (as shown in FIG. 8b), and then a plurality of carbon nanotubes 111 The angle between them is negligible, that is, the multiple carbon nanotubes 111 can be arranged regularly, which can improve the low mobility of the thin film transistor caused by the irregular arrangement of the multiple carbon nanotubes 111 in the active pattern. The problem.
  • each sub-pattern 11 in the groove 141 there may be multiple ways of disposing each sub-pattern 11 in the groove 141 in the above-mentioned active pattern.
  • the surface of the sub-pattern 11 on the side close to the substrate 10 is flush with the bottom surface of the corresponding groove 141. That is, the sub-pattern 11 is directly formed in the groove 141 corresponding thereto.
  • the bottom surface of the groove 141 that is, the surface of the groove 141 close to the substrate 10.
  • the insulating layer 14 having the groove 141 may be formed on the substrate 10 first; then, the sub-pattern 11 is directly formed in the groove 141 to obtain a plurality of sub-patterns 11 arranged at intervals.
  • the material of the decoration pattern 20 is selected and set according to actual needs.
  • the material of the modified pattern 20 may chemically react with the carbon nanotube 111, such as chemical adsorption, so that the sub-pattern 11 is only formed on the modified pattern 20.
  • the material of the modification pattern 20 does not undergo a condensation reaction with the material of the insulating layer 14, so as to prevent the modification pattern 20 from being formed on the surface of the insulating layer 14 facing away from the substrate 10. This prevents the active pattern from being formed in areas other than the area where the groove 141 is located.
  • the thickness of the modification pattern 20 is smaller than the depth of the corresponding groove 141.
  • the sum of the thickness of the modified pattern 20 and the sub-pattern 11 is greater than the depth of the corresponding groove 141, a part of the sub-pattern 11 is filled in the corresponding groove 141, and the other part is higher than the distance of the insulating layer 14.
  • the surface of the substrate 10. When the sum of the thickness of the modified pattern 20 and the sub-pattern 11 is less than or equal to the depth of the corresponding groove 141, the sub-pattern 11 is completely filled in the corresponding groove 141.
  • the thickness of the modified pattern 20 is exactly equal to the depth of the corresponding groove 141, and all the sub-patterns 11 are higher than the surface of the insulating layer 14 away from the substrate 10.
  • the thickness of the modification pattern 20 is greater than the depth of the corresponding groove 141.
  • the groove 141 may penetrate through the insulating layer 14 or not through the insulating layer 14.
  • the thickness direction of the sub-pattern 11, the thickness direction of the modification pattern 20, and the depth direction of the groove 141 are all parallel to the thickness direction of the substrate 10.
  • the depth of the groove 141 at each position may be the same or different.
  • the embodiment of the present disclosure compares the maximum depth of the groove 141 with the maximum thickness of the sub-pattern 11 or the maximum thickness of the modification pattern 20.
  • the modification pattern 20 is formed in the groove 141 first, and then the sub-pattern 11 is formed on the side of the modification pattern 20 facing away from the substrate 10.
  • the modification pattern 20 can be formed only in the groove 141. Since the material of the modified pattern 20 can chemically react with the carbon nanotubes 111, the modified pattern 20 can firmly adsorb and fix the carbon nanotubes 111, so that the sub-pattern 11 is only formed on the modified pattern 20.
  • the multiple sub-patterns 11 in the finally obtained active pattern are spaced apart from each other, and the orthographic projection of each sub-pattern 11 on the substrate 10 and the orthographic projection of the corresponding groove 141 on the substrate 10 exactly overlap.
  • the gate insulating layer 16 can be used as the insulating layer 14; if the thin film transistor is top For gate thin film transistors or double gate thin film transistors, the buffer layer 17 can be used as the insulating layer 14 in common. In this way, the manufacturing process of the thin film transistor can be simplified and the cost can be saved.
  • the gate insulating layer 16 is disposed on the insulating layer 14 close to the substrate 10.
  • the modified pattern 20 is in direct contact with the gate insulating layer 16.
  • the material of the modification pattern 20 may undergo a condensation reaction with the material of the gate insulating layer 16 to enhance the adhesion between the modification pattern 20 and the gate insulating layer 16 so that the modification pattern 20 is fixed on the gate insulating layer 16.
  • the material of the modification pattern 20 may be an amphoteric coupling agent.
  • one group in the amphoteric coupling agent chemically reacts with the carbon nanotube 111, and the other group undergoes a condensation polymerization reaction with the material of the gate insulating layer 16.
  • the amphoteric coupling agent is a silane coupling agent, for example, 3-aminopropyltriethoxysilane (APTES).
  • the material of the gate insulating layer 16 is silicon oxide (SiO x ), hafnium dioxide (HfO 2 ), or a composite film layer of magnesium oxide (MgO) and HfO 2 .
  • the material of the insulating layer 14 is a hydrophobic insulating material, such as silicon nitride (SiN x ).
  • the silane coupling agent includes an amino group and a carboxyl group.
  • the carboxyl group and the material of the gate insulating layer 16 are polycondensed to form a self-assembled monolayer.
  • the amino group reacts chemically with the carbon nanotube 111 and adsorbs it on the surface of the modified pattern 20.
  • the material of the modified pattern 20 may undergo a condensation reaction with the material of the buffer layer 17 to enhance the adhesion between the modified pattern 20 and the buffer layer 17 so that the modified pattern 20 is fixed on the buffer layer 17.
  • the material of the modification pattern 20 may be an amphoteric coupling agent.
  • one group in the amphoteric coupling agent chemically reacts with the carbon nanotube 111, and the other group undergoes a condensation polymerization reaction with the material of the buffer layer 17.
  • the silane coupling agent includes an amino group and a carboxyl group.
  • the carboxyl group and the material of the buffer layer 17 are polycondensed to form a self-assembled monolayer.
  • the amino group reacts chemically with the carbon nanotube 111 and adsorbs it on the surface of the modified pattern 20.
  • the embodiment of the present disclosure also provides an array substrate 21.
  • the array substrate 21 includes a plurality of pixel circuits 210 (the figure only schematically illustrates the location of the pixel circuit 210, and does not limit the structure thereof).
  • Each pixel circuit 210 includes at least one driving transistor 31, and the at least one driving transistor 31 is the thin film transistor described in any of the foregoing embodiments.
  • the embodiments of the present disclosure also provide a method for manufacturing a thin film transistor for manufacturing the thin film transistor described in some of the above embodiments. As shown in FIG. 16, the manufacturing method of the thin film transistor includes S11 to S13.
  • the carbon nanotubes 111 in the embodiments of the present disclosure are used for making active patterns
  • the carbon nanotubes 111 used in the embodiments of the present disclosure are semiconductor-type carbon nanotubes.
  • the method of obtaining the semiconductor carbon nanotubes can be referred to the relevant records of the foregoing embodiments, and the details are omitted here.
  • the formation method of the active pattern can be selected and set according to actual needs.
  • the carbon nanotube 111 solution can be formed on the substrate 10 by spraying, spin coating, blade coating, or inkjet printing; after that, the carbon nanotube 111 solution is dried at a high temperature to obtain carbon nanotubes. film.
  • the obtained carbon nanotube film is the active pattern.
  • a source electrode 12 and a drain electrode 13 are respectively formed on the side of the active pattern away from the substrate 10. Along the first direction, one end of each sub-pattern 11 in the active pattern is in contact with the source electrode 12 and the other end is in contact with the drain electrode 13.
  • the materials and structures of the source electrode 12 and the drain electrode 13 can be referred to the relevant description of the foregoing embodiment, and will not be described in detail here.
  • the manufacturing method of the thin film transistor provided by the embodiment of the present disclosure has the same technical effect as the aforementioned thin film transistor, and will not be repeated here.
  • the method for manufacturing the thin film transistor further includes: filling each groove 141 with a modified pattern 20.
  • the forming of the active pattern in S12 further includes: forming a corresponding sub-pattern 11 on the surface of the modified pattern 20 facing away from the substrate 10.
  • the modification pattern 20 has a one-to-one correspondence and direct contact with the sub-pattern 11, and the orthographic projection of the modification pattern 20 on the substrate 10 and the orthographic projection of the corresponding sub-pattern 11 on the substrate 10 completely overlap.
  • the groove 141 penetrates through the insulating layer 14.
  • the thin film transistor is a bottom-gate thin film transistor.
  • the manufacturing method of the thin film transistor further includes forming a gate insulating layer 16 on the substrate 10.
  • the modification pattern 20 directly contacts the gate insulating layer 16 disposed on the side of the insulating layer 14 close to the substrate 10.
  • the thin film transistor is a top gate thin film transistor or a double gate thin film transistor.
  • the manufacturing method of the thin film transistor further includes forming a buffer layer 17 on the substrate 10.
  • the modification pattern 20 directly contacts the buffer layer 17 disposed on the side of the insulating layer 14 close to the substrate 10.
  • the material of the aforementioned modification pattern 20 can be selected and set according to actual requirements.
  • the material of the modified pattern 20 can chemically react with the carbon nanotubes 111 so that the sub-pattern 11 is only formed on the modified pattern 20.
  • the material of the modification pattern 20 does not undergo condensation reaction with the material of the insulating layer 14, which can prevent the modification pattern 20 from being formed on the surface of the insulating layer 14 facing away from the substrate 10. This prevents the active pattern from being formed in areas other than the area where the groove 141 is located.
  • the material of the modified pattern 20 can also undergo a condensation reaction with the material of the gate insulating layer 16, so that the modified pattern 20 is fixed on the gate insulating layer 16; or, if the thin film If the transistor is a top-gate thin film transistor or a double-gate thin film transistor, the material of the modified pattern 20 can also undergo a condensation reaction with the material of the buffer layer 17 so that the modified pattern 20 is fixed on the buffer layer 17.
  • the material of the modified pattern 20 is an amphoteric coupling agent, such as APTES in a silane coupling agent.
  • the material of the gate insulating layer 16 is SiO x , HfO 2 , or a composite film layer of MgO and HfO 2 .
  • the material of the insulating layer 14 (or buffer layer) is a hydrophobic insulating material, such as SiN x .
  • the thickness of the modification pattern 20 is smaller than the depth of the corresponding groove 141.
  • the thickness of the modification pattern 20 is exactly equal to the depth of the corresponding groove 141.
  • the thickness of the modification pattern 20 is greater than the depth of the corresponding groove 141.

Abstract

Disclosed are a thin film transistor and a preparation method therefor, an array substrate and a display device. The thin film transistor comprises an active pattern, a source electrode and a drain electrode, which are provided on a substrate. The material of the active pattern includes a carbon nano tube. The active pattern includes a plurality of sub-patterns extending along a first direction and arranged at intervals. Along the first direction, one end of each sub-pattern in the active pattern is in contact with the source electrode, and the other end thereof is in contact with the drain electrode.

Description

薄膜晶体管及其制备方法、阵列基板、显示装置Thin film transistor and preparation method thereof, array substrate and display device
本申请要求于2019年4月26日提交的、申请号为201910346336.6的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims the priority of the Chinese patent application with application number 201910346336.6 filed on April 26, 2019, the entire content of which is incorporated into this application by reference.
技术领域Technical field
本公开涉及显示技术领域，尤其涉及一种薄膜晶体管及其制备方法、阵列基板、显示装置。The present disclosure relates to the field of display technology, in particular to a thin film transistor and a preparation method thereof, an array substrate, and a display device.
背景技术Background technique
近年来，用户对高品质的显示面板的需求逐渐提高，进而对薄膜晶体管(Thin-film transistor，简称TFT)的要求也越来越高。目前，薄膜晶体管中的有源层常用低温多晶硅(Low Temperature Poly-silicon，简称LTPS)材料或氧化物半导体材料制作形成。In recent years, users’ demands for high-quality display panels have gradually increased, and the demands on thin-film transistors (TFTs for short) have also become higher. Currently, the active layer in thin film transistors is commonly made of low temperature polysilicon (LTPS) materials or oxide semiconductor materials.
发明内容Summary of the invention
一方面，提供一种薄膜晶体管。所述薄膜晶体管包括设置于衬底上的有源图案、源极和漏极。所述有源图案的材料包括碳纳米管。所述有源图案包括沿第一方向延伸且间隔设置的多个子图案。沿所述第一方向，所述有源图案中的每个所述子图案中的一端与所述源极相接触、另一端与所述漏极相接触。In one aspect, a thin film transistor is provided. The thin film transistor includes an active pattern, a source electrode, and a drain electrode provided on a substrate. The material of the active pattern includes carbon nanotubes. The active pattern includes a plurality of sub-patterns extending along the first direction and arranged at intervals. Along the first direction, one end of each of the sub-patterns in the active pattern is in contact with the source electrode, and the other end is in contact with the drain electrode.
在一些实施例中，所述薄膜晶体管还包括设置于所述衬底与所述有源图案之间的绝缘层。所述绝缘层包括多个凹槽。所述凹槽与所述子图案一一对应，且所述凹槽在所述衬底上的正投影与对应的所述子图案在所述衬底上的正投影重叠。In some embodiments, the thin film transistor further includes an insulating layer disposed between the substrate and the active pattern. The insulating layer includes a plurality of grooves. The grooves correspond to the sub-patterns one-to-one, and the orthographic projection of the grooves on the substrate overlaps the orthographic projection of the corresponding sub-patterns on the substrate.
在一些实施例中，所述子图案填充于对应的所述凹槽中。所述子图案的靠近所述衬底的一侧的表面和与其对应的所述凹槽的底面平齐。In some embodiments, the sub-pattern is filled in the corresponding groove. The surface of the sub-pattern on the side close to the substrate is flush with the bottom surface of the corresponding groove.
在一些实施例中，所述薄膜晶体管还包括填充于每个所述凹槽中的修饰图案。所述有源图案设置于所述修饰图案的背离所述衬底的一侧。所述修饰图案与所述子图案一一对应且直接接触，所述修饰图案在所述衬底上的正投 影和与其对应的所述子图案在所述衬底上正投影重叠。In some embodiments, the thin film transistor further includes a modification pattern filled in each of the grooves. The active pattern is arranged on a side of the modification pattern away from the substrate. The modification pattern corresponds to the sub-pattern in a one-to-one correspondence and is in direct contact, and the orthographic projection of the modification pattern on the substrate overlaps the orthographic projection of the corresponding sub-pattern on the substrate.
在一些实施例中，所述薄膜晶体管为底栅型薄膜晶体管、顶栅型薄膜晶体管或双栅型薄膜晶体管中的一种。所述绝缘层设置于所述有源图案的靠近所述衬底的一侧。所述凹槽未贯通所述绝缘层。In some embodiments, the thin film transistor is one of a bottom gate thin film transistor, a top gate thin film transistor or a double gate thin film transistor. The insulating layer is disposed on a side of the active pattern close to the substrate. The groove does not penetrate the insulating layer.
在一些实施例中，所述薄膜晶体管为底栅型薄膜晶体管；所述薄膜晶体管还包括设置于所述衬底上的栅绝缘层，所述栅绝缘层设置于所述绝缘层的靠近所述衬底的一侧。或者，所述薄膜晶体管为顶栅型薄膜晶体管或双栅型薄膜晶体管；所述薄膜晶体管还包括设置于所述衬底上的缓冲层，所述缓冲层设置于所述绝缘层的靠近所述衬底的一侧。In some embodiments, the thin film transistor is a bottom-gate thin film transistor; the thin film transistor further includes a gate insulating layer disposed on the substrate, and the gate insulating layer is disposed near the insulating layer. One side of the substrate. Alternatively, the thin film transistor is a top gate thin film transistor or a double gate thin film transistor; the thin film transistor further includes a buffer layer disposed on the substrate, and the buffer layer is disposed near the insulating layer. One side of the substrate.
在一些实施例中，所述凹槽贯通所述绝缘层。所述薄膜晶体管为底栅型薄膜晶体管；所述薄膜晶体管还包括设置于所述衬底上的栅绝缘层，所述栅绝缘层设置于所述绝缘层的靠近所述衬底的一侧，所述修饰图案与所述栅绝缘层直接接触。或者，所述薄膜晶体管为顶栅型薄膜晶体管或双栅型薄膜晶体管；所述薄膜晶体管还包括设置于所述衬底上的缓冲层，所述缓冲层设置于所述绝缘层的靠近所述衬底的一侧，所述修饰图案与所述缓冲层直接接触。In some embodiments, the groove penetrates the insulating layer. The thin film transistor is a bottom-gate thin film transistor; the thin film transistor further includes a gate insulating layer disposed on the substrate, and the gate insulating layer is disposed on a side of the insulating layer close to the substrate, The modification pattern directly contacts the gate insulating layer. Alternatively, the thin film transistor is a top gate thin film transistor or a double gate thin film transistor; the thin film transistor further includes a buffer layer disposed on the substrate, and the buffer layer is disposed near the insulating layer. On one side of the substrate, the modified pattern is in direct contact with the buffer layer.
在一些实施例中，所述修饰图案的材料为硅烷偶联剂，所述绝缘层的材料为疏水性绝缘材料。所述底栅型薄膜晶体管中的所述栅绝缘层的材料可与羧基发生缩聚反应；或者，所述顶栅型薄膜晶体管或所述双栅型薄膜晶体管中的所述缓冲层的材料可与羧基发生缩聚反应。In some embodiments, the material of the modified pattern is a silane coupling agent, and the material of the insulating layer is a hydrophobic insulating material. The material of the gate insulating layer in the bottom-gate thin film transistor may undergo a condensation reaction with carboxyl groups; or, the material of the buffer layer in the top-gate thin film transistor or the double-gate thin film transistor may be combined with The carboxyl group undergoes condensation polymerization.
在一些实施例中，所述子图案的横截面的宽度范围为大于或等于500nm、且小于1000nm。所述横截面与所述衬底的厚度方向垂直，所述横截面的宽度与所述第一方向垂直。In some embodiments, the width of the cross section of the sub-pattern is greater than or equal to 500 nm and less than 1000 nm. The cross section is perpendicular to the thickness direction of the substrate, and the width of the cross section is perpendicular to the first direction.
另一方面，提供一种阵列基板。所述阵列基板包括多个像素电路。每个像素电路包括至少一个驱动晶体管。所述至少一个驱动晶体管为如上一些实施例所述的薄膜晶体管。In another aspect, an array substrate is provided. The array substrate includes a plurality of pixel circuits. Each pixel circuit includes at least one driving transistor. The at least one driving transistor is a thin film transistor as described in some embodiments above.
在一些实施例中，所述每个像素电路还包括至少一个开关晶体管。所述至少一个开关晶体管包括氧化物薄膜晶体管或低温多晶硅薄膜晶体管。In some embodiments, each pixel circuit further includes at least one switching transistor. The at least one switching transistor includes an oxide thin film transistor or a low temperature polysilicon thin film transistor.
又一方面，提供了一种显示装置。所述显示装置包括如上一些实施例所述的阵列基板。In yet another aspect, a display device is provided. The display device includes the array substrate as described in some of the above embodiments.
又一方面，提供了一种薄膜晶体管的制备方法。所述薄膜晶体管的制备方法包括：In another aspect, a method for manufacturing a thin film transistor is provided. The manufacturing method of the thin film transistor includes:
在衬底上形成绝缘薄膜，在所述绝缘薄膜中形成多个沿第一方向延伸且间隔设置的凹槽，得到绝缘层。An insulating film is formed on the substrate, and a plurality of grooves extending along the first direction and arranged at intervals are formed in the insulating film to obtain an insulating layer.
在所述绝缘层的背离所述衬底的一侧形成包括碳纳米管的有源图案；所述有源图案包括间隔设置的多个子图案，所述子图案与所述凹槽一一对应，且所述子图案在所述衬底上的正投影和与其对应的所述凹槽在所述衬底上的正投影重叠。An active pattern including carbon nanotubes is formed on the side of the insulating layer away from the substrate; the active pattern includes a plurality of sub-patterns arranged at intervals, and the sub-patterns correspond to the grooves one-to-one, And the orthographic projection of the sub-pattern on the substrate overlaps the orthographic projection of the corresponding groove on the substrate.
在所述有源图案的背离所述衬底的一侧分别形成源极和漏极，沿所述第一方向，所述有源图案中的每个子图案中的一端与所述源极相接触、另一端与所述漏极相接触。A source and a drain are respectively formed on the side of the active pattern away from the substrate, and along the first direction, one end of each sub-pattern in the active pattern is in contact with the source The other end is in contact with the drain.
在一些实施例中，在形成所述绝缘层之后，形成所述有源图案之前，所述薄膜晶体管的制备方法还包括：向每个所述凹槽中填充修饰图案。形成所述有源图案还包括：在所述修饰图案的背离所述衬底的表面上形成对应的所述子图案，所述修饰图案在所述衬底上的正投影和与其对应的所述子图案在所述衬底上正投影重叠。In some embodiments, after forming the insulating layer and before forming the active pattern, the method for manufacturing the thin film transistor further includes: filling each of the grooves with a modified pattern. Forming the active pattern further includes: forming the corresponding sub-pattern on the surface of the modified pattern facing away from the substrate, the orthographic projection of the modified pattern on the substrate and the corresponding sub-pattern The sub-patterns overlap in orthographic projection on the substrate.
在一些实施例中，所述凹槽贯通所述绝缘层。所述薄膜晶体管为底栅型薄膜晶体管；在形成所述绝缘层之前，所述薄膜晶体管的制备方法还包括在衬底上形成栅绝缘层；所述修饰图案与所述栅绝缘层直接接触。或者，所述薄膜晶体管为顶栅型薄膜晶体管或双栅型薄膜晶体管；在形成所述绝缘层之前，所述薄膜晶体管的制备方法还包括在衬底上形成缓冲层；所述修饰图案与所述缓冲层直接接触。In some embodiments, the groove penetrates the insulating layer. The thin film transistor is a bottom-gate thin film transistor; before forming the insulating layer, the method for preparing the thin film transistor further includes forming a gate insulating layer on a substrate; the modified pattern is in direct contact with the gate insulating layer. Alternatively, the thin film transistor is a top-gate thin film transistor or a double-gate thin film transistor; before forming the insulating layer, the method for preparing the thin film transistor further includes forming a buffer layer on a substrate; the modified pattern and the The buffer layer is in direct contact.
附图说明Description of the drawings
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图 仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。In order to explain the technical solutions of the present disclosure more clearly, the following will briefly introduce the drawings that need to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are merely appendices to some embodiments of the present disclosure. Figures, for those of ordinary skill in the art, other drawings can be obtained based on these drawings. In addition, the drawings in the following description may be regarded as schematic diagrams, and are not limitations on the actual size of the products involved in the embodiments of the present disclosure, the actual process of the method, and the actual timing of the signals.
图1为根据本公开一些实施例中的一种显示装置的结构示意图；FIG. 1 is a schematic structural diagram of a display device according to some embodiments of the present disclosure;
图2为根据本公开一些实施例中的一种薄膜晶体管的俯视示意图；FIG. 2 is a schematic top view of a thin film transistor according to some embodiments of the present disclosure;
图3为图2中所示薄膜晶体管的一种A-A1向的剖视示意图；3 is a schematic cross-sectional view of the thin film transistor shown in FIG. 2 taken along the A-A1 direction;
图4为根据本公开一些实施例中的一种薄膜晶体管的结构示意图；FIG. 4 is a schematic structural diagram of a thin film transistor according to some embodiments of the present disclosure;
图5为根据本公开一些实施例中的另一种薄膜晶体管的结构示意图；FIG. 5 is a schematic structural diagram of another thin film transistor in some embodiments of the present disclosure;
图6为根据本公开一些实施例中的又一种薄膜晶体管的结构示意图；FIG. 6 is a schematic structural diagram of yet another thin film transistor in some embodiments of the present disclosure;
图7为根据本公开一些实施例中的又一种薄膜晶体管的结构示意图；FIG. 7 is a schematic structural diagram of yet another thin film transistor in some embodiments of the present disclosure;
图8a为相关技术中的一种碳纳米管的排布示意图；Fig. 8a is a schematic diagram of the arrangement of a carbon nanotube in the related art;
图8b为根据本公开一些实施例中的一种碳纳米管的排布示意图；Fig. 8b is a schematic diagram of an arrangement of carbon nanotubes according to some embodiments of the present disclosure;
图9为根据本公开一些实施例中的一种绝缘层的结构示意图；FIG. 9 is a schematic structural diagram of an insulating layer in some embodiments according to the present disclosure;
图10为根据本公开一些实施例中的又一种薄膜晶体管的结构示意图；FIG. 10 is a schematic structural diagram of yet another thin film transistor in some embodiments of the present disclosure;
图11为根据本公开一些实施例中的又一种薄膜晶体管的结构示意图；FIG. 11 is a schematic structural diagram of yet another thin film transistor in some embodiments of the present disclosure;
图12为根据本公开一些实施例中的又一种薄膜晶体管的结构示意图；FIG. 12 is a schematic structural diagram of another thin film transistor according to some embodiments of the present disclosure;
图13为根据本公开一些实施例中的一种阵列基板的结构示意图；FIG. 13 is a schematic structural diagram of an array substrate according to some embodiments of the present disclosure;
图14为根据本公开一些实施例中的另一种阵列基板的结构示意图；FIG. 14 is a schematic structural diagram of another array substrate according to some embodiments of the present disclosure;
图15为根据本公开一些实施例中的又一种阵列基板的结构示意图；FIG. 15 is a schematic structural diagram of another array substrate according to some embodiments of the present disclosure;
图16为根据本公开一些实施例中的一种薄膜晶体管的制备方法的 流程示意图；Fig. 16 is a schematic flow chart of a method for manufacturing a thin film transistor in some embodiments of the present disclosure;
图17为根据本公开一些实施例中的一种薄膜晶体管的制备过程示意图。FIG. 17 is a schematic diagram of a manufacturing process of a thin film transistor in some embodiments of the present disclosure.
具体实施方式Detailed ways
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。The technical solutions in some embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art fall within the protection scope of the present disclosure.
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms such as the third-person singular form "comprises" and the present participle form "comprising" are Interpreted as open and inclusive means "including, but not limited to." In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" "example)" or "some examples" are intended to indicate that a specific feature, structure, material, or characteristic related to the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any suitable manner.
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。Hereinafter, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以 上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。In describing some embodiments, the expressions "coupled" and "connected" and their extensions may be used. For example, the term "connected" may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. As another example, the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。"At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。"A and/or B" includes the following three combinations: A only, B only, and the combination of A and B.
显示装置可以用作手机、平板电脑、个人数字助理(personal digital assistant，PDA)、车载电脑等，本公开一些实施例对显示装置的应用不做限制。The display device can be used as a mobile phone, a tablet computer, a personal digital assistant (PDA), a vehicle-mounted computer, etc. Some embodiments of the present disclosure do not limit the application of the display device.
在一些实施例中，如图1所示，该显示装置例如可以包括框架1、显示面板2、电路板3、盖板4、以及包括摄像头等在内的其他电子配件(图中未视出)。In some embodiments, as shown in FIG. 1, the display device may include, for example, a frame 1, a display panel 2, a circuit board 3, a cover 4, and other electronic accessories (not shown in the figure) including a camera. .
以上述显示面板2的出光方向为顶发光为例，框架1为U形框架，显示面板2和电路板3设置于框架1中。盖板4设置于显示面板2的出光侧，盖板4为透光盖板，例如玻璃盖板。电路板3设置于显示面板2的背离盖板4的一侧，并与显示面板2电连接，配置为控制显示面板2的显示。Taking the light emitting direction of the above display panel 2 as top-emitting as an example, the frame 1 is a U-shaped frame, and the display panel 2 and the circuit board 3 are arranged in the frame 1. The cover plate 4 is arranged on the light emitting side of the display panel 2, and the cover plate 4 is a transparent cover plate, such as a glass cover plate. The circuit board 3 is arranged on the side of the display panel 2 facing away from the cover 4 and is electrically connected to the display panel 2 to control the display of the display panel 2.
上述显示面板2可以是有机电致(organic light emitting diode，简称OLED)显示面板，或发光二极管(light emitting diode，简称LED)显示面板，或量子点电致(Quantum Dot Light Emitting Diodes，简称QLED)显示面板，或液晶显示面板。示例的，上述显示面板2为液晶显示面板，该液晶显示面板至少包括阵列基板21和对置基板22。The above-mentioned display panel 2 may be an organic light emitting diode (OLED for short) display panel, or a light emitting diode (light emitting diode, LED for short) display panel, or Quantum Dot Light Emitting Diodes (QLED for short) Display panel, or liquid crystal display panel. For example, the above-mentioned display panel 2 is a liquid crystal display panel, and the liquid crystal display panel includes at least an array substrate 21 and a counter substrate 22.
在一些实施例中，显示面板2包括阵列基板21。阵列基板21包括多个像素，其中每个像素包括像素电路。各像素电路分别包括至少一个薄膜晶体管。In some embodiments, the display panel 2 includes an array substrate 21. The array substrate 21 includes a plurality of pixels, where each pixel includes a pixel circuit. Each pixel circuit includes at least one thin film transistor.
本公开实施例提供一种薄膜晶体管，该薄膜晶体管可以用作上述阵列基板21中的薄膜晶体管。当然，该薄膜晶体管还可以用于显示装置的 其他电路结构，例如其他基板，本公开实施例不作限定。The embodiment of the present disclosure provides a thin film transistor, which can be used as the thin film transistor in the above-mentioned array substrate 21. Of course, the thin film transistor can also be used in other circuit structures of the display device, such as other substrates, which are not limited in the embodiment of the present disclosure.
如图2和图3、图17所示，该薄膜晶体管包括设置于衬底10上的有源图案、源极12和漏极13。有源图案的材料包括碳纳米管。有源图案包括沿第一方向延伸且间隔设置的多个子图案11。沿第一方向，有源图案中的每个子图案11中的一端与源极12相接触、另一端与漏极13相接触。As shown in FIGS. 2, 3 and 17, the thin film transistor includes an active pattern, a source electrode 12 and a drain electrode 13 arranged on a substrate 10. The material of the active pattern includes carbon nanotubes. The active pattern includes a plurality of sub-patterns 11 extending along the first direction and arranged at intervals. Along the first direction, one end of each sub-pattern 11 in the active pattern is in contact with the source electrode 12 and the other end is in contact with the drain electrode 13.
此处，由于各子图案11沿第一方向延伸，且沿第一方向，有源图案中的每个子图案11中的一端与源极12相接触、另一端与漏极13相接触。因此，第一方向为源极12指向漏极13的方向，也即源极12与漏极13之间的导电沟道延伸方向的平行方向。Here, since each sub-pattern 11 extends along the first direction and along the first direction, one end of each sub-pattern 11 in the active pattern is in contact with the source electrode 12 and the other end is in contact with the drain electrode 13. Therefore, the first direction is the direction in which the source 12 points to the drain 13, that is, the direction parallel to the extending direction of the conductive channel between the source 12 and the drain 13.
此外，沿第一方向，每个子图案11具有相对的两端，因此，子图案11的一端与源极12相接触、另一端与漏极13相接触是清楚且唯一的。In addition, along the first direction, each sub-pattern 11 has opposite ends. Therefore, it is clear and unique that one end of the sub-pattern 11 is in contact with the source 12 and the other end is in contact with the drain 13.
在一些实施例中，上述的薄膜晶体管还包括设置于衬底10与有源图案之间的绝缘层14。绝缘层14包括多个凹槽141，凹槽141与子图案11一一对应，且凹槽141在衬底10上的正投影与子图案11在衬底10上的正投影完全重叠。In some embodiments, the above-mentioned thin film transistor further includes an insulating layer 14 disposed between the substrate 10 and the active pattern. The insulating layer 14 includes a plurality of grooves 141, and the grooves 141 correspond to the sub-pattern 11 one-to-one, and the orthographic projection of the groove 141 on the substrate 10 and the orthographic projection of the sub-pattern 11 on the substrate 10 completely overlap.
上述薄膜晶体管的结构可以有多种选择，例如：薄膜晶体管是底栅型薄膜晶体管、顶栅型薄膜晶体管或双栅型薄膜晶体管中的一种。上述绝缘层14用于绝缘，其在不同类型的薄膜晶体管中可以独立于栅绝缘层或缓冲层等其他膜层存在，或，共用为栅绝缘层或缓冲层等其他膜层。There are many options for the structure of the above-mentioned thin film transistor. For example, the thin film transistor is one of a bottom-gate thin film transistor, a top-gate thin film transistor, or a double-gate thin film transistor. The above-mentioned insulating layer 14 is used for insulation, and it can exist independently of other film layers such as a gate insulating layer or a buffer layer in different types of thin film transistors, or can be shared as other film layers such as a gate insulating layer or a buffer layer.
在一些实施例中，如图4和图5所示，薄膜晶体管为底栅型薄膜晶体管，也即栅极15位于有源图案的靠近衬底10的一侧。可选的，如图4所示，绝缘层14共用为栅绝缘层16。或者，如图5所示，绝缘层14独立于栅绝缘层16存在，该底栅型薄膜晶体管还包括设置于栅极15与有源图案之间的栅绝缘层16。栅绝缘层16设置于绝缘层14的靠近衬底10的一侧。In some embodiments, as shown in FIGS. 4 and 5, the thin film transistor is a bottom-gate thin film transistor, that is, the gate 15 is located on the side of the active pattern close to the substrate 10. Optionally, as shown in FIG. 4, the insulating layer 14 is shared as the gate insulating layer 16. Alternatively, as shown in FIG. 5, the insulating layer 14 exists independently of the gate insulating layer 16, and the bottom-gate thin film transistor further includes a gate insulating layer 16 disposed between the gate 15 and the active pattern. The gate insulating layer 16 is disposed on the side of the insulating layer 14 close to the substrate 10.
此外，该底栅型薄膜晶体管还可以包括设置于衬底10与栅极15之 间的缓冲层17。In addition, the bottom-gate thin film transistor may further include a buffer layer 17 disposed between the substrate 10 and the gate 15.
在另一些实施例中，如图6所示，薄膜晶体管为顶栅型薄膜晶体管，也即栅极15位于有源图案的背离衬底10的一侧。该顶栅型薄膜晶体管还包括设置于有源图案和栅极15之间的栅绝缘层16、以及设置于栅极15与源极12、漏极13之间的层间绝缘层18。源极12和漏极13分别穿过层间绝缘层18、栅绝缘层16二者上的对应过孔与有源图案相接触，也即电连接。In other embodiments, as shown in FIG. 6, the thin film transistor is a top-gate thin film transistor, that is, the gate 15 is located on the side of the active pattern away from the substrate 10. The top-gate thin film transistor further includes a gate insulating layer 16 arranged between the active pattern and the gate 15 and an interlayer insulating layer 18 arranged between the gate 15 and the source 12 and the drain 13. The source electrode 12 and the drain electrode 13 respectively pass through corresponding via holes on the interlayer insulating layer 18 and the gate insulating layer 16 to contact the active pattern, that is, to be electrically connected.
可选的，在该顶栅型薄膜晶体管中，如图6所示，绝缘层14共用为缓冲层17。或者，绝缘层14独立于缓冲层17存在，该顶栅型薄膜晶体管还包括设置于绝缘层14与衬底10之间的缓冲层17。Optionally, in the top-gate thin film transistor, as shown in FIG. 6, the insulating layer 14 is shared as the buffer layer 17. Alternatively, the insulating layer 14 exists independently of the buffer layer 17, and the top-gate thin film transistor further includes a buffer layer 17 disposed between the insulating layer 14 and the substrate 10.
在又一些实施例中，如图7所示，薄膜晶体管为双栅型薄膜晶体管，也即薄膜晶体管包括栅极15以及与栅极15对应电连接的辅栅电极19，所述栅极15以及辅栅电极19分别位于有源图案的背离衬底10的一侧。该双栅型薄膜晶体管还包括设置于有源图案和栅极15之间的栅绝缘层16、以及设置于栅极15与辅栅电极19、源极12、漏极13三者之间的层间绝缘层18。栅绝缘层16、栅极15、以及层间绝缘层18位于源极12和漏极13二者的靠近衬底10的一侧，源极12和漏极13分别穿过层间绝缘层18、栅绝缘层16二者上的对应过孔与有源图案相接触。辅栅极19设置于层间绝缘层18的背离衬底10的一侧，并穿过层间绝缘层18上的对应过孔与栅极15电连接。In still other embodiments, as shown in FIG. 7, the thin film transistor is a double-gate thin film transistor, that is, the thin film transistor includes a gate 15 and an auxiliary gate electrode 19 electrically connected to the gate 15, the gate 15 and The auxiliary gate electrodes 19 are respectively located on the side of the active pattern away from the substrate 10. The double-gate thin film transistor also includes a gate insulating layer 16 disposed between the active pattern and the gate 15 and a layer disposed between the gate 15 and the auxiliary gate electrode 19, the source electrode 12, and the drain electrode 13. Between insulating layer 18. The gate insulating layer 16, the gate 15 and the interlayer insulating layer 18 are located on the side of the source 12 and the drain 13 close to the substrate 10. The source 12 and the drain 13 respectively pass through the interlayer insulating layer 18, The corresponding via holes on both the gate insulating layer 16 are in contact with the active pattern. The auxiliary gate 19 is disposed on a side of the interlayer insulating layer 18 away from the substrate 10, and is electrically connected to the gate 15 through corresponding via holes on the interlayer insulating layer 18.
可选的，在该双栅型薄膜晶体管中，如图7所示，绝缘层14独立于缓冲层17存在，该双栅型薄膜晶体管还包括设置于绝缘层14与衬底10之间的缓冲层17。或者，绝缘层14共用为缓冲层17。Optionally, in the double-gate thin film transistor, as shown in FIG. 7, the insulating layer 14 exists independently of the buffer layer 17, and the double-gate thin film transistor further includes a buffer disposed between the insulating layer 14 and the substrate 10. Layer 17. Alternatively, the insulating layer 14 is shared as the buffer layer 17.
需要说明的是，由于本公开实施例中的碳纳米管用于制作有源图案，因此，本公开实施例所采用的碳纳米管为半导体型碳纳米管。此处，碳纳米管原材料包括金属型碳纳米管和半导体型碳纳米管。本公开实施例可以采用离心等方式去除碳纳米管原材料中的金属型碳纳米管，以得到 所述半导体型碳纳米管。It should be noted that, since the carbon nanotubes in the embodiments of the present disclosure are used to make active patterns, the carbon nanotubes used in the embodiments of the present disclosure are semiconductor-type carbon nanotubes. Here, the carbon nanotube raw materials include metallic carbon nanotubes and semiconductor carbon nanotubes. In the embodiments of the present disclosure, the metallic carbon nanotubes in the carbon nanotube raw materials can be removed by centrifugation or the like to obtain the semiconductor carbon nanotubes.
示例的，采用离心的方式去除碳纳米管原材料中的金属型碳纳米管。先在碳纳米管原材料中添加聚合物，并采用超声分散方式将碳纳米管中的多个半导体型碳纳米管、以及金属型碳纳米管分散成独立的个体。这样聚合物与半导体型碳纳米管反应，并包裹在半导体型碳纳米管的表面，可以避免任意一个半导体型碳纳米管与金属型碳纳米管和其他半导体型碳纳米管接触。然后，再根据半导体型碳纳米管与金属型碳纳米管的密度差异，便可采用离心工艺分离出半导体型碳纳米管。For example, a centrifugal method is used to remove metallic carbon nanotubes from the carbon nanotube raw material. First, a polymer is added to the carbon nanotube raw materials, and a plurality of semiconducting carbon nanotubes and metallic carbon nanotubes in the carbon nanotubes are dispersed into independent individuals by ultrasonic dispersion. In this way, the polymer reacts with the semiconducting carbon nanotube and wraps it on the surface of the semiconducting carbon nanotube, which can prevent any semiconducting carbon nanotube from contacting with the metal carbon nanotube and other semiconducting carbon nanotubes. Then, according to the density difference between the semiconductor carbon nanotubes and the metallic carbon nanotubes, the semiconductor carbon nanotubes can be separated by a centrifugal process.
在此基础上，还可以去除半导体型碳纳米管表面的聚合物，例如可以利用溶剂将半导体型碳纳米管表面的聚合物溶解去除。On this basis, the polymer on the surface of the semiconductor carbon nanotube can also be removed. For example, the polymer on the surface of the semiconductor carbon nanotube can be dissolved and removed by using a solvent.
本公开一些实施例不对有源图案中子图案11的个数进行限定。有源图案中子图案11的个数，与源极12和漏极13的尺寸、以及每个子图案11的横截面的宽度有关。此处，子图案11的横截面为沿其垂直于衬底10厚度方向的截面，且子图案11的横截面的宽度与第一方向垂直。Some embodiments of the present disclosure do not limit the number of sub-patterns 11 in the active pattern. The number of sub-patterns 11 in the active pattern is related to the size of the source electrode 12 and the drain electrode 13 and the width of the cross section of each sub-pattern 11. Here, the cross-section of the sub-pattern 11 is a cross-section along the thickness direction perpendicular to the substrate 10, and the width of the cross-section of the sub-pattern 11 is perpendicular to the first direction.
可选的，有源图案中的多个子图案11的尺寸可以相同也可以不相同。Optionally, the sizes of the multiple sub-patterns 11 in the active pattern may be the same or different.
可选的，碳纳米管的形状近似可看作圆柱体。碳纳米管的直径(圆柱体的底面的直径)约为1nm、长度(圆柱体的高)约为1000nm。Optionally, the shape of the carbon nanotube can be approximately regarded as a cylinder. The diameter of the carbon nanotube (the diameter of the bottom surface of the cylinder) is about 1 nm, and the length (the height of the cylinder) is about 1000 nm.
本公开实施例不对多个子图案11的横截面的宽度范围进行限定。每个子图案11的横截面的宽度应至少大于或等于一个碳纳米管的直径的尺寸，且小于碳纳米管的长度尺寸，以利于实现多根碳纳米管的顺序排列。示例的，子图案11的横截面的宽度范围为大于等于1nm、且小于1000nm。The embodiment of the present disclosure does not limit the width range of the cross section of the plurality of sub-patterns 11. The width of the cross section of each sub-pattern 11 should be at least greater than or equal to the diameter of one carbon nanotube, and less than the length of the carbon nanotube, so as to facilitate the sequential arrangement of multiple carbon nanotubes. For example, the width range of the cross section of the sub-pattern 11 is greater than or equal to 1 nm and less than 1000 nm.
可选的，如图8b所示，子图案11的横截面的宽度W范围为大于或等于500nm、且小于1000nm。Optionally, as shown in FIG. 8b, the width W of the cross section of the sub-pattern 11 is greater than or equal to 500 nm and less than 1000 nm.
示例的，子图案11的横截面的宽度为500nm、655nm或1000nm。For example, the width of the cross section of the sub-pattern 11 is 500 nm, 655 nm, or 1000 nm.
由于碳纳米管111的直径约为1nm、长度约为1000nm，因此，碳纳 米管111的长度比其直径大得多。Since the diameter of the carbon nanotube 111 is about 1 nm and the length is about 1000 nm, the length of the carbon nanotube 111 is much larger than its diameter.
基于此，本公开实施例中，由于碳纳米管111的长度比其直径大得多，因此，子图案11的横截面的宽度越小，每根碳纳米管111与第一方向之间的夹角越小。本公开实施例通过将碳纳米管111限定在宽度范围为大于或等于500nm、且小于1000nm的区域内，以使得每根碳纳米管111与第一方向之间的夹角均较小，进而多个碳纳米管111之间的夹角可忽略不计，从而提高薄膜晶体管的迁移率。Based on this, in the embodiments of the present disclosure, since the length of the carbon nanotube 111 is much larger than its diameter, the smaller the width of the cross section of the sub-pattern 11 is, the smaller the width between each carbon nanotube 111 and the first direction is The smaller the angle. In the embodiment of the present disclosure, the carbon nanotube 111 is limited to a region with a width greater than or equal to 500 nm and less than 1000 nm, so that the angle between each carbon nanotube 111 and the first direction is small, and more The angle between the two carbon nanotubes 111 is negligible, thereby improving the mobility of the thin film transistor.
此外，本公开实施例不对子图案11沿第一方向的尺寸进行限定，子图案11沿第一方向的尺寸与源极12和漏极13之间的间距、以及碳纳米管的尺寸有关。In addition, the embodiment of the present disclosure does not limit the size of the sub-pattern 11 along the first direction, and the size of the sub-pattern 11 along the first direction is related to the distance between the source 12 and the drain 13 and the size of the carbon nanotubes.
在本公开一些实施例中，有源图案中的多个子图案11的形状相同或相似，所述形状包括条形。这样不仅方便于在每个子图案11中实现碳纳米管的顺序排列，也有利于实现有源图案中各子图案11的整齐排列，从而确保有源图案的电学性能稳定。In some embodiments of the present disclosure, the shapes of the multiple sub-patterns 11 in the active pattern are the same or similar, and the shapes include bar shapes. This not only facilitates the sequential arrangement of the carbon nanotubes in each sub-pattern 11, but also facilitates the neat arrangement of the sub-patterns 11 in the active pattern, thereby ensuring stable electrical performance of the active pattern.
当然，各子图案11的形状并不仅限于条形，其他方便制作、且有利于实现碳纳米管顺序排列以及各子图案11整齐排列的形状也均可。Of course, the shape of each sub-pattern 11 is not limited to a stripe shape, and other shapes that are convenient for manufacturing and facilitate the sequential arrangement of carbon nanotubes and the neat arrangement of the sub-patterns 11 are also acceptable.
在一些实施例中，源极12和漏极13的材料包括钼(Mo)、铜(Cu)、钼铌合金(MoNb)、铝(Al)等金属材料。在另一些实施例中，源极12和漏极13的材料包括氧化铟锡(Indium tin oxide，简称ITO)等等透明导电材料。In some embodiments, the material of the source electrode 12 and the drain electrode 13 includes metal materials such as molybdenum (Mo), copper (Cu), molybdenum-niobium alloy (MoNb), and aluminum (Al). In other embodiments, the material of the source electrode 12 and the drain electrode 13 includes transparent conductive materials such as indium tin oxide (ITO).
类似的，在一些实施例中，栅极15的材料包括Mo、Cu、MoNb、Al等金属材料。在另一些实施例中，栅极15的材料包括ITO等等透明导电材料。Similarly, in some embodiments, the material of the gate 15 includes metal materials such as Mo, Cu, MoNb, and Al. In other embodiments, the material of the gate 15 includes transparent conductive materials such as ITO.
此外，源极12、漏极13、以及栅极15可以是单层结构，也可以是多层结构。例如，源极12、漏极13、栅极15包括一层金属层，且材料为铜；或者，源极12、漏极13、栅极15包括层叠设置的两层金属层，其中一层金属层的材料为铬(Cr)，另一层金属层的材料为金(Au)。In addition, the source electrode 12, the drain electrode 13, and the gate electrode 15 may have a single-layer structure or a multilayer structure. For example, the source electrode 12, the drain electrode 13, and the gate electrode 15 include a metal layer, and the material is copper; or, the source electrode 12, the drain electrode 13, and the gate electrode 15 include two stacked metal layers, one of which is a metal layer. The material of the layer is chromium (Cr), and the material of the other metal layer is gold (Au).
相关技术中，如图8a所示，碳纳米管111通常呈无序排列。若采用碳纳米管制得的有源图案中的多个碳纳米管111无序排列，容易使得薄膜晶体管的迁移率较低。In the related art, as shown in FIG. 8a, the carbon nanotubes 111 are usually arranged in disorder. If a plurality of carbon nanotubes 111 in the active pattern obtained by using carbon nanotubes are arranged disorderly, the mobility of the thin film transistor is likely to be lower.
在本公开实施例提供的薄膜晶体管中，有源图案包括间隔设置的多个子图案11，以使得每个子图案11包括一个或多个碳纳米管111。这样每个子图案11中的碳纳米管111被限定在该子图案11所在的区域内，可以使得一个子图案11中的碳纳米管111的排列受限。相较于多个碳纳米管111无序排列在整个有源图案所在的区域，本公开实施例的每个子图案11所在的区域小得多，因此，相较于多个碳纳米管111在整个有源图案所在的区域沿任意方向排列，本公开实施例的碳纳米管111的延伸方向与第一方向之间的夹角均较小(如图8b所示)，进而多个碳纳米管111之间的夹角可忽略不计，也即可以使得多个碳纳米管111整体呈规则排列，从而可改善因有源图案中多个碳纳米管111不规则排列而导致的薄膜晶体管的迁移率低的问题。In the thin film transistor provided by the embodiment of the present disclosure, the active pattern includes a plurality of sub-patterns 11 arranged at intervals, so that each sub-pattern 11 includes one or more carbon nanotubes 111. In this way, the carbon nanotubes 111 in each sub-pattern 11 are limited to the area where the sub-pattern 11 is located, which can limit the arrangement of the carbon nanotubes 111 in one sub-pattern 11. Compared with a plurality of carbon nanotubes 111 arranged disorderly in the area where the entire active pattern is located, the area where each sub-pattern 11 is located in the embodiment of the present disclosure is much smaller. The regions where the active patterns are located are arranged in any direction, and the angle between the extending direction of the carbon nanotubes 111 and the first direction in the embodiment of the present disclosure is small (as shown in FIG. 8b), and then a plurality of carbon nanotubes 111 The angle between them is negligible, that is, the multiple carbon nanotubes 111 can be arranged regularly, which can improve the low mobility of the thin film transistor caused by the irregular arrangement of the multiple carbon nanotubes 111 in the active pattern. The problem.
此外，上述有源图案中各子图案11在凹槽141中的设置方式可以有多种。In addition, there may be multiple ways of disposing each sub-pattern 11 in the groove 141 in the above-mentioned active pattern.
可选的，如图4-图7所示，子图案11的靠近衬底10一侧的表面和与其对应的凹槽141的底面平齐。即，子图案11直接形成在与其对应的凹槽141中。此处，凹槽141的底面，即，凹槽141中靠近衬底10的面。Optionally, as shown in FIGS. 4-7, the surface of the sub-pattern 11 on the side close to the substrate 10 is flush with the bottom surface of the corresponding groove 141. That is, the sub-pattern 11 is directly formed in the groove 141 corresponding thereto. Here, the bottom surface of the groove 141, that is, the surface of the groove 141 close to the substrate 10.
可选的，如图4和图6所示，子图案11的厚度恰好等于与其对应的凹槽141的深度。或者，如图5和图7所示，子图案11的厚度小于与其对应的凹槽141的深度。或者，子图案11的背离衬底10的表面与衬底10之间的距离大于绝缘层14的背离衬底10的表面与衬底10之间的距离。Optionally, as shown in FIGS. 4 and 6, the thickness of the sub-pattern 11 is exactly equal to the depth of the corresponding groove 141. Alternatively, as shown in FIGS. 5 and 7, the thickness of the sub-pattern 11 is smaller than the depth of the corresponding groove 141. Alternatively, the distance between the surface of the sub-pattern 11 facing away from the substrate 10 and the substrate 10 is greater than the distance between the surface of the insulating layer 14 facing away from the substrate 10 and the substrate 10.
本公开实施例中，可先在衬底10上形成具有凹槽141的绝缘层14；之后，再在凹槽141中直接形成子图案11，以得到间隔设置的多个子图案11。In the embodiment of the present disclosure, the insulating layer 14 having the groove 141 may be formed on the substrate 10 first; then, the sub-pattern 11 is directly formed in the groove 141 to obtain a plurality of sub-patterns 11 arranged at intervals.
此外，在一些实施例中，如图10-图12所示，凹槽141中还设置有其他结构，例如薄膜晶体管还包括填充于每个凹槽141中的修饰图案20。修饰图案20设置于有源图案的靠近衬底10一侧。修饰图案20与有源图案中的各子图案11一一对应且直接接触。修饰图案20在衬底10上的正投影和与其对应的子图案11在衬底10上正投影重叠。In addition, in some embodiments, as shown in FIG. 10 to FIG. 12, other structures are also provided in the grooves 141. For example, the thin film transistor further includes a modification pattern 20 filled in each groove 141. The modification pattern 20 is disposed on the side of the active pattern close to the substrate 10. The modified pattern 20 has a one-to-one correspondence with each sub-pattern 11 in the active pattern and directly contacts. The orthographic projection of the modified pattern 20 on the substrate 10 and the orthographic projection of the corresponding sub-pattern 11 on the substrate 10 overlap.
可选的，修饰图案20的材料根据实际需求选择设置。一方面，修饰图案20的材料可以与碳纳米管111发生化学反应，例如化学吸附，以使得子图案11仅形成于修饰图案20上。另一方面，在凹槽141贯通绝缘层14的情况下，修饰图案20的材料不与绝缘层14的材料发生缩聚反应，以避免修饰图案20形成在绝缘层14的背离衬底10一侧表面上，进而避免有源图案形成在除凹槽141所在的区域以外的区域。Optionally, the material of the decoration pattern 20 is selected and set according to actual needs. On the one hand, the material of the modified pattern 20 may chemically react with the carbon nanotube 111, such as chemical adsorption, so that the sub-pattern 11 is only formed on the modified pattern 20. On the other hand, when the groove 141 penetrates the insulating layer 14, the material of the modification pattern 20 does not undergo a condensation reaction with the material of the insulating layer 14, so as to prevent the modification pattern 20 from being formed on the surface of the insulating layer 14 facing away from the substrate 10. This prevents the active pattern from being formed in areas other than the area where the groove 141 is located.
可选的，如图10所示，修饰图案20的厚度小于与其对应的凹槽141的深度。在修饰图案20与子图案11的厚度之和大于与其对应的凹槽141的深度的情况下，子图案11中的一部分填充于与其对应的凹槽141中，另一部分高出绝缘层14的远离衬底10的表面。在修饰图案20与子图案11的厚度之和小于或等于与其对应的凹槽141的深度的情况下，子图案11完全填充于与其对应的凹槽141中。Optionally, as shown in FIG. 10, the thickness of the modification pattern 20 is smaller than the depth of the corresponding groove 141. In the case where the sum of the thickness of the modified pattern 20 and the sub-pattern 11 is greater than the depth of the corresponding groove 141, a part of the sub-pattern 11 is filled in the corresponding groove 141, and the other part is higher than the distance of the insulating layer 14. The surface of the substrate 10. When the sum of the thickness of the modified pattern 20 and the sub-pattern 11 is less than or equal to the depth of the corresponding groove 141, the sub-pattern 11 is completely filled in the corresponding groove 141.
或者，如图11和图12所示，修饰图案20的厚度恰好等于与其对应的凹槽141的深度，子图案11全部高出绝缘层14的远离衬底10的表面。Alternatively, as shown in FIGS. 11 and 12, the thickness of the modified pattern 20 is exactly equal to the depth of the corresponding groove 141, and all the sub-patterns 11 are higher than the surface of the insulating layer 14 away from the substrate 10.
或者，修饰图案20的厚度大于与其对应的凹槽141的深度。Or, the thickness of the modification pattern 20 is greater than the depth of the corresponding groove 141.
对于上述，凹槽141可以贯通绝缘层14，也可以不贯通绝缘层14。子图案11的厚度方向、修饰图案20的厚度方向、以及凹槽141的深度方向均与衬底10的厚度方向平行。凹槽141在各个位置处的深度可以相同，也可以不相同。本公开实施例以凹槽141的最大深度与子图案11的最大厚度或修饰图案20的最大厚度进行比较。For the above, the groove 141 may penetrate through the insulating layer 14 or not through the insulating layer 14. The thickness direction of the sub-pattern 11, the thickness direction of the modification pattern 20, and the depth direction of the groove 141 are all parallel to the thickness direction of the substrate 10. The depth of the groove 141 at each position may be the same or different. The embodiment of the present disclosure compares the maximum depth of the groove 141 with the maximum thickness of the sub-pattern 11 or the maximum thickness of the modification pattern 20.
本公开实施例中，先在凹槽141中形成修饰图案20，再在修饰图案20的背离衬底10的一侧形成子图案11。在修饰图案20的材料不与绝缘 层14的材料发生缩聚反应的情况下，修饰图案20能够仅形成于凹槽141中。由于修饰图案20的材料可以与碳纳米管111发生化学反应，因此，修饰图案20可以将碳纳米管111牢牢地吸附固定住，从而使得子图案11仅形成于修饰图案20上。最终得到的有源图案中的多个子图案11相互间隔设置，且每个子图案11在衬底10上的正投影和与其对应的凹槽141在衬底10上的正投影恰好完全重叠。In the embodiment of the present disclosure, the modification pattern 20 is formed in the groove 141 first, and then the sub-pattern 11 is formed on the side of the modification pattern 20 facing away from the substrate 10. In the case where the material of the modification pattern 20 does not undergo a condensation reaction with the material of the insulating layer 14, the modification pattern 20 can be formed only in the groove 141. Since the material of the modified pattern 20 can chemically react with the carbon nanotubes 111, the modified pattern 20 can firmly adsorb and fix the carbon nanotubes 111, so that the sub-pattern 11 is only formed on the modified pattern 20. The multiple sub-patterns 11 in the finally obtained active pattern are spaced apart from each other, and the orthographic projection of each sub-pattern 11 on the substrate 10 and the orthographic projection of the corresponding groove 141 on the substrate 10 exactly overlap.
本公开实施例中，在凹槽141未贯通绝缘层14的情况下，若所述薄膜晶体管为底栅型薄膜晶体管，则可用栅绝缘层16共用作绝缘层14；若所述薄膜晶体管为顶栅型薄膜晶体管或双栅型薄膜晶体管，则可用缓冲层17共用作绝缘层14。这样一来，可以简化薄膜晶体管的制备流程，节省成本。In the embodiment of the present disclosure, when the groove 141 does not penetrate the insulating layer 14, if the thin film transistor is a bottom-gate thin film transistor, the gate insulating layer 16 can be used as the insulating layer 14; if the thin film transistor is top For gate thin film transistors or double gate thin film transistors, the buffer layer 17 can be used as the insulating layer 14 in common. In this way, the manufacturing process of the thin film transistor can be simplified and the cost can be saved.
本公开实施例中，在凹槽141贯通绝缘层14的情况下，若所述薄膜晶体管为底栅型薄膜晶体管，如图10所示，栅绝缘层16设置于绝缘层14的靠近衬底10的一侧，修饰图案20与栅绝缘层16直接接触。可选的，修饰图案20的材料可以与栅绝缘层16的材料发生缩聚反应，以增强修饰图案20与栅绝缘层16的粘附性，使得修饰图案20固定在栅绝缘层16上。In the embodiment of the present disclosure, when the groove 141 penetrates the insulating layer 14, if the thin film transistor is a bottom-gate thin film transistor, as shown in FIG. 10, the gate insulating layer 16 is disposed on the insulating layer 14 close to the substrate 10. On one side, the modified pattern 20 is in direct contact with the gate insulating layer 16. Optionally, the material of the modification pattern 20 may undergo a condensation reaction with the material of the gate insulating layer 16 to enhance the adhesion between the modification pattern 20 and the gate insulating layer 16 so that the modification pattern 20 is fixed on the gate insulating layer 16.
此处，修饰图案20的材料可以是两性偶联剂。其中，两性偶联剂中的一个基团与碳纳米管111发生化学反应，另一个基团与栅绝缘层16的材料发生缩聚反应。Here, the material of the modification pattern 20 may be an amphoteric coupling agent. Among them, one group in the amphoteric coupling agent chemically reacts with the carbon nanotube 111, and the other group undergoes a condensation polymerization reaction with the material of the gate insulating layer 16.
示例的，该两性偶联剂为硅烷偶联剂，例如，3-氨丙基三乙氧基硅烷(APTES)。栅绝缘层16的材料为氧化硅(SiO x)、二氧化铪(HfO 2)，或氧化镁(MgO)与HfO 2的复合膜层。绝缘层14的材料为疏水型绝缘材料，例如氮化硅(SiN x)。 Illustratively, the amphoteric coupling agent is a silane coupling agent, for example, 3-aminopropyltriethoxysilane (APTES). The material of the gate insulating layer 16 is silicon oxide (SiO x ), hafnium dioxide (HfO 2 ), or a composite film layer of magnesium oxide (MgO) and HfO 2 . The material of the insulating layer 14 is a hydrophobic insulating material, such as silicon nitride (SiN x ).
硅烷偶联剂包括氨基和羧基。羧基与栅绝缘层16的材料缩聚，能够形成一层自组装单分子层。氨基与碳纳米管111发生化学反应，并将其吸附在修饰图案20表面。The silane coupling agent includes an amino group and a carboxyl group. The carboxyl group and the material of the gate insulating layer 16 are polycondensed to form a self-assembled monolayer. The amino group reacts chemically with the carbon nanotube 111 and adsorbs it on the surface of the modified pattern 20.
在另一些实施例中，如图11和图12所示，若所述薄膜晶体管为顶栅型薄膜晶体管或双栅型薄膜晶体管，缓冲层17设置于绝缘层14的靠近衬底10的一侧，修饰图案20与缓冲层17直接接触。In other embodiments, as shown in FIGS. 11 and 12, if the thin film transistor is a top gate thin film transistor or a double gate thin film transistor, the buffer layer 17 is disposed on the side of the insulating layer 14 close to the substrate 10. , The modification pattern 20 is in direct contact with the buffer layer 17.
可选的，修饰图案20的材料可以与缓冲层17的材料发生缩聚反应，以增强修饰图案20与缓冲层17的粘附性，使得修饰图案20固定在缓冲层17上。Optionally, the material of the modified pattern 20 may undergo a condensation reaction with the material of the buffer layer 17 to enhance the adhesion between the modified pattern 20 and the buffer layer 17 so that the modified pattern 20 is fixed on the buffer layer 17.
此处，修饰图案20的材料可以是两性偶联剂。其中，两性偶联剂中的一个基团与碳纳米管111发生化学反应，另一个基团与缓冲层17的材料发生缩聚反应。Here, the material of the modification pattern 20 may be an amphoteric coupling agent. Among them, one group in the amphoteric coupling agent chemically reacts with the carbon nanotube 111, and the other group undergoes a condensation polymerization reaction with the material of the buffer layer 17.
示例的，该两性偶联剂为硅烷偶联剂，例如，APTES。缓冲层17的材料为SiO x、HfO 2、或MgO与HfO 2的复合膜层。绝缘层14的材料为疏水型绝缘材料，例如SiN x。 Illustratively, the amphoteric coupling agent is a silane coupling agent, for example, APTES. The material of the buffer layer 17 is SiO x , HfO 2 , or a composite film layer of MgO and HfO 2 . The material of the insulating layer 14 is a hydrophobic insulating material, such as SiN x .
硅烷偶联剂包括氨基和羧基。羧基与缓冲层17的材料缩聚，能够形成一层自组装单分子层。氨基与碳纳米管111发生化学反应，并将其吸附在修饰图案20表面。The silane coupling agent includes an amino group and a carboxyl group. The carboxyl group and the material of the buffer layer 17 are polycondensed to form a self-assembled monolayer. The amino group reacts chemically with the carbon nanotube 111 and adsorbs it on the surface of the modified pattern 20.
本公开实施例还提供了一种阵列基板21。如图13和图14所示，阵列基板21包括多个像素电路210(图中仅示意性的说明像素电路210的设置位置，并未对其结构进行限定)。每个像素电路210包括至少一个驱动晶体管31，所述至少一个驱动晶体管31为前述任一实施例所述的薄膜晶体管。The embodiment of the present disclosure also provides an array substrate 21. As shown in FIG. 13 and FIG. 14, the array substrate 21 includes a plurality of pixel circuits 210 (the figure only schematically illustrates the location of the pixel circuit 210, and does not limit the structure thereof). Each pixel circuit 210 includes at least one driving transistor 31, and the at least one driving transistor 31 is the thin film transistor described in any of the foregoing embodiments.
在上述基础上，每个像素电路210还包括其他元件，例如至少一个开关晶体管和至少一个存储电容。开关晶体管可以是前述任一实施例所述的薄膜晶体管，或者，如图15所示，开关晶体管32也可以是相关技术中其他类型的薄膜晶体管，例如氧化物薄膜晶体管或低温多晶硅薄膜晶体管。Based on the foregoing, each pixel circuit 210 further includes other elements, such as at least one switching transistor and at least one storage capacitor. The switching transistor may be the thin film transistor described in any of the foregoing embodiments, or, as shown in FIG. 15, the switching transistor 32 may also be other types of thin film transistors in the related art, such as oxide thin film transistors or low temperature polysilicon thin film transistors.
此处，图15仅是针对驱动晶体管31和开关晶体管32在阵列基板21中的一种膜层结构进行了示意，并未对驱动晶体管31和开关晶体管 32二者的数量及相应的电连接关系进行限制，也并非是唯一限定。Here, FIG. 15 only illustrates a layer structure of the driving transistor 31 and the switching transistor 32 in the array substrate 21, and does not indicate the number of the driving transistor 31 and the switching transistor 32 and the corresponding electrical connection relationship. Restrictions are not the only restriction.
可选的，如图15所示，开关晶体管32采用顶栅型薄膜晶体管，其有源图案为低温多晶硅半导体图案110。驱动晶体管31采用底栅型薄膜晶体管。如此，驱动晶体管31的栅极15和开关晶体管32的栅极15可以同层设置。驱动晶体管31的源极12、漏极13和开关晶体管32的源极12、漏极13可以同层设置。从而能够简化阵列基板21的制作工艺。Optionally, as shown in FIG. 15, the switching transistor 32 is a top-gate thin film transistor, and its active pattern is a low-temperature polysilicon semiconductor pattern 110. The driving transistor 31 uses a bottom-gate thin film transistor. In this way, the gate 15 of the driving transistor 31 and the gate 15 of the switching transistor 32 can be arranged in the same layer. The source 12 and the drain 13 of the driving transistor 31 and the source 12 and the drain 13 of the switching transistor 32 may be arranged in the same layer. Therefore, the manufacturing process of the array substrate 21 can be simplified.
可选的，以像素电路为2T1C电路为例，也即像素电路至少包括一个开关晶体管(T1)、一个驱动晶体管31(T2)和一个存储电容(C)。开关晶体管的源极12与数据信号端连接、漏极13与驱动晶体管31的栅极15和存储电容的一端连接。驱动晶体管31的源极12与VDD信号线或信号端子连接、漏极13与存储电容的另一端和发光器件(例如下文的中的OLED或LED发光单元)的一端连接。发光器件的另一端与VSS信号线或信号端子连接。Optionally, taking the pixel circuit as a 2T1C circuit as an example, that is, the pixel circuit includes at least one switching transistor (T1), one driving transistor 31 (T2) and one storage capacitor (C). The source 12 of the switching transistor is connected to the data signal terminal, and the drain 13 is connected to the gate 15 of the driving transistor 31 and one end of the storage capacitor. The source 12 of the driving transistor 31 is connected to the VDD signal line or signal terminal, and the drain 13 is connected to the other end of the storage capacitor and one end of the light emitting device (for example, an OLED or LED light emitting unit below). The other end of the light emitting device is connected to the VSS signal line or signal terminal.
本公开实施例还提供了一种显示装置，包括如上一些实施例所述的阵列基板21。可选的，显示装置是OLED显示装置、QLED显示装置或LED显示装置。The embodiments of the present disclosure also provide a display device, including the array substrate 21 described in some of the above embodiments. Optionally, the display device is an OLED display device, a QLED display device or an LED display device.
如图13所示，在显示装置为OLED显示装置或QLED显示装置的情况下，OLED显示装置或QLED显示装置包括阵列基板21。阵列基板21还包括设置在像素电路210的背离衬底10的一侧的多个发光器件。发光器件包括依次层叠设置的第一电极42、发光层43和第二电极44。第一电极42与对应像素电路210中的驱动晶体管31的漏极13电连接。在此基础上，阵列基板21还包括设置在相邻发光器件之间的像素界定层45，也即各发光器件分别位于像素界定层45界定的对应开口区域内。As shown in FIG. 13, when the display device is an OLED display device or a QLED display device, the OLED display device or QLED display device includes an array substrate 21. The array substrate 21 also includes a plurality of light emitting devices disposed on a side of the pixel circuit 210 facing away from the substrate 10. The light emitting device includes a first electrode 42, a light emitting layer 43, and a second electrode 44 that are sequentially stacked. The first electrode 42 is electrically connected to the drain 13 of the driving transistor 31 in the corresponding pixel circuit 210. On this basis, the array substrate 21 further includes a pixel defining layer 45 arranged between adjacent light emitting devices, that is, each light emitting device is located in a corresponding opening area defined by the pixel defining layer 45 respectively.
在一些实施例中，发光器件中的第一电极42为阳极，第二电极44为阴极；或者，发光器件中的第一电极42为阴极，第二电极44为阳极。In some embodiments, the first electrode 42 in the light emitting device is an anode, and the second electrode 44 is a cathode; or, the first electrode 42 in the light emitting device is a cathode, and the second electrode 44 is an anode.
在一些实施例中，若显示装置为OLED显示装置，则发光层43为有机发光功能层；若显示装置为QLED显示装置，则发光层43为量子点发 光层。In some embodiments, if the display device is an OLED display device, the light-emitting layer 43 is an organic light-emitting functional layer; if the display device is a QLED display device, the light-emitting layer 43 is a quantum dot light-emitting layer.
如图14所示，在显示装置为LED显示装置的情况下，阵列基板21还包括设置在像素电路210的背离衬底10的一侧的多个LED发光单元41。每个LED发光单元41与对应像素电路210中的驱动晶体管31的漏极13电连接。每个LED发光单元41的阴极与VSS信号线或信号端子相连。As shown in FIG. 14, when the display device is an LED display device, the array substrate 21 further includes a plurality of LED light-emitting units 41 arranged on the side of the pixel circuit 210 away from the substrate 10. Each LED light emitting unit 41 is electrically connected to the drain 13 of the driving transistor 31 in the corresponding pixel circuit 210. The cathode of each LED light emitting unit 41 is connected to the VSS signal line or signal terminal.
在本公开实施例提供的阵列基板和显示装置中，由于驱动晶体管31通常需要较高的迁移率，因此，可采用本公开实施例的薄膜晶体管作为驱动晶体管31，以提高各像素电路210对应的发光器件的发光效率。此外，在本公开实施例中，驱动晶体管31采用碳纳米晶体管，开关晶体管32采用氧化物薄膜晶体管或低温多晶硅薄膜晶体管，有利于在确保阵列基板21具有良好电学性能的前提下，通过驱动晶体管31和开关晶体管32的合理设计，实现阵列基板以及显示装置的大尺寸显示或超大尺寸显示。In the array substrate and the display device provided by the embodiment of the present disclosure, since the driving transistor 31 generally requires higher mobility, the thin film transistor of the embodiment of the present disclosure may be used as the driving transistor 31 to improve the corresponding pixel circuit 210. Luminous efficiency of light-emitting devices. In addition, in the embodiment of the present disclosure, the driving transistor 31 is a carbon nano transistor, and the switching transistor 32 is an oxide thin film transistor or a low-temperature polysilicon thin film transistor, which is beneficial to ensure that the array substrate 21 has good electrical performance. And the reasonable design of the switching transistor 32 realizes large-size display or super-large-size display of the array substrate and the display device.
本公开实施例还提供了一种薄膜晶体管的制备方法，用于制作上述一些实施例所述的薄膜晶体管。如图16所示，该薄膜晶体管的制备方法包括S11～S13。The embodiments of the present disclosure also provide a method for manufacturing a thin film transistor for manufacturing the thin film transistor described in some of the above embodiments. As shown in FIG. 16, the manufacturing method of the thin film transistor includes S11 to S13.
S11、如图17中的(a)所示，在衬底10上形成绝缘薄膜，在绝缘薄膜中形成多个沿第一方向延伸且间隔设置的凹槽141，以得到绝缘层14。S11. As shown in FIG. 17(a), an insulating film is formed on the substrate 10, and a plurality of grooves 141 extending along the first direction and arranged at intervals are formed in the insulating film to obtain the insulating layer 14.
可选的，如图9所示，不论衬底10上设置有一个或多个所述薄膜晶体管，绝缘层14中除凹槽141以外的其他部分的背离衬底10一侧的表面与衬底10之间的距离都相同。Optionally, as shown in FIG. 9, regardless of the one or more thin film transistors provided on the substrate 10, the surface of the insulating layer 14 on the side facing away from the substrate 10 and the substrate 10 except for the groove 141 The distance between 10 is the same.
根据绝缘层14的材料的不同，绝缘层14的形成方式也不相同。示例的，若绝缘层14的材料包括无机绝缘材料或感光材料，则可以采用光刻工艺形成包括多个凹槽141的绝缘层14。Depending on the material of the insulating layer 14, the insulating layer 14 is formed in different ways. For example, if the material of the insulating layer 14 includes an inorganic insulating material or a photosensitive material, the insulating layer 14 including a plurality of grooves 141 can be formed by using a photolithography process.
S12、如图17中的(b)所示，在绝缘层14的背离衬底10一侧形成 包括碳纳米管的有源图案。有源图案包括间隔设置的多个子图案11；子图案11与凹槽141一一对应，且子图案11在衬底10上的正投影和与其对应的凹槽141在衬底10上的正投影完全重叠。S12. As shown in FIG. 17(b), an active pattern including carbon nanotubes is formed on the side of the insulating layer 14 away from the substrate 10. The active pattern includes a plurality of sub-patterns 11 arranged at intervals; the sub-pattern 11 corresponds to the groove 141 one-to-one, and the orthographic projection of the sub-pattern 11 on the substrate 10 and the orthographic projection of the corresponding groove 141 on the substrate 10 Completely overlap.
此处，子图案11沿第一方向延伸，且沿第一方向，有源图案中的每个子图案11中的一端与源极12相接触、另一端与漏极13相接触。因此，上述第一方向即待形成的源极12指向漏极13的方向。Here, the sub-pattern 11 extends along the first direction, and along the first direction, one end of each sub-pattern 11 in the active pattern is in contact with the source 12 and the other end is in contact with the drain 13. Therefore, the above-mentioned first direction, that is, the direction in which the source electrode 12 to be formed points to the drain electrode 13.
由于本公开实施例中的碳纳米管111用于制作有源图案，因此，本公开实施例所采用的碳纳米管111为半导体型碳纳米管。半导体型碳纳米管的获取方式可参见前述实施例的相关记载，此处不再详述。Since the carbon nanotubes 111 in the embodiments of the present disclosure are used for making active patterns, the carbon nanotubes 111 used in the embodiments of the present disclosure are semiconductor-type carbon nanotubes. The method of obtaining the semiconductor carbon nanotubes can be referred to the relevant records of the foregoing embodiments, and the details are omitted here.
上述有源图案中子图案11的个数、形状和尺寸，均可参见前述实施例的相关记载，此处不再详述。The number, shape and size of the sub-patterns 11 in the above-mentioned active pattern can all be referred to the relevant description of the foregoing embodiment, and the detailed description is omitted here.
有源图案的形成方式可以根据实际需求选择设置。示例的，可以采用喷涂、旋涂、刮涂或喷墨打印等方式在衬底10上形成碳纳米管111溶液；之后，再用高温对碳纳米管111溶液进行烘干处理，得到碳纳米管薄膜。The formation method of the active pattern can be selected and set according to actual needs. For example, the carbon nanotube 111 solution can be formed on the substrate 10 by spraying, spin coating, blade coating, or inkjet printing; after that, the carbon nanotube 111 solution is dried at a high temperature to obtain carbon nanotubes. film.
若采用喷涂、旋涂、刮涂等方式在凹槽141中形成碳纳米管溶液，在得到碳纳米管薄膜之后，还需在碳纳米管薄膜背离衬底10一侧形成光刻胶；对光刻胶进行曝光、显影，形成光刻胶图案；最后，对碳纳米管薄膜进行刻蚀，得到所述有源图案，并剥离光刻胶图案。If the carbon nanotube solution is formed in the groove 141 by spraying, spin coating, blade coating, etc., after the carbon nanotube film is obtained, a photoresist needs to be formed on the side of the carbon nanotube film away from the substrate 10; The resist is exposed and developed to form a photoresist pattern; finally, the carbon nanotube film is etched to obtain the active pattern, and the photoresist pattern is stripped.
若采用喷墨打印的方式形成碳纳米管溶液，则得到的碳纳米管薄膜即为所述有源图案。If the carbon nanotube solution is formed by inkjet printing, the obtained carbon nanotube film is the active pattern.
S13、参考图4-图7所示，在有源图案的背离衬底10的一侧分别形成源极12和漏极13。沿第一方向，有源图案中的每个子图案11中的一端与源极12相接触、另一端与漏极13相接触。S13. Referring to FIGS. 4-7, a source electrode 12 and a drain electrode 13 are respectively formed on the side of the active pattern away from the substrate 10. Along the first direction, one end of each sub-pattern 11 in the active pattern is in contact with the source electrode 12 and the other end is in contact with the drain electrode 13.
源极12和漏极13二者的材料及结构，可参见前述实施例的相关记载，此处不再详述。The materials and structures of the source electrode 12 and the drain electrode 13 can be referred to the relevant description of the foregoing embodiment, and will not be described in detail here.
本公开实施例提供的薄膜晶体管的制备方法，具有与前述薄膜晶体 管相同的技术效果，在此不再赘述。The manufacturing method of the thin film transistor provided by the embodiment of the present disclosure has the same technical effect as the aforementioned thin film transistor, and will not be repeated here.
在一些实施例中，如图10-图12所示，在形成绝缘层14之后，形成有源图案之前，该薄膜晶体管的制备方法还包括：向每个凹槽141中填充修饰图案20。In some embodiments, as shown in FIGS. 10 to 12, after the insulating layer 14 is formed and before the active pattern is formed, the method for manufacturing the thin film transistor further includes: filling each groove 141 with a modified pattern 20.
S12中形成有源图案，还包括：在修饰图案20的背离衬底10的表面上形成对应的子图案11。修饰图案20与子图案11一一对应且直接接触，修饰图案20在衬底10上的正投影和与其对应的子图案11在衬底10上正投影完全重叠。The forming of the active pattern in S12 further includes: forming a corresponding sub-pattern 11 on the surface of the modified pattern 20 facing away from the substrate 10. The modification pattern 20 has a one-to-one correspondence and direct contact with the sub-pattern 11, and the orthographic projection of the modification pattern 20 on the substrate 10 and the orthographic projection of the corresponding sub-pattern 11 on the substrate 10 completely overlap.
在一些实施例中，凹槽141贯通绝缘层14。In some embodiments, the groove 141 penetrates through the insulating layer 14.
可选的，如图10所示，薄膜晶体管为底栅型薄膜晶体管。在形成绝缘层14之前，所述薄膜晶体管的制备方法还包括在衬底10上形成栅绝缘层16。修饰图案20与设置于绝缘层14的靠近衬底10一侧的栅绝缘层16直接接触。Optionally, as shown in FIG. 10, the thin film transistor is a bottom-gate thin film transistor. Before forming the insulating layer 14, the manufacturing method of the thin film transistor further includes forming a gate insulating layer 16 on the substrate 10. The modification pattern 20 directly contacts the gate insulating layer 16 disposed on the side of the insulating layer 14 close to the substrate 10.
可选的，如图11和图12所示，薄膜晶体管为顶栅型薄膜晶体管或双栅型薄膜晶体管。在形成绝缘层14之前，所述薄膜晶体管的制备方法还包括在衬底10上形成缓冲层17。修饰图案20与设置于绝缘层14的靠近衬底10一侧的缓冲层17直接接触。Optionally, as shown in FIGS. 11 and 12, the thin film transistor is a top gate thin film transistor or a double gate thin film transistor. Before forming the insulating layer 14, the manufacturing method of the thin film transistor further includes forming a buffer layer 17 on the substrate 10. The modification pattern 20 directly contacts the buffer layer 17 disposed on the side of the insulating layer 14 close to the substrate 10.
上述修饰图案20的材料可以根据实际需求选择设置。The material of the aforementioned modification pattern 20 can be selected and set according to actual requirements.
一方面，修饰图案20的材料可以与碳纳米管111发生化学反应，以使得子图案11仅形成于修饰图案20上。On the one hand, the material of the modified pattern 20 can chemically react with the carbon nanotubes 111 so that the sub-pattern 11 is only formed on the modified pattern 20.
另一方面，在凹槽141贯通绝缘层14的情况下，修饰图案20的材料不与绝缘层14的材料发生缩聚反应，可以避免修饰图案20形成在绝缘层14的背离衬底10一侧表面上，进而避免有源图案形成在除凹槽141所在的区域以外的区域。On the other hand, when the groove 141 penetrates the insulating layer 14, the material of the modification pattern 20 does not undergo condensation reaction with the material of the insulating layer 14, which can prevent the modification pattern 20 from being formed on the surface of the insulating layer 14 facing away from the substrate 10. This prevents the active pattern from being formed in areas other than the area where the groove 141 is located.
又一方面，若薄膜晶体管为底栅型薄膜晶体管，则修饰图案20的材料还可与栅绝缘层16的材料发生缩聚反应，以使得修饰图案20固定在栅绝缘层16上；或者，若薄膜晶体管为顶栅型薄膜晶体管或双栅型薄膜 晶体管，则修饰图案20的材料还可与缓冲层17的材料发生缩聚反应，以使得修饰图案20固定在缓冲层17上。On the other hand, if the thin film transistor is a bottom-gate thin film transistor, the material of the modified pattern 20 can also undergo a condensation reaction with the material of the gate insulating layer 16, so that the modified pattern 20 is fixed on the gate insulating layer 16; or, if the thin film If the transistor is a top-gate thin film transistor or a double-gate thin film transistor, the material of the modified pattern 20 can also undergo a condensation reaction with the material of the buffer layer 17 so that the modified pattern 20 is fixed on the buffer layer 17.
可选的，修饰图案20的材料是两性偶联剂，例如硅烷偶联剂中的APTES。栅绝缘层16的材料为SiO x、HfO 2，或MgO与HfO 2的复合膜层。绝缘层14(或缓冲层)的材料为疏水型绝缘材料，例如SiN x。 Optionally, the material of the modified pattern 20 is an amphoteric coupling agent, such as APTES in a silane coupling agent. The material of the gate insulating layer 16 is SiO x , HfO 2 , or a composite film layer of MgO and HfO 2 . The material of the insulating layer 14 (or buffer layer) is a hydrophobic insulating material, such as SiN x .
可选的，如图10所示，修饰图案20的厚度小于与其对应的凹槽141的深度。或者，如图11和图12所示，修饰图案20的厚度恰好等于与其对应的凹槽141的深度。或者，修饰图案20的厚度大于与其对应的凹槽141的深度。Optionally, as shown in FIG. 10, the thickness of the modification pattern 20 is smaller than the depth of the corresponding groove 141. Or, as shown in FIGS. 11 and 12, the thickness of the modification pattern 20 is exactly equal to the depth of the corresponding groove 141. Or, the thickness of the modification pattern 20 is greater than the depth of the corresponding groove 141.
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who thinks of changes or substitutions within the technical scope disclosed in the present disclosure shall cover Within the protection scope of this disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims (15)

  1. 一种薄膜晶体管，包括设置于衬底上的有源图案、源极和漏极；其中，A thin film transistor including an active pattern, a source electrode and a drain electrode arranged on a substrate; wherein,
    所述有源图案的材料包括碳纳米管；所述有源图案包括沿第一方向延伸且间隔设置的多个子图案；沿所述第一方向，所述有源图案中的每个所述子图案中的一端与所述源极相接触、另一端与所述漏极相接触。The material of the active pattern includes carbon nanotubes; the active pattern includes a plurality of sub-patterns extending along a first direction and arranged at intervals; along the first direction, each of the sub-patterns in the active pattern One end of the pattern is in contact with the source and the other end is in contact with the drain.
  2. 根据权利要求1所述的薄膜晶体管，还包括设置于所述衬底与所述有源图案之间的绝缘层；The thin film transistor according to claim 1, further comprising an insulating layer provided between the substrate and the active pattern;
    所述绝缘层包括多个凹槽；所述凹槽与所述子图案一一对应，且所述凹槽在所述衬底上的正投影与对应的所述子图案在所述衬底上的正投影重叠。The insulating layer includes a plurality of grooves; the grooves and the sub-patterns correspond one-to-one, and the orthographic projection of the grooves on the substrate and the corresponding sub-patterns on the substrate The orthographic projections overlap.
  3. 根据权利要求2所述的薄膜晶体管，其中，所述子图案填充于对应的所述凹槽中；4. The thin film transistor of claim 2, wherein the sub-pattern is filled in the corresponding groove;
    所述子图案的靠近所述衬底的一侧的表面和与其对应的所述凹槽的底面平齐。The surface of the sub-pattern on the side close to the substrate is flush with the bottom surface of the corresponding groove.
  4. 根据权利要求2所述的薄膜晶体管，还包括填充于每个所述凹槽中的修饰图案；3. The thin film transistor according to claim 2, further comprising a modification pattern filled in each of the grooves;
    所述有源图案设置于所述修饰图案的背离所述衬底的一侧；所述修饰图案与所述子图案一一对应且直接接触，所述修饰图案在所述衬底上的正投影和与其对应的所述子图案在所述衬底上正投影重叠。The active pattern is arranged on the side of the modification pattern away from the substrate; the modification pattern corresponds to the sub-patterns one-to-one and directly contacts, and the orthographic projection of the modification pattern on the substrate And the corresponding sub-pattern is overlapped by orthographic projection on the substrate.
  5. 根据权利要求2所述的薄膜晶体管，其中，The thin film transistor according to claim 2, wherein
    所述薄膜晶体管为底栅型薄膜晶体管、顶栅型薄膜晶体管或双栅型薄膜晶体管中的一种；The thin film transistor is one of a bottom-gate thin film transistor, a top-gate thin film transistor or a double-gate thin film transistor;
    所述绝缘层设置于所述有源图案的靠近所述衬底的一侧；所述凹槽未贯通所述绝缘层。The insulating layer is disposed on a side of the active pattern close to the substrate; the groove does not penetrate the insulating layer.
  6. 根据权利要求3或4所述的薄膜晶体管，其中，The thin film transistor according to claim 3 or 4, wherein:
    所述薄膜晶体管为底栅型薄膜晶体管；所述薄膜晶体管还包括设置于所述衬底上的栅绝缘层，所述栅绝缘层设置于所述绝缘层的靠近所述 衬底的一侧；The thin film transistor is a bottom-gate thin film transistor; the thin film transistor further includes a gate insulating layer disposed on the substrate, and the gate insulating layer is disposed on a side of the insulating layer close to the substrate;
    或者，所述薄膜晶体管为顶栅型薄膜晶体管或双栅型薄膜晶体管；所述薄膜晶体管还包括设置于所述衬底上的缓冲层，所述缓冲层设置于所述绝缘层的靠近所述衬底的一侧。Alternatively, the thin film transistor is a top gate thin film transistor or a double gate thin film transistor; the thin film transistor further includes a buffer layer disposed on the substrate, and the buffer layer is disposed near the insulating layer. One side of the substrate.
  7. 根据权利要求4所述的薄膜晶体管，其中，所述凹槽贯通所述绝缘层；4. The thin film transistor of claim 4, wherein the groove penetrates the insulating layer;
    所述薄膜晶体管为底栅型薄膜晶体管；所述薄膜晶体管还包括设置于所述衬底上的栅绝缘层，所述栅绝缘层设置于所述绝缘层的靠近所述衬底的一侧，所述修饰图案与所述栅绝缘层直接接触；The thin film transistor is a bottom-gate thin film transistor; the thin film transistor further includes a gate insulating layer disposed on the substrate, and the gate insulating layer is disposed on a side of the insulating layer close to the substrate, The modification pattern is in direct contact with the gate insulating layer;
    或者，所述薄膜晶体管为顶栅型薄膜晶体管或双栅型薄膜晶体管；所述薄膜晶体管还包括设置于所述衬底上的缓冲层，所述缓冲层设置于所述绝缘层的靠近所述衬底的一侧，所述修饰图案与所述缓冲层直接接触。Alternatively, the thin film transistor is a top gate thin film transistor or a double gate thin film transistor; the thin film transistor further includes a buffer layer disposed on the substrate, and the buffer layer is disposed near the insulating layer. On one side of the substrate, the modified pattern is in direct contact with the buffer layer.
  8. 根据权利要求7所述的薄膜晶体管，其中，所述修饰图案的材料为硅烷偶联剂，所述绝缘层的材料为疏水性绝缘材料；8. The thin film transistor according to claim 7, wherein the material of the modified pattern is a silane coupling agent, and the material of the insulating layer is a hydrophobic insulating material;
    所述底栅型薄膜晶体管中的所述栅绝缘层的材料可与羧基发生缩聚反应；或者，所述顶栅型薄膜晶体管或所述双栅型薄膜晶体管中的所述缓冲层的材料可与羧基发生缩聚反应。The material of the gate insulating layer in the bottom-gate thin film transistor may undergo a condensation reaction with carboxyl groups; or, the material of the buffer layer in the top-gate thin film transistor or the double-gate thin film transistor may be combined with The carboxyl group undergoes condensation polymerization.
  9. 根据权利要求1-4任一项所述的薄膜晶体管，其中，所述子图案的横截面的宽度范围为大于或等于500nm、且小于1000nm；The thin film transistor according to any one of claims 1 to 4, wherein the width range of the cross section of the sub-pattern is greater than or equal to 500 nm and less than 1000 nm;
    其中，所述横截面与所述衬底的厚度方向垂直，所述横截面的宽度与所述第一方向垂直。Wherein, the cross section is perpendicular to the thickness direction of the substrate, and the width of the cross section is perpendicular to the first direction.
  10. 一种阵列基板，包括多个像素电路；每个像素电路包括至少一个驱动晶体管；所述至少一个驱动晶体管为权利要求1-9任一项所述的薄膜晶体管。An array substrate including a plurality of pixel circuits; each pixel circuit includes at least one driving transistor; the at least one driving transistor is the thin film transistor according to any one of claims 1-9.
  11. 根据权利要求10所述的阵列基板，其中，所述每个像素电路还包括至少一个开关晶体管；10. The array substrate according to claim 10, wherein each pixel circuit further comprises at least one switching transistor;
    所述至少一个开关晶体管包括氧化物薄膜晶体管或低温多晶硅薄膜晶体管。The at least one switching transistor includes an oxide thin film transistor or a low temperature polysilicon thin film transistor.
  12. 一种显示装置，包括权利要求10或11所述的阵列基板。A display device comprising the array substrate according to claim 10 or 11.
  13. 一种薄膜晶体管的制备方法，包括：A method for manufacturing a thin film transistor, including:
    在衬底上形成绝缘薄膜，在所述绝缘薄膜中形成多个沿第一方向延伸且间隔设置的凹槽，得到绝缘层；Forming an insulating film on the substrate, and forming a plurality of grooves extending along the first direction and spaced apart in the insulating film to obtain an insulating layer;
    在所述绝缘层的背离所述衬底的一侧形成包括碳纳米管的有源图案；所述有源图案包括间隔设置的多个子图案，所述子图案与所述凹槽一一对应，且所述子图案在所述衬底上的正投影和与其对应的所述凹槽在所述衬底上的正投影重叠；An active pattern including carbon nanotubes is formed on the side of the insulating layer away from the substrate; the active pattern includes a plurality of sub-patterns arranged at intervals, and the sub-patterns correspond to the grooves one-to-one, And the orthographic projection of the sub-pattern on the substrate overlaps the orthographic projection of the corresponding groove on the substrate;
    在所述有源图案的背离所述衬底的一侧分别形成源极和漏极，沿所述第一方向，所述有源图案中的每个子图案中的一端与所述源极相接触、另一端与所述漏极相接触。A source and a drain are respectively formed on the side of the active pattern away from the substrate, and along the first direction, one end of each sub-pattern in the active pattern is in contact with the source The other end is in contact with the drain.
  14. 根据权利要求13所述的薄膜晶体管的制备方法，其中，The method of manufacturing a thin film transistor according to claim 13, wherein:
    在形成所述绝缘层之后，形成所述有源图案之前，所述薄膜晶体管的制备方法还包括：向每个所述凹槽中填充修饰图案；After forming the insulating layer and before forming the active pattern, the method for manufacturing the thin film transistor further includes: filling each of the grooves with a modified pattern;
    形成所述有源图案还包括：在所述修饰图案的背离所述衬底的表面上形成对应的所述子图案，所述修饰图案在所述衬底上的正投影和与其对应的所述子图案在所述衬底上正投影重叠。Forming the active pattern further includes: forming the corresponding sub-pattern on the surface of the modified pattern facing away from the substrate, the orthographic projection of the modified pattern on the substrate and the corresponding sub-pattern The sub-patterns overlap in orthographic projection on the substrate.
  15. 根据权利要求14所述的薄膜晶体管的制备方法，其中，所述凹槽贯通所述绝缘层；14. The method of manufacturing a thin film transistor according to claim 14, wherein the groove penetrates the insulating layer;
    所述薄膜晶体管为底栅型薄膜晶体管；在形成所述绝缘层之前，所述薄膜晶体管的制备方法还包括在衬底上形成栅绝缘层；所述修饰图案与所述栅绝缘层直接接触；The thin film transistor is a bottom-gate thin film transistor; before forming the insulating layer, the method for preparing the thin film transistor further includes forming a gate insulating layer on a substrate; the modified pattern is in direct contact with the gate insulating layer;
    或者，所述薄膜晶体管为顶栅型薄膜晶体管或双栅型薄膜晶体管；在形成所述绝缘层之前，所述薄膜晶体管的制备方法还包括在衬底上形成缓冲层；所述修饰图案与所述缓冲层直接接触。Alternatively, the thin film transistor is a top-gate thin film transistor or a double-gate thin film transistor; before forming the insulating layer, the method for preparing the thin film transistor further includes forming a buffer layer on a substrate; the modified pattern and the The buffer layer is in direct contact.
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