WO2020215856A1 - 芯片转移方法、显示装置、芯片及目标基板 - Google Patents

芯片转移方法、显示装置、芯片及目标基板 Download PDF

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Publication number
WO2020215856A1
WO2020215856A1 PCT/CN2020/074709 CN2020074709W WO2020215856A1 WO 2020215856 A1 WO2020215856 A1 WO 2020215856A1 CN 2020074709 W CN2020074709 W CN 2020074709W WO 2020215856 A1 WO2020215856 A1 WO 2020215856A1
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WIPO (PCT)
Prior art keywords
bonding structure
chip
alignment
substrate
opening
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PCT/CN2020/074709
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English (en)
French (fr)
Inventor
陈亮
王磊
玄明花
肖丽
刘冬妮
赵德涛
陈昊
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/057,351 priority Critical patent/US11616043B2/en
Publication of WO2020215856A1 publication Critical patent/WO2020215856A1/zh

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Definitions

  • the application relates to a chip transfer method, a display device, a chip and a target substrate.
  • Micro Light Emitting Diode (English: Micro Light Emitting Diode; abbreviation: Micro LED/ ⁇ LED) chip is a new type of LED chip, which has the advantages of high brightness, high luminous efficiency and low power consumption. It has a wide range of application prospects in the display industry . Micro LED chips are usually formed on a sapphire substrate (hereinafter referred to as a source substrate), and the Micro LED chips need to be transferred from the source substrate to the target substrate (such as a display backplane) during use.
  • a source substrate hereinafter referred to as a source substrate
  • the Micro LED chips need to be transferred from the source substrate to the target substrate (such as a display backplane) during use.
  • the application provides a chip transfer method, a display device, a chip and a target substrate.
  • the technical solutions are as follows:
  • a chip transfer method including:
  • the target substrate including a first alignment bonding structure and a second alignment bonding structure
  • a charge of a second polarity is applied to a first chip bonding structure of a chip, the chip includes a second chip bonding structure and the first chip bonding structure, the second polarity is the same as the first polarity different;
  • Insulating fluid is injected into the sealed chamber to make the chip suspend in the insulating fluid in the sealed chamber, wherein, between the first chip bonding structure and the first alignment bonding structure Under the action, the chip moves close to the target substrate, so that the first chip bonding structure is in contact with the first alignment bonding structure, and the second chip bonding structure is in contact with the second alignment bond Combined structure contact;
  • the method further includes:
  • injecting an insulating fluid into the airtight chamber to suspend the chip in the insulating fluid in the airtight chamber includes:
  • the chip is set in the sealed chamber, and an insulating fluid is injected into the sealed chamber, so that the chip is suspended in the insulating fluid in the sealed chamber; or,
  • the chip is mixed with an insulating fluid, and the insulating fluid mixed with the chip is injected into the sealed chamber, so that the chip is suspended in the insulating fluid in the sealed chamber.
  • the method before injecting an insulating fluid into the sealed chamber to suspend the chip in the insulating fluid in the sealed chamber, the method further includes:
  • the chip is separated from the source substrate.
  • the target substrate includes a laminated bonding layer and an alignment layer
  • the bonding layer includes a first substrate bonding structure and a second substrate bonding structure
  • the alignment layer has a first alignment opening And a second alignment opening
  • the first alignment bonding structure includes the first substrate bonding structure and the first alignment opening
  • the second alignment bonding structure includes the second substrate bond The joint structure and the second alignment opening
  • Applying a charge of a first polarity to the first alignment bonding structure of the target substrate includes:
  • the charge of the first polarity is applied to the first substrate bonding structure of the target substrate, wherein, under the action of the first chip bonding structure and the first substrate bonding structure, the The chip moves closer to the target substrate, the first chip bonding structure enters the first alignment opening to contact the first substrate bonding structure, and the second chip bonding structure enters the second alignment The opening is in contact with the second substrate bonding structure.
  • a display device including: a chip and a target substrate,
  • the chip includes a first chip bonding structure and a second chip bonding structure
  • the target substrate includes a first alignment bonding structure and a second alignment bonding structure
  • the first chip bonding structure and the The first alignment bonding structure is bonded
  • the second chip bonding structure is bonded to the second alignment bonding structure.
  • the target substrate includes a laminated bonding layer and an alignment layer
  • the bonding layer includes a first substrate bonding structure and a second substrate bonding structure
  • the alignment layer has a first alignment opening And a second alignment opening
  • the first alignment bonding structure includes the first substrate bonding structure and the first alignment opening
  • the second alignment bonding structure includes the second substrate bond The joint structure and the second alignment opening
  • the first chip bonding structure is bonded to the first substrate bonding structure through the first alignment opening, and the second chip bonding structure is bonded to the second substrate through the second alignment opening The bonding structure is bonded.
  • the size of the first chip bonding structure is smaller than the size of the first alignment opening
  • the size of the second chip bonding structure is smaller than the size of the second alignment opening and larger than the size of the first alignment opening.
  • the distance between the first chip bonding structure and the second chip bonding structure is equal to the distance between the first alignment opening and the second alignment opening.
  • the first alignment opening is an alignment hole
  • the second alignment opening is an alignment slit
  • the size of the first chip bonding structure is smaller than the aperture of the first alignment opening
  • the size of the second chip bonding structure is smaller than the width of the second alignment opening and larger than the aperture of the first alignment opening.
  • the orthographic projection of the first substrate bonding structure on the alignment layer covers the first alignment opening
  • the orthographic projection of the second substrate bonding structure on the alignment layer covers The second alignment opening
  • the first chip bonding structure, the second chip bonding structure, and the first substrate bonding structure are all columnar structures, the second substrate bonding structure is a ring structure, and the The first alignment opening is an alignment hole, the second alignment opening is an annular alignment slit, the first substrate bonding structure is located at the center of the ring of the second substrate bonding structure, and the first pair The position opening is located at the center of the ring of the second alignment opening;
  • the size of the bottom surface of the first chip bonding structure is smaller than the aperture of the first alignment opening, and the size of the bottom surface of the second chip bonding structure is larger than the aperture of the first alignment opening and smaller than the aperture of the first alignment opening.
  • the height of the first chip bonding structure is equal to the height of the second chip bonding structure, and the height of the first substrate bonding structure is equal to the height of the second substrate bonding structure;
  • the shape of the opening surface of the first alignment opening is the same as the shape of the bottom surface of the first substrate bonding structure, and the aperture of the first alignment opening is less than or equal to that of the bottom surface of the first substrate bonding structure. size;
  • the shape of the opening surface of the second alignment opening is the same as the ring shape of the second substrate bonding structure, and the width of the second alignment opening is less than or equal to the width of the second substrate bonding structure.
  • the first chip bonding structure, the second chip bonding structure and the first substrate bonding structure are all cylindrical structures, and the second substrate bonding structure is an annular structure,
  • the first alignment opening is a circular hole, and the second alignment opening is a circular annular slit;
  • the diameter of the first chip bonding structure is smaller than the aperture of the first alignment opening, and the diameter of the second chip bonding structure is larger than the aperture of the first alignment opening and smaller than the second alignment opening Width
  • the aperture of the first alignment opening is smaller than or equal to the diameter of the first substrate bonding structure, and the width of the second alignment opening is smaller than or equal to the width of the second substrate bonding structure.
  • the chip further includes: a weight body distributed in the same layer as the second chip bonding structure, and the weight body is used to make the center of gravity of the chip coincide with the center of the chip.
  • the longitudinal axis sections of the first chip bonding structure, the second chip bonding structure and the weight body are coplanar.
  • the first chip bonding structure and the first substrate bonding structure are both columnar structures
  • the second chip bonding structure and the second substrate bonding structure are both ring structures
  • the first alignment opening is an alignment hole
  • the second alignment opening is an annular alignment slit
  • the first chip bonding structure is located at the center of the ring of the second chip bonding structure
  • the first A substrate bonding structure is located at the center of the ring of the second substrate bonding structure
  • the first alignment opening is located at the center of the ring of the second alignment opening
  • the size of the bottom surface of the first chip bonding structure is smaller than the aperture of the first alignment opening, and the width of the second chip bonding structure is smaller than the width of the second alignment opening;
  • the height of the first chip bonding structure is equal to the height of the second chip bonding structure, and the height of the first substrate bonding structure is equal to the height of the second substrate bonding structure;
  • the shape of the opening surface of the first alignment opening is the same as the shape of the bottom surface of the first substrate bonding structure, and the aperture of the first alignment opening is less than or equal to that of the bottom surface of the first substrate bonding structure. size;
  • the shape of the opening surface of the second alignment opening is the same as the ring shape of the second substrate bonding structure, and the width of the second alignment opening is less than or equal to the width of the second substrate bonding structure.
  • the first chip bonding structure and the first substrate bonding structure are both cylindrical structures, and the second chip bonding structure and the second substrate bonding structure are both annular structures ,
  • the first alignment opening is a circular alignment hole, and the second alignment opening is a circular alignment slit;
  • the diameter of the first chip bonding structure is smaller than the aperture of the first alignment opening, and the width of the second chip bonding structure is smaller than the width of the second alignment opening;
  • the aperture of the first alignment opening is smaller than or equal to the diameter of the first substrate bonding structure, and the width of the second alignment opening is smaller than or equal to the width of the second substrate bonding structure.
  • a chip including:
  • the first chip bonding structure is configured to bond with a first alignment bonding structure of a target substrate
  • the second chip bonding structure is configured to bond with a second alignment bonding structure of the target substrate Together.
  • the first chip bonding structure and the second chip bonding structure are both columnar structures, and the shape of the bottom surface of the first chip bonding structure is the same as that of the bottom surface of the second chip bonding structure.
  • the size of the bottom surface of the first chip bonding structure is smaller than the size of the bottom surface of the second chip bonding structure, the height of the first chip bonding structure and the height of the second chip bonding structure equal.
  • the first chip bonding structure and the second chip bonding structure are both cylindrical structures, and the diameter of the first chip bonding structure is smaller than the diameter of the second chip bonding structure.
  • the chip further includes: a weight body distributed in the same layer as the second chip bonding structure, and the weight body is used to make the center of gravity of the chip coincide with the center of the chip.
  • the longitudinal axis sections of the first chip bonding structure, the second chip bonding structure and the weight body are coplanar.
  • the first chip bonding structure is a columnar structure
  • the second chip bonding structure is a ring structure
  • the first chip bonding structure is located at the center of the ring of the second chip bonding structure ;
  • the height of the first chip bonding structure is equal to the height of the second chip bonding structure.
  • the first chip bonding structure is a cylindrical structure
  • the second chip bonding structure is a circular ring structure.
  • the chip body has a columnar structure, and the axis of the first chip bonding structure is collinear with the axis of the chip body.
  • a target substrate including:
  • the first substrate bonding structure is configured to bond with the first chip bonding structure of the chip
  • the second substrate bonding structure is configured to bond with the second chip bonding structure of the chip
  • the target substrate includes a laminated bonding layer and an alignment layer
  • the bonding layer includes a first substrate bonding structure and a second substrate bonding structure
  • the alignment layer has a first alignment opening And a second alignment opening
  • the first alignment bonding structure includes the first substrate bonding structure and the first alignment opening
  • the second alignment bonding structure includes the second substrate bond The joint structure and the second alignment opening
  • the first alignment opening is used to bond the first substrate bonding structure to the first chip bonding structure
  • the second alignment opening is used to make the second substrate bonding structure and the first chip bonding structure bond.
  • the second chip bonding structure is bonded.
  • the first substrate bonding structure is at least partially exposed through the first alignment hole opening
  • the second substrate bonding structure is at least partially exposed through the second alignment opening
  • the first chip The size of the bonding structure is smaller than the size of the first alignment opening
  • the size of the second chip bonding structure is smaller than the size of the second alignment opening and larger than the size of the first alignment opening
  • the The distance between the first chip bonding structure and the second chip bonding structure is equal to the distance between the first alignment opening and the second alignment opening.
  • the first alignment opening is an alignment hole
  • the second alignment opening is an alignment slit
  • the size of the first chip bonding structure is smaller than the aperture of the first alignment opening
  • the size of the second chip bonding structure is smaller than the width of the second alignment opening and larger than the aperture of the first alignment opening.
  • the orthographic projection of the first substrate bonding structure on the alignment layer covers the first alignment opening
  • the orthographic projection of the second substrate bonding structure on the alignment layer covers The second alignment opening
  • the first substrate bonding structure is a columnar structure
  • the second substrate bonding structure is an annular structure
  • the first alignment opening is an alignment hole
  • the second alignment opening is an annular structure. Aligning slit, the first substrate bonding structure is located at the center of the ring of the second substrate bonding structure, and the first alignment opening is located at the center of the ring of the second alignment opening;
  • the height of the first substrate bonding structure is equal to the height of the second substrate bonding structure, and the aperture of the first alignment opening is smaller than the width of the second alignment opening;
  • the shape of the opening surface of the first alignment opening is the same as the shape of the bottom surface of the first substrate bonding structure, and the aperture of the first alignment opening is less than or equal to that of the bottom surface of the first substrate bonding structure. size;
  • the shape of the opening surface of the second alignment opening is the same as the shape of the bottom surface of the second substrate bonding structure, and the width of the second alignment opening is less than or equal to the width of the second substrate bonding structure.
  • the first substrate bonding structure is a cylindrical structure
  • the second substrate bonding structure is an annular structure
  • the first alignment opening is a circular alignment hole
  • the second pair The position opening is a circular ring alignment seam
  • the aperture of the first alignment opening is smaller than or equal to the diameter of the first substrate bonding structure, and the width of the second alignment opening is smaller than or equal to the width of the second substrate bonding structure.
  • FIG. 1 is a schematic cross-sectional structure diagram of a chip provided by an embodiment of the present application.
  • Fig. 2 is a schematic front view of the structure of the chip shown in Fig. 1;
  • FIG. 3 is a schematic cross-sectional structure diagram of another chip provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the front view structure of the chip shown in FIG. 3;
  • FIG. 5 is a schematic cross-sectional structure diagram of a target substrate provided by an embodiment of the present application.
  • FIG. 6 is a schematic front view of the structure of the target substrate shown in FIG. 5;
  • FIG. 7 is a schematic cross-sectional structure diagram of another target substrate provided by an embodiment of the present application.
  • FIG. 8 is a method flowchart of a chip transfer method provided by an embodiment of the present application.
  • 9 to 13 are schematic diagrams of a chip transfer process provided by an embodiment of the present application.
  • Micro LED technology is a new type of display technology that can be applied to display products such as TVs, iPhones (Apple mobile phones) and iPads (Apple tablet computers).
  • Micro LED chips are nano-level LED chips.
  • Micro LED chips are usually formed on a sapphire substrate (hereinafter referred to as a source substrate) by molecular beam epitaxy.
  • the size of the sapphire substrate is usually the size of the silicon wafer. It is smaller, and the size of the display product is usually larger. Therefore, when preparing the display product, it is necessary to transfer the Micro LED chip from the source substrate to the target substrate.
  • the target substrate may be a flexible substrate (also referred to as a flexible substrate) or a rigid substrate (such as a glass substrate).
  • Micro LED technology is not the preparation of Micro LED chips, but the transfer of Micro LED chips.
  • the massive transfer of Micro LED chips has always been a technical bottleneck for industrial development.
  • the most commonly used technology to transfer Micro LED chips is the micro transfer printing (English: Micro Transfer Printing; abbreviated as: ⁇ TP) technology.
  • ⁇ TP Micro Transfer Printing
  • the ⁇ TP technology was originally developed by John A. Rogers of the University of Illinois in the United States and others using the sacrificial layer wet etching and polymerization.
  • Methylsiloxane (English: polydimethylsiloxane; abbreviation: PDMS) transfer technology, transfer Micro LED chips to the target substrate to produce Micro LED chip array technology, this technology was Spin-out (transferred) to Semprius in 2006, In 2013, X-Celeprint obtained the Semprius technology license and officially started operations in early 2014.
  • the transfer equipment used in ⁇ TP technology includes a print head and an elastic stamp (English: stamp). In simple terms, the transfer process is to use an elastic stamp in combination with the print head to selectively pick up Micro LED chips from the source substrate and pick up The Micro LED chip is printed to the target substrate.
  • a sacrificial layer (English: sacrificial layer) and a Micro LED chip are fabricated on the source substrate (such as the "source” wafer), and the sacrificial layer is located between the source substrate and the Micro LED chip; then, by removing the sacrificial layer The layer “releases” the Micro LED chip (English: release), so that the Micro LED chip is separated from the source substrate; then, the print head is used to cooperate with the elastic stamp (the elastic stamp has a microstructure that matches the "source” wafer). The source substrate picks up the Micro LED chip; finally, the picked up Micro LED chip is printed on the target substrate.
  • the source substrate picks up the Micro LED chip; finally, the picked up Micro LED chip is printed on the target substrate.
  • the adhesion force between the elastic stamp and the Micro LED chip can be selectively adjusted to control the transfer process of the Micro LED chip.
  • the adhesive force between the elastic stamp and the Micro LED chip is larger, which causes the Micro LED chip to separate from the source substrate; when the elastic stamp moves slowly, between the elastic stamp and the Micro LED chip
  • the adhesion force of the Micro LED chip is small, so that the Micro LED chip is separated from the elastic mold and printed on the target substrate. Among them, it is possible to transfer multiple Micro LED chips at a time by customizing the design of the elastic stamp.
  • the embodiments of the present application provide a chip transfer method, a display device, a chip, and a target substrate. Insulating fluid combined with electrostatic adsorption force can be used to realize the alignment of the chip and the target substrate, and the microfluidic technology can be used to realize batch transfer of chips. Micro LED chip transfer. Compared with the ⁇ TP technology, the solution provided by the embodiment of the present application helps to improve the transfer efficiency of the chip, and can reduce the transfer cost to a certain extent. The detailed solution of the application is described below in conjunction with the drawings.
  • the embodiment of the present application provides a chip.
  • the chip may include a chip body and a first chip bonding structure and a second chip bonding structure on the chip body.
  • the first chip bonding structure is configured to be connected to a target substrate.
  • the first alignment bonding structure is bonded
  • the second chip bonding structure is configured to bond with the second alignment bonding structure of the target substrate.
  • the first chip bonding structure and the second chip bonding structure may be distributed in the same layer.
  • the chip may include a bonding layer on the chip body, and the bonding layer may include a first chip bonding structure and a second chip bonding structure.
  • the first chip bonding structure may be a columnar structure
  • the second chip bonding structure may be a columnar structure or a ring structure.
  • both the first chip bonding structure and the second chip bonding structure are columnar structures.
  • FIG. 1 shows a schematic cross-sectional structure diagram of a chip 01 provided by an embodiment of the present application.
  • the chip 01 includes a chip main body 011 and a first chip bonding structure 012 and The second chip bonding structure 013, the first chip bonding structure 012 and the second chip bonding structure 013 are distributed in the same layer, and the size of the first chip bonding structure 012 is different from the size of the second chip bonding structure 013.
  • both the first chip bonding structure 012 and the second chip bonding structure 013 may be columnar structures, and the bottom surface of the first chip bonding structure 012 (for example, the side of the first chip bonding structure 012 away from the chip body 01)
  • the shape of the bottom surface of the second chip bonding structure 013 (for example, the side of the second chip bonding structure 013 away from the chip body 01) may be the same shape, and the size of the bottom surface of the first chip bonding structure 012 may be smaller than that of the second chip bonding structure.
  • the size of the bottom surface of the bonding structure 013, the height h012 of the first chip bonding structure 012 and the height h013 of the second chip bonding structure 013 may be equal.
  • both the first chip bonding structure 012 and the second chip bonding structure 013 may be cylindrical structures, and the first The size of the bottom surface of the chip bonding structure 012 may refer to the diameter D012 of the first chip bonding structure 012, and the size of the bottom surface of the second chip bonding structure 013 may refer to the diameter D013 of the second chip bonding structure 013.
  • the diameter D012 of the chip bonding structure 012 may be smaller than the diameter D013 of the second chip bonding structure 013.
  • the chip 01 may further include: a weight body 014, which is distributed in the same layer as the second chip bonding structure 013, because the first chip bonding structure 012 and the second chip bonding structure 013
  • the structure 013 can be distributed in the same layer, so the weight 014, the first chip bonding structure 012 and the second chip bonding structure 013 can be distributed in the same layer.
  • the weight 014 is used to make the center of gravity of the chip 01 coincide with the center of the chip 01.
  • the weight body 014 may have a columnar structure, the height h014 of the weight body 014 may be smaller than the height h013 of the second chip bonding structure 013, and the size of the bottom surface of the weight body 014 (for example, the side of the weight body 014 away from the chip body 01) It may be larger than the size of the bottom surface of the second die bonding structure 013. 1 and 2, the weight body 014 may have a cylindrical structure, the size of the bottom surface of the weight body 014 may be equal to the diameter D014 of the weight body 014, and the diameter D014 of the weight body 014 may be larger than the diameter D013 of the second chip bonding structure 013 .
  • the longitudinal cross sections of the first chip bonding structure 012, the second chip bonding structure 013, and the weight body 014 may be coplanar, and the first chip bonding structure 012, the The longitudinal interface of any one of the two-chip bonding structure 013 and the weight body 014 may be perpendicular to the surface of the chip body 011.
  • the first chip bonding structure 012 and the second chip bonding structure 013 may also be a prismatic structure.
  • the prismatic structure may be, for example, a hexagonal prism structure, a triangular prism structure or a quadrangular prism structure.
  • the first chip bonding structure 012, the second chip bonding structure 013 and The structure of the weight 014 may be the same or different.
  • the weight body 014 can be a weight body of any structure, as long as the center of gravity of the chip 01 coincides with the center of the chip 01.
  • the first chip bonding structure is a columnar structure
  • the second chip bonding structure is a ring structure.
  • FIG. 3 shows a schematic cross-sectional structure diagram of another chip 01 provided by an embodiment of the present application.
  • the chip 01 includes a chip main body 011 and a first chip bonding structure 012 located on the chip main body 011 It is distributed in the same layer as the second chip bonding structure 013, the first chip bonding structure 012 and the second chip bonding structure 013.
  • the first chip bonding structure 012 may be a columnar structure
  • the second chip bonding structure 013 may be a ring structure
  • the first chip bonding structure 012 may be located at the center of the ring of the second chip bonding structure 013,
  • the height h012 of the first chip bonding structure 012 and the height h013 of the second chip bonding structure 013 may be equal.
  • FIG. 4 is a front view structural diagram of the chip 01 shown in FIG. 3.
  • the first chip bonding structure 012 may be a cylindrical structure
  • the second chip bonding structure 013 may be a circular ring ⁇ Like structure.
  • the diameter D012 of the first chip bonding structure 012 may be greater than the width w013 of the second chip bonding structure 013, may also be equal to the width w013 of the second chip bonding structure 013, or may be smaller than that of the second chip bonding structure 013.
  • the width w013 is not limited in the embodiment of the present application.
  • first chip bonding structure 012 and the second chip bonding structure 013 in FIGS. 3 and 4 is exemplary, and the first chip bonding structure 012 may also be a prismatic structure, for example, the first chip
  • the bonding structure 012 may be a hexagonal prism structure, a triangular prism structure or a quadrangular prism structure, etc.
  • the second chip bonding structure 013 may also be other ring structures, for example, the second chip bonding structure 013 may be a six Edge ring structure, three-sided ring structure or four-sided ring structure, etc.
  • the chip main body 011 may have a columnar structure, and the axis of the first chip bonding structure 012 and the axis of the chip main body 011 may be collinear.
  • the chip main body 011 may have a cylindrical structure.
  • the height direction of the first chip bonding structure 012, the height direction of the second chip bonding structure 013, and the height direction of the weight 014 may all be parallel to the height direction of the chip 01 h.
  • the height of any structure is the size of the structure in the direction h parallel to the height.
  • the chip 01 may be a light-emitting chip
  • the chip body 011 may include a base substrate and a light-emitting unit and an encapsulation layer sequentially located on the base substrate.
  • the light-emitting unit may include two stacked electrodes and
  • the above-mentioned two chip bonding structures (the first chip bonding structure 012 and the second chip bonding structure 013) can be electrically connected to the two electrodes of the light-emitting unit in a one-to-one correspondence.
  • Each chip bonding structure is used to bond with the substrate bonding structure of the target substrate when the chip 01 is transferred to the target substrate.
  • the above two electrodes may include an anode and a cathode
  • the first chip bonding structure 012 may be an anode bonding structure
  • the first chip bonding structure 012 may be electrically connected to the anode of the chip 01
  • the first chip bonding structure 012 Used for bonding with the anode bonding structure of the target substrate
  • the second chip bonding structure 013 may be a cathode bonding structure
  • the second chip bonding structure 013 may be electrically connected to the cathode of the chip 01
  • the second chip bonding structure 013 Used to bond with the cathode bonding structure of the target substrate.
  • the anode bonding structure is also called anode pad
  • the cathode bonding structure is also called cathode pad.
  • the chip 01 may be an LED chip, for example, the chip 01 may be a Micro LED chip, and the light-emitting unit may be a Micro LED.
  • the material of the first chip bonding structure 012 and the material of the second chip bonding structure 013 are both conductive materials, and the material of the first chip bonding structure 012 and the material of the second chip bonding structure 013 Can be the same or different.
  • both the material of the first chip bonding structure 012 and the material of the second chip bonding structure 013 may be metal materials, such as metal Mo (Chinese: molybdenum), metal Cu (Chinese: copper), metal Al (Chinese: Aluminum) and its alloy materials, or the material of the first chip bonding structure 012 and the material of the second chip bonding structure 013 may both be semiconductor oxides, such as indium tin oxide (English: Indium tin oxide; abbreviation: ITO), indium zinc oxide (English: Indium zinc oxide; abbreviation: IZO), or aluminum-doped zinc oxide (English: aluminum-doped zinc oxide; abbreviation: ZnO:Al), etc.
  • ITO Indium tin oxide
  • IZO indium zinc oxide
  • ZnO aluminum-doped zinc oxide
  • the material of the weight 014 can be an insulating material such as SiNx (Chinese: silicon oxide), SiO 2 (Chinese: silicon dioxide), Al 2 O 3 (Chinese: alumina), or organic resin.
  • the first chip bonding structure 012 and the second chip bonding structure 013 can be prepared by photolithography or electroplating, and the weight 014 can be prepared by photolithography.
  • FIG. 5 shows a schematic cross-sectional structure diagram of a target substrate 02 provided by an embodiment of the present application.
  • the target substrate 02 includes a base substrate 021 and a first pair on the base substrate 021.
  • the first alignment bonding structure 023K is configured to bond with the first chip bonding structure of the chip
  • the second alignment bonding structure 024F is configured to bond with the second chip bonding structure of the chip.
  • the target substrate 02 includes a bonding layer (not shown in FIG. 5) and an alignment layer 022 laminated on the base substrate 021, and the bonding layer includes a first substrate bonding structure 023
  • the alignment layer 022 has a first alignment opening K and a second alignment opening F
  • the first alignment bonding structure 023K includes a first substrate bonding structure 023 and a first alignment opening K
  • the second alignment bonding structure 024F includes a second substrate bonding structure 024 and a second alignment opening F.
  • the first alignment opening K is used to make the first substrate bonding structure 023 and the first chip bonding structure
  • the second alignment opening F is used to bond the second substrate bonding structure 024 to the second chip bonding structure.
  • the first substrate bonding structure 023 is at least partially exposed through the first alignment opening K
  • the second substrate bonding structure 024 is at least partially exposed through the second alignment opening F
  • the first alignment The size of the opening K and the size of the second alignment opening F may be different.
  • the size of the first chip bonding structure is smaller than the size of the first alignment opening K
  • the size of the second chip bonding structure is smaller than the size of the second alignment opening F and larger than the size of the first alignment opening K
  • the distance between the first chip bonding structure and the second chip bonding structure is equal to the distance between the first alignment opening K and the second alignment opening F.
  • the first alignment opening K can facilitate the A substrate bonding structure 023 is bonded to the first chip bonding structure
  • the second alignment opening F makes the second substrate bonding structure 024 bond to the second chip bonding structure.
  • the orthographic projection of the first substrate bonding structure 023 on the alignment layer 022 may cover the first alignment opening K
  • the orthographic projection of the second substrate bonding structure 024 on the alignment layer 022 may cover the second alignment.
  • the positioning opening F can facilitate the first substrate bonding structure 023 to be exposed through the first alignment opening K as much as possible, and the second substrate bonding structure 024 to be exposed through the second alignment opening F as much as possible.
  • the first alignment opening K may be an alignment hole
  • the second alignment opening F may be an alignment slit
  • the size of the first chip bonding structure is smaller than the aperture DK of the first alignment opening K
  • the second The size of the chip bonding structure may be smaller than the width wF of the second alignment opening F and larger than the aperture DK of the first alignment opening K, so that the first chip bonding structure can easily enter the first alignment opening K.
  • the bonding structure enters the second alignment opening F and cannot enter the first alignment opening K, thereby ensuring that the first alignment opening K enables the first substrate bonding structure 023 to be bonded to the first chip bonding structure, and the second alignment The opening F makes the second substrate bonding structure 024 bond with the second chip bonding structure.
  • the first substrate bonding structure 023 may be a columnar structure
  • the second substrate bonding structure 024 may be a ring structure
  • the first substrate bonding structure 023 may be located at the center of the ring of the second substrate bonding structure 024
  • the first alignment opening K may be an alignment hole
  • the second alignment opening F may be an annular alignment slit
  • the first alignment opening K may be located at the center of the ring of the second alignment opening F
  • the height h023 of 023 and the height h024 of the second substrate bonding structure 024 may be equal
  • the size of the first alignment opening K may be the aperture DK of the first alignment opening K
  • the size of the second alignment opening F may be the second
  • the aperture DK of the first alignment opening K may be smaller than the width wF of the second alignment opening F
  • the shape of the opening surface of the first alignment opening K is the same as the bottom surface of the first substrate bonding structure 023 (
  • FIG. 6 is a front view structural diagram of the target substrate 02 shown in FIG. 5.
  • the first substrate bonding structure 023 may be a cylindrical structure
  • the second substrate bonding structure 024 may be a circle.
  • the first alignment opening K can be a circular alignment hole
  • the second alignment opening F can be a circular alignment slit
  • the aperture DK of the first alignment opening K can be less than or equal to the first substrate key
  • the width wF of the second alignment opening F may be less than or equal to the width w024 of the second substrate bonding structure 024.
  • the base substrate 021 may include two electrodes, and the two electrodes are connected to the two substrate bonding structures (the first substrate bonding structure 023 and the second substrate bonding structure 024).
  • the two substrate bonding structures are used to bond with the chip bonding structure when the chip is transferred to the target substrate 02.
  • the above two electrodes may include an anode and a cathode
  • the first substrate bonding structure 023 may be an anode bonding structure
  • the first substrate bonding structure 023 may be electrically connected to the anode of the base substrate 021
  • the first substrate bonding structure The structure 023 is used for bonding with the anode bonding structure of the chip
  • the second substrate bonding structure 024 may be a cathode bonding structure
  • the second substrate bonding structure 024 may be electrically connected to the cathode of the base substrate 021
  • the bonding structure 024 is used for bonding with the cathode bonding structure of the chip.
  • the anode bonding structure is also called anode pad
  • the cathode bonding structure is also called cathode pad.
  • the base substrate 021 may be a display backplane.
  • FIG. 7 shows a schematic cross-sectional structure diagram of another target substrate 02 provided in an embodiment of the present application.
  • the substrate 021 includes a glass substrate (or other rigid or flexible substrate) 0211 and a thin film transistor (English: Thin Film Transistor; abbreviation: TFT) 0222, a flat layer (abbreviation: PLN) 0223 and an electrode layer ( Figure 7), the electrode layer may include an anode 0224 and a cathode 0225, the TFT 0222 may include a gate, a gate insulating layer, an active layer, an interlayer dielectric layer, a source and a drain, and the base substrate 021 also includes data Line and cathode trace 0226, data line, cathode trace 0226, source and drain can be distributed in the same layer, data line can be electrically connected with source, flat layer 0223 can have anode via and cathode via, anode 0224
  • TFT Thin Film
  • the bonding layer may be located on the side of the electrode layer away from the flat layer 023, the first substrate bonding structure 023 may be electrically connected to the anode 0224, and the second substrate bonding structure 024 may be electrically connected to the cathode 0225.
  • the material of the first substrate bonding structure 023 and the material of the second substrate bonding structure 024 are both conductive materials, and the material of the first substrate bonding structure 023 and the material of the second substrate bonding structure 024 Can be the same or different.
  • the material of the first substrate bonding structure 023 and the material of the second substrate bonding structure 024 may both be metallic materials, such as metallic Mo, metallic Cu, metallic Al and their alloy materials, or the first Both the material of the substrate bonding structure 023 and the material of the second substrate bonding structure 024 may be semiconductor oxides, such as ITO, IZO, or ZnO:Al.
  • the material of the alignment layer 022 may be an organic insulating material, such as an organic resin.
  • the first substrate bonding structure 023 and the second substrate bonding structure 024 can be prepared by photolithography or electroplating, and the alignment layer 022 can be prepared by photolithography, which will not be repeated in the embodiments of the present application.
  • the chip transfer method provided by the embodiments of the application can be used to transfer chips from the source substrate to the target substrate. It may be the chip 01 shown in FIGS. 1 to 4, and the target substrate may be the target substrate 02 shown in FIGS. 5 to 7.
  • FIG. 8 shows a method flowchart of a chip transfer method provided by an embodiment of the present application.
  • the method includes the following steps:
  • a target substrate is set in a closed chamber, and the target substrate includes a first alignment bonding structure and a second alignment bonding structure.
  • a support frame may be provided in the airtight chamber, and the target substrate may be placed on the support frame, so that the target substrate is set in the airtight chamber.
  • the target substrate may include a first alignment bonding structure and a second alignment bonding structure.
  • the target substrate 02 includes a first alignment bonding structure 023K and a second alignment bonding structure 024F.
  • step 802 a charge of the first polarity is applied to the first alignment bonding structure of the target substrate.
  • the first alignment bonding structure may include a first substrate bonding structure and a first alignment opening, and a charge of the first polarity may be applied to the first substrate bonding structure, thereby bonding to the first alignment
  • the structure applies a charge of the first polarity.
  • the target substrate has a trace electrically connected to the first substrate bonding structure, and a charge of the first polarity can be applied to the first substrate bonding structure through the trace.
  • the first alignment bonding structure 023K includes a first substrate bonding structure 023 and a first alignment opening K, and the data line (not shown in FIG. 7) can pass through the TFT 0222 and the anode 0224.
  • first substrate bonding structure 023 It is electrically connected to the first substrate bonding structure 023, and a charge of the first polarity can be applied to the first substrate bonding structure 023 through a data line, thereby applying a charge of the first polarity to the first alignment bonding structure 023K.
  • the charge of the first polarity can also be applied to the second alignment bonding structure, or the second alignment is bonded
  • the structure is grounded.
  • the second alignment bonding structure may include a second substrate bonding structure and a second alignment opening, and a charge of the first polarity may be applied to the second substrate bonding structure or the second substrate bonding structure may be grounded, Thus, the charge of the first polarity is applied to the second alignment bonding structure or the second alignment bonding structure is grounded.
  • the target substrate has a trace electrically connected to the second substrate bonding structure, and the second substrate bonding structure can be applied with a charge of the first polarity through the trace or the second substrate bonding structure can be grounded.
  • the second alignment bonding structure 024F includes a second substrate bonding structure 024 and a second alignment opening F.
  • the cathode trace 0226 is electrically connected to the second substrate bonding structure 024, which can be The cathode trace 0226 applies a charge of the first polarity to the second substrate bonding structure 024 or grounds the second substrate bonding structure 024, thereby applying a charge of the first polarity to the second alignment bonding structure 024F or connects the second substrate bonding structure 024F.
  • the two-position bonding structure 024F is grounded.
  • step 803 a charge of the second polarity is applied to the first chip bonding structure of the chip.
  • the chip includes the second chip bonding structure and the first chip bonding structure, and the second polarity is different from the first polarity.
  • the chip may include a first chip bonding structure and a second chip bonding structure.
  • the chip 01 may include a first alignment bonding structure 012 and a second alignment bonding structure 013.
  • the charge of the second polarity may be applied to the second chip bonding structure, or the second chip bonding structure may not be applied.
  • the charge is applied, which is not limited in the embodiment of the present application.
  • step 804 an insulating fluid is injected into the airtight chamber to suspend the chip in the insulating fluid in the airtight chamber, wherein, under the action of the first chip bonding structure and the first alignment bonding structure, the chip approaches the target substrate Move so that the first chip bonding structure is in contact with the first alignment bonding structure, and the second chip bonding structure is in contact with the second alignment bonding structure.
  • the airtight chamber may have a fluid inlet, and an insulating fluid may be injected into the airtight chamber through the fluid inlet, so that the chip is suspended in the insulating fluid in the airtight chamber.
  • the first alignment bonding structure and the first chip bonding structure carry charges of different polarities, there is an attractive force between the first chip bonding structure and the first alignment bonding structure, and the attraction and the insulating fluid Under the effect of the suspension force, the first chip bonding structure moves closer to the first alignment bonding structure, driving the chip to move closer to the target substrate, making the first chip bonding structure contact the first alignment bonding structure, and the second chip The bonding structure is in contact with the second para-bonding structure. So far, the alignment of the chip and the target substrate can be completed.
  • the first alignment bonding structure may include a first substrate bonding structure and a first alignment opening
  • the second alignment bonding structure may include a second substrate bonding structure and a second alignment opening.
  • Applying a charge of the first polarity to the one-to-one bonding structure may apply a charge of the first polarity to the first substrate bonding structure, so the first substrate bonding structure and the first chip bonding structure may carry different polarities Charge, there is an attractive force between the first chip bonding structure and the first substrate bonding structure.
  • the chip moves closer to the target substrate, causing the first chip bonding structure to enter the first
  • the alignment opening is in contact with the first substrate bonding structure, and the second chip bonding structure enters the second alignment opening to contact the second substrate bonding structure.
  • the size of the first chip bonding structure may be smaller than the size of the first alignment opening
  • the size of the second chip bonding structure may be smaller than the size of the second alignment opening and larger than the size of the first alignment opening.
  • the distance between the first chip bonding structure and the second chip bonding structure can be equal to the distance between the first alignment opening and the second alignment opening, so the first chip bonding structure can enter the first alignment Opening, the second chip bonding structure can enter the second alignment opening but cannot enter the first alignment opening. While the first chip bonding structure enters the first alignment opening, the second chip bonding structure can enter the second alignment opening.
  • the alignment opening finally, the first chip bonding structure can contact the first substrate bonding structure through the first alignment opening, and the second chip bonding structure can contact the second substrate bonding structure through the second alignment opening.
  • the size of the first chip bonding structure 012 may be smaller than the size of the first alignment opening K
  • the size of the second chip bonding structure 013 may be smaller than the size of the second alignment opening F
  • the distance d1 between the first chip bonding structure 012 and the second chip bonding structure 013 may be equal to the distance d2 between the first alignment opening K and the second alignment opening F Therefore, the first chip bonding structure 012 can enter the first alignment opening K, and the second chip bonding structure 013 can enter the second alignment opening F but cannot enter the first alignment opening K.
  • the second chip bonding structure 013 can enter the second alignment opening F.
  • the first chip bonding structure 012 and the second chip bonding structure 013 are both cylindrical structures, the first chip bonding structure 012 and the second chip bonding structure The distance d1 between 013 may be the distance between the axis of the first chip bonding structure 012 and the axis of the second chip bonding structure 013. As shown in FIGS.
  • the first chip bonding structure 012 when the first chip bonding structure 012 is a cylindrical structure and the second chip bonding structure 013 is a circular ring structure, the first chip bonding structure 012 and the second chip bonding structure
  • the distance d1 between 013 may be the distance between the axis of the first chip bonding structure 012 and the middle plane M of the second chip bonding structure 013, and any point on the middle plane M and the second chip bonding structure
  • the distance between the inner ring of 013 is equal to the distance between this arbitrary point and the outer ring of the second chip bonding structure 013.
  • the distance d2 between the first alignment opening K and the second alignment opening F may be between the axis of the first alignment opening K and the median plane G of the second alignment opening F The distance between any point on the median plane G and the two side surfaces of the second alignment opening F are equal.
  • the airtight chamber may also have a fluid outlet. While the insulating fluid is injected into the airtight chamber through the fluid inlet, the insulating fluid can be drawn from the airtight chamber through the fluid outlet. In this way, the insulating fluid can be controlled in the airtight chamber The direction of flow.
  • injecting an insulating fluid into the airtight chamber to suspend the chip in the insulating fluid in the airtight chamber may include: first setting the chip in the airtight chamber, and then injecting the insulating fluid into the airtight chamber , Under the action of the insulating fluid, the chip is suspended in the insulating fluid in the sealed chamber; or, the chip is mixed with the insulating fluid first, and then the insulating fluid mixed with the chip is injected into the sealed chamber, so that the chip is suspended in the sealed chamber. Insulating fluid. It is easy to understand that the chip can also be suspended in the insulating fluid in the sealed chamber in other ways, which is not limited in the embodiment of the present application.
  • the chip may be grown on the source substrate, and the chip may be separated from the source substrate before the chip is placed in the sealed chamber.
  • the source substrate may have a sacrificial layer
  • the chip may be grown on the sacrificial layer
  • the sacrificial layer may be etched to separate the chip from the source substrate.
  • step 805 a bonding force is applied to the chip so that the first chip bonding structure is bonded to the first alignment bonding structure, and the second chip bonding structure is bonded to the second alignment bonding structure.
  • the chip After the first chip bonding structure is in contact with the first alignment bonding structure, and the second chip bonding structure is in contact with the second alignment bonding structure (that is, after the chip is aligned with the target substrate), the chip can be The bonding force is applied to bond the first chip bonding structure and the first alignment bonding structure, and the second chip bonding structure and the second alignment bonding structure are bonded, so far, the chip transfer is completed.
  • the contact between the first chip bonding structure and the first alignment bonding structure may be that the first chip bonding structure contacts the first substrate bonding structure through the first alignment opening
  • the second chip bonding The contact between the structure and the second alignment bonding structure may be that the second chip bonding structure contacts the second substrate bonding structure through the second alignment opening. Therefore, applying bonding force to the chip can make the first chip bonding structure and the first The substrate bonding structure is bonded, and the second chip bonding structure is bonded to the second substrate bonding structure.
  • a press-bonded substrate opposite to the target substrate may be provided in the sealed chamber, and pressure may be applied to the chip by pressing the substrate to bond the first chip-bonding structure to the first substrate-bonding structure, and the second chip-bonding structure The bonding structure is bonded to the second substrate bonding structure.
  • the target substrate is set in a closed chamber; the first polarity of charge is applied to the first alignment bonding structure of the target substrate; the first chip bonding structure of the chip Apply a charge of the second polarity, the second polarity is different from the first polarity; the insulating fluid is injected into the sealed chamber, so that the chip is suspended in the insulating fluid in the sealed chamber, in the first chip bonding structure and the first pair Under the action of the position bonding structure, the chip moves close to the target substrate, the first chip bonding structure contacts the first alignment bonding structure, and the second chip bonding structure contacts the second alignment bonding structure; bonding is applied to the chip
  • the combined force causes the first chip bonding structure to bond with the first alignment bonding structure, and the second chip bonding structure to bond with the second alignment bonding structure. Since the insulating fluid combined with the electrostatic adsorption force can be used to realize the alignment of the chip and the target substrate, it is helpful to realize the batch transfer of the chips
  • the solution provided by the embodiments of this application realizes the alignment of the chip and the target substrate based on the electrostatic adsorption force between the target substrate and the chip and the suspension force of the insulating fluid in the insulating fluid, which helps to achieve the high
  • the high-efficiency, low-cost, and high-precision alignment can be used for massive transfer of chips and reduce the cost of chip transfer.
  • FIGS. 9 to 13 are schematic diagrams of a chip transfer method provided by embodiments of the present application.
  • FIGS. 9 to 13 take the transfer of the chip 01 shown in FIG. 1 to the target substrate 02 shown in FIG. 5 as an example for description.
  • the target substrate 02 is set in a closed chamber (not shown in FIGS. 9 to 13), a positive charge is applied to the first substrate bonding structure 023, and the second substrate bonding structure 024 is grounded; A negative charge is applied to the first chip bonding structure 012 and the second chip bonding structure 013, and the chip 01 is placed in a sealed chamber; then an insulating fluid flowing in the direction X is injected into the sealed chamber, and the chip 01 is suspended in the insulating fluid in.
  • the chip 01 moves closer to the target substrate 02.
  • FIG. 12 The cross-sectional view after transferring the chip 01 shown in FIG. 1 to the target substrate 02 shown in FIG. 5 may be as shown in FIG. 12, and the front view may be as shown in FIG. 13, which is easy to understand, in order to clearly show the first chip bonding structure
  • the relationship between 012 and the first substrate bonding structure 023, and the relationship between the second chip bonding structure 013 and the second substrate bonding structure 024, the weight 014 and the chip body 011 are not shown in FIG.
  • the second chip bonding structure 013 since the size of the second chip bonding structure 013 is larger than the aperture DK of the first alignment opening K, the second chip bonding structure 013 cannot enter during the alignment process of the chip 01 and the target substrate 02
  • the first alignment opening K will appear as shown in FIG. 11.
  • the chip 01 will continue to flow with the insulating fluid until the first chip bonding structure 012 enters the first alignment opening K.
  • FIG. 14 to FIG. 17 are schematic diagrams of another chip transfer method provided by embodiments of the present application.
  • FIG. 14 to FIG. 17 take the transfer of the chip 01 shown in FIG. 3 to the target substrate shown in FIG. 5 as an example for description.
  • the target substrate 02 is set in a closed chamber (not shown in FIGS. 14 to 17), and a positive charge is applied to the first substrate bonding structure 023 and the second substrate bonding structure 024;
  • a chip bonding structure 012 and a second chip bonding structure 013 apply negative charges to place the chip 01 in a sealed chamber, and then inject the insulating fluid flowing in the direction X into the sealed chamber, and the chip 01 is suspended in the insulating fluid.
  • the chip 01 moves closer to the target substrate 02.
  • the size of the first chip bonding structure 012 is smaller than that of the first The aperture DK of the alignment opening K
  • the second chip bonding structure 013 is a ring structure centered on the first chip bonding structure 012, so the first chip bonding structure 012 can enter the first alignment opening K (as shown in Fig.
  • the second chip bonding structure 013 cannot enter the first alignment opening K; and because the size of the second chip bonding structure 013 is smaller than the width wF of the second alignment opening F, the first chip bonding structure 012
  • the distance d1 from the second chip bonding structure 013 is equal to the distance d2 between the first alignment opening K and the second alignment opening F. Therefore, as shown in FIG. 16, the first chip bonding structure 012 enters the first At the same time as the alignment opening K, the second chip bonding structure 013 enters the second alignment opening F, the first chip bonding structure 012 contacts the first substrate bonding structure 023 through the first alignment opening K, and the second chip The bonding structure 013 contacts the second substrate bonding structure 024 through the second alignment opening F. So far, the alignment of the chip 01 and the target substrate 02 is completed.
  • FIG. 16 The cross-sectional view after transferring the chip 01 shown in FIG. 3 to the target substrate 02 shown in FIG. 5 may be shown in FIG. 16, and the front view may be shown in FIG. 17, which is easy to understand, in order to clearly show the first chip bonding structure
  • the chip main body 011 is not shown in FIG.
  • an embodiment of the present application also provides a display device, which includes the target substrate and chip provided in the above embodiment, and the chip is transferred from the source substrate to the target substrate using the chip transfer method provided in the above embodiment.
  • the display device may be as shown in FIG. 12 and FIG. 13, or the display device may be as shown in FIG. 16 and FIG.
  • the display device can be any product or component with display function such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator or wearable device.
  • the display device includes a chip 01 and a target substrate 02.
  • the chip 01 includes a first chip bonding structure 012 and a second chip Bonding structure 013
  • the target substrate 02 includes a first alignment bonding structure 023K and a second alignment bonding structure 024F
  • the first chip bonding structure 012 is bonded to the first alignment bonding structure
  • the structure 023K is bonded
  • the second chip bonding structure 013 is bonded to the second alignment bonding structure 024F.
  • the target substrate 02 includes a laminated bonding layer and an alignment layer 022
  • the bonding layer includes a first substrate bonding structure 023 and the second substrate bonding structure 024
  • the alignment layer 022 has a first alignment opening K and a second alignment opening F
  • the first alignment bonding structure 023K includes a first substrate bonding structure 023 and a first alignment Opening K
  • the second alignment bonding structure 024F includes a second substrate bonding structure 024 and a second alignment opening F.
  • the first chip bonding structure 012 is bonded to the first substrate bonding structure 023 through the first alignment opening K
  • the second chip bonding structure 013 is bonded to the second substrate bonding structure 024 through the second alignment opening F.
  • the size of the first chip bonding structure 012 is smaller than the size of the first alignment opening K, and the second chip bonding structure 013
  • the size of is smaller than the size of the second alignment opening F and greater than the size of the first alignment opening K
  • the distance d1 between the first die bonding structure 012 and the second die bonding structure 013 is equal to the first alignment opening K and The distance d2 between the second alignment openings F.
  • the first alignment opening K is an alignment hole
  • the second alignment opening F is an alignment slit
  • the first chip key The size of the bonding structure 012 is smaller than the aperture DK of the first alignment opening K
  • the size of the second chip bonding structure 013 is smaller than the width wF of the second alignment opening F and larger than the aperture DK of the first alignment opening.
  • a chip bonding structure 012 enters the first alignment opening K, and the second chip bonding structure 013 enters the second alignment opening F and cannot enter the first alignment opening K, thereby ensuring that the first chip bonding structure 012 passes through the first
  • the alignment opening K is bonded to the first substrate bonding structure 023, and the second chip bonding structure 013 is bonded to the second substrate bonding structure 024 through the second alignment opening F.
  • the orthographic projection of the first substrate bonding structure 023 on the alignment layer 022 covers the first alignment opening K
  • the second The orthographic projection of the substrate bonding structure 024 on the alignment layer 022 covers the second alignment opening F, so that the first substrate bonding structure 023 can be exposed as much as possible through the first alignment opening K and bonded to the first chip.
  • the bonding structure 012 is in contact
  • the second substrate bonding structure 024 is exposed through the second alignment opening F as much as possible and is in contact with the second chip bonding structure 013 to ensure effective bonding of the chip 01 and the target substrate 02.
  • the first chip bonding structure 012, the second chip bonding structure 013, and the first substrate bonding structure 023 may all be Columnar structure
  • the second substrate bonding structure 024 may be a ring structure
  • the first alignment opening K may be an alignment hole
  • the second alignment opening F may be an annular alignment slit
  • the first substrate bonding structure 023 may be located In the center of the ring of the second substrate bonding structure 024, the first alignment opening K may be located at the center of the ring of the second alignment opening F.
  • the size of the bottom surface of the first chip bonding structure 012 may be smaller than the aperture DK of the first alignment opening K, and the size of the bottom surface of the second chip bonding structure 013 may be larger than the aperture DK of the first alignment opening K and smaller than the second pair
  • the width wF of the position opening F can facilitate the first chip bonding structure 012 to enter the first alignment opening K, and the second chip bonding structure 013 to enter the second alignment opening F.
  • the height h012 of the first chip bonding structure 012 and the height h013 of the second chip bonding structure 013 may be equal, and the height h023 of the first substrate bonding structure 023 and the height h024 of the second substrate bonding structure 024 may be equal, such that Then, when the first chip bonding structure 012 is in contact with the first substrate bonding structure 023, the second chip bonding structure 013 is in contact with the second substrate bonding structure 024.
  • the shape of the opening surface of the first alignment opening K may be the same as the shape of the bottom surface of the first substrate bonding structure 023, and the aperture DK of the first alignment opening K may be smaller than Or equal to the size of the bottom surface of the first substrate bonding structure 023, the shape of the opening surface of the second alignment opening F and the ring shape of the second substrate bonding structure 024 can be the same, and the width wF of the second alignment opening F can be Is less than or equal to the width of the second substrate bonding structure 024. In this way, it can be ensured that the first chip bonding structure 012 can fully contact the first substrate bonding structure 023, and the second substrate bonding structure 024 can be The substrate bonding structure 024 is in full contact.
  • the first chip bonding structure 012, the second chip bonding structure 013, and the first substrate bonding structure 023 may all be cylindrical structures, and the second substrate
  • the bonding structure 024 may be an annular structure, the first alignment opening K may be a circular alignment hole, and the second alignment opening F may be a circular alignment slit;
  • the diameter D012 of the first chip bonding structure 012 It can be smaller than the aperture DK of the first alignment opening K, and the diameter D013 of the second chip bonding structure 013 can be greater than the aperture DK of the first alignment opening K and smaller than the width wF of the second alignment opening F;
  • the aperture DK of K may be less than or equal to the diameter D023 of the first substrate bonding structure 023, and the width wF of the second alignment opening F may be less than or equal to the width w024 of the second substrate bonding structure 024.
  • the chip 01 further includes: a weight body 014 distributed in the same layer as the second chip bonding structure 013, and the weight body is used to make the center of gravity of the chip 01 and The centers of chip 01 coincide.
  • the longitudinal cross sections of the first chip bonding structure 012, the second chip bonding structure 013, and the weight body 014 are coplanar.
  • the first chip bonding structure 012 and the first substrate bonding structure 023 are both columnar structures, and the second chip bonding structure 013 is bonded to the second substrate
  • the structures 024 are all ring structures
  • the first alignment opening K is an alignment hole
  • the second alignment opening F is an annular alignment slit
  • the first chip bonding structure 012 is located at the center of the ring of the second chip bonding structure 013
  • the first substrate bonding structure 023 is located at the center of the ring of the second substrate bonding structure 024
  • the first alignment opening K is located at the center of the ring of the second alignment opening F
  • the size of the bottom surface of the first chip bonding structure 012 It is smaller than the aperture DK of the first alignment opening K
  • the width w013 of the second chip bonding structure 013 is smaller than the width wF of the second alignment opening F, so that the first chip bonding structure 012 can easily enter the first alignment Opening K, the second chip bonding
  • the height h012 of the first chip bonding structure 012 is equal to the height h013 of the second chip bonding structure 013, and the height h023 of the first substrate bonding structure 023 is the same as the height h024 of the second substrate bonding structure 024. In this way, It is convenient for the first chip bonding structure 012 to contact the first substrate bonding structure 023 while the second chip bonding structure 013 contacts the second substrate bonding structure 024.
  • the shape of the opening surface of the first alignment opening K is the same as the shape of the bottom surface of the first substrate bonding structure 023, and the aperture of the first alignment opening K DK is less than or equal to the size of the bottom surface of the first substrate bonding structure 023;
  • the shape of the opening surface of the second alignment opening F is the same as the ring shape of the second substrate bonding structure 024, and the width of the second alignment opening F is wF It is less than or equal to the width w024 of the second substrate bonding structure 024.
  • the first chip bonding structure 012 and the first substrate bonding structure 023 are both cylindrical structures, and the second chip bonding structure 013 and the second substrate bonding
  • the bonding structures 024 are all circular structures, the first alignment opening K is a circular alignment hole, and the second alignment opening F is a circular alignment slit; the diameter D012 of the first die bonding structure 012 is smaller than the first The aperture DK of the alignment opening K, the width w013 of the second chip bonding structure 013 is smaller than the width wF of the second alignment opening F; the aperture DK of the first alignment opening K is less than or equal to the diameter of the first substrate bonding structure 023 D023, the width wF of the second alignment opening F is less than or equal to the width of the second substrate bonding structure 024.
  • electrically connected refers to connection and capable of transferring charges, but not necessarily charge transfer.
  • a and B are electrically connected to indicate that A and B are connected and A and B can transfer charges, but A and B There is not necessarily charge transfer between B.

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Abstract

一种芯片转移方法、显示装置、芯片及目标基板。将目标基板设置在密闭腔室内，目标基板包括第一对位键合结构和第二对位键合结构；向第一对位键合结构施加第一极性的电荷；向芯片的第一芯片键合结构施加第二极性的电荷，芯片包括第一芯片键合结构和第二芯片键合结构，第二极性与第一极性不同；向密闭腔室内注入绝缘流体，使芯片悬浮于绝缘流体中，在第一芯片键合结构和第一对位键合结构的作用下，芯片靠近目标基板移动，第一芯片键合结构与第一对位键合结构接触，第二芯片键合结构与第二对位键合结构接触；向芯片施加键合力，使第一芯片键合结构与第一对位键合结构键合，第二芯片键合结构与第二对位键合结构键合。本申请有助于提高芯片转移效率。

Description

芯片转移方法、显示装置、芯片及目标基板
本申请要求于2019年04月24日提交的申请号为201910333482.5、发明名称为“芯片转移方法、芯片及目标基板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及一种芯片转移方法、显示装置、芯片及目标基板。
背景技术
微型发光二极管(英文：Micro Light Emitting Diode；简称：Micro LED/μ LED)芯片是一种新型的LED芯片，具有亮度高、发光效率高以及功耗低等优点，在显示行业具有广泛的应用前景。Micro LED芯片通常在蓝宝石类基板(以下称为源基板)上形成，使用时需要将Micro LED芯片从源基板转移至目标基板(例如显示背板)。
发明内容
本申请提供一种芯片转移方法、显示装置、芯片及目标基板。技术方案如下：
第一方面，提供一种芯片转移方法，包括：
将目标基板设置在密闭腔室内，所述目标基板包括第一对位键合结构和第二对位键合结构；
向所述目标基板的所述第一对位键合结构施加第一极性的电荷；
向芯片的第一芯片键合结构施加第二极性的电荷，所述芯片包括第二芯片键合结构和所述第一芯片键合结构，所述第二极性与所述第一极性不同；
向所述密闭腔室内注入绝缘流体，使所述芯片悬浮于所述密闭腔室内的所述绝缘流体中，其中，在所述第一芯片键合结构和所述第一对位键合结构的作用下，所述芯片靠近所述目标基板移动，使所述第一芯片键合结构与所述第一对位键合结构接触，所述第二芯片键合结构与所述第二对位键合结构接触；
向所述芯片施加键合力，使所述第一芯片键合结构与所述第一对位键合结 构键合，所述第二芯片键合结构与所述第二对位键合结构键合。
可选地，所述方法还包括：
向所述目标基板的所述第二对位键合结构施加所述第一极性的电荷，以及，向所述芯片的所述第二芯片键合结构施加所述第二极性的电荷；或者，
将所述目标基板的所述第二对位键合结构接地，以及，向所述芯片的所述第二芯片键合结构施加所述第二极性的电荷。
可选地，向所述密闭腔室内注入绝缘流体，使所述芯片悬浮于所述密闭腔室内的所述绝缘流体中，包括：
将所述芯片设置在所述密闭腔室内，并向所述密闭腔室内注入绝缘流体，使所述芯片悬浮于所述密闭腔室内的所述绝缘流体中；或者，
将所述芯片与绝缘流体混合，并向所述密闭腔室内注入混合有所述芯片的所述绝缘流体，使所述芯片悬浮于所述密闭腔室内的所述绝缘流体中。
可选地，在向所述密闭腔室内注入绝缘流体，使所述芯片悬浮于所述密闭腔室内的所述绝缘流体中之前，所述方法还包括：
将所述芯片与所述源基板分离。
可选地，所述目标基板包括层叠的键合层和对位层，所述键合层包括第一基板键合结构和第二基板键合结构，所述对位层具有第一对位开口和第二对位开口，所述第一对位键合结构包括所述第一基板键合结构和所述第一对位开口，所述第二对位键合结构包括所述第二基板键合结构和所述第二对位开口，
向所述目标基板的所述第一对位键合结构施加第一极性的电荷，包括：
向所述目标基板的所述第一基板键合结构施加所述第一极性的电荷，其中，在所述第一芯片键合结构和所述第一基板键合结构的作用下，所述芯片靠近所述目标基板移动，所述第一芯片键合结构进入所述第一对位开口与所述第一基板键合结构接触，所述第二芯片键合结构进入所述第二对位开口与所述第二基板键合结构接触。
第二方面，提供一种显示装置，包括：芯片和目标基板，
所述芯片包括第一芯片键合结构和第二芯片键合结构，所述目标基板包括第一对位键合结构和第二对位键合结构，所述第一芯片键合结构与所述第一对位键合结构键合，所述第二芯片键合结构与所述第二对位键合结构键合。
可选地，所述目标基板包括层叠的键合层和对位层，所述键合层包括第一基板键合结构和第二基板键合结构，所述对位层具有第一对位开口和第二对位 开口，所述第一对位键合结构包括所述第一基板键合结构和所述第一对位开口，所述第二对位键合结构包括所述第二基板键合结构和所述第二对位开口，
所述第一芯片键合结构通过所述第一对位开口与所述第一基板键合结构键合，所述第二芯片键合结构通过所述第二对位开口与所述第二基板键合结构键合。
可选地，所述第一芯片键合结构的尺寸小于所述第一对位开口的尺寸，所述第二芯片键合结构的尺寸小于所述第二对位开口的尺寸且大于所述第一对位开口的尺寸，所述第一芯片键合结构与所述第二芯片键合结构之间的距离等于所述第一对位开口与所述第二对位开口之间的距离。
可选地，所述第一对位开口为对位孔，所述第二对位开口为对位缝，所述第一芯片键合结构的尺寸小于所述第一对位开口的孔径，所述第二芯片键合结构的尺寸小于所述第二对位开口的宽度且大于所述第一对位开口的孔径。
可选地，所述第一基板键合结构在所述对位层上的正投影覆盖所述第一对位开口，所述第二基板键合结构在所述对位层上的正投影覆盖所述第二对位开口。
可选地，所述第一芯片键合结构、所述第二芯片键合结构和所述第一基板键合结构均为柱状结构，所述第二基板键合结构为环状结构，所述第一对位开口为对位孔，所述第二对位开口为环形对位缝，所述第一基板键合结构位于所述第二基板键合结构的环形的中心，所述第一对位开口位于所述第二对位开口的环形的中心；
所述第一芯片键合结构的底面的尺寸小于所述第一对位开口的孔径，所述第二芯片键合结构的底面的尺寸大于所述第一对位开口的孔径且小于所述第二对位开口的宽度；
所述第一芯片键合结构的高度与所述第二芯片键合结构的高度相等，所述第一基板键合结构的高度与所述第二基板键合结构的高度相等；
所述第一对位开口的开口面的形状与所述第一基板键合结构的底面的形状相同，所述第一对位开口的孔径小于或等于所述第一基板键合结构的底面的尺寸；
所述第二对位开口的开口面的形状与所述第二基板键合结构的环形的形状相同，所述第二对位开口的宽度小于或等于所述第二基板键合结构的宽度。
可选地，所述第一芯片键合结构、所述第二芯片键合结构和所述第一基板 键合结构均为圆柱状结构，所述第二基板键合结构为圆环状结构，所述第一对位开口为圆形孔，所述第二对位开口为圆环形缝；
所述第一芯片键合结构的直径小于所述第一对位开口的孔径，所述第二芯片键合结构的直径大于所述第一对位开口的孔径且小于所述第二对位开口的宽度；
所述第一对位开口的孔径小于或等于所述第一基板键合结构的直径，所述第二对位开口的宽度小于或等于所述第二基板键合结构的宽度。
可选地，所述芯片还包括：与所述第二芯片键合结构同层分布的配重体，所述配重体用于使所述芯片的重心与所述芯片的中心重合。
可选地，所述第一芯片键合结构、所述第二芯片键合结构和所述配重体这三者的纵轴截面共面。
可选地，所述第一芯片键合结构和所述第一基板键合结构均为柱状结构，所述第二芯片键合结构和所述第二基板键合结构均为环状结构，所述第一对位开口为对位孔，所述第二对位开口为为环形对位缝，所述第一芯片键合结构位于所述第二芯片键合结构的环形的中心，所述第一基板键合结构位于所述第二基板键合结构的环形的中心，所述第一对位开口位于所述第二对位开口的环形的中心；
所述第一芯片键合结构的底面的尺寸小于所述第一对位开口的孔径，所述第二芯片键合结构的宽度小于所述第二对位开口的宽度；
所述第一芯片键合结构的高度与所述第二芯片键合结构的高度相等，所述第一基板键合结构的高度与所述第二基板键合结构的高度相等；
所述第一对位开口的开口面的形状与所述第一基板键合结构的底面的形状相同，所述第一对位开口的孔径小于或等于所述第一基板键合结构的底面的尺寸；
所述第二对位开口的开口面的形状与所述第二基板键合结构的环形的形状相同，所述第二对位开口的宽度小于或等于所述第二基板键合结构的宽度。
可选地，所述第一芯片键合结构和所述第一基板键合结构均为圆柱状结构，所述第二芯片键合结构和所述第二基板键合结构均为圆环状结构，所述第一对位开口为圆形对位孔，所述第二对位开口为圆环形对位缝；
所述第一芯片键合结构的直径小于所述第一对位开口的孔径，所述第二芯片键合结构的宽度小于所述第二对位开口的宽度；
所述第一对位开口的孔径小于或等于所述第一基板键合结构的直径，所述第二对位开口的宽度小于或等于所述第二基板键合结构的宽度。
第三方面，提供一种芯片，包括：
芯片主体以及位于所述芯片主体上的第一芯片键合结构和第二芯片键合结构；
所述第一芯片键合结构被配置为与目标基板的第一对位键合结构键合，所述第二芯片键合结构被配置为与所述目标基板的第二对位键合结构键合。
可选地，所述第一芯片键合结构和所述第二芯片键合结构均为柱状结构，所述第一芯片键合结构的底面的形状与所述第二芯片键合结构的底面的形状相同，所述第一芯片键合结构的底面的尺寸小于所述第二芯片键合结构的底面的尺寸，所述第一芯片键合结构的高度与所述第二芯片键合结构的高度相等。
可选地，所述第一芯片键合结构和所述第二芯片键合结构均为圆柱状结构，所述第一芯片键合结构的直径小于所述第二芯片键合结构的直径。
可选地，所述芯片还包括：与所述第二芯片键合结构同层分布的配重体，所述配重体用于使所述芯片的重心与所述芯片的中心重合。
可选地，所述第一芯片键合结构、所述第二芯片键合结构和所述配重体这三者的纵轴截面共面。
可选地，所述第一芯片键合结构为柱状结构，所述第二芯片键合结构为环状结构，所述第一芯片键合结构位于所述第二芯片键合结构的环形的中心；
所述第一芯片键合结构的高度与所述第二芯片键合结构的高度相等。
可选地，所述第一芯片键合结构为圆柱状结构，所述第二芯片键合结构为圆环状结构。
可选地，所述芯片主体呈柱状结构，所述第一芯片键合结构的轴线与所述芯片主体的轴线共线。
第四方面，提供一种目标基板，包括：
衬底基板以及位于所述衬底基板上的第一对位键合结构和第二对位键合结构；
所述第一基板键合结构被配置为与芯片的第一芯片键合结构键合，所述第二基板键合结构被配置为与所述芯片的第二芯片键合结构键合。
可选地，所述目标基板包括层叠的键合层和对位层，所述键合层包括第一基板键合结构和第二基板键合结构，所述对位层具有第一对位开口和第二对位 开口，所述第一对位键合结构包括所述第一基板键合结构和所述第一对位开口，所述第二对位键合结构包括所述第二基板键合结构和所述第二对位开口，
所述第一对位开口用于使所述第一基板键合结构与所述第一芯片键合结构键合，所述第二对位开口用于使所述第二基板键合结构与所述第二芯片键合结构键合。
可选地，所述第一基板键合结构至少部分通过所述第一对位孔开口裸露，所述第二基板键合结构至少部分通过所述第二对位开口裸露，所述第一芯片键合结构的尺寸小于所述第一对位开口的尺寸，所述第二芯片键合结构的尺寸小于所述第二对位开口的尺寸且大于所述第一对位开口的尺寸，所述第一芯片键合结构与所述第二芯片键合结构之间的距离等于所述第一对位开口与所述第二对位开口之间的距离。
可选地，所述第一对位开口为对位孔，所述第二对位开口为对位缝，所述第一芯片键合结构的尺寸小于所述第一对位开口的孔径，所述第二芯片键合结构的尺寸小于所述第二对位开口的宽度且大于所述第一对位开口的孔径。
可选地，所述第一基板键合结构在所述对位层上的正投影覆盖所述第一对位开口，所述第二基板键合结构在所述对位层上的正投影覆盖所述第二对位开口。
可选地，所述第一基板键合结构为柱状结构，所述第二基板键合结构为环状结构，所述第一对位开口为对位孔，所述第二对位开口为环形对位缝，所述第一基板键合结构位于所述第二基板键合结构的环形的中心，所述第一对位开口位于所述第二对位开口的环形的中心；
所述第一基板键合结构的高度与所述第二基板键合结构的高度相等，所述第一对位开口的孔径小于所述第二对位开口的宽度；
所述第一对位开口的开口面的形状与所述第一基板键合结构的底面的形状相同，所述第一对位开口的孔径小于或等于所述第一基板键合结构的底面的尺寸；
所述第二对位开口的开口面的形状与所述第二基板键合结构的底面的形状相同，所述第二对位开口的宽度小于或等于所述第二基板键合结构的宽度。
可选地，所述第一基板键合结构为圆柱状结构，所述第二基板键合结构为圆环状结构，所述第一对位开口为圆形对位孔，所述第二对位开口为圆环形对位缝；
所述第一对位开口的孔径小于或等于所述第一基板键合结构的直径，所述第二对位开口的宽度小于或等于所述第二基板键合结构的宽度。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种芯片的剖视结构示意图；
图2是图1所示的芯片的正视结构示意图；
图3是本申请实施例提供的另一种芯片的剖视结构示意图；
图4是图3所示的芯片的正视结构示意；
图5是本申请实施例提供的一种目标基板的剖视结构示意图；
图6是图5所示的目标基板的正视结构示意图；
图7是本申请实施例提供的另一种目标基板的剖视结构示意图；
图8是本申请实施例提供的一种芯片转移方法的方法流程图；
图9至图13是本申请实施例提供的一种芯片转移过程的示意图；
图14至图17是本申请实施例提供的另一种芯片转移过程的示意图。
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本申请的实施例，并与说明书一起用于解释本申请的原理。
具体实施方式
为了使本申请的原理、技术方案和优点更加清楚，下面将结合附图对本申请作描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。
Micro LED技术是一种新型的显示技术，可以应用于电视机、iPhone(苹果手机)和iPad(苹果平板电脑)等显示产品。Micro LED芯片是一种纳米级LED芯片，Micro LED芯片通常在蓝宝石类基板(以下称为源基板)上通过分子束外延的方式形成，蓝宝石类基板的尺寸通常就是硅晶元的尺寸，其尺寸较小，而显示产品的尺寸通常较大，因此，在制备显示产品时，需要将Micro LED芯片 从源基板转移至目标基板。其中，该目标基板可以是柔性基板(又称为可挠式基板)或刚性基板(例如玻璃基板)。
Micro LED技术的核心并不是Micro LED芯片的制备，而是Micro LED芯片的转移，Micro LED芯片的巨量转移一直是产业发展的技术瓶颈。目前，转移Micro LED芯片比较常用的技术是微转印(英文：Micro Transfer Printing；简称：μTP)技术，μTP技术最初是由美国Illinois University的John A.Rogers等人利用牺牲层湿蚀刻和聚二甲基硅氧烷(英文：polydimethylsiloxane；简称：PDMS)转贴的技术，将Micro LED芯片转移至目标基板上来制作Micro LED芯片阵列的技术，该技术于2006年Spin-out(转让)给Semprius公司，在2013年X-Celeprint获得Semprius技术授权，并于2014年初开始正式运营。μTP技术使用的转印设备包括打印头和弹性印模(英文：stamp)，转移过程简单来说，就是使用弹性印模结合打印头，有选择的从源基板上拾取Micro LED芯片，并将拾取的Micro LED芯片打印至目标基板。可选地，首先，在源基板(例如“源”晶圆)上制作牺牲层(英文：sacrificial layer)和Micro LED芯片，牺牲层位于源基板与Micro LED芯片之间；然后，通过移除牺牲层对Micro LED芯片进行“释放”(英文：release)，使Micro LED芯片脱离源基板；接着，采用打印头配合弹性印模(弹性印模具有与“源”晶圆相匹配的微结构)从源基板拾取Micro LED芯片；最后，将拾取的Micro LED芯片打印到目标基板上。
在μTP技术中，可以通过调整打印头的移动速度，选择性地调整弹性印模与Micro LED芯片之间的黏附力，从而控制Micro LED芯片的转移工艺。当弹性印模移动较快时，弹性印模与Micro LED芯片之间的黏附力较大，使Micro LED芯片脱离源基板；当弹性印模移动较慢时，弹性印模与Micro LED芯片之间的黏附力较小，使Micro LED芯片脱离弹性印模，被打印至目标基板。其中，可以通过定制化设计弹性印模来实现单次转移多个Micro LED芯片。
但是，弹性印模每次拾取的Micro LED芯片的数量较少，面对显示产品动辄百万级的转印量，μTP技术显得转移效率较低，并且μTP技术的转移效率较低会在一定程度上导致Micro LED芯片转移的成本较高。
本申请实施例提供一种芯片转移方法、显示装置、芯片及目标基板，可以采用绝缘流体结合静电吸附力实现芯片与目标基板的对位，利用微流控技术实现芯片的批量转移，可以用于Micro LED芯片转移。与μTP技术相比，本申请实施例提供的方案有助于提高芯片的转移效率，可以在一定程度上降低转移成 本。下面结合附图阐述本申请的详细方案。
首先，对本申请实施例的芯片进行介绍：
本申请实施例提供了一种芯片，该芯片可以包括芯片主体以及位于芯片主体上的第一芯片键合结构和第二芯片键合结构，该第一芯片键合结构被配置为与目标基板的第一对位键合结构键合，该第二芯片键合结构被配置与目标基板的第二对位键合结构键合。其中，第一芯片键合结构和第二芯片键合结构可以同层分布。例如，芯片可以包括位于芯片主体上的键合层，键合层可以包括第一芯片键合结构和第二芯片键合结构。在本申请实施例中，第一芯片键合结构可以为柱状结构，第二芯片键合结构可以为柱状结构或环状结构。下面根据第二芯片键合结构的不同，分为两种可能的实现方式对本申请实施例提供的芯片进行说明。
第一种可能的实现方式：第一芯片键合结构和第二芯片键合结构均为柱状结构。
请参考图1，其示了本申请实施例提供的一种芯片01的剖视结构示意图，参见图1，该芯片01包括芯片主体011以及位于芯片主体011上的第一芯片键合结构012和第二芯片键合结构013，第一芯片键合结构012和第二芯片键合结构013同层分布，第一芯片键合结构012的尺寸与第二芯片键合结构013的尺寸不同。可选地，第一芯片键合结构012和第二芯片键合结构013均可以为柱状结构，第一芯片键合结构012的底面(例如第一芯片键合结构012远离芯片主体01的一面)的形状与第二芯片键合结构013的底面(例如第二芯片键合结构013远离芯片主体01的一面)的形状可以相同，第一芯片键合结构012的底面的尺寸可以小于第二芯片键合结构013的底面的尺寸，第一芯片键合结构012的高度h012与第二芯片键合结构013的高度h013可以相等。可选地，图2是图1所示的芯片01的正视结构示意图，结合图1和图2，第一芯片键合结构012和第二芯片键合结构013均可以为圆柱状结构，第一芯片键合结构012的底面的尺寸可以是指第一芯片键合结构012的直径D012，第二芯片键合结构013的底面的尺寸可以是指第二芯片键合结构013的直径D013，第一芯片键合结构012的直径D012可以小于第二芯片键合结构013的直径D013。
可选地，如图1所示，该芯片01还可以包括：配重体014，配重体014与第二芯片键合结构013同层分布，由于第一芯片键合结构012和第二芯片键合 结构013可以同层分布，因此配重体014、第一芯片键合结构012和第二芯片键合结构013这三者可以同层分布。其中，该配重体014用于使芯片01的重心与芯片01的中心重合。可选地，配重体014可以呈柱状结构，配重体014的高度h014可以小于第二芯片键合结构013的高度h013，配重体014的底面(例如配重体014远离芯片主体01的一面)的尺寸可以大于第二芯片键合结构013的底面的尺寸。结合图1和图2，配重体014可以呈圆柱状结构，配重体014的底面的尺寸可以等于配重体014的直径D014，配重体014的直径D014可以大于第二芯片键合结构013的直径D013。可选地，在本申请实施例中，第一芯片键合结构012、第二芯片键合结构013和配重体014这三者的纵轴截面可以共面，第一芯片键合结构012、第二芯片键合结构013和配重体014中任一结构的纵轴界面可以垂直于芯片主体011的表面。
容易理解，图1和图2对第一芯片键合结构012、第二芯片键合结构013和配重体014的描述是示例性的，第一芯片键合结构012、第二芯片键合结构013和配重体014还可以是棱柱状结构，该棱柱状结构例如可以为六棱柱状结构、三棱柱状结构或四棱柱状结构等，第一芯片键合结构012、第二芯片键合结构013和配重体014的结构可以相同，也可以不同。配重体014可以是任意结构的配重体，只要保证芯片01的重心与芯片01的中心重合即可。
第二种可能的实现方式：第一芯片键合结构为柱状结构，第二芯片键合结构为环状结构。
请参考图3，其示了本申请实施例提供的另一种芯片01的剖视结构示意图，参见图3，该芯片01包括芯片主体011以及位于芯片主体011上的第一芯片键合结构012和第二芯片键合结构013，第一芯片键合结构012和第二芯片键合结构013同层分布。可选地，第一芯片键合结构012可以为柱状结构，第二芯片键合结构013可以为环状结构，第一芯片键合结构012可以位于第二芯片键合结构013的环形的中心，第一芯片键合结构012的高度h012与第二芯片键合结构013的高度h013可以相等。可选地，图4是图3所示的芯片01的正视结构示意图，结合图3和图4，第一芯片键合结构012可以为圆柱状结构，第二芯片键合结构013可以为圆环状结构。其中，第一芯片键合结构012的直径D012可以大于第二芯片键合结构013的宽度w013，也可以等于第二芯片键合结构013的宽度w013，还可以小于第二芯片键合结构013的宽度w013，本申请实施例对此不作限定。
容易理解，图3和图4对第一芯片键合结构012和第二芯片键合结构013的描述是示例性的，第一芯片键合结构012还可以是棱柱状结构，例如，第一芯片键合结构012可以为六棱柱状结构，三棱柱状结构或四棱柱状结构等，第二芯片键合结构013还可以是其他的环状结构，例如，第二芯片键合结构013可以为六边环状结构、三边环状结构或四边环状结构等。
可选地，在本申请实施例中，芯片主体011可以呈柱状结构，第一芯片键合结构012的轴线与芯片主体011的轴线可以共线。例如，如图2和图4所示，芯片主体011可以呈圆柱状结构。可选地，如图1和图3所示，第一芯片键合结构012的高度方向、第二芯片键合结构013的高度方向和配重体014的高度方向均可以平行于芯片01的高度方向h，第一芯片键合结构012、第二芯片键合结构013和配重体014中，任一结构的高度为该结构在平行于该高度方向h上的尺寸。
可选地，在本申请实施例中，芯片01可以为发光芯片，芯片主体011可以包括衬底基板以及依次位于衬底基板上的发光单元和封装层，发光单元可以包括层叠的两个电极以及位于该两个电极之间的发光层，上述两个芯片键合结构(第一芯片键合结构012和第二芯片键合结构013)可以与发光单元的两个电极一一对应电连接，两个芯片键合结构用于在将芯片01转移至目标基板时，与目标基板的基板键合结构键合。示例地，上述两个电极可以包括阳极和阴极，第一芯片键合结构012可以为阳极键合结构，第一芯片键合结构012可以与芯片01的阳极电连接，第一芯片键合结构012用于与目标基板的阳极键合结构键合，第二芯片键合结构013可以为阴极键合结构，第二芯片键合结构013可以与芯片01的阴极电连接，第二芯片键合结构013用于与目标基板的阴极键合结构键合。在一些实施场景中，阳极键合结构又称为阳极pad，阴极键合结构又称为阴极pad。可选地，芯片01可以为LED芯片，例如芯片01可以是Micro LED芯片，发光单元可以是Micro LED。
在本申请实施例中，第一芯片键合结构012的材料和第二芯片键合结构013的材料均为导电材料，第一芯片键合结构012的材料和第二芯片键合结构013的材料可以相同或不同。可选地，第一芯片键合结构012的材料和第二芯片键合结构013的材料均可以为金属材料，该金属材料例如金属Mo(中文：钼)、金属Cu(中文：铜)、金属Al(中文：铝)及其合金材料，或者，第一芯片键合结构012的材料和第二芯片键合结构013的材料均可以为半导体氧化物，该 半导体氧化物例如氧化铟锡(英文：Indium tin oxide；简称：ITO)、氧化铟锌(英文：Indium zinc oxide；简称：IZO)或掺铝氧化锌(英文：aluminum-doped zinc oxide；简称：ZnO:Al)等。配重体014的材料可以为SiNx(中文：氧化硅)、SiO 2(中文：二氧化硅)、Al 2O 3(中文：氧化铝)或有机树脂等绝缘材料。其中，第一芯片键合结构012和第二芯片键合结构013可以采用光刻法或电镀法制备，配重体014可以采用光刻法制备。
以上为本申请实施例提供的芯片实施例，下面对本申请实施例提供的目标基板进行介绍：
请参考图5，其示出了本申请实施例提供的一种目标基板02的剖视结构示意图，参见图5，该目标基板02包括衬底基板021以及位于衬底基板021上的第一对位键合结构023K和第二对位键合结构024F。该第一对位键合结构023K被配置为与芯片的第一芯片键合结构键合，该第二对位键合结构024F被配置为与芯片的第二芯片键合结构键合。
可选地，如图5所示，目标基板02包括层叠在衬底基板021上的键合层(图5中未标出)和对位层022，键合层包括第一基板键合结构023和第二基板键合结构024，对位层022具有第一对位开口K和第二对位开口F，第一对位键合结构023K包括第一基板键合结构023和第一对位开口K，第二对位键合结构024F包括第二基板键合结构024和第二对位开口F，该第一对位开口K用于使第一基板键合结构023与第一芯片键合结构键合，该第二对位开口F用于使第二基板键合结构024与第二芯片键合结构键合。
可选地，如图5所示，第一基板键合结构023至少部分通过第一对位开口K裸露，第二基板键合结构024至少部分通过第二对位开口F裸露，第一对位开口K的尺寸与第二对位开口F的尺寸可以不同。可选地，第一芯片键合结构的尺寸小于第一对位开口K的尺寸，第二芯片键合结构的尺寸小于第二对位开口F的尺寸且大于第一对位开口K的尺寸，第一芯片键合结构与第二芯片键合结构之间的距离等于第一对位开口K与第二对位开口F之间的距离，这样一来，可以便于第一对位开口K使第一基板键合结构023与第一芯片键合结构键合，该第二对位开口F使第二基板键合结构024与第二芯片键合结构键合。
可选地，第一基板键合结构023在对位层022上的正投影可以覆盖第一对位开口K，第二基板键合结构024在对位层022上的正投影可以覆盖第二对位 开口F，这样可以便于第一基板键合结构023尽可能多的通过第一对位开口K裸露，第二基板键合结构024尽可能多的通过第二对位开口F裸露。
可选地，第一对位开口K可以为对位孔，第二对位开口F可以为对位缝，第一芯片键合结构的尺寸小于可以第一对位开口K的孔径DK，第二芯片键合结构的尺寸可以小于第二对位开口F的宽度wF且大于第一对位开口K的孔径DK，这样可以便于第一芯片键合结构进入第一对位开口K，第二芯片键合结构进入第二对位开口F且不能进入第一对位开口K，从而保证第一对位开口K使第一基板键合结构023与第一芯片键合结构键合，该第二对位开口F使第二基板键合结构024与第二芯片键合结构键合。
可选地，第一基板键合结构023可以为柱状结构，第二基板键合结构024可以为环状结构，第一基板键合结构023可以位于第二基板键合结构024的环形的中心，第一对位开口K可以为对位孔，第二对位开口F可以为环形对位缝，第一对位开口K可以位于第二对位开口F的环形的中心；第一基板键合结构023的高度h023与第二基板键合结构024的高度h024可以相等，第一对位开口K的尺寸可以是第一对位开口K的孔径DK，第二对位开口F的尺寸可以是第二对位开口F的宽度wF，第一对位开口K的孔径DK可以小于第二对位开口F的宽度wF；第一对位开口K的开口面的形状与第一基板键合结构023的底面(例如第一基板键合结构023远离衬底基板021的一面)的形状可以相同，第一对位开口K的孔径DK可以小于或等于第一基板键合结构023的底面的尺寸，使得第一基板键合结构023在对位层022上的正投影可以覆盖第一对位开口K；第二对位开口F的开口面的形状与第二基板键合结构024的底面(例如第二基板键合结构024远离衬底基板021的一面)的形状可以相同，第二对位开口F的宽度wF可以小于或等于第二基板键合结构024的宽度，使得第二基板键合结构024在对位层022上的正投影可以覆盖第二对位开口F。其中，环状结构的底面可以是指环状结构的端面。
可选地，图6是图5所示的目标基板02的正视结构示意图，结合图5和图6，第一基板键合结构023可以为圆柱状结构，第二基板键合结构024可以为圆环状结构，第一对位开口K可以为圆形对位孔，第二对位开口F可以为圆环形对位缝；第一对位开口K的孔径DK可以小于或等于第一基板键合结构023的直径D023，第二对位开口F的宽度wF可以小于或等于第二基板键合结构024的宽度w024。
可选地，在本申请实施例中，衬底基板021可以包括两个电极，两个电极与上述两个基板键合结构(第一基板键合结构023和第二基板键合结构024)一一对应电连接，两个基板键合结构用于在将芯片转移至该目标基板02时与芯片键合结构键合。示例地，上述两个电极可以包括阳极和阴极，第一基板键合结构023可以为阳极键合结构，第一基板键合结构023可以与衬底基板021的阳极电连接，第一基板键合结构023用于与芯片的阳极键合结构键合，第二基板键合结构024可以为阴极键合结构，第二基板键合结构024可以与衬底基板021的阴极电连接，第二基板键合结构024用于与芯片的阴极键合结构键合。在一些实施场景中，阳极键合结构又称为阳极pad，阴极键合结构又称为阴极pad。
在本申请实施例中，衬底基板021可以是显示背板，请参考图7，其示出了本申请实施例提供的另一种目标基板02的剖视结构示意图，参见图7，衬底基板021包括玻璃基板(或者其他刚性基板或柔性基板)0211以及依次位于玻璃基板上的薄膜晶体管(英文：Thin Film Transistor；简称：TFT)0222、平坦层(简称：PLN)0223和电极层(图7中未标出)，电极层可以包括阳极0224和阴极0225，TFT 0222可以包括栅极、栅绝缘层、有源层、层间介质层、源极和漏极，衬底基板021还包括数据线和阴极走线0226，数据线、阴极走线0226、源极和漏极可以同层分布，数据线可以与源极电连接，平坦层0223可以具有阳极过孔和阴极过孔，阳极0224可以通过阳极过孔与漏极电连接，阴极0225可以通过阴极过孔与阴极走线0226电连接。键合层可以位于电极层远离平坦层023的一侧，第一基板键合结构023可以与阳极0224电连接，第二基板键合结构024可以与阴极0225电连接。
在本申请实施例中，第一基板键合结构023的材料和第二基板键合结构024的材料均为导电材料，第一基板键合结构023的材料和第二基板键合结构024的材料可以相同或不同。可选地，第一基板键合结构023的材料和第二基板键合结构024的材料均可以为金属材料，该金属材料例如金属Mo、金属Cu、金属Al及其合金材料，或者，第一基板键合结构023的材料和第二基板键合结构024的材料均可以为半导体氧化物，该半导体氧化物例如ITO、IZO或ZnO:Al等。对位层022的材料可以为有机绝缘材料，例如有机树脂等。其中，第一基板键合结构023和第二基板键合结构024可以采用光刻法或电镀法制备，对位层022可以采用光刻法制备，本申请实施例在此不再赘述。
以上为本申请实施例提供的目标基板的实施例，下面对本申请实施例提供的芯片转移方法进行介绍：本申请实施例提供的芯片转移方法可以用于将芯片从源基板转移至目标基板，芯片可以为图1至图4所示的芯片01，目标基板可以如图5至图7所示的目标基板02。
请参考图8，其示出了本申请实施例提供的一种芯片转移方法的方法流程图，参见图8，该方法包括如下几个步骤：
在步骤801中、将目标基板设置在密闭腔室内，该目标基板包括第一对位键合结构和第二对位键合结构。
可选地，密闭腔室内可以设置有支撑架，可以将目标基板放置在支撑架上，从而将目标基板设置在密闭腔室内。在本申请实施例中，目标基板可以包括第一对位键合结构和第二对位键合结构。例如，如图5至图7所示，目标基板02包括第一对位键合结构023K和第二对位键合结构024F。
在步骤802中、向目标基板的第一对位键合结构施加第一极性的电荷。
可选地，第一对位键合结构可以包括第一基板键合结构和第一对位开口，可以向第一基板键合结构施加第一极性的电荷，从而向第一对位键合结构施加第一极性的电荷。可选地，目标基板上具有与第一基板键合结构电连接的走线，可以通过该走线向第一基板键合结构施加第一极性的电荷。示例地，如图7所示，第一对位键合结构023K包括第一基板键合结构023和第一对位开口K，数据线(图7中未示出)可以通过TFT 0222和阳极0224与第一基板键合结构023电连接，可以通过数据线向第一基板键合结构023施加第一极性的电荷，从而向第一对位键合结构023K施加第一极性的电荷。
可选地，在向第一对位键合结构施加第一极性的电荷的同时，还可以向第二对位键合结构施加第一极性的电荷，或者将该第二对位键合结构接地。其中，第二对位键合结构可以包括第二基板键合结构和第二对位开口，可以向第二基板键合结构施加第一极性的电荷或者将该第二基板键合结构接地，从而向第二对位键合结构施加第一极性的电荷或者将该第二对位键合结构接地。可选地，目标基板上具有与第二基板键合结构电连接的走线，可以通过该走线向第二基板键合结构施加第一极性的电荷或者将该第二基板键合结构接地。示例地，如图7所示，第二对位键合结构024F包括第二基板键合结构024和第二对位开口F，阴极走线0226与第二基板键合结构024电连接，可以通过阴极走线0226向第二基板键合结构024施加第一极性的电荷或者将第二基板键合结构024接地， 从而向第二对位键合结构024F施加第一极性的电荷或者将第二对位键合结构024F接地。
在步骤803中、向芯片的第一芯片键合结构施加第二极性的电荷，芯片包括第二芯片键合结构和第一芯片键合结构，第二极性与第一极性不同。
可选地，可以通过摩擦生电的方式向第一芯片键合结构施加第二极性的电荷，第二极性与第一极性不同。示例地，第一极性为正性、第二极性为负性。在本申请实施例中，芯片可以包括第一芯片键合结构和第二芯片键合结构。例如，如图1至图4所示，芯片01可以包括第一对位键合结构012和第二对位键合结构013。
可选地，在向第一芯片键合结构施加第二极性的电荷的同时，还可以向第二芯片键合结构施加第二极性的电荷，或者也可以不向第二芯片键合结构施加电荷，本申请实施例对此不做限定。
在步骤804中、向密闭腔室内注入绝缘流体，使芯片悬浮于密闭腔室内的绝缘流体中，其中，在第一芯片键合结构和第一对位键合结构的作用下，芯片靠近目标基板移动，使第一芯片键合结构与第一对位键合结构接触，第二芯片键合结构与第二对位键合结构接触。
可选地，密闭腔室可以具有流体入口，可以通过流体入口向密闭腔室内注入绝缘流体，使芯片悬浮于密闭腔室内的绝缘流体中。由于第一对位键合结构与第一芯片键合结构携带不同极性的电荷，因此第一芯片键合结构与第一对位键合结构之间存在吸引力，在该吸引力以及绝缘流体的悬浮力的作用下，第一芯片键合结构靠近第一对位键合结构移动，带动芯片靠近目标基板移动，使第一芯片键合结构与第一对位键合结构接触，第二芯片键合结构与第二对位键合结构接触。至此，可以完成芯片与目标基板的对位。
可选地，第一对位键合结构可以包括第一基板键合结构和第一对位开口，第二对位键合结构可以包括第二基板键合结构和第二对位开口，向第一对位键合结构施加第一极性的电荷可以是向第一基板键合结构施加第一极性的电荷，因此第一基板键合结构与第一芯片键合结构可以携带不同极性的电荷，第一芯片键合结构与第一基板键合结构之间存在吸引力，在该吸引力以及绝缘流体的悬浮力的作用下，芯片靠近目标基板移动，使第一芯片键合结构进入第一对位开口与第一基板键合结构接触，第二芯片键合结构进入第二对位开口与第二基板键合结构接触。
在本申请实施例中，第一芯片键合结构的尺寸可以小于第一对位开口的尺寸，第二芯片键合结构的尺寸可以小于第二对位开口的尺寸且大于第一对位开口的孔径，第一芯片键合结构与第二芯片键合结构之间的距离可以等于第一对位开口与第二对位开口之间的距离，因此第一芯片键合结构能够进入第一对位开口，第二芯片键合结构能够进入第二对位开口而无法进入第一对位开口，在第一芯片键合结构进入第一对位开口的同时，第二芯片键合结构可以进入第二对位开口，最终，第一芯片键合结构可以通过第一对位开口与第一基板键合结构接触，第二芯片键合结构可以通过第二对位开口与第二基板键合结构接触。
示例地，结合图1至图6，第一芯片键合结构012的尺寸可以小于第一对位开口K的尺寸，第二芯片键合结构013的尺寸可以小于第二对位开口F的尺寸且大于第一对位开口K的尺寸，第一芯片键合结构012与第二芯片键合结构013之间的距离d1可以等于第一对位开口K与第二对位开口F之间的距离d2，因此第一芯片键合结构012能够进入第一对位开口K，第二芯片键合结构013能够进入第二对位开口F而无法进入第一对位开口K，在第一芯片键合结构012进入第一对位开口K的同时，第二芯片键合结构013可以进入第二对位开口F。可选地，如图1和图2所示，当第一芯片键合结构012和第二芯片键合结构013均为圆柱状结构时，第一芯片键合结构012与第二芯片键合结构013之间的距离d1可以是第一芯片键合结构012的轴线与第二芯片键合结构013的轴线之间的距离。如图3和图4所示，当第一芯片键合结构012为圆柱状结构，第二芯片键合结构013为圆环状结构时，第一芯片键合结构012与第二芯片键合结构013之间的距离d1可以是第一芯片键合结构012的轴线与第二芯片键合结构013的中位面M之间的距离，该中位面M上任意一点与第二芯片键合结构013的内环之间的距离等于该任意一点与第二芯片键合结构013的外环之间的距离。如图5和图6所示，第一对位开口K与第二对位开口F之间的距离d2可以是第一对位开口K的轴线与第二对位开口F的中位面G之间的距离，该中位面G上任意一点与第二对位开口F的两侧面之间的距离相等。
可选地，密闭腔室还可以具有流体出口，通过流体入口向密闭腔室内注入绝缘流体的同时，可以通过流体出口从密闭腔室抽绝缘流体，通过这样的方式可以控制绝缘流体在密闭腔室的流动方向。
可选地，在本申请实施例中，向密闭腔室内注入绝缘流体，使芯片悬浮于密闭腔室内的绝缘流体中可以包括：首先将芯片设置在密闭腔室内，然后向密 闭腔室内注入绝缘流体，在绝缘流体的作用下，芯片悬浮于密闭腔室内的绝缘流体中；或者，首先将芯片与绝缘流体混合，然后向密闭腔室内注入混合有芯片的绝缘流体，使芯片悬浮于密闭腔室内的绝缘流体中。容易理解，还可以以其他方式使芯片悬浮于密闭腔室内的绝缘流体中，本申请实施例对此不做限定。
可选地，在本申请实施例中，芯片可以生长在源基板上，在将芯片设置于密闭腔室内之前，可以将芯片与源基板分离。示例地，源基板上可以具有牺牲层，芯片可以生长在牺牲层上，可以通过刻蚀牺牲层，使芯片与源基板分离。
在步骤805中、向芯片施加键合力，使第一芯片键合结构与第一对位键合结构键合，第二芯片键合结构与第二对位键合结构键合。
在第一芯片键合结构与第一对位键合结构接触，且第二芯片键合结构与第二对位键合结构接触之后(也即是芯片与目标基板对位之后)，可以向芯片施加键合力，使第一芯片键合结构与第一对位键合结构键合，第二芯片键合结构与第二对位键合结构键合，至此，完成芯片转移。如前所述容易理解，第一芯片键合结构与第一对位键合结构接触可以是第一芯片键合结构通过第一对位开口与第一基板键合结构接触，第二芯片键合结构与第二对位键合结构接触可以是第二芯片键合结构通过第二对位开口与第二基板键合结构接触，因此向芯片施加键合力可以使第一芯片键合结构与第一基板键合结构键合，第二芯片键合结构与第二基板键合结构键合。
可选地，密闭腔室内可以设置有与目标基板相对的压合基板，可以通过压合基板向芯片施加压力，使第一芯片键合结构与第一基板键合结构键合，第二芯片键合结构与第二基板键合结构键合。
综上所述，本申请提供的芯片转移方法，将目标基板设置在密闭腔室内；向目标基板的第一对位键合结构施加第一极性的电荷；向芯片的第一芯片键合结构施加第二极性的电荷，第二极性与第一极性不同；向密闭腔室内注入绝缘流体，使芯片悬浮于密闭腔室内的绝缘流体中，在第一芯片键合结构与第一对位键合结构的作用下，芯片靠近目标基板移动，第一芯片键合结构与第一对位键合结构接触，第二芯片键合结构与第二对位键合结构接触；向芯片施加键合力，使第一芯片键合结构与第一对位键合结构键合，第二芯片键合结构与第二对位键合结构键合。由于可以采用绝缘流体结合静电吸附力实现芯片与目标基板的对位，因此有助于实现芯片的批量转移，有助于提高芯片的转移效率。
本申请实施例提供的方案，在绝缘流体中，基于目标基板与芯片之间的静 电吸附力和绝缘流体的悬浮力，实现芯片与目标基板的对位，有助于实现目标基板与芯片的高效率、低成本，高精度的对位，可以用于芯片的巨量转移，降低芯片转移成本。
下面结合图1至图6，分为两个实施示例，以将图1所示的01转移至图5所示的目标基板02，以及，将图3所示的芯片01转移至图5所示的目标基板02为例，对本申请实施例提供的芯片转移过程进行说明。
图9至图13是本申请实施例提供的一种芯片转移方法的示意图，图9至图13以将图1所示的芯片01转移至图5所示的目标基板02为例进行说明。
参见图9，将目标基板02设置在密闭腔室(图9至图13中均未示出)内，向第一基板键合结构023施加正性电荷，将第二基板键合结构024接地；向第一芯片键合结构012和第二芯片键合结构013施加负性电荷，将芯片01设置在密闭腔室内；之后向密闭腔室内注入按照方向X流动的绝缘流体，芯片01悬浮于绝缘流体中。由于第一基板键合结构023与第一芯片键合结构012携带异性电荷，因此第一基板键合结构023与第一芯片键合结构012之间存在吸引力，在第一基板键合结构023与第一芯片键合结构012之间的吸引力以及绝缘流体对芯片01的悬浮力的作用下，芯片01靠近目标基板02移动。
参见图10和图11，并结合图1、图2、图5和图6，以第一对位开口K为对位孔，第二对位开口F为对位缝为例，由于第一芯片键合结构012的尺寸小于第一对位开口K的孔径DK，第二芯片键合结构013的尺寸大于第一对位开口K的孔径DK，因此第一芯片键合结构012能够进入第一对位开口K(如图10所示)，第二芯片键合结构013无法进入第一对位开口K(如图11所示)；又由于第二芯片键合结构013的尺寸小于第二对位开口F的宽度wF，第一芯片键合结构012与第二芯片键合结构013之间的距离d1等于第一对位开口K与第二对位开口F之间的距离d2，因此如图10所示，在第一芯片键合结构012进入第一对位开口K的同时，第二芯片键合结构013进入第二对位开口F，第一芯片键合结构012通过第一对位开口K与第一基板键合结构023接触，第二芯片键合结构013通过第二对位开口F与第二基板键合结构024接触。至此，完成芯片01与目标基板02的对位。
最后，向芯片01施加键合力，使第一芯片键合结构012与第一基板键合结构023键合，第二芯片键合结构013与第二基板键合结构024键合(如图12所 示)。至此完成芯片转移。将图1所示的芯片01转移至图5所示的目标基板02后的剖视图可以如图12所示，正视图可以如图13所示，容易理解，为了清楚示出第一芯片键合结构012与第一基板键合结构023的关系，以及第二芯片键合结构013与第二基板键合结构024的关系，该图13中未示出配重件014以及芯片主体011。
在本申请实施例中，由于第二芯片键合结构013的尺寸大于第一对位开口K的孔径DK，在芯片01与目标基板02对位的过程中，第二芯片键合结构013无法进入第一对位开口K，会出现如图11的情况，对于如图11所示的情况，芯片01会继续随绝缘流体流动，直至第一芯片键合结构012进入第一对位开口K。
图14至图17是本申请实施例提供的另一种芯片转移方法的示意图，该图14至图17以将图3所示的芯片01转移至图5所示的目标基板为例进行说明。
参见图14，将目标基板02设置在密闭腔室(图14至图17中均未示出)内，向第一基板键合结构023和第二基板键合结构024施加正性电荷；向第一芯片键合结构012和第二芯片键合结构013施加负性电荷，将芯片01设置在密闭腔室内，之后向密闭腔室内注入按照方向X流动的绝缘流体，芯片01悬浮于绝缘流体中。由于第一基板键合结构023与第一芯片键合结构012携带异性电荷，因此第一基板键合结构023与第一芯片键合结构012之间存在吸引力，在第一基板键合结构023与第一芯片键合结构012之间的吸引力以及绝缘流体对芯片01的悬浮力的作用下，芯片01靠近目标基板02移动。
参见图15，并结合图4至图6，以第一对位开口K为对位孔，第二对位开口F为对位缝为例，由于第一芯片键合结构012的尺寸小于第一对位开口K的孔径DK，第二芯片键合结构013为以第一芯片键合结构012为中心的环状结构，因此第一芯片键合结构012能够进入第一对位开口K(如图16所示)，第二芯片键合结构013无法进入第一对位开口K；又由于第二芯片键合结构013的尺寸小于第二对位开口F的宽度wF，第一芯片键合结构012与第二芯片键合结构013之间的距离d1等于第一对位开口K与第二对位开口F之间的距离d2，因此如图16所示，在第一芯片键合结构012进入第一对位开口K的同时，第二芯片键合结构013进入第二对位开口F，第一芯片键合结构012通过第一对位开口K与第一基板键合结构023接触，第二芯片键合结构013通过第二对位开口F与第二基板键合结构024接触。至此，完成芯片01与目标基板02的对位。
最后，向芯片01施加键合力，使第一芯片键合结构012与第一基板键合结构023键合，第二芯片键合结构013与第二基板键合结构024键合。至此完成芯片转移。将图3所示的芯片01转移至图5所示的目标基板02后的剖视图可以如图16所示，正视图可以如图17所示，容易理解，为了清楚示出第一芯片键合结构012与第一基板键合结构023的关系，以及第二芯片键合结构013与第二基板键合结构024的关系，该图17中未示出芯片主体011。
基于同样的发明构思，本申请实施例还提供了一种显示装置，该显示装置包括上述实施例提供的目标基板和芯片，芯片采用上述实施例提供的芯片转移方法从源基板转移至目标基板。其中，该显示装置可以如图12和图13所示，或者该显示装置可以如图16和图17所示。
其中，该显示装置可以是电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪或可穿戴设备等任何具有显示功能的产品或部件。
可选地，参见图12、图13、图16和图17，该显示装置包括芯片01和目标基板02，结合图1至图4，该芯片01包括第一芯片键合结构012和第二芯片键合结构013，结合图5至图7，该目标基板02包括第一对位键合结构023K和第二对位键合结构024F，该第一芯片键合结构012与第一对位键合结构023K键合，该第二芯片键合结构013与第二对位键合结构024F键合。
可选地，参见图12、图13、图16和图17并结合图5至图7，该目标基板02包括层叠的键合层和对位层022，键合层包括第一基板键合结构023和第二基板键合结构024，对位层022具有第一对位开口K和第二对位开口F，第一对位键合结构023K包括第一基板键合结构023和第一对位开口K，第二对位键合结构024F包括第二基板键合结构024和第二对位开口F，第一芯片键合结构012通过第一对位开口K与第一基板键合结构023键合，第二芯片键合结构013通过第二对位开口F与第二基板键合结构024键合。
可选地，参见图12、图13、图16和图17并结合图1至图7，第一芯片键合结构012的尺寸小于第一对位开口K的尺寸，第二芯片键合结构013的尺寸小于第二对位开口F的尺寸且大于第一对位开口K的尺寸，第一芯片键合结构012与第二芯片键合结构013之间的距离d1等于第一对位开口K与第二对位开口F之间的距离d2。
可选地，参见图12、图13、图16和图17并结合图1至图7，第一对位开口K为对位孔，第二对位开口F为对位缝，第一芯片键合结构012的尺寸小于第一对位开口K的孔径DK，第二芯片键合结构013的尺寸小于第二对位开口F的宽度wF且大于第一对位开口的孔径DK，这样可以便于第一芯片键合结构012进入第一对位开口K，第二芯片键合结构013进入第二对位开口F且不能进入第一对位开口K，从而保证第一芯片键合结构012通过第一对位开口K与第一基板键合结构023键合，第二芯片键合结构013通过第二对位开口F与第二基板键合结构024键合。
可选地，参见图12、图13、图16和图17并结合图5至图7，第一基板键合结构023在对位层022上的正投影覆盖第一对位开口K，第二基板键合结构024在对位层022上的正投影覆盖第二对位开口F，这样可以便于第一基板键合结构023尽可能多的通过第一对位开口K露出并与第一芯片键合结构012接触，第二基板键合结构024尽可能多的通过第二对位开口F露出并与第二芯片键合结构013接触，保证芯片01和目标基板02的有效键合。
可选地，参见图12和图13并结合图1、图2、图5至图7，第一芯片键合结构012、第二芯片键合结构013和第一基板键合结构023均可以为柱状结构，第二基板键合结构024可以为环状结构，第一对位开口K可以为对位孔，第二对位开口F可以为环形对位缝，第一基板键合结构023可以位于第二基板键合结构024的环形的中心，第一对位开口K可以位于第二对位开口F的环形的中心。第一芯片键合结构012的底面的尺寸可以小于第一对位开口K的孔径DK，第二芯片键合结构013的底面的尺寸可以大于第一对位开口K的孔径DK且小于第二对位开口F的宽度wF，这样一来，可以便于第一芯片键合结构012进入第一对位开口K，第二芯片键合结构013进入第二对位开口F。第一芯片键合结构012的高度h012与第二芯片键合结构013的高度h013可以相等，第一基板键合结构023的高度h023与第二基板键合结构024的高度h024可以相等，这样一来，在第一芯片键合结构012与第一基板键合结构023接触时，第二芯片键合结构013与第二基板键合结构024接触。
可选地，如图5和图6所示，第一对位开口K的开口面的形状与第一基板键合结构023的底面的形状可以相同，第一对位开口K的孔径DK可以小于或等于第一基板键合结构023的底面的尺寸，第二对位开口F的开口面的形状与第二基板键合结构024的环形的形状可以相同，第二对位开口F的宽度wF可以 小于或等于第二基板键合结构024的宽度，这样一来，可以保证第一芯片键合结构012能够与第一基板键合结构023充分接触，以及第二基板键合结构024能够与第二基板键合结构024充分接触。
可选地，结合图1、图2、图5和图6，第一芯片键合结构012、第二芯片键合结构013和第一基板键合结构023均可以为圆柱状结构，第二基板键合结构024可以为圆环状结构，第一对位开口K可以为圆形对位孔，第二对位开口F可以为圆环形对位缝；第一芯片键合结构012的直径D012可以小于第一对位开口K的孔径DK，第二芯片键合结构013的直径D013可以大于第一对位开口K的孔径DK且小于第二对位开口F的宽度wF；第一对位开口K的孔径DK可以小于或等于第一基板键合结构023的直径D023，第二对位开口F的宽度wF可以小于或等于第二基板键合结构024的宽度w024。
可选地，参见图12和图13并结合图1和图2，芯片01还包括：与第二芯片键合结构013同层分布的配重体014，该配重体用于使芯片01的重心与芯片01的中心重合。可选地，第一芯片键合结构012、第二芯片键合结构013和配重体014这三者的纵轴截面共面。
可选地，参见图16和图17结合图3至图7，第一芯片键合结构012和第一基板键合结构023均为柱状结构，第二芯片键合结构013和第二基板键合结构024均为环状结构，第一对位开口K为对位孔，第二对位开口F为环形对位缝，第一芯片键合结构012位于第二芯片键合结构013的环形的中心，第一基板键合结构023位于第二基板键合结构024的环形的中心，第一对位开口K位于第二对位开口F的环形的中心；第一芯片键合结构012的底面的尺寸小于第一对位开口K的孔径DK，第二芯片键合结构013的宽度w013小于第二对位开口F的宽度wF，这样一来，可以便于第一芯片键合结构012进入第一对位开口K，第二芯片键合结构013进入第二对位开口F。第一芯片键合结构012的高度h012与第二芯片键合结构013的高度h013相等，第一基板键合结构023的高度h023与第二基板键合结构024的高度h024相等，这样一来，可以便于第一芯片键合结构012与第一基板键合结构023接触的同时，第二芯片键合结构013与第二基板键合结构024接触。
可选地，参见图16和图17结合图3至图7，第一对位开口K的开口面的形状与第一基板键合结构023的底面的形状相同，第一对位开口K的孔径DK小于或等于第一基板键合结构023的底面的尺寸；第二对位开口F的开口面的 形状与第二基板键合结构024的环形的形状相同，第二对位开口F的宽度wF小于或等于第二基板键合结构024的宽度w024，这样一来，可以保证第一芯片键合结构012能够与第一基板键合结构023充分接触，且第二芯片键合结构013能够与第二基板键合结构024充分接触。
可选地，参见图16和图17结合图3至图7，第一芯片键合结构012和第一基板键合结构023均为圆柱状结构，第二芯片键合结构013和第二基板键合结构024均为圆环状结构，第一对位开口K为圆形对位孔，第二对位开口F为圆环形对位缝；第一芯片键合结构012的直径D012小于第一对位开口K的孔径DK，第二芯片键合结构013的宽度w013小于第二对位开口F的宽度wF；第一对位开口K的孔径DK小于或等于第一基板键合结构023的直径D023，第二对位开口F的宽度wF小于或等于第二基板键合结构024的宽度。
本申请中字符“/”，一般表示前后关联对象是一种“或”的关系。
在本申请中，“电连接”指的是连接且能够传输电荷，但不必然有电荷传输，例如，A与B电连接表示A与B连接且A与B之间能够传输电荷，但是A与B之间并不必然有电荷传输。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (31)

  1. 一种芯片转移方法，包括：
    将目标基板设置在密闭腔室内，所述目标基板包括第一对位键合结构和第二对位键合结构；
    向所述目标基板的所述第一对位键合结构施加第一极性的电荷；
    向芯片的第一芯片键合结构施加第二极性的电荷，所述芯片包括第二芯片键合结构和所述第一芯片键合结构，所述第二极性与所述第一极性不同；
    向所述密闭腔室内注入绝缘流体，使所述芯片悬浮于所述密闭腔室内的所述绝缘流体中，其中，在所述第一芯片键合结构和所述第一对位键合结构的作用下，所述芯片靠近所述目标基板移动，使所述第一芯片键合结构与所述第一对位键合结构接触，所述第二芯片键合结构与所述第二对位键合结构接触；
    向所述芯片施加键合力，使所述第一芯片键合结构与所述第一对位键合结构键合，所述第二芯片键合结构与所述第二对位键合结构键合。
  2. 根据权利要求1所述的方法，其中，所述方法还包括：
    向所述目标基板的所述第二对位键合结构施加所述第一极性的电荷，以及，向所述芯片的所述第二芯片键合结构施加所述第二极性的电荷；或者，
    将所述目标基板的所述第二对位键合结构接地，以及，向所述芯片的所述第二芯片键合结构施加所述第二极性的电荷。
  3. 根据权利要求1或2所述的方法，其中，
    向所述密闭腔室内注入绝缘流体，使所述芯片悬浮于所述密闭腔室内的所述绝缘流体中，包括：
    将所述芯片设置在所述密闭腔室内，并向所述密闭腔室内注入绝缘流体，使所述芯片悬浮于所述密闭腔室内的所述绝缘流体中；或者，
    将所述芯片与绝缘流体混合，并向所述密闭腔室内注入混合有所述芯片的所述绝缘流体，使所述芯片悬浮于所述密闭腔室内的所述绝缘流体中。
  4. 根据权利要求1至3任一所述的方法，其中，
    在向所述密闭腔室内注入绝缘流体，使所述芯片悬浮于所述密闭腔室内的 所述绝缘流体中之前，所述方法还包括：
    将所述芯片与所述源基板分离。
  5. 根据权利要求1至4任一所述的方法，其中，
    所述目标基板包括层叠的键合层和对位层，所述键合层包括第一基板键合结构和第二基板键合结构，所述对位层具有第一对位开口和第二对位开口，所述第一对位键合结构包括所述第一基板键合结构和所述第一对位开口，所述第二对位键合结构包括所述第二基板键合结构和所述第二对位开口，
    向所述目标基板的所述第一对位键合结构施加第一极性的电荷，包括：
    向所述目标基板的所述第一基板键合结构施加所述第一极性的电荷，其中，在所述第一芯片键合结构和所述第一基板键合结构的作用下，所述芯片靠近所述目标基板移动，所述第一芯片键合结构进入所述第一对位开口与所述第一基板键合结构接触，所述第二芯片键合结构进入所述第二对位开口与所述第二基板键合结构接触。
  6. 一种显示装置，包括：芯片和目标基板，
    所述芯片包括第一芯片键合结构和第二芯片键合结构，所述目标基板包括第一对位键合结构和第二对位键合结构，所述第一芯片键合结构与所述第一对位键合结构键合，所述第二芯片键合结构与所述第二对位键合结构键合。
  7. 根据权利要求6所述的显示装置，其中，
    所述目标基板包括层叠的键合层和对位层，所述键合层包括第一基板键合结构和第二基板键合结构，所述对位层具有第一对位开口和第二对位开口，所述第一对位键合结构包括所述第一基板键合结构和所述第一对位开口，所述第二对位键合结构包括所述第二基板键合结构和所述第二对位开口，
    所述第一芯片键合结构通过所述第一对位开口与所述第一基板键合结构键合，所述第二芯片键合结构通过所述第二对位开口与所述第二基板键合结构键合。
  8. 根据权利要求7所述的显示装置，其中，
    所述第一芯片键合结构的尺寸小于所述第一对位开口的尺寸，所述第二芯片键合结构的尺寸小于所述第二对位开口的尺寸且大于所述第一对位开口的尺寸，所述第一芯片键合结构与所述第二芯片键合结构之间的距离等于所述第一对位开口与所述第二对位开口之间的距离。
  9. 根据权利要求8所述的显示装置，其中，
    所述第一对位开口为对位孔，所述第二对位开口为对位缝，所述第一芯片键合结构的尺寸小于所述第一对位开口的孔径，所述第二芯片键合结构的尺寸小于所述第二对位开口的宽度且大于所述第一对位开口的孔径。
  10. 根据权利要求7至9任一所述的显示装置，其中，
    所述第一基板键合结构在所述对位层上的正投影覆盖所述第一对位开口，所述第二基板键合结构在所述对位层上的正投影覆盖所述第二对位开口。
  11. 根据权利要求7至10任一所述的显示装置，其中，
    所述第一芯片键合结构、所述第二芯片键合结构和所述第一基板键合结构均为柱状结构，所述第二基板键合结构为环状结构，所述第一对位开口为对位孔，所述第二对位开口为环形对位缝，所述第一基板键合结构位于所述第二基板键合结构的环形的中心，所述第一对位开口位于所述第二对位开口的环形的中心；
    所述第一芯片键合结构的底面的尺寸小于所述第一对位开口的孔径，所述第二芯片键合结构的底面的尺寸大于所述第一对位开口的孔径且小于所述第二对位开口的宽度；
    所述第一芯片键合结构的高度与所述第二芯片键合结构的高度相等，所述第一基板键合结构的高度与所述第二基板键合结构的高度相等；
    所述第一对位开口的开口面的形状与所述第一基板键合结构的底面的形状相同，所述第一对位开口的孔径小于或等于所述第一基板键合结构的底面的尺寸；
    所述第二对位开口的开口面的形状与所述第二基板键合结构的环形的形状相同，所述第二对位开口的宽度小于或等于所述第二基板键合结构的宽度。
  12. 根据权利要求11所述的显示装置，其中，
    所述第一芯片键合结构、所述第二芯片键合结构和所述第一基板键合结构均为圆柱状结构，所述第二基板键合结构为圆环状结构，所述第一对位开口为圆形对位孔，所述第二对位开口为圆环形对位缝；
    所述第一芯片键合结构的直径小于所述第一对位开口的孔径，所述第二芯片键合结构的直径大于所述第一对位开口的孔径且小于所述第二对位开口的宽度；
    所述第一对位开口的孔径小于或等于所述第一基板键合结构的直径，所述第二对位开口的宽度小于或等于所述第二基板键合结构的宽度。
  13. 根据权利要求11或12所述的显示装置，其中，
    所述芯片还包括：与所述第二芯片键合结构同层分布的配重体，所述配重体用于使所述芯片的重心与所述芯片的中心重合。
  14. 根据权利要求13所述的显示装置，其中，
    所述第一芯片键合结构、所述第二芯片键合结构和所述配重体这三者的纵轴截面共面。
  15. 根据权利要求7至9任一所述的显示装置，其中，
    所述第一芯片键合结构和所述第一基板键合结构均为柱状结构，所述第二芯片键合结构和所述第二基板键合结构均为环状结构，所述第一对位开口为对位孔，所述第二对位开口为环形对位缝，所述第一芯片键合结构位于所述第二芯片键合结构的环形的中心，所述第一基板键合结构位于所述第二基板键合结构的环形的中心，所述第一对位开口位于所述第二对位开口的环形的中心；
    所述第一芯片键合结构的底面的尺寸小于所述第一对位开口的孔径，所述第二芯片键合结构的宽度小于所述第二对位开口的宽度；
    所述第一芯片键合结构的高度与所述第二芯片键合结构的高度相等，所述第一基板键合结构的高度与所述第二基板键合结构的高度相等；
    所述第一对位开口的开口面的形状与所述第一基板键合结构的底面的形状 相同，所述第一对位开口的孔径小于或等于所述第一基板键合结构的底面的尺寸；
    所述第二对位开口的开口面的形状与所述第二基板键合结构的环形的形状相同，所述第二对位开口的宽度小于或等于所述第二基板键合结构的宽度。
  16. 根据权利要求15所述的显示装置，其中，
    所述第一芯片键合结构和所述第一基板键合结构均为圆柱状结构，所述第二芯片键合结构和所述第二基板键合结构均为圆环状结构，所述第一对位开口为圆形对位孔，所述第二对位开口为圆环形对位缝；
    所述第一芯片键合结构的直径小于所述第一对位开口的孔径，所述第二芯片键合结构的宽度小于所述第二对位开口的宽度；
    所述第一对位开口的孔径小于或等于所述第一基板键合结构的直径，所述第二对位开口的宽度小于或等于所述第二基板键合结构的宽度。
  17. 一种芯片，包括：
    芯片主体以及位于所述芯片主体上的第一芯片键合结构和第二芯片键合结构；
    所述第一芯片键合结构被配置为与目标基板的第一对位键合结构键合，所述第二芯片键合结构被配置与所述目标基板的第二对位键合结构键合。
  18. 根据权利要求17所述的芯片，其中，
    所述第一芯片键合结构和所述第二芯片键合结构均为柱状结构，所述第一芯片键合结构的底面的形状与所述第二芯片键合结构的底面的形状相同，所述第一芯片键合结构的底面的尺寸小于所述第二芯片键合结构的底面的尺寸，所述第一芯片键合结构的高度与所述第二芯片键合结构的高度相等。
  19. 根据权利要求18所述的芯片，其中，
    所述第一芯片键合结构和所述第二芯片键合结构均为圆柱状结构，所述第一芯片键合结构的直径小于所述第二芯片键合结构的直径。
  20. 根据权利要求18或19所述的芯片，其中，
    所述芯片还包括：与所述第二芯片键合结构同层分布的配重体，所述配重体用于使所述芯片的重心与所述芯片的中心重合。
  21. 根据权利要求20所述的芯片，其中，
    所述第一芯片键合结构、所述第二芯片键合结构和所述配重体这三者的纵轴截面共面。
  22. 根据权利要求17所述的芯片，其中，
    所述第一芯片键合结构为柱状结构，所述第二芯片键合结构为环状结构，所述第一芯片键合结构位于所述第二芯片键合结构的环形的中心；
    所述第一芯片键合结构的高度与所述第二芯片键合结构的高度相等。
  23. 根据权利要求22所述的芯片，其中，
    所述第一芯片键合结构为圆柱状结构，所述第二芯片键合结构为圆环状结构。
  24. 根据权利要求17至23任一所述的芯片，其中，
    所述芯片主体呈柱状结构，所述第一芯片键合结构的轴线与所述芯片主体的轴线共线。
  25. 一种目标基板，包括：
    衬底基板以及位于所述衬底基板上的第一对位键合结构和第二对位键合结构；
    所述第一对位键合结构被配置为与芯片的第一芯片键合结构键合，所述第二对位键合结构被配置为与所述芯片的第二芯片键合结构键合。
  26. 根据权利要求25所述的目标基板，其中，
    所述目标基板包括层叠的键合层和对位层，所述键合层包括第一基板键合结构和第二基板键合结构，所述对位层具有第一对位开口和第二对位开口，所 述第一对位键合结构包括所述第一基板键合结构和所述第一对位开口，所述第二对位键合结构包括所述第二基板键合结构和所述第二对位开口，
    所述第一对位开口用于使所述第一基板键合结构与所述第一芯片键合结构键合，所述第二对位开口用于使所述第二基板键合结构与所述第二芯片键合结构键合。
  27. 根据权利要求26所述的目标基板，其中，
    所述第一基板键合结构至少部分通过所述第一对位孔开口裸露，所述第二基板键合结构至少部分通过所述第二对位开口裸露，所述第一芯片键合结构的尺寸小于所述第一对位开口的尺寸，所述第二芯片键合结构的尺寸小于所述第二对位开口的尺寸且大于所述第一对位开口的尺寸，所述第一芯片键合结构与所述第二芯片键合结构之间的距离等于所述第一对位开口与所述第二对位开口之间的距离。
  28. 根据权利要求27所述的目标基板，其中，
    所述第一对位开口为对位孔，所述第二对位开口为对位缝，所述第一芯片键合结构的尺寸小于所述第一对位开口的孔径，所述第二芯片键合结构的尺寸小于所述第二对位开口的宽度且大于所述第一对位开口的孔径。
  29. 根据权利要求26至28任一所述的目标基板，其中，
    所述第一基板键合结构在所述对位层上的正投影覆盖所述第一对位开口，所述第二基板键合结构在所述对位层上的正投影覆盖所述第二对位开口。
  30. 根据权利要求26至29任一所述的目标基板，其中，
    所述第一基板键合结构为柱状结构，所述第二基板键合结构为环状结构，所述第一对位开口为对位孔，所述第二对位开口为环形对位缝，所述第一基板键合结构位于所述第二基板键合结构的环形的中心，所述第一对位开口位于所述第二对位开口的环形的中心；
    所述第一基板键合结构的高度与所述第二基板键合结构的高度相等，所述第一对位开口的孔径小于所述第二对位开口的宽度；
    所述第一对位开口的开口面的形状与所述第一基板键合结构的底面的形状相同，所述第一对位开口的孔径小于或等于所述第一基板键合结构的底面的尺寸；
    所述第二对位开口的开口面的形状与所述第二基板键合结构的底面的形状相同，所述第二对位开口的宽度小于或等于所述第二基板键合结构的宽度。
  31. 根据权利要求30所述的目标基板，其中，
    所述第一基板键合结构为圆柱状结构，所述第二基板键合结构为圆环状结构，所述第一对位开口为圆形对位孔，所述第二对位开口为圆环形对位缝；
    所述第一对位开口的孔径小于或等于所述第一基板键合结构的直径，所述第二对位开口的宽度小于或等于所述第二基板键合结构的宽度。
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