WO2020201005A1 - Semiconductor module and method for manufacturing it - Google Patents

Semiconductor module and method for manufacturing it Download PDF

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Publication number
WO2020201005A1
WO2020201005A1 PCT/EP2020/058532 EP2020058532W WO2020201005A1 WO 2020201005 A1 WO2020201005 A1 WO 2020201005A1 EP 2020058532 W EP2020058532 W EP 2020058532W WO 2020201005 A1 WO2020201005 A1 WO 2020201005A1
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WO
WIPO (PCT)
Prior art keywords
metal body
shaped metal
semiconductor module
structuring
semiconductor
Prior art date
Application number
PCT/EP2020/058532
Other languages
French (fr)
Inventor
David Benning
André Bastos Abibe
Martin Becker
Original Assignee
Danfoss Silicon Power Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Danfoss Silicon Power Gmbh filed Critical Danfoss Silicon Power Gmbh
Publication of WO2020201005A1 publication Critical patent/WO2020201005A1/en

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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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    • H01L23/3677Wire-like or pin-like cooling fins or heat sinks
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    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
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Definitions

  • the present invention relates to a semiconductor module comprising a shaped metal body fixed to an upper surface of a semiconductor having a lower sur face that is sintered onto a top layer of a substrate.
  • the invention also relates to a method for manufacturing a semiconductor module.
  • Modern power electronics applies solid-state electronics to control and convert electric power with semiconductor switching devices such as diodes, thyristors and transistors. In contrast to electronic systems that are configured to trans mit and process signals and data, in power electronics substantial amounts of electrical energy are processed.
  • More and more applications are adopting power electronics technologies to improve energy efficiency, reliability, and control .
  • Semiconductor components are essential for power semiconductors and, since such components are sen sitive to high temperatures, to avoid device failure due to thermal runaway, effective cooling is required.
  • air-cooling provides a simple, low cost, effective, and reliable cool ing solution.
  • the prior air cooling technology may not be sufficient.
  • the semiconductor module according to the invention is a semiconductor module comprising a shaped metal body fixed to an upper surface of a semi conductor having a lower surface that is sintered onto a top layer of a sub strate, wherein the shaped metal body comprises a top surface provided with surface structuring that increases the surface area of the top surface.
  • the shaped metal body is at tached to the upper surface of the semiconductor by means of a sintering layer.
  • the sintering technology of the invention may use a silver-based paste to connect the respective elements.
  • Silver is thermally very stable, suffering from virtually no creep effects in power module service temperatures. This provides a considerable advantage over the standard solder technology using low-melting temperature metals for connecting chips to substrates or other elements.
  • the temperatures in power modules are in the range of creep effects for solder alloys, meaning that they can crack and/or deform easily in service.
  • a soldering process requires a subsequent process step to clean the surface from unwanted chemicals. This is not required in a sintering process.
  • the surface structuring may be of any suitable type as long as it increases the surface area of the top surface.
  • the increased surface area of the top surface increases the cooling capacity of the top surface. Accordingly, it is an ad vantage to have a surface structuring that increases the surface area of the top surface to a large extent.
  • the surface structuring increases the surface area of that portion of the top surface at which the surface structuring is provided, with at least 10 %.
  • the surface structuring increases the surface area of that portion of the top surface at which the surface structuring is provided, with at least 25 %.
  • the surface structuring increases the surface area of that portion of the top surface at which the surface structuring is provided, with at least 40 %.
  • the surface structuring increases the surface area of that portion of the top surface at which the surface structuring is provided, with at least 50 %.
  • the surface structuring increases the surface area of that portion of the top surface at which the surface structuring is provided, with more than 50 %.
  • the semiconductor module may be a power module for automotive, solar, wind or industrial applications.
  • the shaped metal body may be a plate-shaped metal body.
  • the shaped metal body is made of copper.
  • the shaped metal body is a copper foil.
  • the semiconductor module is a power module.
  • the shaped metal body is fixed to an upper surface of the semiconductor, the semiconductor having a lower surface being sintered onto a top layer of the substrate.
  • the semiconductor module comprises an encapsulation that is brought into thermal contact with the surface structuring, wherein the encapsulation covers at least a portion the surface structuring and is electri cally insulating and thermally conductive.
  • thermally conductive encapsulation By applying a thermally conductive encapsulation, it is possible to increase the heat transfer coefficient of the media (encapsulation) covering the surface structuring and thus enhance the cooling capacity of the surface structuring. Accordingly, it advantageous to apply an encapsulation having a thermal con ductance that is higher than a predefined level such as more than 0.1 W/mK.
  • the electrically insulating and thermally conductive en capsulation has a thermal conductance in the range 0.1-15 W/mK.
  • the electrically insulating and thermally conductive en capsulation has a thermal conductance in the range 0.15-10 W/mK. In one embodiment, the electrically insulating and thermally conductive en capsulation is made of epoxy, preferably epoxy having a thermal conductance in the range 1 to 10 W/mK.
  • the electrically insulating and thermally conductive en capsulation is made of, preferably silicone having a thermal conductance in the range 0.17 W/mK up to 3 W/mK.
  • the electrically insulating and thermally conductive en capsulation is made of cement, preferably cement having a thermal conduct ance in the range with 2-10 W/mK.
  • the electrically insulating and thermally conductive en capsulation is a cement-ceramic encapsulation material comprising a calcium aluminate cement matrix.
  • the cement-ceramic encapsu lation material may comprise alumina fillers.
  • the encapsulation covers the entire surface structuring.
  • the thermal conductance of the encapsulation is in the range 0.17-10 W/mK.
  • the encapsulation has a dielectric strength of at least 10 kV/mm.
  • the height of the encapsulation is more than two times larger than the height of the surface structuring.
  • the height of the encapsulation is more than four times larger than the height of the surface structuring.
  • one or more wire bonds or ribbon bonds are attached to the shaped metal body.
  • one or more wire bonds or ribbon bonds are electrically connected to a structure being electrically insulated from the top layer of the substrate.
  • the wire bonds or ribbon bonds are used as connectors providing electrical connection.
  • the use of wire bonds or ribbon bonds having a large cross-sectional area makes it possible to reduce the electrical re sistance and hereby the heat generation.
  • the surface structuring comprises wires or ribbons at tached to the top surface of the shaped metal body.
  • This type of surface struc turing can be provided using the same bonding machine utilised for other bonds in the module, and thus no additional steps or tools are required in the production process, leading to an efficient and cost-effective means of provid ing efficient cooling. Furthermore, it is possible to provide a very large surface area of the surface structuring.
  • the surface structuring comprises a plurality of structures made by a laser structuring process applied to the top surface of the shaped metal body.
  • a laser structuring process applied to the top surface of the shaped metal body.
  • the structures made by the laser structuring process are protruding structures and/or groove-shaped structures.
  • the ratio between height and distance of the struc tures is in the range from 1 : 2 up to 30 : 1.
  • the height of the structures is below 3 mm, preferably below 2 mm, more preferably below 1,5 mm, and in a small-scale pattern in the range of 0.5 to 1,0 mm, wherein the distance between the individual structures is below 6 mm, pref erably below 4 mm, more preferably below 3 mm, and in a small-scale pattern in the range of 1.5 to 2.0 mm.
  • the smallest size is achieved using laser struc turing and may be down to 20nm in form of pores or protrusions.
  • the laser structuring process is combined with another surface structuring process.
  • another surface structuring process it is possible to increase the surface area of the top surface of the shaped metal body even further.
  • the surface structuring comprises structures made by a stamping process applied to the top surface of the shaped metal body.
  • a stamping process applied to the top surface of the shaped metal body.
  • the surface structuring comprises protruding pins attached to the top surface of the shaped metal body.
  • the protruding pins may comprise a cylindrical portion.
  • the protruding pins may comprise a con ical portion, e.g. a pointed distal portion.
  • the surface structuring comprises protruding pins at tached to the top surface of the shaped metal body, wherein the protruding pins extend basically perpendicular to the top surface of the shaped metal body.
  • the shaped metal body comprises a lateral por tion without surface structuring.
  • a connector e.g. a wire bond
  • the shaped metal body comprises a central portion with out surface structuring.
  • a connector such as a wire bond
  • the shaped metal body in the central portion.
  • the substrate is attached to a base plate, pref erably by means of a sintering process.
  • a firm attachment between the substrate and the base plate can be provided.
  • the shaped metal body is sintered to the upper surface of the semiconductor. Accordingly, it is possible to provide a strong and reli able attachment between the shaped metal body and the semiconductor.
  • the substrate is a direct bonded copper (DBC) substrate.
  • DBC direct bonded copper
  • AMB active metal brazed
  • the method according to the invention is a method for manufacturing a sem iconductor module, wherein the method comprises the step of:
  • the method comprises the step of providing to the top surface of the shaped metal body a surface structuring that increases the surface area of the top surface.
  • the method comprises the step of connecting the shaped metal body and one additional component using wire bonds or ribbon bonds.
  • the stamped structures are provided to the shaped metal body prior to attaching the shaped metal body to the upper surface of the semiconductor.
  • lasered structures are provided to the shaped metal body prior to or after attaching the shaped metal body to the upper surface of the semiconductor.
  • the shaped metal body is fixed onto the upper surface of the semiconductor by using a sintering process.
  • the semiconductor is fixed onto the top layer of the sub strate by using a sintering process.
  • the substrate is a DBC substrate.
  • Fig. 1A shows a cross-sectional view of a prior art semiconductor mod ule
  • Fig. IB shows a close-up view of the prior art semiconductor module shown in Fig. 1A;
  • Fig. 2A shows a cross-sectional view of a semiconductor module accord ing to the invention
  • Fig. 2B shows a cross-sectional view of a portion of a semiconductor module according to the invention
  • Fig. 2C shows a cross-sectional view of a portion of another semiconduc tor module according to the invention
  • Fig. 2D shows a cross-sectional view of a portion of a further semicon ductor module according to the invention
  • Fig. 2E shows a top view of the semiconductor module shown in Fig. 2C;
  • Fig. 2F shows a top view of the semiconductor module shown in Fig. 2D;
  • Fig. 3A shows a top view of a shaped metal body comprising a top surface provided with surface structuring
  • Fig. 3B shows a top view of another shaped metal body comprising a top surface provided with surface structuring
  • Fig. 3C shows a close-up view of the surface structuring shown in Fig.
  • Fig. 3D shows a cross-sectional view of a shaped metal body comprising a top surface provided with surface structuring according to the invention
  • Fig. 3E shows a cross-sectional view of another shaped metal body com prising a top surface provided with surface structuring according to the invention
  • Fig. 4A shows a cross-sectional view of a shaped metal body comprising a top surface provided with surface structuring according to the invention
  • Fig. 4B shows a close-up cross-sectional view of a shaped metal body comprising a top surface provided with surface structuring ac cording to the invention
  • Fig. 4C shows the shaped metal body shown in Fig. 4B in a configuration, in which an encapsulation is covering the surface structuring.
  • a semiconductor module 2 of the pre sent invention is illustrated in Fig. 2A.
  • Fig. 2A is a schematic side view of a semiconductor module 2 according to the invention.
  • the semiconductor module 2 comprises a shaped metal body 20 fixed to an upper surface of a semiconductor 26 having a lower surface that is sintered onto a top layer 8' of a substrate 4.
  • the shaped metal body 20 comprises a top surface provided with surface structuring 32.
  • the surface structuring 32 increases the surface area of the top surface.
  • the semiconductor module 2 comprises a base plate 6.
  • a sintering layer 12 is provided on the top of the base plate 6 in order to attach (during a sintering process) a copper layer 8 thereto.
  • Other means of attaching the copper layer 8 to the base plate 6 are also possible, such as the use of solder.
  • the copper layer 8 constitutes the bottom part of a direct bonded copper (DBC) substrate 4.
  • the DCB substrate 4 comprises a ceramic substrate 10 sandwiched between the lower copper layer 8 and an upper copper layer 8'.
  • a separate conducting portion 16 of the upper copper layer is also shown here attached to the top portion of the ceramic substrate 10. This may form a separate section of the electrical circuit pattern on the upper surface of the DBC.
  • a shaped metal body 20 is attached to the semiconductor 26 (of silicon or silicon carbide).
  • the semiconductor 26 is attached to the upper copper layer 8' by means of a sintering layer 28.
  • the surface structuring 32 is attached to a shaped metal body 20 that is attached to the semiconductor 26 by means of a sintering layer 22.
  • a wire bond 18 is electrically connected to the shaped metal body 20 and the conducting portion 16.
  • the semiconductor module 2 comprises an encapsula tion 34 that is brought into thermal contact with the surface structuring 32.
  • the encapsulation 34 covers the entire surface structuring 32 and is electri cally insulating and thermally conductive. It can be seen that the height H2 of the encapsulation 34 is larger than the height Hi of the surface structuring 32.
  • the shaped metal body 20 is a copper foil.
  • the wire bond may be replaced by ribbon bond (e.g. made of cop per).
  • Fig. 2B illustrates a cross-sectional view of a portion of a semiconductor mod ule according to the invention comprising a shaped metal body 20 provided with surface structuring 32'.
  • the surface structuring 32' is attached to a shaped metal body 20 a chip 30.
  • the surface structuring 32' is made from wire bonds.
  • the surface structuring 32 comprises a central portion attached to the shaped metal body 20 and lateral portions that protrude therefrom. Accordingly, the surface area and thus the cooling capacity of the shaped metal body 20 is increased.
  • the surface structuring 32' may be attached to the shaped metal body 20 by using the same technique as when attaching a wire bond 18. It can be seen that the surface structuring 32' comprises a plurality of members made from wire bonds. These members are spaced from each other.
  • Fig. 2C illustrates a cross-sectional view of a portion of another semiconductor module according to the invention
  • Fig. 2E illustrates a top view of the semiconductor module shown in Fig. 2C in a configuration, in which no wire bond 18 is attached to the shaped metal body 20.
  • the shaped metal body 20 is provided with a surface structuring 32" formed by a plurality of pins protruding from the lower portion of the shaped metal body 20.
  • the shaped metal body 20 comprises a central portion 36 without surface structuring.
  • the central portion 36 is rectangular, however, it could be shaped differently.
  • a wire bond 18 is attached to the central portion 36.
  • Fig. 2D illustrates a cross-sectional view of a portion of a semiconductor mod ule according to the invention
  • Fig. 2F illustrates a top view of the semiconductor module shown in Fig. 2D in a configuration, in which no wire bond 18 is attached to the shaped metal body 20.
  • the shaped metal body 20 is provided with a surface structuring 32" comprising a plurality of pins protruding from the lower portion of the shaped metal body 20.
  • the shaped metal body 20 comprises a lateral portion 38 having no surface structuring.
  • the lateral portion 38 extends along the periphery of the shaped metal body 20.
  • a wire bond 18 is attached to the lateral portion 38.
  • Fig. 1A illustrates a cross-sectional view of a prior art semiconductor module 102.
  • the semiconductor module 102 comprises a heatsink 14 attached to the bottom surface of a base plate 6.
  • the prior art semiconductor module 102 comprises a metal body 20 fixed to an upper surface of a semiconductor 26 having a lower surface that is sintered onto a top layer 8' of a substrate 4.
  • the top surface of the metal body 20 is not provided with any surface struc turing.
  • a sintering layer 12 is provided on the top of the base plate 6 in order to attach a copper layer 8 thereto.
  • Other means of attaching the copper layer 8 to the base plate 6 are also known, such as the use of solder.
  • the copper layer 8 constitutes the bottom part of a DBC substrate 4 comprising a ceramic substrate 10 sandwiched between the lower copper layer 8 and an upper cop per layer 8'.
  • a conducting portion 16 is attached to the top portion of the ceramic substrate 10 in a distance from the upper copper layer 8'.
  • the semiconductor 26 is attached to the upper copper layer 8' by means of a sintering layer 28.
  • the surface structuring 32 is attached to a shaped metal body 20 that is attached to the semiconductor 26 by means of a sintering layer 22.
  • Fig. IB illustrates a close-up view of the prior art semiconductor module shown in Fig. 1A.
  • Fig. 3A illustrates a top view of a shaped metal body 20 comprising a top surface provided with surface structuring 32"'.
  • the surface structuring 32"' is made by a stamping process applied to the top surface of the shaped metal body 20.
  • protruding members and groove members it is possible to provide both protruding members and groove members.
  • protruding struc tures and groove structures are arranged in the top surface of the shaped metal body 20 in an alternating manner.
  • the shaped metal body 20 comprises a lateral portion 38 without surface structuring.
  • a connector e.g. a wire bond
  • the lateral portion 38 is pro vided in the right side of the shaped metal body 20.
  • Fig. 3B illustrates a top view of a shaped metal body 20 having a top surface provided with surface structuring 32"".
  • the surface structuring comprises pro truding pins attached to the top surface of the shaped metal body 20.
  • the protruding pins have a basically a cylindrical body portion and a conical distal portion.
  • the shaped metal body 20 comprises a lateral portion 38 without surface structuring.
  • the lateral portion 38 extends along the periphery of the shaped metal body 20.
  • Fig. 3C illustrates a close-up view of the surface structuring 32"" shown in Fig. 3B. It can be seen that the pins are evenly distributed and formed as convex bodies protruding from the shaped metal body.
  • Fig. 3D illustrates a cross-sectional view of a shaped metal body 20 comprises a top surface provided with surface structuring 32"" according to the inven tion.
  • the shaped metal body 20 is provided with a surface structuring 32"" formed by a plurality of pins protruding from the lower portion of the shaped metal body 20.
  • the shaped metal body 20 comprises a central portion, in which no surface structuring is provided.
  • a wire bond 18 is attached to the central portion.
  • it is achieved that a large contact area is provided between the wire bond 18 and the central portion of the shaped metal body 20.
  • Fig. 3E illustrates a cross-sectional view of a shaped metal body 20 comprising a top surface provided with surface structuring 32""' according to the inven tion.
  • the shaped metal body 20 is provided with a surface structuring 32"" formed by a plurality of pins protruding from the lower portion of the shaped metal body 20.
  • the shaped metal body 20 comprises a lateral portion, in which no surface structuring is provided.
  • a wire bond 18 is attached to the lateral portion.
  • a large contact area is provided between the wire bond 18 and the lateral portion of the shaped metal body 20.
  • Fig. 4A illustrates a cross-sectional view of a shaped metal body 20 comprising a top surface provided with surface structuring 32""' according to the inven tion.
  • the shaped metal body 20 is provided with a surface structuring 32'"" formed by a plurality of pins protruding from the lower portion of the shaped metal body 20.
  • the surface structuring 32'"" is provided at the entire top surface of the shaped metal body 20. Accordingly, a wire bond 18 attached to a portion of the shaped metal body 20 is attached to the surface structuring 32""'.
  • Fig. 4B illustrates a close-up cross-sectional view of a shaped metal body 20 which is provided with surface structuring 32' according to the invention.
  • the surface structuring 32' is made by a plurality of the wire bonds each being fixed in both ends to the top surface of the shaped metal body 20.
  • Each wire bond is basically U-shaped and protrudes from the top surface of the shaped metal body 20.
  • the wire bonds basically extend perpendicular to the top sur face of the shaped metal body 20.
  • Fig. 4C illustrates the shaped metal body 20 shown in Fig. 4B in a configura tion, in which an encapsulation 34 is covering the surface structuring 32'.
  • the thermal flow 42 is indicated with undulating arrows. It can be seen that the thermal flow 42 occurs from the entire outer surface of the encapsulation 34.
  • the encapsulation 34 entirely encloses the surface structuring 32' and the portion of the top surface of the shaped metal body 20, onto which the wire bonds are fixed.

Abstract

A semiconductor module (2) is disclosed. The semiconductor module (2) comprises a shaped metal body (20) fixed to an upper surface of a semiconductor (26) having a lower surface that is connected by sintering onto a top layer (S') of a substrate (4). The shaped metal body (20) comprises a top surface (30) provided with surface structuring (32) that increases the surface area of the top surface (30). The semiconductor module (2) enables an improved cooling solution and thus makes it possible to improve the volumetric power density.

Description

Semiconductor Module and Method for Manufacturing it
Field of invention
The present invention relates to a semiconductor module comprising a shaped metal body fixed to an upper surface of a semiconductor having a lower sur face that is sintered onto a top layer of a substrate. The invention also relates to a method for manufacturing a semiconductor module.
Prior art
Modern power electronics applies solid-state electronics to control and convert electric power with semiconductor switching devices such as diodes, thyristors and transistors. In contrast to electronic systems that are configured to trans mit and process signals and data, in power electronics substantial amounts of electrical energy are processed.
More and more applications are adopting power electronics technologies to improve energy efficiency, reliability, and control . Semiconductor components are essential for power semiconductors and, since such components are sen sitive to high temperatures, to avoid device failure due to thermal runaway, effective cooling is required.
Moreover, the increasing demand for enhanced functionality, smaller form factor, higher reliability and lower cost in electronic devices has initiated de velopment of large-scale integrations and miniaturizations. These miniaturi- zations and large-scale integrations in turn are responsible for a steady in crease in the power dissipated by the electronic chips and other components. Accordingly, effective cooling technologies have attracted the attention of pro ducers and researchers.
In general, air-cooling provides a simple, low cost, effective, and reliable cool ing solution. However, with the increase of heat flux dissipation, the prior air cooling technology may not be sufficient.
It is an object to provide a semiconductor module that enables an improved, effective, and reliable air-cooling solution.
Summary of the invention
The object of the present invention can be achieved by a semiconductor mod ule as defined in claim 1 and by a method as defined in claim 12. Preferred embodiments are defined in the dependent subclaims, explained in the fol lowing description and illustrated in the accompanying drawings.
The semiconductor module according to the invention is a semiconductor module comprising a shaped metal body fixed to an upper surface of a semi conductor having a lower surface that is sintered onto a top layer of a sub strate, wherein the shaped metal body comprises a top surface provided with surface structuring that increases the surface area of the top surface.
Hereby, it is possible to provide a semiconductor module that enables an im proved, effective, and reliable cooling solution. Accordingly, it is possible to increase the volumetric power density.
In a preferred embodiment of the invention, the shaped metal body is at tached to the upper surface of the semiconductor by means of a sintering layer.
The sintering technology of the invention may use a silver-based paste to connect the respective elements. Silver is thermally very stable, suffering from virtually no creep effects in power module service temperatures. This provides a considerable advantage over the standard solder technology using low-melting temperature metals for connecting chips to substrates or other elements. The temperatures in power modules are in the range of creep effects for solder alloys, meaning that they can crack and/or deform easily in service. Moreover, in terms of process flow, a soldering process requires a subsequent process step to clean the surface from unwanted chemicals. This is not required in a sintering process.
The surface structuring may be of any suitable type as long as it increases the surface area of the top surface. The increased surface area of the top surface increases the cooling capacity of the top surface. Accordingly, it is an ad vantage to have a surface structuring that increases the surface area of the top surface to a large extent.
In one embodiment, the surface structuring increases the surface area of that portion of the top surface at which the surface structuring is provided, with at least 10 %.
In one embodiment, the surface structuring increases the surface area of that portion of the top surface at which the surface structuring is provided, with at least 25 %.
In one embodiment, the surface structuring increases the surface area of that portion of the top surface at which the surface structuring is provided, with at least 40 %.
In one embodiment, the surface structuring increases the surface area of that portion of the top surface at which the surface structuring is provided, with at least 50 %.
In one embodiment, the surface structuring increases the surface area of that portion of the top surface at which the surface structuring is provided, with more than 50 %. In one embodiment, the semiconductor module may be a power module for automotive, solar, wind or industrial applications.
The shaped metal body may be a plate-shaped metal body. In one embodi ment, the shaped metal body is made of copper.
In one embodiment, the shaped metal body is a copper foil.
In a preferred embodiment, the semiconductor module is a power module.
In one embodiment, the shaped metal body is fixed to an upper surface of the semiconductor, the semiconductor having a lower surface being sintered onto a top layer of the substrate.
In one embodiment, the semiconductor module comprises an encapsulation that is brought into thermal contact with the surface structuring, wherein the encapsulation covers at least a portion the surface structuring and is electri cally insulating and thermally conductive.
By applying a thermally conductive encapsulation, it is possible to increase the heat transfer coefficient of the media (encapsulation) covering the surface structuring and thus enhance the cooling capacity of the surface structuring. Accordingly, it advantageous to apply an encapsulation having a thermal con ductance that is higher than a predefined level such as more than 0.1 W/mK.
In one embodiment, the electrically insulating and thermally conductive en capsulation has a thermal conductance in the range 0.1-15 W/mK.
In one embodiment, the electrically insulating and thermally conductive en capsulation has a thermal conductance in the range 0.15-10 W/mK. In one embodiment, the electrically insulating and thermally conductive en capsulation is made of epoxy, preferably epoxy having a thermal conductance in the range 1 to 10 W/mK.
In one embodiment, the electrically insulating and thermally conductive en capsulation is made of, preferably silicone having a thermal conductance in the range 0.17 W/mK up to 3 W/mK.
In one embodiment, the electrically insulating and thermally conductive en capsulation is made of cement, preferably cement having a thermal conduct ance in the range with 2-10 W/mK.
In one embodiment, the electrically insulating and thermally conductive en capsulation is a cement-ceramic encapsulation material comprising a calcium aluminate cement matrix. In one embodiment, the cement-ceramic encapsu lation material may comprise alumina fillers.
In one embodiment, the encapsulation covers the entire surface structuring. Hereby, it is possible to increase the cooling capacity of the surface structuring to a very high level.
In one embodiment, the thermal conductance of the encapsulation is in the range 0.17-10 W/mK.
In one embodiment, the encapsulation has a dielectric strength of at least 10 kV/mm.
It may be an advantage that the height of the encapsulation is more than two times larger than the height of the surface structuring.
In one embodiment, the height of the encapsulation is more than four times larger than the height of the surface structuring. Hereby, it is possible to pro vide a semiconductor, wherein the cooling capacity of the surface structuring is enhanced.
In one embodiment, one or more wire bonds or ribbon bonds are attached to the shaped metal body. By this way it is possible to increase the surface area of the shaped metal body and thus enhance the cooling capacity by simple means.
In one embodiment, one or more wire bonds or ribbon bonds are electrically connected to a structure being electrically insulated from the top layer of the substrate. Thus, the wire bonds or ribbon bonds are used as connectors providing electrical connection. The use of wire bonds or ribbon bonds having a large cross-sectional area makes it possible to reduce the electrical re sistance and hereby the heat generation.
In one embodiment, the surface structuring comprises wires or ribbons at tached to the top surface of the shaped metal body. This type of surface struc turing can be provided using the same bonding machine utilised for other bonds in the module, and thus no additional steps or tools are required in the production process, leading to an efficient and cost-effective means of provid ing efficient cooling. Furthermore, it is possible to provide a very large surface area of the surface structuring.
In one embodiment, the surface structuring comprises a plurality of structures made by a laser structuring process applied to the top surface of the shaped metal body. Hereby, it is possible to increase the surface structuring without adding any structures.
It may be advantageous that the structures made by the laser structuring process are protruding structures and/or groove-shaped structures. According to the invention, the ratio between height and distance of the struc tures is in the range from 1 : 2 up to 30 : 1. In an inventive pattern, the height of the structures is below 3 mm, preferably below 2 mm, more preferably below 1,5 mm, and in a small-scale pattern in the range of 0.5 to 1,0 mm, wherein the distance between the individual structures is below 6 mm, pref erably below 4 mm, more preferably below 3 mm, and in a small-scale pattern in the range of 1.5 to 2.0 mm. The smallest size is achieved using laser struc turing and may be down to 20nm in form of pores or protrusions.
In one embodiment, the laser structuring process is combined with another surface structuring process. Thus, it is possible to increase the surface area of the top surface of the shaped metal body even further.
In one embodiment, the surface structuring comprises structures made by a stamping process applied to the top surface of the shaped metal body. Hereby, it is possible to provide protruding structures and groove structures arranged in an alternating manner.
It may be an advantage that the surface structuring comprises protruding pins attached to the top surface of the shaped metal body. The protruding pins may comprise a cylindrical portion. The protruding pins may comprise a con ical portion, e.g. a pointed distal portion.
In one embodiment, the surface structuring comprises protruding pins at tached to the top surface of the shaped metal body, wherein the protruding pins extend basically perpendicular to the top surface of the shaped metal body.
It may be advantageous that the shaped metal body comprises a lateral por tion without surface structuring. Hereby, it is possible to establish a good electrical connection (providing a large contact area) between a connector (e.g. a wire bond) and the shaped metal body in the lateral portion.
In one embodiment, the shaped metal body comprises a central portion with out surface structuring. Hereby, it is possible to provide a good electrical con nection between a connector such as a wire bond and the shaped metal body in the central portion.
It may be an advantage that the substrate is attached to a base plate, pref erably by means of a sintering process. Hereby, a firm attachment between the substrate and the base plate can be provided.
In one embodiment, the shaped metal body is sintered to the upper surface of the semiconductor. Accordingly, it is possible to provide a strong and reli able attachment between the shaped metal body and the semiconductor.
In one embodiment, the substrate is a direct bonded copper (DBC) substrate. Hereby, it is possible to achieve a very good thermal conductivity. The use of other substrates is also possible, such as ceramic (or ceramic-metal) sub strates in general, and/or active metal brazed (AMB) substrates.
The method according to the invention is a method for manufacturing a sem iconductor module, wherein the method comprises the step of:
a) placing a shaped metal body on an upper surface of a semiconductor; b) placing the semiconductor on a substrate;
c) fixing the shaped metal body onto the upper surface of the semiconduc tor and fixing the semiconductor onto the top layer of the substrate, wherein the method comprises the step of providing to the top surface of the shaped metal body a surface structuring that increases the surface area of the top surface. Hereby, it is possible to manufacture a semiconductor module having a high volumetric power density due to the improved cooling properties caused by the increased surface area.
In one embodiment, the method comprises the step of connecting the shaped metal body and one additional component using wire bonds or ribbon bonds.
In one embodiment, the stamped structures are provided to the shaped metal body prior to attaching the shaped metal body to the upper surface of the semiconductor.
In one embodiment, lasered structures are provided to the shaped metal body prior to or after attaching the shaped metal body to the upper surface of the semiconductor. Hereby, it is possible to increases the surface area of the top surface without adding structures to the shaped metal body.
It may be an advantage that the shaped metal body is fixed onto the upper surface of the semiconductor by using a sintering process.
In one embodiment, the semiconductor is fixed onto the top layer of the sub strate by using a sintering process.
It may be advantageous that the substrate is a DBC substrate.
Description of the Drawings
The invention will become more fully understood from the detailed description given herein below. The accompanying drawings are given by way of illustra tion only, and thus, they are not limitative of the present invention. In the accompanying drawings:
Fig. 1A shows a cross-sectional view of a prior art semiconductor mod ule; Fig. IB shows a close-up view of the prior art semiconductor module shown in Fig. 1A;
Fig. 2A shows a cross-sectional view of a semiconductor module accord ing to the invention;
Fig. 2B shows a cross-sectional view of a portion of a semiconductor module according to the invention;
Fig. 2C shows a cross-sectional view of a portion of another semiconduc tor module according to the invention;
Fig. 2D shows a cross-sectional view of a portion of a further semicon ductor module according to the invention;
Fig. 2E shows a top view of the semiconductor module shown in Fig. 2C;
Fig. 2F shows a top view of the semiconductor module shown in Fig. 2D;
Fig. 3A shows a top view of a shaped metal body comprising a top surface provided with surface structuring;
Fig. 3B shows a top view of another shaped metal body comprising a top surface provided with surface structuring;
Fig. 3C shows a close-up view of the surface structuring shown in Fig.
3B;
Fig. 3D shows a cross-sectional view of a shaped metal body comprising a top surface provided with surface structuring according to the invention;
Fig. 3E shows a cross-sectional view of another shaped metal body com prising a top surface provided with surface structuring according to the invention;
Fig. 4A shows a cross-sectional view of a shaped metal body comprising a top surface provided with surface structuring according to the invention;
Fig. 4B shows a close-up cross-sectional view of a shaped metal body comprising a top surface provided with surface structuring ac cording to the invention and
Fig. 4C shows the shaped metal body shown in Fig. 4B in a configuration, in which an encapsulation is covering the surface structuring.
Detailed description of the invention
Referring now in detail to the drawings for the purpose of illustrating preferred embodiments of the present invention, a semiconductor module 2 of the pre sent invention is illustrated in Fig. 2A.
Fig. 2A is a schematic side view of a semiconductor module 2 according to the invention. The semiconductor module 2 comprises a shaped metal body 20 fixed to an upper surface of a semiconductor 26 having a lower surface that is sintered onto a top layer 8' of a substrate 4. The shaped metal body 20 comprises a top surface provided with surface structuring 32. Hereby, the surface structuring 32 increases the surface area of the top surface.
The semiconductor module 2 comprises a base plate 6. A sintering layer 12 is provided on the top of the base plate 6 in order to attach (during a sintering process) a copper layer 8 thereto. Other means of attaching the copper layer 8 to the base plate 6 are also possible, such as the use of solder. The copper layer 8 constitutes the bottom part of a direct bonded copper (DBC) substrate 4. The DCB substrate 4 comprises a ceramic substrate 10 sandwiched between the lower copper layer 8 and an upper copper layer 8'. A separate conducting portion 16 of the upper copper layer is also shown here attached to the top portion of the ceramic substrate 10. This may form a separate section of the electrical circuit pattern on the upper surface of the DBC.
A shaped metal body 20 is attached to the semiconductor 26 (of silicon or silicon carbide). The semiconductor 26 is attached to the upper copper layer 8' by means of a sintering layer 28. The surface structuring 32 is attached to a shaped metal body 20 that is attached to the semiconductor 26 by means of a sintering layer 22. A wire bond 18 is electrically connected to the shaped metal body 20 and the conducting portion 16. The semiconductor module 2 comprises an encapsula tion 34 that is brought into thermal contact with the surface structuring 32. The encapsulation 34 covers the entire surface structuring 32 and is electri cally insulating and thermally conductive. It can be seen that the height H2 of the encapsulation 34 is larger than the height Hi of the surface structuring 32.
In one embodiment, the shaped metal body 20 is a copper foil. In one em bodiment, the wire bond may be replaced by ribbon bond (e.g. made of cop per).
Fig. 2B illustrates a cross-sectional view of a portion of a semiconductor mod ule according to the invention comprising a shaped metal body 20 provided with surface structuring 32'. The surface structuring 32' is attached to a shaped metal body 20 a chip 30. The surface structuring 32' is made from wire bonds. The surface structuring 32 comprises a central portion attached to the shaped metal body 20 and lateral portions that protrude therefrom. Accordingly, the surface area and thus the cooling capacity of the shaped metal body 20 is increased. The surface structuring 32' may be attached to the shaped metal body 20 by using the same technique as when attaching a wire bond 18. It can be seen that the surface structuring 32' comprises a plurality of members made from wire bonds. These members are spaced from each other.
Fig. 2C illustrates a cross-sectional view of a portion of another semiconductor module according to the invention, whereas Fig. 2E illustrates a top view of the semiconductor module shown in Fig. 2C in a configuration, in which no wire bond 18 is attached to the shaped metal body 20. The shaped metal body 20 is provided with a surface structuring 32" formed by a plurality of pins protruding from the lower portion of the shaped metal body 20. The shaped metal body 20 comprises a central portion 36 without surface structuring. The central portion 36 is rectangular, however, it could be shaped differently. In Fig. 2C, a wire bond 18 is attached to the central portion 36.
Fig. 2D illustrates a cross-sectional view of a portion of a semiconductor mod ule according to the invention, whereas Fig. 2F illustrates a top view of the semiconductor module shown in Fig. 2D in a configuration, in which no wire bond 18 is attached to the shaped metal body 20.
The shaped metal body 20 is provided with a surface structuring 32" compris ing a plurality of pins protruding from the lower portion of the shaped metal body 20. The shaped metal body 20 comprises a lateral portion 38 having no surface structuring. The lateral portion 38 extends along the periphery of the shaped metal body 20. In Fig. 2D, a wire bond 18 is attached to the lateral portion 38.
Fig. 1A illustrates a cross-sectional view of a prior art semiconductor module 102. The semiconductor module 102 comprises a heatsink 14 attached to the bottom surface of a base plate 6. The prior art semiconductor module 102 comprises a metal body 20 fixed to an upper surface of a semiconductor 26 having a lower surface that is sintered onto a top layer 8' of a substrate 4. The top surface of the metal body 20 is not provided with any surface struc turing.
A sintering layer 12 is provided on the top of the base plate 6 in order to attach a copper layer 8 thereto. Other means of attaching the copper layer 8 to the base plate 6 are also known, such as the use of solder. The copper layer 8 constitutes the bottom part of a DBC substrate 4 comprising a ceramic substrate 10 sandwiched between the lower copper layer 8 and an upper cop per layer 8'. A conducting portion 16 is attached to the top portion of the ceramic substrate 10 in a distance from the upper copper layer 8'. The semiconductor 26 is attached to the upper copper layer 8' by means of a sintering layer 28. The surface structuring 32 is attached to a shaped metal body 20 that is attached to the semiconductor 26 by means of a sintering layer 22.
Fig. IB illustrates a close-up view of the prior art semiconductor module shown in Fig. 1A.
Fig. 3A illustrates a top view of a shaped metal body 20 comprising a top surface provided with surface structuring 32"'. The surface structuring 32"' is made by a stamping process applied to the top surface of the shaped metal body 20. Although it is not shown, it is possible to provide both protruding members and groove members. In a preferred embodiment, protruding struc tures and groove structures are arranged in the top surface of the shaped metal body 20 in an alternating manner.
The shaped metal body 20 comprises a lateral portion 38 without surface structuring. Hereby, it is possible to establish a good electrical connection (having a large contact area) between a connector (e.g. a wire bond) and the shaped metal body 20 in the lateral portion 38. The lateral portion 38 is pro vided in the right side of the shaped metal body 20.
Fig. 3B illustrates a top view of a shaped metal body 20 having a top surface provided with surface structuring 32"". The surface structuring comprises pro truding pins attached to the top surface of the shaped metal body 20. The protruding pins have a basically a cylindrical body portion and a conical distal portion.
The shaped metal body 20 comprises a lateral portion 38 without surface structuring. The lateral portion 38 extends along the periphery of the shaped metal body 20.
Fig. 3C illustrates a close-up view of the surface structuring 32"" shown in Fig. 3B. It can be seen that the pins are evenly distributed and formed as convex bodies protruding from the shaped metal body.
Fig. 3D illustrates a cross-sectional view of a shaped metal body 20 comprises a top surface provided with surface structuring 32"" according to the inven tion. The shaped metal body 20 is provided with a surface structuring 32"" formed by a plurality of pins protruding from the lower portion of the shaped metal body 20. The shaped metal body 20 comprises a central portion, in which no surface structuring is provided. A wire bond 18 is attached to the central portion. Hereby, it is achieved that a large contact area is provided between the wire bond 18 and the central portion of the shaped metal body 20.
Fig. 3E illustrates a cross-sectional view of a shaped metal body 20 comprising a top surface provided with surface structuring 32""' according to the inven tion. The shaped metal body 20 is provided with a surface structuring 32"" formed by a plurality of pins protruding from the lower portion of the shaped metal body 20. The shaped metal body 20 comprises a lateral portion, in which no surface structuring is provided. A wire bond 18 is attached to the lateral portion. Hereby, a large contact area is provided between the wire bond 18 and the lateral portion of the shaped metal body 20.
Fig. 4A illustrates a cross-sectional view of a shaped metal body 20 comprising a top surface provided with surface structuring 32""' according to the inven tion. The shaped metal body 20 is provided with a surface structuring 32'"" formed by a plurality of pins protruding from the lower portion of the shaped metal body 20. The surface structuring 32'"" is provided at the entire top surface of the shaped metal body 20. Accordingly, a wire bond 18 attached to a portion of the shaped metal body 20 is attached to the surface structuring 32""'. Fig. 4B illustrates a close-up cross-sectional view of a shaped metal body 20 which is provided with surface structuring 32' according to the invention. The surface structuring 32' is made by a plurality of the wire bonds each being fixed in both ends to the top surface of the shaped metal body 20. Each wire bond is basically U-shaped and protrudes from the top surface of the shaped metal body 20. The wire bonds basically extend perpendicular to the top sur face of the shaped metal body 20.
Fig. 4C illustrates the shaped metal body 20 shown in Fig. 4B in a configura tion, in which an encapsulation 34 is covering the surface structuring 32'. The thermal flow 42 is indicated with undulating arrows. It can be seen that the thermal flow 42 occurs from the entire outer surface of the encapsulation 34.
The encapsulation 34 entirely encloses the surface structuring 32' and the portion of the top surface of the shaped metal body 20, onto which the wire bonds are fixed.
Artlkel L List of reference numerals
2 Semiconductor module (power module)
4 Direct bonded copper (DBC) substrate
6 Base plate
8, 8' Copper layer
10 Ceramic substrate
12 Sinter layer
14 Heatsink
16 Conductor
18 Wire bond or ribbon bond (e.g. made of copper)
20 Shaped metal body
22 Sinter layer
26 Semiconductor (such as a semiconductor comprising silicon or silicon carbide)
28 Sinter layer
30 Chip
32, 32', 32" Surface structuring
32'", 32"", 32'"" Surface structuring
34 Encapsulation
36 Central portion
38 Lateral portion
42 Thermal flow
102 Prior art semiconductor module
H i, H2 Height

Claims

Claims
1. A semiconductor module (2) comprising a shaped metal body (20) fixed to an upper surface of a semiconductor (26) having a lower surface that is sin tered onto a top layer (8') of a substrate (4), characterised in that the shaped metal body (20) comprises a top surface (30) provided with surface structuring (32, 32', 32", 32"', 32"", 32'"") that increases the surface area of the top surface (30),
2. A semiconductor module (2) according to claim 1, characterized in that the shaped metal body (20) is attached to the upper surface of the semicon ductor (26) by means of a sintering layer (22).
3. A semiconductor module (2) according to claim 1 or 2 , characterised in that the semiconductor module (2) comprises an encapsulation (34) that is brought into thermal contact with the surface structuring (32, 32', 32", 32'", 32"", 32'""), wherein the encapsulation (34) covers at least a portion the surface structuring (32, 32', 32", 32'", 32"", 32'"") and is electrically insulat ing and thermally conductive.
4. A semiconductor module (2) according to claim 3, characterised in that the encapsulation (34) has a thermal conductance in the range 0.17-10 W/mK.
5. A semiconductor module (2) according to one of the claims 3-4, characterised in that the encapsulation (34) has a dielectric strength of at least 10k V/mm.
6. A semiconductor module (2) according to one of claims 3-5, characterised in that the encapsulation (34) is made of cement.
7. A semiconductor module (2) according to one of the preceding claims, characterised in that one or more wire bonds or ribbon bonds (18) are at tached to the shaped metal body (20).
8. A semiconductor module (2) according to one of the preceding claims, characterised in that the surface structuring (32, 32', 32", 32"', 32"", 32'"") comprises wires (32') or ribbons attached to the top surface (30) of the shaped metal body (20).
9. A semiconductor module (2) according to one of the preceding claims, characterised in that the surface structuring (32, 32', 32", 32'", 32"", 32'"") comprises a plurality of structures (32") made by a laser structuring process applied to the top surface (30) of the shaped metal body (20).
10. A semiconductor module (2) according to one of the preceding claims, characterised in that the surface structuring (32, 32', 32", 32'", 32"", 32'"") comprises structures (32") made by a stamping process applied to the top surface (30) of the shaped metal body (20).
11. A semiconductor module (2) according to one of the preceding claims, characterised in that the surface structuring (32, 32', 32", 32'", 32"", 32'"") comprises protruding pins (32'"") attached to the top surface (30) of the shaped metal body (2T0).
12. A semiconductor module (2) according to one of the preceding claims, characterised in that the shaped metal body (20) comprises a lateral portion (38) without surface structuring (32, 32', 32", 32'", 32"", 32'"").
13. A semiconductor module (2) according to one of the preceding claims, characterised in that the shaped metal body (20) comprises a central por tion (36) without surface structuring (32, 32', 32", 32'", 32"", 32'"").
14. A method for manufacturing a semiconductor module (2), wherein the method comprises the step of:
a) placing a shaped metal body (20) on an upper surface of a semiconductor (26);
b) placing the semiconductor (26) on a substrate (4);
c) fixing the shaped metal body (20) onto the upper surface of the semi conductor (26) and fixing the semiconductor (26) onto the top layer (8') of the substrate (4);
characterised in that the method comprises the step of providing to the top surface (30) of the shaped metal body (20) a surface structuring (32, 32', 32", 32"', 32"", 32'"") that increases the surface area of the top surface (30).
15. A method according to claim 14, characterised in that the method com prises the step of attaching the shaped metal body (20) to the upper surface of the semiconductor (26) by means of a sintering layer (22).
16. A method according to claim 14 or 15, characterised in that the method comprises the step of connecting the shaped metal body (20) and one addi tional component (16) using wire bonds or ribbon bonds (18).
17. A method according to any of claims 14-16, characterised in that the stamped structures (32'") are provided to the shaped metal body (20) prior to attaching the shaped metal body (20) to the upper surface of the semicon ductor (26).
PCT/EP2020/058532 2019-04-05 2020-03-26 Semiconductor module and method for manufacturing it WO2020201005A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006012847A1 (en) * 2004-07-29 2006-02-09 Infineon Technologies Ag Vertical power semiconductor component comprising a semiconductor chip, and method for producing the same
US20160260648A1 (en) * 2013-11-07 2016-09-08 Heraeus Deutschland GmbH & Co. KG Semi-conductor module with an encapsulating cement mass that covers a semi-conductor component
WO2019197304A1 (en) * 2018-04-11 2019-10-17 Abb Schweiz Ag Material reduced metallic plate on power semiconductor chip

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5514906A (en) 1993-11-10 1996-05-07 Fujitsu Limited Apparatus for cooling semiconductor chips in multichip modules
JP3602453B2 (en) 2000-08-31 2004-12-15 Necエレクトロニクス株式会社 Semiconductor device
JP4112816B2 (en) 2001-04-18 2008-07-02 株式会社東芝 Semiconductor device and manufacturing method of semiconductor device
CN100435324C (en) 2004-12-20 2008-11-19 半导体元件工业有限责任公司 Semiconductor package structure having enhanced thermal dissipation characteristics
JP5857468B2 (en) 2011-06-22 2016-02-10 株式会社デンソー Semiconductor device
DE102016117841A1 (en) 2016-09-21 2018-03-22 HYUNDAI Motor Company 231 Pack with roughened encapsulated surface to promote adhesion

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006012847A1 (en) * 2004-07-29 2006-02-09 Infineon Technologies Ag Vertical power semiconductor component comprising a semiconductor chip, and method for producing the same
US20160260648A1 (en) * 2013-11-07 2016-09-08 Heraeus Deutschland GmbH & Co. KG Semi-conductor module with an encapsulating cement mass that covers a semi-conductor component
WO2019197304A1 (en) * 2018-04-11 2019-10-17 Abb Schweiz Ag Material reduced metallic plate on power semiconductor chip

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