WO2020199018A1 - 像素补偿电路、显示面板、驱动方法及显示装置 - Google Patents
像素补偿电路、显示面板、驱动方法及显示装置 Download PDFInfo
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- WO2020199018A1 WO2020199018A1 PCT/CN2019/080633 CN2019080633W WO2020199018A1 WO 2020199018 A1 WO2020199018 A1 WO 2020199018A1 CN 2019080633 W CN2019080633 W CN 2019080633W WO 2020199018 A1 WO2020199018 A1 WO 2020199018A1
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Definitions
- the present disclosure relates to the field of display technology, and in particular to a pixel compensation circuit, a display panel, a driving method, and a display device.
- OLED display panels have the advantages of low energy consumption and self-luminescence, and are one of the hot spots in the field of flat panel display panel research. Since OLED is driven by current, a stable current is required to control its light emission. Generally, an OLED display panel uses a pixel compensation circuit to generate a driving current to drive the OLED to emit light.
- a driving circuit configured to generate a driving current input to the first electrode of the light emitting device
- a light emitting control circuit configured to provide a first power signal to the second electrode of the light emitting device in response to a first light emitting control signal, and to provide a second power signal to the light emitting device in response to a second light emitting control signal
- the second electrode wherein, the first power signal and the second power signal have opposite levels.
- the driving circuit and the light emitting device are configured in a display area of a display panel, and the light emission control circuit is configured in a non-display area of the display panel.
- the light emission control circuit includes: a first transistor and a second transistor;
- the gate of the first transistor is configured to receive the first light emission control signal, the first electrode of the first transistor is configured to receive the first power signal, and the second electrode of the first transistor is connected to The second electrode of the light emitting device is coupled;
- the gate of the second transistor is configured to receive the second light emission control signal
- the first electrode of the second transistor is configured to receive the second power signal
- the second electrode of the second transistor is connected to The second electrode of the light emitting device is coupled.
- the first light emission control signal and the second light emission control signal are the same signal, and the transistor types of the first transistor and the second transistor are different.
- the first light emission control signal is different from the second light emission control signal, and the transistor types of the first transistor and the second transistor are the same.
- the driving circuit includes: a driving transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor;
- the gate of the driving transistor is coupled to the first end of the first capacitor, the first electrode of the driving transistor is configured to receive the first power signal, and the second electrode of the driving transistor is connected to the The first electrode of the light emitting device is coupled;
- the gate of the third transistor is coupled to the scan signal terminal, the first electrode of the third transistor is coupled to the data signal terminal, and the second electrode of the third transistor is coupled to the gate of the driving transistor ;
- the gate of the fourth transistor is coupled to the reset signal terminal, the first electrode of the fourth transistor is coupled to the initialization signal terminal, and the second electrode of the fourth transistor is coupled to the first electrode of the light emitting device Connect
- the second end of the first capacitor is coupled to the first electrode of the light emitting device
- the first terminal of the second capacitor is configured to receive the first power signal, and the second terminal of the second capacitor is coupled to the first electrode of the light emitting device.
- an embodiment of the present disclosure also provides a display panel, which includes: a base substrate and a plurality of pixel compensation circuits described above; wherein, the base substrate includes a display area and a non-display area surrounding the display area;
- the driving circuit and the light emitting device in each pixel compensation circuit are located in the display area of the base substrate.
- the light emission control circuit is located in the non-display area.
- the display panel further includes: at least one of a driving chip, a flexible circuit board, and a printed circuit board;
- the light emission control circuit is located in at least one of the driving chip, the flexible circuit board and the printed circuit board.
- the display area includes: a plurality of sub-display areas; all the light-emitting devices in each of the sub-display areas are coupled to the same light-emitting control circuit.
- each of the sub-display areas corresponds to one of the light-emitting control circuits, and the light-emitting control circuits are located in the corresponding sub-display areas on the base substrate.
- each of the sub-display areas extends along a first direction, and each of the sub-display areas is arranged along a second direction; the first direction crosses the second direction.
- each of the sub-display areas is distributed in a matrix arrangement.
- all the pixel compensation circuits share a light emission control circuit.
- the display panel further includes: a plurality of gate lines, a gate driving circuit, and a gate control circuit corresponding to each of the gate lines one-to-one;
- Each of the gate lines is respectively coupled to a signal output terminal of the gate driving circuit through a corresponding gate control circuit;
- the gate control circuit is configured to conduct the fixed voltage signal terminal with the corresponding gate line in response to the conduction control signal having the first level; and in response to the conduction control signal having the second level , Connecting the connected signal output terminal to the corresponding gate line.
- the conduction control signal received by each of the gate control circuits is the same signal.
- embodiments of the present disclosure also provide a display device, which includes the above-mentioned display panel.
- one frame time includes:
- At least part of the light emitting control circuit provides a first power signal to the second electrode of the light emitting device in response to the first light emitting control signal;
- At least part of the light-emitting control circuit responds to the second light-emitting control signal to provide a second power signal to the second electrode of the light-emitting device; all the driving circuits generate driving input to the first electrode of the light-emitting device The current drives the light-emitting device to emit light.
- the non-luminous phase includes:
- all third transistors are turned on at the same time in response to the signal at the scan signal terminal, and the reference voltage signal at the data signal terminal is provided to the gate of the driving transistor; all fourth transistors are turned on at the same time in response to the signal at the reset signal terminal, and will initialize the signal terminal at the same time.
- all the third transistors are turned on simultaneously in response to the signal from the scan signal terminal, and the reference voltage signal of the data signal terminal is provided to the gate of the driving transistor; all the driving transistors are turned on simultaneously On, write the threshold voltage of the drive transistor to the second pole of the drive transistor;
- the third transistor is turned on row by row in response to the signal from the scan signal terminal, and provides the data signal from the data signal terminal to the gate of the driving transistor; and through the first capacitor and the The second capacitor writes the voltage of the data signal into the second electrode of the driving transistor.
- FIG. 1 is a schematic structural diagram of a pixel compensation circuit provided by an embodiment of the disclosure
- FIG. 3 is one of signal timing diagrams provided by an embodiment of the disclosure.
- FIG. 4 is a second schematic diagram of a specific structure of a pixel compensation circuit provided by an embodiment of the disclosure.
- FIG. 5 is the second signal timing diagram provided by an embodiment of the disclosure.
- FIG. 6 is the third schematic diagram of a specific structure of a pixel compensation circuit provided by an embodiment of the disclosure.
- FIG. 7 is the third signal timing diagram provided by an embodiment of the disclosure.
- FIG. 8 is a fourth schematic diagram of a specific structure of a pixel compensation circuit provided by an embodiment of the disclosure.
- FIG. 9 is the fourth signal timing diagram provided by an embodiment of the disclosure.
- FIG. 10 is one of schematic structural diagrams of a display panel provided by an embodiment of the disclosure.
- FIG. 11 is the second schematic diagram of the structure of the display panel provided by the embodiment of the disclosure.
- FIG. 12 is the third structural diagram of a display panel provided by an embodiment of the disclosure.
- FIG. 13 is a schematic diagram of a scan signal provided by an embodiment of the disclosure.
- FIG. 14 is the fifth signal timing diagram provided by an embodiment of the disclosure.
- 16 is the fifth structural diagram of the display panel provided by the embodiments of the disclosure.
- FIG. 17 is a flowchart of a driving method of a display panel provided by an embodiment of the disclosure.
- FIG. 18 is a schematic structural diagram of a display device provided by an embodiment of the disclosure.
- a driving current is generated by a driving transistor in the pixel compensation circuit, and the driving current is provided to the OLED to drive the OLED to emit light.
- the threshold voltage V th of the driving transistor is uneven, which causes the driving current to change, which causes uneven display brightness, thereby affecting the display effect of the entire image.
- a pixel compensation circuit capable of compensating the threshold voltage V th may be used to generate the driving current.
- a non-light-emitting phase is set within one frame time to compensate the threshold voltage V th in the non-light-emitting phase.
- the pixel compensation circuit needs to be provided with a larger number of transistors. This will cause greater process difficulty, increased production costs, and cause the pixel compensation circuit to occupy a larger area, which is not conducive to the realization of high resolution of the display panel.
- the embodiments of the present disclosure provide a pixel compensation circuit with a simple structure, which can reduce process difficulty, reduce production costs, and reduce the area occupied by the pixel compensation circuit, thereby facilitating the display panel to achieve high resolution.
- Some pixel compensation circuits provided by the embodiments of the present disclosure may include: a light-emitting device L, a driving circuit 10, and a light-emitting control circuit 20.
- the driving circuit 10 is configured to generate a driving current input to the first electrode of the light emitting device L.
- the light emission control circuit 20 is configured to provide the first power signal ELVDD to the second electrode of the light emitting device L in response to the first light emission control signal EM1, and to provide the second power signal ELVSS to the light emitting device in response to the second light emission control signal EM2
- the second electrode of L wherein the first power signal ELVDD and the second power signal ELVSS have opposite levels.
- the light emitting control circuit responds to the first light emitting control signal to provide the first power signal to the second electrode of the light emitting device to control the light emitting device not to emit light.
- the driving current input to the first electrode of the light-emitting device is generated by the driving circuit, and the second power signal is provided to the second electrode of the light-emitting device through the light-emitting control circuit in response to the second light-emitting control signal, so that the driving current Drive the light emitting device to emit light. Therefore, a simple structure can be used to control whether the light-emitting device emits light, thereby reducing process difficulty, reducing production costs, reducing the area occupied by the pixel compensation circuit, and helping the display panel to achieve high resolution.
- a light emitting device has a turn-on voltage, and emits light when the voltage difference between the first electrode and the second electrode of the light-emitting device is greater than or equal to the turn-on voltage.
- the first electrode of the light-emitting device is electrically connected with the driving circuit
- the second electrode of the light-emitting device is electrically connected with the light-emitting control circuit.
- the light emitting device may include: an electroluminescent diode.
- the anode of the electroluminescent diode is used as the first electrode of the light emitting device
- the cathode of the electroluminescent diode is used as the second electrode of the light emitting device.
- the electroluminescent diode may include: OLED, or Quantum Dot Light Emitting Diodes (QLED).
- the driving circuit and the light emitting device may be configured in the display area of the display panel, so that the display panel realizes screen display.
- the light emitting control circuit can be configured in the non-display area of the display panel, which can reduce the space occupied by the display area.
- the light emitting control circuit may be located in a non-display area arranged around the display area in the base substrate of the display panel.
- the light emission control circuit may also be in at least one of a driving chip, a flexible circuit board, and a printed circuit board in the display panel.
- the first power signal ELVDD may be a high-level voltage signal, for example, the voltage V dd of the first power signal ELVDD is generally a positive value.
- the second power signal ELVSS may be a low-level voltage signal.
- the voltage V ss of the second power signal ELVSS is generally a ground voltage or a negative value.
- the above-mentioned voltages need to be designed and determined according to the actual application environment, which is not limited here.
- the driving circuit 10 may include: a driving transistor M0, a third transistor M3, a fourth transistor M4, a first capacitor C1, and a second capacitor C2; wherein,
- the gate G of the driving transistor M0 is coupled to the first end of the first capacitor C1, the first electrode D of the driving transistor M0 is configured to receive the first power signal ELVDD, and the second electrode S of the driving transistor M0 is connected to the light emitting device L First electrode coupling;
- the gate of the third transistor M3 is coupled to the scan signal terminal GA, the first electrode of the third transistor M3 is coupled to the data signal terminal DA, and the second electrode of the third transistor M3 is coupled to the gate G of the driving transistor M0;
- the gate of the fourth transistor M4 is coupled to the reset signal terminal RES, the first pole of the fourth transistor M4 is coupled to the initialization signal terminal VINIT, and the second pole of the fourth transistor M4 is coupled to the first electrode of the light emitting device L;
- the second end of the first capacitor C1 is coupled to the first electrode of the light emitting device L;
- the first terminal of the second capacitor C2 is configured to receive the first power signal ELVDD, and the second terminal of the second capacitor C2 is coupled to the first electrode of the light emitting device L.
- the driving transistor M0 can be configured as an N-type transistor; wherein, the first electrode S of the driving transistor M0 is used as its drain, and the second electrode of the driving transistor M0 is D is its source. And the current when the driving transistor M0 is in a saturated state flows from the drain of the driving transistor M0 to its source. Moreover, the light-emitting device L generally realizes light emission under the action of the current when the driving transistor M0 is in a saturated state.
- the driving transistor is an N-type transistor as an example for description.
- the design principle is the same as that of the present disclosure and also falls within the protection scope of the present disclosure.
- transistors that use Low Temperature Poly-Silicon (LTPS) materials as the active layer have high mobility, can be made thinner and smaller, and have lower power consumption.
- the active layer of the drive transistor The material may include low temperature polysilicon material.
- the third transistor M3 when the third transistor M3 is in the on state under the control of the signal of the scan signal terminal GA, it can provide the signal of the data signal terminal DA to the gate of the driving transistor M0.
- the fourth transistor M4 when the fourth transistor M4 is in the on state under the control of the signal of the reset signal terminal RES, it can provide the signal of the initialization signal terminal VINIT to the first electrode of the light emitting device L.
- the first capacitor C1 can store the signals input to the first terminal and the second terminal thereof, and when the second terminal of the first capacitor C1 is in a floating state, it can couple the signal input to the gate of the driving transistor to the first capacitor The second end of C1.
- the second capacitor C2 can store the signals input to the first terminal and the second terminal thereof, and divide the voltage of the signal coupled to the second terminal of the first capacitor C1 by the first capacitor C1.
- the leakage current of transistors using metal oxide semiconductor materials as the active layer is relatively small.
- the third transistor M3 has The material of the source layer may be set as a metal oxide semiconductor material.
- it may be indium gallium zinc oxide (IGZO).
- the material of the active layer can also be other materials that can realize the solution of the present disclosure, which is not limited herein.
- the material of the active layer of the fourth transistor M4 may be set to a metal oxide semiconductor material.
- a metal oxide semiconductor material may be indium gallium zinc oxide (IGZO).
- IGZO indium gallium zinc oxide
- the material of the active layer can also be other materials that can realize the solution of the present disclosure, which is not limited herein.
- the light emission control circuit 20 may include: a first transistor M1 and a second transistor M2; wherein,
- the gate of the first transistor M1 is configured to receive the first light emission control signal EM1, the first electrode of the first transistor M1 is configured to receive the first power signal ELVDD, and the second electrode of the first transistor M1 is connected to the first light emitting device L Two-electrode coupling;
- the gate of the second transistor M2 is configured to receive the second light emission control signal EM2, the first electrode of the second transistor M2 is configured to receive the second power signal ELVSS, and the second electrode of the second transistor M2 is connected to the first electrode of the light emitting device L. Two-electrode coupling.
- the first power signal ELVDD can be provided to the second electrode of the light emitting device L to The light emitting device L is made not to emit light.
- the second power signal ELVSS can be provided to the second electrode of the light emitting device L, so that the light emitting device L receives the low level voltage and is normal Glow.
- the first emission control signal EM1 is different from the second emission control signal EM2, and the transistor types of the first transistor M1 and the second transistor M2 are the same.
- the first transistor M1 and the second transistor M2 are both N-type transistors, and the first emission control signal EM1 and the second emission control signal EM2 are as shown in FIG. 3.
- the first to fourth transistors M1 to M4 may all be N-type transistors.
- the material of the active layer of the first transistor M1 may include low-temperature polysilicon material or metal oxide semiconductor material, which is not limited herein.
- the material of the active layer of the second transistor M2 may include a low-temperature polysilicon material or a metal oxide semiconductor material, which is not limited herein.
- transistors may be bottom-gate transistors or top-gate transistors, which need to be designed and determined according to the actual application environment, which is not limited here.
- the first electrode of the above-mentioned transistor can be used as its source and the second electrode can be used as its drain; alternatively, the first electrode can be used as its drain and the second electrode can be used as its source, and no specific distinction is made here.
- the N-type transistor is turned on under the action of a high-level signal, and turned off under the action of a low-level signal.
- the P-type transistor is turned off under the action of a high-level signal, and turned on under the action of a low-level signal.
- the foregoing is only an example to illustrate the specific structure of the pixel compensation circuit provided by the embodiment of the present disclosure.
- the specific structure of the above-mentioned driving circuit and light-emitting control circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may also be technical in the art. Other structures known to the personnel are not limited here.
- 1 represents a high-level signal
- 0 represents a low-level signal.
- 1 and 0 are logic levels, which are only used to better explain the specific working process of the embodiments of the present disclosure. It is not the voltage applied to the gate of each transistor during implementation.
- One frame time may include a non-light emitting phase T10 and a light emitting phase T20.
- the non-light emitting phase T10 may include: a reset phase T11, a threshold compensation phase T12, and a data writing phase T13.
- the third transistor M3 is turned on to provide the reference voltage signal input from the data signal terminal DA to the gate G of the driving transistor M0, so that the voltage of the gate G of the driving transistor M0 is the reference voltage signal The voltage V ref .
- the fourth transistor M4 is turned on to provide the initialization signal input by the initialization signal terminal VINIT to the first electrode of the light emitting device L, so that the voltage of the first electrode of the light emitting device L is the voltage V init of the initialization signal . Therefore, the voltage difference across the first capacitor C1 is V ref -V init .
- the voltage difference across the second capacitor C2 is V dd -V init .
- V ref and V init can be made to satisfy the relationship: V ref >V init +V th ; where V th represents the threshold voltage of the driving transistor M0.
- V init and V dd may satisfy the relationship: V init ⁇ V dd .
- the driving transistor M0 can be turned on, thereby generating a current flowing from the first pole D to the second pole S, so as to charge the first capacitor C1 and the second capacitor C2 through the current, In this way, the voltage of the second terminal of the first capacitor C1 and the second terminal of the second capacitor C2 (that is, the voltage at the NB point) gradually increases.
- the driving transistor M0 is turned off. At this time, the voltage difference across the first capacitor C1 is V th .
- the driving transistor M0 generates a driving current I L under the control of the voltage V NB2 of its second pole S and the voltage V DA of its gate G, among them, ⁇ n represents the mobility of the driving transistor M0, and C ox is the capacitance of the gate oxide layer per unit area, To drive the width-to-length ratio of the transistor M0, these values are relatively stable in the same structure and can be regarded as constants. I L which can drive the light emitting element L emits light by a driving current.
- the threshold voltage V th of the driving transistor will drift. This will cause the driving current flowing through each light-emitting device to be affected by the V th drift and change resulting in uneven display brightness. Affect the display effect of the entire image.
- the driving current IL is only related to the voltage V data of the data signal input from the data signal terminal DA and the voltage V ref of the reference voltage signal, and has nothing to do with the threshold voltage V th of the driving transistor M0 It can solve the influence of the drift of the threshold voltage V th caused by the process of the driving transistor M0 and the long-term operation on the driving current I L , so that the driving current I L of the light emitting device L is kept stable, thereby ensuring the light emitting device L normal work.
- a buffer stage may be provided between the threshold compensation stage T12 and the data writing stage T13, so that after the voltage difference between the two ends of the first capacitor C1 is stabilized, V data can be written, thereby further improving circuit stability.
- the present disclosure can prevent the light emitting device from emitting light during the threshold compensation stage and the data writing stage through a simple structure of the pixel compensation circuit, thereby avoiding image retention.
- the embodiments of the present disclosure provide other pixel compensation circuits, as shown in FIG. 4, which are modified from the implementation shown in FIG. 2. The following only describes the differences between this embodiment and the embodiment of the pixel compensation circuit shown in FIG. 2, and the similarities are not repeated here.
- the first light emission control signal EM1 is different from the second light emission control signal EM2, and the transistor types of the first transistor M1 and the second transistor M2 are the same.
- the first transistor M1 and the second transistor M2 are both P-type transistors
- the first light emission control signal EM1 and the second light emission control signal EM2 are as shown in FIG. 5.
- the first to fourth transistors M1 to M4 may be all P-type transistors, which is not limited herein.
- 1 represents a high-level signal
- 0 represents a low-level signal.
- 1 and 0 are logic levels, which are only used to better explain the specific working process of the embodiments of the present disclosure. It is not the voltage applied to the gate of each transistor during implementation.
- One frame time may include a non-light emitting phase T10 and a light emitting phase T20.
- the non-light emitting phase T10 may include: a reset phase T11, a threshold compensation phase T12, and a data writing phase T13.
- the specific process at this stage refer to the light-emitting stage T20 in the embodiment of the pixel compensation circuit shown in FIG. 2, and the details are not repeated here.
- the embodiments of the present disclosure provide further pixel compensation circuits, as shown in FIG. 6, which are modified from the implementation shown in FIG. 2. The following only describes the differences between this embodiment and the embodiment of the pixel compensation circuit shown in FIG. 2, and the similarities are not repeated here.
- the first light emission control signal and the second light emission control signal are the same signal, and the transistor types of the first transistor M1 and the second transistor M2 are different.
- the first transistor M1 is an N-type transistor
- the second transistor M2 is a P-type transistor
- the gate of the first transistor M1 and the gate of the second transistor M2 both receive the first light emission control signal EM1
- the gate of the first transistor M1 and the second transistor M2 are simultaneously controlled by the first light emission control signal EM1.
- the first light emission control signal EM1 is shown in FIG. 7.
- 1 represents a high-level signal
- 0 represents a low-level signal.
- 1 and 0 are logic levels, which are only used to better explain the specific working process of the embodiments of the present disclosure. It is not the voltage applied to the gate of each transistor during implementation.
- One frame time may include a non-light emitting phase T10 and a light emitting phase T20.
- the non-light emitting phase T10 may include: a reset phase T11, a threshold compensation phase T12, and a data writing phase T13.
- the embodiments of the present disclosure provide further pixel compensation circuits, as shown in FIG. 8, which are modified from the embodiment shown in FIG. 2. The following only describes the differences between this embodiment and the embodiment of the pixel compensation circuit shown in FIG. 2, and the similarities are not repeated here.
- the first light-emitting control signal and the second light-emitting control signal are the same signal, and the transistor types of the first transistor M1 and the second transistor M2 are different.
- the first transistor M1 is a P-type transistor
- the second transistor M2 is an N-type transistor
- the gate of the first transistor M1 and the gate of the second transistor M2 both receive the first light emission control signal EM1
- the gate of the first transistor M1 and the second transistor M2 are simultaneously controlled by the first light emission control signal EM1.
- the first light emission control signal EM1 is shown in FIG. 9.
- 1 represents a high-level signal
- 0 represents a low-level signal.
- 1 and 0 are logic levels, which are only used to better explain the specific working process of the embodiments of the present disclosure. It is not the voltage applied to the gate of each transistor during implementation.
- One frame time may include a non-light emitting phase T10 and a light emitting phase T20.
- the non-light emitting phase T10 may include: a reset phase T11, a threshold compensation phase T12, and a data writing phase T13.
- an embodiment of the present disclosure further provides a display panel, as shown in FIG. 10, which may include: a base substrate 100 and any of the aforementioned pixel compensation circuits provided by the embodiment of the present disclosure.
- the base substrate 100 includes a display area AA and a non-display area surrounding the display area AA.
- the driving circuit 10 and the light emitting device L in each pixel compensation circuit are located in the display area AA of the base substrate 100.
- the display panel provided by the embodiment of the present disclosure adopts the above-mentioned pixel compensation circuit, so that the display panel does not emit light during the threshold compensation stage and the data writing stage, thereby avoiding image retention.
- the display area of a display panel may include multiple pixel units, and each pixel unit may include multiple sub-pixels.
- the pixel unit may include red sub-pixels, green sub-pixels, and blue sub-pixels.
- the display panel can adopt the principle of mixing red, green and blue to display images.
- the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, which is not limited here.
- each sub-pixel upx is provided with a driving circuit 10 and a light-emitting device L, so that the display area is changed little, or even the display area is not changed.
- all pixel compensation circuits can share one light emission control circuit 20. That is, it is equivalent to only one light emitting control circuit 20 is provided in the display panel, and the second electrodes of all light emitting devices L in the display area AA are electrically connected to the same light emitting control circuit 20.
- the light-emitting control circuit 20, the light-emitting device L and the driving circuit 10 in a sub-pixel upx can form a pixel compensation circuit.
- the light emitting control circuit 20, the light emitting device L and the driving circuit 10 in another sub-pixel upx may constitute another pixel compensation circuit.
- the rest can be deduced by analogy, so I won’t repeat them here. This can reduce the arrangement of transistors and signal lines, which is beneficial to pixel wiring and improves resolution.
- the display panel may further include: a plurality of gate lines 310, a plurality of data lines 320 and a reset signal line 330.
- the sub-pixels in a row of pixel units correspond to one gate line 310
- one column of sub-pixels corresponds to one data line 320.
- the gate line 310 is electrically connected to the gate of the third transistor M3 of the driving circuit 10 in the corresponding pixel unit, so as to transmit signals of corresponding timing to the scan signal terminal GA through the gate line 310.
- the data line 320 is electrically connected to the first pole of the third transistor M3 of the driving circuit 10 in the corresponding pixel unit to transmit a corresponding signal to the data signal terminal DA through the data line 320.
- the gate of the fourth transistor M4 of the driving circuit 10 is electrically connected to the reset signal line 330.
- the gates of the fourth transistors M4 of all the driving circuits 10 in the display area AA are electrically connected to the same reset signal line 330, that is, the gates of all the fourth transistors M4 in the display area AA are electrically connected to the reset signal terminal RES.
- the signal is the same.
- the display area may also include: a first power signal line and an initialization signal line.
- the first power signal line has a grid structure
- the first pole D of the driving transistor M0 in each driving circuit 10 is electrically connected to the first power signal line to transmit the first power through the first power signal line.
- Signal ELVDD The first pole of the fourth transistor M4 in each driving circuit 10 is electrically connected to the initialization signal line to transmit the initialization signal of the voltage V init through the initialization signal line.
- the base substrate has a non-display area surrounding the display area.
- the non-display area BB is arranged around the display area AA, and the light-emitting control circuit 20 can be located on the substrate.
- the non-display area is an area excluding the display area AA of the base substrate 100. In this way, the transistors in the light-emitting control circuit 20 and the transistors in the display area AA can be prepared at the same time, thereby reducing the difficulty of process preparation.
- the display panel may further include at least one of a driving chip, a flexible printed circuit (FPC) and a printed circuit board (PCB).
- the driver chip may be a driver integrated circuit (Integrated Circuit, IC).
- the light emission control circuit may be located in at least one of a driving chip, a flexible circuit board, and a printed circuit board.
- the light emission control circuit 20 may be provided in the printed circuit board 200.
- FIG. 11 only illustrates the case where the light emission control circuit 20 is provided in the printed circuit board 200, and the light emission control circuit 20 is provided in the driving chip and the light emission control circuit 20 is provided in the flexible circuit board. You can also refer to the setting method shown in FIG. 11, which will not be described in detail here.
- the display panel may further include: a gate driving circuit 410 and a gate control circuit 420 corresponding to each gate line 310 in a one-to-one manner.
- each gate line 310 is respectively coupled to a signal output terminal OUT of the gate driving circuit 410 through a corresponding gate control circuit 420.
- the gate control circuit 420 is configured to conduct the fixed voltage signal terminal VGH with the corresponding gate line 310 in response to the conduction control signal SEL having the first level; and in response to the conduction control signal having the second level SEL, connects the connected signal output terminal OUT with the corresponding gate line 310.
- the first level may be a high level
- the second level may be a low level.
- the first level may be a low level
- the second level may be a high level, which is not limited here.
- the gate driving circuit 410 can use the input frame trigger signal STV and clock signals CLK_1 ⁇ CLK_M (M is the total number of clock signals, and the value of M can be designed according to the actual application environment.
- the scan signal is output to the gate line row by row. For example, as shown in FIG. 13, taking only the gate lines 310 corresponding to the pixel units in the first row to the third row as an example, the gate driving circuit 410 may output the scan signal ga_1 to the gate lines 310 corresponding to the pixel units in the first row.
- the scan signal ga_2 is output to the gate line 310 corresponding to the pixel unit of the second row
- the scan signal ga_3 is output to the gate line 310 corresponding to the pixel unit of the third row
- the rest is deduced by analogy, which will not be repeated here.
- the structure and working principle of the gate driving circuit and the gate control circuit may be basically the same as those in the related art, and will not be repeated here.
- the conduction control signals received by each gate control circuit can be the same signal. As shown in Fig. 12, in this way, all the gate control circuits 420 can be electrically connected to the same conduction control signal line 340 so as to transmit the conduction control signal SEL to each gate control circuit 420 through the conduction control signal line 340.
- each gate control circuit 420 can be electrically connected to the same conductive fixed voltage signal line 350, so as to transmit a fixed voltage signal to each gate control circuit 420 through the fixed voltage signal line 350 VGH.
- the frame trigger signal STV, clock signals CLK_1 ⁇ CLK_M, fixed voltage signal VGH, conduction control signal SEL, reset signal RE, first power signal ELVDD, initialization signal can be other circuits or drive ICs set on the PCB What is provided is not limited here.
- One frame time may include a non-light emitting phase T10 and a light emitting phase T20.
- the non-light emitting phase T10 may include: a reset phase T11, a threshold compensation phase T12, and a data writing phase T13.
- the signal output terminal OUT of the gate driving circuit 410 is disconnected from the gate line 310, and the fixed voltage signal terminal VGH is connected to each gate line 310, so that the signal on each gate line 310
- the signal is a high level signal.
- the first row of gate lines 310 are transmitted to the signal GA_1 of the scan signal terminal GA
- the second row of gate lines 310 are transmitted to the signal GA_2 of the scan signal terminal GA
- the third row of gate lines 310 are transmitted to the scan signal terminal GA.
- all the third transistors M3 in the display area AA can be turned on at the same time to provide the reference voltage signal input from the data signal terminal DA to the gate G of the driving transistor M0, so that each The voltage of the gate G of the driving transistor M0 is the voltage Vref of the reference voltage signal.
- all the fourth transistors M4 in the display area AA are turned on to provide the initialization signal input from the initialization signal terminal VINIT to the first electrode of the light emitting device L, so that the first electrode of each light emitting device L The voltage is the voltage V init of the initialization signal.
- each third transistor M3 in the display area AA can be turned on at the same time to provide the reference voltage signal input from the data signal terminal DA to the gate G of the driving transistor M0, so that each The voltage of the gate G of the driving transistor M0 is the voltage Vref of the reference voltage signal.
- each first capacitor C1 can maintain the voltage difference between its two ends at V ref -V init . Since V ref >V init +V th , each driving transistor M0 can be turned on, thereby generating a current flowing from the first pole D to the second pole S, so that the current flows through the first capacitor C1 and the second capacitor C2.
- each driving transistor M0 is turned off.
- the third transistor M3 in each sub-pixel in the first row is turned on to provide the data signal input from the data signal terminal DA to the gate G of the driving transistor M0, and to connect the first capacitor C1 And the second capacitor C2 is charged.
- the voltage of the gate G of the driving transistor M0 is the voltage of the data signal V DA
- the voltage of the point NB is V NB2 .
- the third transistor M3 in each sub-pixel in the second row is turned on to provide the data signal input from the data signal terminal DA to the gate G of the driving transistor M0, and to connect the first capacitor C1 and The second capacitor C2 is charged.
- the voltage of the gate G of the driving transistor M0 is the voltage of the data signal V DA
- the voltage of the point NB is V NB2 .
- the third transistor M3 in each sub-pixel in the third row is turned on to provide the data signal input from the data signal terminal DA to the gate G of the driving transistor M0, and to connect the first capacitor C1 and The second capacitor C2 is charged.
- the voltage of the gate G of the driving transistor M0 is the voltage of the data signal V DA
- the voltage of the point NB is V NB2 .
- the turned-on second transistor M2 provides the second power signal ELVSS to the second electrode of each light emitting device L so that the voltage of the second electrode of each light emitting device L is V ss .
- Each driving transistor M0 generates a driving current I L under the control of the voltage V NB2 of its second pole S and the voltage V DA of its gate G, Drive current I L to drive the light emitting element L emits light.
- the display panel provided by the embodiment of the present disclosure controls the display panel to be in the non-display stage T10 through the first transistor M1, and controls the display panel to be in the display stage T20 through the second transistor M2, so that simple pixel compensation can be used.
- the structure of the circuit is such that the display panel is completely in the non-display stage, which can avoid the afterimage in the non-display stage and improve the display effect.
- V ref can be written to the gate G of each driving transistor M0 at the same time.
- V init can be written to the second electrode S of each driving transistor M0 at the same time, and the first electrode of the light emitting device L can be reset at the same time. This can reduce the number of grid lines.
- threshold compensation is generally performed by writing V th row by row, so that the time for compensating V th is only the time for one row of pixels to turn on, which results in a shorter time for compensating V th and a lower charging rate.
- each third transistor M3 in the display panel in the threshold compensation stage T12, is turned on at the same time to write the V th of each driving transistor M0 into its gate G at the same time.
- a data signal is written to each drive transistor M0 row by row.
- the time for writing V th can be made long enough, and the charging rate of writing V th can be increased to solve the problem of insufficient V th writing at a high refresh rate.
- only the data line can be used to transmit both the reference voltage signal and the data signal, thereby reducing the number of signal lines.
- the maintenance duration t 13 of the data writing phase T13 can satisfy: t 13 ⁇ t F -(t 11 +t 12 +t 20 ); where t F represents the maintenance duration of one frame time, and t 11 represents one frame time when the duration T11 of the reset phase is maintained, t 12 to maintain the representative threshold compensation stage in a longer time T12, t 20 representative of the emission phase duration within a time period T20 is maintained.
- the sustaining time length of a row of pixel unit scanning is t 13 /K; where K represents the total number of gate lines.
- t 13 can be k times t 13 /K, where k can be a positive integer, for example, k is a value from 1 to 50.
- the brightness of the light-emitting device can also be set by t 20 /t F.
- the specific values of K and the above-mentioned maintenance duration can be designed and determined according to the actual application environment, and are not limited here.
- FIGS. 15 and 16 are modified from the embodiment shown in FIG. 10. The following only describes the differences between this embodiment and the embodiment of the display panel shown in FIG. 10, and the similarities are not repeated here.
- each sub-display area may include multiple pixel units.
- each sub-display area may also include only one sub-pixel.
- the specific implementation of the sub-display area can be designed and determined according to the actual application environment, which is not limited here.
- each sub-display area aa_y corresponds to one light-emitting control circuit 20 one by one
- the light-emitting control circuit 20 can be located on the base substrate 100 to correspond to In the sub-display area aa_y.
- the light emitting control circuit can be closer to the corresponding light emitting device L.
- the light emission control circuit 20 may be located in the non-display area.
- the light emission control circuit 20 is located in the non-display area of the base substrate 100 surrounding the display area AA.
- the light emission control circuit 20 is located in at least one of a driving chip, a flexible circuit board and a printed circuit board.
- this can be designed and determined according to the actual application environment, which is not limited here.
- each sub-display area can be extended along a first direction, and each sub-display area can be arranged along a second direction; wherein the first direction crosses the second direction.
- the first direction may be the row direction of the pixel unit
- the second direction may be the column direction of the pixel unit.
- Each sub-display area aa_y extends along the row direction of the pixel unit, and each sub-display area aa_y Arrange along the column direction of the pixel unit.
- the first direction can also be the column direction of the pixel unit, and the second direction is the row direction of the pixel unit.
- Each sub-display area extends along the column direction of the pixel unit, and each sub-display area is arranged along the row direction of the pixel unit.
- this can be designed and determined according to the actual application environment, which is not limited here.
- the sub-display areas aa_y may also be distributed in a matrix arrangement.
- one frame time includes:
- At least part of the light-emitting control circuit provides a first power signal to the second electrode of the light-emitting device in response to the first light-emitting control signal.
- all the light emitting control circuits can be made to respond to the first light emitting control signal to provide the first power signal to the second electrode of the light emitting device.
- part of the light emission control circuit can also be made to respond to the first light emission control signal to provide the first power signal to the second electrode of the light emitting device.
- this can be designed and determined according to the actual application environment, which is not limited here.
- the light-emitting control circuit responds to the second light-emitting control signal to provide a second power signal to the second electrode of the light-emitting device; the driving circuit generates a driving current input to the first electrode of the light-emitting device to drive the light-emitting device Glow.
- all the light-emitting control circuits can be made to respond to the second light-emitting control signal to provide the second power signal to the second electrode of the light-emitting device; all the driving circuits generate a driving current input to the first electrode of the light-emitting device to drive the light-emitting device Glow.
- the light-emitting control circuit responds to the second light-emitting control signal to provide the second power signal to the second electrode of the light-emitting device; the driving circuit corresponding to the light-emitting control circuit generates input to the first electrode of the light-emitting device Drive the current to drive the light-emitting device to emit light.
- this can be designed and determined according to the actual application environment, which is not limited here.
- the non-luminous phase may include:
- all third transistors are turned on at the same time in response to the signal at the scan signal terminal, and the reference voltage signal at the data signal terminal is provided to the gate of the driving transistor; all fourth transistors are turned on at the same time in response to the signal at the reset signal terminal, and will initialize The signal is provided to the first electrode of the light emitting device;
- all third transistors are turned on at the same time in response to the signal from the scan signal terminal, and the reference voltage signal of the data signal terminal is provided to the gate of the driving transistor; all driving transistors are turned on at the same time, and the threshold voltage of the driving transistor is written into the driving transistor The second pole
- the third transistor is turned on line by line in response to the signal from the scan signal terminal, and provides the data signal at the data signal terminal to the gate of the driving transistor; and writes the voltage of the data signal through the first capacitor and the second capacitor Drive the second pole of the transistor.
- the driving principle and specific implementation of the driving method of the display panel are the same as the principles and implementations of the display panel of the foregoing embodiment. Therefore, the driving method of the display panel can be implemented with reference to the specific implementation of the display panel in the foregoing embodiment. , I won’t repeat it here.
- embodiments of the present disclosure also provide a display device, including the above-mentioned display panel provided by the embodiments of the present disclosure.
- the problem-solving principle of the display device is similar to that of the aforementioned display panel. Therefore, the implementation of the display device can refer to the implementation of the aforementioned display panel, and the repetition is not repeated here.
- the display device provided by the embodiment of the present disclosure may be a mobile phone as shown in FIG. 18.
- the display device provided by the embodiment of the present disclosure may also be any product or component with display function, such as a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
- the other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
- the light emitting control circuit responds to the first light emitting control signal to provide the first power signal to the second electrode of the light emitting device to Control the light emitting device not to emit light.
- the driving current input to the first electrode of the light-emitting device is generated by the driving circuit, and the second power signal is provided to the second electrode of the light-emitting device through the light-emitting control circuit in response to the second light-emitting control signal, so that the driving current Drive the light emitting device to emit light. Therefore, a simple structure can be used to control whether the light-emitting device emits light, thereby reducing process difficulty, reducing production cost, reducing the area occupied by the pixel compensation circuit, and helping the display panel to achieve high resolution.
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Abstract
一种像素补偿电路、显示面板、驱动方法及显示装置。像素补偿电路包括:发光器件(L);驱动电路(10),产生向发光器件(L)的第一电极输入的驱动电流;发光控制电路(20),响应于第一发光控制信号(EM1)将第一电源信号(ELVDD)提供给发光器件(L)的第二电极,以及响应于第二发光控制信号(EM2)将第二电源信号(ELVSS)提供给发光器件(L)的第二电极;第一电源信号(ELVDD)与第二电源信号(ELVSS)的电平相反。能够降低像素补偿电路占用面积,利于显示面板实现高分辨率。
Description
本公开涉及显示技术领域,特别涉及像素补偿电路、显示面板、驱动方法及显示装置。
有机发光二极管(Organic Light Emitting Diode,OLED)显示面板具有低能耗、自发光等优点,是平板显示面板研究领域的热点之一。由于OLED属于电流驱动,需要稳定的电流来控制其发光。一般OLED显示面板采用像素补偿电路产生驱动电流以驱动OLED发光。
发明内容
本公开实施例提供的像素补偿电路,其中,包括:
发光器件;
驱动电路,被配置为产生向所述发光器件的第一电极输入的驱动电流;
发光控制电路,被配置为响应于第一发光控制信号将第一电源信号提供给所述发光器件的第二电极,以及响应于第二发光控制信号将第二电源信号提供给所述发光器件的第二电极;其中,所述第一电源信号与所述第二电源信号的电平相反。
可选地,在本公开实施例中,所述驱动电路和所述发光器件被配置在显示面板的显示区,所述发光控制电路被配置在所述显示面板的非显示区。
可选地,在本公开实施例中,所述发光控制电路包括:第一晶体管和第二晶体管;
所述第一晶体管的栅极被配置为接收所述第一发光控制信号,所述第一晶体管的第一极被配置为接收所述第一电源信号,所述第一晶体管的第二极与所述发光器件的第二电极耦接;
所述第二晶体管的栅极被配置为接收所述第二发光控制信号,所述第二晶体管的第一极被配置为接收所述第二电源信号,所述第二晶体管的第二极与所述发光器件的第二电极耦接。
可选地,在本公开实施例中,所述第一发光控制信号与所述第二发光控制信号为同一信号,所述第一晶体管和所述第二晶体管的晶体管类型不同。
可选地,在本公开实施例中,所述第一发光控制信号与所述第二发光控制信号不同,所述第一晶体管和所述第二晶体管的晶体管类型相同。
可选地,在本公开实施例中,所述驱动电路包括:驱动晶体管、第三晶体管、第四晶体管、第一电容以及第二电容;
所述驱动晶体管的栅极与所述第一电容的第一端耦接,所述驱动晶体管的第一极被配置为接收所述第一电源信号,所述驱动晶体管的第二极与所述发光器件的第一电极耦接;
所述第三晶体管的栅极与扫描信号端耦接,所述第三晶体管的第一极与数据信号端耦接,所述第三晶体管的第二极与所述驱动晶体管的栅极耦接;
所述第四晶体管的栅极与复位信号端耦接,所述第四晶体管的第一极与初始化信号端耦接,所述第四晶体管的第二极与所述发光器件的第一电极耦接;
所述第一电容的第二端与所述发光器件的第一电极耦接;
所述第二电容的第一端被配置为接收所述第一电源信号,所述第二电容的第二端与所述发光器件的第一电极耦接。
相应地,本公开实施例还提供了显示面板,其中,包括:衬底基板和多个上述像素补偿电路;其中,所述衬底基板包括显示区和围绕所述显示区的非显示区;
各所述像素补偿电路中的驱动电路和发光器件位于所述衬底基板的显示区。
可选地,在本公开实施例中,所述发光控制电路位于所述非显示区内。
可选地,在本公开实施例中,所述显示面板还包括:驱动芯片、柔性电 路板以及印刷电路板中至少一种;
所述发光控制电路位于所述驱动芯片、柔性电路板以及印刷电路板中至少一种内。
可选地,在本公开实施例中,所述显示区包括:多个子显示区;每一个所述子显示区中的所有发光器件耦接同一个发光控制电路。
可选地,在本公开实施例中,每一个所述子显示区一一对应一个所述发光控制电路,所述发光控制电路位于所述衬底基板上对应的所述子显示区内。
可选地,在本公开实施例中,各所述子显示区沿第一方向延伸,且各所述子显示区沿第二方向排列;所述第一方向与所述第二方向交叉。
可选地,在本公开实施例中,各所述子显示区呈矩阵排列方式分布。
可选地,在本公开实施例中,所有所述像素补偿电路共用一个发光控制电路。
可选地,在本公开实施例中,所述显示面板还包括:多条栅线、栅极驱动电路以及与各所述栅线一一对应的选通控制电路;
各所述栅线分别通过对应的选通控制电路与所述栅极驱动电路的一个信号输出端耦接;
所述选通控制电路被配置为响应于具有第一电平的导通控制信号,将固定电压信号端与对应的所述栅线导通;以及响应于具有第二电平的导通控制信号,将连接的所述信号输出端与对应的所述栅线导通。
可选地,在本公开实施例中,各所述选通控制电路接收的导通控制信号为同一信号。
相应地,本公开实施例还提供了显示装置,其中,包括上述显示面板。
相应地,本公开实施例还提供了上述显示面板的驱动方法,其中,一帧时间包括:
非发光阶段,至少部分所述发光控制电路响应于第一发光控制信号,将第一电源信号提供给所述发光器件的第二电极;
发光阶段,至少部分所述发光控制电路响应于第二发光控制信号,将第 二电源信号提供给发光器件的第二电极;所有所述驱动电路产生向所述发光器件的第一电极输入的驱动电流,驱动所述发光器件发光。
可选地,在本公开实施例中,所述非发光阶段包括:
复位阶段,所有第三晶体管响应于扫描信号端的信号同时导通,将数据信号端的参考电压信号提供给驱动晶体管的栅极;所有第四晶体管响应于复位信号端的信号同时导通,将初始化信号端的信号提供给所述发光器件的第一电极;
阈值补偿阶段,所有所述第三晶体管响应于所述扫描信号端的信号同时导通,将所述数据信号端的所述参考电压信号提供给所述驱动晶体管的栅极;所有所述驱动晶体管同时导通,将所述驱动晶体管的阈值电压写入所述驱动晶体管的第二极;
数据写入阶段,所述第三晶体管响应于所述扫描信号端的信号逐行导通,将所述数据信号端的数据信号提供给所述驱动晶体管的栅极;并通过所述第一电容和所述第二电容,将所述数据信号的电压写入所述驱动晶体管的第二极。
图1为本公开实施例提供的像素补偿电路的结构示意图;
图2为本公开实施例提供的像素补偿电路的具体结构示意图之一;
图3为本公开实施例提供的信号时序图之一;
图4为本公开实施例提供的像素补偿电路的具体结构示意图之二;
图5为本公开实施例提供的信号时序图之二;
图6为本公开实施例提供的像素补偿电路的具体结构示意图之三;
图7为本公开实施例提供的信号时序图之三;
图8为本公开实施例提供的像素补偿电路的具体结构示意图之四;
图9为本公开实施例提供的信号时序图之四;
图10为本公开实施例提供的显示面板的结构示意图之一;
图11为本公开实施例提供的显示面板的结构示意图之二;
图12为本公开实施例提供的显示面板的结构示意图之三;
图13为本公开实施例提供的扫描信号的示意图;
图14为本公开实施例提供的信号时序图之五;
图15为本公开实施例提供的显示面板的结构示意图之四;
图16为本公开实施例提供的显示面板的结构示意图之五;
图17为本公开实施例提供的显示面板的驱动方法的流程图;
图18为本公开实施例提供的显示装置的结构示意图。
为了使本公开的目的,技术方案和优点更加清楚,下面结合附图,对本公开实施例提供的像素补偿电路、显示面板,驱动方法及显示装置的具体实施方式进行详细地说明。应当理解,下面所描述的优选实施例仅被配置为说明和解释本公开,并不被配置为限定本公开。并且在不冲突的情况下,本公开中的实施例及实施例中的特征可以相互组合。需要注意的是,附图中各图形的尺寸和形状不反映真实比例,目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
一般通过像素补偿电路中的驱动晶体管产生驱动电流,并将驱动电流提供给OLED,以驱动OLED发光。然而,由于工艺制程和器件老化等原因,导致驱动晶体管的阈值电压V
th存在不均匀性,这样导致驱动电流会发生变化,使得显示亮度不均,从而影响整个图像的显示效果。为了提高驱动电流的稳定性,可以采用能够补偿阈值电压V
th的像素补偿电路产生驱动电流。然而,为了避免像素补偿电路在进行阈值电压V
th补偿时对显示的影响,因此在一帧时间内设置非发光阶段,以在非发光阶段中进行补偿阈值电压V
th。然而,为了实现非发光阶段,像素补偿电路需要设置个数较多的晶体管。这样将会导致工艺难度较大,生产成本增加,以及导致像素补偿电路占用较大面积,从而不利于显示面板实现高分辨率。
有鉴于此,本公开实施例提供了采用简单结构设置的像素补偿电路,可以降低工艺难度,降低生产成本,以及降低像素补偿电路占用面积,从而有利于显示面板实现高分辨率。
本公开实施例提供的一些像素补偿电路,如图1所示,可以包括:发光器件L、驱动电路10、以及发光控制电路20。其中,驱动电路10被配置为产生向发光器件L的第一电极输入的驱动电流。发光控制电路20被配置为响应于第一发光控制信号EM1将第一电源信号ELVDD提供给发光器件L的第二电极,以及响应于第二发光控制信号EM2将第二电源信号ELVSS提供给发光器件L的第二电极;其中,第一电源信号ELVDD与第二电源信号ELVSS的电平相反。
本公开实施例提供的像素补偿电路,在非发光阶段,通过发光控制电路响应于第一发光控制信号将第一电源信号提供给发光器件的第二电极,以控制发光器件不发光。在发光阶段,通过驱动电路产生向发光器件的第一电极输入的驱动电流,并通过发光控制电路响应于第二发光控制信号将第二电源信号提供给发光器件的第二电极,以使驱动电流驱动发光器件发光。从而可以采用简单的结构控制发光器件是否发光,进而可以降低工艺难度,降低生产成本,降低像素补偿电路占用面积,以及有利于显示面板实现高分辨率。
一般发光器件具有开启电压,在发光器件的第一电极和第二电极之间的电压差大于或等于开启电压时进行发光。在具体实施时,发光器件的第一电极与驱动电路电连接,发光器件的第二电极与发光控制电路电连接。在本公开实施例中,发光器件可以包括:电致发光二极管。其中,电致发光二极管的阳极作为发光器件的第一电极,电致发光二极管的阴极作为发光器件的第二电极。具体地,电致发光二极管可以包括:OLED,或量子点发光二极管(Quantum Dot Light Emitting Diodes,QLED)。
在具体实施时,在本公开实施例中,驱动电路和发光器件可以被配置在显示面板的显示区,以使显示面板实现画面显示。
在具体实施时,在本公开实施例中,发光控制电路可以被配置在显示面 板的非显示区,可以减低占用显示区的空间。其中,发光控制电路可以位于显示面板的衬底基板中围绕显示区设置的非显示区。或者,发光控制电路也可以为显示面板中的驱动芯片、柔性电路板以及印刷电路板中至少一种内。
在具体实施时,在本公开实施例中,第一电源信号ELVDD可以为高电平电压信号,例如第一电源信号ELVDD的电压V
dd一般为正值。第二电源信号ELVSS可以为低电平电压信号,例如第二电源信号ELVSS的电压V
ss一般为接地电压或为负值。在实际应用中,上述各电压需要根据实际应用环境来设计确定,在此不作限定。
在具体实施时,在本公开实施例中,如图2所示,驱动电路10可以包括:驱动晶体管M0、第三晶体管M3、第四晶体管M4、第一电容C1以及第二电容C2;其中,
驱动晶体管M0的栅极G与第一电容C1的第一端耦接,驱动晶体管M0的第一极D被配置为接收第一电源信号ELVDD,驱动晶体管M0的第二极S与发光器件L的第一电极耦接;
第三晶体管M3的栅极与扫描信号端GA耦接,第三晶体管M3的第一极与数据信号端DA耦接,第三晶体管M3的第二极与驱动晶体管M0的栅极G耦接;
第四晶体管M4的栅极与复位信号端RES耦接,第四晶体管M4的第一极与初始化信号端VINIT耦接,第四晶体管M4的第二极与发光器件L的第一电极耦接;
第一电容C1的第二端与发光器件L的第一电极耦接;
第二电容C2的第一端被配置为接收第一电源信号ELVDD,第二电容C2的第二端与发光器件L的第一电极耦接。
在具体实施时,在本公开实施例中,如图2所示,驱动晶体管M0可以设置为N型晶体管;其中,驱动晶体管M0的第一极S作为其漏极,驱动晶体管M0的第二极D作为其源极。并且该驱动晶体管M0处于饱和状态时的电流由驱动晶体管M0的漏极流向其源极。并且,发光器件L一般在驱动晶体 管M0处于饱和状态时的电流的作用下实现发光。当然,在本公开实施例中,仅是以驱动晶体管为N型晶体管为例进行说明的,对于驱动晶体管为P型晶体管的情况,设计原理与本公开相同,也属于本公开保护的范围。
一般采用低温多晶硅(Low Temperature Poly-Silicon,LTPS)材料作为有源层的晶体管的迁移率高且可以做得更薄更小、功耗更低等,在具体实施时,驱动晶体管的有源层的材料可以包括低温多晶硅材料。
在具体实施时,在本公开实施例中,第三晶体管M3在扫描信号端GA的信号的控制下处于导通状态时,可以将数据信号端DA的信号提供给驱动晶体管M0的栅极。第四晶体管M4在复位信号端RES的信号的控制下处于导通状态时,可以将初始化信号端VINIT的信号提供给发光器件L的第一电极。第一电容C1可以将输入其第一端和第二端的信号进行存储,以及在第一电容C1的第二端处于浮接状态时,可以将输入驱动晶体管的栅极的信号耦合到第一电容C1的第二端。第二电容C2可以将输入其第一端和第二端的信号进行存储,并对第一电容C1耦合到第一电容C1的第二端的信号的电压进行分压。
一般采用金属氧化物半导体材料作为有源层的晶体管的漏电流较小,为了降低驱动晶体管M0的栅极G的漏电流,在具体实施时,在本公开实施例中,第三晶体管M3的有源层的材料可以设置为金属氧化物半导体材料。例如可以为铟镓锌氧化物(IGZO)。当然,有源层的材料也可以为能够实现本公开方案的其他材料,在此不做限定。
为了降低第一电容C1的第二端的漏电流,在具体实施时,在本公开实施例中,第四晶体管M4的有源层的材料可以设置为金属氧化物半导体材料。例如可以为铟镓锌氧化物(IGZO)。当然,有源层的材料也可以为能够实现本公开方案的其他材料,在此不做限定。
在具体实施时,在本公开实施例中,如图2所示,发光控制电路20可以包括:第一晶体管M1和第二晶体管M2;其中,
第一晶体管M1的栅极被配置为接收第一发光控制信号EM1,第一晶体管M1的第一极被配置为接收第一电源信号ELVDD,第一晶体管M1的第二 极与发光器件L的第二电极耦接;
第二晶体管M2的栅极被配置为接收第二发光控制信号EM2,第二晶体管M2的第一极被配置为接收第二电源信号ELVSS,第二晶体管M2的第二极与发光器件L的第二电极耦接。
在具体实施时,在本公开实施例中,第一晶体管M1在第一发光控制信号EM1的控制下处于导通状态时,可以将第一电源信号ELVDD提供给发光器件L的第二电极,以使发光器件L不发光。第二晶体管M2在第二发光控制信号EM2的控制下处于导通状态时,可以将第二电源信号ELVSS提供给发光器件L的第二电极,以使发光器件L接收到低电平电压而正常发光。
在具体实施时,在本公开实施例中,如图2所示,第一发光控制信号EM1与第二发光控制信号EM2不同,第一晶体管M1和第二晶体管M2的晶体管类型相同。例如,图2所示,第一晶体管M1和第二晶体管M2均为N型晶体管,则第一发光控制信号EM1与第二发光控制信号EM2如图3所示。
为了简化制备工艺,在具体实施时,在本公开实施例中,如图2所示,第一晶体管至第四晶体管M1~M4可以均为N型晶体管。
在具体实施时,第一晶体管M1的有源层的材料可以包括低温多晶硅材料或金属氧化物半导体材料,在此不作限定。
在具体实施时,第二晶体管M2的有源层的材料可以包括低温多晶硅材料或金属氧化物半导体材料,在此不作限定。
需要说明的是,上述晶体管可以为底栅型晶体管或顶栅型晶体管,这需要根据实际应用环境来设计确定,在此不作限定。
在具体实施时,上述晶体管的第一极可以作为其源极,第二极可以作为其漏极;或者,第一极作为其漏极,第二极作为其源极,在此不作具体区分。
进一步的,在具体实施时,N型晶体管在高电平信号作用下导通,在低电平信号作用下截止。P型晶体管在高电平信号作用下截止,在低电平信号作用下导通。
以上仅是举例说明本公开实施例提供的像素补偿电路的具体结构,在具 体实施时,上述驱动电路和发光控制电路的具体结构不限于本公开实施例提供的上述结构,还可以是本领域技术人员可知的其他结构,在此不作限定。
下面以图2所示的像素补偿电路为例,结合图3所示的信号时序图对本公开实施例提供的上述像素补偿电路的工作过程作以描述。下述描述中以1表示高电平信号,0表示低电平信号,需要说明的是,1和0是逻辑电平,其仅是为了更好的解释本公开实施例的具体工作过程,而不是在具体实施时施加在各晶体管的栅极上的电压。
一帧时间可以包括非发光阶段T10和发光阶段T20。其中,非发光阶段T10可以包括:复位阶段T11、阈值补偿阶段T12以及数据写入阶段T13。
在非发光阶段T10中,由于EM1=1,因此第一晶体管M1一直导通,以将第一电源信号ELVDD提供给发光器件L的第二电极,以使发光器件L的第二电极的电压为V
dd,从而使发光器件L处于负偏置状态而不发光。由于EM2=0,因此第二晶体管M2一直截止。
在复位阶段T11,RES=1、GA=1。
由于GA=1,因此第三晶体管M3导通,以将数据信号端DA输入的参考电压信号提供给驱动晶体管M0的栅极G,以使驱动晶体管M0的栅极G的电压为参考电压信号的电压V
ref。由于RES=1,因此第四晶体管M4导通,以将初始化信号端VINIT输入的初始化信号提供给发光器件L的第一电极,使发光器件L的第一电极的电压为初始化信号的电压V
init。因此,第一电容C1两端的电压差为V
ref-V
init。第二电容C2两端的电压差为V
dd-V
init。并且,为了确保驱动晶体管M0在阈值补偿阶段可以导通,因此可以使V
ref和V
init满足关系:V
ref>V
init+V
th;其中,V
th代表驱动晶体管M0的阈值电压。并且,为了避免发光器件L发光,可以使V
init和V
dd满足关系:V
init<V
dd。
在阈值补偿阶段T12,RES=0、GA=1。
由于GA=1,因此第三晶体管M3导通,以将数据信号端DA输入的参考电压信号提供给驱动晶体管M0的栅极G,以使驱动晶体管M0的栅极G的电压继续为参考电压信号的电压V
ref。由于RES=0,因此第四晶体管M4截止。 由于第四晶体管M4截止的瞬间,第一电容C1可以保持其两端的电压差仍为V
ref-V
init。由于V
ref>V
init+V
th,因此驱动晶体管M0可以导通,从而产生由第一极D流向第二极S的电流,以通过该电流对第一电容C1和第二电容C2进行充电,以使第一电容C1的第二端和第二电容C2的第二端的电压(即NB点的电压)逐渐上升。当NB点的电压V
NB1上升到V
ref-V
th时,驱动晶体管M0截止。此时第一电容C1两端的电压差为V
th。并且,当NB点的电压上升到V
ref-V
th,NB点的电荷Q
NBT12可以满足公式:Q
NBT12=c2(V
NB1-V
dd)+c1(V
NB1-V
ref)+cL(V
NB1-V
dd)=(c2+cL)(V
ref-V
th-V
dd)-c1V
th;其中,c1代表第一电容C1的电容值,c2代表第二电容C2的电容值,cL代表发光器件L的第一电极和第二电极之间的电容值。并且,为了避免发光器件L发光,可以使V
ref-V
th<V
dd。
数据写入阶段T13,RES=0、GA=1。
由于RES=0,因此第四晶体管M4截止。由于GA=1,因此第三晶体管M3导通,以将数据信号端DA输入的数据信号提供给驱动晶体管M0的栅极G,并对第一电容C1和第二电容C2充电。在平衡后,驱动晶体管M0的栅极G的电压为数据信号的电压V
DA,NB点的电压为V
NB2。则此时,NB点的电荷Q
NBT13可以满足公式:Q
NBT12=(c2+cL)(V
NB2-V
dd)-c1(V
data-V
NB2)。在数据信号输入的过程中,NB点既没有电荷流入也没有电荷流出,因此Q
NBT13=Q
NBT12。因此,
在发光阶段T20中,由于EM1=0,因此第一晶体管M1一直截止。由于RES=0,因此第四晶体管M4截止。由于GA=0,因此第三晶体管M3截止。由于EM2=1,因此第二晶体管M2一直导通,以将第二电源信号ELVSS提供给发光器件L的第二电极,以使发光器件L的第二电极的电压为V
ss,从而使发光器件L处于正偏置状态。驱动晶体管M0在其第二极S的电压V
NB2与其栅极G的电压V
DA的控制下产生驱动电流I
L,
其中,
μ
n代表驱动晶体管M0的迁移率,C
ox为单位面积栅氧化层电容,
为驱动晶体管M0的宽长比,相同结构中这些数值相对稳定,可以算作常量。这样可以通过驱动电流I
L驱动发光器件L发光。
由于工艺制程和器件老化等原因,会使驱动晶体管的阈值电压V
th产生漂移,这样就导致了流过每个发光器件的驱动电流受V
th漂移的影响而发生变化导致显示亮度不均,从而影响整个图像的显示效果。通过上述驱动电流I
L满足的公式可知,驱动电流I
L仅与数据信号端DA输入的数据信号的电压V
data以及参考电压信号的电压V
ref有关,而与驱动晶体管M0的阈值电压V
th无关,可以解决由于驱动晶体管M0的工艺制程以及长时间的操作造成的阈值电压V
th漂移对驱动电流I
L的影响,从而使发光器件L的驱动电流I
L保持稳定,进而保证了发光器件L的正常工作。
并且,在阈值补偿阶段T12与数据写入阶段T13之间还可以设置有缓冲阶段,这样可以使第一电容C1两端的电压差稳定后,再进行写入V
data,进而进一步提高电路稳定性。
通过上述实施例可以看出,本公开可以通过简单的像素补偿电路的结构,可以在阈值补偿阶段、数据写入阶段使发光器件不进行发光,从而可以避免残影。
本公开实施例提供了另一些像素补偿电路,如图4所示,其针对图2所示的实施方式进行了变形。下面仅说明本实施例与图2所示的像素补偿电路的实施例的区别之处,其相同之处在此不作赘述。
在具体实施时,在本公开实施例中,如图4所示,第一发光控制信号EM1与第二发光控制信号EM2不同,第一晶体管M1和第二晶体管M2的晶体管类型相同。例如,第一晶体管M1和第二晶体管M2均为P型晶体管,则第一发光控制信号EM1与第二发光控制信号EM2如图5所示。进一步地,为了简化制备工艺,也可以使第一晶体管至第四晶体管M1~M4均为P型晶体管, 在此不作限定。
下面以图4所示的像素补偿电路为例,结合图5所示的信号时序图对本公开实施例提供的上述像素补偿电路的工作过程作以描述。下述描述中以1表示高电平信号,0表示低电平信号,需要说明的是,1和0是逻辑电平,其仅是为了更好的解释本公开实施例的具体工作过程,而不是在具体实施时施加在各晶体管的栅极上的电压。
一帧时间可以包括非发光阶段T10和发光阶段T20。其中,非发光阶段T10可以包括:复位阶段T11、阈值补偿阶段T12以及数据写入阶段T13。
在非发光阶段T10中,由于EM1=0,因此第一晶体管M1一直导通,以将第一电源信号ELVDD提供给发光器件L的第二电极,以使发光器件L的第二电极的电压为V
dd。由于EM2=1,因此第二晶体管M2一直截止。
在复位阶段T11,由于GA=0,因此第三晶体管M3导通。并且,由于RES=0,因此第四晶体管M4导通。本阶段的具体过程可以参见图2所示的像素补偿电路的实施例中的复位阶段T11,具体在此不作赘述。
在阈值补偿阶段T12,由于GA=0,因此第三晶体管M3导通。并且,由于RES=1,因此第四晶体管M4截止。本阶段的具体过程可以参见图2所示的像素补偿电路的实施例中的阈值补偿阶段T12,具体在此不作赘述。
在数据写入阶段T13,由于RES=1,因此第四晶体管M4截止。由于GA=0,因此第三晶体管M3导通。本阶段的具体过程可以参见图2所示的像素补偿电路的实施例中的数据写入阶段T13,具体在此不作赘述。
在发光阶段T20中,由于EM1=1,因此第一晶体管M1一直截止。由于RES=1,因此第四晶体管M4截止。由于GA=1,因此第三晶体管M3截止。由于EM2=0,因此第二晶体管M2一直导通,以将第二电源信号ELVSS提供给发光器件L的第二电极,以使发光器件L的第二电极的电压为V
ss。本阶段的具体过程可以参见图2所示的像素补偿电路的实施例中的发光阶段T20,具体在此不作赘述。
本公开实施例提供了又一些像素补偿电路,如图6所示,其针对图2所 示的实施方式进行了变形。下面仅说明本实施例与图2所示的像素补偿电路的实施例的区别之处,其相同之处在此不作赘述。
在具体实施时,在本公开实施例中,如图6所示,第一发光控制信号与第二发光控制信号为同一信号,第一晶体管M1和第二晶体管M2的晶体管类型不同。例如图6所示,第一晶体管M1为N型晶体管,第二晶体管M2为P型晶体管,并且,第一晶体管M1的栅极和第二晶体管M2的栅极均接收第一发光控制信号EM1,以通过第一发光控制信号EM1同时控制第一晶体管M1的栅极和第二晶体管M2。并且,第一发光控制信号EM1如图7所示。当然,也可以使第一晶体管M1的栅极和第二晶体管M2的栅极均接收第二发光控制信号EM2,在此不作限定。
下面以图6所示的像素补偿电路为例,结合图7所示的信号时序图对本公开实施例提供的上述像素补偿电路的工作过程作以描述。下述描述中以1表示高电平信号,0表示低电平信号,需要说明的是,1和0是逻辑电平,其仅是为了更好的解释本公开实施例的具体工作过程,而不是在具体实施时施加在各晶体管的栅极上的电压。
一帧时间可以包括非发光阶段T10和发光阶段T20。其中,非发光阶段T10可以包括:复位阶段T11、阈值补偿阶段T12以及数据写入阶段T13。
在非发光阶段T10中,由于EM1=1,因此第一晶体管M1一直导通,而第二晶体管M2一直截止。
在复位阶段T11,由于GA=1,因此第三晶体管M3导通。并且,由于RES=1,因此第四晶体管M4导通。本阶段的具体过程可以参见图2所示的像素补偿电路的实施例中的复位阶段T11,具体在此不作赘述。
在阈值补偿阶段T12,由于GA=1,因此第三晶体管M3导通。并且,由于RES=0,因此第四晶体管M4截止。本阶段的具体过程可以参见图2所示的像素补偿电路的实施例中的阈值补偿阶段T12,具体在此不作赘述。
在数据写入阶段T13,由于RES=0,因此第四晶体管M4截止。由于GA=1,因此第三晶体管M3导通。本阶段的具体过程可以参见图2所示的像素补偿电 路的实施例中的数据写入阶段T13,具体在此不作赘述。
在发光阶段T20中,由于EM1=0,因此第一晶体管M1一直截止,而第二晶体管M2一直导通。由于RES=0,因此第四晶体管M4截止。由于GA=0,因此第三晶体管M3截止。本阶段的具体过程可以参见图2所示的像素补偿电路的实施例中的发光阶段T20,具体在此不作赘述。
本公开实施例提供了又一些像素补偿电路,如图8所示,其针对图2所示的实施方式进行了变形。下面仅说明本实施例与图2所示的像素补偿电路的实施例的区别之处,其相同之处在此不作赘述。
在具体实施时,在本公开实施例中,如图8所示,第一发光控制信号与第二发光控制信号为同一信号,第一晶体管M1和第二晶体管M2的晶体管类型不同。例如图8所示,第一晶体管M1为P型晶体管,第二晶体管M2为N型晶体管,并且,第一晶体管M1的栅极和第二晶体管M2的栅极均接收第一发光控制信号EM1,以通过第一发光控制信号EM1同时控制第一晶体管M1的栅极和第二晶体管M2。并且,第一发光控制信号EM1如图9所示。当然,也可以使第一晶体管M1的栅极和第二晶体管M2的栅极均接收第二发光控制信号EM2,在此不作限定。
下面以图8所示的像素补偿电路为例,结合图9所示的信号时序图对本公开实施例提供的上述像素补偿电路的工作过程作以描述。下述描述中以1表示高电平信号,0表示低电平信号,需要说明的是,1和0是逻辑电平,其仅是为了更好的解释本公开实施例的具体工作过程,而不是在具体实施时施加在各晶体管的栅极上的电压。
一帧时间可以包括非发光阶段T10和发光阶段T20。其中,非发光阶段T10可以包括:复位阶段T11、阈值补偿阶段T12以及数据写入阶段T13。
在非发光阶段T10中,由于EM1=0,因此第一晶体管M1一直导通,而第二晶体管M2一直截止。
在复位阶段T11,由于GA=1,因此第三晶体管M3导通。并且,由于RES=1,因此第四晶体管M4导通。本阶段的具体过程可以参见图2所示的像素补偿电 路的实施例中的复位阶段T11,具体在此不作赘述。
在阈值补偿阶段T12,由于GA=1,因此第三晶体管M3导通。并且,由于RES=0,因此第四晶体管M4截止。本阶段的具体过程可以参见图2所示的像素补偿电路的实施例中的阈值补偿阶段T12,具体在此不作赘述。
在数据写入阶段T13,由于RES=0,因此第四晶体管M4截止。由于GA=1,因此第三晶体管M3导通。本阶段的具体过程可以参见图2所示的像素补偿电路的实施例中的数据写入阶段T13,具体在此不作赘述。
在发光阶段T20中,由于EM0=0,因此第一晶体管M1一直截止,而第二晶体管M2一直导通。由于RES=0,因此第四晶体管M4截止。由于GA=0,因此第三晶体管M3截止。本阶段的具体过程可以参见图2所示的像素补偿电路的实施例中的发光阶段T20,具体在此不作赘述。
基于同一发明构思,本公开实施例还提供了显示面板,如图10所示,可以包括:衬底基板100和本公开实施例提供的上述任意像素补偿电路。其中,衬底基板100包括显示区AA和围绕显示区AA的非显示区。各像素补偿电路中的驱动电路10和发光器件L位于衬底基板100的显示区AA。本公开实施例提供的显示面板,通过采用上述像素补偿电路,可以使显示面板在阈值补偿阶段、数据写入阶段中不进行发光,从而可以避免残影。
一般显示面板的显示区可以包括多个像素单元,各像素单元可以包括多个子像素。例如,像素单元可以包括红色子像素、绿色子像素、蓝色子像素,这样可以使显示面板采用红绿蓝混色的原理进行画面显示。当然,在实际应用中,像素单元中的子像素可以根据实际应用环境来设计确定,在此不作限定。
在具体实施时,如图10所示,每一个子像素upx中设置一个驱动电路10和一个发光器件L,这样对显示区的改动较小,甚至未对显示区进行改动。在本公开实施例中,可以使所有像素补偿电路共用一个发光控制电路20。即相当于显示面板中仅设置了一个发光控制电路20,显示区AA中的所有发光器件L的第二电极均与同一个发光控制电路20电连接。例如结合图10所示, 发光控制电路20与一个子像素upx中的发光器件L和驱动电路10可以组成一个像素补偿电路。发光控制电路20与另一个子像素upx中的发光器件L和驱动电路10可以组成另一个像素补偿电路。其余以此类推,在此不作赘述。这样可以减少晶体管和信号线的设置,有利于像素布线,提高分辨率。
在具体实施时,在本公开实施例中,如图10所示,显示面板还可以包括:多条栅线310、多条数据线320以及复位信号线330。其中,一行像素单元中的子像素对应一条栅线310,一列子像素对应一条数据线320。结合图2与图10所示,栅线310与对应的像素单元中驱动电路10的第三晶体管M3的栅极电连接,以通过栅线310向扫描信号端GA传输对应时序的信号。数据线320与对应的像素单元中驱动电路10的第三晶体管M3的第一极电连接,以通过数据线320向数据信号端DA传输对应的信号。并且,驱动电路10的第四晶体管M4的栅极与复位信号线330电连接。进一步地,显示区AA中所有驱动电路10的第四晶体管M4的栅极与同一复位信号线330电连接,即向显示区AA中所有第四晶体管M4的栅极电连接的复位信号端RES传输的信号相同。当然,显示区还可以包括:第一电源信号线以及初始化信号线。具体地,第一电源信号线为网格状结构,每一个驱动电路10中的驱动晶体管M0的第一极D均与第一电源信号线电连接,以通过第一电源信号线传输第一电源信号ELVDD。每一个驱动电路10中的第四晶体管M4的第一极均与初始化信号线电连接,以通过初始化信号线传输电压V
init的初始化信号。
一般衬底基板具有围绕显示区的非显示区,在具体实施时,在本公开实施例中,如图10所示,非显示区BB围绕显示区AA设置,可以将发光控制电路20位于衬底基板100的非显示区内。其中,非显示区为除衬底基板100的显示区AA之外的区域。这样可以将发光控制电路20中的晶体管与显示区AA中的晶体管同时进行制备,从而可以降低工艺制备难度。
一般为了向显示区AA提供信号,在具体实施时,显示面板还可以包括:驱动芯片、柔性电路板(Flexible Printed Circuit,FPC)以及印刷电路板(Printed Circuit Board,PCB)中至少一种。其中,驱动芯片可以为驱动集成电路 (Integrated Circuit,IC)。发光控制电路可以位于驱动芯片、柔性电路板以及印刷电路板中至少一种内。例如图11所示,发光控制电路20可以设置于印刷电路板200中。需要说明的是,图11仅是示意出发光控制电路20设置于印刷电路板200中的情况,在发光控制电路20设置于驱动芯片中的情况和发光控制电路20设置于柔性电路板中的情况也可以参照图11所示的设置方式,具体在此不作赘述。
在具体实施时,在本公开实施例中,如图12所示,显示面板还可以包括:栅极驱动电路410以及与各栅线310一一对应的选通控制电路420。其中,各栅线310分别通过对应的选通控制电路420与栅极驱动电路410的一个信号输出端OUT耦接。选通控制电路420被配置为响应于具有第一电平的导通控制信号SEL,将固定电压信号端VGH与对应的栅线310导通;以及响应于具有第二电平的导通控制信号SEL,将连接的信号输出端OUT与对应的栅线310导通。具体地,第一电平可以为高电平,第二电平可以为低电平。或者,第一电平可以为低电平,第二电平可以为高电平,在此不作限定。
在具体实施时,在本公开实施例中,栅极驱动电路410可以通过输入的帧触发信号STV和时钟信号CLK_1~CLK_M(M为时钟信的总数,M的取值可以根据实际应用环境来设计确定,在此不作限定)的控制下,逐行向栅线输出扫描信号。例如结合图13所示,仅以第一行像素单元至第三行像素单元对应的栅线310为例,栅极驱动电路410可以向第一行像素单元对应的栅线310输出扫描信号ga_1,向第二行像素单元对应的栅线310输出扫描信号ga_2,向第三行像素单元对应的栅线310输出扫描信号ga_3,其余以此类推,在此不作赘述。
在具体实施时,在本公开实施例中,栅极驱动电路与选通控制电路的结构和工作原理可以与相关技术中的基本相同,在此不作赘述。
在具体实施时,可以使各选通控制电路接收的导通控制信号为同一信号。如图12所示,这样可以使所有选通控制电路420均与同一导通控制信号线340电连接,以通过导通控制信号线340向各选通控制电路420传输导通控制信 号SEL。
在具体实施时,如图12所示,可以使各选通控制电路420均与同一导通固定电压信号线350电连接,以通过固定电压信号线350向各选通控制电路420传输固定电压信号VGH。
在具体实施时,帧触发信号STV、时钟信号CLK_1~CLK_M、固定电压信号VGH、导通控制信号SEL、复位信号RE、第一电源信号ELVDD、初始化信号可以是PCB上设置的其余电路或驱动IC提供的,在此不作限定。
下面以图6,图10、图12、以及第一行像素单元至第三行像素单元对应的栅线310为例,结合图14所示的信号时序图,对本公开提供的显示面板的工作过程进行说明。但读者应知,其具体过程不局限于此。
一帧时间可以包括非发光阶段T10和发光阶段T20。其中,非发光阶段T10可以包括:复位阶段T11、阈值补偿阶段T12以及数据写入阶段T13。
在非发光阶段T10中,由于EM1=1,因此第一晶体管M1一直导通,以将第一电源信号ELVDD提供给每个发光器件L的第二电极,以使每个发光器件L的第二电极的电压为V
dd。并且,由于EM1=1,因此第二晶体管M2一直截止。
在复位阶段T11,由于SEL=1,因此栅极驱动电路410的信号输出端OUT与栅线310断开,而固定电压信号端VGH与各栅线310导通,以使各栅线310上的信号为高电平信号,例如,第一行栅线310传输给扫描信号端GA的信号GA_1,第二行栅线310传输给扫描信号端GA的信号GA_2,第三行栅线310传输给扫描信号端GA的信号GA_3。由于GA_1=1~GA_3=1,因此,显示区AA中的所有第三晶体管M3可以同时导通,以将数据信号端DA输入的参考电压信号提供给驱动晶体管M0的栅极G,以使每个驱动晶体管M0的栅极G的电压为参考电压信号的电压V
ref。由于RES=1,因此显示区AA中的所有第四晶体管M4导通,以将初始化信号端VINIT输入的初始化信号提供给发光器件L的第一电极,使每个发光器件L的第一电极的电压为初始化信号的电压V
init。
在阈值补偿阶段T12,由于RES=0,因此显示区AA中的所有第四晶体管M4截止。由于SEL=1,因此固定电压信号端VGH与各栅线310导通,以使各栅线310上的信号为高电平信号,例如,第一行栅线310传输给扫描信号端GA的信号GA_1,第二行栅线310传输给扫描信号端GA的信号GA_2,第三行栅线310传输给扫描信号端GA的信号GA_3。由于GA_1=1~GA_3=1,因此,显示区AA中的所有第三晶体管M3可以同时导通,以将数据信号端DA输入的参考电压信号提供给驱动晶体管M0的栅极G,以使每个驱动晶体管M0的栅极G的电压为参考电压信号的电压V
ref。由于第四晶体管M4截止的瞬间,每个第一电容C1可以保持其两端的电压差仍为V
ref-V
init。由于V
ref>V
init+V
th,因此每个驱动晶体管M0可以导通,从而产生由第一极D流向第二极S的电流,以通过该电流对第一电容C1和第二电容C2进行充电,以使第一电容C1的第二端和第二电容C2的第二端的电压(即NB点的电压)逐渐上升。当NB点的电压V
NB1上升到V
ref-V
th时,每个驱动晶体管M0截止。并且,每个NB点的电荷Q
NBT12可以满足公式:Q
NBT12=c2(V
NB1-V
dd)+c1(V
NB1-V
ref)+cL(V
NB1-V
dd)=(c2+cL)(V
ref-V
th-V
dd)-c1V
th。
在数据写入阶段T13,由于RES=0,因此显示区AA中的所有第四晶体管M4截止。由于SEL=0,因此固定电压信号端VGH与各栅线310断开,而栅极驱动电路410的信号输出端OUT与栅线310导通,以使栅极驱动电路410向栅线输出扫描信号,第一行栅线310传输给扫描信号端GA的信号GA_1,第二行栅线310传输给扫描信号端GA的信号GA_2,第三行栅线310传输给扫描信号端GA的信号GA_3,以控制第三晶体管逐行导通。
具体地,由于GA_1=1,因此第一行各子像素中的第三晶体管M3导通,以将数据信号端DA输入的数据信号提供给驱动晶体管M0的栅极G,并对第一电容C1和第二电容C2充电。在平衡后,驱动晶体管M0的栅极G的电压为数据信号的电压V
DA,NB点的电压为V
NB2。则此时,NB点的电荷Q
NBT13可以满足公式:Q
NBT12=(c2+cL)(V
NB2-V
dd)-c1(V
data-V
NB2)。在数据信号输入的过 程中,NB点既没有电荷流入也没有电荷流出,因此T13阶段中NB点的电荷Q
NBT13=Q
NBT12。因此,
由于GA_2=0,因此第二行各子像素中的第三晶体管M3截止。由于GA_3=0,因此第三行各子像素中的第三晶体管M3截止。其余依次类推,在此不作赘述。
之后,由于GA_2=1,因此第二行各子像素中的第三晶体管M3导通,以将数据信号端DA输入的数据信号提供给驱动晶体管M0的栅极G,并对第一电容C1和第二电容C2充电。在平衡后,驱动晶体管M0的栅极G的电压为数据信号的电压V
DA,NB点的电压为V
NB2。则此时,NB点的电荷Q
NBT13可以满足公式:Q
NBT12=(c2+cL)(V
NB2-V
dd)-c1(V
data-V
NB2)。在数据信号输入的过程中,NB点既没有电荷流入也没有电荷流出,因此T13阶段中NB点的电荷Q
NBT13=Q
NBT12。因此,
由于GA_1=0,因此第一行各子像素中的第三晶体管M3截止。由于GA_3=0,因此第三行各子像素中的第三晶体管M3截止。其余依次类推,在此不作赘述。
之后,由于GA_3=1,因此第三行各子像素中的第三晶体管M3导通,以将数据信号端DA输入的数据信号提供给驱动晶体管M0的栅极G,并对第一电容C1和第二电容C2充电。在平衡后,驱动晶体管M0的栅极G的电压为数据信号的电压V
DA,NB点的电压为V
NB2。则此时,NB点的电荷Q
NBT13可以满足公式:Q
NBT12=(c2+cL)(V
NB2-V
dd)-c1(V
data-V
NB2)。在数据信号输入的过程中,NB点既没有电荷流入也没有电荷流出,因此T13阶段中NB点的电荷Q
NBT13=Q
NBT12。因此,
由于GA_1=0,因此第一行各子像素中的第三晶体管M3截止。由于GA_2=0,因此第二行各子像素中的第三晶体管M3截止。其余依次类推,在此不作赘述。
在发光阶段T20中,由于SEL=0,因此栅极驱动电路410的信号输出端OUT与栅线310导通,以使栅极驱动电路410向栅线输出扫描信号,第一行栅线310传输给扫描信号端GA的信号GA_1,第二行栅线310传输给扫描信 号端GA的信号GA_2,第三行栅线310传输给扫描信号端GA的信号GA_3,以控制各第三晶体管截止。由于EM1=0,因此第一晶体管M1一直截止,第二晶体管M2一直导通。由于RES=0,因此第四晶体管M4截止。导通的第二晶体管M2将第二电源信号ELVSS提供给每个发光器件L的第二电极,以使每个发光器件L的第二电极的电压为V
ss。每个驱动晶体管M0在其第二极S的电压V
NB2与其栅极G的电压V
DA的控制下产生驱动电流I
L,
以通过驱动电流I
L驱动发光器件L发光。
通过上述实施例可以看出,本公开实施例提供的显示面板通过第一晶体管M1控制显示面板处于非显示阶段T10,通过第二晶体管M2控制显示面板处于显示阶段T20,从而可以采用简单的像素补偿电路的结构以使显示面板完全处于非显示阶段,从而可以避免非显示阶段出现残影,提高显示效果。
并且,在复位阶段T11,通过使显示面板中的第三晶体管M3同时打开,可以同时对每个驱动晶体管M0的栅极G写入V
ref。以及通过使显示面板中的第四晶体管M4同时打开,可以同时对每个驱动晶体管M0的第二极S写入V
init,以及同时对发光器件L的第一电极进行复位。这样可以减少栅线的设置。
并且,目前一般采用逐行写入V
th的方式进行阈值补偿,使得补偿V
th的时间仅有一行像素打开的时间,这样导致补偿V
th的时间较短,充电率较低。而本公开实施例提供的显示面板,在阈值补偿阶段T12,通过使显示面板中的每个第三晶体管M3同时打开,以将每个驱动晶体管M0的V
th同时写入其栅极G,之后在数据写入阶段T13中,逐行对每个驱动晶体管M0写入数据信号。这样与逐行写入V
th相比,可以使写入V
th的时间足够长,提高写入V
th的充电率,以解决在高刷新率下V
th写入不充分的问题。并且,还可以仅采用数据线既可以传输参考电压信号,又可以传输数据信号,从而降低信号线的数量。
并且,数据写入阶段T13的维持时长t
13可以满足:t
13≤t
F-(t
11+t
12+t
20); 其中,t
F代表一帧时间的维持时长,t
11代表一帧时间内的复位阶段T11的维持时长,t
12代表一帧时间内的阈值补偿阶段T12的维持时长,t
20代表一帧时间内的发光阶段T20的维持时长。一行像素单元扫描的维持时长为t
13/K;其中K代表栅线的总数。进一步地,t
13可以为k个t
13/K的时间,其中k可以正整数,例如k为1至50中的一个数值。并且,还可以通过t
20/t
F来设置发光器件的亮度。当然,在实际应用中,K及上述维持时长的具体数值可以根据实际应用环境来设计确定,在此不作限定。
本公开实施例提供了另一些显示面板,如图15与图16所示,其针对图10所示的实施方式进行了变形。下面仅说明本实施例与图10所示的显示面板的实施例的区别之处,其相同之处在此不作赘述。
在具体实施时,在本公开实施例中,如图15与图16所示,显示区AA可以包括:多个子显示区aa_y(y为大于1且小于或等于Y的整数,Y为子显示区的总数,图15以Y=2为例,图16以Y=4为例)。可以使每一个子显示区aa_y中的所有发光器件L均耦接同一个发光控制电路20,以进行分区域控制。不去,这样还可以发光控制电路20的驱动难度。
在具体实施时,在本公开实施例中,每个子显示区可以包括多个像素单元。或者,每个子显示区也可以仅包括一个子像素。在实际应用中,子显示区的具体实现方式可以根据实际应用环境来设计确定,在此不作限定。
在具体实施时,在本公开实施例中,如图15与图16所示,每一个子显示区aa_y一一对应一个发光控制电路20,并且可以使发光控制电路20位于衬底基板100上对应的子显示区aa_y内。这样可以使发光控制电路距离对应的发光器件L更近。或者,也可以使发光控制电路20位于非显示区内。例如,发光控制电路20位于衬底基板100围绕显示区AA的非显示内。或者发光控制电路20位于驱动芯片、柔性电路板以及印刷电路板中至少一种内。当然,这可以根据实际应用环境来设计确定,在此不作限定。
在具体实施时,在本公开实施例中,可以使各子显示区沿第一方向延伸,且各子显示区沿第二方向排列;其中,第一方向与第二方向交叉。具体地, 如图15所示,第一方向可以为像素单元的行方向,第二方向可以为像素单元的列方向,各子显示区aa_y沿像素单元的行方向延伸,且各子显示区aa_y沿像素单元的列方向排列。或者,第一方向也可以为像素单元的列方向,第二方向为像素单元的行方向,各子显示区沿像素单元的列方向延伸,且各子显示区沿像素单元的行方向排列。当然,这可以根据实际应用环境来设计确定,在此不作限定。
在具体实施时,在本公开实施例中,如图16所示,也可以使各子显示区aa_y呈矩阵排列方式分布。
基于同一发明构思,本公开实施例还提供了上述显示面板的驱动方法,其中,如图17所示,一帧时间包括:
S100、非发光阶段,至少部分发光控制电路响应于第一发光控制信号,将第一电源信号提供给发光器件的第二电极。具体地,可以使所有发光控制电路响应于第一发光控制信号,将第一电源信号提供给发光器件的第二电极。或者,也可以使部分发光控制电路响应于第一发光控制信号,将第一电源信号提供给发光器件的第二电极。当然,这可以根据实际应用环境来设计确定,在此不作限定。
S200、发光阶段,至少部分发光控制电路响应于第二发光控制信号,将第二电源信号提供给发光器件的第二电极;驱动电路产生向发光器件的第一电极输入的驱动电流,驱动发光器件发光。具体地,可以使所有发光控制电路响应于第二发光控制信号,将第二电源信号提供给发光器件的第二电极;所有驱动电路产生向发光器件的第一电极输入的驱动电流,驱动发光器件发光。或者,也可以使部分发光控制电路响应于第二发光控制信号,将第二电源信号提供给发光器件的第二电极;与该发光控制电路对应的驱动电路产生向发光器件的第一电极输入的驱动电流,驱动发光器件发光。当然,这可以根据实际应用环境来设计确定,在此不作限定。
在具体实施时,在本公开实施例中,非发光阶段可以包括:
复位阶段,所有第三晶体管响应于扫描信号端的信号同时导通,将数据 信号端的参考电压信号提供给驱动晶体管的栅极;所有第四晶体管响应于复位信号端的信号同时导通,将初始化信号端的信号提供给发光器件的第一电极;
阈值补偿阶段,所有第三晶体管响应于扫描信号端的信号同时导通,将数据信号端的参考电压信号提供给驱动晶体管的栅极;所有驱动晶体管同时导通,将驱动晶体管的阈值电压写入驱动晶体管的第二极;
数据写入阶段,第三晶体管响应于扫描信号端的信号逐行导通,将数据信号端的数据信号提供给驱动晶体管的栅极;并通过第一电容和第二电容,将数据信号的电压写入驱动晶体管的第二极。
其中,该显示面板的驱动方法的驱动原理和具体实施方式与上述实施例显示面板的原理和实施方式相同,因此,该显示面板的驱动方法可参见上述实施例中显示面板的具体实施方式进行实施,在此不再赘述。
基于同一发明构思,本公开实施例还提供了显示装置,包括本公开实施例提供的上述显示面板。该显示装置解决问题的原理与前述显示面板相似,因此该显示装置的实施可以参见前述显示面板的实施,重复之处在此不再赘述。
在具体实施时,本公开实施例提供的显示装置可以为如图18所示的手机。当然,本公开实施例提供的显示装置也可以为平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的,在此不做赘述,也不应作为对本公开的限制。
本公开实施例提供的像素补偿电路、显示面板,驱动方法及显示装置,在非发光阶段,通过发光控制电路响应于第一发光控制信号将第一电源信号提供给发光器件的第二电极,以控制发光器件不发光。在发光阶段,通过驱动电路产生向发光器件的第一电极输入的驱动电流,并通过发光控制电路响应于第二发光控制信号将第二电源信号提供给发光器件的第二电极,以使驱动电流驱动发光器件发光。从而可以采用简单的结构控制发光器件是否发光, 进而可以降低工艺难度,降低生产成本,降低像素补偿电路占用面积,以及有利于显示面板实现高分辨率。
显然,本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样,倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内,则本公开也意图包含这些改动和变型在内。
Claims (19)
- 一种像素补偿电路,其中,包括:发光器件;驱动电路,被配置为产生向所述发光器件的第一电极输入的驱动电流;发光控制电路,被配置为响应于第一发光控制信号将第一电源信号提供给所述发光器件的第二电极,以及响应于第二发光控制信号将第二电源信号提供给所述发光器件的第二电极;其中,所述第一电源信号与所述第二电源信号的电平相反。
- 如权利要求1所述的像素补偿电路,其中,所述驱动电路和所述发光器件被配置在显示面板的显示区,所述发光控制电路被配置在所述显示面板的非显示区。
- 如权利要求1或2所述的像素补偿电路,其中,所述发光控制电路包括:第一晶体管和第二晶体管;所述第一晶体管的栅极被配置为接收所述第一发光控制信号,所述第一晶体管的第一极被配置为接收所述第一电源信号,所述第一晶体管的第二极与所述发光器件的第二电极耦接;所述第二晶体管的栅极被配置为接收所述第二发光控制信号,所述第二晶体管的第一极被配置为接收所述第二电源信号,所述第二晶体管的第二极与所述发光器件的第二电极耦接。
- 如权利要求2所述的像素补偿电路,其中,所述第一发光控制信号与所述第二发光控制信号为同一信号,所述第一晶体管和所述第二晶体管的晶体管类型不同。
- 如权利要求2所述的像素补偿电路,其中,所述第一发光控制信号与所述第二发光控制信号不同,所述第一晶体管和所述第二晶体管的晶体管类型相同。
- 如权利要求1或2所述的像素补偿电路,其中,所述驱动电路包括: 驱动晶体管、第三晶体管、第四晶体管、第一电容以及第二电容;所述驱动晶体管的栅极与所述第一电容的第一端耦接,所述驱动晶体管的第一极被配置为接收所述第一电源信号,所述驱动晶体管的第二极与所述发光器件的第一电极耦接;所述第三晶体管的栅极与扫描信号端耦接,所述第三晶体管的第一极与数据信号端耦接,所述第三晶体管的第二极与所述驱动晶体管的栅极耦接;所述第四晶体管的栅极与复位信号端耦接,所述第四晶体管的第一极与初始化信号端耦接,所述第四晶体管的第二极与所述发光器件的第一电极耦接;所述第一电容的第二端与所述发光器件的第一电极耦接;所述第二电容的第一端被配置为接收所述第一电源信号,所述第二电容的第二端与所述发光器件的第一电极耦接。
- 一种显示面板,其中,包括:衬底基板和多个如权利要求1所述的像素补偿电路;其中,所述衬底基板包括显示区和围绕所述显示区的非显示区;各所述像素补偿电路中的驱动电路和发光器件位于所述衬底基板的显示区。
- 如权利要求7所述的显示面板,其中,所述发光控制电路位于所述非显示区内。
- 如权利要求7所述的显示面板,其中,所述显示面板还包括:驱动芯片、柔性电路板以及印刷电路板中至少一种;所述发光控制电路位于所述驱动芯片、柔性电路板以及印刷电路板中至少一种内。
- 如权利要求7所述的显示面板,其中,所述显示区包括:多个子显示区;每一个所述子显示区中的所有发光器件耦接同一个发光控制电路。
- 如权利要求10所述的显示面板,其中,每一个所述子显示区一一对应一个所述发光控制电路,所述发光控制电路位于所述衬底基板上对应的所述子显示区内。
- 如权利要求10或11所述的显示面板,其中,各所述子显示区沿第一方向延伸,且各所述子显示区沿第二方向排列;所述第一方向与所述第二方向交叉。
- 如权利要求10或11所述的显示面板,其中,各所述子显示区呈矩阵排列方式分布。
- 如权利要求7-9任一项所述的显示面板,其中,所有所述像素补偿电路共用一个发光控制电路。
- 如权利要求7-14任一项所述的显示面板,其中,所述显示面板还包括:多条栅线、栅极驱动电路以及与各所述栅线一一对应的选通控制电路;各所述栅线分别通过对应的选通控制电路与所述栅极驱动电路的一个信号输出端耦接;所述选通控制电路被配置为响应于具有第一电平的导通控制信号,将固定电压信号端与对应的所述栅线导通;以及响应于具有第二电平的导通控制信号,将连接的所述信号输出端与对应的所述栅线导通。
- 如权利要求15所述的显示面板,其中,各所述选通控制电路接收的导通控制信号为同一信号。
- 一种显示装置,其中,包括如权利要求7-16任一项所述的显示面板。
- 一种如权利要求7-16任一项所述的显示面板的驱动方法,其中,一帧时间包括:非发光阶段,至少部分所述发光控制电路响应于第一发光控制信号,将第一电源信号提供给所述发光器件的第二电极;发光阶段,至少部分所述发光控制电路响应于第二发光控制信号,将第二电源信号提供给发光器件的第二电极;所述驱动电路产生向所述发光器件的第一电极输入的驱动电流,驱动所述发光器件发光。
- 如权利要求18所述的驱动方法,其中,所述非发光阶段包括:复位阶段,所有第三晶体管响应于扫描信号端的信号同时导通,将数据信号端的参考电压信号提供给驱动晶体管的栅极;所有第四晶体管响应于复 位信号端的信号同时导通,将初始化信号端的信号提供给所述发光器件的第一电极;阈值补偿阶段,所有所述第三晶体管响应于所述扫描信号端的信号同时导通,将所述数据信号端的所述参考电压信号提供给所述驱动晶体管的栅极;所有所述驱动晶体管同时导通,将所述驱动晶体管的阈值电压写入所述驱动晶体管的第二极;数据写入阶段,所述第三晶体管响应于所述扫描信号端的信号逐行导通,将所述数据信号端的数据信号提供给所述驱动晶体管的栅极;并通过所述第一电容和所述第二电容,将所述数据信号的电压写入所述驱动晶体管的第二极。
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EP3951759A4 (en) | 2022-10-26 |
JP2022534548A (ja) | 2022-08-02 |
CN112352274B (zh) | 2022-11-04 |
CN112352274A (zh) | 2021-02-09 |
EP3951759A1 (en) | 2022-02-09 |
US20210241688A1 (en) | 2021-08-05 |
US11462158B2 (en) | 2022-10-04 |
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