WO2020196106A1 - プリント配線板の製造方法 - Google Patents
プリント配線板の製造方法 Download PDFInfo
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- WO2020196106A1 WO2020196106A1 PCT/JP2020/011792 JP2020011792W WO2020196106A1 WO 2020196106 A1 WO2020196106 A1 WO 2020196106A1 JP 2020011792 W JP2020011792 W JP 2020011792W WO 2020196106 A1 WO2020196106 A1 WO 2020196106A1
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- electroless plating
- plating layer
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- base material
- insulating base
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1633—Process of electroless plating
- C23C18/1646—Characteristics of the product obtained
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1633—Process of electroless plating
- C23C18/1689—After-treatment
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/18—Pretreatment of the material to be coated
- C23C18/20—Pretreatment of the material to be coated of organic surfaces, e.g. resins
- C23C18/2006—Pretreatment of the material to be coated of organic surfaces, e.g. resins by other methods than those of C23C18/22 - C23C18/30
- C23C18/2046—Pretreatment of the material to be coated of organic surfaces, e.g. resins by other methods than those of C23C18/22 - C23C18/30 by chemical pretreatment
- C23C18/2073—Multistep pretreatment
- C23C18/2086—Multistep pretreatment with use of organic or inorganic compounds other than metals, first
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/18—Pretreatment of the material to be coated
- C23C18/20—Pretreatment of the material to be coated of organic surfaces, e.g. resins
- C23C18/22—Roughening, e.g. by etching
- C23C18/24—Roughening, e.g. by etching using acid aqueous solutions
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
- C25D5/022—Electroplating of selected surface areas using masking means
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/16—Coating processes; Apparatus therefor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
- G03F7/405—Treatment with inorganic or organometallic reagents after imagewise removal
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1152—Replicating the surface structure of a sacrificial layer, e.g. for roughening
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
- H05K3/025—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
Definitions
- the present invention relates to a method for manufacturing a printed wiring board.
- the semi-additive method is widely adopted as a method for manufacturing a printed wiring board suitable for circuit miniaturization.
- the SAP method is a method suitable for forming an extremely fine circuit, and as an example thereof, a roughened copper foil with a carrier is used. For example, as shown in FIGS. 10 and 11, the roughened copper foil 110 is pressed and adhered to the base material 111a on the insulating resin substrate 111 provided with the lower layer circuit 111b by using the prepreg 112 and the primer layer 113.
- Step (a) the carrier (not shown) is peeled off, and then a via hole 114 is formed by laser perforation if necessary (step (b)).
- step (c) the roughened copper foil 110 is removed by etching to expose the primer layer 113 having the roughened surface profile (step (c)).
- electrolytic copper plating 115 is applied to the roughened surface (step (d))
- masking is performed in a predetermined pattern by exposure and development using a dry film 116 (step (e)), and electrolytic copper plating 117 is applied. (Step (f)).
- step (g) After removing the dry film 116 to form the wiring portion 117a (step (g)), the unnecessary electroless copper plating 115 between the adjacent wiring portions 117a and 117a was removed by etching (step (h)). Obtain wiring 118 formed in a predetermined pattern.
- the roughened copper foil itself is removed by etching after laser perforation (step (c)). Then, since the uneven shape of the roughened surface of the roughened copper foil is transferred to the surface of the laminate from which the roughened copper foil has been removed, the insulating layer (for example, the primer layer 113 or it) is transferred in the subsequent steps. If not, the adhesion between the prepreg 112) and the plating circuit (for example, the wiring 118) can be ensured.
- the surface profile suitable for improving the adhesion to the plating circuit generally tends to have rough irregularities, the etching property for electroless copper plating tends to decrease in the step (h). That is, since the electroless copper plating bites into the rough unevenness, more etching is required to eliminate the residual copper.
- Patent Document 1 International Publication No. 2016/158775 describes a roughened copper foil having a roughened surface on at least one side, wherein the roughened surface is a plurality of substantially spherical surfaces made of copper particles. Those provided with protrusions and having a substantially spherical protrusion having an average height of 2.60 ⁇ m or less are disclosed. Further, in Patent Document 2 (International Publication No.
- a copper foil having a smooth surface and having small roughened particles is used. It is conceivable to impart a roughened surface profile to the insulating substrate. Further, if electroless plating can be thinly applied (for example, less than 1.0 ⁇ m) to the surface of the insulating base material to which the roughened surface profile is given, the etching amount can be reduced and the circuit can be further miniaturized. It is convenient because it can be done.
- the present inventors have recently performed electroless plating on an insulating base material having a roughened surface to form an electroless plating layer having a predetermined surface parameter and having a thickness of less than 1.0 ⁇ m, thereby causing a pattern defect. It was found that it is possible to provide a method for manufacturing a printed wiring board, which effectively suppresses the above-mentioned problems and has excellent fine circuit formability.
- an object of the present invention is to provide a method for manufacturing a printed wiring board, which effectively suppresses pattern defects and is also excellent in fine circuit formability.
- the "arithmetic mean swell Wa” is the arithmetic mean height at the reference length of the swell curve as a contour curve, which is measured in accordance with JIS B0601-2001.
- the waviness curve represents a larger scale of unevenness (ie, waviness) rather than the fine irregularities represented by the roughness curve.
- the arithmetic mean waviness Wa can be calculated by measuring the surface profile of a predetermined measurement length (for example, a one-dimensional region of 64.124 ⁇ m) on the roughened surface with a commercially available laser microscope.
- Kurtosis Sk is a parameter representing the sharpness of the height distribution measured in accordance with ISO25178, and is also referred to as sharpness.
- Sku 3 means that the height distribution is a normal distribution, and when Sku> 3, there are many sharp peaks and valleys on the surface, and when Suku ⁇ 3, the surface is flat.
- the Kurtsis Sk can be calculated by measuring the surface profile of a predetermined measurement area (for example, a two-dimensional region of 6811.801 ⁇ m 2 ) on the roughened surface with a commercially available laser microscope.
- the "maximum height Sz" is a parameter representing the distance from the highest point to the lowest point on the surface, which is measured according to ISO25178.
- the maximum height Sz can be calculated by measuring the surface profile of a predetermined measurement area (for example, a two-dimensional region of 6811.801 ⁇ m 2 ) on the roughened surface with a commercially available laser microscope.
- the "surface load curve” (hereinafter, simply referred to as "load curve”) is a curve representing the height at which the load area ratio is 0% to 100%, which is measured in accordance with ISO25178.
- the load area ratio is a parameter representing the area of a region having a certain height c or more.
- the load area ratio at the height c corresponds to Smr (c) in FIG.
- the secant line of the load curve drawn from the load area ratio of 0% along the load curve with the difference of the load area ratio set to 40% is moved from the load area ratio of 0% and the secant line.
- the position where the slope is the gentlest is called the central part of the load curve.
- the straight line that minimizes the sum of squares of the deviations in the vertical axis direction with respect to this central portion is called an equivalent straight line.
- the portion included in the height range of the load area ratio of the equivalent straight line from 0% to 100% is called the core portion.
- the part higher than the core part is called the protruding mountain part, and the part lower than the core part is called the protruding valley part.
- the core portion represents the height of the area that comes into contact with other objects after the initial wear is completed.
- the “load area ratio Smr2 that separates the protruding valley portion and the core portion” is the height and load curve of the lower portion of the core portion measured in accordance with ISO25178 as shown in FIG. It is a parameter representing the load area ratio at the intersection of (that is, the load area ratio that separates the core portion and the protruding valley portion). The larger this value is, the larger the proportion of the protruding valley is.
- the “valley void volume Vvv” is a parameter representing the volume of the protruding valley space, which is measured in accordance with ISO25178. As shown in FIG. 9, Vvv represents the volume of the space portion calculated from the load curve from the load area ratio Smr2 to the load area ratio 100%.
- the void volume Vvv of the valley can be calculated by measuring the surface profile of a predetermined measurement area (for example, a two-dimensional region of 6811.801 ⁇ m 2 ) on the roughened surface with a commercially available laser microscope.
- the load area ratio Smr2 that separates the protruding valley portion and the core portion is specified as 80%, and the void volume Vvv of the valley portion is calculated.
- the present invention relates to a manufacturing method of a printed wiring board.
- the method of the present invention includes (a) preparation of an insulating base material, (b) formation of an electroless plating layer, (c) lamination of a photoresist, (d) formation of a resist pattern, and (e) formation of an electroplating layer. Each step of (f) peeling of the resist pattern and (g) forming of the wiring pattern is included.
- an insulating base material 20 having a roughened surface 20a is prepared.
- the insulating base material 20 may have roughened surfaces 20a on both sides, or may have roughened surfaces 20a on only one side.
- the insulating base material 20 preferably contains an insulating resin.
- the insulating base material 20 is preferably a prepreg and / or a resin sheet.
- Prepreg is a general term for composite materials in which a base material such as a synthetic resin plate, a glass plate, a glass woven fabric, a glass non-woven fabric, or paper is impregnated with a synthetic resin.
- Preferred examples of the insulating resin impregnated in the prepreg include an epoxy resin, a cyanate resin, a bismaleimide triazine resin (BT resin), a polyphenylene ether resin, a phenol resin and the like. Further, examples of the insulating resin constituting the resin sheet include insulating resins such as epoxy resin, polyimide resin, and polyester resin.
- the insulating base material 20 may contain filler particles made of various inorganic particles such as silica and alumina from the viewpoint of improving the insulating property.
- the thickness of the insulating base material 20 is not particularly limited, but is preferably 1 ⁇ m or more and 1000 ⁇ m or less, more preferably 2 ⁇ m or more and 400 ⁇ m or less, and further preferably 3 ⁇ m or more and 200 ⁇ m or less.
- the insulating base material 20 may be composed of a plurality of layers.
- the roughened surface 20a of the insulating base material 20 may be formed by any method, but is typically formed by transferring the uneven shape of the treated surface of the surface-treated copper foil to the surface of the insulating base material 20. Will be done.
- the roughened surface 20a is formed by using the surface-treated copper foil by preparing (a-1) a surface-treated copper foil having a predetermined treated surface and (a-2) surface-treating. After laminating an insulating base material on the treated surface of the copper foil and transferring the surface shape of the treated surface to the surface of the insulating base material, the surface treated copper foil is removed by (a-3) etching to obtain a roughened surface. This is done by obtaining a provided insulating substrate.
- the specific procedure of each step is as follows.
- a surface-treated copper foil 10 having a treated surface 10a on at least one side is prepared.
- the treated surface 10a is a surface that has been subjected to some surface treatment, and is typically a roughened surface.
- the treated surface 10a typically comprises a plurality of bumps (eg roughened particles).
- the surface-treated copper foil 10 may have a treated surface 10a on both sides, or may have a treated surface 10a on only one side.
- the surface on the laser irradiation side (the surface opposite to the surface in close contact with the insulating base material) is also surface-treated when used in the SAP method, so that the laser absorbency As a result, the laser perforation property can also be improved.
- the surface-treated copper foil 10 may be in the form of a copper foil with a carrier.
- the copper foil with a carrier includes a carrier, a release layer provided on the carrier, and a surface-treated copper foil 10 provided on the release layer with the treated surface 10a on the outside. It is typical.
- the copper foil with a carrier a known layer structure can be adopted except that the surface-treated copper foil 10 is used.
- the treated surface 10a of the surface-treated copper foil 10 preferably has an arithmetic mean waviness Wa of 0.20 ⁇ m or more and 0.35 ⁇ m or less, and more preferably 0.25 ⁇ m or more and 0.32 ⁇ m or less.
- the treated surface 10a of the surface-treated copper foil 10 preferably has a maximum height Sz of 3.0 ⁇ m or more and 4.0 ⁇ m or less, and more preferably 3.1 ⁇ m or more and 3.9 ⁇ m or less.
- the treated surface 10a of the surface-treated copper foil 10 preferably has a valley void volume Vvv of 0.030 ⁇ m 3 / ⁇ m 2 or more and 0.050 ⁇ m 3 / ⁇ m 2 or less, more preferably 0.035 ⁇ m 3 /. It is ⁇ m 2 or more and 0.045 ⁇ m 3 / ⁇ m 2 or less. It can be said that the treated surface 10a having such surface parameters has a shape having large waviness and small bumps (for example, roughened particles).
- the electroless plating layer 22 having a unique surface parameter described later is formed on the roughened surface 20a of the insulating base material 20. It becomes easy to form.
- the treated surface 10a having the above surface parameters can be formed by subjecting the copper foil surface to a surface treatment (typically roughening treatment) under known or desired conditions. Further, a commercially available copper foil having a treated surface 10a satisfying the above conditions may be selectively obtained.
- the insulating base material 20' (that is, the roughened surface 20a is formed on the treated surface 10a of the surface-treated copper foil 10).
- the uninsulated insulating base material 20) is laminated to form a copper-clad laminate 12.
- the surface shape of the treated surface 10a can be transferred to the surface of the insulating base material 20'.
- Lamination of the insulating base material 20' preferably involves hot press working, and the processing temperature and processing time of this hot pressing work are appropriately determined based on known conditions according to the type of the insulating base material 20'to be laminated and the like. can do.
- the preferred types of the insulating base material 20' are as described above with respect to the insulating base material 20.
- the insulating base material 20' may be laminated on the surface-treated copper foil 10 in advance via a primer layer (not shown) applied to the treated surface 10a of the surface-treated copper foil 10.
- the primer layer is considered to form a part of the insulating base material.
- the primer layer is preferably composed of a resin, and this resin preferably contains an insulating resin. If desired, via holes (not shown) may be formed in the copper-clad laminate 12 by laser perforation prior to the removal of the surface-treated copper foil 10 in the next step.
- the surface-treated copper foil 10 of the copper-clad laminate 12 is removed by etching to provide insulation having a roughened surface 20a.
- the etching of the surface-treated copper foil 10 may be performed according to an etching method and conditions generally used for manufacturing a printed wiring board using, for example, a sulfuric acid-hydrogen peroxide-based etching solution, and is not particularly limited.
- electroless plating for example, electroless copper plating
- the electroless plating layer 22 of the above is formed.
- the electroless plating may be performed according to a method and conditions generally used for manufacturing a printed wiring board using a commercially available electroless plating solution, and is not particularly limited.
- the arithmetic mean waviness Wa is 0.10 ⁇ m or more and 0.25 ⁇ m or less, and the void volume Vvv at the valley is 0.010 ⁇ m 3 / ⁇ m 2 or more and 0.028 ⁇ m 3 / ⁇ m 2 or less. is there.
- the insulating base material 20 provided with the roughened surface 20a is electroless plated to form the electroless plating layer 22 having the above-mentioned predetermined surface parameters and having a thickness of less than 1.0 ⁇ m, whereby the pattern is defective. It is possible to provide a method for manufacturing a printed wiring board, which effectively suppresses the above and is also excellent in fine circuit formability.
- a copper foil having a smooth surface and provided with small roughened particles is used. It is conceivable to impart a roughened surface profile to the insulating substrate. Further, if electroless plating can be thinly applied (for example, less than 1.0 ⁇ m) to the surface of the insulating base material to which the roughened surface profile is given, the etching amount can be reduced and the circuit can be further miniaturized. It is convenient because it can be done.
- the roughened surface of the insulating base material generally reflects the surface profile of the surface-treated copper foil.
- electroless plating is applied to the roughened surface of the insulating base material with a thickness of less than 1.0 ⁇ m, the surface shape of the electroless plated layer largely reflects the surface shape of the roughened surface of the insulating base material. It will be the one that was done. Therefore, as the copper foil used for transferring the surface profile to the insulating base material, a copper foil having a smooth surface and having small roughened particles (in other words, a copper foil having a fine uneven shape) is used.
- FIGS. 4 (i) to 4 (iv) electrolessly laminated laminated on an insulating base material 20 in order to form a circuit in a predetermined pattern.
- a photoresist 24 (including, for example, a dry film resist 24a and a support film 24b) is further laminated on the surface of the plating layer 22, and exposure and development are performed to form a resist pattern 26.
- FIG. 4 (i) to 4 (iv) electrolessly laminated laminated on an insulating base material 20 in order to form a circuit in a predetermined pattern.
- a photoresist 24 including, for example, a dry film resist 24a and a support film 24b
- the portion of the photoresist 24 (for example, the dry film resist 24a) directly under the foreign matter F, which should have been originally exposed, remains unexposed (see FIG. 4 (iii)), and the hole H is formed after development. Is formed (see FIG. 4 (iv)).
- electroplating is applied to a portion where the circuit should not be formed, and this unnecessary electroplating portion causes a short circuit or a convex portion of the circuit described above, which is considered to cause a problem of poor pattern.
- the present inventors have investigated the relationship between the surface of the electroless plating layer and the unexposed portion caused by foreign matter, and the relationship between the surface of the electroless plating layer and the fine circuit formability.
- the arithmetic mean waviness Wa on the surface of the electroless plating layer is 0.10 ⁇ m or more and 0.25 ⁇ m or less, and the void volume Vvv at the valley is 0.010 ⁇ m 3 / ⁇ m 2 or more and 0.028 ⁇ m 3 / ⁇ m.
- the present invention has been made by finding that when the number is 2 or less, pattern defects can be effectively suppressed and a fine circuit can be formed satisfactorily.
- the void volume Vvv of the valley portion on the surface of the electroless plating layer 22 is 0.028 ⁇ m 3 / ⁇ m 2.
- the valley of the unevenness on the surface of the electroless plating layer 22 becomes shallow. Therefore, the exposure incident light I can be diffusely reflected in the shallow valley on the surface of the electroless plating layer 22, and the light intensity of the exposure reflected light R is kept strong.
- the exposure incident light I can be diffusely reflected with strong light intensity. I can say.
- the exposure reflected light R can effectively expose the portion of the photoresist 24 (for example, the dry film resist 24a) directly under the foreign matter F. In this way, the formation of the unexposed portion of the photoresist 24 due to the foreign matter F is effectively prevented (see FIG. 5 (iii)), and the formation of unnecessary holes H due to development is suppressed (FIG. 5 (FIG. 5). iv) see).
- the problem of poor pattern such as short circuit or convex portion is less likely to occur in the circuit.
- the etching property for the electroless plating layer 22 tends to decrease.
- the thickness of the electroless plating layer 22 is formed as thin as less than 1.0 ⁇ m, and the arithmetic mean waviness Wa on the surface of the electroless plating layer 22 is set to 0.25 ⁇ m or less, which is good for the electroless plating layer 22. It is considered that a good etching property can be ensured and the fine circuit formability can be improved.
- the surface of the electroless plating layer 22 has an arithmetic mean waviness Wa of 0.10 ⁇ m or more and 0.25 ⁇ m or less, preferably 0.20 ⁇ m or more and 0.25 ⁇ m or less.
- the void volume Vvv of the valley portion is 0.010 ⁇ m 3 / ⁇ m 2 or more and 0.028 ⁇ m 3 / ⁇ m 2 or less, preferably 0.017 ⁇ m 3 / ⁇ m 2 or more and 0.025 ⁇ m. It is 3 / ⁇ m 2 or less.
- the surface of the electroless plating layer 22 preferably has a Kurtosis Sku of 2.0 or more and 3.5 or less, and more preferably 3.0 or more and 3.5 or less. By doing so, the sharpness of the valleys of the unevenness on the surface of the electroless plating layer 22 is suppressed, and as a result, the light intensity of the exposure reflected light R can be kept stronger, and the fine circuit formability is further improved. Can be improved.
- the electroless plating layer 22 having the above-mentioned unique surface parameters can be formed by applying electroless plating on the roughened surface 20a of the insulating base material 20 with a thickness of less than 1.0 ⁇ m. As described above, it can be said that the surface shape of the electroless plating layer 22 largely reflects the surface shape of the roughened surface 20a of the insulating base material 20.
- the roughened surface 20a can be preferably formed, for example, by transferring the surface shape of the surface-treated copper foil 10 having the surface parameters described in (a) above to the insulating base material 20.
- the thickness of the electroless plating layer 22 is less than 1.0 ⁇ m, preferably 0.3 ⁇ m or more and less than 1.0 ⁇ m. With such a thickness, it is possible to reduce the amount of etching at the time of forming the wiring pattern, and it is extremely suitable for forming a fine circuit.
- the photoresist 24 is laminated on the surface of the electroless plating layer 22.
- the laminating speed when laminating the photoresist 24 is not particularly limited, but is typically 1.0 m / min or more and 2.0 m / min or less.
- the photoresist 24 a known material generally used for manufacturing a printed wiring board can be used.
- the photoresist 24 may be either a negative type or a positive type, and may be a film type or a liquid type.
- the photoresist 24 comprises a dry film resist 24a.
- the photoresist 24 is preferably a photosensitive film, for example, a photosensitive dry film. As shown in FIG.
- the photoresist 24 may be a dry film resist 24a as a photosensitive layer on which a support film 24b such as a polyethylene terephthalate (PET) film is further laminated.
- the thickness of the photoresist 24 or the dry film resist 24a is preferably 2 ⁇ m or more and 35 ⁇ m or less, and more preferably 5 ⁇ m or more and 24 ⁇ m or less.
- the resist pattern 26 is formed by exposing and developing the photoresist 24.
- the exposure and development may be performed according to known methods and conditions generally used for manufacturing a printed wiring board, and are not particularly limited.
- a direct drawing exposure method such as a Laser Direct Imaging (LDI) exposure method or a Digital Light Processing (DLP) exposure method can be adopted.
- the exposure amount at the time of exposure is preferably 5 mJ / cm 2 or more and 150 mJ / cm 2 or less.
- the developing method may be either wet development or dry development.
- the developer used may be a developer such as sodium carbonate, sodium hydroxide, or an amine-based aqueous solution.
- the photoresist 24 contains the support film 24b, it is preferable to perform the development after removing the support film 24b.
- Electroplating for example, electrolytic copper plating
- the electroplating layer 28 can be formed between the resist patterns 26.
- the electroplating is not particularly limited as long as it is performed according to various pattern plating methods and conditions generally used for producing a printed wiring board such as a copper sulfate plating solution or a copper pyrophosphate plating solution.
- the resist pattern 26 is peeled off.
- the electroplating layer 28 remains in the wiring pattern, and the unnecessary portion of the electroless plating layer 22 that does not form the wiring pattern is exposed.
- the peeling of the resist pattern 26 is not particularly limited as long as an aqueous solution of sodium hydroxide, an amine solution or an aqueous solution thereof or the like is adopted and it is carried out according to various peeling methods and conditions generally used for printed wiring boards.
- (G) Formation of Wiring Pattern An unnecessary portion (that is, a portion that does not form a wiring pattern) of the electroless plating layer 22 exposed by peeling of the resist pattern 26 is removed by etching to form a wiring pattern 30.
- Etching of the unnecessary portion of the electroless plating layer 22 may be performed according to an etching method and conditions generally used for manufacturing a printed wiring board using, for example, a sulfuric acid-hydrogen peroxide-based etching solution, and is not particularly limited.
- the thickness of the wiring pattern 30 (that is, the circuit height) is preferably 2 ⁇ m or more and 30 ⁇ m or less.
- a circuit on the electroless plating layer 22 having a thickness of less than 1.0 ⁇ m having the above-mentioned predetermined surface parameters, it is possible to form such a highly miniaturized wiring pattern.
- the wiring pattern of the wiring pitch within the above range tends to cause a problem of pattern defect such as short circuit or occurrence of a convex portion, but as described above, the method of the present invention effectively solves such a problem. be able to.
- an insulating layer and an nth wiring pattern may be alternately formed on the wiring pattern 30 to form a multilayer wiring board.
- Each wiring pattern constituting the multilayer wiring board can be referred to as a second wiring pattern, a third wiring pattern, ..., Nth wiring pattern, with the wiring pattern 30 as the first wiring pattern.
- the sequential laminated structure composed of the first wiring pattern, the nth wiring pattern, and the insulating layer is generally referred to as a build-up layer or a build-up wiring layer.
- the construction method for forming the build-up layer after the second wiring pattern is not particularly limited, and in addition to the SAP method described above, a modified semi-additive method (MSAP method), a full additive method, a subtractive method, and the like can be used. .. Further, a solder resist, bumps for mounting pillars and the like may be formed on the wiring pattern on the outermost surface of the build-up layer, if necessary. In any case, a known construction method generally adopted for a printed wiring board can be additionally performed as appropriate, and is not particularly limited.
- Examples 1-6 Six types of surface-treated copper foils were prepared, and the surface shape was transferred to an insulating base material using the surface-treated copper foils. The roughened surface of the obtained insulating base material was electroless plated to prepare a laminate for evaluation, and various evaluations were performed. Specifically, it is as follows.
- Maximum height Sz and valley void volume Vvv Using a laser microscope (Keyence Co., Ltd., VK-X200), using a 150x objective lens, magnification 3000x, waviness removal (strength 5), no noise removal by DCL / BCL, S filter (0.
- the maximum height Sz of the copper foil surface and the void volume Vvv of the valley were measured in accordance with ISO25178 under the conditions of the evaluation region 6811.801 ⁇ m 2 with a cutoff by 25 ⁇ m) and an L filter (0.025 mm).
- the surface-treated copper foil 10 of the copper-clad laminate 12 was completely removed with a sulfuric acid-hydrogen peroxide-based etching solution to obtain an insulating base material 20 having a roughened surface 20a to which the surface shape of the treated surface 10a was transferred.
- Electroless copper plating solution (manufactured by Uemura Kogyo Co., Ltd., Sulcup PEA) is used to perform electroless copper plating on the insulating base material 20, and electroless plating with a thickness of 0.7 ⁇ m is performed on the roughened surface 20a side.
- Layer 22 was formed. In this way, a laminate immediately before the photoresist was laminated in the SAP method (hereinafter referred to as an evaluation laminate) was obtained.
- the glass mask 25 has circular light-shielding portions B (diameters 6 ⁇ m, 7 ⁇ m, 8 ⁇ m, 9 ⁇ m, 200 pieces each) in the center of each region partitioned by 100 ⁇ m ⁇ 100 ⁇ m, assuming foreign matter such as dust. It is provided. Therefore, the portion of the glass mask 25 where the light-shielding portion B is not provided allows light to pass through, while the portion of the glass mask 25 where the light-shielding portion B is provided does not transmit light.
- the evaluation laminate after laminating the glass mask 25 was exposed (70 mJ / cm 2 ) and developed to form a resist pattern 26.
- the surface of the resist pattern 26 side of the evaluation laminate after development was observed with a digital microscope (DSX510 manufactured by Olympus Corporation) under the condition of a magnification of 50 times, and as shown in FIG. 6 (ii), the resist pattern
- the number of holes H formed in 26 was counted and used as the number of dust detected.
- Table 1 It can be said that the larger the number of dust detected (that is, the better the resolution), the higher the possibility that unnecessary electroplating is applied to the portion where the circuit should not be formed, and the more likely the pattern defect is to occur.
- the evaluation laminate after the resist pattern 26 was formed was electroplated under known conditions to form an electroplating layer 28 between the resist patterns 26.
- the resist pattern 26 is peeled off from the evaluation laminate after the electroplating layer 28 is formed, and the exposed unnecessary portion of the electroless plating layer 22 is removed by etching with a sulfuric acid-hydrogen peroxide-based etching solution.
- a wiring pattern 30 having a circuit height of 11 ⁇ m was formed.
- the etching amount at this time was performed under the so-called over-etching condition in which the etching rate of the electroless plating layer 22 was measured in advance and 0.3 ⁇ m equivalent was etched further than the so-called just etching (0.7 ⁇ m equivalent). ..
- the circuit width of the wiring pattern 30 thus obtained was observed by SEM under the condition of a magnification of 5000 times. This circuit width was determined by measuring the circuit top width of the wiring pattern 30 in one field of view of the SEM at 10-point intervals at 1 ⁇ m intervals and calculating the average value thereof. The obtained circuit width was evaluated according to the following criteria. The results were as shown in Table 1. -Evaluation A: 6.6 ⁇ m or more-Evaluation B: 5.6 ⁇ m or more and less than 6.6 ⁇ m-Evaluation C: 4.6 ⁇ m or more and less than 5.6 ⁇ m-Evaluation D: Less than 4.6 ⁇ m
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Abstract
Description
(a)粗化面を備えた絶縁基材を準備する工程と、
(b)前記絶縁基材の粗化面に無電解めっきを行って、JIS B0601-2001に準拠して測定される算術平均うねりWaが0.10μm以上0.25μm以下であり、かつ、ISO25178に準拠して測定される谷部の空隙容積Vvvが0.010μm3/μm2以上0.028μm3/μm2以下である表面を有する、厚さ1.0μm未満の無電解めっき層を形成する工程と、
(c)前記無電解めっき層の表面にフォトレジストを積層する工程と、
(d)前記フォトレジストに露光及び現像を行って、レジストパターンを形成する工程と、
(e)前記レジストパターンを介して前記無電解めっき層に電気めっきを施す工程と、
(f)前記レジストパターンを剥離する工程と、
(g)前記レジストパターンの剥離により露出した前記無電解めっき層の不要部分をエッチングにより除去して、配線パターンを形成する工程と、
を含む、方法が提供される。
本発明を特定するために用いられるパラメータの定義を以下に示す。
本発明は、プリント配線板の製造方法に関する。本発明の方法は、(a)絶縁基材の準備、(b)無電解めっき層の形成、(c)フォトレジストの積層、(d)レジストパターンの形成、(e)電気めっき層の形成、(f)レジストパターンの剥離、及び(g)配線パターンの形成の各工程を含む。
図1(a)に示されるように、粗化面20aを備えた絶縁基材20を準備する。絶縁基材20は両側に粗化面20aを有するものであってもよいし、一方の側にのみ粗化面20aを有するものであってもよい。絶縁基材20は、好ましくは絶縁性樹脂を含む。また、絶縁基材20はプリプレグ及び/又は樹脂シートであるのが好ましい。プリプレグとは、合成樹脂板、ガラス板、ガラス織布、ガラス不織布、紙等の基材に合成樹脂を含浸させた複合材料の総称である。プリプレグに含浸される絶縁性樹脂の好ましい例としては、エポキシ樹脂、シアネート樹脂、ビスマレイミドトリアジン樹脂(BT樹脂)、ポリフェニレンエーテル樹脂、フェノール樹脂等が挙げられる。また、樹脂シートを構成する絶縁性樹脂の例としては、エポキシ樹脂、ポリイミド樹脂、ポリエステル樹脂等の絶縁樹脂が挙げられる。絶縁基材20には絶縁性を向上する等の観点からシリカ、アルミナ等の各種無機粒子からなるフィラー粒子等が含有されていてもよい。絶縁基材20の厚さは特に限定されないが、1μm以上1000μm以下が好ましく、より好ましくは2μm以上400μm以下であり、さらに好ましくは3μm以上200μm以下である。絶縁基材20は複数の層で構成されていてよい。
図3(a-1)に示されるように、少なくとも一方の側に処理表面10aを有する表面処理銅箔10を用意する。処理表面10aは何らかの表面処理が施されている面であり、典型的には粗化処理面である。処理表面10aは典型的には複数のコブ(例えば粗化粒子)を備えてなる。いずれにせよ、表面処理銅箔10は両側に処理表面10aを有するものであってもよいし、一方の側にのみ処理表面10aを有するものであってもよい。両側に処理表面10aを有する場合は、SAP法に用いた場合にレーザー照射側の面(絶縁基材に密着させる面と反対側の面)も表面処理されていることになるので、レーザー吸収性が高まる結果、レーザー穿孔性をも向上させることができる。また、表面処理銅箔10は、キャリア付銅箔の形態であってもよい。この場合、キャリア付銅箔は、キャリアと、このキャリア上に設けられた剥離層と、この剥離層上に処理表面10aを外側にして設けられた表面処理銅箔10とを備えてなるのが典型的である。もっとも、キャリア付銅箔は、表面処理銅箔10を用いること以外は、公知の層構成が採用可能である。
図3(a-2)に示されるように、表面処理銅箔10の処理表面10aに絶縁基材20’(すなわち粗化面20aが形成されていない絶縁基材20)を積層して、銅張積層板12とする。こうすることで、処理表面10aの表面形状を絶縁基材20’の表面に転写することができる。絶縁基材20’の積層は熱プレス加工を伴うのが好ましく、この熱プレス加工の加工温度及び加工時間は、積層する絶縁基材20’の種類等に応じて、公知の条件に基づき適宜決定することができる。絶縁基材20’の好ましい種類等については絶縁基材20に関して上述したとおりである。なお、絶縁基材20’は予め表面処理銅箔10の処理表面10aに塗布されるプライマー層(図示せず)を介して表面処理銅箔10に積層されてもよい。この場合、プライマー層は絶縁基材の一部を構成するものとみなす。プライマー層は樹脂で構成されるのが好ましく、この樹脂は絶縁性樹脂を含むのが好ましい。所望により、次工程である表面処理銅箔10の除去に先立ち、銅張積層板12に対して、レーザー穿孔によりビアホール(図示せず)を形成してもよい。
図3(a-3)に示されるように、銅張積層板12の表面処理銅箔10をエッチングにより除去して、粗化面20aを備えた絶縁基材20を得る。表面処理銅箔10のエッチングは、例えば硫酸-過酸化水素系のエッチング液等を用いてプリント配線板の製造に一般的に用いられるエッチング手法及び条件に従い行えばよく、特に限定されない。
図1(b)に示されるように、絶縁基材20の粗化面20aに無電解めっき(例えば無電解銅めっき)を行って、厚さ1.0μm未満の無電解めっき層22を形成する。無電解めっきは、市販の無電解めっき液を用いてプリント配線板の製造に一般的に用いられる手法及び条件に従い行えばよく、特に限定されない。無電解めっき層22表面は、算術平均うねりWaが0.10μm以上0.25μm以下であり、かつ、谷部の空隙容積Vvvが0.010μm3/μm2以上0.028μm3/μm2以下である。このように、粗化面20aを備えた絶縁基材20に無電解めっきを施して、上記所定の表面パラメータを有する厚さ1.0μm未満の無電解めっき層22を形成することにより、パターン不良を効果的に抑制し、かつ、微細回路形成性にも優れた、プリント配線板の製造方法を提供することができる。
図1(c)に示されるように、無電解めっき層22の表面にフォトレジスト24を積層する。フォトレジスト24を積層する際のラミネート速度は特に限定されるものではないが、典型的には1.0m/分以上2.0m/分以下である。フォトレジスト24はプリント配線板の製造に一般的に用いられる公知の材料が使用可能である。フォトレジスト24はネガ型及びポジ型のいずれであってもよく、フィルムタイプ及び液状タイプのいずれであってもよい。好ましくは、フォトレジスト24がドライフィルムレジスト24aを含む。また、フォトレジスト24は感光性フィルムであるのが好ましく、例えば感光性ドライフィルムである。図1(c)に示されるように、フォトレジスト24は、感光層としてのドライフィルムレジスト24a上にポリエチレンテレフタレート(PET)フィルム等の支持フィルム24bがさらに積層されたものであってもよい。フォトレジスト24ないしドライフィルムレジスト24aの厚さは2μm以上35μm以下であるのが好ましく、より好ましくは5μm以上24μm以下である。
図2(d)に示されるように、フォトレジスト24に露光及び現像を行うことにより、レジストパターン26を形成する。露光及び現像は、プリント配線板の製造に一般的に用いられる公知の手法及び条件に従い行えばよく、特に限定されない。例えば、露光方法として、ネガ又はポジ用マスクパターンを用いるマスク露光法の他、Laser Direct Imaging(LDI)露光法やDigital Light Processing(DLP)露光法といった直接描画露光法等を採用することができる。露光時における露光量は5mJ/cm2以上150mJ/cm2以下であるのが好ましい。一方、現像方法としては、ウェット現像及びドライ現像のいずれであってもよい。ウェット現像の場合、用いる現像液としては炭酸ナトリウム、水酸化ナトリウム、アミン系水溶液等の現像液であってよい。なお、フォトレジスト24が支持フィルム24bを含む場合には、支持フィルム24bを除去した後に現像を行うのが好ましい。
レジストパターン26を介して無電解めっき層22に電気めっき(例えば電気銅めっき)を施す。こうすることで、図2(e)に示されるように、レジストパターン26間に電気めっき層28を形成することができる。電気めっきは、例えば硫酸銅めっき液やピロリン酸銅めっき液等のプリント配線板の製造に一般的に用いられる各種パターンめっき手法及び条件に従い行えばよく特に限定されない。
この工程では、レジストパターン26を剥離する。その結果、図2(f)に示されるように、電気めっき層28が配線パターン状に残り、無電解めっき層22の配線パターンを形成しない不要部分が露出することになる。レジストパターン26の剥離は、水酸化ナトリウム水溶液や、アミン系溶液ないしその水溶液等が採用され、プリント配線板の一般的に用いられる各種剥離手法及び条件に従い行えばよく特に限定されない。
レジストパターン26の剥離により露出した無電解めっき層22の不要部分(すなわち配線パターンを形成しない部分)をエッチングにより除去して、配線パターン30を形成する。無電解めっき層22の不要部分のエッチングは、例えば硫酸-過酸化水素系のエッチング液等を用いてプリント配線板の製造に一般的に用いられるエッチング手法及び条件に従い行えばよく、特に限定されない。配線パターン30の厚さ(すなわち回路高さ)は2μm以上30μm以下が好ましい。配線パターン30の配線ピッチは10μm(例えばライン/スペース=5μm/5μm)から20μm(例えばライン/スペース=10μm/10μm)までの範囲内であるのが好ましい。前述した所定の表面パラメータを有する厚さ1.0μm未満の無電解めっき層22上に回路形成を行うことで、このように高度に微細化された配線パターンを形成することが可能となる。また、上記範囲内の配線ピッチの配線パターンは、ショートや凸部の発生といったパターン不良の問題が生じやすいといえるが、前述したとおり、本発明の方法によればかかる問題を効果的に解消することができる。
表面処理銅箔を6種類用意し、この表面処理銅箔を用いて絶縁基材に表面形状を転写した。得られた絶縁基材の粗化面に無電解めっきを施して評価用積層体を作製し、各種評価を行った。具体的には、以下のとおりである。
表1に示される各パラメータを有する処理表面10aを少なくとも一方の面に備えた表面処理銅箔10を6種類用意した。これらの表面処理銅箔10のうち幾つかは市販品であり、その他は公知の方法に基づき別途作製したものである。用意した表面処理銅箔10の処理表面10aにおける各パラメータの測定ないし算出方法は以下のとおりである。
レーザー顕微鏡(株式会社キーエンス製、VK-X200)を用い、150倍の対物レンズを使用し、倍率3000倍、傾き補正あり、DCL/BCLによるノイズ除去あり、カットオフなし、評価長さ64.124μmの条件で、JIS B0601-2001に準拠して銅箔表面の算術平均うねりWaを測定した。
レーザー顕微鏡(株式会社キーエンス製、VK-X200)を用い、150倍の対物レンズを使用し、倍率3000倍、うねり除去あり(強さ5)、DCL/BCLによるノイズ除去なし 、Sフィルター(0.25μm)及びLフィルター(0.025mm)によるカットオフあり、評価領域6811.801μm2の条件で、ISO25178に準拠して銅箔表面の最大高さSz及び谷部の空隙容積Vvvを測定した。
プリプレグ(三菱瓦斯化学株式会社製、GHPL-830NSF、厚さ100μm)を2枚積層した後、図3に示されるように、この絶縁基材20’に上記(1)で用意した表面処理銅箔10を、処理表面10aが当接するように積層し、プレス温度220℃、プレス時間90分、プレス圧力40kgf/cm2の条件でプレスを行って、銅張積層板12を得た。この銅張積層板12の表面処理銅箔10を硫酸-過酸化水素系エッチング液ですべて除去し、処理表面10aの表面形状が転写された粗化面20aを有する絶縁基材20を得た。この絶縁基材20に対して、無電解銅めっき液(上村工業株式会社製、スルカップPEA)を使用して無電解銅めっきを行い、粗化面20a側に厚さ0.7μmの無電解めっき層22を形成した。こうして、SAP法においてフォトレジストが積層される直前の積層体(以下、評価用積層体という)を得た。
上記得られた評価用積層体の無電解めっき層22側表面における、各パラメータの測定を以下のとおり行った。結果は表1に示されるとおりであった。
レーザー顕微鏡(株式会社キーエンス製、VK-X200)を用い、150倍の対物レンズを使用し、倍率3000倍、傾き補正あり、DCL/BCLによるノイズ除去あり、カットオフなし、評価長さ64.124μmの条件で、JIS B0601-2001に準拠して評価用積層体の無電解めっき層22側表面の算術平均うねりWaを測定した。
レーザー顕微鏡(株式会社キーエンス製、VK-X200)を用い、150倍の対物レンズを使用し、倍率3000倍、うねり除去あり(強さ5)、DCL/BCLによるノイズ除去なし、Sフィルター(0.25μm)及びLフィルター(0.025mm)によるカットオフあり、評価領域6811.801μm2の条件で、ISO25178に準拠して評価用積層体の無電解めっき層22側表面のクルトシスSku及び谷部の空隙容積Vvvを測定した。
上記得られた評価用積層体について、各種特性の評価を以下のとおり行った。
ゴミ検出数の評価を次のようにして行った。まず、上記得られた評価用積層体の無電解めっき層22側表面に厚さ19μmのネガ型フォトレジスト24(日立化成株式会社製、RY-5319)を1.5m/分のラミネート速度で積層し、その後、図6(i)に示されるように、フォトレジスト24の表面にガラスマスク25を積層した。なお、ガラスマスク25には、100μm×100μmで区画される各領域の中心部に、ゴミ等の異物を想定した円形状の遮光部B(直径6μm、7μm、8μm又は9μm、各200個)が設けられている。このため、ガラスマスク25の遮光部Bが設けられていない部分は光が透過する一方、ガラスマスク25の遮光部Bが設けられた部分は光が透過しないものとなっている。ガラスマスク25積層後の評価用積層体に対して、露光(70mJ/cm2)及び現像を行って、レジストパターン26を形成した。現像後の評価用積層体のレジストパターン26側の表面を倍率50倍の条件でデジタルマイクロスコープ(オリンパス株式会社製、DSX510)にて観察し、図6(ii)に示されるように、レジストパターン26に形成された穴Hの個数をカウントし、ゴミ検出数とした。結果は、表1に示されるとおりであった。なお、ゴミ検出数が多い(すなわち解像性が良い)ほど、本来回路が形成されるべきでない箇所に不要な電気めっきが施されるおそれが高く、パターン不良が発生しやすいといえる。
回路形成性の評価を次のようにして行った。図1に示されるように、上記得られた評価用積層体の無電解めっき層22側表面に厚さ15μmのネガ型フォトレジスト24(旭化成株式会社製、UFG-155)を1.5m/分のラミネート速度で積層し、その後、狙いの回路幅が7μmとなるように、フォトレジスト24上にライン/スペース(L/S)=9μm/6μmのマスクを積層した。図2に示されるように、マスク積層後の評価用積層体に対して、露光(70mJ/cm2)及び現像を行い、レジストパターン26を形成した。レジストパターン26形成後の評価用積層体に対して、公知の条件で電気銅めっきを行い、レジストパターン26間に電気めっき層28を形成した。電気めっき層28形成後の評価用積層体に対して、レジストパターン26の剥離を行い、それにより露出した無電解めっき層22の不要部分を硫酸-過酸化水素系エッチング液を用いたエッチングにより除去して、回路高さ11μmの配線パターン30を形成した。このときのエッチング量は、予め無電解めっき層22のエッチング速度を測定しておき、いわゆるジャストエッチング(0.7μm相当)よりもさらに0.3μm相当をエッチングする、いわゆるオーバーエッチングの条件で行った。こうして得られた配線パターン30の回路幅を、倍率5000倍の条件でSEMにて観察した。この回路幅は、SEMの1視野内における配線パターン30の回路トップ幅を1μm間隔で10点測長し、それらの平均値を算出することにより決定した。得られた回路幅を以下の基準に従い評価した。結果は、表1に示されるとおりであった。
‐評価A:6.6μm以上
‐評価B:5.6μm以上6.6μm未満
‐評価C:4.6μm以上5.6μm未満
‐評価D:4.6μm未満
Claims (8)
- プリント配線板の製造方法であって、
(a)粗化面を備えた絶縁基材を準備する工程と、
(b)前記絶縁基材の粗化面に無電解めっきを行って、JIS B0601-2001に準拠して測定される算術平均うねりWaが0.10μm以上0.25μm以下であり、かつ、ISO25178に準拠して測定される谷部の空隙容積Vvvが0.010μm3/μm2以上0.028μm3/μm2以下である表面を有する、厚さ1.0μm未満の無電解めっき層を形成する工程と、
(c)前記無電解めっき層の表面にフォトレジストを積層する工程と、
(d)前記フォトレジストに露光及び現像を行って、レジストパターンを形成する工程と、
(e)前記レジストパターンを介して前記無電解めっき層に電気めっきを施す工程と、
(f)前記レジストパターンを剥離する工程と、
(g)前記レジストパターンの剥離により露出した前記無電解めっき層の不要部分をエッチングにより除去して、配線パターンを形成する工程と、
を含む、方法。 - 前記工程(a)が、
(a-1)JIS B0601-2001に準拠して測定される算術平均うねりWaが0.20μm以上0.35μm以下であり、かつ、ISO25178に準拠して測定される谷部の空隙容積Vvvが0.030μm3/μm2以上0.050μm3/μm2以下である処理表面を有する、表面処理銅箔を用意し、
(a-2)前記表面処理銅箔の前記処理表面に絶縁基材を積層して、前記処理表面の表面形状を前記絶縁基材の表面に転写した後、
(a-3)エッチングにより前記表面処理銅箔を除去して、前記粗化面を備えた絶縁基材を得ること
を含む、請求項1に記載の方法。 - 前記無電解めっき層の表面における、前記算術平均うねりWaが0.20μm以上0.25μm以下である、請求項1又は2に記載の方法。
- 前記無電解めっき層の表面における、前記谷部の空隙容積Vvvが0.017μm3/μm2以上0.025μm3/μm2以下である、請求項1~3のいずれか一項に記載の方法。
- 前記無電解めっき層の厚さが0.3μm以上1.0μm未満である、請求項1~4のいずれか一項に記載の方法。
- 前記フォトレジストがドライフィルムレジストを含む、請求項1~5のいずれか一項に記載の方法。
- 前記ドライフィルムレジストの厚さが2μm以上35μm以下である、請求項6に記載の方法。
- 前記配線パターンの厚さが2μm以上30μm以下である、請求項1~7のいずれか一項に記載の方法。
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