WO2020192476A1 - Multi-path selection circuit and driving method, and multi-path selection unit and display apparatus - Google Patents
Multi-path selection circuit and driving method, and multi-path selection unit and display apparatus Download PDFInfo
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- WO2020192476A1 WO2020192476A1 PCT/CN2020/079561 CN2020079561W WO2020192476A1 WO 2020192476 A1 WO2020192476 A1 WO 2020192476A1 CN 2020079561 W CN2020079561 W CN 2020079561W WO 2020192476 A1 WO2020192476 A1 WO 2020192476A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
Definitions
- the present disclosure relates to the field of display technology, and in particular to a multiplex selection circuit and driving method, multiplex selection unit, and display device.
- a plurality of sub-pixels are arranged inside the display device, and the screen display is realized by controlling the display of the sub-pixels.
- each sub-pixel of the display device is provided with a pixel circuit for controlling the sub-pixel to display, and the pixel circuit controls the sub-pixel display under the control of the scan signal provided by the gate line and the data signal provided by the data line.
- the multiple selection circuit includes a charging sub-circuit, a control sub-circuit and a delay sub-circuit.
- the charging sub-circuit is respectively coupled to the selection signal terminal, the data signal terminal and the sub-pixel to be charged, and the charging sub-circuit is configured to, under the control of the signal received at the selection signal terminal, load the data
- the signal received at the signal terminal is transmitted to the sub-pixel to be charged;
- the control sub-circuit is respectively coupled to the selection signal terminal and the data signal terminal, and the control sub-circuit is configured to: Under the control of the signal received at the terminal, the signal received at the data signal terminal is transmitted;
- the delay sub-circuit is respectively coupled to the sub-pixel to be charged and the control sub-circuit, the delay sub-circuit Is configured to delay the transmission of the signal received at the data signal terminal transmitted through the control sub-circuit, and after the charging sub-circuit charges the sub-pixel to be charged for a preset time, the data
- the delay sub-circuit includes: a third transistor, a fourth transistor and a first capacitor.
- the control electrode of the third transistor is coupled to the control signal terminal, the first electrode of the third transistor is coupled to the control sub-circuit; the control electrode of the fourth transistor is connected to the second terminal of the third transistor.
- the first electrode of the fourth transistor is coupled to the control sub-circuit, and the second electrode of the fourth transistor is coupled to the sub-pixel to be charged; the first terminal of the first capacitor Are respectively coupled to the control sub-circuit, the first pole of the third transistor and the first pole of the fourth transistor, and the second terminal of the first capacitor is coupled to the first voltage terminal.
- the aspect ratio of the channel of the fourth transistor is greater than the aspect ratio of the channel of the third transistor.
- the delay sub-circuit further includes a second capacitor.
- the first terminal of the second capacitor is respectively coupled to the second electrode of the fourth transistor and the sub-pixel to be charged, and the second terminal of the second capacitor is coupled to the first voltage terminal.
- control sub-circuit includes a second transistor.
- the control electrode of the second transistor is coupled to the selection signal terminal, the first electrode of the second transistor is coupled to the data signal terminal, and the second electrode of the second transistor is coupled to the delay element. Circuit coupling.
- the charging sub-circuit includes a first transistor.
- the control electrode of the first transistor is coupled to the selection signal terminal, the first electrode of the first transistor is coupled to the data signal terminal, and the second electrode of the first transistor is connected to the sub-to-be-charged. Pixel coupling.
- the multiple selection circuit further includes a storage sub-circuit.
- the storage sub-circuit is respectively coupled to the charging sub-circuit, the sub-pixel to be charged and the first voltage terminal, and the storage sub-circuit is configured to transmit data to the charging sub-circuit at the data signal terminal Storing the signal received there, and transmitting the stored signal to the sub-pixel to be charged.
- the storage sub-circuit includes a third capacitor.
- the first terminal of the third capacitor is respectively coupled to the charging sub-circuit and the sub-pixel to be charged, and the second terminal of the third capacitor is coupled to the first voltage terminal.
- the multiple selection unit includes: at least one multiple selection group.
- the multiple selection group includes a plurality of multiple selection circuits as described in any of the foregoing embodiments; each of the multiple selection circuits in the multiple selection unit is coupled to a different selection signal terminal.
- the light-emitting colors of the sub-pixels to be charged coupled to each multiplex selection circuit in the multiplex selection group are different.
- a plurality of the multiple selection circuits in the multiple selection unit are coupled to the same data signal terminal.
- the multiplexing unit includes two multiplexing groups, and the multiplexing group includes three multiplexing circuits.
- one of the two multiplexer groups is coupled to the sub-pixels of the odd-numbered columns of pixels, and the other multiplexer group is coupled to the sub-pixels of the even-numbered columns of pixels.
- a display device in another aspect, includes at least one multiple selection unit and a display panel as described in any of the above embodiments.
- the display panel includes a base substrate; the multiple selection unit is arranged on the base substrate.
- the display device further includes a source driver and at least one data signal transmission channel.
- the source driver is bound to the base substrate, and is coupled to each of the multiple selection units; the data signal transmission channel is arranged on the base substrate, and one multiple selection unit passes through one The data transmission channel is coupled to the source driver.
- multiple data signal terminals are coupled to the source driver through one signal line.
- a method for driving a multiple selection circuit as described in any of the above embodiments includes: inputting a turn-on signal at the selection signal terminal, and the charging sub-circuit under the control of the signal received at the selection signal terminal, The signal received at the data signal terminal is transmitted to the sub-pixel to be charged; the control sub-circuit transmits the signal received at the data signal terminal under the control of the signal received at the selection signal terminal; the delay sub-circuit will The signal received at the data signal terminal transmitted through the control sub-circuit is delayed in transmission.
- the delay sub-circuit After the charging sub-circuit charges the sub-pixel to be charged for a preset time, the delay sub-circuit will The signal received at the data signal terminal is transmitted to the sub-pixel to be charged; the selection signal terminal inputs a cut-off signal, and the charging sub-circuit and the control sub-circuit cut off under the control of the signal received at the selection signal terminal , The delay sub-circuit continues to transmit the signal received at the data signal terminal to the sub-pixel to be charged.
- FIG. 1 is a structural diagram of a display device according to some embodiments.
- FIG. 2 is another structural diagram of a display device according to some embodiments.
- Fig. 3 is a structural diagram of a display device according to the related art
- FIG. 4 is another structural diagram of a display device according to the related art.
- Fig. 5 is a structural diagram of a multiple selection circuit according to some embodiments.
- Fig. 6 is another structural diagram of a multiple selection circuit according to some embodiments.
- FIG. 7 is another structural diagram of a multiple selection circuit according to some embodiments.
- Fig. 8 is another structural diagram of a multiple selection circuit according to some embodiments.
- Fig. 9 is a structural diagram of a multiple selection unit according to some embodiments.
- Fig. 10 is another structural diagram of a multiple selection unit according to some embodiments.
- FIG. 11 is another structural diagram of a multiple selection unit according to some embodiments.
- Fig. 12 is another structural diagram of a multiple selection unit according to some embodiments.
- FIG. 13 is a structural diagram of a display panel according to some embodiments.
- FIG. 14 is another structural diagram of a display panel according to some embodiments.
- FIG. 15 is another structural diagram of a display panel according to some embodiments.
- FIG. 16 is another structural diagram of a display device according to some embodiments.
- FIG. 17 is another structural diagram of a display device according to some embodiments.
- FIG. 18 is a driving timing diagram of the multiple selection unit according to some embodiments.
- Fig. 19 is a driving flowchart of a multiple selection unit according to some embodiments.
- first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
- the expressions “coupled” and “connected” and their extensions may be used.
- the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
- the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
- the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
- the embodiments disclosed herein are not necessarily limited to the content herein.
- At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
- azimuth terms such as “upper”, “lower”, “left”, “right”, “horizontal” and “vertical” are defined relative to the directions in which the components in the drawings are schematically placed. It should be understood that these directional terms are relative concepts, and they are used for relative description and clarification, which can be changed correspondingly according to the changes in the orientation of the components in the drawings.
- each data line DL in the display panel 10' needs to receive a data signal.
- the display panel 10' including 1080 columns of sub-pixels 20' as an example, there are 1080 data lines DL that need to receive data signals, and the source driver 01' (Source IC) that provides data signals for the data lines DL 1080 output ports are required, which leads to an increase in the manufacturing cost of the source driver 01' in the display device 200' and an increase in the occupied area.
- Source IC Source IC
- a multiplexer circuit 110' is usually used to convert the signals and charge the sub-pixels 20'.
- the multiple selection circuit 110' controls the levels of the red selection signal terminal MUXR, the green selection signal terminal MUXG, and the blue selection signal terminal MUXB so that the first thin film transistor M1 and the second thin film transistor M2 ,
- the third thin film transistor M3 is turned on sequentially, and sequentially transmits the signal of the data signal terminal Vs to realize charging of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B.
- Three sub-pixels located in the same pixel are connected to the same data signal terminal Vs. In this way, the number of output ports of the source driver 01' can be reduced to one third of the original number.
- FIG. 4 shows a scheme in which the multiple selection circuit 110' receives a signal through a data signal terminal Vs and charges 6 sub-pixels 20'.
- the selection signal terminal is turned on in turn, and the 6 sub-pixels 20' are sequentially charged, thereby reducing Source driver 01' cost and size to achieve a full screen with ultra-narrow bezel.
- the charging time required for each sub-pixel 20' is fixed. If the charging time of each sub-pixel 20 is reduced, the sub-pixel 20' will be undercharged. Affect the display effect.
- the total charging time of one data line DL is 3.6 us. If the multiplex circuit 110' receives a signal through a data signal terminal Vs, it charges three sub-pixels 20', and each sub-pixel 20' charges The time is 1.2us, which can also guarantee the normal display of the display device. However, if the multiplexer circuit 110' receives signals through a data signal terminal Vs and charges the 6 sub-pixels 20', the charging time of each sub-pixel 20' is 0.6us, and the charging time is reduced by half, resulting in sub-pixels If the charging is insufficient at 20', the display effect will deteriorate.
- the embodiment of the present disclosure provides a multiple selection circuit 110, as shown in FIG. 5, including: a charging sub-circuit 40, a control sub-circuit 50, and a delay sub-circuit 30.
- the charging sub-circuit 40 is respectively coupled to the selection signal terminal MUX, the data signal terminal Vs and the sub-pixel to be charged.
- the control sub-circuit 50 is respectively coupled to the selection signal terminal MUX and the data signal terminal Vs.
- the delay sub-circuit 30 is respectively coupled to the sub-pixel to be charged and the control sub-circuit 50.
- the charging sub-circuit 40 is configured to transmit the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged under the control of the signal received at the selection signal terminal MUX.
- the charging sub-circuit 40 actually transmits the signal received at the data signal terminal Vs to the pixel circuit to control the display of the sub-pixel pixel to be charged. Taking the pixel circuit 201 shown in FIG. 2 as an example, the charging sub-circuit 40 transmits the signal received at the data signal terminal Vs to the data line DL, and then to the first pole of the transistor M in the pixel circuit 201.
- the sub-pixel pixel to be charged may be any sub-pixel 20 in the display panel 10, for example, it may be a red sub-pixel R, a green sub-pixel G, or a blue sub-pixel B.
- the control sub-circuit 50 is configured to transmit the signal received at the data signal terminal Vs under the control of the signal received at the selection signal terminal MUX.
- control sub-circuit 50 is substantially equivalent to a switch, and any structure that can achieve the same effect as the control sub-circuit 50 belongs to the protection scope of the present application.
- the delay sub-circuit 30 is configured to delay the transmission of the signal received at the data signal terminal Vs transmitted through the control sub-circuit 50. After the charging sub-circuit 40 charges the sub-pixel pixel to be charged for a preset time, it will be at the data signal terminal. The signal received at Vs is transmitted to the sub-pixel pixel to be charged.
- the time that the delay sub-circuit 30 charges the sub-pixel pixel to be charged is delayed relative to the time that the charging sub-circuit 40 charges the sub-pixel pixel to be charged, and the delayed time is the preset time.
- the delay sub-circuit 30 starts charging the sub-pixel pixel to be charged the charging sub-circuit 40 has not finished charging the sub-pixel pixel to be charged, or when the delay sub-circuit 30 charges the sub-pixel pixel to be charged At the same time as the charging starts, the charging of the sub-pixel pixel to be charged by the charging sub-circuit 40 ends.
- the signal from the control sub-circuit 50 is the signal received by the control sub-circuit 50 at the data signal terminal Vs.
- the charging sub-circuit 40 transmits the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged, and at the same time, the control sub-circuit 50 will be at the data signal terminal
- the signal received at Vs is transmitted to the delay sub-circuit 30, but at this time, the delay sub-circuit 30 does not transmit the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged.
- the delay sub-circuit 30 transmits the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged.
- the charging sub-circuit 40 sends the The sub-pixel pixel charging is not over yet.
- the charging time of the charging sub-circuit 40 ends, under the control of the signal received at the selection signal terminal MUX, the charging sub-circuit 40 is closed, the charging sub-circuit 40 stops charging the sub-pixel pixel to be charged, and the control sub-circuit 50 stops at The signal received at the data signal terminal Vs is transmitted.
- the delay sub-circuit 30 continues to transmit the signal from the control sub-circuit 50, that is, the signal received at the data signal terminal Vs to the sub-pixel to be charged.
- the embodiment of the present disclosure does not limit the specific structure of the delay sub-circuit 30, and the sub-circuit structure capable of delaying signal transmission belongs to the protection scope of the present disclosure. Moreover, after the delay sub-circuit 30 delays the signal, the time that the sub-pixel pixel to be charged can continue to be charged is related to the specific structure of the delay sub-circuit 30 and can be set reasonably according to needs.
- the selection signal terminal MUX is turned on for 0.6us
- the delay sub-circuit 30 is configured so that the delay sub-circuit 30 delays the signal received at the data signal terminal Vs, and then charges the sub-pixel pixel to be charged.
- the time that can be continuously charged is also 0.6us. In this way, it takes 0.6us to charge each sub-pixel, but the effect achieved is the same as that of 1.2us.
- the charging sub-circuit 40 and the delay sub-circuit 30 are both used to transmit the data voltage signal to the sub-pixel pixel to be charged.
- the charging sub-circuit 40 and the delay sub-circuit 30 receive the signal on the data signal terminal Vs at the same time, they both transmit the signal of the data signal terminal Vs to the sub-pixel pixel to be charged at different times.
- the delay sub-circuit 30 Delay the signal transmission to the sub-pixel to be charged.
- the signal received at the selection signal terminal MUX controls the time for the charging sub-circuit 40 to turn on to be shortened, that is, when the charging sub-circuit 40 shortens the charging time of the sub-pixel pixel to be charged, the delay sub-circuit 30 delays the transmission of the data signal.
- the signal of the terminal Vs prolongs the charging time of the sub-pixel pixel to be charged, and ensures the charging effect of the sub-pixel pixel to be charged.
- the charging sub-circuit 40 and the delay sub-circuit 30 in the multiple selection circuit are used to charge the sub-pixel pixel to be charged, but both charge the sub-pixel pixel to be charged. The moments are different.
- the charging sub-circuit 40 is turned on under the control of the signal received at the selection signal terminal MUX.
- the charging sub-circuit 40 charges the sub-pixel pixel to be charged.
- the delay sub-circuit 30 is compared with the charging sub-circuit.
- the signal received by the delay sub-circuit 30 at the selection signal terminal MUX controls the charging sub-circuit 40 to disconnect, and then continues to charge the sub-pixel pixel to be charged. That is to say, when the next multiplexer circuit charges the next sub-pixel pixel to be charged, the delay sub-circuit 30 in the previous multiplexer circuit is still charging the next sub-pixel pixel to be charged, and the delay sub-circuit 30 Charging the sub-pixel pixel to be charged does not cause the total charging time to increase. Therefore, the multiple selection circuit provided by the embodiment of the present disclosure not only shortens the charging time of the sub-pixel pixel to be charged, but also ensures the charging effect of the sub-pixel pixel to be charged.
- the multiplexer circuit 100 When the multiplexer circuit is applied to a display device, the multiplexer circuit 100 is coupled to the output port of the source driver 01 through the data signal transmission channel, which can reduce the number of output ports of the source driver 01 and reduce the number of output ports of the source driver 01.
- the number of data signal transmission channels coupled to the output port of 01 does not affect the charging effect of each sub-pixel 20.
- the charging sub-circuit 40 includes a first transistor T1.
- the control electrode of the first transistor T1 is coupled to the selection signal terminal MUX, the first electrode of the first transistor T1 is coupled to the data signal terminal Vs, and the second electrode of the first transistor T1 is coupled to the sub-pixel pixel to be charged.
- the charging sub-circuit 40 may further include a plurality of switching transistors connected in parallel with the first transistor T1.
- control sub-circuit 50 includes a second transistor T2.
- the control electrode of the second transistor T2 is coupled to the selection signal terminal MUX, the first electrode of the second transistor T2 is coupled to the data signal terminal Vs, and the second electrode of the second transistor T2 is coupled to the delay sub-circuit 30.
- control sub-circuit 50 may further include a plurality of switching transistors connected in parallel with the second transistor T2.
- control sub-circuit 50 is only an example of the control sub-circuit 50, and other structures with the same function as the control sub-circuit 50 will not be repeated here, but they should all fall within the protection scope of the present disclosure.
- the delay sub-circuit 30 includes a third transistor T3, a fourth transistor T4 and a first capacitor C1.
- the control electrode of the third transistor T3 is coupled to the control signal terminal Vc, the first electrode of the third transistor T3 is coupled to the control sub-circuit 50, and the second electrode of the third transistor T3 is coupled to the control electrode of the fourth transistor T4.
- the first pole of the fourth transistor T4 is coupled to the control sub-circuit 50, and the second pole of the fourth transistor T4 is coupled to the sub-pixel to be charged.
- the first terminal of the first capacitor C1 is respectively coupled to the control sub-circuit 50, the first pole of the third transistor T3 and the first pole of the fourth transistor T4, and the second terminal of the first capacitor C1 is coupled to the first voltage terminal V1 Pick up.
- the signal received at the control signal terminal Vc is configured to control the third transistor T3 to turn on during the charging phase of the sub-pixel.
- the signal received at the control signal terminal Vc is a DC high-level signal.
- the aspect ratio of the channel of the fourth transistor T4 is greater than the aspect ratio of the channel of the third transistor T3.
- the on-resistance of the third transistor T3 in the linear region is smaller than the on-resistance of the fourth transistor T4 in the linear region.
- the control signal terminal Vc controls the turn-on of the third transistor T3, a part of the signal received at the data signal terminal Vs is transmitted to the control electrode of the fourth transistor T4 through the third transistor T3, and in the signal received at the data signal terminal Vs The other part of is transmitted to the first pole of the fourth transistor T4 to control the turning on of the fourth transistor T4, and the signal received at the data signal terminal Vs can be transmitted to the sub-pixel pixel to be charged through the fourth transistor T4 with a delay.
- the circuit zero point (that is, the delay time of the delay sub-circuit 30 is zero) can be adjusted.
- To control the delay time of the delay sub-circuit 30 transmitting the signal from the control sub-circuit 50 to the sub-pixel to be charged.
- Those skilled in the art can design the width-to-length ratio of the channel of the fourth transistor T4 and the width-to-length ratio of the channel of the third transistor T3 according to actual conditions, which are not limited in the embodiments of the present disclosure.
- the delay sub-circuit 30 further includes: a second capacitor C2.
- the first terminal of the second capacitor C2 is respectively coupled to the second electrode of the fourth transistor T4 and the sub-pixel pixel to be charged, and the second terminal of the second capacitor C2 is coupled to the first voltage terminal V1.
- the delay sub-circuit 30 may be a ⁇ -type delay circuit.
- the multiple selection circuit 110 further includes a storage sub-circuit 60.
- the storage sub-circuit 60 is respectively coupled to the charging sub-circuit 40, the sub-pixel pixel to be charged and the first voltage terminal V1.
- the first voltage terminal V1 in the embodiment of the present disclosure may be, for example, a ground terminal or a fixed voltage terminal.
- the signal received at the first voltage terminal V1 is a DC low-level signal.
- the storage sub-circuit 60 is configured to store the signal received at the data signal terminal Vs transmitted by the charging sub-circuit 40, and to transmit the stored signal to the sub-pixel pixel to be charged.
- the storage sub-circuit 60 can keep the signal transmitted to the sub-pixel pixel to be charged through the charging sub-circuit 40 stable, thereby improving the stability of charging the sub-pixel pixel to be charged.
- the storage sub-circuit 60 includes a third capacitor C3.
- the first terminal of the third capacitor C3 is respectively coupled to the charging sub-circuit 40 and the sub-pixel pixel to be charged, and the second terminal of the third capacitor C3 is coupled to the first voltage terminal V1.
- the first transistor T1 transmits the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged
- the third capacitor C3 stores the signal received at the data signal terminal Vs to improve the stability of the signal transmitted to the sub-pixel pixel to be charged through the first transistor T1.
- the second transistor T2 under the control of the signal received at the selection signal terminal MUX, the second transistor T2 is turned on and transmits the signal received at the data signal terminal Vs to the delay sub-circuit 30.
- the aspect ratio of the channel of the fourth transistor T4 is greater than the aspect ratio of the channel of the third transistor T3, the on-resistance of the third transistor T3 in the linear region is smaller than the on-resistance of the fourth transistor T4 in the linear region, and the control signal
- the terminal Vc controls the turn-on of the third transistor T3, and a part of the signal received at the data signal terminal Vs is transmitted to the control electrode of the fourth transistor T4 through the third transistor T3.
- the other part is transmitted to the first pole of the fourth transistor T4 to control the turning on of the fourth transistor T4.
- the signal received at the data signal terminal Vs can be transmitted to the sub-pixel to be charged through the fourth transistor T4 with a delay.
- the position of the circuit zero point (that is, the delay time of the delay sub-circuit 30 is zero) can be adjusted by adjusting the width to length ratio of the channel of the fourth transistor T4 and the width to length ratio of the channel of the third transistor T3, thereby The delay time can be controlled to delay the transmission of the signal at the data signal terminal Vs.
- the signal terminal MUX to be selected inputs a cut-off signal.
- the delay sub-circuit 30 just transmits the signal of the data signal terminal Vs to the sub-pixel pixel to be charged, and the sub-pixel pixel to be charged continues to be charged to extend the charging time of the sub-pixel pixel to be charged .
- the transistors used in the multiple selection circuit 110 may be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and the embodiments of the present disclosure are not limited thereto.
- the control electrode of each transistor used in the multiplexer circuit 110 is the gate of the transistor, one of the source and drain of the transistor on the first pole, and the other of the source and drain of the transistor on the second pole.
- the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable, that is, the first and second electrodes of the transistor in the embodiment of the present disclosure
- the two poles can be indistinguishable in structure.
- the transistor is a P-type transistor
- the first electrode of the transistor is a source and the second electrode is a drain; for example, when the transistor is an N-type transistor, the first electrode of the transistor is a drain,
- the second pole is the source.
- the specific implementation manners of the delay sub-circuit 30, the charging sub-circuit 40, the control sub-circuit 50, and the storage sub-circuit 60 are not limited to the above-described manner, which can be implemented arbitrarily.
- the method for example, a conventional connection method well known to those skilled in the art, only needs to ensure that the corresponding function is realized.
- the above examples do not limit the protection scope of the present disclosure.
- the skilled person can choose to use or not apply one or more of the above-mentioned circuits according to the situation.
- Various combinations and modifications based on the above-mentioned circuits do not deviate from the principle of the present disclosure, and will not be repeated here.
- the embodiment of the present disclosure provides a multiple selection unit 11. As shown in FIGS. 9 to 12, the multiple selection unit 11 includes at least one multiple selection group, and each multiple selection group includes a plurality of the above multiple selections. Circuit.
- each multiplexing circuit in the multiplexing unit 11 is coupled to a different selection signal terminal MUX.
- Figs. 11 and 12 take the multiple selection unit 11 including two multiple selection groups as an example.
- the multiple sub-pixels to be charged are arranged in a matrix as an example.
- the sub-pixels in the same row can be coupled to one gate line GL, and the sub-pixels in the same column can be coupled to one data line DL.
- at least one column of sub-pixels is coupled to the same data signal terminal Vs.
- R1 and R2 represent red sub-pixels to be charged in different columns
- G1 and G2 represent green sub-pixels to be charged in different columns
- B1 and B2 represent blue sub-pixels to be charged in different columns.
- the pixels in the display panel 10 are divided into odd-numbered columns and even-numbered columns.
- R1 represents the red sub-pixel to be charged in the pixels in the odd-numbered column
- G1 represents the green sub-pixel to be charged in the pixels in the odd-numbered column.
- B1 represents the blue sub-pixel to be charged in the pixel in the odd column
- R2 represents the red sub-pixel to be charged in the pixel in the even column
- G2 represents the green sub-pixel to be charged in the pixel in the even column
- B2 represents the The blue sub-pixels to be charged among the pixels in the even columns.
- one selection voltage terminal Vs is configured to A sub-pixel to be charged is charged.
- one data signal terminal Vs is configured to Six sub-pixels to be charged are charged.
- each multiple selection circuit connected to the sub-pixel pixel to be charged has a different light emission color; each multiple selection circuit in the multiple selection unit 11 is connected to a different selection Signal terminal MUX.
- the multiple selection unit 11 includes the number of multiple selection groups is not limited to two or three, and the number of multiple selection circuits included in each multiple selection group is also It is not limited to three, and Figs. 9-12 are only an illustration.
- the sub-pixels to be charged that are coupled to some of the multiplexer circuits in the same multiplexer group emit the same color.
- the light-emitting colors of the sub-pixel pixels to be charged coupled to the two multiplexer circuits in the same multiplexer group are the same; or, in one column
- the pixel includes sub-pixels of multiple light-emitting colors, among the sub-pixels to be charged coupled to the multiple selection circuits in the same multiple selection group, some of the sub-pixels to be charged have the same light-emitting color.
- the sub-pixel pixels to be charged coupled to each multiplexer circuit in the same multiplexer group have different light-emitting colors, that is, there will not be two multiplexer options in a multiplexer group.
- the circuit is coupled to the sub-pixels to be charged for emitting the same color light. In this way, the number of multiple selection circuits included in a multiple selection group is less than or equal to the number of sub-pixels included in one pixel.
- one multiplex selection group corresponds to one pixel, that is, one multiplex selection group is configured to charge the sub-pixel pixels to be charged in the same pixel.
- a multiplex selection group corresponds to different pixels, that is, a multiplex selection group is configured to charge the sub-pixel pixels located in different pixels to be charged. In this case, the signal interference of different pixels can be avoided, and the charging quality can be improved.
- a dashed box in FIG. 15 represents a pixel.
- a multiple-way selection unit 11 includes a multiple-way selection group as an example for illustration.
- a multiplexing unit 11 includes three multiplexing circuits, one row includes three pixels, and the first multiplexing circuit in the multiplexing unit 11 directs the red sub-pixel R in the first pixel to be charged.
- the second multiplexer circuit charges the green sub-pixel G to be charged in the second pixel
- the third multiplexer circuit charges the blue sub-pixel B to be charged in the third pixel.
- multiple selection group and the pixel may also be in other corresponding manners, and the embodiments of the present disclosure are not limited herein.
- the multiple selection unit 11 provided by the embodiment of the present disclosure, whether it is one multiple selection unit 11 charging three sub-pixels to be charged, or one multiple selection unit 11 charging six sub-pixels to be charged, or Other quantities. Since each multiplex circuit in the multiplexer unit 11 achieves the same charging capacity, the required charging time is often relatively short. Therefore, when the above multiple selection circuit is applied to the multiple selection unit 11, the output ports of the source driver 01 (ie, the source driver IC) can be reduced, and the data signal transmission coupled to the output port of the source driver 01 can be reduced. The number of channels, and to ensure that each sub-pixel to be charged can be fully charged to ensure the display effect.
- multiple multiplexer circuits 110 in the multiplexer unit 11 are coupled to the same data signal terminal Vs.
- one multiplexing unit 11 corresponds to one data signal terminal Vs, and multiplexing circuits belonging to the same multiplexing unit 11 are coupled to the same data signal terminal Vs. Therefore, the number of data signal transmission channels coupled to the output port of the source driver 01 and the data signal terminal Vs of the multiplexer circuit 110 can be reduced.
- the multiplexing unit 11 includes two multiplexing groups, and the multiplexing group includes three multiplexing circuits 110.
- one multiplexing unit 11 is used to charge six sub-pixels to be charged.
- the embodiment of the present disclosure provides a display device 200, as shown in FIG. 16, comprising: a display panel 10 and at least one multiple selection unit 11 as in any of the above embodiments.
- the multiplexing unit 11 is arranged on the base substrate 102.
- the display panel 10 has an active display area (AA) 100 and a non-display area 101 located on at least one side of the active display area 100.
- AA active display area
- non-display area 101 located on at least one side of the active display area 100.
- the above-mentioned effective display area 100 includes a plurality of sub pixels 20.
- the sub-pixel 20 is provided with a pixel circuit 201 for controlling the sub-pixel 20 to display, and the pixel circuit 201 is provided on the base substrate 102 of the display panel.
- the pixel circuit 201 in the sub-pixel 20 will be described as an example.
- the display panel 10 may also be a light emitting diode display panel, or an organic light emitting diode (OLED) display panel.
- the pixel circuit 201 includes a transistor M and a liquid crystal capacitor C.
- the two plates of the liquid crystal capacitor C are respectively composed of a pixel electrode and a common electrode.
- the control electrode of the transistor M is coupled to the gate line GL, the first electrode is coupled to the data line DL, and the second electrode is coupled to the liquid crystal capacitor C.
- the transistor M is configured to transmit the data signal on the data line DL to the liquid crystal capacitor C .
- the display device 200 further includes a source driver 01 and at least one data signal transmission channel 103.
- the source driver 01 is bound to the base substrate 102 and is coupled to each multiplexing unit 11.
- a multiplexing unit 11 is coupled to the source driver 01 through a data transmission channel 103.
- an output port of the source driver 01 is coupled to the data signal terminal Vs of a multiplexer 11 through a data transmission channel 103. Therefore, the number of output ports of the source driver 01 can be reduced and the source The number of data transmission channels 103 to which the pole driver 01 is coupled to the multiplexing unit 11.
- multiple selection unit 11 may also be integrated inside the source driver 01, and the beneficial effects are the same as the beneficial effects of the source driver unit 11, and will not be repeated here.
- the pixels in the display panel 10 are divided into odd-numbered columns of pixels and even-numbered columns of pixels, and the sub-pixels that emit light of the same color in the odd columns are coupled to the same selection signal terminal.
- the MUX couples the sub-pixels emitting the same color light in the even-numbered columns to the same selection signal terminal MUX. Therefore, the number of selection signal terminals MUX can be reduced.
- the charging of the red sub-pixel R1 in the odd column is controlled by the odd red selection signal terminal MUXR1
- the charging of the red sub-pixel R2 in the even column is controlled by the even red selection signal terminal.
- MUXR2 control Taking the green sub-pixel as an example, the charging of the odd-numbered green sub-pixel G1 to be charged is controlled by the odd-numbered green selection signal terminal MUXG1, and the even-numbered column of green sub-pixel G2 to be charged is controlled by the even-numbered green selection signal terminal.
- MUXG2 control Taking the red sub-pixel as an example, the charging of the red sub-pixel R1 in the odd column is controlled by the odd red selection signal terminal MUXR1, and the even-numbered column of green sub-pixel G2 to be charged is controlled by the even-numbered green selection signal terminal.
- the charging of the blue sub-pixels B1 in odd columns is controlled by the odd blue selection signal terminal MUXB1
- the charging of the blue sub-pixels B2 in even columns is controlled by even The blue selection signal terminal MUXB2 control.
- one of the two multiplexer groups is coupled to the sub-pixels to be charged of pixels in odd columns, and the other multiplexer group is coupled to the pixels to be charged in even columns. Charging sub-pixel pixel coupling.
- the gate lines GL are turned on row by row. After each row of the gate lines GL is turned on, the working process of the multiplexing unit 11 is the same. Therefore, the first row of gate lines GL is turned on here. After that, the working process of the multiple selection unit 11 will be illustrated by an example.
- R1-1 represents the timing of the red sub-pixel R1 to be charged in the odd column among the first six sub-pixels to be charged coupled to the multiple selection unit 11 on the left in FIG. 17, and R2-1 represents Among the first six sub-pixels to be charged that are coupled to the multiple selection unit 11 on the left in FIG. 17, the timing of the red sub-pixels to be charged R2 in the even-numbered column.
- R1-2 represents the multiple selection on the right in FIG. Among the first six sub-pixels to be charged that are coupled to the unit 11, the timing of the red sub-pixels to be charged R1 in an odd-numbered column, R2-2 represents the first six coupled to the multiple selection unit 11 on the right in FIG.
- B1-1 shows the timing of the blue sub-pixel B1 to be charged in the odd-numbered column among the first six sub-pixels to be charged coupled by the multiple selection unit 11 on the left in FIG. 17, and B2-1 shows the diagram Among the first six sub-pixels to be charged that are coupled to the multiple selection unit 11 on the left in 17, the timing of the blue sub-pixel to be charged B2 in the even-numbered column.
- B1-2 represents the multiple selection on the right in FIG. Among the first six sub-pixels to be charged that are coupled to the unit 11, the timing of the blue sub-pixel to be charged B1 in the odd-numbered column.
- B2-2 represents the first six that are coupled to the multiplexer unit 11 on the right in FIG.
- the timing of the blue sub-pixels B2 to be charged in the even-numbered column G1-1 shows the timing of the green sub-pixel G1 to be charged in the odd-numbered column among the first six sub-pixels to be charged coupled by the multiple selection unit 11 on the left in FIG. 17, and G2-1 shows the timing of FIG.
- G1-2 represents the multiplexing unit 11 on the right in FIG.
- the timing of the green sub-pixel G1 in the odd-numbered column to be charged is Among the first six coupled sub-pixels to be charged, the timing of the green sub-pixel G1 in the odd-numbered column to be charged.
- G2-2 represents the first six to be charged coupled to the multiplex unit 11 on the right in FIG. In the sub-pixel pixel, the timing of the green sub-pixel G2 to be charged in the even-numbered column.
- the odd red selection signal terminal MUXR1, the odd green selection signal terminal MUXG1, the odd blue selection signal terminal MUXB1, the even red selection signal terminal MUXR2, the even green selection signal terminal MUXG2, and the even blue selection signal terminal MUXB2 are in sequence Input the enable signal
- the data signal terminal Vs1 coupled to the left multiple selection unit 11 inputs the data signal when the odd red selection signal terminal MUXR1 and the even red selection signal terminal MUXR2 input the opening signal, and is coupled to the left multiple selection unit 11
- the red sub-pixel R1 in the odd-numbered column and the red sub-pixel R2 in the even-numbered column are charged, and the remaining four sub-pixels to be charged are not charged.
- the data signal terminal Vs2 coupled to the multiple selection unit 11 on the right inputs a data signal when the even-numbered blue selection signal terminal MUXB2 inputs the turn-on signal, and is coupled to the last six sub-pixel pixels to be charged that are coupled to the multiple selection unit 11 on the right , The blue sub-pixel B2 to be charged in the even-numbered column is charged, and the remaining five sub-pixels to be charged are not charged.
- FIG. 18 is only a schematic diagram of the signal timing of the data signal terminal Vs1 coupled to the multiple selection unit 11 on the left and the data signal terminal Vs2 coupled to the multiple selection unit 11 on the right in FIG. 17, but in practical applications Not limited to this.
- the signals of the data signal terminal Vs1 coupled to the multiple selection unit 11 on the left and the data signal terminal Vs2 coupled to the multiple selection unit 11 on the right may be high.
- the potentials of the high-level signals required for charging different sub-pixels to be charged are not completely equal.
- the signal of the odd-numbered red selection signal terminal MUXR1 is a high-level signal
- the signal received at the data signal terminal Vs1 coupled to the multiple selection unit 11 on the left is a high-level signal
- the red sub-pixels R1 to be charged in odd-numbered columns start to be charged.
- the left multiplexing unit 11 is coupled Among the first six sub-pixels to be charged, the red sub-pixel R1 to be charged in the odd column is still charged. At this time, among the first six sub-pixels to be charged that are coupled to the multiple selection unit 11 on the left, the charging time of the red sub-pixels R1 to be charged in the odd column is longer than the data signal coupled to the multiple selection unit 11 on the left. The length of time that the signal received at the terminal Vs1 is high.
- the charging time period of the sub-pixel pixel to be charged is longer than the valid time period of the signal of the selection signal terminal MUX.
- the multiplexing unit 11 repeats the above process.
- the above-mentioned display device 200 may be any device that displays images whether in motion (for example, video) or fixed (for example, still images), and regardless of text or images. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs) , Handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, car monitors (e.g., Odometer display, etc.), navigator, cockpit controller and/or display, camera view display (for example, the display of a rear-view camera in a vehicle), electronic photos, electronic billboards or signs, projectors, building structures, packaging And aesthetic structure (for example, a display of the image of a piece of jewelry), etc.
- PDAs personal data assistants
- Handheld or portable computers GPS receivers/navigators,
- the multiplexer circuit 110 includes a charging sub-circuit 40, a control sub-circuit 50 and a delay sub-circuit 30.
- the charging sub-circuit 40 is coupled to the selection signal terminal MUX, the data signal terminal Vs and the sub-pixel pixel to be charged;
- the control sub-circuit 50 is coupled to the selection signal terminal MUX and the data signal terminal Vs;
- the delay sub-circuit 30 is coupled to the sub-pixel to be charged
- the pixel is coupled to the control sub-circuit 50.
- the driving method of the multiple selection circuit 110 includes:
- the selection signal terminal MUX inputs the turn-on signal, and the charging sub-circuit 40 transmits the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged under the control of the signal received at the selection signal terminal MUX; the control sub-circuit 50 is at Under the control of the signal received at the selection signal terminal MUX, the signal received at the data signal terminal Vs is transmitted; the delay sub-circuit 30 delays the transmission of the signal received at the data signal terminal Vs transmitted through the control sub-circuit 50, and is After the electronic circuit 40 charges the sub-pixel pixel to be charged for a preset time, the delay sub-circuit 30 transmits the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged.
- the selection signal terminal MUX inputs a cut-off signal
- the charging sub-circuit 40 and the control sub-circuit 50 are cut off under the control of the signal received at the selection signal terminal MUX
- the delay sub-circuit 30 continues to transmit the signal received at the data signal terminal Vs to Sub-pixel pixel to be charged.
Abstract
Description
Claims (16)
- 一种多路选择电路,包括:A multiple selection circuit, including:充电子电路,分别与选择信号端、数据信号端和待充电亚像素耦接;所述充电子电路被配置为,在所述选择信号端处接收的信号的控制下,将在所述数据信号端处接收的信号传输至所述待充电亚像素;The charging sub-circuit is respectively coupled to the selection signal terminal, the data signal terminal, and the sub-pixel to be charged; the charging sub-circuit is configured to, under the control of the signal received at the selection signal terminal, transfer the data signal The signal received at the terminal is transmitted to the sub-pixel to be charged;控制子电路,分别与所述选择信号端和所述数据信号端耦接;所述控制子电路被配置为,在所述选择信号端处接收的信号的控制下,传输在所述数据信号端处接收的信号;The control sub-circuit is respectively coupled to the selection signal terminal and the data signal terminal; the control sub-circuit is configured to transmit to the data signal terminal under the control of the signal received at the selection signal terminal Signal received at延时子电路,分别与所述待充电亚像素和所述控制子电路耦接;所述延时子电路被配置为,将经过所述控制子电路传输的在所述数据信号端处接收的信号延迟传输,在所述充电子电路向所述待充电亚像素充电预设时间后,将在所述数据信号端处接收的信号传输至所述待充电亚像素。The delay sub-circuits are respectively coupled to the sub-pixels to be charged and the control sub-circuit; the delay sub-circuits are configured to transmit data transmitted through the control sub-circuit and received at the data signal terminal Signal transmission is delayed, and after the charging sub-circuit charges the sub-pixel to be charged for a preset time, the signal received at the data signal terminal is transmitted to the sub-pixel to be charged.
- 根据权利要求1所述的多路选择电路,其中,所述延时子电路包括:The multiplexer circuit according to claim 1, wherein the delay sub-circuit comprises:第三晶体管,所述第三晶体管的控制极与控制信号端耦接,所述第三晶体管的第一极与所述控制子电路耦接;A third transistor, a control electrode of the third transistor is coupled to a control signal terminal, and a first electrode of the third transistor is coupled to the control sub-circuit;第四晶体管,所述第四晶体管的控制极与所述第三晶体管的第二极耦接,所述第四晶体管的第一极与所述控制子电路耦接,所述第四晶体管的第二极与所述待充电亚像素耦接;A fourth transistor, the control electrode of the fourth transistor is coupled to the second electrode of the third transistor, the first electrode of the fourth transistor is coupled to the control sub-circuit, and the second electrode of the fourth transistor The two poles are coupled to the sub-pixel to be charged;第一电容,所述第一电容的第一端分别与所述控制子电路、所述第三晶体管的第一极和所述第四晶体管的第一极耦接,所述第一电容的第二端与第一电压端耦接。The first capacitor, the first terminal of the first capacitor is respectively coupled to the control sub-circuit, the first pole of the third transistor, and the first pole of the fourth transistor, the first terminal of the first capacitor The two terminals are coupled with the first voltage terminal.
- 根据权利要求2所述的多路选择电路,其中,所述第四晶体管的沟道的宽长比大于所述第三晶体管的沟道的宽长比。3. The multiplexer circuit according to claim 2, wherein the aspect ratio of the channel of the fourth transistor is greater than the aspect ratio of the channel of the third transistor.
- 根据权利要求3所述的多路选择电路,其中,所述延时子电路还包括:The multiplexer circuit according to claim 3, wherein the delay sub-circuit further comprises:第二电容,所述第二电容的第一端分别与所述第四晶体管的第二极和所述待充电亚像素耦接,所述第二电容的第二端与所述第一电压端耦接。A second capacitor, the first terminal of the second capacitor is respectively coupled to the second terminal of the fourth transistor and the sub-pixel to be charged, and the second terminal of the second capacitor is connected to the first voltage terminal Coupling.
- 根据权利要求1~4中任一项所述的多路选择电路,其中,所述控制子电路包括:The multiplexer circuit according to any one of claims 1 to 4, wherein the control sub-circuit comprises:第二晶体管,所述第二晶体管的控制极与所述选择信号端耦接,所述第二晶体管的第一极与所述数据信号端耦接,所述第二晶体管的第二极与所述延时子电路耦接。The second transistor, the control electrode of the second transistor is coupled to the selection signal terminal, the first electrode of the second transistor is coupled to the data signal terminal, and the second electrode of the second transistor is coupled to the The delay sub-circuit is coupled.
- 根据权利要求1~5中任一项所述的多路选择电路,其中,所述充电子电路包括:The multiplexer circuit according to any one of claims 1 to 5, wherein the charging sub-circuit comprises:第一晶体管,所述第一晶体管的控制极与所述选择信号端耦接,所述第 一晶体管的第一极与所述数据信号端耦接,所述第一晶体管的第二极与所述待充电亚像素耦接。The first transistor, the control electrode of the first transistor is coupled to the selection signal terminal, the first electrode of the first transistor is coupled to the data signal terminal, and the second electrode of the first transistor is coupled to the selection signal terminal. The sub-pixel to be charged is coupled.
- 根据权利要求1~6中任一项所述的多路选择电路,还包括:The multiple selection circuit according to any one of claims 1 to 6, further comprising:存储子电路,所述存储子电路分别与所述充电子电路、所述待充电亚像素和第一电压端耦接;所述存储子电路被配置为,对所述充电子电路传输的在所述数据信号端处接收的信号进行存储,及,将所存储的信号传输至所述待充电亚像素。A storage sub-circuit, the storage sub-circuit is respectively coupled to the charging sub-circuit, the sub-pixel to be charged, and the first voltage terminal; the storage sub-circuit is configured to transmit to the charging sub-circuit in all The signal received at the data signal terminal is stored, and the stored signal is transmitted to the sub-pixel to be charged.
- 根据权利要求7所述的多路选择电路,其中,所述存储子电路包括:8. The multiplexer circuit according to claim 7, wherein the storage sub-circuit comprises:第三电容,所述第三电容的第一端分别与所述充电子电路和所述待充电亚像素耦接,所述第三电容的第二端与所述第一电压端耦接。A third capacitor, the first terminal of the third capacitor is respectively coupled to the charging sub-circuit and the sub-pixel to be charged, and the second terminal of the third capacitor is coupled to the first voltage terminal.
- 一种多路选择单元,包括:A multiple selection unit, including:至少一个多路选择组,每个多路选择组包括多个如权利要求1~8中任一项所述的多路选择电路;At least one multiplexing group, each multiplexing group comprising a plurality of multiplexing circuits according to any one of claims 1-8;所述多路选择单元中的每个所述多路选择电路耦接不同的选择信号端。Each of the multiple selection circuits in the multiple selection unit is coupled to a different selection signal terminal.
- 根据权利要求9所述的多路选择单元,其中,所述多路选择组中的每个多路选择电路耦接的待充电亚像素的发光颜色不同。9. The multiplex selection unit according to claim 9, wherein the sub-pixels to be charged coupled to each multiplex selection circuit in the multiplex selection group have different light-emitting colors.
- 根据权利要求9或10所述的多路选择单元,其中,所述多路选择单元中的多个所述多路选择电路耦接同一数据信号端。10. The multiplexing unit according to claim 9 or 10, wherein a plurality of the multiplexing circuits in the multiplexing unit are coupled to the same data signal terminal.
- 根据权利要求9~11中任一项所述的多路选择单元,其中,所述多路选择单元包括两个所述多路选择组,所述多路选择组包括三个所述多路选择电路。The multiplexing unit according to any one of claims 9 to 11, wherein the multiplexing unit includes two multiplexing groups, and the multiplexing group includes three multiplexing Circuit.
- 根据权利要求12所述的多路选择单元,其中,两个所述多路选择组中的一个多路选择组与奇数列像素的待充电亚像素耦接,另一个多路选择组与偶数列像素的待充电亚像素耦接。The multiplexer unit according to claim 12, wherein one multiplexer group of the two multiplexer groups is coupled to the sub-pixels to be charged of pixels in odd columns, and the other multiplexer group is coupled with even columns The sub-pixel to be charged of the pixel is coupled.
- 一种显示装置,包括:A display device includes:至少一个如权利要求9~13中任一项所述的多路选择单元;At least one multiplexing unit according to any one of claims 9-13;显示面板,所述显示面板包括衬底基板;所述多路选择单元设置于所述衬底基板上。The display panel, the display panel includes a base substrate; the multiplexer is arranged on the base substrate.
- 根据权利要求14所述的显示装置,还包括:The display device according to claim 14, further comprising:源极驱动器,所述源极驱动器与所述衬底基板绑定,并与各所述多路选择单元耦接;和A source driver, the source driver is bound to the base substrate and coupled to each of the multiple selection units; and至少一个数据信号传输通道,所述数据信号传输通道设置于所述衬底基板上;一个所述多路选择单元通过一个数据传输通道与所述源极驱动器耦接。At least one data signal transmission channel, the data signal transmission channel is arranged on the base substrate; one of the multiplexer units is coupled to the source driver through a data transmission channel.
- 一种如权利要求1~8中任一项所述的多路选择电路的驱动方法,包括:A method for driving a multiple selection circuit according to any one of claims 1 to 8, comprising:选择信号端输入开启信号,充电子电路在所述选择信号端处接收的信号的控制下,将在数据信号端处接收的信号传输至待充电亚像素;The selection signal terminal inputs an on signal, and the charging sub-circuit transmits the signal received at the data signal terminal to the sub-pixel to be charged under the control of the signal received at the selection signal terminal;控制子电路在所述选择信号端处接收的信号的控制下,传输在所述数据信号端处接收的信号;The control sub-circuit transmits the signal received at the data signal terminal under the control of the signal received at the selection signal terminal;所述延时子电路将经过所述控制子电路传输的在所述数据信号端处接收的信号延迟传输,在所述充电子电路向所述待充电亚像素充电预设时间后,所述延时子电路将在所述数据信号端处接收的信号传输至所述待充电亚像素;The delay sub-circuit delays the transmission of the signal received at the data signal terminal transmitted through the control sub-circuit. After the charging sub-circuit charges the sub-pixel to be charged for a preset time, the delay The time sub-circuit transmits the signal received at the data signal terminal to the sub-pixel to be charged;所述选择信号端输入截止信号,所述充电子电路和所述控制子电路在所述选择信号端处接收的信号的控制下截止,所述延时子电路继续将在所述数据信号端处接收的信号传输至所述待充电亚像素。The selection signal terminal inputs a cut-off signal, the charging sub-circuit and the control sub-circuit are cut off under the control of the signal received at the selection signal terminal, and the delay sub-circuit continues to be at the data signal terminal The received signal is transmitted to the sub-pixel to be charged.
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CN109785813B (en) * | 2019-03-26 | 2021-01-26 | 京东方科技集团股份有限公司 | Source electrode driving circuit, source electrode driving method, source electrode driving unit, source electrode driver and display device |
CN111402826B (en) * | 2020-03-31 | 2022-04-22 | 合肥鑫晟光电科技有限公司 | Source electrode driving circuit, driving method and display device |
CN115273739B (en) | 2022-09-26 | 2023-01-24 | 惠科股份有限公司 | Display panel, driving method and display device |
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CN109785813A (en) | 2019-05-21 |
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