WO2020192476A1 - Multi-path selection circuit and driving method, and multi-path selection unit and display apparatus - Google Patents

Multi-path selection circuit and driving method, and multi-path selection unit and display apparatus Download PDF

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Publication number
WO2020192476A1
WO2020192476A1 PCT/CN2020/079561 CN2020079561W WO2020192476A1 WO 2020192476 A1 WO2020192476 A1 WO 2020192476A1 CN 2020079561 W CN2020079561 W CN 2020079561W WO 2020192476 A1 WO2020192476 A1 WO 2020192476A1
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sub
circuit
pixel
charged
coupled
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PCT/CN2020/079561
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French (fr)
Chinese (zh)
Inventor
苏旭
王磊
赵晶
孙继刚
王洁琼
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Publication of WO2020192476A1 publication Critical patent/WO2020192476A1/en

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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275Details of drivers for data electrodes
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a multiplex selection circuit and driving method, multiplex selection unit, and display device.
  • a plurality of sub-pixels are arranged inside the display device, and the screen display is realized by controlling the display of the sub-pixels.
  • each sub-pixel of the display device is provided with a pixel circuit for controlling the sub-pixel to display, and the pixel circuit controls the sub-pixel display under the control of the scan signal provided by the gate line and the data signal provided by the data line.
  • the multiple selection circuit includes a charging sub-circuit, a control sub-circuit and a delay sub-circuit.
  • the charging sub-circuit is respectively coupled to the selection signal terminal, the data signal terminal and the sub-pixel to be charged, and the charging sub-circuit is configured to, under the control of the signal received at the selection signal terminal, load the data
  • the signal received at the signal terminal is transmitted to the sub-pixel to be charged;
  • the control sub-circuit is respectively coupled to the selection signal terminal and the data signal terminal, and the control sub-circuit is configured to: Under the control of the signal received at the terminal, the signal received at the data signal terminal is transmitted;
  • the delay sub-circuit is respectively coupled to the sub-pixel to be charged and the control sub-circuit, the delay sub-circuit Is configured to delay the transmission of the signal received at the data signal terminal transmitted through the control sub-circuit, and after the charging sub-circuit charges the sub-pixel to be charged for a preset time, the data
  • the delay sub-circuit includes: a third transistor, a fourth transistor and a first capacitor.
  • the control electrode of the third transistor is coupled to the control signal terminal, the first electrode of the third transistor is coupled to the control sub-circuit; the control electrode of the fourth transistor is connected to the second terminal of the third transistor.
  • the first electrode of the fourth transistor is coupled to the control sub-circuit, and the second electrode of the fourth transistor is coupled to the sub-pixel to be charged; the first terminal of the first capacitor Are respectively coupled to the control sub-circuit, the first pole of the third transistor and the first pole of the fourth transistor, and the second terminal of the first capacitor is coupled to the first voltage terminal.
  • the aspect ratio of the channel of the fourth transistor is greater than the aspect ratio of the channel of the third transistor.
  • the delay sub-circuit further includes a second capacitor.
  • the first terminal of the second capacitor is respectively coupled to the second electrode of the fourth transistor and the sub-pixel to be charged, and the second terminal of the second capacitor is coupled to the first voltage terminal.
  • control sub-circuit includes a second transistor.
  • the control electrode of the second transistor is coupled to the selection signal terminal, the first electrode of the second transistor is coupled to the data signal terminal, and the second electrode of the second transistor is coupled to the delay element. Circuit coupling.
  • the charging sub-circuit includes a first transistor.
  • the control electrode of the first transistor is coupled to the selection signal terminal, the first electrode of the first transistor is coupled to the data signal terminal, and the second electrode of the first transistor is connected to the sub-to-be-charged. Pixel coupling.
  • the multiple selection circuit further includes a storage sub-circuit.
  • the storage sub-circuit is respectively coupled to the charging sub-circuit, the sub-pixel to be charged and the first voltage terminal, and the storage sub-circuit is configured to transmit data to the charging sub-circuit at the data signal terminal Storing the signal received there, and transmitting the stored signal to the sub-pixel to be charged.
  • the storage sub-circuit includes a third capacitor.
  • the first terminal of the third capacitor is respectively coupled to the charging sub-circuit and the sub-pixel to be charged, and the second terminal of the third capacitor is coupled to the first voltage terminal.
  • the multiple selection unit includes: at least one multiple selection group.
  • the multiple selection group includes a plurality of multiple selection circuits as described in any of the foregoing embodiments; each of the multiple selection circuits in the multiple selection unit is coupled to a different selection signal terminal.
  • the light-emitting colors of the sub-pixels to be charged coupled to each multiplex selection circuit in the multiplex selection group are different.
  • a plurality of the multiple selection circuits in the multiple selection unit are coupled to the same data signal terminal.
  • the multiplexing unit includes two multiplexing groups, and the multiplexing group includes three multiplexing circuits.
  • one of the two multiplexer groups is coupled to the sub-pixels of the odd-numbered columns of pixels, and the other multiplexer group is coupled to the sub-pixels of the even-numbered columns of pixels.
  • a display device in another aspect, includes at least one multiple selection unit and a display panel as described in any of the above embodiments.
  • the display panel includes a base substrate; the multiple selection unit is arranged on the base substrate.
  • the display device further includes a source driver and at least one data signal transmission channel.
  • the source driver is bound to the base substrate, and is coupled to each of the multiple selection units; the data signal transmission channel is arranged on the base substrate, and one multiple selection unit passes through one The data transmission channel is coupled to the source driver.
  • multiple data signal terminals are coupled to the source driver through one signal line.
  • a method for driving a multiple selection circuit as described in any of the above embodiments includes: inputting a turn-on signal at the selection signal terminal, and the charging sub-circuit under the control of the signal received at the selection signal terminal, The signal received at the data signal terminal is transmitted to the sub-pixel to be charged; the control sub-circuit transmits the signal received at the data signal terminal under the control of the signal received at the selection signal terminal; the delay sub-circuit will The signal received at the data signal terminal transmitted through the control sub-circuit is delayed in transmission.
  • the delay sub-circuit After the charging sub-circuit charges the sub-pixel to be charged for a preset time, the delay sub-circuit will The signal received at the data signal terminal is transmitted to the sub-pixel to be charged; the selection signal terminal inputs a cut-off signal, and the charging sub-circuit and the control sub-circuit cut off under the control of the signal received at the selection signal terminal , The delay sub-circuit continues to transmit the signal received at the data signal terminal to the sub-pixel to be charged.
  • FIG. 1 is a structural diagram of a display device according to some embodiments.
  • FIG. 2 is another structural diagram of a display device according to some embodiments.
  • Fig. 3 is a structural diagram of a display device according to the related art
  • FIG. 4 is another structural diagram of a display device according to the related art.
  • Fig. 5 is a structural diagram of a multiple selection circuit according to some embodiments.
  • Fig. 6 is another structural diagram of a multiple selection circuit according to some embodiments.
  • FIG. 7 is another structural diagram of a multiple selection circuit according to some embodiments.
  • Fig. 8 is another structural diagram of a multiple selection circuit according to some embodiments.
  • Fig. 9 is a structural diagram of a multiple selection unit according to some embodiments.
  • Fig. 10 is another structural diagram of a multiple selection unit according to some embodiments.
  • FIG. 11 is another structural diagram of a multiple selection unit according to some embodiments.
  • Fig. 12 is another structural diagram of a multiple selection unit according to some embodiments.
  • FIG. 13 is a structural diagram of a display panel according to some embodiments.
  • FIG. 14 is another structural diagram of a display panel according to some embodiments.
  • FIG. 15 is another structural diagram of a display panel according to some embodiments.
  • FIG. 16 is another structural diagram of a display device according to some embodiments.
  • FIG. 17 is another structural diagram of a display device according to some embodiments.
  • FIG. 18 is a driving timing diagram of the multiple selection unit according to some embodiments.
  • Fig. 19 is a driving flowchart of a multiple selection unit according to some embodiments.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content herein.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • azimuth terms such as “upper”, “lower”, “left”, “right”, “horizontal” and “vertical” are defined relative to the directions in which the components in the drawings are schematically placed. It should be understood that these directional terms are relative concepts, and they are used for relative description and clarification, which can be changed correspondingly according to the changes in the orientation of the components in the drawings.
  • each data line DL in the display panel 10' needs to receive a data signal.
  • the display panel 10' including 1080 columns of sub-pixels 20' as an example, there are 1080 data lines DL that need to receive data signals, and the source driver 01' (Source IC) that provides data signals for the data lines DL 1080 output ports are required, which leads to an increase in the manufacturing cost of the source driver 01' in the display device 200' and an increase in the occupied area.
  • Source IC Source IC
  • a multiplexer circuit 110' is usually used to convert the signals and charge the sub-pixels 20'.
  • the multiple selection circuit 110' controls the levels of the red selection signal terminal MUXR, the green selection signal terminal MUXG, and the blue selection signal terminal MUXB so that the first thin film transistor M1 and the second thin film transistor M2 ,
  • the third thin film transistor M3 is turned on sequentially, and sequentially transmits the signal of the data signal terminal Vs to realize charging of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B.
  • Three sub-pixels located in the same pixel are connected to the same data signal terminal Vs. In this way, the number of output ports of the source driver 01' can be reduced to one third of the original number.
  • FIG. 4 shows a scheme in which the multiple selection circuit 110' receives a signal through a data signal terminal Vs and charges 6 sub-pixels 20'.
  • the selection signal terminal is turned on in turn, and the 6 sub-pixels 20' are sequentially charged, thereby reducing Source driver 01' cost and size to achieve a full screen with ultra-narrow bezel.
  • the charging time required for each sub-pixel 20' is fixed. If the charging time of each sub-pixel 20 is reduced, the sub-pixel 20' will be undercharged. Affect the display effect.
  • the total charging time of one data line DL is 3.6 us. If the multiplex circuit 110' receives a signal through a data signal terminal Vs, it charges three sub-pixels 20', and each sub-pixel 20' charges The time is 1.2us, which can also guarantee the normal display of the display device. However, if the multiplexer circuit 110' receives signals through a data signal terminal Vs and charges the 6 sub-pixels 20', the charging time of each sub-pixel 20' is 0.6us, and the charging time is reduced by half, resulting in sub-pixels If the charging is insufficient at 20', the display effect will deteriorate.
  • the embodiment of the present disclosure provides a multiple selection circuit 110, as shown in FIG. 5, including: a charging sub-circuit 40, a control sub-circuit 50, and a delay sub-circuit 30.
  • the charging sub-circuit 40 is respectively coupled to the selection signal terminal MUX, the data signal terminal Vs and the sub-pixel to be charged.
  • the control sub-circuit 50 is respectively coupled to the selection signal terminal MUX and the data signal terminal Vs.
  • the delay sub-circuit 30 is respectively coupled to the sub-pixel to be charged and the control sub-circuit 50.
  • the charging sub-circuit 40 is configured to transmit the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged under the control of the signal received at the selection signal terminal MUX.
  • the charging sub-circuit 40 actually transmits the signal received at the data signal terminal Vs to the pixel circuit to control the display of the sub-pixel pixel to be charged. Taking the pixel circuit 201 shown in FIG. 2 as an example, the charging sub-circuit 40 transmits the signal received at the data signal terminal Vs to the data line DL, and then to the first pole of the transistor M in the pixel circuit 201.
  • the sub-pixel pixel to be charged may be any sub-pixel 20 in the display panel 10, for example, it may be a red sub-pixel R, a green sub-pixel G, or a blue sub-pixel B.
  • the control sub-circuit 50 is configured to transmit the signal received at the data signal terminal Vs under the control of the signal received at the selection signal terminal MUX.
  • control sub-circuit 50 is substantially equivalent to a switch, and any structure that can achieve the same effect as the control sub-circuit 50 belongs to the protection scope of the present application.
  • the delay sub-circuit 30 is configured to delay the transmission of the signal received at the data signal terminal Vs transmitted through the control sub-circuit 50. After the charging sub-circuit 40 charges the sub-pixel pixel to be charged for a preset time, it will be at the data signal terminal. The signal received at Vs is transmitted to the sub-pixel pixel to be charged.
  • the time that the delay sub-circuit 30 charges the sub-pixel pixel to be charged is delayed relative to the time that the charging sub-circuit 40 charges the sub-pixel pixel to be charged, and the delayed time is the preset time.
  • the delay sub-circuit 30 starts charging the sub-pixel pixel to be charged the charging sub-circuit 40 has not finished charging the sub-pixel pixel to be charged, or when the delay sub-circuit 30 charges the sub-pixel pixel to be charged At the same time as the charging starts, the charging of the sub-pixel pixel to be charged by the charging sub-circuit 40 ends.
  • the signal from the control sub-circuit 50 is the signal received by the control sub-circuit 50 at the data signal terminal Vs.
  • the charging sub-circuit 40 transmits the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged, and at the same time, the control sub-circuit 50 will be at the data signal terminal
  • the signal received at Vs is transmitted to the delay sub-circuit 30, but at this time, the delay sub-circuit 30 does not transmit the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged.
  • the delay sub-circuit 30 transmits the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged.
  • the charging sub-circuit 40 sends the The sub-pixel pixel charging is not over yet.
  • the charging time of the charging sub-circuit 40 ends, under the control of the signal received at the selection signal terminal MUX, the charging sub-circuit 40 is closed, the charging sub-circuit 40 stops charging the sub-pixel pixel to be charged, and the control sub-circuit 50 stops at The signal received at the data signal terminal Vs is transmitted.
  • the delay sub-circuit 30 continues to transmit the signal from the control sub-circuit 50, that is, the signal received at the data signal terminal Vs to the sub-pixel to be charged.
  • the embodiment of the present disclosure does not limit the specific structure of the delay sub-circuit 30, and the sub-circuit structure capable of delaying signal transmission belongs to the protection scope of the present disclosure. Moreover, after the delay sub-circuit 30 delays the signal, the time that the sub-pixel pixel to be charged can continue to be charged is related to the specific structure of the delay sub-circuit 30 and can be set reasonably according to needs.
  • the selection signal terminal MUX is turned on for 0.6us
  • the delay sub-circuit 30 is configured so that the delay sub-circuit 30 delays the signal received at the data signal terminal Vs, and then charges the sub-pixel pixel to be charged.
  • the time that can be continuously charged is also 0.6us. In this way, it takes 0.6us to charge each sub-pixel, but the effect achieved is the same as that of 1.2us.
  • the charging sub-circuit 40 and the delay sub-circuit 30 are both used to transmit the data voltage signal to the sub-pixel pixel to be charged.
  • the charging sub-circuit 40 and the delay sub-circuit 30 receive the signal on the data signal terminal Vs at the same time, they both transmit the signal of the data signal terminal Vs to the sub-pixel pixel to be charged at different times.
  • the delay sub-circuit 30 Delay the signal transmission to the sub-pixel to be charged.
  • the signal received at the selection signal terminal MUX controls the time for the charging sub-circuit 40 to turn on to be shortened, that is, when the charging sub-circuit 40 shortens the charging time of the sub-pixel pixel to be charged, the delay sub-circuit 30 delays the transmission of the data signal.
  • the signal of the terminal Vs prolongs the charging time of the sub-pixel pixel to be charged, and ensures the charging effect of the sub-pixel pixel to be charged.
  • the charging sub-circuit 40 and the delay sub-circuit 30 in the multiple selection circuit are used to charge the sub-pixel pixel to be charged, but both charge the sub-pixel pixel to be charged. The moments are different.
  • the charging sub-circuit 40 is turned on under the control of the signal received at the selection signal terminal MUX.
  • the charging sub-circuit 40 charges the sub-pixel pixel to be charged.
  • the delay sub-circuit 30 is compared with the charging sub-circuit.
  • the signal received by the delay sub-circuit 30 at the selection signal terminal MUX controls the charging sub-circuit 40 to disconnect, and then continues to charge the sub-pixel pixel to be charged. That is to say, when the next multiplexer circuit charges the next sub-pixel pixel to be charged, the delay sub-circuit 30 in the previous multiplexer circuit is still charging the next sub-pixel pixel to be charged, and the delay sub-circuit 30 Charging the sub-pixel pixel to be charged does not cause the total charging time to increase. Therefore, the multiple selection circuit provided by the embodiment of the present disclosure not only shortens the charging time of the sub-pixel pixel to be charged, but also ensures the charging effect of the sub-pixel pixel to be charged.
  • the multiplexer circuit 100 When the multiplexer circuit is applied to a display device, the multiplexer circuit 100 is coupled to the output port of the source driver 01 through the data signal transmission channel, which can reduce the number of output ports of the source driver 01 and reduce the number of output ports of the source driver 01.
  • the number of data signal transmission channels coupled to the output port of 01 does not affect the charging effect of each sub-pixel 20.
  • the charging sub-circuit 40 includes a first transistor T1.
  • the control electrode of the first transistor T1 is coupled to the selection signal terminal MUX, the first electrode of the first transistor T1 is coupled to the data signal terminal Vs, and the second electrode of the first transistor T1 is coupled to the sub-pixel pixel to be charged.
  • the charging sub-circuit 40 may further include a plurality of switching transistors connected in parallel with the first transistor T1.
  • control sub-circuit 50 includes a second transistor T2.
  • the control electrode of the second transistor T2 is coupled to the selection signal terminal MUX, the first electrode of the second transistor T2 is coupled to the data signal terminal Vs, and the second electrode of the second transistor T2 is coupled to the delay sub-circuit 30.
  • control sub-circuit 50 may further include a plurality of switching transistors connected in parallel with the second transistor T2.
  • control sub-circuit 50 is only an example of the control sub-circuit 50, and other structures with the same function as the control sub-circuit 50 will not be repeated here, but they should all fall within the protection scope of the present disclosure.
  • the delay sub-circuit 30 includes a third transistor T3, a fourth transistor T4 and a first capacitor C1.
  • the control electrode of the third transistor T3 is coupled to the control signal terminal Vc, the first electrode of the third transistor T3 is coupled to the control sub-circuit 50, and the second electrode of the third transistor T3 is coupled to the control electrode of the fourth transistor T4.
  • the first pole of the fourth transistor T4 is coupled to the control sub-circuit 50, and the second pole of the fourth transistor T4 is coupled to the sub-pixel to be charged.
  • the first terminal of the first capacitor C1 is respectively coupled to the control sub-circuit 50, the first pole of the third transistor T3 and the first pole of the fourth transistor T4, and the second terminal of the first capacitor C1 is coupled to the first voltage terminal V1 Pick up.
  • the signal received at the control signal terminal Vc is configured to control the third transistor T3 to turn on during the charging phase of the sub-pixel.
  • the signal received at the control signal terminal Vc is a DC high-level signal.
  • the aspect ratio of the channel of the fourth transistor T4 is greater than the aspect ratio of the channel of the third transistor T3.
  • the on-resistance of the third transistor T3 in the linear region is smaller than the on-resistance of the fourth transistor T4 in the linear region.
  • the control signal terminal Vc controls the turn-on of the third transistor T3, a part of the signal received at the data signal terminal Vs is transmitted to the control electrode of the fourth transistor T4 through the third transistor T3, and in the signal received at the data signal terminal Vs The other part of is transmitted to the first pole of the fourth transistor T4 to control the turning on of the fourth transistor T4, and the signal received at the data signal terminal Vs can be transmitted to the sub-pixel pixel to be charged through the fourth transistor T4 with a delay.
  • the circuit zero point (that is, the delay time of the delay sub-circuit 30 is zero) can be adjusted.
  • To control the delay time of the delay sub-circuit 30 transmitting the signal from the control sub-circuit 50 to the sub-pixel to be charged.
  • Those skilled in the art can design the width-to-length ratio of the channel of the fourth transistor T4 and the width-to-length ratio of the channel of the third transistor T3 according to actual conditions, which are not limited in the embodiments of the present disclosure.
  • the delay sub-circuit 30 further includes: a second capacitor C2.
  • the first terminal of the second capacitor C2 is respectively coupled to the second electrode of the fourth transistor T4 and the sub-pixel pixel to be charged, and the second terminal of the second capacitor C2 is coupled to the first voltage terminal V1.
  • the delay sub-circuit 30 may be a ⁇ -type delay circuit.
  • the multiple selection circuit 110 further includes a storage sub-circuit 60.
  • the storage sub-circuit 60 is respectively coupled to the charging sub-circuit 40, the sub-pixel pixel to be charged and the first voltage terminal V1.
  • the first voltage terminal V1 in the embodiment of the present disclosure may be, for example, a ground terminal or a fixed voltage terminal.
  • the signal received at the first voltage terminal V1 is a DC low-level signal.
  • the storage sub-circuit 60 is configured to store the signal received at the data signal terminal Vs transmitted by the charging sub-circuit 40, and to transmit the stored signal to the sub-pixel pixel to be charged.
  • the storage sub-circuit 60 can keep the signal transmitted to the sub-pixel pixel to be charged through the charging sub-circuit 40 stable, thereby improving the stability of charging the sub-pixel pixel to be charged.
  • the storage sub-circuit 60 includes a third capacitor C3.
  • the first terminal of the third capacitor C3 is respectively coupled to the charging sub-circuit 40 and the sub-pixel pixel to be charged, and the second terminal of the third capacitor C3 is coupled to the first voltage terminal V1.
  • the first transistor T1 transmits the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged
  • the third capacitor C3 stores the signal received at the data signal terminal Vs to improve the stability of the signal transmitted to the sub-pixel pixel to be charged through the first transistor T1.
  • the second transistor T2 under the control of the signal received at the selection signal terminal MUX, the second transistor T2 is turned on and transmits the signal received at the data signal terminal Vs to the delay sub-circuit 30.
  • the aspect ratio of the channel of the fourth transistor T4 is greater than the aspect ratio of the channel of the third transistor T3, the on-resistance of the third transistor T3 in the linear region is smaller than the on-resistance of the fourth transistor T4 in the linear region, and the control signal
  • the terminal Vc controls the turn-on of the third transistor T3, and a part of the signal received at the data signal terminal Vs is transmitted to the control electrode of the fourth transistor T4 through the third transistor T3.
  • the other part is transmitted to the first pole of the fourth transistor T4 to control the turning on of the fourth transistor T4.
  • the signal received at the data signal terminal Vs can be transmitted to the sub-pixel to be charged through the fourth transistor T4 with a delay.
  • the position of the circuit zero point (that is, the delay time of the delay sub-circuit 30 is zero) can be adjusted by adjusting the width to length ratio of the channel of the fourth transistor T4 and the width to length ratio of the channel of the third transistor T3, thereby The delay time can be controlled to delay the transmission of the signal at the data signal terminal Vs.
  • the signal terminal MUX to be selected inputs a cut-off signal.
  • the delay sub-circuit 30 just transmits the signal of the data signal terminal Vs to the sub-pixel pixel to be charged, and the sub-pixel pixel to be charged continues to be charged to extend the charging time of the sub-pixel pixel to be charged .
  • the transistors used in the multiple selection circuit 110 may be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and the embodiments of the present disclosure are not limited thereto.
  • the control electrode of each transistor used in the multiplexer circuit 110 is the gate of the transistor, one of the source and drain of the transistor on the first pole, and the other of the source and drain of the transistor on the second pole.
  • the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable, that is, the first and second electrodes of the transistor in the embodiment of the present disclosure
  • the two poles can be indistinguishable in structure.
  • the transistor is a P-type transistor
  • the first electrode of the transistor is a source and the second electrode is a drain; for example, when the transistor is an N-type transistor, the first electrode of the transistor is a drain,
  • the second pole is the source.
  • the specific implementation manners of the delay sub-circuit 30, the charging sub-circuit 40, the control sub-circuit 50, and the storage sub-circuit 60 are not limited to the above-described manner, which can be implemented arbitrarily.
  • the method for example, a conventional connection method well known to those skilled in the art, only needs to ensure that the corresponding function is realized.
  • the above examples do not limit the protection scope of the present disclosure.
  • the skilled person can choose to use or not apply one or more of the above-mentioned circuits according to the situation.
  • Various combinations and modifications based on the above-mentioned circuits do not deviate from the principle of the present disclosure, and will not be repeated here.
  • the embodiment of the present disclosure provides a multiple selection unit 11. As shown in FIGS. 9 to 12, the multiple selection unit 11 includes at least one multiple selection group, and each multiple selection group includes a plurality of the above multiple selections. Circuit.
  • each multiplexing circuit in the multiplexing unit 11 is coupled to a different selection signal terminal MUX.
  • Figs. 11 and 12 take the multiple selection unit 11 including two multiple selection groups as an example.
  • the multiple sub-pixels to be charged are arranged in a matrix as an example.
  • the sub-pixels in the same row can be coupled to one gate line GL, and the sub-pixels in the same column can be coupled to one data line DL.
  • at least one column of sub-pixels is coupled to the same data signal terminal Vs.
  • R1 and R2 represent red sub-pixels to be charged in different columns
  • G1 and G2 represent green sub-pixels to be charged in different columns
  • B1 and B2 represent blue sub-pixels to be charged in different columns.
  • the pixels in the display panel 10 are divided into odd-numbered columns and even-numbered columns.
  • R1 represents the red sub-pixel to be charged in the pixels in the odd-numbered column
  • G1 represents the green sub-pixel to be charged in the pixels in the odd-numbered column.
  • B1 represents the blue sub-pixel to be charged in the pixel in the odd column
  • R2 represents the red sub-pixel to be charged in the pixel in the even column
  • G2 represents the green sub-pixel to be charged in the pixel in the even column
  • B2 represents the The blue sub-pixels to be charged among the pixels in the even columns.
  • one selection voltage terminal Vs is configured to A sub-pixel to be charged is charged.
  • one data signal terminal Vs is configured to Six sub-pixels to be charged are charged.
  • each multiple selection circuit connected to the sub-pixel pixel to be charged has a different light emission color; each multiple selection circuit in the multiple selection unit 11 is connected to a different selection Signal terminal MUX.
  • the multiple selection unit 11 includes the number of multiple selection groups is not limited to two or three, and the number of multiple selection circuits included in each multiple selection group is also It is not limited to three, and Figs. 9-12 are only an illustration.
  • the sub-pixels to be charged that are coupled to some of the multiplexer circuits in the same multiplexer group emit the same color.
  • the light-emitting colors of the sub-pixel pixels to be charged coupled to the two multiplexer circuits in the same multiplexer group are the same; or, in one column
  • the pixel includes sub-pixels of multiple light-emitting colors, among the sub-pixels to be charged coupled to the multiple selection circuits in the same multiple selection group, some of the sub-pixels to be charged have the same light-emitting color.
  • the sub-pixel pixels to be charged coupled to each multiplexer circuit in the same multiplexer group have different light-emitting colors, that is, there will not be two multiplexer options in a multiplexer group.
  • the circuit is coupled to the sub-pixels to be charged for emitting the same color light. In this way, the number of multiple selection circuits included in a multiple selection group is less than or equal to the number of sub-pixels included in one pixel.
  • one multiplex selection group corresponds to one pixel, that is, one multiplex selection group is configured to charge the sub-pixel pixels to be charged in the same pixel.
  • a multiplex selection group corresponds to different pixels, that is, a multiplex selection group is configured to charge the sub-pixel pixels located in different pixels to be charged. In this case, the signal interference of different pixels can be avoided, and the charging quality can be improved.
  • a dashed box in FIG. 15 represents a pixel.
  • a multiple-way selection unit 11 includes a multiple-way selection group as an example for illustration.
  • a multiplexing unit 11 includes three multiplexing circuits, one row includes three pixels, and the first multiplexing circuit in the multiplexing unit 11 directs the red sub-pixel R in the first pixel to be charged.
  • the second multiplexer circuit charges the green sub-pixel G to be charged in the second pixel
  • the third multiplexer circuit charges the blue sub-pixel B to be charged in the third pixel.
  • multiple selection group and the pixel may also be in other corresponding manners, and the embodiments of the present disclosure are not limited herein.
  • the multiple selection unit 11 provided by the embodiment of the present disclosure, whether it is one multiple selection unit 11 charging three sub-pixels to be charged, or one multiple selection unit 11 charging six sub-pixels to be charged, or Other quantities. Since each multiplex circuit in the multiplexer unit 11 achieves the same charging capacity, the required charging time is often relatively short. Therefore, when the above multiple selection circuit is applied to the multiple selection unit 11, the output ports of the source driver 01 (ie, the source driver IC) can be reduced, and the data signal transmission coupled to the output port of the source driver 01 can be reduced. The number of channels, and to ensure that each sub-pixel to be charged can be fully charged to ensure the display effect.
  • multiple multiplexer circuits 110 in the multiplexer unit 11 are coupled to the same data signal terminal Vs.
  • one multiplexing unit 11 corresponds to one data signal terminal Vs, and multiplexing circuits belonging to the same multiplexing unit 11 are coupled to the same data signal terminal Vs. Therefore, the number of data signal transmission channels coupled to the output port of the source driver 01 and the data signal terminal Vs of the multiplexer circuit 110 can be reduced.
  • the multiplexing unit 11 includes two multiplexing groups, and the multiplexing group includes three multiplexing circuits 110.
  • one multiplexing unit 11 is used to charge six sub-pixels to be charged.
  • the embodiment of the present disclosure provides a display device 200, as shown in FIG. 16, comprising: a display panel 10 and at least one multiple selection unit 11 as in any of the above embodiments.
  • the multiplexing unit 11 is arranged on the base substrate 102.
  • the display panel 10 has an active display area (AA) 100 and a non-display area 101 located on at least one side of the active display area 100.
  • AA active display area
  • non-display area 101 located on at least one side of the active display area 100.
  • the above-mentioned effective display area 100 includes a plurality of sub pixels 20.
  • the sub-pixel 20 is provided with a pixel circuit 201 for controlling the sub-pixel 20 to display, and the pixel circuit 201 is provided on the base substrate 102 of the display panel.
  • the pixel circuit 201 in the sub-pixel 20 will be described as an example.
  • the display panel 10 may also be a light emitting diode display panel, or an organic light emitting diode (OLED) display panel.
  • the pixel circuit 201 includes a transistor M and a liquid crystal capacitor C.
  • the two plates of the liquid crystal capacitor C are respectively composed of a pixel electrode and a common electrode.
  • the control electrode of the transistor M is coupled to the gate line GL, the first electrode is coupled to the data line DL, and the second electrode is coupled to the liquid crystal capacitor C.
  • the transistor M is configured to transmit the data signal on the data line DL to the liquid crystal capacitor C .
  • the display device 200 further includes a source driver 01 and at least one data signal transmission channel 103.
  • the source driver 01 is bound to the base substrate 102 and is coupled to each multiplexing unit 11.
  • a multiplexing unit 11 is coupled to the source driver 01 through a data transmission channel 103.
  • an output port of the source driver 01 is coupled to the data signal terminal Vs of a multiplexer 11 through a data transmission channel 103. Therefore, the number of output ports of the source driver 01 can be reduced and the source The number of data transmission channels 103 to which the pole driver 01 is coupled to the multiplexing unit 11.
  • multiple selection unit 11 may also be integrated inside the source driver 01, and the beneficial effects are the same as the beneficial effects of the source driver unit 11, and will not be repeated here.
  • the pixels in the display panel 10 are divided into odd-numbered columns of pixels and even-numbered columns of pixels, and the sub-pixels that emit light of the same color in the odd columns are coupled to the same selection signal terminal.
  • the MUX couples the sub-pixels emitting the same color light in the even-numbered columns to the same selection signal terminal MUX. Therefore, the number of selection signal terminals MUX can be reduced.
  • the charging of the red sub-pixel R1 in the odd column is controlled by the odd red selection signal terminal MUXR1
  • the charging of the red sub-pixel R2 in the even column is controlled by the even red selection signal terminal.
  • MUXR2 control Taking the green sub-pixel as an example, the charging of the odd-numbered green sub-pixel G1 to be charged is controlled by the odd-numbered green selection signal terminal MUXG1, and the even-numbered column of green sub-pixel G2 to be charged is controlled by the even-numbered green selection signal terminal.
  • MUXG2 control Taking the red sub-pixel as an example, the charging of the red sub-pixel R1 in the odd column is controlled by the odd red selection signal terminal MUXR1, and the even-numbered column of green sub-pixel G2 to be charged is controlled by the even-numbered green selection signal terminal.
  • the charging of the blue sub-pixels B1 in odd columns is controlled by the odd blue selection signal terminal MUXB1
  • the charging of the blue sub-pixels B2 in even columns is controlled by even The blue selection signal terminal MUXB2 control.
  • one of the two multiplexer groups is coupled to the sub-pixels to be charged of pixels in odd columns, and the other multiplexer group is coupled to the pixels to be charged in even columns. Charging sub-pixel pixel coupling.
  • the gate lines GL are turned on row by row. After each row of the gate lines GL is turned on, the working process of the multiplexing unit 11 is the same. Therefore, the first row of gate lines GL is turned on here. After that, the working process of the multiple selection unit 11 will be illustrated by an example.
  • R1-1 represents the timing of the red sub-pixel R1 to be charged in the odd column among the first six sub-pixels to be charged coupled to the multiple selection unit 11 on the left in FIG. 17, and R2-1 represents Among the first six sub-pixels to be charged that are coupled to the multiple selection unit 11 on the left in FIG. 17, the timing of the red sub-pixels to be charged R2 in the even-numbered column.
  • R1-2 represents the multiple selection on the right in FIG. Among the first six sub-pixels to be charged that are coupled to the unit 11, the timing of the red sub-pixels to be charged R1 in an odd-numbered column, R2-2 represents the first six coupled to the multiple selection unit 11 on the right in FIG.
  • B1-1 shows the timing of the blue sub-pixel B1 to be charged in the odd-numbered column among the first six sub-pixels to be charged coupled by the multiple selection unit 11 on the left in FIG. 17, and B2-1 shows the diagram Among the first six sub-pixels to be charged that are coupled to the multiple selection unit 11 on the left in 17, the timing of the blue sub-pixel to be charged B2 in the even-numbered column.
  • B1-2 represents the multiple selection on the right in FIG. Among the first six sub-pixels to be charged that are coupled to the unit 11, the timing of the blue sub-pixel to be charged B1 in the odd-numbered column.
  • B2-2 represents the first six that are coupled to the multiplexer unit 11 on the right in FIG.
  • the timing of the blue sub-pixels B2 to be charged in the even-numbered column G1-1 shows the timing of the green sub-pixel G1 to be charged in the odd-numbered column among the first six sub-pixels to be charged coupled by the multiple selection unit 11 on the left in FIG. 17, and G2-1 shows the timing of FIG.
  • G1-2 represents the multiplexing unit 11 on the right in FIG.
  • the timing of the green sub-pixel G1 in the odd-numbered column to be charged is Among the first six coupled sub-pixels to be charged, the timing of the green sub-pixel G1 in the odd-numbered column to be charged.
  • G2-2 represents the first six to be charged coupled to the multiplex unit 11 on the right in FIG. In the sub-pixel pixel, the timing of the green sub-pixel G2 to be charged in the even-numbered column.
  • the odd red selection signal terminal MUXR1, the odd green selection signal terminal MUXG1, the odd blue selection signal terminal MUXB1, the even red selection signal terminal MUXR2, the even green selection signal terminal MUXG2, and the even blue selection signal terminal MUXB2 are in sequence Input the enable signal
  • the data signal terminal Vs1 coupled to the left multiple selection unit 11 inputs the data signal when the odd red selection signal terminal MUXR1 and the even red selection signal terminal MUXR2 input the opening signal, and is coupled to the left multiple selection unit 11
  • the red sub-pixel R1 in the odd-numbered column and the red sub-pixel R2 in the even-numbered column are charged, and the remaining four sub-pixels to be charged are not charged.
  • the data signal terminal Vs2 coupled to the multiple selection unit 11 on the right inputs a data signal when the even-numbered blue selection signal terminal MUXB2 inputs the turn-on signal, and is coupled to the last six sub-pixel pixels to be charged that are coupled to the multiple selection unit 11 on the right , The blue sub-pixel B2 to be charged in the even-numbered column is charged, and the remaining five sub-pixels to be charged are not charged.
  • FIG. 18 is only a schematic diagram of the signal timing of the data signal terminal Vs1 coupled to the multiple selection unit 11 on the left and the data signal terminal Vs2 coupled to the multiple selection unit 11 on the right in FIG. 17, but in practical applications Not limited to this.
  • the signals of the data signal terminal Vs1 coupled to the multiple selection unit 11 on the left and the data signal terminal Vs2 coupled to the multiple selection unit 11 on the right may be high.
  • the potentials of the high-level signals required for charging different sub-pixels to be charged are not completely equal.
  • the signal of the odd-numbered red selection signal terminal MUXR1 is a high-level signal
  • the signal received at the data signal terminal Vs1 coupled to the multiple selection unit 11 on the left is a high-level signal
  • the red sub-pixels R1 to be charged in odd-numbered columns start to be charged.
  • the left multiplexing unit 11 is coupled Among the first six sub-pixels to be charged, the red sub-pixel R1 to be charged in the odd column is still charged. At this time, among the first six sub-pixels to be charged that are coupled to the multiple selection unit 11 on the left, the charging time of the red sub-pixels R1 to be charged in the odd column is longer than the data signal coupled to the multiple selection unit 11 on the left. The length of time that the signal received at the terminal Vs1 is high.
  • the charging time period of the sub-pixel pixel to be charged is longer than the valid time period of the signal of the selection signal terminal MUX.
  • the multiplexing unit 11 repeats the above process.
  • the above-mentioned display device 200 may be any device that displays images whether in motion (for example, video) or fixed (for example, still images), and regardless of text or images. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs) , Handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, car monitors (e.g., Odometer display, etc.), navigator, cockpit controller and/or display, camera view display (for example, the display of a rear-view camera in a vehicle), electronic photos, electronic billboards or signs, projectors, building structures, packaging And aesthetic structure (for example, a display of the image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • Handheld or portable computers GPS receivers/navigators,
  • the multiplexer circuit 110 includes a charging sub-circuit 40, a control sub-circuit 50 and a delay sub-circuit 30.
  • the charging sub-circuit 40 is coupled to the selection signal terminal MUX, the data signal terminal Vs and the sub-pixel pixel to be charged;
  • the control sub-circuit 50 is coupled to the selection signal terminal MUX and the data signal terminal Vs;
  • the delay sub-circuit 30 is coupled to the sub-pixel to be charged
  • the pixel is coupled to the control sub-circuit 50.
  • the driving method of the multiple selection circuit 110 includes:
  • the selection signal terminal MUX inputs the turn-on signal, and the charging sub-circuit 40 transmits the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged under the control of the signal received at the selection signal terminal MUX; the control sub-circuit 50 is at Under the control of the signal received at the selection signal terminal MUX, the signal received at the data signal terminal Vs is transmitted; the delay sub-circuit 30 delays the transmission of the signal received at the data signal terminal Vs transmitted through the control sub-circuit 50, and is After the electronic circuit 40 charges the sub-pixel pixel to be charged for a preset time, the delay sub-circuit 30 transmits the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged.
  • the selection signal terminal MUX inputs a cut-off signal
  • the charging sub-circuit 40 and the control sub-circuit 50 are cut off under the control of the signal received at the selection signal terminal MUX
  • the delay sub-circuit 30 continues to transmit the signal received at the data signal terminal Vs to Sub-pixel pixel to be charged.

Abstract

Disclosed is a multi-path selection circuit (110), comprising: a charging sub-circuit (40), a control sub-circuit (50) and a delay sub-circuit (30), wherein the charging sub-circuit (40) is respectively coupled to a selection signal end (MUX), a data signal end (Vs) and a sub-pixel (pixel) to be charged, and under the control of a signal received at the selection signal end (MUX), the charging sub-circuit (40) transmits a signal received at the data signal end (Vs) to the sub-pixel (pixel) to be charged; the control sub-circuit (50) is respectively coupled to the selection signal end (MUX) and the data signal end (Vs), and under the control of the signal received at the selection signal end (MUX), the control sub-circuit (50) transmits the signal received at the data signal end (Vs); the delay sub-circuit (30) is respectively coupled to the sub-pixel (pixel) to be charged and the control sub-circuit (50), and the delay sub-circuit (30) performs delayed transmission on the signal received at the data signal end (Vs) and transmitted by means of the control sub-circuit (50), and transmits the signal of the data signal end (Vs) to the sub-pixel (pixel) to be charged after the charging sub-circuit (40) charges the sub-pixel (pixel) to be charged for a preset time.

Description

多路选择电路及驱动方法、多路选择单元、显示装置Multiplex selection circuit and drive method, multiplex selection unit and display device
本申请要求于2019年03月26日提交的、申请号为201910232613.0的中国专利申请的优先权,其全部内容通过引用结合在本申请中。This application claims the priority of the Chinese patent application with application number 201910232613.0 filed on March 26, 2019, the entire content of which is incorporated into this application by reference.
技术领域Technical field
本公开涉及显示技术领域,尤其涉及一种多路选择电路及驱动方法、多路选择单元、显示装置。The present disclosure relates to the field of display technology, and in particular to a multiplex selection circuit and driving method, multiplex selection unit, and display device.
背景技术Background technique
显示装置内部设置有多个亚像素,通过控制亚像素的显示,来实现画面显示。其中,显示装置的每个亚像素内设置有用于控制亚像素进行显示的像素电路,像素电路在栅线提供的扫描信号和数据线提供的数据信号的控制下,控制亚像素显示。A plurality of sub-pixels are arranged inside the display device, and the screen display is realized by controlling the display of the sub-pixels. Wherein, each sub-pixel of the display device is provided with a pixel circuit for controlling the sub-pixel to display, and the pixel circuit controls the sub-pixel display under the control of the scan signal provided by the gate line and the data signal provided by the data line.
发明内容Summary of the invention
一方面,提供一种多路选择电路。所述多路选择电路包括充电子电路、控制子电路和延时子电路。所述充电子电路分别与选择信号端、数据信号端和待充电亚像素耦接,所述充电子电路被配置为,在所述选择信号端处接收的信号的控制下,将在所述数据信号端处接收的信号传输至所述待充电亚像素;所述控制子电路分别与所述选择信号端和所述数据信号端耦接,所述控制子电路被配置为,在所述选择信号端处接收的信号的控制下,传输在所述数据信号端处接收的信号;所述延时子电路分别与所述待充电亚像素和所述控制子电路耦接,所述延时子电路被配置为,将经过所述控制子电路传输的在所述数据信号端处接收的信号延迟传输,在所述充电子电路向所述待充电亚像素充电预设时间后,将在所述数据信号端处接收的信号传输至所述待充电亚像素。On the one hand, a multiple selection circuit is provided. The multiple selection circuit includes a charging sub-circuit, a control sub-circuit and a delay sub-circuit. The charging sub-circuit is respectively coupled to the selection signal terminal, the data signal terminal and the sub-pixel to be charged, and the charging sub-circuit is configured to, under the control of the signal received at the selection signal terminal, load the data The signal received at the signal terminal is transmitted to the sub-pixel to be charged; the control sub-circuit is respectively coupled to the selection signal terminal and the data signal terminal, and the control sub-circuit is configured to: Under the control of the signal received at the terminal, the signal received at the data signal terminal is transmitted; the delay sub-circuit is respectively coupled to the sub-pixel to be charged and the control sub-circuit, the delay sub-circuit Is configured to delay the transmission of the signal received at the data signal terminal transmitted through the control sub-circuit, and after the charging sub-circuit charges the sub-pixel to be charged for a preset time, the data The signal received at the signal terminal is transmitted to the sub-pixel to be charged.
在一些实施例中,所述延时子电路包括:第三晶体管、第四晶体管和第一电容。所述第三晶体管的控制极与控制信号端耦接,所述第三晶体管的第一极与所述控制子电路耦接;所述第四晶体管的控制极与所述第三晶体管的第二极耦接,所述第四晶体管的第一极与所述控制子电路耦接,所述第四晶体管的第二极与所述待充电亚像素耦接;所述第一电容的第一端分别与所述控制子电路、所述第三晶体管的第一极和所述第四晶体管的第一极耦接,所述第一电容的第二端与第一电压端耦接。In some embodiments, the delay sub-circuit includes: a third transistor, a fourth transistor and a first capacitor. The control electrode of the third transistor is coupled to the control signal terminal, the first electrode of the third transistor is coupled to the control sub-circuit; the control electrode of the fourth transistor is connected to the second terminal of the third transistor. The first electrode of the fourth transistor is coupled to the control sub-circuit, and the second electrode of the fourth transistor is coupled to the sub-pixel to be charged; the first terminal of the first capacitor Are respectively coupled to the control sub-circuit, the first pole of the third transistor and the first pole of the fourth transistor, and the second terminal of the first capacitor is coupled to the first voltage terminal.
在一些实施例中,所述第四晶体管的沟道的宽长比大于所述第三晶体管的沟道的宽长比。In some embodiments, the aspect ratio of the channel of the fourth transistor is greater than the aspect ratio of the channel of the third transistor.
在一些实施例中,所述延时子电路还包括第二电容。所述第二电容的第一端分别与所述第四晶体管的第二极和所述待充电亚像素耦接,所述第二电容的第二端与所述第一电压端耦接。In some embodiments, the delay sub-circuit further includes a second capacitor. The first terminal of the second capacitor is respectively coupled to the second electrode of the fourth transistor and the sub-pixel to be charged, and the second terminal of the second capacitor is coupled to the first voltage terminal.
在一些实施例中,所述控制子电路包括第二晶体管。所述第二晶体管的控制极与所述选择信号端耦接,所述第二晶体管的第一极与所述数据信号端耦接,所述第二晶体管的第二极与所述延时子电路耦接。In some embodiments, the control sub-circuit includes a second transistor. The control electrode of the second transistor is coupled to the selection signal terminal, the first electrode of the second transistor is coupled to the data signal terminal, and the second electrode of the second transistor is coupled to the delay element. Circuit coupling.
在一些实施例中,所述充电子电路包括第一晶体管。所述第一晶体管的控制极与所述选择信号端耦接,所述第一晶体管的第一极与所述数据信号端耦接,所述第一晶体管的第二极与所述待充电亚像素耦接。In some embodiments, the charging sub-circuit includes a first transistor. The control electrode of the first transistor is coupled to the selection signal terminal, the first electrode of the first transistor is coupled to the data signal terminal, and the second electrode of the first transistor is connected to the sub-to-be-charged. Pixel coupling.
在一些实施例中,所述多路选择电路还包括存储子电路。所述存储子电路分别与所述充电子电路、所述待充电亚像素和第一电压端耦接,所述存储子电路被配置为,对所述充电子电路传输的在所述数据信号端处接收的信号进行存储,及,将所存储的信号传输至所述待充电亚像素。In some embodiments, the multiple selection circuit further includes a storage sub-circuit. The storage sub-circuit is respectively coupled to the charging sub-circuit, the sub-pixel to be charged and the first voltage terminal, and the storage sub-circuit is configured to transmit data to the charging sub-circuit at the data signal terminal Storing the signal received there, and transmitting the stored signal to the sub-pixel to be charged.
在一些实施例中,所述存储子电路包括第三电容。所述第三电容的第一端分别与所述充电子电路和所述待充电亚像素耦接,所述第三电容的第二端与所述第一电压端耦接。In some embodiments, the storage sub-circuit includes a third capacitor. The first terminal of the third capacitor is respectively coupled to the charging sub-circuit and the sub-pixel to be charged, and the second terminal of the third capacitor is coupled to the first voltage terminal.
另一方面,提供一种多路选择单元。所述多路选择单元包括:至少一个多路选择组。所述多路选择组包括多个如上述任一实施例所述的多路选择电路;所述多路选择单元中的每个所述多路选择电路耦接不同的选择信号端。On the other hand, a multiple selection unit is provided. The multiple selection unit includes: at least one multiple selection group. The multiple selection group includes a plurality of multiple selection circuits as described in any of the foregoing embodiments; each of the multiple selection circuits in the multiple selection unit is coupled to a different selection signal terminal.
在一些实施例中,所述多路选择组中的每个多路选择电路耦接的待充电亚像素的发光颜色不同。In some embodiments, the light-emitting colors of the sub-pixels to be charged coupled to each multiplex selection circuit in the multiplex selection group are different.
在一些实施例中,所述多路选择单元中的多个所述多路选择电路耦接同一数据信号端。In some embodiments, a plurality of the multiple selection circuits in the multiple selection unit are coupled to the same data signal terminal.
在一些实施例中,所述多路选择单元包括两个所述多路选择组,所述多路选择组包括三个所述多路选择电路。In some embodiments, the multiplexing unit includes two multiplexing groups, and the multiplexing group includes three multiplexing circuits.
在一些实施例中,两个所述多路选择组中的一个多路选择组与奇数列像素的待充电亚像素耦接,另一个多路选择组与偶数列像素的待充电亚像素耦接。In some embodiments, one of the two multiplexer groups is coupled to the sub-pixels of the odd-numbered columns of pixels, and the other multiplexer group is coupled to the sub-pixels of the even-numbered columns of pixels. .
又一方面,提供一种显示装置。所述显示装置包括至少一个如上述任一实施例所述的多路选择单元和显示面板。所述显示面板包括衬底基板;所述多路选择单元设置于所述衬底基板上。In another aspect, a display device is provided. The display device includes at least one multiple selection unit and a display panel as described in any of the above embodiments. The display panel includes a base substrate; the multiple selection unit is arranged on the base substrate.
在一些实施例中,所述显示装置还包括源极驱动器和至少一个数据信号 传输通道。所述源极驱动器与所述衬底基板绑定,并与各所述多路选择单元耦接;所述数据信号传输通道设置于所述衬底基板上,一个所述多路选择单元通过一个数据传输通道与所述源极驱动器耦接。In some embodiments, the display device further includes a source driver and at least one data signal transmission channel. The source driver is bound to the base substrate, and is coupled to each of the multiple selection units; the data signal transmission channel is arranged on the base substrate, and one multiple selection unit passes through one The data transmission channel is coupled to the source driver.
在一些实施例中,在所述多路选择单元包括多个多路选择组的情况下,多个数据信号端通过一条信号线与所述源极驱动器耦接。In some embodiments, in the case where the multiplexer unit includes multiple multiplexer groups, multiple data signal terminals are coupled to the source driver through one signal line.
再一方面,提供一种如上述任一实施例所述的多路选择电路的驱动方法,包括:选择信号端输入开启信号,充电子电路在所述选择信号端处接收的信号的控制下,将在数据信号端处接收的信号传输至待充电亚像素;控制子电路在所述选择信号端处接收的信号的控制下,传输在所述数据信号端处接收的信号;延时子电路将经过所述控制子电路传输的在所述数据信号端处接收的信号延迟传输,在所述充电子电路向所述待充电亚像素充电预设时间后,所述延时子电路将在所述数据信号端处接收的信号传输至所述待充电亚像素;所述选择信号端输入截止信号,所述充电子电路和所述控制子电路在所述选择信号端处接收的信号的控制下截止,所述延时子电路继续将在所述数据信号端处接收的信号传输至所述待充电亚像素。In still another aspect, a method for driving a multiple selection circuit as described in any of the above embodiments is provided, which includes: inputting a turn-on signal at the selection signal terminal, and the charging sub-circuit under the control of the signal received at the selection signal terminal, The signal received at the data signal terminal is transmitted to the sub-pixel to be charged; the control sub-circuit transmits the signal received at the data signal terminal under the control of the signal received at the selection signal terminal; the delay sub-circuit will The signal received at the data signal terminal transmitted through the control sub-circuit is delayed in transmission. After the charging sub-circuit charges the sub-pixel to be charged for a preset time, the delay sub-circuit will The signal received at the data signal terminal is transmitted to the sub-pixel to be charged; the selection signal terminal inputs a cut-off signal, and the charging sub-circuit and the control sub-circuit cut off under the control of the signal received at the selection signal terminal , The delay sub-circuit continues to transmit the signal received at the data signal terminal to the sub-pixel to be charged.
附图说明Description of the drawings
为了更清楚地说明本公开中的技术方案,下面将对本公开一些实施例中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本公开的一些实施例的附图,对于本领域普通技术人员来讲,还可以根据这些附图获得其他的附图。此外,以下描述中的附图可以视作示意图,并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。In order to explain the technical solutions of the present disclosure more clearly, the following will briefly introduce the drawings that need to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are merely appendices to some embodiments of the present disclosure. Figures, for those of ordinary skill in the art, other drawings can be obtained based on these drawings. In addition, the drawings in the following description may be regarded as schematic diagrams, and are not limitations on the actual size of the products involved in the embodiments of the present disclosure, the actual process of the method, and the actual timing of the signals.
图1为根据一些实施例的显示装置的一种结构图;FIG. 1 is a structural diagram of a display device according to some embodiments;
图2为根据一些实施例的显示装置的另一种结构图;FIG. 2 is another structural diagram of a display device according to some embodiments;
图3为根据相关技术的显示装置的一种结构图;Fig. 3 is a structural diagram of a display device according to the related art;
图4为根据相关技术的显示装置的另一种结构图;FIG. 4 is another structural diagram of a display device according to the related art;
图5为根据一些实施例的多路选择电路的一种结构图;Fig. 5 is a structural diagram of a multiple selection circuit according to some embodiments;
图6为根据一些实施例的多路选择电路的另一种结构图;Fig. 6 is another structural diagram of a multiple selection circuit according to some embodiments;
图7为根据一些实施例的多路选择电路的又一种结构图;FIG. 7 is another structural diagram of a multiple selection circuit according to some embodiments;
图8为根据一些实施例的多路选择电路的又一种结构图;Fig. 8 is another structural diagram of a multiple selection circuit according to some embodiments;
图9为根据一些实施例的多路选择单元的一种结构图;Fig. 9 is a structural diagram of a multiple selection unit according to some embodiments;
图10为根据一些实施例的多路选择单元的另一种结构图;Fig. 10 is another structural diagram of a multiple selection unit according to some embodiments;
图11为根据一些实施例的多路选择单元的又一种结构图;FIG. 11 is another structural diagram of a multiple selection unit according to some embodiments;
图12为根据一些实施例的多路选择单元的又一种结构图;Fig. 12 is another structural diagram of a multiple selection unit according to some embodiments;
图13为根据一些实施例的显示面板的一种结构图;FIG. 13 is a structural diagram of a display panel according to some embodiments;
图14为根据一些实施例的显示面板的另一种结构图;FIG. 14 is another structural diagram of a display panel according to some embodiments;
图15为根据一些实施例的显示面板的又一种结构图;FIG. 15 is another structural diagram of a display panel according to some embodiments;
图16为根据一些实施例的显示装置的又一种结构图;FIG. 16 is another structural diagram of a display device according to some embodiments;
图17为根据一些实施例的显示装置的又一种结构图;FIG. 17 is another structural diagram of a display device according to some embodiments;
图18为根据一些实施例的多路选择单元的一种驱动时序图;FIG. 18 is a driving timing diagram of the multiple selection unit according to some embodiments;
图19为根据一些实施例的多路选择单元的一种驱动流程图。Fig. 19 is a driving flowchart of a multiple selection unit according to some embodiments.
具体实施方式detailed description
下面将结合附图,对本公开一些实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本公开一部分实施例,而不是全部的实施例。基于本公开所提供的实施例,本领域普通技术人员所获得的所有其他实施例,都属于本公开保护的范围。The technical solutions in some embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art fall within the protection scope of the present disclosure.
除非上下文另有要求,否则,在整个说明书和权利要求书中,术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思,即为“包含,但不限于”。在说明书的描述中,术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外,所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms such as the third-person singular form "comprises" and the present participle form "comprising" are Interpreted as open and inclusive means "including, but not limited to." In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" "example)" or "some examples" are intended to indicate that a specific feature, structure, material, or characteristic related to the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any suitable manner.
以下,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中,除非另有说明,“多个”的含义是两个或两个以上。Hereinafter, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
在描述一些实施例时,可能使用了“耦接”和“连接”及其衍伸的表达。例如,描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如,描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而,术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触,但仍彼此协作或相互作用。这里所公开的实施 例并不必然限制于本文内容。In describing some embodiments, the expressions "coupled" and "connected" and their extensions may be used. For example, the term "connected" may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. As another example, the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义,均包括以下A、B和C的组合:仅A,仅B,仅C,A和B的组合,A和C的组合,B和C的组合,及A、B和C的组合。"At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
此外,本公开中,“上”、“下”、“左”、“右”、“水平”以及“竖直”等方位术语是相对于附图中的部件示意置放的方位来定义的,应当理解到,这些方向性术语是相对的概念,它们用于相对于的描述和澄清,其可以根据附图中部件所放置的方位的变化而相应地发生变化。In addition, in the present disclosure, the azimuth terms such as "upper", "lower", "left", "right", "horizontal" and "vertical" are defined relative to the directions in which the components in the drawings are schematically placed. It should be understood that these directional terms are relative concepts, and they are used for relative description and clarification, which can be changed correspondingly according to the changes in the orientation of the components in the drawings.
相关技术中,如图3所示,显示面板10'中的每根数据线DL上均需接收数据信号。以显示面板10'包括1080列亚像素20'为例,有1080根数据线DL需要接收数据信号,为数据线DL提供数据信号的源极驱动器01'(即源极驱动IC(Source IC))需要有1080个输出端口,导致显示装置200'中源极驱动器01'的制备成本增加,且占用面积增加。In the related art, as shown in FIG. 3, each data line DL in the display panel 10' needs to receive a data signal. Taking the display panel 10' including 1080 columns of sub-pixels 20' as an example, there are 1080 data lines DL that need to receive data signals, and the source driver 01' (Source IC) that provides data signals for the data lines DL 1080 output ports are required, which leads to an increase in the manufacturing cost of the source driver 01' in the display device 200' and an increase in the occupied area.
为了减少源极驱动器01'输出数据信号的端口的总数,通常采用多路选择电路110'对信号进行转换,对亚像素20'进行充电。例如,如图3所示,多路选择电路110'通过控制红色选择信号端MUXR、绿色选择信号端MUXG、蓝色选择信号端MUXB的电平,使第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3依次开启,依次传输数据信号端Vs的信号,实现对红色亚像素R、绿色亚像素G、蓝色亚像素B的充电。位于同一像素的三个亚像素连接同一个数据信号端Vs,这样一来,源极驱动器01'的输出端口的数量可以减少到原来的三分之一。In order to reduce the total number of ports through which the source driver 01' outputs data signals, a multiplexer circuit 110' is usually used to convert the signals and charge the sub-pixels 20'. For example, as shown in FIG. 3, the multiple selection circuit 110' controls the levels of the red selection signal terminal MUXR, the green selection signal terminal MUXG, and the blue selection signal terminal MUXB so that the first thin film transistor M1 and the second thin film transistor M2 , The third thin film transistor M3 is turned on sequentially, and sequentially transmits the signal of the data signal terminal Vs to realize charging of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B. Three sub-pixels located in the same pixel are connected to the same data signal terminal Vs. In this way, the number of output ports of the source driver 01' can be reduced to one third of the original number.
在此基础上,由于窄边框显示装置已经成为当下流行的趋势,因此,为了减小显示装置的边框占比,实现超窄边框的全面屏。图4示出了多路选择电路110'通过一个数据信号端Vs接收信号,为6个亚像素20'充电的方案,选择信号端依次开启,依次为6个亚像素20'充电,从而可降低源极驱动器01'成本与尺寸,以实现超窄边框的全面屏。On this basis, since narrow-frame display devices have become a popular trend nowadays, in order to reduce the frame ratio of the display device, a full screen with ultra-narrow bezels is realized. FIG. 4 shows a scheme in which the multiple selection circuit 110' receives a signal through a data signal terminal Vs and charges 6 sub-pixels 20'. The selection signal terminal is turned on in turn, and the 6 sub-pixels 20' are sequentially charged, thereby reducing Source driver 01' cost and size to achieve a full screen with ultra-narrow bezel.
然而,虽然源极驱动器01'输出端口的数量减少,但每个亚像素20'需要的充电时间是固定的,若是减少每个亚像素20的充电时间,就会导致亚像素20'充电不足,影响显示效果。However, although the number of output ports of the source driver 01' is reduced, the charging time required for each sub-pixel 20' is fixed. If the charging time of each sub-pixel 20 is reduced, the sub-pixel 20' will be undercharged. Affect the display effect.
示例性地,一根数据线DL的充电总时间为3.6us,如果多路选择电路110'通过一个数据信号端Vs接收信号,为3个亚像素20'充电,每个亚像素20'的充电时间为1.2us,还可以保证显示装置的正常显示。但如果采用多路选择电路110'通过一个数据信号端Vs接收信号,为6个亚像素20'充电的方案,每 个亚像素20'的充电时间为0.6us,充电时间缩短一半,导致亚像素20'充电不足,显示效果就会变差。Exemplarily, the total charging time of one data line DL is 3.6 us. If the multiplex circuit 110' receives a signal through a data signal terminal Vs, it charges three sub-pixels 20', and each sub-pixel 20' charges The time is 1.2us, which can also guarantee the normal display of the display device. However, if the multiplexer circuit 110' receives signals through a data signal terminal Vs and charges the 6 sub-pixels 20', the charging time of each sub-pixel 20' is 0.6us, and the charging time is reduced by half, resulting in sub-pixels If the charging is insufficient at 20', the display effect will deteriorate.
本公开的实施例提供一种多路选择电路110,如图5所示,包括:充电子电路40、控制子电路50和延时子电路30。The embodiment of the present disclosure provides a multiple selection circuit 110, as shown in FIG. 5, including: a charging sub-circuit 40, a control sub-circuit 50, and a delay sub-circuit 30.
充电子电路40分别与选择信号端MUX、数据信号端Vs和待充电亚像素pixel耦接。The charging sub-circuit 40 is respectively coupled to the selection signal terminal MUX, the data signal terminal Vs and the sub-pixel to be charged.
控制子电路50分别与选择信号端MUX和数据信号端Vs耦接。The control sub-circuit 50 is respectively coupled to the selection signal terminal MUX and the data signal terminal Vs.
延时子电路30分别与待充电亚像素pixel和控制子电路50耦接。The delay sub-circuit 30 is respectively coupled to the sub-pixel to be charged and the control sub-circuit 50.
充电子电路40被配置为在选择信号端MUX处接收的信号的控制下,将在数据信号端Vs处接收的信号传输至待充电亚像素pixel。The charging sub-circuit 40 is configured to transmit the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged under the control of the signal received at the selection signal terminal MUX.
可以理解的是,充电子电路40实际是将在数据信号端Vs处接收的信号传输至像素电路,以控制待充电亚像素pixel显示。以图2所示的像素电路201为例,充电子电路40是将在数据信号端Vs处接收的信号传输至数据线DL,进而传输至像素电路201中晶体管M的第一极。It is understandable that the charging sub-circuit 40 actually transmits the signal received at the data signal terminal Vs to the pixel circuit to control the display of the sub-pixel pixel to be charged. Taking the pixel circuit 201 shown in FIG. 2 as an example, the charging sub-circuit 40 transmits the signal received at the data signal terminal Vs to the data line DL, and then to the first pole of the transistor M in the pixel circuit 201.
示例性地,待充电亚像素pixel可以是显示面板10中的任一亚像素20,例如可以是红色亚像素R、绿色亚像素G或者蓝色亚像素B等。Exemplarily, the sub-pixel pixel to be charged may be any sub-pixel 20 in the display panel 10, for example, it may be a red sub-pixel R, a green sub-pixel G, or a blue sub-pixel B.
控制子电路50被配置为在选择信号端MUX处接收的信号的控制下,传输在数据信号端Vs处接收的信号。The control sub-circuit 50 is configured to transmit the signal received at the data signal terminal Vs under the control of the signal received at the selection signal terminal MUX.
需要说明的是,控制子电路50实质上相当于一个开关,任何能达到与控制子电路50效果相同的结构均属于本申请保护的范围。It should be noted that the control sub-circuit 50 is substantially equivalent to a switch, and any structure that can achieve the same effect as the control sub-circuit 50 belongs to the protection scope of the present application.
延时子电路30被配置为将经过控制子电路50传输的在数据信号端Vs处接收的信号延迟传输,在充电子电路40向待充电亚像素pixel充电预设时间后,将在数据信号端Vs处接收的信号传输至待充电亚像素pixel。The delay sub-circuit 30 is configured to delay the transmission of the signal received at the data signal terminal Vs transmitted through the control sub-circuit 50. After the charging sub-circuit 40 charges the sub-pixel pixel to be charged for a preset time, it will be at the data signal terminal. The signal received at Vs is transmitted to the sub-pixel pixel to be charged.
需要说明的是,延时子电路30向待充电亚像素pixel充电的时间,相对于充电子电路40向待充电亚像素pixel充电的时间延迟,延迟的时间即为预设时间。示例性地,当延时子电路30向待充电亚像素pixel充电开始时,充电子电路40向待充电亚像素pixel的充电还未结束,或者,当延时子电路30向待充电亚像素pixel充电开始的同时,充电子电路40向待充电亚像素pixel的充电结束。It should be noted that the time that the delay sub-circuit 30 charges the sub-pixel pixel to be charged is delayed relative to the time that the charging sub-circuit 40 charges the sub-pixel pixel to be charged, and the delayed time is the preset time. Exemplarily, when the delay sub-circuit 30 starts charging the sub-pixel pixel to be charged, the charging sub-circuit 40 has not finished charging the sub-pixel pixel to be charged, or when the delay sub-circuit 30 charges the sub-pixel pixel to be charged At the same time as the charging starts, the charging of the sub-pixel pixel to be charged by the charging sub-circuit 40 ends.
可以理解的是,来自控制子电路50的信号即为该控制子电路50在数据信号端Vs处接收的信号。It can be understood that the signal from the control sub-circuit 50 is the signal received by the control sub-circuit 50 at the data signal terminal Vs.
在此基础上,在选择信号端MUX处接收的信号控制下,充电子电路40将在数据信号端Vs处接收的信号传输至待充电亚像素pixel,同时,控制子电 路50将在数据信号端Vs处接收的信号传输至延时子电路30,但此时,延时子电路30并未将在数据信号端Vs处接收的信号传输至待充电亚像素pixel。在充电子电路40向待充电亚像素pixel充电预设时间后,延时子电路30将在数据信号端Vs处接收的信号传输至待充电亚像素pixel,此时,充电子电路40向待充电亚像素pixel充电还未结束。当充电子电路40的充电时间结束时,在选择信号端MUX处接收的信号的控制下,充电子电路40关闭,充电子电路40停止向待充电亚像素pixel充电,控制子电路50停止将在数据信号端Vs处接收的信号进行传输,此时,延时子电路30继续将来自控制子电路50的信号,即,在数据信号端Vs处接收的信号传输至待充电亚像素pixel。On this basis, under the control of the signal received at the selection signal terminal MUX, the charging sub-circuit 40 transmits the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged, and at the same time, the control sub-circuit 50 will be at the data signal terminal The signal received at Vs is transmitted to the delay sub-circuit 30, but at this time, the delay sub-circuit 30 does not transmit the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged. After the charging sub-circuit 40 charges the sub-pixel pixel to be charged for a preset time, the delay sub-circuit 30 transmits the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged. At this time, the charging sub-circuit 40 sends the The sub-pixel pixel charging is not over yet. When the charging time of the charging sub-circuit 40 ends, under the control of the signal received at the selection signal terminal MUX, the charging sub-circuit 40 is closed, the charging sub-circuit 40 stops charging the sub-pixel pixel to be charged, and the control sub-circuit 50 stops at The signal received at the data signal terminal Vs is transmitted. At this time, the delay sub-circuit 30 continues to transmit the signal from the control sub-circuit 50, that is, the signal received at the data signal terminal Vs to the sub-pixel to be charged.
需要说明的是,本公开的实施例不对延时子电路30的具体结构进行限定,能够起到将信号延时传输作用的子电路结构均属于本公开的保护范围。并且,延时子电路30对信号进行延时后,对待充电亚像素pixel充电时能够持续充电的时间,与延时子电路30的具体结构有关,可以根据需要合理设置。It should be noted that the embodiment of the present disclosure does not limit the specific structure of the delay sub-circuit 30, and the sub-circuit structure capable of delaying signal transmission belongs to the protection scope of the present disclosure. Moreover, after the delay sub-circuit 30 delays the signal, the time that the sub-pixel pixel to be charged can continue to be charged is related to the specific structure of the delay sub-circuit 30 and can be set reasonably according to needs.
例如,选择信号端MUX开启的时间为0.6us,通过设置延时子电路30的结构,使得延时子电路30对在数据信号端Vs处接收的信号进行延时后,对待充电亚像素pixel充电时能够持续充电的时间也为0.6us。这样一来,为每个亚像素充电花费的时间为0.6us,但达到的效果与花费1.2us充电的效果相同。For example, the selection signal terminal MUX is turned on for 0.6us, and the delay sub-circuit 30 is configured so that the delay sub-circuit 30 delays the signal received at the data signal terminal Vs, and then charges the sub-pixel pixel to be charged. The time that can be continuously charged is also 0.6us. In this way, it takes 0.6us to charge each sub-pixel, but the effect achieved is the same as that of 1.2us.
也就是说,本公开的实施例中的多路选择电路110中,充电子电路40和延时子电路30均用于向待充电亚像素pixel传输数据电压信号。充电子电路40和延时子电路30虽然同时接收到数据信号端Vs上的信号,但两者是在不同时刻将数据信号端Vs的信号传输至待充电亚像素pixel的,延时子电路30将信号延迟传输至待充电亚像素pixel。因此,在选择信号端MUX处接收的信号控制充电子电路40开启的时间缩短,即,充电子电路40对待充电亚像素pixel的充电时间缩短的情况下,延时子电路30延时传输数据信号端Vs的信号,使得待充电亚像素pixel的充电时间延长,保证了对待充电亚像素pixel的充电效果。In other words, in the multiplexer circuit 110 in the embodiment of the present disclosure, the charging sub-circuit 40 and the delay sub-circuit 30 are both used to transmit the data voltage signal to the sub-pixel pixel to be charged. Although the charging sub-circuit 40 and the delay sub-circuit 30 receive the signal on the data signal terminal Vs at the same time, they both transmit the signal of the data signal terminal Vs to the sub-pixel pixel to be charged at different times. The delay sub-circuit 30 Delay the signal transmission to the sub-pixel to be charged. Therefore, the signal received at the selection signal terminal MUX controls the time for the charging sub-circuit 40 to turn on to be shortened, that is, when the charging sub-circuit 40 shortens the charging time of the sub-pixel pixel to be charged, the delay sub-circuit 30 delays the transmission of the data signal. The signal of the terminal Vs prolongs the charging time of the sub-pixel pixel to be charged, and ensures the charging effect of the sub-pixel pixel to be charged.
本公开的实施例提供的多路选择电路110,多路选择电路中的充电子电路40和延时子电路30均用于向待充电亚像素pixel充电,但两者向待充电亚像素pixel充电的时刻不同。充电子电路40在选择信号端MUX处接收的信号控制下开启,充电子电路40向待充电亚像素pixel充电,在充电子电路40开启的时间段内,延时子电路30相比充电子电路40延时向待充电亚像素pixel充电,延时子电路30在选择信号端MUX处接收的信号控制充电子电路40断开后,继续向待充电亚像素pixel充电。也就是说,在下一个多路选择电路向下 一个待充电亚像素pixel充电时,上一个多路选择电路中的延时子电路30仍在向上一个待充电亚像素pixel充电,延时子电路30向待充电亚像素pixel充电并不会导致总的充电时间增长。因此,本公开的实施例提供的多路选择电路不仅缩短了待充电亚像素pixel的充电时间,还保证了对待充电亚像素pixel的充电效果。In the multiple selection circuit 110 provided by the embodiment of the present disclosure, the charging sub-circuit 40 and the delay sub-circuit 30 in the multiple selection circuit are used to charge the sub-pixel pixel to be charged, but both charge the sub-pixel pixel to be charged. The moments are different. The charging sub-circuit 40 is turned on under the control of the signal received at the selection signal terminal MUX. The charging sub-circuit 40 charges the sub-pixel pixel to be charged. During the time period when the charging sub-circuit 40 is turned on, the delay sub-circuit 30 is compared with the charging sub-circuit. After 40 delays charging the sub-pixel pixel to be charged, the signal received by the delay sub-circuit 30 at the selection signal terminal MUX controls the charging sub-circuit 40 to disconnect, and then continues to charge the sub-pixel pixel to be charged. That is to say, when the next multiplexer circuit charges the next sub-pixel pixel to be charged, the delay sub-circuit 30 in the previous multiplexer circuit is still charging the next sub-pixel pixel to be charged, and the delay sub-circuit 30 Charging the sub-pixel pixel to be charged does not cause the total charging time to increase. Therefore, the multiple selection circuit provided by the embodiment of the present disclosure not only shortens the charging time of the sub-pixel pixel to be charged, but also ensures the charging effect of the sub-pixel pixel to be charged.
当将该多路选择电路应用于显示装置时,多路选择电路100通过数据信号传输通道与源极驱动器01的输出端口耦接,可以减少源极驱动器01的输出端口数量,减少与源极驱动器01的输出端口耦接的数据信号传输通道的数量,并且不影响每个亚像素20的充电效果。When the multiplexer circuit is applied to a display device, the multiplexer circuit 100 is coupled to the output port of the source driver 01 through the data signal transmission channel, which can reduce the number of output ports of the source driver 01 and reduce the number of output ports of the source driver 01. The number of data signal transmission channels coupled to the output port of 01 does not affect the charging effect of each sub-pixel 20.
示例性地,如图7所示,充电子电路40包括第一晶体管T1。Illustratively, as shown in FIG. 7, the charging sub-circuit 40 includes a first transistor T1.
第一晶体管T1的控制极与选择信号端MUX耦接,第一晶体管T1的第一极与数据信号端Vs耦接,第一晶体管T1的第二极与待充电亚像素pixel耦接。The control electrode of the first transistor T1 is coupled to the selection signal terminal MUX, the first electrode of the first transistor T1 is coupled to the data signal terminal Vs, and the second electrode of the first transistor T1 is coupled to the sub-pixel pixel to be charged.
此外,充电子电路40还可以包括与第一晶体管T1并联的多个开关晶体管。In addition, the charging sub-circuit 40 may further include a plurality of switching transistors connected in parallel with the first transistor T1.
示例性地,如图7所示,控制子电路50包括第二晶体管T2。Illustratively, as shown in FIG. 7, the control sub-circuit 50 includes a second transistor T2.
第二晶体管T2的控制极与选择信号端MUX耦接,第二晶体管T2的第一极与数据信号端Vs耦接,第二晶体管T2的第二极与延时子电路30耦接。The control electrode of the second transistor T2 is coupled to the selection signal terminal MUX, the first electrode of the second transistor T2 is coupled to the data signal terminal Vs, and the second electrode of the second transistor T2 is coupled to the delay sub-circuit 30.
此外,控制子电路50还可以包括与第二晶体管T2并联的多个开关晶体管。In addition, the control sub-circuit 50 may further include a plurality of switching transistors connected in parallel with the second transistor T2.
需要说明的是,上述仅仅是对控制子电路50的举例说明,其它与该控制子电路50功能相同的结构在此不再一一赘述,但都应当属于本公开的保护范围。It should be noted that the foregoing is only an example of the control sub-circuit 50, and other structures with the same function as the control sub-circuit 50 will not be repeated here, but they should all fall within the protection scope of the present disclosure.
示例性地,如图7所示,延时子电路30包括第三晶体管T3、第四晶体管T4和第一电容C1。Exemplarily, as shown in FIG. 7, the delay sub-circuit 30 includes a third transistor T3, a fourth transistor T4 and a first capacitor C1.
第三晶体管T3的控制极与控制信号端Vc耦接,第三晶体管T3的第一极与控制子电路50耦接,第三晶体管T3的第二极与第四晶体管T4的控制极耦接。The control electrode of the third transistor T3 is coupled to the control signal terminal Vc, the first electrode of the third transistor T3 is coupled to the control sub-circuit 50, and the second electrode of the third transistor T3 is coupled to the control electrode of the fourth transistor T4.
第四晶体管T4的第一极与控制子电路50耦接,第四晶体管T4的第二极与待充电亚像素pixel耦接。The first pole of the fourth transistor T4 is coupled to the control sub-circuit 50, and the second pole of the fourth transistor T4 is coupled to the sub-pixel to be charged.
第一电容C1的第一端分别与控制子电路50、第三晶体管T3的第一极和第四晶体管T4的第一极耦接,第一电容C1的第二端与第一电压端V1耦接。The first terminal of the first capacitor C1 is respectively coupled to the control sub-circuit 50, the first pole of the third transistor T3 and the first pole of the fourth transistor T4, and the second terminal of the first capacitor C1 is coupled to the first voltage terminal V1 Pick up.
其中,在控制信号端Vc处接收的信号被配置为,在亚像素的充电阶段, 控制第三晶体管T3开启。示例性地,在亚像素的充电阶段,在控制信号端Vc处接收的信号为直流高电平信号。Wherein, the signal received at the control signal terminal Vc is configured to control the third transistor T3 to turn on during the charging phase of the sub-pixel. Exemplarily, in the charging phase of the sub-pixels, the signal received at the control signal terminal Vc is a DC high-level signal.
在一些实施例中,第四晶体管T4的沟道的宽长比大于第三晶体管T3的沟道的宽长比。In some embodiments, the aspect ratio of the channel of the fourth transistor T4 is greater than the aspect ratio of the channel of the third transistor T3.
在此情况下,第三晶体管T3处于线性区的导通电阻小于第四晶体管T4处于线性区的导通电阻。控制信号端Vc控制第三晶体管T3的开启,在数据信号端Vs处接收的信号中的一部分通过第三晶体管T3,传输至第四晶体管T4的控制极,在数据信号端Vs处接收的信号中的另一部分传输至第四晶体管T4的第一极,以控制第四晶体管T4的开启,在数据信号端Vs处接收的信号通过第四晶体管T4可以延时传输至待充电亚像素pixel。In this case, the on-resistance of the third transistor T3 in the linear region is smaller than the on-resistance of the fourth transistor T4 in the linear region. The control signal terminal Vc controls the turn-on of the third transistor T3, a part of the signal received at the data signal terminal Vs is transmitted to the control electrode of the fourth transistor T4 through the third transistor T3, and in the signal received at the data signal terminal Vs The other part of is transmitted to the first pole of the fourth transistor T4 to control the turning on of the fourth transistor T4, and the signal received at the data signal terminal Vs can be transmitted to the sub-pixel pixel to be charged through the fourth transistor T4 with a delay.
需要说明的是,可以通过调整第四晶体管T4的沟道的宽长比和第三晶体管T3的沟道的宽长比的大小,调整电路零点(即延时子电路30的延时时长为零)的位置,以控制延时子电路30将来自控制子电路50的信号传输至待充电亚像素pixel的延时时长。本领域技术人员可以根据实际情况进行设计第四晶体管T4的沟道的宽长比和第三晶体管T3的沟道的宽长比的大小,本公开的实施例在此不做限定。It should be noted that by adjusting the width-to-length ratio of the channel of the fourth transistor T4 and the width-to-length ratio of the channel of the third transistor T3, the circuit zero point (that is, the delay time of the delay sub-circuit 30 is zero) can be adjusted. ) To control the delay time of the delay sub-circuit 30 transmitting the signal from the control sub-circuit 50 to the sub-pixel to be charged. Those skilled in the art can design the width-to-length ratio of the channel of the fourth transistor T4 and the width-to-length ratio of the channel of the third transistor T3 according to actual conditions, which are not limited in the embodiments of the present disclosure.
在此基础上,示例性地,如图7所示,延时子电路30包括还包括:第二电容C2。On this basis, exemplarily, as shown in FIG. 7, the delay sub-circuit 30 further includes: a second capacitor C2.
第二电容C2的第一端分别与第四晶体管T4的第二极和待充电亚像素pixel耦接,第二电容C2的第二端与第一电压端V1耦接。The first terminal of the second capacitor C2 is respectively coupled to the second electrode of the fourth transistor T4 and the sub-pixel pixel to be charged, and the second terminal of the second capacitor C2 is coupled to the first voltage terminal V1.
示例性地,在延时子电路30包括第三晶体管T3、第四晶体管T4、第一电容C1和第二电容C2的情况下,延时子电路30可以作为π型延时电路。在一些实施例中,如图6所示,多路选择电路110,还包括:存储子电路60。Exemplarily, in the case where the delay sub-circuit 30 includes a third transistor T3, a fourth transistor T4, a first capacitor C1 and a second capacitor C2, the delay sub-circuit 30 may be a π-type delay circuit. In some embodiments, as shown in FIG. 6, the multiple selection circuit 110 further includes a storage sub-circuit 60.
存储子电路60分别与充电子电路40、待充电亚像素pixel和第一电压端V1耦接。The storage sub-circuit 60 is respectively coupled to the charging sub-circuit 40, the sub-pixel pixel to be charged and the first voltage terminal V1.
其中,本公开的实施例中第一电压端V1例如可以是接地端,也可以是固定电压端。示例性地,在第一电压端V1处接收的信号为直流低电平信号。Among them, the first voltage terminal V1 in the embodiment of the present disclosure may be, for example, a ground terminal or a fixed voltage terminal. Exemplarily, the signal received at the first voltage terminal V1 is a DC low-level signal.
存储子电路60被配置为对充电子电路40传输的在数据信号端Vs处接收的信号进行存储,及,将所存储的信号传输至待充电亚像素pixel。The storage sub-circuit 60 is configured to store the signal received at the data signal terminal Vs transmitted by the charging sub-circuit 40, and to transmit the stored signal to the sub-pixel pixel to be charged.
在此情况下,存储子电路60可以使得经过充电子电路40传输至待充电亚像素pixel的信号保持稳定,从而提高待充电亚像素pixel充电的稳定性。In this case, the storage sub-circuit 60 can keep the signal transmitted to the sub-pixel pixel to be charged through the charging sub-circuit 40 stable, thereby improving the stability of charging the sub-pixel pixel to be charged.
示例性地,如图8所示,存储子电路60包括第三电容C3。Exemplarily, as shown in FIG. 8, the storage sub-circuit 60 includes a third capacitor C3.
第三电容C3的第一端分别与充电子电路40和待充电亚像素pixel耦接, 第三电容C3的第二端与第一电压端V1耦接。The first terminal of the third capacitor C3 is respectively coupled to the charging sub-circuit 40 and the sub-pixel pixel to be charged, and the second terminal of the third capacitor C3 is coupled to the first voltage terminal V1.
本公开的实施例提供的多路选择电路110,在选择信号端MUX输入开启信号时,第一晶体管T1将在数据信号端Vs处接收的信号传输至待充电亚像素pixel,同时,第三电容C3对在数据信号端Vs处接收的信号进行存储,以提高通过第一晶体管T1传输至待充电亚像素pixel的信号的稳定性。In the multiple selection circuit 110 provided by the embodiment of the present disclosure, when the select signal terminal MUX inputs the turn-on signal, the first transistor T1 transmits the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged, and the third capacitor C3 stores the signal received at the data signal terminal Vs to improve the stability of the signal transmitted to the sub-pixel pixel to be charged through the first transistor T1.
与此同时,在选择信号端MUX处接收的信号的控制下,第二晶体管T2导通,并将在数据信号端Vs处接收的信号传输至延时子电路30。第四晶体管T4的沟道的宽长比大于第三晶体管T3的沟道的宽长比,第三晶体管T3处于线性区的导通电阻小于第四晶体管T4处于线性区的导通电阻,控制信号端Vc通过控制第三晶体管T3的开启,在数据信号端Vs处接收的信号中的一部分通过第三晶体管T3,传输至第四晶体管T4的控制极,在数据信号端Vs处接收的信号中的另一部分传输至第四晶体管T4的第一极,以控制第四晶体管T4的开启,在数据信号端Vs处接收的信号通过第四晶体管T4可以延时传输至待充电亚像素pixel。At the same time, under the control of the signal received at the selection signal terminal MUX, the second transistor T2 is turned on and transmits the signal received at the data signal terminal Vs to the delay sub-circuit 30. The aspect ratio of the channel of the fourth transistor T4 is greater than the aspect ratio of the channel of the third transistor T3, the on-resistance of the third transistor T3 in the linear region is smaller than the on-resistance of the fourth transistor T4 in the linear region, and the control signal The terminal Vc controls the turn-on of the third transistor T3, and a part of the signal received at the data signal terminal Vs is transmitted to the control electrode of the fourth transistor T4 through the third transistor T3. In the signal received at the data signal terminal Vs, The other part is transmitted to the first pole of the fourth transistor T4 to control the turning on of the fourth transistor T4. The signal received at the data signal terminal Vs can be transmitted to the sub-pixel to be charged through the fourth transistor T4 with a delay.
可以通过调整第四晶体管T4的沟道的宽长比和第三晶体管T3的沟道的宽长比的大小,调整电路零点(即延时子电路30的延时时长为零)的位置,从而可以控制延迟时间,以延迟数据信号端Vs的信号的传输。待选择信号端MUX输入截止信号,此时延时子电路30正好将数据信号端Vs的信号传输至待充电亚像素pixel,待充电亚像素pixel继续充电,以延长待充电亚像素pixel的充电时间。The position of the circuit zero point (that is, the delay time of the delay sub-circuit 30 is zero) can be adjusted by adjusting the width to length ratio of the channel of the fourth transistor T4 and the width to length ratio of the channel of the third transistor T3, thereby The delay time can be controlled to delay the transmission of the signal at the data signal terminal Vs. The signal terminal MUX to be selected inputs a cut-off signal. At this time, the delay sub-circuit 30 just transmits the signal of the data signal terminal Vs to the sub-pixel pixel to be charged, and the sub-pixel pixel to be charged continues to be charged to extend the charging time of the sub-pixel pixel to be charged .
需要说明的是,本公开的实施例提供的多路选择电路110中所采用的晶体管可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件,本公开的实施例对此并不设限。It should be noted that the transistors used in the multiple selection circuit 110 provided by the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and the embodiments of the present disclosure are not limited thereto.
在一些实施例中,多路选择电路110所采用的各晶体管的控制极为晶体管的栅极,第一极为晶体管的源极和漏极中一者,第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的,所以其源极、漏极在结构上可以是没有区别的,也就是说,本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性地,在晶体管为P型晶体管的情况下,晶体管的第一极为源极,第二极为漏极;示例性地,在晶体管为N型晶体管的情况下,晶体管的第一极为漏极,第二极为源极。In some embodiments, the control electrode of each transistor used in the multiplexer circuit 110 is the gate of the transistor, one of the source and drain of the transistor on the first pole, and the other of the source and drain of the transistor on the second pole. One. Since the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable, that is, the first and second electrodes of the transistor in the embodiment of the present disclosure The two poles can be indistinguishable in structure. Exemplarily, when the transistor is a P-type transistor, the first electrode of the transistor is a source and the second electrode is a drain; for example, when the transistor is an N-type transistor, the first electrode of the transistor is a drain, The second pole is the source.
在本公开的实施例提供的电路中,延时子电路30、充电子电路40、控制子电路50和存储子电路60的具体实现方式不局限于上面描述的方式,其可以为任意使用的实现方式,例如为本领域技术人员熟知的常规连接方式,只 需保证实现相应功能即可。上述示例并不能限制本公开的保护范围。在实际应用中,技术人员可以根据情况选择使用或不适用上述各电路中的一个或多个,基于前述各电路的各种组合变型均不脱离本公开的原理,对此不再赘述。In the circuit provided by the embodiment of the present disclosure, the specific implementation manners of the delay sub-circuit 30, the charging sub-circuit 40, the control sub-circuit 50, and the storage sub-circuit 60 are not limited to the above-described manner, which can be implemented arbitrarily. The method, for example, a conventional connection method well known to those skilled in the art, only needs to ensure that the corresponding function is realized. The above examples do not limit the protection scope of the present disclosure. In practical applications, the skilled person can choose to use or not apply one or more of the above-mentioned circuits according to the situation. Various combinations and modifications based on the above-mentioned circuits do not deviate from the principle of the present disclosure, and will not be repeated here.
本公开的实施例提供一种多路选择单元11,如图9~图12所示,多路选择单元11包括至少一个多路选择组,每个多路选择组包括多个上述的多路选择电路。The embodiment of the present disclosure provides a multiple selection unit 11. As shown in FIGS. 9 to 12, the multiple selection unit 11 includes at least one multiple selection group, and each multiple selection group includes a plurality of the above multiple selections. Circuit.
多路选择组中的每个多路选择电路耦接的待充电亚像素pixel的发光颜色不同;多路选择单元11中的每个多路选择电路耦接不同的选择信号端MUX。The light-emitting color of the sub-pixel pixel to be charged coupled to each multiplexing circuit in the multiplexing group is different; each multiplexing circuit in the multiplexing unit 11 is coupled to a different selection signal terminal MUX.
图9和图10以多路选择单元11包括一个多路选择组为例进行示意,图11和图12以多路选择单元11包括两个多路选择组为例进行示意。9 and 10 take the multiple selection unit 11 including one multiple selection group as an example, and Figs. 11 and 12 take the multiple selection unit 11 including two multiple selection groups as an example.
为了方便说明,本公开的实施例中上述多个待充电亚像素是以矩阵形式排列为例进行的说明。在此情况下,参考图12,沿水平方向X排列成一排的亚像素P称为同一行待充电亚像素;沿竖直方向Y排列成一排的亚像素P称为同一列待充电亚像素。For the convenience of description, in the embodiments of the present disclosure, the multiple sub-pixels to be charged are arranged in a matrix as an example. In this case, referring to FIG. 12, the sub-pixels P arranged in a row along the horizontal direction X are called sub-pixels to be charged in the same row; sub-pixels P arranged in a row along the vertical direction Y are called sub-pixels to be charged in the same row.
示例性地,同一行亚像素可以与一根栅线GL耦接,同一列亚像素可以与一根数据线DL耦接。在此情况下,至少一列亚像素耦接同一个数据信号端Vs。Exemplarily, the sub-pixels in the same row can be coupled to one gate line GL, and the sub-pixels in the same column can be coupled to one data line DL. In this case, at least one column of sub-pixels is coupled to the same data signal terminal Vs.
图12中,R1和R2表示位于不同列的红色待充电亚像素,G1和G2表示位于不同列的绿色待充电亚像素,B1和B2表示位于不同列的蓝色待充电亚像素。例如,将显示面板10中的像素分为奇数列和偶数列,图12中,R1表示位于奇数列的像素中的红色待充电亚像素,G1表示位于奇数列的像素中的绿色待充电亚像素,B1表示位于奇数列的像素中的蓝色待充电亚像素;R2表示位于偶数列的像素中的红色待充电亚像素,G2表示位于偶数列的像素中的绿色待充电亚像素,B2表示位于偶数列的像素中的蓝色待充电亚像素。In FIG. 12, R1 and R2 represent red sub-pixels to be charged in different columns, G1 and G2 represent green sub-pixels to be charged in different columns, and B1 and B2 represent blue sub-pixels to be charged in different columns. For example, the pixels in the display panel 10 are divided into odd-numbered columns and even-numbered columns. In FIG. 12, R1 represents the red sub-pixel to be charged in the pixels in the odd-numbered column, and G1 represents the green sub-pixel to be charged in the pixels in the odd-numbered column. , B1 represents the blue sub-pixel to be charged in the pixel in the odd column; R2 represents the red sub-pixel to be charged in the pixel in the even column, G2 represents the green sub-pixel to be charged in the pixel in the even column, B2 represents the The blue sub-pixels to be charged among the pixels in the even columns.
示例性地,如图13所示,在一个多路选择单元11包括一个多路选择组,一个多路选择组包括三个多路选择电路的情况下,一个选择电压端Vs被配置为向三个待充电亚像素pixel充电。Exemplarily, as shown in FIG. 13, in a case where one multiplexer unit 11 includes one multiplexer group, and one multiplexer group includes three multiplexer circuits, one selection voltage terminal Vs is configured to A sub-pixel to be charged is charged.
示例性地,如图14所示,在一个多路选择单元11包括两个多路选择组,一个多路选择组包括三个多路选择电路的情况下,一个数据信号端Vs被配置为向六个待充电亚像素pixel充电。Exemplarily, as shown in FIG. 14, in a case where one multiplexer unit 11 includes two multiplexer groups, and one multiplexer group includes three multiplexer circuits, one data signal terminal Vs is configured to Six sub-pixels to be charged are charged.
多路选择组包括的多个多路选择电路110中,每个多路选择电路连接的待充电亚像素pixel的发光颜色不同;多路选择单元11中的每个多路选择电路连接不同的选择信号端MUX。Among the multiple multiple selection circuits 110 included in the multiple selection group, each multiple selection circuit connected to the sub-pixel pixel to be charged has a different light emission color; each multiple selection circuit in the multiple selection unit 11 is connected to a different selection Signal terminal MUX.
需要说明的是,本公开的实施例提供的多路选择单元11,包括的多路选择组的数量并不限于两个或三个,每个多路选择组包括的多路选择电路的数量也不限于三个,图9-图12仅为一种示意。It should be noted that the multiple selection unit 11 provided in the embodiment of the present disclosure includes the number of multiple selection groups is not limited to two or three, and the number of multiple selection circuits included in each multiple selection group is also It is not limited to three, and Figs. 9-12 are only an illustration.
示例性地,位于同一个多路选择组中的部分多路选择电路耦接的待充电亚像素pixel发光颜色相同。例如,在一个像素包括两个发光颜色相同的亚像素的情况下,位于同一个多路选择组中的两个多路选择电路耦接的待充电亚像素pixel的发光颜色相同;或者,在一列像素包括多种发光颜色亚像素的情况下,位于同一个多路选择组中的多路选择电路所耦接的待充电亚像素pixel中,部分待充电亚像素pixel的发光颜色相同。Exemplarily, the sub-pixels to be charged that are coupled to some of the multiplexer circuits in the same multiplexer group emit the same color. For example, in the case that a pixel includes two sub-pixels with the same light-emitting color, the light-emitting colors of the sub-pixel pixels to be charged coupled to the two multiplexer circuits in the same multiplexer group are the same; or, in one column When the pixel includes sub-pixels of multiple light-emitting colors, among the sub-pixels to be charged coupled to the multiple selection circuits in the same multiple selection group, some of the sub-pixels to be charged have the same light-emitting color.
示例性地,位于同一个多路选择组中的每个多路选择电路耦接的待充电亚像素pixel发光颜色不同,也就是说,一个多路选择组中不会存在有两个多路选择电路耦接用于发同一种颜色光的待充电亚像素pixel。这样一来,一个多路选择组中包含的多路选择电路的数量小于或者等于一个像素中包括的亚像素的数量。Exemplarily, the sub-pixel pixels to be charged coupled to each multiplexer circuit in the same multiplexer group have different light-emitting colors, that is, there will not be two multiplexer options in a multiplexer group. The circuit is coupled to the sub-pixels to be charged for emitting the same color light. In this way, the number of multiple selection circuits included in a multiple selection group is less than or equal to the number of sub-pixels included in one pixel.
在一些实施例中,如图13和图14所示,一个多路选择组对应一个像素,也就是一个多路选择组被配置为向位于同一个像素中的待充电亚像素pixel充电。In some embodiments, as shown in FIGS. 13 and 14, one multiplex selection group corresponds to one pixel, that is, one multiplex selection group is configured to charge the sub-pixel pixels to be charged in the same pixel.
在一些实施例中,如图15所示,一个多路选择组对应不同的像素,也就是一个多路选择组被配置为向位于不同像素中的待充电亚像素pixel充电。在此情况下,可以避免不同像素的信号干扰,提高充电质量。In some embodiments, as shown in FIG. 15, a multiplex selection group corresponds to different pixels, that is, a multiplex selection group is configured to charge the sub-pixel pixels located in different pixels to be charged. In this case, the signal interference of different pixels can be avoided, and the charging quality can be improved.
图15中一个虚线框表示一个像素,图15中以一个多路选择单元11包括一个多路选择组为例进行示意。A dashed box in FIG. 15 represents a pixel. In FIG. 15, a multiple-way selection unit 11 includes a multiple-way selection group as an example for illustration.
示例的,一个多路选择单元11包括三个多路选择电路,一行包括三个像素,多路选择单元11中的第一个多路选择电路向第一个像素中的红色待充电亚像素R充电,第二个多路选择电路向第二个像素中的绿色待充电亚像素G充电,第三个多路选择电路向第三个像素中的蓝色待充电亚像素B充电。For example, a multiplexing unit 11 includes three multiplexing circuits, one row includes three pixels, and the first multiplexing circuit in the multiplexing unit 11 directs the red sub-pixel R in the first pixel to be charged. For charging, the second multiplexer circuit charges the green sub-pixel G to be charged in the second pixel, and the third multiplexer circuit charges the blue sub-pixel B to be charged in the third pixel.
需要说明的是,多路选择组和像素也可以是其他对应方式,本公开的实施例在此不做限定。It should be noted that the multiple selection group and the pixel may also be in other corresponding manners, and the embodiments of the present disclosure are not limited herein.
本公开的实施例提供的多路选择单元11,无论是一个多路选择单元11向三个待充电亚像素pixel充电,还是一个多路选择单元11向六个待充电亚像素pixel充电,或者是其他数量。由于多路选择单元11中的每个多路选择电路在达到相同充电量目的的情况下,所需要的充电时常较短。因此,当将上述多路选择电路应用于多路选择单元11时,可以减少源极驱动器01(即源极 驱动IC)的输出端口,减少与源极驱动器01的输出端口耦接的数据信号传输通道的数量,并保证每个待充电亚像素pixel能够充足的充电,保证显示效果。The multiple selection unit 11 provided by the embodiment of the present disclosure, whether it is one multiple selection unit 11 charging three sub-pixels to be charged, or one multiple selection unit 11 charging six sub-pixels to be charged, or Other quantities. Since each multiplex circuit in the multiplexer unit 11 achieves the same charging capacity, the required charging time is often relatively short. Therefore, when the above multiple selection circuit is applied to the multiple selection unit 11, the output ports of the source driver 01 (ie, the source driver IC) can be reduced, and the data signal transmission coupled to the output port of the source driver 01 can be reduced. The number of channels, and to ensure that each sub-pixel to be charged can be fully charged to ensure the display effect.
在一些实施例中,如图10和图12所示,多路选择单元11中的多个多路选择电路110耦接同一数据信号端Vs。In some embodiments, as shown in FIG. 10 and FIG. 12, multiple multiplexer circuits 110 in the multiplexer unit 11 are coupled to the same data signal terminal Vs.
也就是说,一个多路选择单元11对应一个数据信号端Vs,隶属于同一多路选择单元11的多路选择电路耦接同一数据信号端Vs。因此,可以减少耦接源极驱动器01的输出端口和多路选择电路110的数据信号端Vs的数据信号传输通道的数量。That is to say, one multiplexing unit 11 corresponds to one data signal terminal Vs, and multiplexing circuits belonging to the same multiplexing unit 11 are coupled to the same data signal terminal Vs. Therefore, the number of data signal transmission channels coupled to the output port of the source driver 01 and the data signal terminal Vs of the multiplexer circuit 110 can be reduced.
在一些实施例中,如图11和图12所示,多路选择单元11包括两个多路选择组,多路选择组包括三个多路选择电路110。In some embodiments, as shown in FIGS. 11 and 12, the multiplexing unit 11 includes two multiplexing groups, and the multiplexing group includes three multiplexing circuits 110.
也就是说,一个多路选择单元11用于向六个待充电亚像素pixel充电。In other words, one multiplexing unit 11 is used to charge six sub-pixels to be charged.
本公开的实施例提供一种显示装置200,如图16所示,包括:显示面板10和至少一个如上述任一实施例中的多路选择单元11。该多路选择单元11设置于衬底基板102上。The embodiment of the present disclosure provides a display device 200, as shown in FIG. 16, comprising: a display panel 10 and at least one multiple selection unit 11 as in any of the above embodiments. The multiplexing unit 11 is arranged on the base substrate 102.
如图1所示,显示面板10具有有效显示区(active area,AA)100和位于该有效显示区100至少一侧的非显示区101。As shown in FIG. 1, the display panel 10 has an active display area (AA) 100 and a non-display area 101 located on at least one side of the active display area 100.
上述有效显示区100包括多个亚像素(sub pixel)20。亚像素20内设置有用于控制亚像素20进行显示的像素电路201,像素电路201设置在显示面板的衬底基板102上。The above-mentioned effective display area 100 includes a plurality of sub pixels 20. The sub-pixel 20 is provided with a pixel circuit 201 for controlling the sub-pixel 20 to display, and the pixel circuit 201 is provided on the base substrate 102 of the display panel.
以下以显示面板10为液晶显示面板为例,对亚像素20中的像素电路201进行举例说明。当然,显示面板10也可以是发光二极管显示面板,或有机发光二极管(organic light emitting diode,OLED)显示面板。示例性的,如图2所示,像素电路201包括晶体管M和液晶电容C。该液晶电容C的两个极板分别由像素电极和公共电极构成。晶体管M的控制极与栅线GL耦接,第一极与数据线DL耦接,第二极与液晶电容C耦接,晶体管M被配置为将数据线DL上的数据信号传输至液晶电容C。Hereinafter, taking the display panel 10 as a liquid crystal display panel as an example, the pixel circuit 201 in the sub-pixel 20 will be described as an example. Of course, the display panel 10 may also be a light emitting diode display panel, or an organic light emitting diode (OLED) display panel. Exemplarily, as shown in FIG. 2, the pixel circuit 201 includes a transistor M and a liquid crystal capacitor C. The two plates of the liquid crystal capacitor C are respectively composed of a pixel electrode and a common electrode. The control electrode of the transistor M is coupled to the gate line GL, the first electrode is coupled to the data line DL, and the second electrode is coupled to the liquid crystal capacitor C. The transistor M is configured to transmit the data signal on the data line DL to the liquid crystal capacitor C .
在一些实施例中,如图16所示,显示装置200还包括源极驱动器01和至少一个数据信号传输通道103。In some embodiments, as shown in FIG. 16, the display device 200 further includes a source driver 01 and at least one data signal transmission channel 103.
源极驱动器01与衬底基板102绑定,并与各多路选择单元11耦接。The source driver 01 is bound to the base substrate 102 and is coupled to each multiplexing unit 11.
一个多路选择单元11通过一个数据传输通道103与源极驱动器01耦接。A multiplexing unit 11 is coupled to the source driver 01 through a data transmission channel 103.
在此情况下,源极驱动器01的一个输出端口通过一个数据传输通道103与一个多路选择单元11的数据信号端Vs耦接,因此,可以减少源极驱动器01的输出端口的数量,减少源极驱动器01与多路选择单元11耦接的数据传 输通道103的数量。In this case, an output port of the source driver 01 is coupled to the data signal terminal Vs of a multiplexer 11 through a data transmission channel 103. Therefore, the number of output ports of the source driver 01 can be reduced and the source The number of data transmission channels 103 to which the pole driver 01 is coupled to the multiplexing unit 11.
此外,上述的多路选择单元11也可以集成在源极驱动器01内部,有益效果与源极驱动单元11的有益效果相同,此处不再赘述。In addition, the above-mentioned multiple selection unit 11 may also be integrated inside the source driver 01, and the beneficial effects are the same as the beneficial effects of the source driver unit 11, and will not be repeated here.
在一些实施例中,如图17所示,将显示面板10中的像素划分为奇数列像素和偶数列像素,将位于奇数列像素中的发同一种颜色光的亚像素耦接同一选择信号端MUX,将位于偶数列像素中的发同一种颜色光的亚像素耦接同一选择信号端MUX。因此,可以减少选择信号端MUX的数量。In some embodiments, as shown in FIG. 17, the pixels in the display panel 10 are divided into odd-numbered columns of pixels and even-numbered columns of pixels, and the sub-pixels that emit light of the same color in the odd columns are coupled to the same selection signal terminal. The MUX couples the sub-pixels emitting the same color light in the even-numbered columns to the same selection signal terminal MUX. Therefore, the number of selection signal terminals MUX can be reduced.
以红色亚像素为例,将奇数列的红色待充电亚像素R1的充电与否由奇数红色选择信号端MUXR1控制,将偶数列的红色待充电亚像素R2的充电与否由偶数红色选择信号端MUXR2控制。以绿色亚像素为例,将奇数列的绿色待充电亚像素G1的充电与否由奇数绿色选择信号端MUXG1控制,将偶数列的绿色待充电亚像素G2的充电与否由偶数绿色选择信号端MUXG2控制。以蓝色亚像素为例,将奇数列的蓝色待充电亚像素B1的充电与否由奇数蓝色选择信号端MUXB1控制,将偶数列的蓝色待充电亚像素B2的充电与否由偶数蓝色选择信号端MUXB2控制。Taking the red sub-pixel as an example, the charging of the red sub-pixel R1 in the odd column is controlled by the odd red selection signal terminal MUXR1, and the charging of the red sub-pixel R2 in the even column is controlled by the even red selection signal terminal. MUXR2 control. Taking the green sub-pixel as an example, the charging of the odd-numbered green sub-pixel G1 to be charged is controlled by the odd-numbered green selection signal terminal MUXG1, and the even-numbered column of green sub-pixel G2 to be charged is controlled by the even-numbered green selection signal terminal. MUXG2 control. Taking blue sub-pixels as an example, the charging of the blue sub-pixels B1 in odd columns is controlled by the odd blue selection signal terminal MUXB1, and the charging of the blue sub-pixels B2 in even columns is controlled by even The blue selection signal terminal MUXB2 control.
在一些实施例中,如图17所示,两个多路选择组中的一个多路选择组与奇数列像素的待充电亚像素pixel耦接,另一个多路选择组与偶数列像素的待充电亚像素pixel耦接。In some embodiments, as shown in FIG. 17, one of the two multiplexer groups is coupled to the sub-pixels to be charged of pixels in odd columns, and the other multiplexer group is coupled to the pixels to be charged in even columns. Charging sub-pixel pixel coupling.
以下,结合图18中的时序图,对如图17所示的多路选择单元11的工作过程进行示意说明。Hereinafter, the working process of the multiplexing unit 11 shown in FIG. 17 will be schematically described in conjunction with the timing diagram in FIG. 18.
需要说明的是,在亚像素充电过程中,栅线GL逐行开启,每一行栅线GL开启后,多路选择单元11的工作过程是相同的,因此,此处以第一行栅线GL开启后,多路选择单元11的工作过程进行举例说明。It should be noted that during the sub-pixel charging process, the gate lines GL are turned on row by row. After each row of the gate lines GL is turned on, the working process of the multiplexing unit 11 is the same. Therefore, the first row of gate lines GL is turned on here. After that, the working process of the multiple selection unit 11 will be illustrated by an example.
其中,R1-1表示的是图17中左边的多路选择单元11耦接的前六个待充电亚像素pixel中,位于奇数列的红色待充电亚像素R1的时序,R2-1表示的是图17中左边的多路选择单元11耦接的前六个待充电亚像素pixel中,位于偶数列的红色待充电亚像素R2的时序,R1-2表示的是图17中右边的多路选择单元11耦接的前六个待充电亚像素pixel中,位于奇数列的红色待充电亚像素R1的时序,R2-2表示的是图17中右边的多路选择单元11耦接的前六个待充电亚像素pixel中,位于偶数列的红色待充电亚像素R2的时序。B1-1表示的是图17中左边的多路选择单元11耦接的前六个待充电亚像素pixel中,位于奇数列的蓝色待充电亚像素B1的时序,B2-1表示的是图17中左边的多路选择单元11耦接的前六个待充电亚像素pixel中,位于偶数列的蓝色待充 电亚像素B2的时序,B1-2表示的是图17中右边的多路选择单元11耦接的前六个待充电亚像素pixel中,位于奇数列的蓝色待充电亚像素B1的时序,B2-2表示的是图17中右边的多路选择单元11耦接的前六个待充电亚像素pixel中,位于偶数列的蓝色待充电亚像素B2的时序。G1-1表示的是图17中左边的多路选择单元11耦接的前六个待充电亚像素pixel中,位于奇数列的绿色待充电亚像素G1的时序,G2-1表示的是图17中左边的多路选择单元11耦接的前六个待充电亚像素pixel中,位于偶数列的绿色待充电亚像素G2的时序,G1-2表示的是图17中右边的多路选择单元11耦接的前六个待充电亚像素pixel中,位于奇数列的绿色待充电亚像素G1的时序,G2-2表示的是图17中右边的多路选择单元11耦接的前六个待充电亚像素pixel中,位于偶数列的绿色待充电亚像素G2的时序。Among them, R1-1 represents the timing of the red sub-pixel R1 to be charged in the odd column among the first six sub-pixels to be charged coupled to the multiple selection unit 11 on the left in FIG. 17, and R2-1 represents Among the first six sub-pixels to be charged that are coupled to the multiple selection unit 11 on the left in FIG. 17, the timing of the red sub-pixels to be charged R2 in the even-numbered column. R1-2 represents the multiple selection on the right in FIG. Among the first six sub-pixels to be charged that are coupled to the unit 11, the timing of the red sub-pixels to be charged R1 in an odd-numbered column, R2-2 represents the first six coupled to the multiple selection unit 11 on the right in FIG. Among the sub-pixels to be charged, the timing of the red sub-pixels to be charged R2 in the even column. B1-1 shows the timing of the blue sub-pixel B1 to be charged in the odd-numbered column among the first six sub-pixels to be charged coupled by the multiple selection unit 11 on the left in FIG. 17, and B2-1 shows the diagram Among the first six sub-pixels to be charged that are coupled to the multiple selection unit 11 on the left in 17, the timing of the blue sub-pixel to be charged B2 in the even-numbered column. B1-2 represents the multiple selection on the right in FIG. Among the first six sub-pixels to be charged that are coupled to the unit 11, the timing of the blue sub-pixel to be charged B1 in the odd-numbered column. B2-2 represents the first six that are coupled to the multiplexer unit 11 on the right in FIG. Among the sub-pixels to be charged, the timing of the blue sub-pixels B2 to be charged in the even-numbered column. G1-1 shows the timing of the green sub-pixel G1 to be charged in the odd-numbered column among the first six sub-pixels to be charged coupled by the multiple selection unit 11 on the left in FIG. 17, and G2-1 shows the timing of FIG. Among the first six sub-pixels to be charged that are coupled to the multiplexing unit 11 on the left in the middle, the timing of the green sub-pixel G2 to be charged in the even-numbered column. G1-2 represents the multiplexing unit 11 on the right in FIG. Among the first six coupled sub-pixels to be charged, the timing of the green sub-pixel G1 in the odd-numbered column to be charged. G2-2 represents the first six to be charged coupled to the multiplex unit 11 on the right in FIG. In the sub-pixel pixel, the timing of the green sub-pixel G2 to be charged in the even-numbered column.
如图18所示,奇数红色选择信号端MUXR1、奇数绿色选择信号端MUXG1、奇数蓝色选择信号端MUXB1、偶数红色选择信号端MUXR2、偶数绿色选择信号端MUXG2和偶数蓝色选择信号端MUXB2依次输入开启信号,左边的多路选择单元11耦接的数据信号端Vs1在奇数红色选择信号端MUXR1和偶数红色选择信号端MUXR2输入开启信号时输入数据信号,与左边的多路选择单元11耦接的前六个待充电亚像素pixel中,位于奇数列的红色待充电亚像素R1和位于偶数列的红色待充电亚像素R2充电,其余四个待充电亚像素pixel并未充电。右边的多路选择单元11耦接的数据信号端Vs2在偶数蓝色选择信号端MUXB2输入开启信号时输入数据信号,与右边的多路选择单元11耦接的后六个待充电亚像素pixel中,位于偶数列的蓝色待充电亚像素B2充电,其余五个待充电亚像素pixel并未充电。As shown in Figure 18, the odd red selection signal terminal MUXR1, the odd green selection signal terminal MUXG1, the odd blue selection signal terminal MUXB1, the even red selection signal terminal MUXR2, the even green selection signal terminal MUXG2, and the even blue selection signal terminal MUXB2 are in sequence Input the enable signal, the data signal terminal Vs1 coupled to the left multiple selection unit 11 inputs the data signal when the odd red selection signal terminal MUXR1 and the even red selection signal terminal MUXR2 input the opening signal, and is coupled to the left multiple selection unit 11 Among the first six sub-pixels to be charged, the red sub-pixel R1 in the odd-numbered column and the red sub-pixel R2 in the even-numbered column are charged, and the remaining four sub-pixels to be charged are not charged. The data signal terminal Vs2 coupled to the multiple selection unit 11 on the right inputs a data signal when the even-numbered blue selection signal terminal MUXB2 inputs the turn-on signal, and is coupled to the last six sub-pixel pixels to be charged that are coupled to the multiple selection unit 11 on the right , The blue sub-pixel B2 to be charged in the even-numbered column is charged, and the remaining five sub-pixels to be charged are not charged.
需要说明的是,图18仅为图17中的左边的多路选择单元11耦接的数据信号端Vs1和右边的多路选择单元11耦接的数据信号端Vs2的信号时序示意图,但实际应用不限于此。例如,在第一行亚像素全部充电的情况下,左边的多路选择单元11耦接的数据信号端Vs1和右边的多路选择单元11耦接的数据信号端Vs2的信号可以为高电平信号,且对于不同的待充电亚像素pixel充电所需的高电平信号的电位不完全相等。It should be noted that FIG. 18 is only a schematic diagram of the signal timing of the data signal terminal Vs1 coupled to the multiple selection unit 11 on the left and the data signal terminal Vs2 coupled to the multiple selection unit 11 on the right in FIG. 17, but in practical applications Not limited to this. For example, when the first row of sub-pixels are fully charged, the signals of the data signal terminal Vs1 coupled to the multiple selection unit 11 on the left and the data signal terminal Vs2 coupled to the multiple selection unit 11 on the right may be high. The potentials of the high-level signals required for charging different sub-pixels to be charged are not completely equal.
请继续参见图18,示例性地,当奇数红色选择信号端MUXR1的信号为高电平信号,左边的多路选择单元11耦接的数据信号端Vs1处接收的信号为高电平信号时,图17中左边的多路选择单元11耦接的前六个待充电亚像素pixel中,位于奇数列的红色待充电亚像素R1开始充电。并且,当奇数红色选择信号端MUXR1的信号为低电平信号,左边的多路选择单元11耦接的数 据信号端Vs1处接收的信号为低电平信号时,左边的多路选择单元11耦接的前六个待充电亚像素pixel中,位于奇数列的红色待充电亚像素R1仍充电。此时,左边的多路选择单元11耦接的前六个待充电亚像素pixel中,位于奇数列的红色待充电亚像素R1的充电时长,大于左边的多路选择单元11耦接的数据信号端Vs1处接收的信号为高电平的时长。Please continue to refer to FIG. 18. Illustratively, when the signal of the odd-numbered red selection signal terminal MUXR1 is a high-level signal, and the signal received at the data signal terminal Vs1 coupled to the multiple selection unit 11 on the left is a high-level signal, Among the first six sub-pixels to be charged that are coupled by the multiple selection unit 11 on the left in FIG. 17, the red sub-pixels R1 to be charged in odd-numbered columns start to be charged. Moreover, when the signal of the odd red selection signal terminal MUXR1 is a low-level signal, and the signal received at the data signal terminal Vs1 coupled to the left multiplexing unit 11 is a low-level signal, the left multiplexing unit 11 is coupled Among the first six sub-pixels to be charged, the red sub-pixel R1 to be charged in the odd column is still charged. At this time, among the first six sub-pixels to be charged that are coupled to the multiple selection unit 11 on the left, the charging time of the red sub-pixels R1 to be charged in the odd column is longer than the data signal coupled to the multiple selection unit 11 on the left. The length of time that the signal received at the terminal Vs1 is high.
因此,在待充电亚像素pixel的充电阶段,待充电亚像素pixel的充电时长,大于选择信号端MUX的信号有效的时长。Therefore, in the charging phase of the sub-pixel pixel to be charged, the charging time period of the sub-pixel pixel to be charged is longer than the valid time period of the signal of the selection signal terminal MUX.
需要说明的是,每一行栅线GL输入扫描信号后,参考图18,多路选择单元11重复上述过程。It should be noted that after the scanning signal is input to each row of gate lines GL, referring to FIG. 18, the multiplexing unit 11 repeats the above process.
此外,上述显示装置200可以是显示不论运动(例如,视频)还是固定(例如,静止图像)的且不论文字还是的图像的任何装置。更明确地说,预期所述实施例可实施在多种电子装置中或与多种电子装置关联,所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如,里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如,车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如,对于一件珠宝的图像的显示器)等。In addition, the above-mentioned display device 200 may be any device that displays images whether in motion (for example, video) or fixed (for example, still images), and regardless of text or images. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs) , Handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, car monitors (e.g., Odometer display, etc.), navigator, cockpit controller and/or display, camera view display (for example, the display of a rear-view camera in a vehicle), electronic photos, electronic billboards or signs, projectors, building structures, packaging And aesthetic structure (for example, a display of the image of a piece of jewelry), etc.
本公开的实施例提供一种多路选择电路的驱动方法。参考图5,多路选择电路110包括充电子电路40、控制子电路50和延时子电路30。充电子电路40与选择信号端MUX、数据信号端Vs和待充电亚像素pixel耦接;控制子电路50与选择信号端MUX和数据信号端Vs耦接;延时子电路30与待充电亚像素pixel和控制子电路50耦接。The embodiment of the present disclosure provides a method for driving a multiple selection circuit. Referring to FIG. 5, the multiplexer circuit 110 includes a charging sub-circuit 40, a control sub-circuit 50 and a delay sub-circuit 30. The charging sub-circuit 40 is coupled to the selection signal terminal MUX, the data signal terminal Vs and the sub-pixel pixel to be charged; the control sub-circuit 50 is coupled to the selection signal terminal MUX and the data signal terminal Vs; the delay sub-circuit 30 is coupled to the sub-pixel to be charged The pixel is coupled to the control sub-circuit 50.
多路选择电路110的驱动方法,如图19所示,包括:The driving method of the multiple selection circuit 110, as shown in FIG. 19, includes:
S10、选择信号端MUX输入开启信号,充电子电路40在选择信号端MUX处接收的信号的控制下,将在数据信号端Vs处接收的信号传输至待充电亚像素pixel;控制子电路50在选择信号端MUX处接收的信号的控制下,传输在数据信号端Vs处接收的信号;延时子电路30将经过控制子电路50传输的在数据信号端Vs处接收的信号延迟传输,在充电子电路40向待充电亚像素pixel充电预设时间后,延时子电路30将在数据信号端Vs处接收的信号传输至待充电亚像素pixel。S10. The selection signal terminal MUX inputs the turn-on signal, and the charging sub-circuit 40 transmits the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged under the control of the signal received at the selection signal terminal MUX; the control sub-circuit 50 is at Under the control of the signal received at the selection signal terminal MUX, the signal received at the data signal terminal Vs is transmitted; the delay sub-circuit 30 delays the transmission of the signal received at the data signal terminal Vs transmitted through the control sub-circuit 50, and is After the electronic circuit 40 charges the sub-pixel pixel to be charged for a preset time, the delay sub-circuit 30 transmits the signal received at the data signal terminal Vs to the sub-pixel pixel to be charged.
S20、选择信号端MUX输入截止信号,充电子电路40和控制子电路50 在选择信号端MUX处接收的信号的控制下截止,延时子电路30继续将数据信号端Vs处接收的信号传输至待充电亚像素pixel。S20. The selection signal terminal MUX inputs a cut-off signal, the charging sub-circuit 40 and the control sub-circuit 50 are cut off under the control of the signal received at the selection signal terminal MUX, and the delay sub-circuit 30 continues to transmit the signal received at the data signal terminal Vs to Sub-pixel pixel to be charged.
本公开的实施例提供的多路选择电路的驱动方法的有益效果与上述多路选择电路的有益效果相同,此处不再赘述。The beneficial effects of the driving method of the multiple selection circuit provided by the embodiments of the present disclosure are the same as the beneficial effects of the above multiple selection circuit, and will not be repeated here.
以上所述,仅为本公开的具体实施方式,但本公开的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本公开揭露的技术范围内,想到变化或替换,都应涵盖在本公开的保护范围之内。因此,本公开的保护范围应以所述权利要求的保护范围为准。The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who thinks of changes or substitutions within the technical scope disclosed in the present disclosure shall cover Within the protection scope of this disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims (16)

  1. 一种多路选择电路,包括:A multiple selection circuit, including:
    充电子电路,分别与选择信号端、数据信号端和待充电亚像素耦接;所述充电子电路被配置为,在所述选择信号端处接收的信号的控制下,将在所述数据信号端处接收的信号传输至所述待充电亚像素;The charging sub-circuit is respectively coupled to the selection signal terminal, the data signal terminal, and the sub-pixel to be charged; the charging sub-circuit is configured to, under the control of the signal received at the selection signal terminal, transfer the data signal The signal received at the terminal is transmitted to the sub-pixel to be charged;
    控制子电路,分别与所述选择信号端和所述数据信号端耦接;所述控制子电路被配置为,在所述选择信号端处接收的信号的控制下,传输在所述数据信号端处接收的信号;The control sub-circuit is respectively coupled to the selection signal terminal and the data signal terminal; the control sub-circuit is configured to transmit to the data signal terminal under the control of the signal received at the selection signal terminal Signal received at
    延时子电路,分别与所述待充电亚像素和所述控制子电路耦接;所述延时子电路被配置为,将经过所述控制子电路传输的在所述数据信号端处接收的信号延迟传输,在所述充电子电路向所述待充电亚像素充电预设时间后,将在所述数据信号端处接收的信号传输至所述待充电亚像素。The delay sub-circuits are respectively coupled to the sub-pixels to be charged and the control sub-circuit; the delay sub-circuits are configured to transmit data transmitted through the control sub-circuit and received at the data signal terminal Signal transmission is delayed, and after the charging sub-circuit charges the sub-pixel to be charged for a preset time, the signal received at the data signal terminal is transmitted to the sub-pixel to be charged.
  2. 根据权利要求1所述的多路选择电路,其中,所述延时子电路包括:The multiplexer circuit according to claim 1, wherein the delay sub-circuit comprises:
    第三晶体管,所述第三晶体管的控制极与控制信号端耦接,所述第三晶体管的第一极与所述控制子电路耦接;A third transistor, a control electrode of the third transistor is coupled to a control signal terminal, and a first electrode of the third transistor is coupled to the control sub-circuit;
    第四晶体管,所述第四晶体管的控制极与所述第三晶体管的第二极耦接,所述第四晶体管的第一极与所述控制子电路耦接,所述第四晶体管的第二极与所述待充电亚像素耦接;A fourth transistor, the control electrode of the fourth transistor is coupled to the second electrode of the third transistor, the first electrode of the fourth transistor is coupled to the control sub-circuit, and the second electrode of the fourth transistor The two poles are coupled to the sub-pixel to be charged;
    第一电容,所述第一电容的第一端分别与所述控制子电路、所述第三晶体管的第一极和所述第四晶体管的第一极耦接,所述第一电容的第二端与第一电压端耦接。The first capacitor, the first terminal of the first capacitor is respectively coupled to the control sub-circuit, the first pole of the third transistor, and the first pole of the fourth transistor, the first terminal of the first capacitor The two terminals are coupled with the first voltage terminal.
  3. 根据权利要求2所述的多路选择电路,其中,所述第四晶体管的沟道的宽长比大于所述第三晶体管的沟道的宽长比。3. The multiplexer circuit according to claim 2, wherein the aspect ratio of the channel of the fourth transistor is greater than the aspect ratio of the channel of the third transistor.
  4. 根据权利要求3所述的多路选择电路,其中,所述延时子电路还包括:The multiplexer circuit according to claim 3, wherein the delay sub-circuit further comprises:
    第二电容,所述第二电容的第一端分别与所述第四晶体管的第二极和所述待充电亚像素耦接,所述第二电容的第二端与所述第一电压端耦接。A second capacitor, the first terminal of the second capacitor is respectively coupled to the second terminal of the fourth transistor and the sub-pixel to be charged, and the second terminal of the second capacitor is connected to the first voltage terminal Coupling.
  5. 根据权利要求1~4中任一项所述的多路选择电路,其中,所述控制子电路包括:The multiplexer circuit according to any one of claims 1 to 4, wherein the control sub-circuit comprises:
    第二晶体管,所述第二晶体管的控制极与所述选择信号端耦接,所述第二晶体管的第一极与所述数据信号端耦接,所述第二晶体管的第二极与所述延时子电路耦接。The second transistor, the control electrode of the second transistor is coupled to the selection signal terminal, the first electrode of the second transistor is coupled to the data signal terminal, and the second electrode of the second transistor is coupled to the The delay sub-circuit is coupled.
  6. 根据权利要求1~5中任一项所述的多路选择电路,其中,所述充电子电路包括:The multiplexer circuit according to any one of claims 1 to 5, wherein the charging sub-circuit comprises:
    第一晶体管,所述第一晶体管的控制极与所述选择信号端耦接,所述第 一晶体管的第一极与所述数据信号端耦接,所述第一晶体管的第二极与所述待充电亚像素耦接。The first transistor, the control electrode of the first transistor is coupled to the selection signal terminal, the first electrode of the first transistor is coupled to the data signal terminal, and the second electrode of the first transistor is coupled to the selection signal terminal. The sub-pixel to be charged is coupled.
  7. 根据权利要求1~6中任一项所述的多路选择电路,还包括:The multiple selection circuit according to any one of claims 1 to 6, further comprising:
    存储子电路,所述存储子电路分别与所述充电子电路、所述待充电亚像素和第一电压端耦接;所述存储子电路被配置为,对所述充电子电路传输的在所述数据信号端处接收的信号进行存储,及,将所存储的信号传输至所述待充电亚像素。A storage sub-circuit, the storage sub-circuit is respectively coupled to the charging sub-circuit, the sub-pixel to be charged, and the first voltage terminal; the storage sub-circuit is configured to transmit to the charging sub-circuit in all The signal received at the data signal terminal is stored, and the stored signal is transmitted to the sub-pixel to be charged.
  8. 根据权利要求7所述的多路选择电路,其中,所述存储子电路包括:8. The multiplexer circuit according to claim 7, wherein the storage sub-circuit comprises:
    第三电容,所述第三电容的第一端分别与所述充电子电路和所述待充电亚像素耦接,所述第三电容的第二端与所述第一电压端耦接。A third capacitor, the first terminal of the third capacitor is respectively coupled to the charging sub-circuit and the sub-pixel to be charged, and the second terminal of the third capacitor is coupled to the first voltage terminal.
  9. 一种多路选择单元,包括:A multiple selection unit, including:
    至少一个多路选择组,每个多路选择组包括多个如权利要求1~8中任一项所述的多路选择电路;At least one multiplexing group, each multiplexing group comprising a plurality of multiplexing circuits according to any one of claims 1-8;
    所述多路选择单元中的每个所述多路选择电路耦接不同的选择信号端。Each of the multiple selection circuits in the multiple selection unit is coupled to a different selection signal terminal.
  10. 根据权利要求9所述的多路选择单元,其中,所述多路选择组中的每个多路选择电路耦接的待充电亚像素的发光颜色不同。9. The multiplex selection unit according to claim 9, wherein the sub-pixels to be charged coupled to each multiplex selection circuit in the multiplex selection group have different light-emitting colors.
  11. 根据权利要求9或10所述的多路选择单元,其中,所述多路选择单元中的多个所述多路选择电路耦接同一数据信号端。10. The multiplexing unit according to claim 9 or 10, wherein a plurality of the multiplexing circuits in the multiplexing unit are coupled to the same data signal terminal.
  12. 根据权利要求9~11中任一项所述的多路选择单元,其中,所述多路选择单元包括两个所述多路选择组,所述多路选择组包括三个所述多路选择电路。The multiplexing unit according to any one of claims 9 to 11, wherein the multiplexing unit includes two multiplexing groups, and the multiplexing group includes three multiplexing Circuit.
  13. 根据权利要求12所述的多路选择单元,其中,两个所述多路选择组中的一个多路选择组与奇数列像素的待充电亚像素耦接,另一个多路选择组与偶数列像素的待充电亚像素耦接。The multiplexer unit according to claim 12, wherein one multiplexer group of the two multiplexer groups is coupled to the sub-pixels to be charged of pixels in odd columns, and the other multiplexer group is coupled with even columns The sub-pixel to be charged of the pixel is coupled.
  14. 一种显示装置,包括:A display device includes:
    至少一个如权利要求9~13中任一项所述的多路选择单元;At least one multiplexing unit according to any one of claims 9-13;
    显示面板,所述显示面板包括衬底基板;所述多路选择单元设置于所述衬底基板上。The display panel, the display panel includes a base substrate; the multiplexer is arranged on the base substrate.
  15. 根据权利要求14所述的显示装置,还包括:The display device according to claim 14, further comprising:
    源极驱动器,所述源极驱动器与所述衬底基板绑定,并与各所述多路选择单元耦接;和A source driver, the source driver is bound to the base substrate and coupled to each of the multiple selection units; and
    至少一个数据信号传输通道,所述数据信号传输通道设置于所述衬底基板上;一个所述多路选择单元通过一个数据传输通道与所述源极驱动器耦接。At least one data signal transmission channel, the data signal transmission channel is arranged on the base substrate; one of the multiplexer units is coupled to the source driver through a data transmission channel.
  16. 一种如权利要求1~8中任一项所述的多路选择电路的驱动方法,包括:A method for driving a multiple selection circuit according to any one of claims 1 to 8, comprising:
    选择信号端输入开启信号,充电子电路在所述选择信号端处接收的信号的控制下,将在数据信号端处接收的信号传输至待充电亚像素;The selection signal terminal inputs an on signal, and the charging sub-circuit transmits the signal received at the data signal terminal to the sub-pixel to be charged under the control of the signal received at the selection signal terminal;
    控制子电路在所述选择信号端处接收的信号的控制下,传输在所述数据信号端处接收的信号;The control sub-circuit transmits the signal received at the data signal terminal under the control of the signal received at the selection signal terminal;
    所述延时子电路将经过所述控制子电路传输的在所述数据信号端处接收的信号延迟传输,在所述充电子电路向所述待充电亚像素充电预设时间后,所述延时子电路将在所述数据信号端处接收的信号传输至所述待充电亚像素;The delay sub-circuit delays the transmission of the signal received at the data signal terminal transmitted through the control sub-circuit. After the charging sub-circuit charges the sub-pixel to be charged for a preset time, the delay The time sub-circuit transmits the signal received at the data signal terminal to the sub-pixel to be charged;
    所述选择信号端输入截止信号,所述充电子电路和所述控制子电路在所述选择信号端处接收的信号的控制下截止,所述延时子电路继续将在所述数据信号端处接收的信号传输至所述待充电亚像素。The selection signal terminal inputs a cut-off signal, the charging sub-circuit and the control sub-circuit are cut off under the control of the signal received at the selection signal terminal, and the delay sub-circuit continues to be at the data signal terminal The received signal is transmitted to the sub-pixel to be charged.
PCT/CN2020/079561 2019-03-26 2020-03-17 Multi-path selection circuit and driving method, and multi-path selection unit and display apparatus WO2020192476A1 (en)

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