WO2020188643A1 - Display device - Google Patents

Display device Download PDF

Info

Publication number
WO2020188643A1
WO2020188643A1 PCT/JP2019/010911 JP2019010911W WO2020188643A1 WO 2020188643 A1 WO2020188643 A1 WO 2020188643A1 JP 2019010911 W JP2019010911 W JP 2019010911W WO 2020188643 A1 WO2020188643 A1 WO 2020188643A1
Authority
WO
WIPO (PCT)
Prior art keywords
display device
transistor
upper gate
insulating film
region
Prior art date
Application number
PCT/JP2019/010911
Other languages
French (fr)
Japanese (ja)
Inventor
正悟 村重
悠二郎 武田
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to PCT/JP2019/010911 priority Critical patent/WO2020188643A1/en
Publication of WO2020188643A1 publication Critical patent/WO2020188643A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to a display device having a transistor.
  • an organic EL display device uses a configuration including a pixel circuit that supplies a current to pixels in a light emitting layer, and the pixel circuit is provided with a TFT (thin film transistor).
  • TFT thin film transistor
  • Examples of the TFT used in the pixel circuit include a top gate structure (see, for example, Patent Document 1).
  • the semiconductor device described in Patent Document 1 has a semiconductor region having silicon, an insulating layer above the semiconductor region, and a conductive layer above the insulating layer, and a channel forming region is provided in the semiconductor region.
  • the present invention has been made to solve the above problems, and an object of the present invention is to provide a display device capable of relaxing electric field concentration and improving withstand voltage.
  • the display device is a display device having a first transistor formed by laminating an oxide semiconductor layer, an upper gate insulating film, an upper gate electrode, and an interlayer insulating film on a substrate.
  • the upper gate electrode of one transistor has a metal oxide layer laminated in order from the substrate side and a metal layer covering the side surface and the upper surface of the metal oxide layer, and the oxide semiconductor of the first transistor.
  • the layers include a channel region facing the metal oxide layer via the upper gate insulating film, a source region and a drain region provided so as to sandwich the channel region between each other, and the channel region and the above.
  • the upper gate insulating film is provided between the first active region facing the metal layer and the channel region and the drain region via the upper gate insulating film. It is characterized by including a second active region facing the metal layer via the metal layer.
  • the metal oxide layer may be configured to contain In.
  • the metal oxide layer may be configured to contain Ga and Zn.
  • the metal oxide layer may be configured to contain Sn and Zn.
  • the first active region and the second active region may have a lower resistivity than the channel region and a higher resistivity than the source region and the drain region.
  • the channel region of the first transistor is aligned with the metal oxide layer, and the end of the first active region on the source region side is the source region side of the metal layer.
  • the end portion of the second active region on the drain region side may be aligned with the end portion of the metal layer on the drain region side.
  • the upper gate electrode may be configured to match the upper gate insulating film.
  • the upper gate insulating film may be configured to be a silicon oxide film.
  • the interlayer insulating film may be configured such that a portion in contact with the oxide semiconductor layer and the upper gate electrode is formed of a silicon nitride film.
  • the interlayer insulating film may be configured such that a portion in contact with the oxide semiconductor layer and the upper gate electrode is formed of a silicon oxide film.
  • a lower gate electrode and a lower gate insulating film are provided between the substrate and the oxide semiconductor layer, and the lower gate electrode is formed via the lower gate insulating film. It may be configured to overlap with the channel region.
  • the lower gate electrode may be configured such that the end portion on the source region side overlaps with the source region and the end portion on the drain region side overlaps with the drain region.
  • the lower gate electrode has a configuration in which the end portion on the source region side overlaps with the first active region and the end portion on the drain region side overlaps with the second active region. May be.
  • the display device may include a peripheral circuit monolithically provided in the frame region, and the first transistor may be a switching transistor included in the peripheral circuit.
  • a second transistor formed by laminating an oxide semiconductor layer, an upper gate insulating film, an upper gate electrode, and an interlayer insulating film is provided on the substrate, and the second transistor is provided.
  • the upper gate electrode has a metal oxide layer and a metal layer laminated in this order from the substrate side, and the oxide semiconductor layer of the second transistor passes through the upper gate insulating film.
  • the configuration may include a channel region facing the upper gate electrode and a source region and a drain region provided so as to sandwich the channel region between them.
  • the display device includes pixel circuits provided in a matrix in a display region, the pixel circuits include the first transistor, the second transistor, and a capacitance, and the first transistor includes a capacitance. It is a threshold control transistor, the second transistor is a drive transistor, the control terminal of the drive transistor is electrically connected to one electrode of the capacitance, and the threshold control transistor has one conduction terminal. , One conductive terminal of the drive transistor may be electrically connected, and the other conductive terminal may be electrically connected to its own control terminal.
  • the display device includes a terminal portion provided in the frame region, a routing wiring extended from the terminal portion, and a filter circuit provided between the terminal portion and the display area, and the terminal.
  • the unit may be electrically connected to the wiring in the display area via the filter circuit, and the first transistor may be included in the filter circuit.
  • the source region may be electrically connected to the high power supply voltage line
  • the drain region and the upper gate electrode may be electrically connected to the routing wiring.
  • the source region may be electrically connected to the routing wiring, and the drain region and the upper gate electrode may be electrically connected to the low power supply voltage line.
  • the routing wiring may be configured to be electrically connected to the data signal line in the display area.
  • the routing wiring may be configured to be electrically connected to the scanning signal line in the display area.
  • the length of the second active region may be longer than the length of the first active region in the channel length direction in which the source region and the drain region face each other.
  • an LDD structure can be formed, electric field concentration can be relaxed, and withstand voltage can be improved.
  • FIG. 1 is a schematic cross-sectional view schematically showing a first transistor in the display device according to the first embodiment of the present invention
  • FIG. 2 is a schematic plan view schematically showing the first transistor shown in FIG. Is.
  • hatching is omitted in FIG. 1, and the base layer 5 and the interlayer insulating film 9 and the like are transparently shown in FIG.
  • FIG. 1 corresponds to the cross section of the arrow AA in FIG.
  • the first transistor 1 in the display device 100 (see FIG. 6 described later) according to the first embodiment of the present invention has a base layer 5, an oxide semiconductor layer 6, and an upper gate insulating film 7 on a substrate 3.
  • the upper gate electrode 8, the interlayer insulating film 9 (the first interlayer insulating film 9a and the second interlayer insulating film 9b), and the terminal electrode (source electrode 10 and drain electrode 11) are laminated in this order.
  • FIG. 1 shows an enlarged view of one first transistor 1 formed on the substrate 3, and a plurality of transistors may be further formed on the substrate 3.
  • the base layer 5 is formed so as to cover the entire substrate 3.
  • the direction along the surface of the substrate 3 may be referred to as the channel length direction L.
  • the oxide semiconductor layer 6 is provided on the base layer 5, and is arranged for each first transistor 1. That is, the oxide semiconductor layer 6 is provided apart from the oxide semiconductor layer 6 in other transistors.
  • the upper gate insulating film 7 is provided on the oxide semiconductor layer 6, and the upper gate electrode 8 is provided on the upper gate insulating film 7.
  • the upper gate electrode 8 is composed of a metal oxide layer 8a laminated in order from the substrate 3 side, and a metal layer 8b covering the side surface and the upper surface of the metal oxide layer 8a.
  • the metal oxide layer 8a has a shorter length in the channel length direction L than the metal layer 8b, and covers the center of the upper gate insulating film 7, but covers both ends of the upper gate insulating film 7. Not covered.
  • the metal layer 8b is aligned with the upper gate insulating film 7 in a plan view. That is, the metal layer 8b is provided so as to cover the entire upper gate insulating film 7, and the portion of the upper gate insulating film 7 that is not covered by the metal oxide layer 8a is covered by the metal layer 8b.
  • the matching does not mean that the matching is exact, and includes a dimensional deviation of about several ⁇ m caused by a difference in etching rate or the like.
  • the oxide semiconductor layer 6 includes conductor regions (source region 6b and drain region 6c) located at both ends in the channel length direction L and a channel region 6a located at the center in the channel length direction L.
  • the conductor region is a region in which the oxide semiconductor has a lower resistance than the channel region 6a.
  • the metal oxide layer 8a faces the channel region 6a via the upper gate insulating film 7.
  • the oxide semiconductor layer 6 has a first active region 6d provided between the channel region 6a and the source region 6b, and a second active region 6e provided between the channel region 6a and the drain region 6c. are doing.
  • the first active region 6d and the second active region 6e face the portion of the upper gate electrode 8 provided with only the metal layer 8b via the upper gate insulating film 7.
  • the interlayer insulating film 9 (first interlayer insulating film 9a and second interlayer insulating film 9b) is formed so as to cover the oxide semiconductor layer 6 and the upper gate electrode 8.
  • a source electrode 10 (left in FIG. 1) and a drain electrode 11 (right in FIG. 1) are provided on the second interlayer insulating film 9b.
  • the source electrode 10 and the drain electrode 11 are provided apart from each other in the channel length direction L.
  • the source electrode 10 is electrically connected to the source region 6b of the oxide semiconductor layer 6 via the source contact hole Ha provided in the first interlayer insulating film 9a and the second interlayer insulating film 9b.
  • the drain electrode 11 is electrically connected to the drain region 6c of the oxide semiconductor layer 6 via the drain contact holes Hb provided in the first interlayer insulating film 9a and the second interlayer insulating film 9b.
  • the first metal wiring includes the upper gate electrode 8 and the second routing wiring 104b (see FIG. 8 described later).
  • the second metal wiring includes the first routing wiring 104a (see FIG. 8 described later).
  • the third metal wiring includes a high power supply voltage line EL VDD of the filter circuit 105, a low power supply voltage line ELVSS of the filter circuit 105, and a connection wiring for connecting various wirings.
  • the constant potential voltage line, the first routing wire, the second routing wiring, the high power supply voltage line of the filter circuit, the low power supply voltage line of the filter circuit, and the connection wiring are not specified in the above combination, and the three metal wirings. It may be composed of any of. Further, the configuration including the three metal wirings has been described, but the present invention is not limited to this, and the number of metal wirings may be increased, and an insulating film may be appropriately provided between the metal wirings.
  • a base layer 5 which is an insulating film is formed on the substrate 3.
  • the substrate 3 for example, a glass substrate, a silicon substrate, and a heat-resistant plastic substrate (resin substrate) can be used.
  • the plastic substrate polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), acrylic resin, polyimide and the like can be used.
  • the base layer 5 is formed by forming a SiO 2 film by a CVD method.
  • the base layer 5 is not limited to this, and for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxide nitride (SiO x N y ; x> y), silicon nitride (SiN x Oy ;). It may be formed of x> y), aluminum oxide, tantalum oxide, or the like, or a plurality of layers may be laminated.
  • the thickness of the base layer 5 is preferably 500 nm or less.
  • the oxide semiconductor layer 6 is formed on the base layer 5.
  • the oxide semiconductor layer 6 is formed by, for example, a sputtering method, and is an In—Ga—Zn—O-based semiconductor film having a thickness of 50 nm.
  • the oxide semiconductor layer 6 is formed into an island shape corresponding to each first transistor 1 by patterning by a photolithography process and etching.
  • the upper gate insulating film 7 and the upper gate electrode 8 are formed so as to cover the oxide semiconductor layer 6.
  • the upper gate insulating film 7 is formed of silicon oxide (SiO x ) formed by a CVD method.
  • the upper gate insulating film 7 may be formed of the same material as the base layer 5, may have a laminated structure in which a plurality of layers are laminated, and preferably has a thickness of 200 nm or less.
  • the metal oxide layer 8a is formed by, for example, a sputtering method.
  • the metal oxide layer 8a may be formed of the same material as the oxide semiconductor layer 6, and is an In—Ga—Zn—O (IGZO) -based semiconductor film.
  • the metal oxide layer 8a may be an In—Zn—O (IZO) -based semiconductor film or an In—Sn—Zn—O-based semiconductor film, and has a blocking property against H 2 and H 2 O. Anything that has The metal oxide layer 8a may be appropriately patterned by a photolithography process after forming a film.
  • the metal layer 8b of the upper gate electrode 8 is formed by a sputtering method, and for example, aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), and titanium (Ti) are formed. ), And a metal film containing an element selected from copper (Cu), an alloy film containing these elements as a component, or a laminated film containing a plurality of these elements may be used. Good.
  • the metal layer 8b is a laminated film composed of Ti / Al / Ti, and has a thickness of 100 nm or more and 300 nm or less.
  • the metal layer 8b of the upper gate electrode 8 and the upper gate insulating film 7 are continuously etched using the same resist mask patterned by the photolithography process. As a result, the metal layer 8b and the upper gate insulating film 7 have the same patterning shape and are formed into a shape based on the same resist pattern.
  • plasma treatment is applied to the entire surface of the substrate 3 from above the upper gate electrode 8.
  • the plasma treatment includes, for example, hydrogen plasma treatment and He plasma treatment.
  • the upper gate electrode 8 and the upper gate insulating film 7 function as a mask, and the portion of the oxide semiconductor layer 6 that is not covered with the upper gate electrode 8 and the upper gate insulating film 7 (upper gate insulating film 7).
  • the resistance of the source region 6b and the drain region 6c, which are the portions exposed from the above, is reduced.
  • first interlayer insulating film 9a covering the oxide semiconductor layer 6 and the upper gate electrode 8 is formed, and a second interlayer insulating film 9b is formed on the first interlayer insulating film 9a.
  • the first interlayer insulating film 9a and the second interlayer insulating film 9b may be formed by the same material and method as the base layer 5, and in the present embodiment, the first interlayer insulating film 9a has a thickness of 100 nm. It is SiN, and the second interlayer insulating film 9b is SiO 2 having a thickness of 400 nm.
  • the metal oxide layer 8a is made into a conductor by plasma treatment on the oxide semiconductor layer 6, and the resistance is lowered by supplying hydrogen from the nitride film (first interlayer insulating film 9a). Further, the resistance of the metal oxide layer 8a is lowered by hydrogen diffusion from Ti (metal layer 8b) and plasma at the time of forming the metal layer 8b. In this way, since the influence on the lower layer in the manufacturing process is blocked by the metal oxide layer 8a, the channel region 6a overlapping the metal oxide layer 8a of the oxide semiconductor layer 6 is not made into a conductor. , Retains the properties of intrinsic semiconductors. On the other hand, in the first active region 6d and the second active region 6e that overlap with only the metal layer 8b of the oxide semiconductor layer 6, some hydrogen permeates through the metal layer 8b, so that the resistance is slightly lowered. To.
  • the first active region 6d and the second active region 6e are regions having a low resistivity such as a conductor region, have a resistivity lower than that of the channel region 6a, and the source region 6b and the drain region 6c. It is said to be a conductor with a higher resistivity than.
  • the metal oxide layer 8a it is possible to select the region where the resistance is lowered.
  • the channel region 6a is aligned with the metal oxide layer 8a, and the end portion of the first active region 6d on the source region 6b side is the end portion of the metal layer 8b on the source region 6b side.
  • the end portion of the second active region 6e on the drain region 6c side is aligned with the end portion of the metal layer 8b on the drain region 6c side.
  • the length of the channel length direction L including the channel region 6a, the first active region 6d, and the second active region 6e is about 10 ⁇ m, and the first active region 6d and the second active region 6e The length of each channel length direction L is about 1 ⁇ m.
  • a source contact hole Ha and a drain contact hole Hb that expose a part of the oxide semiconductor layer 6 are formed on the first interlayer insulating film 9a and the second interlayer insulating film 9b by a known photolithography process.
  • a conductive film for electrodes which is the base of the source electrode 10 and the drain electrode 11, is formed on the second interlayer insulating film 9b and in the contact hole.
  • the conductive film for the electrode the material exemplified as the upper gate electrode 8 can be used. By patterning the conductive film for electrodes, a source electrode 10 and a drain electrode 11 that are separated from each other are formed.
  • the oxide semiconductor layer 6 is not limited to the above-mentioned materials, and may be formed of other materials.
  • the oxide semiconductor contained in the oxide semiconductor layer 6 may be, for example, an amorphous oxide semiconductor (amorphous oxide semiconductor) or a crystalline oxide semiconductor having a crystalline portion.
  • Examples of the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface.
  • the oxide semiconductor layer 6 may have a laminated structure of two or more layers, and in this case, the oxide semiconductor layer 6 includes an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. You may be. Alternatively, it may contain a plurality of crystalline oxide semiconductor layers having different crystal structures, or may include a plurality of amorphous oxide semiconductor layers.
  • the oxide semiconductor layer 6 may contain at least one metal element among, for example, In, Ga, and Zn, and in the present embodiment, the In—Ga—Zn—O-based semiconductor (for example, Indium gallium zinc oxide) was used.
  • the In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the proportion (composition) of In, Ga, and Zn.
  • the In—Ga—Zn—O-based semiconductor may be amorphous or crystalline.
  • a crystalline In—Ga—Zn—O-based semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable.
  • a TFT having an In—Ga—Zn—O-based semiconductor layer has higher mobility and lower leakage current than an a—Si TFT, and is therefore preferably used as the first transistor 1 of the display device 100. be able to.
  • the oxide semiconductor layer 6 may contain another oxide semiconductor instead of the In—Ga—Zn—O semiconductor, and may contain, for example, an In—Sn—Zn—O semiconductor.
  • In-Sn-Zn-O-based semiconductor is, In, a ternary oxide of Sn (tin), and Zn, for example, In 2 O 3 -SnO 2 -ZnO (InSnZnO) , and the like.
  • the oxide semiconductor layer 6 is not limited to this, and the In—Al—Zn—O system semiconductor, In—Al—Sn—Zn—O system semiconductor, Zn—O system semiconductor, In—Zn—O system semiconductor, Zn— Ti-O-based semiconductors, Cd-Ge-O-based semiconductors, Cd-Pb-O-based semiconductors, CdO (cadmium oxide), Mg-Zn-O-based semiconductors, In-Ga-Sn-O-based semiconductors, In-Ga- O-based semiconductor, Zr-In-Zn-O-based semiconductor, Hf-In-Zn-O-based semiconductor, Al-Ga-Zn-O-based semiconductor, Ga-Zn-O-based semiconductor, In-Ga-Zn-Sn- It may contain O-based semiconductors, InGaO 3 (ZnO) 5 , zinc oxide (Mg X Zn 1-X O), zinc oxide (Cd X Zn 1-X O), and the like.
  • ZnO is in an amorphous state to which one or more of group 1 elements, group 13 elements, group 14 elements, group 15 elements or group 17 elements are added.
  • the polycrystalline state or the microcrystalline state in which the amorphous state and the polycrystalline state are mixed, or the one to which no impurity element is added can be used.
  • FIG. 3 is a schematic cross-sectional view schematically showing the first transistor in the display device according to the second embodiment of the present invention. In consideration of the legibility of the drawings, hatching is omitted in FIG.
  • the first transistor 1 in the second embodiment is different from the first embodiment in that the lower gate electrode 4 is provided.
  • the lower gate electrode 4 is laminated between the substrate 3 and the base layer 5.
  • the substrate 3 may be insulated from the lower gate electrode 4 by providing an insulating film on the surface thereof. Further, in the present embodiment, it is desirable that an insulating film is provided between the lower gate electrode 4 and the oxide semiconductor layer 6.
  • the base layer 5 (corresponding to the lower gate insulating film) is insulated. It may be made of a material having a property.
  • the lower gate electrode 4 may be formed of the same material as the metal layer 8b of the upper gate electrode 8 and is patterned by a photolithography process.
  • the end portion on the source region 6b side overlaps with the source region 6b
  • the end portion on the drain region 6c side overlaps with the drain region, and the channel region 6a, via the base layer 5, It faces the first active region 6d and the second active region 6e.
  • the first transistor 1 in the second embodiment When the first transistor 1 in the second embodiment is used in the display device 100, different voltages may be input to the upper gate electrode 8 and the lower gate electrode 4. For example, a fluctuating voltage may be input to the upper gate electrode 8 to control the driving of the transistor, and a threshold control voltage set to a constant voltage may be input to the lower gate electrode 4. As described above, the double gate structure including the upper gate electrode 8 and the lower gate electrode 4 can improve the characteristics of the transistor.
  • FIG. 4 is a schematic cross-sectional view of a modified example of the first transistor shown in FIG.
  • the length of the lower gate electrode 4 in the channel length direction L is different from that of the structure shown in FIG. Specifically, in the lower gate electrode 4, the end portion on the source region 6b side is superimposed on the first active region 6d, and the end portion on the drain region 6c side is superimposed on the second active region 6e. That is, in the structure of FIG. 3, the lower gate electrode 4 overlaps the entire upper gate electrode 8 and the end portion protrudes to a position where it overlaps with the source region 6b and the drain region 6c. On the other hand, in the modified example, the lower gate electrode 4 is within the range of overlapping with the upper gate electrode 8. As a result, the lower gate electrode 4 does not overlap with the source region 6b and the drain region 6c, so that the parasitic capacitance generated between the oxide semiconductor layer 6 and the lower gate electrode 4 can be reduced.
  • FIG. 5 is a schematic cross-sectional view schematically showing a second transistor in the display device according to the third embodiment of the present invention. In consideration of the legibility of the drawings, hatching is omitted in FIG.
  • the second transistor 2 is provided on the substrate 3 in addition to the first transistor 1, and in FIG. 5, one second transistor 2 formed on the substrate 3 is enlarged. Is shown.
  • the second transistor 2 has a base layer 5, an oxide semiconductor layer 6, an upper gate insulating film 7, an upper gate electrode 8, and an interlayer insulating film 9 (first interlayer insulating film 9a and second interlayer insulating film 9b) on the substrate 3. , And the terminal electrodes (source electrode 10 and drain electrode 11) are laminated in this order.
  • the layers of the second transistor 2 may be formed at the same time when the layers of the first transistor 1 are formed on the substrate, and each layer is formed by substantially the same material and method.
  • the second transistor 2 has a different configuration of the oxide semiconductor layer 6 and the upper gate electrode 8 from the first transistor 1, and the description of common parts will be omitted.
  • the upper gate electrode 8 of the second transistor 2 is formed by laminating a metal oxide layer 8a and a metal layer 8b, but the range in which the metal oxide layer 8a is provided is the same as that of the first transistor 1. different.
  • the metal oxide layer 8a and the metal layer 8b have the same length in the channel length direction L, and the metal oxide layer 8a is provided so as to cover the entire upper gate insulating film 7. ing. That is, the metal oxide layer 8a, the metal layer 8b, and the upper gate insulating film 7 are aligned in a plan view.
  • the metal oxide layer 8a and the metal layer 8b of the second transistor 2 may be formed of the same material as the metal oxide layer 8a and the metal layer 8b of the upper gate electrode 8 of the first transistor 1.
  • the metal oxide layer 8a was patterned in the portion corresponding to the first transistor 1, but the metal oxide layer 8a was patterned in the portion corresponding to the second transistor 2. Instead, the metal oxide layer 8a may be etched together with the metal layer 8b. Further, when the metal oxide layer 8a is patterned, it may be left larger than the range in which the upper gate electrode 8 is provided and etched so as to match the range with the metal layer 8b.
  • the oxide semiconductor layer 6 of the second transistor 2 is composed of a channel region 6a, a source region 6b, and a drain region 6c. That is, the second transistor 2 is different from the first transistor 1 in that it does not have the first active region 6d and the second active region 6e.
  • the display device 100 can be applied by appropriately combining transistors according to the application.
  • FIG. 6 is a schematic configuration diagram schematically showing a display device according to a fourth embodiment of the present invention.
  • the display device 100 includes a display area 101 in which pixel circuits are provided in a matrix, and a frame area 102 that surrounds the display area 101.
  • a terminal portion 103 for electrically connecting to the outside, a routing wiring 104 extended from the terminal portion 103, and a filter circuit 105 provided between the terminal portion 103 and the display area 101 ( An example of a peripheral circuit) is provided.
  • the number of the routing wiring 104 may be appropriately determined according to the size of the display device 100, and a plurality of routing wirings 104 are provided.
  • a high voltage may be applied, so it is preferable to use a transistor having a high withstand voltage. Further, when the filter circuit 105 is used as a circuit for filtering low voltage noise, noise having a voltage lower than that of the low voltage (low power supply voltage) is prevented from passing through.
  • FIG. 7 is a circuit configuration diagram showing a part of a filter circuit using the first transistor.
  • a low power supply voltage line ELVSS and a high power supply voltage line EL VDD are provided so as to intersect a plurality of signal wiring SLs (route wiring 104).
  • FIG. 7 shows a state in which the low power supply voltage line ELVSS and the high power supply voltage line EL VDD intersect with each other for the four signal wiring SLs, but the number of signal wiring SLs is not limited to this. , May increase or decrease.
  • the low voltage transistor 1a (first transistor 1) connected to each signal wiring SL and the low power supply voltage line ELVSS, and each signal wiring SL and the high power supply voltage line EL VDD are connected to each other.
  • a high voltage transistor 1b (first transistor 1) is provided. That is, each signal wiring SL is not directly connected to the low power supply voltage line ELVSS and the high power supply voltage line EL VDD, but is connected to the low power supply voltage line ELVSS via the low voltage transistor 1a to connect the high voltage transistor 1b. It is connected to the high power supply voltage line EL VDD via.
  • the upper gate electrode 8 and the drain electrode 11 are connected to the low power supply voltage line ELVSS, and the source electrode 10 is connected to the signal wiring SL.
  • the source electrode 10 is connected to the high power supply voltage line EL VDD, and the upper gate electrode 8 and the drain electrode 11 are connected to the signal wiring SL.
  • the potentials applied to the low power supply voltage line ELVSS and the high power supply voltage line EL VDD are set to predetermined values as "ELVSS" and "EL VDD", respectively.
  • the low-voltage transistor 1a is a low-voltage filter that keeps the potential applied to the signal wiring SL at "ELVSS” when a potential of "ELVSS" or less is applied to the signal wiring SL, and is a high-voltage transistor 1b. Is a high voltage filter that keeps the potential applied to the signal wiring SL at "EL VDD” when a potential equal to or higher than "EL VDD" is applied to the signal wiring SL.
  • FIG. 8 is a schematic plan view showing a part of the first transistor in the filter circuit
  • FIG. 9A is a schematic cross-sectional view showing a cross section at the arrow CC of FIG. 8
  • FIG. 9B is a schematic cross-sectional view. It is a schematic cross-sectional view which shows the cross section at the arrow line DD of FIG.
  • hatching is omitted in FIGS. 9A and 9B, and the base layer 5 and the interlayer insulating film 9 and the like are transparently shown in FIG.
  • FIG. 8 a part (4) of a plurality of first transistors 1 provided in the filter circuit 105 is extracted and shown, and two low-voltage transistors 1a and two high-voltage transistors 1b are shown.
  • FIG. 9A is a filter circuit for filtering low-voltage noise and shows two low-voltage transistors 1a
  • FIG. 9B is a filter circuit for filtering high-voltage noise and has two.
  • the high voltage transistor 1b is shown.
  • one (first low-voltage transistor 1aa) is connected to the first routing wiring 104a, and the other (second low-voltage transistor 1ab) is connected to the second routing wiring 104b. It is connected to the.
  • the other (second high voltage transistor 1bb) is connected to the second routing. It is connected to the wiring 104b.
  • the first routing wiring 104a may be formed by forming a metal film and patterning after forming the first interlayer insulating film 9a and before forming the second interlayer insulating film 9b. Further, the contact hole for the first routing wiring 104a may be formed by etching the second interlayer insulating film 9b together with the source contact hole Ha and the drain contact hole Hb, or may be formed separately. ..
  • the second routing wiring 104b is formed together with the step of forming the upper gate insulating film 7 and the upper gate electrode 8. That is, in the photolithography process of the upper gate electrode 8 (particularly, the metal layer 8b), a resist mask may be formed also on the portion corresponding to the second routing wiring 104b. As a result, when the upper gate insulating film 7 and the upper gate electrode 8 are etched, the second routing wiring 104b and the wiring portion insulating film 13 aligned with the second routing wiring 104b are formed together. Further, the contact hole for the second routing wiring 104b may be formed by etching the first interlayer insulating film 9a and the second interlayer insulating film 9b together with the source contact hole Ha and the drain contact hole Hb, or separately. May be formed.
  • the low power supply voltage line ELVSS and the high power supply voltage line EL VDD are formed together with the source electrode 10 and the drain electrode 11 and are provided on the second interlayer insulating film 9b. That is, the low power supply voltage line ELVSS and the high power supply voltage line EL VDD are formed of the electrode conductive film which is the base of the source electrode 10 and the drain electrode 11, and also include the low power supply voltage line ELVSS and the high power supply voltage line EL VDD. It is patterned so that it has a shape.
  • the source extending portion 21 extends from the source electrode 10 to the first routing wiring 104a and the second routing wiring 104b, and is electrically connected to the first routing wiring 104a and the second routing wiring 104b.
  • the drain extending portion 22 extends from the drain electrode 11 to the low power supply voltage line ELVSS and is electrically connected to the low power supply voltage line ELVSS.
  • the gate extending portion 23 extends from the low power supply voltage line ELVSS to the upper gate electrode 8 and is electrically connected to the upper gate electrode 8.
  • the source extending portion 21 extends from the source electrode 10 to the high power supply voltage line EL VDD and is electrically connected to the high power supply voltage line EL VDD.
  • the drain extension portion 22 extends from the drain electrode 11 to the first routing wiring 104a and the second routing wiring 104b, and is electrically connected to the first routing wiring 104a and the second routing wiring 104b.
  • the gate extending portion 23 extends from the first routing wiring 104a and the second routing wiring 104b to the upper gate electrode 8 and is electrically connected to the first routing wiring 104a and the second routing wiring 104b.
  • the source stretching portion 21, the drain stretching portion 22, and the gate stretching portion 23 are formed from the above-mentioned electrode conductive film, and are formed together with the source electrode 10 and the drain electrode 11.
  • contact holes may be appropriately formed in the overlapping portions.
  • the source extending portion 21 is connected to the first routing wiring 104a via the routing contact hole He.
  • the source extending portion 21 is connected to the second routing wiring 104b via the routing contact hole Hf.
  • the gate extending portion 23 of the first low-voltage transistor 1aa and the second low-voltage transistor 1ab is formed so as to penetrate the first interlayer insulating film 9a and the second interlayer insulating film 9b on the upper gate electrode 8. It is connected to the corresponding upper gate electrode 8 via the contact hole Hc.
  • the drain extension portion 22 is connected to the first routing wiring 104a via the routing contact hole Hg.
  • the drain extension portion 22 is connected to the second routing wiring 104b via the routing contact hole Hh.
  • the gate extension portion 23 in the first high voltage transistor 1ba and the second high voltage transistor 1bb is connected to the second routing wiring 104b via the routing contact hole Hd.
  • the contact hole Hc may be provided in the same manner as in the first low voltage transistor 1aa and the second low voltage transistor 1ab.
  • the range in which the source electrode 10 and the drain electrode 11 overlap with the oxide semiconductor layer 6 is not particularly limited, and the source electrode 10 and the drain electrode 11 are provided so as to connect various wirings to the corresponding contact holes. Just do it.
  • first transistors 1 of the filter circuit 105 are extracted and shown, but the present invention is not limited to this, and the first transistor 1 may be increased or decreased as appropriate according to the number of routing wires 104. Further, regarding the routing wiring 104, the first routing wiring 104a and the second routing wiring 104b may be arranged alternately, or one of them may be arranged continuously.
  • various wirings such as the upper gate electrode 8, the source electrode 10, the drain electrode 11, and the routing wiring 104 are laminated with various insulating films sandwiched between them, and are appropriately laminated in a contact hole.
  • the above configuration is only an example, and the stacking order may be changed as appropriate.
  • the source electrode 10, the source stretching portion 21, the low power supply voltage line ELVSS, the high power supply voltage line EL VDD, and the like are provided on the same layer (layer), and the same electrode conductive film is used at once. Although it was formed, it may be provided in different layers and formed separately.
  • FIG. 10 is a schematic cross-sectional view schematically showing a first transistor in the display device according to the fifth embodiment of the present invention
  • FIG. 11 is a schematic plan view schematically showing the first transistor shown in FIG. Is.
  • hatching is omitted in FIG. 10
  • the base layer 5 and the interlayer insulating film 9 and the like are transparently shown in FIG.
  • FIG. 10 corresponds to the cross section of the arrow EE in FIG.
  • the position of the metal oxide layer 8a in the upper gate electrode 8 is different from that in the first embodiment.
  • the metal oxide layer 8a is arranged substantially in the center in the channel length direction L in the upper gate electrode 8.
  • the metal oxide layer 8a is unevenly arranged on the source region 6b side in the upper gate electrode 8. That is, in the channel length direction L, the length of the second active region 6e (second active region length KL2) is longer than the length of the first active region 6d (first active region length KL1).
  • the first transistor 1 in the present embodiment may be used in the filter circuit 105 described above, and the upper gate electrode 8, the source electrode 10, and the source electrode 10 may be used depending on what is applied as the low voltage transistor 1a and the high voltage transistor 1b. And the drain electrode 11 may be appropriately connected to various wirings.
  • FIG. 12 is an equivalent circuit diagram showing a pixel circuit of the display device.
  • the display device 100 has a display area 101 composed of a plurality of pixels arranged in a matrix.
  • the plurality of pixels typically include a red pixel that displays red, a green pixel that displays green, and a blue pixel that displays blue.
  • a corresponding light emitting diode LD is provided in each pixel, and is controlled by a corresponding pixel circuit.
  • the straight line corresponding to "S (m)” indicates the source signal line
  • the straight lines corresponding to "G (n)” and “G (n-1)” indicate the gate signal line
  • "EM (n)” The straight line corresponding to "” indicates a light emission control line.
  • "EL VDD” indicates a high power supply voltage
  • a straight line connected to the high power supply voltage corresponds to a high power supply voltage line.
  • "ELVSS” indicates a low power supply voltage
  • a straight line connected to the low power supply voltage corresponds to a low power supply voltage line.
  • the straight line corresponding to "Vini (n)” indicates the reset signal line corresponding to the reset potential.
  • FIG. 8 shows an example of a pixel circuit, which is configured by combining seven transistors (first circuit transistor T1 to seventh circuit transistor T7), a capacitor Ca, and a light emitting diode LD.
  • the first transistor 1 described above may be applied to any of the first circuit transistor T1 to the seventh circuit transistor T7, but it is desirable that the first transistor 1 be arranged at a location corresponding to each characteristic, and the first transistor 1 may be used as a switching transistor in a pixel circuit. It is preferably applied.
  • the first circuit transistor T1 to the third circuit transistor T3 and the fifth circuit transistor T5 to the seventh circuit transistor T7 are used as switching transistors.
  • the fourth circuit transistor T4 is a drive transistor that supplies power to the light emitting diode LD.
  • the second transistor 2 described above is preferably applied to a drive transistor in a pixel circuit.
  • the display device 100 is not particularly limited as long as it is a display panel provided with a display element.
  • the display element includes a display element whose brightness and transmittance are controlled by an electric current and a display element whose brightness and transmittance are controlled by a voltage.
  • Examples of the current control display element include an EL display such as an organic EL (Electro Luminescence) display equipped with an OLED (Organic Light Emitting Diode), an inorganic EL display provided with an inorganic light emitting diode, and an EL display.
  • EL display such as an organic EL (Electro Luminescence) display equipped with an OLED (Organic Light Emitting Diode), an inorganic EL display provided with an inorganic light emitting diode, and an EL display.
  • the voltage control display element there is a liquid crystal

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

A display device (100) according to the present invention comprises a first transistor (1) which is formed by stacking, on a substrate (3), an oxide semiconductor layer (6), an upper gate insulating film (7), an upper gate electrode (8) and an interlayer insulating film (9). The upper gate electrode (8) of the first transistor (1) comprises a metal oxide layer (8a) and a metal layer (8b) that covers the lateral surface and the upper surface of the metal oxide layer (8a), said layers being sequentially stacked from the substrate (3) side. The oxide semiconductor layer (6) of the first transistor (1) comprises: a channel region (6a) which faces the metal oxide layer (8a); a source region (6b) and a drain region (6c), which are arranged such that the channel region (6a) is sandwiched therebetween; a first active region (6d) which is arranged between the channel region (6a) and the source region (6b) so as to face the metal layer (8b); and a second active region (6e) which is arranged between the channel region (6a) and the drain region (6c) so as to face the metal layer (8b).

Description

表示装置Display device
　本発明は、トランジスタを有する表示装置に関する。 The present invention relates to a display device having a transistor.
　近年、ＯＬＥＤ（Ｏｒｇａｎｉｃ　Ｌｉｇｈｔ　Ｅｍｉｔｔｉｎｇ　Ｄｉｏｄｅ）技術の進歩に伴い、有機ＥＬ（エレクトロルミネッセンス）表示装置を備えた製品が広がってきている。一般に、有機ＥＬ表示装置では、発光層における画素に電流を供給する画素回路を含む構成を用いられており、画素回路には、ＴＦＴ（薄膜トランジスタ）が設けられている。画素回路に用いるＴＦＴとしては、例えば、トップゲート構造が挙げられる（例えば、特許文献１参照）。 In recent years, with the progress of OLED (Organic Light Emitting Diode) technology, products equipped with an organic EL (electroluminescence) display device have been spreading. Generally, an organic EL display device uses a configuration including a pixel circuit that supplies a current to pixels in a light emitting layer, and the pixel circuit is provided with a TFT (thin film transistor). Examples of the TFT used in the pixel circuit include a top gate structure (see, for example, Patent Document 1).
特開２０１５－１１１７０６号公報Japanese Unexamined Patent Publication No. 2015-111706
　特許文献１に記載の半導体装置は、シリコンを有する半導体領域と、半導体領域上方の絶縁層と、絶縁層上方の導電層とを有し、半導体領域にチャネル形成領域が設けられている。 The semiconductor device described in Patent Document 1 has a semiconductor region having silicon, an insulating layer above the semiconductor region, and a conductive layer above the insulating layer, and a channel forming region is provided in the semiconductor region.
　上述した半導体装置のように、導体化してチャネルを形成したトランジスタでは、チャネルとドレインとの境界において、互いの抵抗率の差により高電界が印加され、電荷が集中して耐圧の低下を引き起こすことがあった。 In a transistor in which a channel is formed by conducting a conductor like the above-mentioned semiconductor device, a high electric field is applied at the boundary between the channel and the drain due to the difference in resistivity between the channels, and electric charges are concentrated to cause a decrease in withstand voltage. was there.
　本発明は、上記の課題を解決するためになされたものであり、電界集中を緩和して耐圧を向上させることができる表示装置を提供することを目的とする。 The present invention has been made to solve the above problems, and an object of the present invention is to provide a display device capable of relaxing electric field concentration and improving withstand voltage.
　本発明に係る表示装置は、基板上に、酸化物半導体層、上部ゲート絶縁膜、上部ゲート電極、および層間絶縁膜を積層して形成された第１トランジスタを有する表示装置であって、前記第１トランジスタの前記上部ゲート電極は、前記基板側から順に積層された金属酸化物層と、前記金属酸化物層の側面および上面を覆う金属層とを有し、前記第１トランジスタの前記酸化物半導体層は、前記上部ゲート絶縁膜を介して、前記金属酸化物層と対向するチャネル領域と、前記チャネル領域を互いの間に挟むように設けられたソース領域およびドレイン領域と、前記チャネル領域と前記ソース領域との間に設けられ、前記上部ゲート絶縁膜を介して、前記金属層と対向する第１活性領域と、前記チャネル領域と前記ドレイン領域との間に設けられ、前記上部ゲート絶縁膜を介して、前記金属層と対向する第２活性領域とを含むことを特徴とする。 The display device according to the present invention is a display device having a first transistor formed by laminating an oxide semiconductor layer, an upper gate insulating film, an upper gate electrode, and an interlayer insulating film on a substrate. The upper gate electrode of one transistor has a metal oxide layer laminated in order from the substrate side and a metal layer covering the side surface and the upper surface of the metal oxide layer, and the oxide semiconductor of the first transistor. The layers include a channel region facing the metal oxide layer via the upper gate insulating film, a source region and a drain region provided so as to sandwich the channel region between each other, and the channel region and the above. The upper gate insulating film is provided between the first active region facing the metal layer and the channel region and the drain region via the upper gate insulating film. It is characterized by including a second active region facing the metal layer via the metal layer.
　本発明に係る表示装置では、前記金属酸化物層は、Ｉｎを含有している構成としてもよい。 In the display device according to the present invention, the metal oxide layer may be configured to contain In.
　本発明に係る表示装置では、前記金属酸化物層は、ＧａおよびＺｎを含有している構成としてもよい。 In the display device according to the present invention, the metal oxide layer may be configured to contain Ga and Zn.
　本発明に係る表示装置では、前記金属酸化物層は、ＳｎおよびＺｎを含有している構成としてもよい。 In the display device according to the present invention, the metal oxide layer may be configured to contain Sn and Zn.
　本発明に係る表示装置では、前記第１活性領域および前記第２活性領域は、前記チャネル領域よりも抵抗率が低く、前記ソース領域および前記ドレイン領域よりも抵抗率が高い構成としてもよい。 In the display device according to the present invention, the first active region and the second active region may have a lower resistivity than the channel region and a higher resistivity than the source region and the drain region.
　本発明に係る表示装置では、前記第１トランジスタの前記チャネル領域は、前記金属酸化物層と整合し、前記第１活性領域の前記ソース領域側の端部は、前記金属層の前記ソース領域側の端部と整合し、前記第２活性領域の前記ドレイン領域側の端部は、前記金属層の前記ドレイン領域側の端部と整合する構成としてもよい。 In the display device according to the present invention, the channel region of the first transistor is aligned with the metal oxide layer, and the end of the first active region on the source region side is the source region side of the metal layer. The end portion of the second active region on the drain region side may be aligned with the end portion of the metal layer on the drain region side.
　本発明に係る表示装置では、前記上部ゲート電極は、前記上部ゲート絶縁膜と整合する構成としてもよい。 In the display device according to the present invention, the upper gate electrode may be configured to match the upper gate insulating film.
　本発明に係る表示装置では、前記上部ゲート絶縁膜は、酸化シリコン膜である構成としてもよい。 In the display device according to the present invention, the upper gate insulating film may be configured to be a silicon oxide film.
　本発明に係る表示装置では、前記層間絶縁膜は、前記酸化物半導体層および前記上部ゲート電極と接する部分が、窒化シリコン膜で形成されている構成としてもよい。 In the display device according to the present invention, the interlayer insulating film may be configured such that a portion in contact with the oxide semiconductor layer and the upper gate electrode is formed of a silicon nitride film.
　本発明に係る表示装置では、前記層間絶縁膜は、前記酸化物半導体層および前記上部ゲート電極と接する部分が、酸化シリコン膜で形成されている構成としてもよい。 In the display device according to the present invention, the interlayer insulating film may be configured such that a portion in contact with the oxide semiconductor layer and the upper gate electrode is formed of a silicon oxide film.
　本発明に係る表示装置では、前記基板と前記酸化物半導体層の間には、下部ゲート電極と下部ゲート絶縁膜とが設けられ、前記下部ゲート電極は、前記下部ゲート絶縁膜を介して、前記チャネル領域と重畳する構成としてもよい。 In the display device according to the present invention, a lower gate electrode and a lower gate insulating film are provided between the substrate and the oxide semiconductor layer, and the lower gate electrode is formed via the lower gate insulating film. It may be configured to overlap with the channel region.
　本発明に係る表示装置では、前記下部ゲート電極は、前記ソース領域側の端部が、前記ソース領域と重畳し、前記ドレイン領域側の端部が、前記ドレイン領域と重畳する構成としてもよい。 In the display device according to the present invention, the lower gate electrode may be configured such that the end portion on the source region side overlaps with the source region and the end portion on the drain region side overlaps with the drain region.
　本発明に係る表示装置では、前記下部ゲート電極は、前記ソース領域側の端部が、前記第１活性領域と重畳し、前記ドレイン領域側の端部が、前記第２活性領域と重畳する構成としてもよい。 In the display device according to the present invention, the lower gate electrode has a configuration in which the end portion on the source region side overlaps with the first active region and the end portion on the drain region side overlaps with the second active region. May be.
　本発明に係る表示装置は、額縁領域にモノリシックに設けられた周辺回路を備え、前記第１トランジスタは、前記周辺回路に含まれるスイッチングトランジスタである構成としてもよい。 The display device according to the present invention may include a peripheral circuit monolithically provided in the frame region, and the first transistor may be a switching transistor included in the peripheral circuit.
　本発明に係る表示装置は、前記基板上には、酸化物半導体層、上部ゲート絶縁膜、上部ゲート電極、および層間絶縁膜を積層して形成された第２トランジスタが設けられ、前記第２トランジスタの前記上部ゲート電極は、前記基板側から順に積層された金属酸化物層と、金属層とを有し、前記第２トランジスタの前記酸化物半導体層は、前記上部ゲート絶縁膜を介して、前記上部ゲート電極と対向するチャネル領域と、前記チャネル領域を互いの間に挟むように設けられたソース領域およびドレイン領域とを含む構成としてもよい。 In the display device according to the present invention, a second transistor formed by laminating an oxide semiconductor layer, an upper gate insulating film, an upper gate electrode, and an interlayer insulating film is provided on the substrate, and the second transistor is provided. The upper gate electrode has a metal oxide layer and a metal layer laminated in this order from the substrate side, and the oxide semiconductor layer of the second transistor passes through the upper gate insulating film. The configuration may include a channel region facing the upper gate electrode and a source region and a drain region provided so as to sandwich the channel region between them.
　本発明に係る表示装置は、表示領域にマトリクス状に設けられた画素回路を備え、前記画素回路は、前記第１トランジスタと、前記第２トランジスタと、容量とを含み、前記第１トランジスタは、閾値制御トランジスタであり、前記第２トランジスタは、駆動トランジスタであり、前記駆動トランジスタは、制御端子が、前記容量の一方の電極と電気的に接続され、前記閾値制御トランジスタは、一方の導通端子が、前記駆動トランジスタの一方の導通端子と電気的に接続され、他方の導通端子が、自身の制御端子と電気的に接続される構成としてもよい。 The display device according to the present invention includes pixel circuits provided in a matrix in a display region, the pixel circuits include the first transistor, the second transistor, and a capacitance, and the first transistor includes a capacitance. It is a threshold control transistor, the second transistor is a drive transistor, the control terminal of the drive transistor is electrically connected to one electrode of the capacitance, and the threshold control transistor has one conduction terminal. , One conductive terminal of the drive transistor may be electrically connected, and the other conductive terminal may be electrically connected to its own control terminal.
　本発明に係る表示装置は、額縁領域に設けられた端子部と、前記端子部から延伸された引き回し配線と、前記端子部と表示領域との間に設けられたフィルタ回路とを備え、前記端子部は、前記フィルタ回路を介して、前記表示領域の配線と電気的に接続され、前記第１トランジスタは、前記フィルタ回路に含まれる構成としてもよい。 The display device according to the present invention includes a terminal portion provided in the frame region, a routing wiring extended from the terminal portion, and a filter circuit provided between the terminal portion and the display area, and the terminal. The unit may be electrically connected to the wiring in the display area via the filter circuit, and the first transistor may be included in the filter circuit.
　本発明に係る表示装置では、前記ソース領域は、高電源電圧線と電気的に接続され、前記ドレイン領域および前記上部ゲート電極は、前記引き回し配線と電気的に接続される構成としてもよい。 In the display device according to the present invention, the source region may be electrically connected to the high power supply voltage line, and the drain region and the upper gate electrode may be electrically connected to the routing wiring.
　本発明に係る表示装置では、前記ソース領域は、前記引き回し配線と電気的に接続され、前記ドレイン領域および前記上部ゲート電極は、低電源電圧線と電気的に接続される構成としてもよい。 In the display device according to the present invention, the source region may be electrically connected to the routing wiring, and the drain region and the upper gate electrode may be electrically connected to the low power supply voltage line.
　本発明に係る表示装置では、前記引き回し配線は、前記表示領域のデータ信号線と電気的に接続される構成としてもよい。 In the display device according to the present invention, the routing wiring may be configured to be electrically connected to the data signal line in the display area.
　本発明に係る表示装置では、前記引き回し配線は、前記表示領域の走査信号線と電気的に接続される構成としてもよい。 In the display device according to the present invention, the routing wiring may be configured to be electrically connected to the scanning signal line in the display area.
　本発明に係る表示装置では、前記ソース領域と前記ドレイン領域とが対向するチャネル長方向において、前記第２活性領域の長さは、前記第１活性領域の長さよりも長い構成としてもよい。 In the display device according to the present invention, the length of the second active region may be longer than the length of the first active region in the channel length direction in which the source region and the drain region face each other.
　本発明によると、チャネル領域の端部に接合する活性領域を設けることで、ＬＤＤ構造が形成されて、電界集中を緩和して耐圧を向上させることができる。 According to the present invention, by providing an active region to be joined at the end of the channel region, an LDD structure can be formed, electric field concentration can be relaxed, and withstand voltage can be improved.
本発明の第１実施形態に係る表示装置における第１トランジスタを模式的に示す模式断面図である。It is a schematic cross-sectional view which shows typically the 1st transistor in the display device which concerns on 1st Embodiment of this invention. 図１に示す第１トランジスタを模式的に示す模式平面図である。It is a schematic plan view which shows typically the 1st transistor shown in FIG. 本発明の第２実施形態に係る表示装置における第１トランジスタを模式的に示す模式断面図である。It is a schematic cross-sectional view which shows typically the 1st transistor in the display device which concerns on 2nd Embodiment of this invention. 図３に示す第１トランジスタの変形例の模式断面図である。It is a schematic cross-sectional view of the modification of the 1st transistor shown in FIG. 本発明の第３実施形態に係る表示装置における第２トランジスタを模式的に示す模式断面図である。It is a schematic cross-sectional view which shows typically the 2nd transistor in the display device which concerns on 3rd Embodiment of this invention. 本発明の第４実施形態に係る表示装置を模式的に示す概略構成図である。It is a schematic block diagram which shows typically the display device which concerns on 4th Embodiment of this invention. 第１トランジスタを用いたフィルタ回路の一部を示す回路構成図である。It is a circuit block diagram which shows a part of the filter circuit using the 1st transistor. フィルタ回路における一部の第１トランジスタを示す模式平面図である。It is a schematic plan view which shows a part 1st transistor in a filter circuit. 図８の矢符Ｃ－Ｃでの断面を示す模式断面図である。It is a schematic cross-sectional view which shows the cross section at the arrow CC of FIG. 図８の矢符Ｄ－Ｄでの断面を示す模式断面図である。It is a schematic cross-sectional view which shows the cross section at the arrow DD of FIG. 本発明の第５実施形態に係る表示装置における第１トランジスタを模式的に示す模式断面図である。It is a schematic cross-sectional view which shows typically the 1st transistor in the display device which concerns on 5th Embodiment of this invention. 図１０に示す第１トランジスタを模式的に示す模式平面図である。It is a schematic plan view which shows typically the 1st transistor shown in FIG. 表示装置の画素回路を示す等価回路図である。It is an equivalent circuit diagram which shows the pixel circuit of a display device.
　（第１実施形態）
　以下、本発明の第１実施形態に係る表示装置について、図面を参照して説明する。 (First Embodiment)
Hereinafter, the display device according to the first embodiment of the present invention will be described with reference to the drawings.
　図１は、本発明の第１実施形態に係る表示装置における第１トランジスタを模式的に示す模式断面図であって、図２は、図１に示す第１トランジスタを模式的に示す模式平面図である。なお、図面の見易さを考慮して、図１では、ハッチングを省略しており、図２では、下地層５や層間絶縁膜９等を透視的に示している。また、図１は、図２の矢符Ａ－Ａでの断面に相当する。 FIG. 1 is a schematic cross-sectional view schematically showing a first transistor in the display device according to the first embodiment of the present invention, and FIG. 2 is a schematic plan view schematically showing the first transistor shown in FIG. Is. In consideration of the legibility of the drawings, hatching is omitted in FIG. 1, and the base layer 5 and the interlayer insulating film 9 and the like are transparently shown in FIG. Further, FIG. 1 corresponds to the cross section of the arrow AA in FIG.
　本発明の第１実施形態に係る表示装置１００（後述する図６参照）における第１トランジスタ１（薄膜トランジスタ：ＴＦＴ）は、基板３に、下地層５、酸化物半導体層６、上部ゲート絶縁膜７、上部ゲート電極８、層間絶縁膜９（第１層間絶縁膜９ａおよび第２層間絶縁膜９ｂ）、および端子電極（ソース電極１０およびドレイン電極１１）を順に積層して形成されている。 The first transistor 1 (thin film transistor: TFT) in the display device 100 (see FIG. 6 described later) according to the first embodiment of the present invention has a base layer 5, an oxide semiconductor layer 6, and an upper gate insulating film 7 on a substrate 3. , The upper gate electrode 8, the interlayer insulating film 9 (the first interlayer insulating film 9a and the second interlayer insulating film 9b), and the terminal electrode (source electrode 10 and drain electrode 11) are laminated in this order.
　図１では、基板３上に形成された１つの第１トランジスタ１を拡大して示しており、基板３には、さらに、複数のトランジスタが形成されていてもよい。下地層５は、基板３全体を覆うように形成されている。なお、以下では説明のため、基板３の表面に沿う方向をチャネル長方向Ｌと呼ぶことがある。 FIG. 1 shows an enlarged view of one first transistor 1 formed on the substrate 3, and a plurality of transistors may be further formed on the substrate 3. The base layer 5 is formed so as to cover the entire substrate 3. In the following, for the sake of explanation, the direction along the surface of the substrate 3 may be referred to as the channel length direction L.
　酸化物半導体層６は、下地層５上に設けられ、それぞれの第１トランジスタ１毎に配置されている。つまり、酸化物半導体層６は、他のトランジスタにおける酸化物半導体層６と離間して設けられている。上部ゲート絶縁膜７は、酸化物半導体層６上に設けられ、上部ゲート電極８は、上部ゲート絶縁膜７上に設けられている。 The oxide semiconductor layer 6 is provided on the base layer 5, and is arranged for each first transistor 1. That is, the oxide semiconductor layer 6 is provided apart from the oxide semiconductor layer 6 in other transistors. The upper gate insulating film 7 is provided on the oxide semiconductor layer 6, and the upper gate electrode 8 is provided on the upper gate insulating film 7.
　本実施の形態において、上部ゲート電極８は、基板３側から順に積層された金属酸化物層８ａと、金属酸化物層８ａの側面および上面を覆う金属層８ｂとで構成されている。具体的に、金属酸化物層８ａは、金属層８ｂよりも、チャネル長方向Ｌでの長さが短く、上部ゲート絶縁膜７の中央は覆っているが、上部ゲート絶縁膜７の両端部を覆っていない。金属層８ｂは、平面視において、上部ゲート絶縁膜７と整合している。つまり、金属層８ｂは、上部ゲート絶縁膜７全体を覆うように設けられており、上部ゲート絶縁膜７のうち、金属酸化物層８ａに覆われていない部分は、金属層８ｂによって覆われている。なお、ここでの整合とは、厳密に一致することを意味せず、エッチングレートの違いなどによって生じる数μｍ程度の寸法のズレも含まれる。 In the present embodiment, the upper gate electrode 8 is composed of a metal oxide layer 8a laminated in order from the substrate 3 side, and a metal layer 8b covering the side surface and the upper surface of the metal oxide layer 8a. Specifically, the metal oxide layer 8a has a shorter length in the channel length direction L than the metal layer 8b, and covers the center of the upper gate insulating film 7, but covers both ends of the upper gate insulating film 7. Not covered. The metal layer 8b is aligned with the upper gate insulating film 7 in a plan view. That is, the metal layer 8b is provided so as to cover the entire upper gate insulating film 7, and the portion of the upper gate insulating film 7 that is not covered by the metal oxide layer 8a is covered by the metal layer 8b. There is. It should be noted that the matching here does not mean that the matching is exact, and includes a dimensional deviation of about several μm caused by a difference in etching rate or the like.
　酸化物半導体層６は、チャネル長方向Ｌでの両端部に位置する導体領域（ソース領域６ｂおよびドレイン領域６ｃ）と、チャネル長方向Ｌでの中央部に位置するチャネル領域６ａとを含む。導体領域は、酸化物半導体がチャネル領域６ａよりも低抵抗化された領域である。金属酸化物層８ａは、上部ゲート絶縁膜７を介して、チャネル領域６ａに対向している。 The oxide semiconductor layer 6 includes conductor regions (source region 6b and drain region 6c) located at both ends in the channel length direction L and a channel region 6a located at the center in the channel length direction L. The conductor region is a region in which the oxide semiconductor has a lower resistance than the channel region 6a. The metal oxide layer 8a faces the channel region 6a via the upper gate insulating film 7.
　酸化物半導体層６は、チャネル領域６ａとソース領域６ｂとの間に設けられた第１活性領域６ｄと、チャネル領域６ａとドレイン領域６ｃとの間に設けられた第２活性領域６ｅとを有している。第１活性領域６ｄおよび第２活性領域６ｅは、上部ゲート電極８のうち、金属層８ｂだけが設けられた部分に対し、上部ゲート絶縁膜７を介して対向している。 The oxide semiconductor layer 6 has a first active region 6d provided between the channel region 6a and the source region 6b, and a second active region 6e provided between the channel region 6a and the drain region 6c. are doing. The first active region 6d and the second active region 6e face the portion of the upper gate electrode 8 provided with only the metal layer 8b via the upper gate insulating film 7.
　層間絶縁膜９（第１層間絶縁膜９ａおよび第２層間絶縁膜９ｂ）は、酸化物半導体層６および上部ゲート電極８を覆うように形成されている。第１トランジスタ１では、第２層間絶縁膜９ｂ上に、ソース電極１０（図１では、左方）およびドレイン電極１１（図１では、右方）が設けられている。ソース電極１０とドレイン電極１１とは、チャネル長方向Ｌで離間して設けられている。 The interlayer insulating film 9 (first interlayer insulating film 9a and second interlayer insulating film 9b) is formed so as to cover the oxide semiconductor layer 6 and the upper gate electrode 8. In the first transistor 1, a source electrode 10 (left in FIG. 1) and a drain electrode 11 (right in FIG. 1) are provided on the second interlayer insulating film 9b. The source electrode 10 and the drain electrode 11 are provided apart from each other in the channel length direction L.
　ソース電極１０は、第１層間絶縁膜９ａおよび第２層間絶縁膜９ｂに設けられたソースコンタクトホールＨａを介して、酸化物半導体層６のうち、ソース領域６ｂと電気的に接続されている。ドレイン電極１１は、第１層間絶縁膜９ａおよび第２層間絶縁膜９ｂに設けられたドレインコンタクトホールＨｂを介して、酸化物半導体層６のうち、ドレイン領域６ｃと電気的に接続されている。 The source electrode 10 is electrically connected to the source region 6b of the oxide semiconductor layer 6 via the source contact hole Ha provided in the first interlayer insulating film 9a and the second interlayer insulating film 9b. The drain electrode 11 is electrically connected to the drain region 6c of the oxide semiconductor layer 6 via the drain contact holes Hb provided in the first interlayer insulating film 9a and the second interlayer insulating film 9b.
　上述したように、第１トランジスタ１は、基板３の上に、第１金属配線、第２金属配線、および第３金属配線の３つの金属配線が順に積層されており、それぞれの金属配線の間に、絶縁膜が設けられている。ここで、第１金属配線は、上部ゲート電極８および第２引き回し配線１０４ｂ（後述する図８参照）を含んでいる。第２金属配線は、第１引き回し配線１０４ａ（後述する図８参照）を含んでいる。第３金属配線は、フィルタ回路１０５の高電源電圧線ＥＬＶＤＤ、フィルタ回路１０５の低電源電圧線ＥＬＶＳＳ、および各種の配線間を接続する接続配線を含んでいる。 As described above, in the first transistor 1, three metal wirings of a first metal wiring, a second metal wiring, and a third metal wiring are laminated in this order on the substrate 3, and between the metal wirings. Is provided with an insulating film. Here, the first metal wiring includes the upper gate electrode 8 and the second routing wiring 104b (see FIG. 8 described later). The second metal wiring includes the first routing wiring 104a (see FIG. 8 described later). The third metal wiring includes a high power supply voltage line EL VDD of the filter circuit 105, a low power supply voltage line ELVSS of the filter circuit 105, and a connection wiring for connecting various wirings.
　なお、定電位電圧線、第１引き回し配線、第２引き回し配線、フィルタ回路の高電源電圧線、フィルタ回路の低電源電圧線、および接続配線は、上述した組み合わせに特定されず、３つの金属配線のうちのいずれで構成されていてもよい。また、３つの金属配線を備える構成について説明したが、これに限定されず、金属配線の数を増やしてもよく、金属配線の間に、適宜絶縁膜を設ければよい。 The constant potential voltage line, the first routing wire, the second routing wiring, the high power supply voltage line of the filter circuit, the low power supply voltage line of the filter circuit, and the connection wiring are not specified in the above combination, and the three metal wirings. It may be composed of any of. Further, the configuration including the three metal wirings has been described, but the present invention is not limited to this, and the number of metal wirings may be increased, and an insulating film may be appropriately provided between the metal wirings.
　次に、第１トランジスタ１の製造工程について、詳細に説明する。 Next, the manufacturing process of the first transistor 1 will be described in detail.
　第１トランジスタ１の製造工程では、絶縁膜である下地層５を基板３上に成膜する。基板３としては、例えば、ガラス基板、シリコン基板、および耐熱性を有するプラスチック基板（樹脂基板）を用いることができる。プラスチック基板（樹脂基板）の材料としては、ポリエチレンテレフタレート（ＰＥＴ）、ポリエチレンナフタレート（ＰＥＮ）、ポリエーテルサルフォン（ＰＥＳ）、アクリル樹脂、およびポリイミド等を用いることができる。 In the manufacturing process of the first transistor 1, a base layer 5 which is an insulating film is formed on the substrate 3. As the substrate 3, for example, a glass substrate, a silicon substrate, and a heat-resistant plastic substrate (resin substrate) can be used. As the material of the plastic substrate (resin substrate), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), acrylic resin, polyimide and the like can be used.
　本実施の形態において、下地層５は、ＳｉＯ２膜をＣＶＤ法によって成膜した。下地層５は、これに限定されず、例えば、酸化珪素（ＳｉＯｘ）、窒化珪素（ＳｉＮｘ）、酸化窒化珪素（ＳｉＯｘＮｙ；ｘ＞ｙ）、窒化酸化珪素（ＳｉＮｘＯｙ；ｘ＞ｙ）、酸化アルミニウム、および酸化タンタルなどで形成されていてもよく、複数の層を積層してもよい。下地層５の厚さは、５００ｎｍ以下とされていることが好ましい。 In the present embodiment, the base layer 5 is formed by forming a SiO 2 film by a CVD method. The base layer 5 is not limited to this, and for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxide nitride (SiO x N y ; x> y), silicon nitride (SiN x Oy ;). It may be formed of x> y), aluminum oxide, tantalum oxide, or the like, or a plurality of layers may be laminated. The thickness of the base layer 5 is preferably 500 nm or less.
　続いて、下地層５の上に、酸化物半導体層６を成膜する。酸化物半導体層６は、例えば、スパッタリング法で形成され、厚さが５０ｎｍのＩｎ－Ｇａ－Ｚｎ－Ｏ系半導体膜とされている。そして、半導体層エッチング工程において、酸化物半導体層６は、フォトリソグラフィプロセスおよびエッチングによりパターニングすることによって、それぞれの第１トランジスタ１毎に対応した島状に形成される。 Subsequently, the oxide semiconductor layer 6 is formed on the base layer 5. The oxide semiconductor layer 6 is formed by, for example, a sputtering method, and is an In—Ga—Zn—O-based semiconductor film having a thickness of 50 nm. Then, in the semiconductor layer etching step, the oxide semiconductor layer 6 is formed into an island shape corresponding to each first transistor 1 by patterning by a photolithography process and etching.
　さらに、酸化物半導体層６を覆うように、上部ゲート絶縁膜７および上部ゲート電極８が成膜される。上部ゲート絶縁膜７は、ＣＶＤ法を用いて成膜された酸化珪素（ＳｉＯｘ）で形成される。上部ゲート絶縁膜７は、下地層５と同じ材料で形成してもよく、複数の層を重ねた積層構造とされていてもよく、厚さが２００ｎｍ以下とされていることが好ましい。 Further, the upper gate insulating film 7 and the upper gate electrode 8 are formed so as to cover the oxide semiconductor layer 6. The upper gate insulating film 7 is formed of silicon oxide (SiO x ) formed by a CVD method. The upper gate insulating film 7 may be formed of the same material as the base layer 5, may have a laminated structure in which a plurality of layers are laminated, and preferably has a thickness of 200 nm or less.
　上部ゲート電極８のうち、金属酸化物層８ａは、例えば、スパッタリング法を用いて成膜される。金属酸化物層８ａは、酸化物半導体層６と同じ材料で形成してもよく、Ｉｎ－Ｇａ－Ｚｎ－Ｏ（ＩＧＺＯ）系半導体膜とされている。なお、これに限らず、金属酸化物層８ａは、Ｉｎ－Ｚｎ－Ｏ（ＩＺＯ）系半導体膜や、Ｉｎ－Ｓｎ－Ｚｎ－Ｏ系半導体膜としてもよく、Ｈ２やＨ２Ｏに対するブロッキング性があるものであればよい。金属酸化物層８ａは、成膜した後、フォトリソグラフィプロセスによって適宜パターニングすればよい。 Of the upper gate electrode 8, the metal oxide layer 8a is formed by, for example, a sputtering method. The metal oxide layer 8a may be formed of the same material as the oxide semiconductor layer 6, and is an In—Ga—Zn—O (IGZO) -based semiconductor film. Not limited to this, the metal oxide layer 8a may be an In—Zn—O (IZO) -based semiconductor film or an In—Sn—Zn—O-based semiconductor film, and has a blocking property against H 2 and H 2 O. Anything that has The metal oxide layer 8a may be appropriately patterned by a photolithography process after forming a film.
　上部ゲート電極８のうち金属層８ｂは、スパッタリング法を用いて成膜され、例えば、アルミニウム（Ａｌ）、タングステン（Ｗ）、モリブデン（Ｍｏ）、タンタル（Ｔａ）、クロム（Ｃｒ）、チタン（Ｔｉ）、および銅（Ｃｕ）から選ばれた元素を含む金属膜、またはこれらの元素を成分とする合金膜などを用いてもよいし、これらのうちの複数の膜を含む積層膜を用いてもよい。本実施の形態において、金属層８ｂは、Ｔｉ／Ａｌ／Ｔｉで構成された積層膜とされ、厚さが１００ｎｍ以上３００ｎｍ以下とされている。 The metal layer 8b of the upper gate electrode 8 is formed by a sputtering method, and for example, aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), and titanium (Ti) are formed. ), And a metal film containing an element selected from copper (Cu), an alloy film containing these elements as a component, or a laminated film containing a plurality of these elements may be used. Good. In the present embodiment, the metal layer 8b is a laminated film composed of Ti / Al / Ti, and has a thickness of 100 nm or more and 300 nm or less.
　上部ゲート電極８の金属層８ｂと上部ゲート絶縁膜７とは、フォトリソグラフィプロセスによってパターニングした同じレジストマスクを用いて、連続してエッチングが行われる。これによって、金属層８ｂと上部ゲート絶縁膜７とは、パターニング形状が整合し、同じレジストパターンに基づいた形状に成形される。 The metal layer 8b of the upper gate electrode 8 and the upper gate insulating film 7 are continuously etched using the same resist mask patterned by the photolithography process. As a result, the metal layer 8b and the upper gate insulating film 7 have the same patterning shape and are formed into a shape based on the same resist pattern.
　このように、金属層８ｂと上部ゲート絶縁膜７とのパターニング形状を整合させることで、セルフアライメント構造とすることができる。これによって、工程を簡略化しつつ、両者を精度良く位置合わせすることができる。 By matching the patterning shapes of the metal layer 8b and the upper gate insulating film 7 in this way, a self-alignment structure can be obtained. As a result, both can be accurately aligned while simplifying the process.
　レジストマスクを除去した後、上部ゲート電極８の上方から、基板３の全面に対して、プラズマ処理が施される。プラズマ処理は、例えば、水素プラズマ処理やＨｅプラズマ処理などである。プラズマ処理では、上部ゲート電極８および上部ゲート絶縁膜７がマスクとして機能し、酸化物半導体層６のうち、上部ゲート電極８および上部ゲート絶縁膜７で覆われていない部分（上部ゲート絶縁膜７から露出した部分）であるソース領域６ｂおよびドレイン領域６ｃが低抵抗化される。 After removing the resist mask, plasma treatment is applied to the entire surface of the substrate 3 from above the upper gate electrode 8. The plasma treatment includes, for example, hydrogen plasma treatment and He plasma treatment. In the plasma treatment, the upper gate electrode 8 and the upper gate insulating film 7 function as a mask, and the portion of the oxide semiconductor layer 6 that is not covered with the upper gate electrode 8 and the upper gate insulating film 7 (upper gate insulating film 7). The resistance of the source region 6b and the drain region 6c, which are the portions exposed from the above, is reduced.
　そして、酸化物半導体層６および上部ゲート電極８を覆う第１層間絶縁膜９ａが成膜され、第１層間絶縁膜９ａの上に、第２層間絶縁膜９ｂが成膜される。第１層間絶縁膜９ａおよび第２層間絶縁膜９ｂは、下地層５と同様の材料および方法で形成してもよく、本実施の形態において、第１層間絶縁膜９ａは、厚さが１００ｎｍのＳｉＮとされ、第２層間絶縁膜９ｂは、厚さが４００ｎｍのＳｉＯ２とされている。 Then, a first interlayer insulating film 9a covering the oxide semiconductor layer 6 and the upper gate electrode 8 is formed, and a second interlayer insulating film 9b is formed on the first interlayer insulating film 9a. The first interlayer insulating film 9a and the second interlayer insulating film 9b may be formed by the same material and method as the base layer 5, and in the present embodiment, the first interlayer insulating film 9a has a thickness of 100 nm. It is SiN, and the second interlayer insulating film 9b is SiO 2 having a thickness of 400 nm.
　金属酸化物層８ａについては、酸化物半導体層６に対するプラズマ処理によって導体化され、窒化膜（第１層間絶縁膜９ａ）からの水素供給で抵抗が下がる。さらに、金属酸化物層８ａは、Ｔｉ（金属層８ｂ）からの水素拡散や、金属層８ｂ形成時のプラズマによって抵抗が下がる。このように、製造工程における下層への影響を、金属酸化物層８ａによってブロッキングしているため、酸化物半導体層６のうち、金属酸化物層８ａと重畳するチャネル領域６ａでは、導体化されず、真性半導体の性質を維持したままになる。これに対し、酸化物半導体層６のうち、金属層８ｂだけと重畳する第１活性領域６ｄおよび第２活性領域６ｅでは、一部の水素が金属層８ｂを透過するため、若干低抵抗化される。 The metal oxide layer 8a is made into a conductor by plasma treatment on the oxide semiconductor layer 6, and the resistance is lowered by supplying hydrogen from the nitride film (first interlayer insulating film 9a). Further, the resistance of the metal oxide layer 8a is lowered by hydrogen diffusion from Ti (metal layer 8b) and plasma at the time of forming the metal layer 8b. In this way, since the influence on the lower layer in the manufacturing process is blocked by the metal oxide layer 8a, the channel region 6a overlapping the metal oxide layer 8a of the oxide semiconductor layer 6 is not made into a conductor. , Retains the properties of intrinsic semiconductors. On the other hand, in the first active region 6d and the second active region 6e that overlap with only the metal layer 8b of the oxide semiconductor layer 6, some hydrogen permeates through the metal layer 8b, so that the resistance is slightly lowered. To.
　上述したように、第１活性領域６ｄおよび第２活性領域６ｅは、導体領域のように低抵抗化された領域であって、チャネル領域６ａよりも抵抗率が低く、ソース領域６ｂおよびドレイン領域６ｃよりも抵抗率が高い導体とされている。このように、チャネル領域６ａの端部に接合する活性領域（第１活性領域６ｄおよび第２活性領域６ｅ）を設けることで、ＬＤＤ構造が形成されて、電界集中を緩和して耐圧を向上させることができる。なお、ここでの耐圧とは、例えば、上部ゲート電極８に１０Ｖを印加し、ドレイン電極１１に印加する電圧を大きくしていく場合の耐圧を示している。 As described above, the first active region 6d and the second active region 6e are regions having a low resistivity such as a conductor region, have a resistivity lower than that of the channel region 6a, and the source region 6b and the drain region 6c. It is said to be a conductor with a higher resistivity than. By providing the active regions (first active region 6d and second active region 6e) joined to the end of the channel region 6a in this way, the LDD structure is formed, the electric field concentration is relaxed, and the withstand voltage is improved. be able to. The withstand voltage here indicates, for example, the withstand voltage when 10 V is applied to the upper gate electrode 8 and the voltage applied to the drain electrode 11 is increased.
　また、金属酸化物層８ａを設けることで、低抵抗化する領域を選別することできる。その結果、平面視した状態で、チャネル領域６ａは、金属酸化物層８ａと整合し、第１活性領域６ｄにおけるソース領域６ｂ側の端部は、金属層８ｂにおけるソース領域６ｂ側の端部と整合し、第２活性領域６ｅにおけるドレイン領域６ｃ側の端部は、金属層８ｂにおけるドレイン領域６ｃ側の端部と整合する。このように、上層と下層とで端部が整合したセルフアライメント構造を用いることで、工程を簡略化しつつ、両者を精度良く位置合わせすることができる。 Further, by providing the metal oxide layer 8a, it is possible to select the region where the resistance is lowered. As a result, in the plan view, the channel region 6a is aligned with the metal oxide layer 8a, and the end portion of the first active region 6d on the source region 6b side is the end portion of the metal layer 8b on the source region 6b side. The end portion of the second active region 6e on the drain region 6c side is aligned with the end portion of the metal layer 8b on the drain region 6c side. By using the self-alignment structure in which the ends of the upper layer and the lower layer are aligned in this way, it is possible to align the two with high accuracy while simplifying the process.
　本実施の形態において、チャネル領域６ａ、第１活性領域６ｄ、および第２活性領域６ｅを併せたチャネル長方向Ｌの長さは、１０μｍ程度とされ、第１活性領域６ｄおよび第２活性領域６ｅは、それぞれチャネル長方向Ｌの長さが、１μｍ程度とされている。 In the present embodiment, the length of the channel length direction L including the channel region 6a, the first active region 6d, and the second active region 6e is about 10 μm, and the first active region 6d and the second active region 6e The length of each channel length direction L is about 1 μm.
　第１層間絶縁膜９ａおよび第２層間絶縁膜９ｂには、公知のフォトリソグラフィプロセスにより、酸化物半導体層６の一部を露出するソースコンタクトホールＨａおよびドレインコンタクトホールＨｂが形成される。 A source contact hole Ha and a drain contact hole Hb that expose a part of the oxide semiconductor layer 6 are formed on the first interlayer insulating film 9a and the second interlayer insulating film 9b by a known photolithography process.
　第２層間絶縁膜９ｂを形成した後、第２層間絶縁膜９ｂ上およびコンタクトホール内に、ソース電極１０およびドレイン電極１１の基となる電極用導電膜を成膜している。電極用導電膜は、上部ゲート電極８として例示した材料を用いることができる。電極用導電膜に対して、パターニングを行うことで、互いに離間したソース電極１０とドレイン電極１１とが形成される。 After forming the second interlayer insulating film 9b, a conductive film for electrodes, which is the base of the source electrode 10 and the drain electrode 11, is formed on the second interlayer insulating film 9b and in the contact hole. As the conductive film for the electrode, the material exemplified as the upper gate electrode 8 can be used. By patterning the conductive film for electrodes, a source electrode 10 and a drain electrode 11 that are separated from each other are formed.
　酸化物半導体層６については、上述した材料だけに限らず、他の材料によって形成してもよい。酸化物半導体層６に含まれる酸化物半導体は、例えば、アモルファス酸化物半導体（非晶質酸化物半導体）であってもよいし、結晶質部分を有する結晶質酸化物半導体であってもよい。結晶質酸化物半導体としては、多結晶酸化物半導体、微結晶酸化物半導体、およびｃ軸が層面に概ね垂直に配向した結晶質酸化物半導体などが挙げられる。 The oxide semiconductor layer 6 is not limited to the above-mentioned materials, and may be formed of other materials. The oxide semiconductor contained in the oxide semiconductor layer 6 may be, for example, an amorphous oxide semiconductor (amorphous oxide semiconductor) or a crystalline oxide semiconductor having a crystalline portion. Examples of the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface.
　また、酸化物半導体層６は、２層以上の積層構造を有していてもよく、この場合、酸化物半導体層６は、非晶質酸化物半導体層と結晶質酸化物半導体層とを含んでいてもよい。あるいは、結晶構造が異なる複数の結晶質酸化物半導体層を含んでいてもよいし、複数の非晶質酸化物半導体層を含んでいてもよい。 Further, the oxide semiconductor layer 6 may have a laminated structure of two or more layers, and in this case, the oxide semiconductor layer 6 includes an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. You may be. Alternatively, it may contain a plurality of crystalline oxide semiconductor layers having different crystal structures, or may include a plurality of amorphous oxide semiconductor layers.
　次に、非晶質酸化物半導体および結晶質酸化物半導体の材料や構造などについて、詳細に説明する。酸化物半導体層６は、例えば、Ｉｎ、Ｇａ、およびＺｎのうち、少なくとも１種の金属元素を含んでいてもよく、本実施の形態では、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体（例えば、酸化インジウムガリウム亜鉛）を用いた。ここで、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体は、Ｉｎ（インジウム）、Ｇａ（ガリウム）、およびＺｎ（亜鉛）の三元系酸化物であって、Ｉｎ、Ｇａ、およびＺｎの割合（組成比）は、特に限定されず、例えば、Ｉｎ：Ｇａ：Ｚｎ＝２：２：１、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１、およびＩｎ：Ｇａ：Ｚｎ＝１：１：２等を含む。また、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体は、アモルファスでもよいし、結晶質でもよい。結晶質Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体としては、ｃ軸が層面に概ね垂直に配向した結晶質Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体が好ましい。 Next, the materials and structures of the amorphous oxide semiconductor and the crystalline oxide semiconductor will be described in detail. The oxide semiconductor layer 6 may contain at least one metal element among, for example, In, Ga, and Zn, and in the present embodiment, the In—Ga—Zn—O-based semiconductor (for example, Indium gallium zinc oxide) was used. Here, the In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the proportion (composition) of In, Ga, and Zn. The ratio) is not particularly limited, and includes, for example, In: Ga: Zn = 2: 2: 1, In: Ga: Zn = 1: 1: 1, and In: Ga: Zn = 1: 1: 2. .. Further, the In—Ga—Zn—O-based semiconductor may be amorphous or crystalline. As the crystalline In—Ga—Zn—O-based semiconductor, a crystalline In—Ga—Zn—O-based semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable.
　Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体層を有するＴＦＴは、ａ－ＳｉＴＦＴに比べて、高い移動度および低いリーク電流を有しているので、表示装置１００の第１トランジスタ１として、好適に用いることができる。 A TFT having an In—Ga—Zn—O-based semiconductor layer has higher mobility and lower leakage current than an a—Si TFT, and is therefore preferably used as the first transistor 1 of the display device 100. be able to.
　酸化物半導体層６は、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体の換わりに、他の酸化物半導体を含んでいてもよく、例えば、Ｉｎ－Ｓｎ－Ｚｎ－Ｏ系半導体を含んでいてもよい。Ｉｎ－Ｓｎ－Ｚｎ－Ｏ系の半導体は、Ｉｎ、Ｓｎ（スズ）、およびＺｎの三元系酸化物であって、例えば、Ｉｎ２Ｏ３－ＳｎＯ２－ＺｎＯ（ＩｎＳｎＺｎＯ）などが挙げられる。 The oxide semiconductor layer 6 may contain another oxide semiconductor instead of the In—Ga—Zn—O semiconductor, and may contain, for example, an In—Sn—Zn—O semiconductor. In-Sn-Zn-O-based semiconductor is, In, a ternary oxide of Sn (tin), and Zn, for example, In 2 O 3 -SnO 2 -ZnO (InSnZnO) , and the like.
　酸化物半導体層６は、これに限らず、Ｉｎ－Ａｌ－Ｚｎ－Ｏ系半導体、Ｉｎ－Ａｌ－Ｓｎ－Ｚｎ－Ｏ系半導体、Ｚｎ－Ｏ系半導体、Ｉｎ－Ｚｎ－Ｏ系半導体、Ｚｎ－Ｔｉ－Ｏ系半導体、Ｃｄ－Ｇｅ－Ｏ系半導体、Ｃｄ－Ｐｂ－Ｏ系半導体、ＣｄＯ（酸化カドミウム）、Ｍｇ－Ｚｎ－Ｏ系半導体、Ｉｎ－Ｇａ－Ｓｎ－Ｏ系半導体、Ｉｎ－Ｇａ－Ｏ系半導体、Ｚｒ－Ｉｎ－Ｚｎ－Ｏ系半導体、Ｈｆ－Ｉｎ－Ｚｎ－Ｏ系半導体、Ａｌ－Ｇａ－Ｚｎ－Ｏ系半導体、Ｇａ－Ｚｎ－Ｏ系半導体、Ｉｎ－Ｇａ－Ｚｎ－Ｓｎ－Ｏ系半導体、ＩｎＧａＯ３（ＺｎＯ）５、酸化マグネシウム亜鉛（ＭｇＸＺｎ１－ＸＯ）、および酸化カドミウム亜鉛（ＣｄＸＺｎ１－ＸＯ）などを含んでいてもよい。Ｚｎ－Ｏ系半導体としては、１族元素、１３族元素、１４族元素、１５族元素または１７族元素のうち一種、または複数種の不純物元素が添加されたＺｎＯの非晶質（アモルファス）状態、多結晶状態または非晶質状態と多結晶状態が混在する微結晶状態のもの、または何も不純物元素が添加されていないものを用いることができる。 The oxide semiconductor layer 6 is not limited to this, and the In—Al—Zn—O system semiconductor, In—Al—Sn—Zn—O system semiconductor, Zn—O system semiconductor, In—Zn—O system semiconductor, Zn— Ti-O-based semiconductors, Cd-Ge-O-based semiconductors, Cd-Pb-O-based semiconductors, CdO (cadmium oxide), Mg-Zn-O-based semiconductors, In-Ga-Sn-O-based semiconductors, In-Ga- O-based semiconductor, Zr-In-Zn-O-based semiconductor, Hf-In-Zn-O-based semiconductor, Al-Ga-Zn-O-based semiconductor, Ga-Zn-O-based semiconductor, In-Ga-Zn-Sn- It may contain O-based semiconductors, InGaO 3 (ZnO) 5 , zinc oxide (Mg X Zn 1-X O), zinc oxide (Cd X Zn 1-X O), and the like. As a Zn—O semiconductor, ZnO is in an amorphous state to which one or more of group 1 elements, group 13 elements, group 14 elements, group 15 elements or group 17 elements are added. , The polycrystalline state or the microcrystalline state in which the amorphous state and the polycrystalline state are mixed, or the one to which no impurity element is added can be used.
　（第２実施形態）
　次に、本発明の第２実施形態に係る表示装置について、図面を参照して説明する。なお、第２実施形態において、第１実施形態と機能が実質的に等しい構成要素については、同一の符号を付して説明を省略する。 (Second Embodiment)
Next, the display device according to the second embodiment of the present invention will be described with reference to the drawings. In the second embodiment, the components having substantially the same functions as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.
　図３は、本発明の第２実施形態に係る表示装置における第１トランジスタを模式的に示す模式断面図である。なお、図面の見易さを考慮して、図３では、ハッチングを省略している。 FIG. 3 is a schematic cross-sectional view schematically showing the first transistor in the display device according to the second embodiment of the present invention. In consideration of the legibility of the drawings, hatching is omitted in FIG.
　第２実施形態における第１トランジスタ１は、第１実施形態に対して、下部ゲート電極４を設けている点で異なる。具体的に、下部ゲート電極４は、基板３と下地層５との間に積層されている。なお、基板３は、表面に絶縁膜を設けるなどして、下部ゲート電極４と絶縁してもよい。また、本実施の形態では、下部ゲート電極４と酸化物半導体層６との間に、絶縁膜が設けられていることが望ましく、例えば、下地層５（下部ゲート絶縁膜に相当）が、絶縁性を有する材料で形成されていればよい。 The first transistor 1 in the second embodiment is different from the first embodiment in that the lower gate electrode 4 is provided. Specifically, the lower gate electrode 4 is laminated between the substrate 3 and the base layer 5. The substrate 3 may be insulated from the lower gate electrode 4 by providing an insulating film on the surface thereof. Further, in the present embodiment, it is desirable that an insulating film is provided between the lower gate electrode 4 and the oxide semiconductor layer 6. For example, the base layer 5 (corresponding to the lower gate insulating film) is insulated. It may be made of a material having a property.
　下部ゲート電極４は、上部ゲート電極８の金属層８ｂと同じ材料で形成してもよく、フォトリソグラフィプロセスによってパターニングされる。下部ゲート電極４は、ソース領域６ｂ側の端部が、ソース領域６ｂと重畳し、ドレイン領域６ｃ側の端部が、ドレイン領域と重畳しており、下地層５を介して、チャネル領域６ａ、第１活性領域６ｄ、および第２活性領域６ｅと対向している。 The lower gate electrode 4 may be formed of the same material as the metal layer 8b of the upper gate electrode 8 and is patterned by a photolithography process. In the lower gate electrode 4, the end portion on the source region 6b side overlaps with the source region 6b, and the end portion on the drain region 6c side overlaps with the drain region, and the channel region 6a, via the base layer 5, It faces the first active region 6d and the second active region 6e.
　表示装置１００で、第２実施形態における第１トランジスタ１を用いる際は、上部ゲート電極８と下部ゲート電極４とで異なる電圧を入力してもよい。例えば、上部ゲート電極８には、変動する電圧を入力して、トランジスタの駆動を制御し、下部ゲート電極４には、定電圧とされた閾値制御電圧を入力してもよい。このように、上部ゲート電極８と下部ゲート電極４とを備えたダブルゲート構造とすることで、トランジスタの特性を向上させることができる。 When the first transistor 1 in the second embodiment is used in the display device 100, different voltages may be input to the upper gate electrode 8 and the lower gate electrode 4. For example, a fluctuating voltage may be input to the upper gate electrode 8 to control the driving of the transistor, and a threshold control voltage set to a constant voltage may be input to the lower gate electrode 4. As described above, the double gate structure including the upper gate electrode 8 and the lower gate electrode 4 can improve the characteristics of the transistor.
　図４は、図３に示す第１トランジスタの変形例の模式断面図である。 FIG. 4 is a schematic cross-sectional view of a modified example of the first transistor shown in FIG.
　図４に示す変形例では、図３に示す構造に対して、チャネル長方向Ｌでの下部ゲート電極４の長さが異なる。具体的に、下部ゲート電極４は、ソース領域６ｂ側の端部が、第１活性領域６ｄと重畳し、ドレイン領域６ｃ側の端部が、第２活性領域６ｅと重畳している。つまり、図３の構造では、下部ゲート電極４が、上部ゲート電極８の全体と重畳し、端部がソース領域６ｂおよびドレイン領域６ｃと重畳する位置まではみ出していた。これに対し、変形例では、下部ゲート電極４が、上部ゲート電極８と重畳する範囲内に収まっている。その結果、ソース領域６ｂおよびドレイン領域６ｃに対して、下部ゲート電極４が重畳しない構造となるので、酸化物半導体層６と下部ゲート電極４との間に生じる寄生容量を減らすことができる。 In the modified example shown in FIG. 4, the length of the lower gate electrode 4 in the channel length direction L is different from that of the structure shown in FIG. Specifically, in the lower gate electrode 4, the end portion on the source region 6b side is superimposed on the first active region 6d, and the end portion on the drain region 6c side is superimposed on the second active region 6e. That is, in the structure of FIG. 3, the lower gate electrode 4 overlaps the entire upper gate electrode 8 and the end portion protrudes to a position where it overlaps with the source region 6b and the drain region 6c. On the other hand, in the modified example, the lower gate electrode 4 is within the range of overlapping with the upper gate electrode 8. As a result, the lower gate electrode 4 does not overlap with the source region 6b and the drain region 6c, so that the parasitic capacitance generated between the oxide semiconductor layer 6 and the lower gate electrode 4 can be reduced.
　（第３実施形態）
　次に、本発明の第３実施形態に係る表示装置について、図面を参照して説明する。なお、第３実施形態において、第１実施形態および第２実施形態と機能が実質的に等しい構成要素については、同一の符号を付して説明を省略する。 (Third Embodiment)
Next, the display device according to the third embodiment of the present invention will be described with reference to the drawings. In the third embodiment, the components having substantially the same functions as those of the first embodiment and the second embodiment are designated by the same reference numerals and the description thereof will be omitted.
　図５は、本発明の第３実施形態に係る表示装置における第２トランジスタを模式的に示す模式断面図である。なお、図面の見易さを考慮して、図５では、ハッチングを省略している。 FIG. 5 is a schematic cross-sectional view schematically showing a second transistor in the display device according to the third embodiment of the present invention. In consideration of the legibility of the drawings, hatching is omitted in FIG.
　第３実施形態において、基板３上には、第１トランジスタ１の他に、第２トランジスタ２が設けられており、図５では、基板３上に形成された１つの第２トランジスタ２を拡大して示している。 In the third embodiment, the second transistor 2 is provided on the substrate 3 in addition to the first transistor 1, and in FIG. 5, one second transistor 2 formed on the substrate 3 is enlarged. Is shown.
　第２トランジスタ２は、基板３に、下地層５、酸化物半導体層６、上部ゲート絶縁膜７、上部ゲート電極８、層間絶縁膜９（第１層間絶縁膜９ａおよび第２層間絶縁膜９ｂ）、および端子電極（ソース電極１０およびドレイン電極１１）を順に積層して形成されている。なお、第２トランジスタ２における各層については、第１トランジスタ１における各層を基板上に形成する際、同時に形成してもよく、各層は、略同様の材料および方法によって形成される。 The second transistor 2 has a base layer 5, an oxide semiconductor layer 6, an upper gate insulating film 7, an upper gate electrode 8, and an interlayer insulating film 9 (first interlayer insulating film 9a and second interlayer insulating film 9b) on the substrate 3. , And the terminal electrodes (source electrode 10 and drain electrode 11) are laminated in this order. The layers of the second transistor 2 may be formed at the same time when the layers of the first transistor 1 are formed on the substrate, and each layer is formed by substantially the same material and method.
　第２トランジスタ２は、第１トランジスタ１に対して、酸化物半導体層６および上部ゲート電極８の構成が異なっており、共通する部分については、説明を省略する。具体的に、第２トランジスタ２の上部ゲート電極８は、金属酸化物層８ａと金属層８ｂとを積層して形成されているが、金属酸化物層８ａを設けた範囲が第１トランジスタ１と異なる。具体的に、金属酸化物層８ａと金属層８ｂとは、チャネル長方向Ｌでの長さが同じとされており、金属酸化物層８ａは、上部ゲート絶縁膜７全体を覆うように設けられている。つまり、金属酸化物層８ａと金属層８ｂと上部ゲート絶縁膜７とは、平面視で整合している。なお、第２トランジスタ２の金属酸化物層８ａおよび金属層８ｂは、第１トランジスタ１の上部ゲート電極８における金属酸化物層８ａおよび金属層８ｂと、同じ材料で形成してもよい。 The second transistor 2 has a different configuration of the oxide semiconductor layer 6 and the upper gate electrode 8 from the first transistor 1, and the description of common parts will be omitted. Specifically, the upper gate electrode 8 of the second transistor 2 is formed by laminating a metal oxide layer 8a and a metal layer 8b, but the range in which the metal oxide layer 8a is provided is the same as that of the first transistor 1. different. Specifically, the metal oxide layer 8a and the metal layer 8b have the same length in the channel length direction L, and the metal oxide layer 8a is provided so as to cover the entire upper gate insulating film 7. ing. That is, the metal oxide layer 8a, the metal layer 8b, and the upper gate insulating film 7 are aligned in a plan view. The metal oxide layer 8a and the metal layer 8b of the second transistor 2 may be formed of the same material as the metal oxide layer 8a and the metal layer 8b of the upper gate electrode 8 of the first transistor 1.
　上部ゲート電極８を形成する工程において、第１トランジスタ１に対応する部分では、金属酸化物層８ａをパターニングしていたが、第２トランジスタ２に対応する部分では、金属酸化物層８ａをパターニングせず、金属層８ｂと併せて金属酸化物層８ａをエッチングしてもよい。また、金属酸化物層８ａをパターニングする際、上部ゲート電極８を設ける範囲より大きく残しておき、金属層８ｂと範囲を合わせるように、エッチングしてもよい。 In the step of forming the upper gate electrode 8, the metal oxide layer 8a was patterned in the portion corresponding to the first transistor 1, but the metal oxide layer 8a was patterned in the portion corresponding to the second transistor 2. Instead, the metal oxide layer 8a may be etched together with the metal layer 8b. Further, when the metal oxide layer 8a is patterned, it may be left larger than the range in which the upper gate electrode 8 is provided and etched so as to match the range with the metal layer 8b.
　第２トランジスタ２の酸化物半導体層６は、チャネル領域６ａ、ソース領域６ｂ、およびドレイン領域６ｃで構成されている。つまり、第２トランジスタ２は、第１トランジスタ１に対し、第１活性領域６ｄおよび第２活性領域６ｅを有しない点で異なる。 The oxide semiconductor layer 6 of the second transistor 2 is composed of a channel region 6a, a source region 6b, and a drain region 6c. That is, the second transistor 2 is different from the first transistor 1 in that it does not have the first active region 6d and the second active region 6e.
　上述したように、特性が異なる第１トランジスタ１と第２トランジスタ２とを同一の基板３上に設けることで、表示装置１００において、用途に応じたトランジスタを、適宜組み合わせて適用することができる。 As described above, by providing the first transistor 1 and the second transistor 2 having different characteristics on the same substrate 3, the display device 100 can be applied by appropriately combining transistors according to the application.
　（第４実施形態）
　次に、本発明の第４実施形態に係る表示装置について、図面を参照して説明する。なお、第４実施形態において、第１実施形態ないし第３実施形態と機能が実質的に等しい構成要素については、同一の符号を付して説明を省略する。 (Fourth Embodiment)
Next, the display device according to the fourth embodiment of the present invention will be described with reference to the drawings. In the fourth embodiment, the components having substantially the same functions as those of the first to third embodiments are designated by the same reference numerals and the description thereof will be omitted.
　図６は、本発明の第４実施形態に係る表示装置を模式的に示す概略構成図である。 FIG. 6 is a schematic configuration diagram schematically showing a display device according to a fourth embodiment of the present invention.
　本発明の第４実施形態に係る表示装置１００は、画素回路がマトリクス状に設けられた表示領域１０１と、表示領域１０１の周囲を囲む額縁領域１０２とを備える。額縁領域１０２には、外部と電気的に接続するための端子部１０３と、端子部１０３から延伸された引き回し配線１０４と、端子部１０３と表示領域１０１との間に設けられたフィルタ回路１０５（周辺回路の一例）とを備える。引き回し配線１０４は、表示装置１００のサイズに応じて、適宜数を決定すればよく、複数設けられている。 The display device 100 according to the fourth embodiment of the present invention includes a display area 101 in which pixel circuits are provided in a matrix, and a frame area 102 that surrounds the display area 101. In the frame area 102, a terminal portion 103 for electrically connecting to the outside, a routing wiring 104 extended from the terminal portion 103, and a filter circuit 105 provided between the terminal portion 103 and the display area 101 ( An example of a peripheral circuit) is provided. The number of the routing wiring 104 may be appropriately determined according to the size of the display device 100, and a plurality of routing wirings 104 are provided.
　フィルタ回路１０５では、高い電圧（ノイズ）が加わることがあり、耐圧の高いトランジスタを用いることが好ましい。また、フィルタ回路１０５が、低電圧のノイズをフィルタする回路として用いられる場合は、低電圧（低電源電圧）よりも電圧が低いノイズを通さないようにする。 In the filter circuit 105, a high voltage (noise) may be applied, so it is preferable to use a transistor having a high withstand voltage. Further, when the filter circuit 105 is used as a circuit for filtering low voltage noise, noise having a voltage lower than that of the low voltage (low power supply voltage) is prevented from passing through.
　図７は、第１トランジスタを用いたフィルタ回路の一部を示す回路構成図である。 FIG. 7 is a circuit configuration diagram showing a part of a filter circuit using the first transistor.
　フィルタ回路１０５では、複数の信号配線ＳＬ（引き回し配線１０４）に対して交差するように、低電源電圧線ＥＬＶＳＳと高電源電圧線ＥＬＶＤＤとが設けられている。図７では、４つの信号配線ＳＬに対して、低電源電圧線ＥＬＶＳＳと高電源電圧線ＥＬＶＤＤとがそれぞれ交差している状態を示しているが、これに限定されず、信号配線ＳＬの数は、増減してもよい。 In the filter circuit 105, a low power supply voltage line ELVSS and a high power supply voltage line EL VDD are provided so as to intersect a plurality of signal wiring SLs (route wiring 104). FIG. 7 shows a state in which the low power supply voltage line ELVSS and the high power supply voltage line EL VDD intersect with each other for the four signal wiring SLs, but the number of signal wiring SLs is not limited to this. , May increase or decrease.
　フィルタ回路１０５では、それぞれの信号配線ＳＬと低電源電圧線ＥＬＶＳＳとに接続された低電圧用トランジスタ１ａ（第１トランジスタ１）と、それぞれの信号配線ＳＬと高電源電圧線ＥＬＶＤＤとに接続された高電圧用トランジスタ１ｂ（第１トランジスタ１）とが設けられている。つまり、それぞれの信号配線ＳＬは、低電源電圧線ＥＬＶＳＳおよび高電源電圧線ＥＬＶＤＤと直接繋がっておらず、低電圧用トランジスタ１ａを介して低電源電圧線ＥＬＶＳＳと接続され、高電圧用トランジスタ１ｂを介して高電源電圧線ＥＬＶＤＤと接続されている。 In the filter circuit 105, the low voltage transistor 1a (first transistor 1) connected to each signal wiring SL and the low power supply voltage line ELVSS, and each signal wiring SL and the high power supply voltage line EL VDD are connected to each other. A high voltage transistor 1b (first transistor 1) is provided. That is, each signal wiring SL is not directly connected to the low power supply voltage line ELVSS and the high power supply voltage line EL VDD, but is connected to the low power supply voltage line ELVSS via the low voltage transistor 1a to connect the high voltage transistor 1b. It is connected to the high power supply voltage line EL VDD via.
　低電圧用トランジスタ１ａは、上部ゲート電極８およびドレイン電極１１が低電源電圧線ＥＬＶＳＳに接続され、ソース電極１０が信号配線ＳＬに接続されている。高電圧用トランジスタ１ｂは、ソース電極１０が高電源電圧線ＥＬＶＤＤに接続され、上部ゲート電極８およびドレイン電極１１が信号配線ＳＬに接続されている。 In the low voltage transistor 1a, the upper gate electrode 8 and the drain electrode 11 are connected to the low power supply voltage line ELVSS, and the source electrode 10 is connected to the signal wiring SL. In the high voltage transistor 1b, the source electrode 10 is connected to the high power supply voltage line EL VDD, and the upper gate electrode 8 and the drain electrode 11 are connected to the signal wiring SL.
　表示装置１００では、低電源電圧線ＥＬＶＳＳおよび高電源電圧線ＥＬＶＤＤに印加される電位が、それぞれ「ＥＬＶＳＳ」および「ＥＬＶＤＤ」として、所定の値に設定されている。低電圧用トランジスタ１ａは、「ＥＬＶＳＳ」以下の電位が信号配線ＳＬに印加された場合、信号配線ＳＬに印加される電位を「ＥＬＶＳＳ」に保つ低電圧フィルタとされており、高電圧用トランジスタ１ｂは、「ＥＬＶＤＤ」以上の電位が信号配線ＳＬに印加された場合、信号配線ＳＬに印加される電位を「ＥＬＶＤＤ」に保つ高電圧フィルタとされている。 In the display device 100, the potentials applied to the low power supply voltage line ELVSS and the high power supply voltage line EL VDD are set to predetermined values as "ELVSS" and "EL VDD", respectively. The low-voltage transistor 1a is a low-voltage filter that keeps the potential applied to the signal wiring SL at "ELVSS" when a potential of "ELVSS" or less is applied to the signal wiring SL, and is a high-voltage transistor 1b. Is a high voltage filter that keeps the potential applied to the signal wiring SL at "EL VDD" when a potential equal to or higher than "EL VDD" is applied to the signal wiring SL.
　図８は、フィルタ回路における一部の第１トランジスタを示す模式平面図であって、図９Ａは、図８の矢符Ｃ－Ｃでの断面を示す模式断面図であって、図９Ｂは、図８の矢符Ｄ－Ｄでの断面を示す模式断面図である。なお、図面の見易さを考慮して、図９Ａおよび図９Ｂでは、ハッチングを省略しており、図８では、下地層５や層間絶縁膜９等を透視的に示している。 FIG. 8 is a schematic plan view showing a part of the first transistor in the filter circuit, FIG. 9A is a schematic cross-sectional view showing a cross section at the arrow CC of FIG. 8, and FIG. 9B is a schematic cross-sectional view. It is a schematic cross-sectional view which shows the cross section at the arrow line DD of FIG. In consideration of the legibility of the drawings, hatching is omitted in FIGS. 9A and 9B, and the base layer 5 and the interlayer insulating film 9 and the like are transparently shown in FIG.
　図８では、フィルタ回路１０５に設けられた複数の第１トランジスタ１の一部（４つ）を抽出して示しており、２つの低電圧用トランジスタ１ａと２つの高電圧用トランジスタ１ｂとを示している。また、図９Ａは、低電圧のノイズをフィルタするフィルタ回路であって、２つの低電圧用トランジスタ１ａを示しており、図９Ｂは、高電圧のノイズをフィルタするフィルタ回路であって、２つの高電圧用トランジスタ１ｂを示している。本実施の形態においては、設ける層が異なる２種類の引き回し配線１０４が存在する。具体的に、２種類の引き回し配線１０４は、第１層間絶縁膜９ａの上に設けられた第１引き回し配線１０４ａと、下地層５の上に配線部絶縁膜１３を介して設けられた第２引き回し配線１０４ｂとである。２つの低電圧用トランジスタ１ａのうち、一方（第１低電圧用トランジスタ１ａａ）は、第１引き回し配線１０４ａに接続されており、他方（第２低電圧用トランジスタ１ａｂ）は、第２引き回し配線１０４ｂに接続されている。また、２つの高電圧用トランジスタ１ｂのうち、一方（第１高電圧用トランジスタ１ｂａ）は、第１引き回し配線１０４ａに接続されており、他方（第２高電圧用トランジスタ１ｂｂ）は、第２引き回し配線１０４ｂに接続されている。 In FIG. 8, a part (4) of a plurality of first transistors 1 provided in the filter circuit 105 is extracted and shown, and two low-voltage transistors 1a and two high-voltage transistors 1b are shown. ing. Further, FIG. 9A is a filter circuit for filtering low-voltage noise and shows two low-voltage transistors 1a, and FIG. 9B is a filter circuit for filtering high-voltage noise and has two. The high voltage transistor 1b is shown. In the present embodiment, there are two types of routing wiring 104 having different layers. Specifically, the two types of routing wiring 104 are the first routing wiring 104a provided on the first interlayer insulating film 9a and the second routing wiring 104 provided on the base layer 5 via the wiring portion insulating film 13. It is a routing wiring 104b. Of the two low-voltage transistors 1a, one (first low-voltage transistor 1aa) is connected to the first routing wiring 104a, and the other (second low-voltage transistor 1ab) is connected to the second routing wiring 104b. It is connected to the. Further, of the two high voltage transistors 1b, one (first high voltage transistor 1ba) is connected to the first routing wiring 104a, and the other (second high voltage transistor 1bb) is connected to the second routing. It is connected to the wiring 104b.
　第１引き回し配線１０４ａは、第１層間絶縁膜９ａを形成した後、第２層間絶縁膜９ｂを成膜する前に、金属膜の成膜とパターニングとによって形成すればよい。また、第１引き回し配線１０４ａに対するコンタクトホールは、ソースコンタクトホールＨａおよびドレインコンタクトホールＨｂと併せて、第２層間絶縁膜９ｂをエッチングして形成してもよいし、別にして形成してもよい。 The first routing wiring 104a may be formed by forming a metal film and patterning after forming the first interlayer insulating film 9a and before forming the second interlayer insulating film 9b. Further, the contact hole for the first routing wiring 104a may be formed by etching the second interlayer insulating film 9b together with the source contact hole Ha and the drain contact hole Hb, or may be formed separately. ..
　第２引き回し配線１０４ｂは、上部ゲート絶縁膜７および上部ゲート電極８を形成する工程と併せて形成される。つまり、上部ゲート電極８（特に、金属層８ｂ）におけるフォトリソグラフィプロセスの際、第２引き回し配線１０４ｂに対応する部分にもレジストマスクを形成すればよい。それによって、上部ゲート絶縁膜７および上部ゲート電極８におけるエッチングの際、第２引き回し配線１０４ｂと、第２引き回し配線１０４ｂに整合した配線部絶縁膜１３とが併せて成形される。また、第２引き回し配線１０４ｂに対するコンタクトホールは、ソースコンタクトホールＨａおよびドレインコンタクトホールＨｂと併せて、第１層間絶縁膜９ａおよび第２層間絶縁膜９ｂをエッチングして形成してもよいし、別にして形成してもよい。 The second routing wiring 104b is formed together with the step of forming the upper gate insulating film 7 and the upper gate electrode 8. That is, in the photolithography process of the upper gate electrode 8 (particularly, the metal layer 8b), a resist mask may be formed also on the portion corresponding to the second routing wiring 104b. As a result, when the upper gate insulating film 7 and the upper gate electrode 8 are etched, the second routing wiring 104b and the wiring portion insulating film 13 aligned with the second routing wiring 104b are formed together. Further, the contact hole for the second routing wiring 104b may be formed by etching the first interlayer insulating film 9a and the second interlayer insulating film 9b together with the source contact hole Ha and the drain contact hole Hb, or separately. May be formed.
　低電源電圧線ＥＬＶＳＳおよび高電源電圧線ＥＬＶＤＤについては、ソース電極１０およびドレイン電極１１と併せて形成されており、第２層間絶縁膜９ｂの上に設けられている。つまり、低電源電圧線ＥＬＶＳＳおよび高電源電圧線ＥＬＶＤＤは、ソース電極１０およびドレイン電極１１の基となる電極用導電膜から形成されており、低電源電圧線ＥＬＶＳＳおよび高電源電圧線ＥＬＶＤＤも含んだ形状となるように、パターニングしている。 The low power supply voltage line ELVSS and the high power supply voltage line EL VDD are formed together with the source electrode 10 and the drain electrode 11 and are provided on the second interlayer insulating film 9b. That is, the low power supply voltage line ELVSS and the high power supply voltage line EL VDD are formed of the electrode conductive film which is the base of the source electrode 10 and the drain electrode 11, and also include the low power supply voltage line ELVSS and the high power supply voltage line EL VDD. It is patterned so that it has a shape.
　低電圧用トランジスタ１ａにおいて、ソース電極１０から第１引き回し配線１０４ａおよび第２引き回し配線１０４ｂまで、ソース延伸部２１が延伸し、第１引き回し配線１０４ａおよび第２引き回し配線１０４ｂと電気的に接続している。また、ドレイン電極１１から低電源電圧線ＥＬＶＳＳまで、ドレイン延伸部２２が延伸し、低電源電圧線ＥＬＶＳＳと電気的に接続している。さらに、低電源電圧線ＥＬＶＳＳから上部ゲート電極８まで、ゲート延伸部２３が延伸し、上部ゲート電極８と電気的に接続している。 In the low-voltage transistor 1a, the source extending portion 21 extends from the source electrode 10 to the first routing wiring 104a and the second routing wiring 104b, and is electrically connected to the first routing wiring 104a and the second routing wiring 104b. There is. Further, the drain extending portion 22 extends from the drain electrode 11 to the low power supply voltage line ELVSS and is electrically connected to the low power supply voltage line ELVSS. Further, the gate extending portion 23 extends from the low power supply voltage line ELVSS to the upper gate electrode 8 and is electrically connected to the upper gate electrode 8.
　高電圧用トランジスタ１ｂにおいて、ソース電極１０から高電源電圧線ＥＬＶＤＤまで、ソース延伸部２１が延伸し、高電源電圧線ＥＬＶＤＤと電気的に接続している。また、ドレイン電極１１から第１引き回し配線１０４ａおよび第２引き回し配線１０４ｂまで、ドレイン延伸部２２が延伸し、第１引き回し配線１０４ａおよび第２引き回し配線１０４ｂと電気的に接続している。さらに、第１引き回し配線１０４ａおよび第２引き回し配線１０４ｂから上部ゲート電極８まで、ゲート延伸部２３が延伸し、第１引き回し配線１０４ａおよび第２引き回し配線１０４ｂと電気的に接続している。 In the high voltage transistor 1b, the source extending portion 21 extends from the source electrode 10 to the high power supply voltage line EL VDD and is electrically connected to the high power supply voltage line EL VDD. Further, the drain extension portion 22 extends from the drain electrode 11 to the first routing wiring 104a and the second routing wiring 104b, and is electrically connected to the first routing wiring 104a and the second routing wiring 104b. Further, the gate extending portion 23 extends from the first routing wiring 104a and the second routing wiring 104b to the upper gate electrode 8 and is electrically connected to the first routing wiring 104a and the second routing wiring 104b.
　ソース延伸部２１、ドレイン延伸部２２、およびゲート延伸部２３は、上述した電極用導電膜から形成されており、ソース電極１０およびドレイン電極１１と併せて形成される。異なる層の配線と接続する場合は、互いが重複する部分に、適宜コンタクトホールを形成すればよい。 The source stretching portion 21, the drain stretching portion 22, and the gate stretching portion 23 are formed from the above-mentioned electrode conductive film, and are formed together with the source electrode 10 and the drain electrode 11. When connecting to wirings of different layers, contact holes may be appropriately formed in the overlapping portions.
　第１低電圧用トランジスタ１ａａにおいては、ソース延伸部２１が、引き回しコンタクトホールＨｅを介して第１引き回し配線１０４ａと接続されている。第２低電圧用トランジスタ１ａｂにおいては、ソース延伸部２１が、引き回しコンタクトホールＨｆを介して第２引き回し配線１０４ｂと接続されている。また、第１低電圧用トランジスタ１ａａおよび第２低電圧用トランジスタ１ａｂにおけるゲート延伸部２３では、上部ゲート電極８上の第１層間絶縁膜９ａおよび第２層間絶縁膜９ｂを貫通するように形成されたコンタクトホールＨｃを介して、対応する上部ゲート電極８と接続されている。 In the first low voltage transistor 1aa, the source extending portion 21 is connected to the first routing wiring 104a via the routing contact hole He. In the second low-voltage transistor 1ab, the source extending portion 21 is connected to the second routing wiring 104b via the routing contact hole Hf. Further, the gate extending portion 23 of the first low-voltage transistor 1aa and the second low-voltage transistor 1ab is formed so as to penetrate the first interlayer insulating film 9a and the second interlayer insulating film 9b on the upper gate electrode 8. It is connected to the corresponding upper gate electrode 8 via the contact hole Hc.
　第１高電圧用トランジスタ１ｂａにおいては、ドレイン延伸部２２が、引き回しコンタクトホールＨｇを介して第１引き回し配線１０４ａと接続されている。第２高電圧用トランジスタ１ｂｂにおいては、ドレイン延伸部２２が、引き回しコンタクトホールＨｈを介して第２引き回し配線１０４ｂと接続されている。また、第１高電圧用トランジスタ１ｂａおよび第２高電圧用トランジスタ１ｂｂにおけるゲート延伸部２３では、引き回しコンタクトホールＨｄを介して第２引き回し配線１０４ｂと接続されている。なお、ゲート延伸部２３と上部ゲート電極８との接続については、第１低電圧用トランジスタ１ａａおよび第２低電圧用トランジスタ１ａｂと同様に、コンタクトホールＨｃを設ければよい。 In the first high voltage transistor 1ba, the drain extension portion 22 is connected to the first routing wiring 104a via the routing contact hole Hg. In the second high voltage transistor 1bb, the drain extension portion 22 is connected to the second routing wiring 104b via the routing contact hole Hh. Further, the gate extension portion 23 in the first high voltage transistor 1ba and the second high voltage transistor 1bb is connected to the second routing wiring 104b via the routing contact hole Hd. Regarding the connection between the gate extending portion 23 and the upper gate electrode 8, the contact hole Hc may be provided in the same manner as in the first low voltage transistor 1aa and the second low voltage transistor 1ab.
　なお、酸化物半導体層６に対し、ソース電極１０およびドレイン電極１１が重複する範囲は特に限定されず、各種配線から対応するコンタクトホールまで繋がるように、ソース電極１０およびドレイン電極１１が設けられていればよい。 The range in which the source electrode 10 and the drain electrode 11 overlap with the oxide semiconductor layer 6 is not particularly limited, and the source electrode 10 and the drain electrode 11 are provided so as to connect various wirings to the corresponding contact holes. Just do it.
　図８では、フィルタ回路１０５のうち、４つの第１トランジスタ１を抜き出して示しているが、これに限定されず、引き回し配線１０４の数に応じて、適宜第１トランジスタ１を増減すればよい。また、引き回し配線１０４については、第１引き回し配線１０４ａと第２引き回し配線１０４ｂとを交互に並べてもよいし、いずれか一方を連続して配置してもよい。 In FIG. 8, four first transistors 1 of the filter circuit 105 are extracted and shown, but the present invention is not limited to this, and the first transistor 1 may be increased or decreased as appropriate according to the number of routing wires 104. Further, regarding the routing wiring 104, the first routing wiring 104a and the second routing wiring 104b may be arranged alternately, or one of them may be arranged continuously.
　本実施の形態に係る第１トランジスタ１では、上部ゲート電極８、ソース電極１０、ドレイン電極１１、および引き回し配線１０４などの各種配線について、各種絶縁膜を間に挟んで積層し、コンタクトホールで適宜接続しているが、上述した構成は一例にすぎず、適宜積層する順番を入れ替えてもよい。例えば、上述した構成では、ソース電極１０、ソース延伸部２１、低電源電圧線ＥＬＶＳＳ、および高電源電圧線ＥＬＶＤＤなどが、同じ層（レイアー）に設けられ、同じ電極用導電膜を用いて一度に形成されていたが、異なる層に設けて、別々に成膜してもよい。 In the first transistor 1 according to the present embodiment, various wirings such as the upper gate electrode 8, the source electrode 10, the drain electrode 11, and the routing wiring 104 are laminated with various insulating films sandwiched between them, and are appropriately laminated in a contact hole. Although they are connected, the above configuration is only an example, and the stacking order may be changed as appropriate. For example, in the above-described configuration, the source electrode 10, the source stretching portion 21, the low power supply voltage line ELVSS, the high power supply voltage line EL VDD, and the like are provided on the same layer (layer), and the same electrode conductive film is used at once. Although it was formed, it may be provided in different layers and formed separately.
　（第５実施形態）
　次に、本発明の第５実施形態に係る表示装置について、図面を参照して説明する。なお、第５実施形態において、第１実施形態ないし第４実施形態と機能が実質的に等しい構成要素については、同一の符号を付して説明を省略する。 (Fifth Embodiment)
Next, the display device according to the fifth embodiment of the present invention will be described with reference to the drawings. In the fifth embodiment, the components having substantially the same functions as those of the first to fourth embodiments are designated by the same reference numerals and the description thereof will be omitted.
　図１０は、本発明の第５実施形態に係る表示装置における第１トランジスタを模式的に示す模式断面図であって、図１１は、図１０に示す第１トランジスタを模式的に示す模式平面図である。なお、図面の見易さを考慮して、図１０では、ハッチングを省略しており、図１１では、下地層５や層間絶縁膜９等を透視的に示している。また、図１０は、図１１の矢符Ｅ－Ｅでの断面に相当する。 FIG. 10 is a schematic cross-sectional view schematically showing a first transistor in the display device according to the fifth embodiment of the present invention, and FIG. 11 is a schematic plan view schematically showing the first transistor shown in FIG. Is. In consideration of the legibility of the drawings, hatching is omitted in FIG. 10, and the base layer 5 and the interlayer insulating film 9 and the like are transparently shown in FIG. Further, FIG. 10 corresponds to the cross section of the arrow EE in FIG.
　第５実施形態は、第１実施形態に対し、上部ゲート電極８のなかでの金属酸化物層８ａの位置が異なる。具体的に、第１実施形態において、金属酸化物層８ａは、上部ゲート電極８のなかで、チャネル長方向Ｌでの略中央に配置されていた。これに対し、第５実施形態において、金属酸化物層８ａは、上部ゲート電極８のなかで、ソース領域６ｂ側に偏って配置されている。つまり、チャネル長方向Ｌにおいて、第２活性領域６ｅの長さ（第２活性領域長ＫＬ２）は、第１活性領域６ｄの長さ（第１活性領域長ＫＬ１）よりも長くなっている。上部ゲート電極８のなかでの金属酸化物層８ａの位置をずらすことで、上部ゲート電極８自体の長さを変えることなく、第１活性領域長ＫＬ１および第２活性領域長ＫＬ２を適宜調整することができる。このように、電荷が集中する側の領域を広くして、耐圧の向上を図りつつ、上部ゲート電極８のサイズを小さく収めることで、トランジスタの小型化に有利に働く。 In the fifth embodiment, the position of the metal oxide layer 8a in the upper gate electrode 8 is different from that in the first embodiment. Specifically, in the first embodiment, the metal oxide layer 8a is arranged substantially in the center in the channel length direction L in the upper gate electrode 8. On the other hand, in the fifth embodiment, the metal oxide layer 8a is unevenly arranged on the source region 6b side in the upper gate electrode 8. That is, in the channel length direction L, the length of the second active region 6e (second active region length KL2) is longer than the length of the first active region 6d (first active region length KL1). By shifting the position of the metal oxide layer 8a in the upper gate electrode 8, the first active region length KL1 and the second active region length KL2 are appropriately adjusted without changing the length of the upper gate electrode 8 itself. be able to. As described above, by widening the region on the side where the electric charge is concentrated to improve the withstand voltage and keeping the size of the upper gate electrode 8 small, it is advantageous for the miniaturization of the transistor.
　本実施の形態における第１トランジスタ１を、上述したフィルタ回路１０５に用いてもよく、低電圧用トランジスタ１ａおよび高電圧用トランジスタ１ｂとして適用するものに応じて、上部ゲート電極８、ソース電極１０、およびドレイン電極１１が各種配線と適宜接続されていればよい。 The first transistor 1 in the present embodiment may be used in the filter circuit 105 described above, and the upper gate electrode 8, the source electrode 10, and the source electrode 10 may be used depending on what is applied as the low voltage transistor 1a and the high voltage transistor 1b. And the drain electrode 11 may be appropriately connected to various wirings.
　図１２は、表示装置の画素回路を示す等価回路図である。 FIG. 12 is an equivalent circuit diagram showing a pixel circuit of the display device.
　表示装置１００は、マトリクス状に配列された複数の画素によって構成された表示領域１０１を有する。複数の画素は、典型的には、赤を表示する赤画素、緑を表示する緑画素、および青を表示する青画素を含む。それぞれの画素では、対応する発光ダイオードＬＤが設けられており、対応する画素回路によって制御している。 The display device 100 has a display area 101 composed of a plurality of pixels arranged in a matrix. The plurality of pixels typically include a red pixel that displays red, a green pixel that displays green, and a blue pixel that displays blue. A corresponding light emitting diode LD is provided in each pixel, and is controlled by a corresponding pixel circuit.
　「Ｓ（ｍ）」に対応する直線は、ソース信号線を示し、「Ｇ（ｎ）」および「Ｇ（ｎ－１）」に対応する直線は、ゲート信号線を示し、「ＥＭ（ｎ）」に対応する直線は、発光制御線を示している。また、「ＥＬＶＤＤ」は、高電源電圧を示し、これに繋がる直線は、高電源電圧線に相当する。さらに、「ＥＬＶＳＳ」は、低電源電圧を示し、これに繋がる直線は、低電源電圧線に相当する。そして、「Ｖｉｎｉ（ｎ）」に対応する直線は、リセット電位に対応するリセット信号線を示している。 The straight line corresponding to "S (m)" indicates the source signal line, and the straight lines corresponding to "G (n)" and "G (n-1)" indicate the gate signal line, and "EM (n)" The straight line corresponding to "" indicates a light emission control line. Further, "EL VDD" indicates a high power supply voltage, and a straight line connected to the high power supply voltage corresponds to a high power supply voltage line. Further, "ELVSS" indicates a low power supply voltage, and a straight line connected to the low power supply voltage corresponds to a low power supply voltage line. The straight line corresponding to "Vini (n)" indicates the reset signal line corresponding to the reset potential.
　図８は、画素回路の一例を示しており、７つのトランジスタ（第１回路トランジスタＴ１ないし第７回路トランジスタＴ７）、コンデンサＣａ、および発光ダイオードＬＤを組み合わせて構成されている。上述した第１トランジスタ１は、第１回路トランジスタＴ１ないし第７回路トランジスタＴ７のいずれに適用してもよいが、それぞれの特性に応じた箇所に配置されることが望ましく、画素回路におけるスイッチングトランジスタに適用されることが好ましい。 FIG. 8 shows an example of a pixel circuit, which is configured by combining seven transistors (first circuit transistor T1 to seventh circuit transistor T7), a capacitor Ca, and a light emitting diode LD. The first transistor 1 described above may be applied to any of the first circuit transistor T1 to the seventh circuit transistor T7, but it is desirable that the first transistor 1 be arranged at a location corresponding to each characteristic, and the first transistor 1 may be used as a switching transistor in a pixel circuit. It is preferably applied.
　画素回路において、第１回路トランジスタＴ１ないし第３回路トランジスタＴ３と、第５回路トランジスタＴ５ないし第７回路トランジスタＴ７とは、スイッチングトランジスタとして用いられている。また、第４回路トランジスタＴ４は、発光ダイオードＬＤに電源を供給する駆動トランジスタとされている。上述した第２トランジスタ２は、画素回路における駆動トランジスタに適用されることが好ましい。 In the pixel circuit, the first circuit transistor T1 to the third circuit transistor T3 and the fifth circuit transistor T5 to the seventh circuit transistor T7 are used as switching transistors. Further, the fourth circuit transistor T4 is a drive transistor that supplies power to the light emitting diode LD. The second transistor 2 described above is preferably applied to a drive transistor in a pixel circuit.
　本実施の形態に係る表示装置１００は、表示素子を備えた表示パネルであれば、特に限定されるものではない。表示素子は、電流によって輝度や透過率が制御される表示素子と、電圧によって輝度や透過率が制御される表示素子とがある。電流制御の表示素子としては、例えば、ＯＬＥＤ（Ｏｒｇａｎｉｃ　Ｌｉｇｈｔ　Ｅｍｉｔｔｉｎｇ　Ｄｉｏｄｅ：有機発光ダイオード）を備えた有機ＥＬ（Ｅｌｅｃｔｒｏ　Ｌｕｍｉｎｅｓｃｅｎｃｅ：エレクトロルミネッセンス）ディスプレイ、無機発光ダイオードを備えた無機ＥＬディスプレイ等のＥＬディスプレイ、およびＱＬＥＤ（Ｑｕａｎｔｕｍ　ｄｏｔ　Ｌｉｇｈｔ　Ｅｍｉｔｔｉｎｇ　Ｄｉｏｄｅ：量子ドット発光ダイオード）を備えたＱＬＥＤディスプレイ等がある。また、電圧制御の表示素子としては、液晶表示素子等がある。 The display device 100 according to the present embodiment is not particularly limited as long as it is a display panel provided with a display element. The display element includes a display element whose brightness and transmittance are controlled by an electric current and a display element whose brightness and transmittance are controlled by a voltage. Examples of the current control display element include an EL display such as an organic EL (Electro Luminescence) display equipped with an OLED (Organic Light Emitting Diode), an inorganic EL display provided with an inorganic light emitting diode, and an EL display. There are QLED displays and the like equipped with QLEDs (Quantum dot Light Emitting Diode: Quantum Dot Light Emitting Diodes). Further, as the voltage control display element, there is a liquid crystal display element or the like.
　なお、今回開示した実施の形態は全ての点で例示であって、限定的な解釈の根拠となるものではない。従って、本発明の技術的範囲は、上記した実施の形態のみによって解釈されるものではなく、特許請求の範囲の記載に基づいて画定される。また、特許請求の範囲と均等の意味および範囲内での全ての変更が含まれる。 It should be noted that the embodiment disclosed this time is an example in all respects and does not serve as a basis for a limited interpretation. Therefore, the technical scope of the present invention is not construed solely by the above-described embodiment, but is defined based on the description of the scope of claims. It also includes all changes within the meaning and scope of the claims.
　１　第１トランジスタ
　２　第２トランジスタ
　３　基板
　４　下部ゲート電極
　５　下地層
　６　酸化物半導体層
　６ａ　チャネル領域
　６ｂ　ソース領域
　６ｃ　ドレイン領域
　６ｄ　第１活性領域
　６ｅ　第２活性領域
　７　上部ゲート絶縁膜
　８　上部ゲート電極
　８ａ　金属酸化物層
　８ｂ　金属層
　９　層間絶縁膜
　９ａ　第１層間絶縁膜
　９ｂ　第２層間絶縁膜
　１０　ソース電極
　１１　ドレイン電極
　１００　表示装置
　１０１　表示領域
　１０２　額縁領域
　１０３　端子部
　１０４　引き回し配線
　１０５　フィルタ回路
　ＥＬＶＤＤ　高電源電圧線
　ＥＬＶＳＳ　低電源電圧線
　Ｌ　チャネル長方向
  1 1st transistor 2 2nd transistor 3 Substrate 4 Lower gate electrode 5 Underlayer 6 Oxide semiconductor layer 6a Channel region 6b Source region 6c Drain region 6d 1st active region 6e 2nd active region 7 Upper gate insulating film 8 Upper gate electrode 8a metal oxide layer 8b metal layer 9 interlayer insulating film 9a first interlayer insulating film 9b second interlayer insulating film 10 source electrode 11 drain electrode 100 display device 101 display area 102 frame area 103 terminal part 104 routing wiring 105 filter circuit EL VDD high Power supply voltage line ELVSS low power supply voltage line L channel length direction

Claims (22)

  1. 　基板上に、酸化物半導体層、上部ゲート絶縁膜、上部ゲート電極、および層間絶縁膜を積層して形成された第１トランジスタを有する表示装置であって、
    　前記第１トランジスタの前記上部ゲート電極は、前記基板側から順に積層された金属酸化物層と、前記金属酸化物層の側面および上面を覆う金属層とを有し、
    　前記第１トランジスタの前記酸化物半導体層は、
    　前記上部ゲート絶縁膜を介して、前記金属酸化物層と対向するチャネル領域と、
    　前記チャネル領域を互いの間に挟むように設けられたソース領域およびドレイン領域と、
    　前記チャネル領域と前記ソース領域との間に設けられ、前記上部ゲート絶縁膜を介して、前記金属層と対向する第１活性領域と、
    　前記チャネル領域と前記ドレイン領域との間に設けられ、前記上部ゲート絶縁膜を介して、前記金属層と対向する第２活性領域とを含むこと
    　を特徴とする表示装置。     A display device having a first transistor formed by laminating an oxide semiconductor layer, an upper gate insulating film, an upper gate electrode, and an interlayer insulating film on a substrate.
    The upper gate electrode of the first transistor has a metal oxide layer laminated in order from the substrate side, and a metal layer covering the side surface and the upper surface of the metal oxide layer.
    The oxide semiconductor layer of the first transistor is
    A channel region facing the metal oxide layer and a channel region facing the metal oxide layer via the upper gate insulating film.
    A source region and a drain region provided so as to sandwich the channel region between them,
    A first active region provided between the channel region and the source region and facing the metal layer via the upper gate insulating film,
    A display device provided between the channel region and the drain region, and including a second active region facing the metal layer via the upper gate insulating film.
  2. 　請求項１に記載の表示装置であって、
    　前記金属酸化物層は、Ｉｎを含有していること
    　を特徴とする表示装置。     The display device according to claim 1.
    A display device characterized in that the metal oxide layer contains In.
  3. 　請求項２に記載の表示装置であって、
    　前記金属酸化物層は、ＧａおよびＺｎを含有していること
    　を特徴とする表示装置。     The display device according to claim 2.
    A display device characterized in that the metal oxide layer contains Ga and Zn.
  4. 　請求項２に記載の表示装置であって、
    　前記金属酸化物層は、ＳｎおよびＺｎを含有していること
    　を特徴とする表示装置。     The display device according to claim 2.
    A display device characterized in that the metal oxide layer contains Sn and Zn.
  5. 　請求項１から請求項４までのいずれか１つに記載の表示装置であって、
    　前記第１活性領域および前記第２活性領域は、前記チャネル領域よりも抵抗率が低く、前記ソース領域および前記ドレイン領域よりも抵抗率が高いこと
    　を特徴とする表示装置。     The display device according to any one of claims 1 to 4.
    A display device characterized in that the first active region and the second active region have a lower resistivity than the channel region and a higher resistivity than the source region and the drain region.
  6. 　請求項１から請求項５までのいずれか１つに記載の表示装置であって、
    　前記第１トランジスタの前記チャネル領域は、前記金属酸化物層と整合し、
    　前記第１活性領域の前記ソース領域側の端部は、前記金属層の前記ソース領域側の端部と整合し、
    　前記第２活性領域の前記ドレイン領域側の端部は、前記金属層の前記ドレイン領域側の端部と整合すること
    　を特徴とする表示装置。     The display device according to any one of claims 1 to 5.
    The channel region of the first transistor is aligned with the metal oxide layer and
    The end of the first active region on the source region side is aligned with the end of the metal layer on the source region side.
    A display device characterized in that the end portion of the second active region on the drain region side is aligned with the end portion of the metal layer on the drain region side.
  7. 　請求項１から請求項６までのいずれか１つに記載の表示装置であって、
    　前記上部ゲート電極は、前記上部ゲート絶縁膜と整合すること
    　を特徴とする表示装置。     The display device according to any one of claims 1 to 6.
    A display device characterized in that the upper gate electrode is aligned with the upper gate insulating film.
  8. 　請求項１から請求項７までのいずれか１つに記載の表示装置であって、
    　前記上部ゲート絶縁膜は、酸化シリコン膜であること
    　を特徴とする表示装置。     The display device according to any one of claims 1 to 7.
    A display device characterized in that the upper gate insulating film is a silicon oxide film.
  9. 　請求項８に記載の表示装置であって、
    　前記層間絶縁膜は、前記酸化物半導体層および前記上部ゲート電極と接する部分が、窒化シリコン膜で形成されていること
    　を特徴とする表示装置。     The display device according to claim 8.
    The interlayer insulating film is a display device characterized in that a portion in contact with the oxide semiconductor layer and the upper gate electrode is formed of a silicon nitride film.
  10. 　請求項８に記載の表示装置であって、
    　前記層間絶縁膜は、前記酸化物半導体層および前記上部ゲート電極と接する部分が、酸化シリコン膜で形成されていること
    　を特徴とする表示装置。     The display device according to claim 8.
    The interlayer insulating film is a display device characterized in that a portion in contact with the oxide semiconductor layer and the upper gate electrode is formed of a silicon oxide film.
  11. 　請求項１から請求項１０までのいずれか１つに記載の表示装置であって、
    　前記基板と前記酸化物半導体層の間には、下部ゲート電極と下部ゲート絶縁膜とが設けられ、
    　前記下部ゲート電極は、前記下部ゲート絶縁膜を介して、前記チャネル領域と重畳すること
    　を特徴とする表示装置。     The display device according to any one of claims 1 to 10.
    A lower gate electrode and a lower gate insulating film are provided between the substrate and the oxide semiconductor layer.
    A display device characterized in that the lower gate electrode is superimposed on the channel region via the lower gate insulating film.
  12. 　請求項１１に記載の表示装置であって、
    　前記下部ゲート電極は、前記ソース領域側の端部が、前記ソース領域と重畳し、前記ドレイン領域側の端部が、前記ドレイン領域と重畳すること
    　を特徴とする表示装置。     The display device according to claim 11.
    The lower gate electrode is a display device characterized in that an end portion on the source region side overlaps with the source region and an end portion on the drain region side overlaps with the drain region.
  13. 　請求項１１に記載の表示装置であって、
    　前記下部ゲート電極は、前記ソース領域側の端部が、前記第１活性領域と重畳し、前記ドレイン領域側の端部が、前記第２活性領域と重畳すること
    　を特徴とする表示装置。     The display device according to claim 11.
    The lower gate electrode is a display device characterized in that an end portion on the source region side is superimposed on the first active region and an end portion on the drain region side is superimposed on the second active region.
  14. 　請求項１から請求項１３までのいずれか１つに記載の表示装置であって、
    　額縁領域にモノリシックに設けられた周辺回路を備え、
    　前記第１トランジスタは、前記周辺回路に含まれるスイッチングトランジスタであること
    　を特徴とする表示装置。     The display device according to any one of claims 1 to 13.
    Equipped with a monolithic peripheral circuit in the frame area
    The display device, wherein the first transistor is a switching transistor included in the peripheral circuit.
  15. 　請求項１から請求項１４までのいずれか１つに記載の表示装置であって、
    　前記基板上には、酸化物半導体層、上部ゲート絶縁膜、上部ゲート電極、および層間絶縁膜を積層して形成された第２トランジスタが設けられ、
    　前記第２トランジスタの前記上部ゲート電極は、前記基板側から順に積層された金属酸化物層と、金属層とを有し、
    　前記第２トランジスタの前記酸化物半導体層は、
    　前記上部ゲート絶縁膜を介して、前記上部ゲート電極と対向するチャネル領域と、
    　前記チャネル領域を互いの間に挟むように設けられたソース領域およびドレイン領域とを含むこと
    　を特徴とする表示装置。     The display device according to any one of claims 1 to 14.
    A second transistor formed by laminating an oxide semiconductor layer, an upper gate insulating film, an upper gate electrode, and an interlayer insulating film is provided on the substrate.
    The upper gate electrode of the second transistor has a metal oxide layer and a metal layer laminated in order from the substrate side.
    The oxide semiconductor layer of the second transistor is
    A channel region facing the upper gate electrode via the upper gate insulating film,
    A display device including a source region and a drain region provided so as to sandwich the channel region between them.
  16. 　請求項１５に記載の表示装置であって、
    　表示領域にマトリクス状に設けられた画素回路を備え、
    　前記画素回路は、前記第１トランジスタと、前記第２トランジスタと、容量とを含み、
    　前記第１トランジスタは、閾値制御トランジスタであり、
    　前記第２トランジスタは、駆動トランジスタであり、
    　前記駆動トランジスタは、制御端子が、前記容量の一方の電極と電気的に接続され、
    　前記閾値制御トランジスタは、一方の導通端子が、前記駆動トランジスタの一方の導通端子と電気的に接続され、他方の導通端子が、自身の制御端子と電気的に接続されること
    　を特徴とする表示装置。     The display device according to claim 15.
    Equipped with a pixel circuit provided in a matrix in the display area,
    The pixel circuit includes the first transistor, the second transistor, and a capacitance.
    The first transistor is a threshold control transistor and
    The second transistor is a drive transistor and
    In the drive transistor, the control terminal is electrically connected to one electrode of the capacitance.
    The threshold control transistor is characterized in that one conductive terminal is electrically connected to one conductive terminal of the drive transistor and the other conductive terminal is electrically connected to its own control terminal. apparatus.
  17. 　請求項１から請求項１３までのいずれか１つに記載の表示装置であって、
    　額縁領域に設けられた端子部と、
    　前記端子部から延伸された引き回し配線と、
    　前記端子部と表示領域との間に設けられたフィルタ回路とを備え、
    　前記端子部は、前記フィルタ回路を介して、前記表示領域の配線と電気的に接続され、
    　前記第１トランジスタは、前記フィルタ回路に含まれること
    　を特徴とする表示装置。     The display device according to any one of claims 1 to 13.
    The terminal part provided in the frame area and
    The routing wiring extended from the terminal portion and
    A filter circuit provided between the terminal portion and the display area is provided.
    The terminal portion is electrically connected to the wiring in the display area via the filter circuit.
    The display device, wherein the first transistor is included in the filter circuit.
  18. 　請求項１７に記載の表示装置であって、
    　前記ソース領域は、高電源電圧線と電気的に接続され、
    　前記ドレイン領域および前記上部ゲート電極は、前記引き回し配線と電気的に接続されること
    　を特徴とする表示装置。     The display device according to claim 17.
    The source area is electrically connected to the high power supply voltage line.
    A display device characterized in that the drain region and the upper gate electrode are electrically connected to the routing wiring.
  19. 　請求項１７に記載の表示装置であって、
    　前記ソース領域は、前記引き回し配線と電気的に接続され、
    　前記ドレイン領域および前記上部ゲート電極は、低電源電圧線と電気的に接続されること
    　を特徴とする表示装置。     The display device according to claim 17.
    The source area is electrically connected to the routing wiring.
    A display device characterized in that the drain region and the upper gate electrode are electrically connected to a low power supply voltage line.
  20. 　請求項１８または請求項１９に記載の表示装置であって、
    　前記引き回し配線は、前記表示領域のデータ信号線と電気的に接続されること
    　を特徴とする表示装置。     The display device according to claim 18 or 19.
    A display device characterized in that the routing wiring is electrically connected to a data signal line in the display area.
  21. 　請求項１８または請求項１９に記載の表示装置であって、
    　前記引き回し配線は、前記表示領域の走査信号線と電気的に接続されること
    　を特徴とする表示装置。     The display device according to claim 18 or 19.
    A display device characterized in that the routing wiring is electrically connected to a scanning signal line in the display area.
  22. 　請求項１７に記載の表示装置であって、
    　前記ソース領域と前記ドレイン領域とが対向するチャネル長方向において、前記第２活性領域の長さは、前記第１活性領域の長さよりも長いこと
    　を特徴とする表示装置。
     
          The display device according to claim 17.
    A display device characterized in that the length of the second active region is longer than the length of the first active region in the channel length direction in which the source region and the drain region face each other.
PCT/JP2019/010911 2019-03-15 2019-03-15 Display device WO2020188643A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2019/010911 WO2020188643A1 (en) 2019-03-15 2019-03-15 Display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2019/010911 WO2020188643A1 (en) 2019-03-15 2019-03-15 Display device

Publications (1)

Publication Number Publication Date
WO2020188643A1 true WO2020188643A1 (en) 2020-09-24

Family

ID=72519235

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2019/010911 WO2020188643A1 (en) 2019-03-15 2019-03-15 Display device

Country Status (1)

Country Link
WO (1) WO2020188643A1 (en)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000216399A (en) * 1998-11-17 2000-08-04 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacture
JP2000223716A (en) * 1998-11-25 2000-08-11 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacture
JP2001210833A (en) * 1999-11-18 2001-08-03 Semiconductor Energy Lab Co Ltd Semiconductor device and method of manufacturing it
JP2007043114A (en) * 2005-06-30 2007-02-15 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacturing method
KR100857455B1 (en) * 2007-04-17 2008-09-08 한국전자통신연구원 Method of fabricating thin film transistor including ald deposited protection layer on the oxide semiconductor
JP2013105852A (en) * 2011-11-11 2013-05-30 Semiconductor Energy Lab Co Ltd Semiconductor device and semiconductor device manufacturing method
JP2016027649A (en) * 2014-07-03 2016-02-18 株式会社半導体エネルギー研究所 Semiconductor device and display device having semiconductor device
JP2017037301A (en) * 2015-08-07 2017-02-16 株式会社半導体エネルギー研究所 Display panel and method for manufacturing display panel
JP2018159910A (en) * 2016-12-27 2018-10-11 株式会社半導体エネルギー研究所 Display panel, display device, input/output device, and information processing device

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000216399A (en) * 1998-11-17 2000-08-04 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacture
JP2000223716A (en) * 1998-11-25 2000-08-11 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacture
JP2001210833A (en) * 1999-11-18 2001-08-03 Semiconductor Energy Lab Co Ltd Semiconductor device and method of manufacturing it
JP2007043114A (en) * 2005-06-30 2007-02-15 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacturing method
KR100857455B1 (en) * 2007-04-17 2008-09-08 한국전자통신연구원 Method of fabricating thin film transistor including ald deposited protection layer on the oxide semiconductor
JP2013105852A (en) * 2011-11-11 2013-05-30 Semiconductor Energy Lab Co Ltd Semiconductor device and semiconductor device manufacturing method
JP2016027649A (en) * 2014-07-03 2016-02-18 株式会社半導体エネルギー研究所 Semiconductor device and display device having semiconductor device
JP2017037301A (en) * 2015-08-07 2017-02-16 株式会社半導体エネルギー研究所 Display panel and method for manufacturing display panel
JP2018159910A (en) * 2016-12-27 2018-10-11 株式会社半導体エネルギー研究所 Display panel, display device, input/output device, and information processing device

Similar Documents

Publication Publication Date Title
JP6916256B2 (en) Display device
KR102543577B1 (en) Transistor array panel, manufacturing method thereof, and disalay device comprising the same
USRE48032E1 (en) Thin-film semiconductor substrate, light-emitting panel, and method of manufacturing the thin-film semiconductor substrate
US9659967B2 (en) Thin-film transistor and display device having the same
JP6019507B2 (en) THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR PRODUCING THIN FILM TRANSISTOR SUBSTRATE
KR20140104263A (en) Organic light emitting display device and method of manufacturing thereof
TW201304149A (en) Active matrix substrate, display device and method for manufacturing active matrix substrate
TW201344920A (en) Semiconductor device, display, and method of manufacturing semiconductor device
US11569324B2 (en) Active matrix substrate and method for manufacturing same
US10879329B2 (en) Semiconductor device, semiconductor substrate, luminescent unit, and display unit
WO2020059027A1 (en) Display device
WO2020213102A1 (en) Display device
US11695016B2 (en) Active matrix substrate and method for manufacturing same
WO2020188643A1 (en) Display device
WO2013191044A1 (en) Semiconductor device and method for producing same
WO2020208704A1 (en) Display device and manufacturing method
JP6311900B2 (en) Method for manufacturing thin film transistor substrate
WO2019187070A1 (en) Transistor and display device
JP2021013021A (en) Display device
WO2020161775A1 (en) Display device
US20230075289A1 (en) Active matrix substrate and method for manufacturing same
KR20150009848A (en) Organic light emitting diode display and method for manufacturing the same
US11437520B2 (en) Transistor and display device
KR20210004794A (en) Display apparatus
KR20220073547A (en) Display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19919640

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19919640

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP