WO2020186700A1 - 肖特基二极管及其制备方法 - Google Patents

肖特基二极管及其制备方法 Download PDF

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WO2020186700A1
WO2020186700A1 PCT/CN2019/103911 CN2019103911W WO2020186700A1 WO 2020186700 A1 WO2020186700 A1 WO 2020186700A1 CN 2019103911 W CN2019103911 W CN 2019103911W WO 2020186700 A1 WO2020186700 A1 WO 2020186700A1
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gallium oxide
type material
electrode
epitaxial layer
substrate
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PCT/CN2019/103911
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English (en)
French (fr)
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于洪宇
曾凡明
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南方科技大学
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes

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  • the embodiments of the present application relate to semiconductor technology, for example, to a Schottky diode and a manufacturing method thereof.
  • Gallium oxide is a wide band gap semiconductor material.
  • the band gap of ⁇ -Ga 2 O 3 is about 4.85 eV.
  • Its critical breakdown electric field is as high as 8 MV/cm. It also has controllable n-type doping, radiation resistance, and high melting point. Suitable for making high-voltage power electronic devices. Its applications include power electronic devices, radio frequency electronic devices, ultraviolet detectors, gas sensors, etc., and have broad application prospects in solid-state lighting, communications, consumer electronics, as well as new energy vehicles, smart grids and other fields.
  • Gallium oxide has better high voltage resistance characteristics than third-generation semiconductor materials such as silicon carbide.
  • BFOM Baliga's figure merit
  • gallium oxide materials Due to the deep acceptor energy level of gallium oxide and the hole self-binding effect, it is difficult for traditional p-type acceptor elements to be doped into gallium oxide to form a p-type material, and the related technology uses gallium oxide material to achieve PN The knot is usually accompanied by high technical difficulty and high cost. This largely limits the use of gallium oxide materials to make Schottky diodes, that is, it is impossible to use gallium oxide materials to make high-performance Schottky diodes.
  • the application provides a Schottky diode and a preparation method thereof, so as to realize a high-performance Schottky diode using gallium oxide material.
  • an embodiment of the present application provides a Schottky diode
  • the Schottky diode includes: a gallium oxide substrate; a gallium oxide epitaxial layer on the gallium oxide substrate, wherein the gallium oxide The side of the epitaxial layer away from the gallium oxide substrate is provided with multiple trenches; multiple p-type material structures located in the multiple trenches; covering the p-type material structure and the gallium oxide epitaxial layer First electrode; a second electrode located on the side of the gallium oxide substrate away from the gallium oxide epitaxial layer.
  • the thickness of the p-type material structure ranges from 20 nanometers to 500 nanometers.
  • the grooves are periodically arranged, and the grooves are strip-shaped grooves or annular grooves.
  • the gallium oxide substrate is an ⁇ -Ga 2 O 3 substrate, a ⁇ -Ga 2 O 3 substrate, a ⁇ -Ga 2 O 3 substrate, a ⁇ -Ga 2 O 3 substrate, or ⁇ -Ga 2 O 3 substrate.
  • both the first electrode and the second electrode include at least one of Ni, Ti, Al, Au, TiN, W, Pt, Pd, Mo, and ITO.
  • the first electrode includes a field plate structure.
  • an embodiment of the present application also provides a method for manufacturing a Schottky diode.
  • the method includes: providing a gallium oxide substrate including an epitaxial layer; forming a plurality of trenches on the gallium oxide epitaxial layer; A plurality of p-type material structures are formed in the plurality of trenches; a first electrode is formed on the gallium oxide epitaxial layer and the p-type material structure; on the side of the gallium oxide substrate away from the gallium oxide epitaxial layer The second electrode is formed.
  • forming a plurality of p-type material structures in the plurality of trenches includes: growing a p-type material film on the epitaxial layer of gallium oxide, the p-type material film filling the plurality of trenches Groove; remove the p-type material film outside the plurality of groove structures.
  • forming the first electrode on the epitaxial layer of gallium oxide and the p-type material structure includes: fabricating the first electrode on the epitaxial layer of gallium oxide and the p-type material structure by metal evaporation.
  • Electrode; forming a second electrode on the side of the gallium oxide substrate away from the epitaxial layer of gallium oxide includes: fabricating the second electrode on the side of the gallium oxide substrate away from the epitaxial layer of gallium oxide by metal evaporation The second electrode.
  • FIG. 1 is a schematic structural diagram of a Schottky diode provided by an embodiment of the application
  • FIG. 2 is a flowchart of a method for manufacturing a Schottky diode according to an embodiment of the application
  • 3-6 are schematic diagrams of the structure of the film formed by the manufacturing method of the Schottky diode provided by the embodiment of the application.
  • FIG. 1 is a schematic structural diagram of a Schottky diode provided by an embodiment of the application.
  • the Schottky diode includes a gallium oxide substrate 102; a gallium oxide epitaxial layer 103 on the gallium oxide substrate 102, wherein, The gallium oxide epitaxial layer 103 is provided with multiple trenches on the side away from the gallium oxide substrate 102; the p-type material structure 105 located in the multiple trenches; the first electrode covering the p-type material structure 105 and the gallium oxide epitaxial layer 103 104; the second electrode 101 located on the side of the gallium oxide substrate 102 away from the gallium oxide epitaxial layer 103.
  • the gallium oxide substrate 102 is n-type highly doped (n+) gallium oxide, and the gallium oxide epitaxial layer 103 is n-type lowly doped (n-); the second electrode 101 and the gallium oxide substrate 102 There may be an ohmic contact between the first electrode 104, the gallium oxide epitaxial layer 103 and the plurality of p-type material structures 105, and the p-type material structure 105 may be placed in the trench. Concentrating on the bottom of the trench improves the voltage division capability of the depletion region in other parts and effectively increases the reverse breakdown voltage of the Schottky diode.
  • the majority carriers in the p-type material structure 105 are holes, and the majority carriers in the gallium oxide epitaxial layer 103 are electrons, and the majority carriers (holes) in the p-type material structure 105 are directed to the gallium oxide epitaxial layer.
  • the majority carriers (electrons) in the gallium oxide epitaxial layer 103 move to the p-type material structure 105, and a hetero PN junction structure is formed between the p-type material structure 105 and the gallium oxide epitaxial layer 103; and the first electrode A Schottky junction structure is formed between 104 and the gallium oxide epitaxial layer 103; and because the manufacturing technology of the p-type material structure 105 is relatively low, it only needs to grow on the gallium oxide epitaxial layer 103, that is, the p-type material structure 105 The formation of the structure has lower technical difficulty and cost compared with the use of gallium oxide materials to form p-type semiconductor materials, thereby greatly reducing the difficulty and cost of using gallium oxide materials to form PN junctions; when the Schottky diode is working in the forward direction, When a small operating voltage is applied between the first electrode 104 and the second electrode 101, because the Schottky junction has a small turn-on voltage, the Schottky junction is turned
  • the heterogeneous PN The junction also begins to conduct, and the N-type material begins to inject a large amount of electrons into the drift region, thereby reducing the on-resistance in the drift region. That is, when the Schottky diode is working at a large current, its forward voltage is also lower. At the same time, after the PN junction is turned on, the pressure drop of the PN junction remains unchanged.
  • the technical solution of this embodiment adopts a Schottky diode including a gallium oxide substrate, a gallium oxide epitaxial layer, multiple p-type material structures, a first electrode and a second electrode, and the p-type material structure and the gallium oxide epitaxial layer Heterogeneous PN junction structure is formed between them, thereby avoiding the high technical difficulty and high cost that accompany the production of Schottky diodes due to the difficulty of forming p-type doped materials with gallium oxide materials.
  • the diode has a lower turn-on voltage and a higher reverse breakdown voltage in the case of high voltage and large current, which improves the stability of the Schottky diode.
  • the p-type material structure 105 adopts a p-type In x Al y Ga z N single-layer structure, a p-type In x Al y Ga z N multilayer overlap structure or a p-type silicon carbide; when the p-type material structure When 105 adopts a p-type In x Al y Ga z N single-layer structure or a p-type In x Al y Ga z N multilayer overlap structure, the p-type material structure 105 is doped with magnesium; when the p-type material structure 105 adopts In the case of p-type silicon carbide, the p-type material structure 105 is doped with aluminum.
  • the doped p-type material structure 105 when the p-type material structure 105 adopts a p-type In x Al y Ga z N single-layer structure or a p-type In x Al y Ga z N multilayer structure, the doped p-type material structure 105
  • the element may also be other elements except magnesium; when p-type silicon carbide is used in the p-type material structure 105, the element doped in the p-type material structure 105 may also be other elements other than aluminum.
  • the thickness of the p-type material structure 105 ranges from 20 nanometers to 500 nanometers. If the p-type material structure 105 is too thin, it cannot provide effective holes, and if the p-type material structure 105 is too thick, it will introduce more material defects, increase the body resistance and capacitance, and affect the performance of the Schottky diode. performance. By controlling the thickness of the p-type material structure 105, the thickness of the depletion layer between the p-type material structure 105 and the gallium oxide epitaxial layer 103 can reach a better level, which further improves the performance of the Schottky diode, such as p-type The thickness of the material structure 105 may be 100 nanometers.
  • the gallium oxide substrate 102 uses an ⁇ -Ga 2 O 3 substrate, a ⁇ -Ga 2 O 3 substrate, a ⁇ -Ga 2 O 3 substrate, a ⁇ -Ga 2 O 3 substrate, or ⁇ -Ga 2 O 3 substrate.
  • the ⁇ -Ga 2 O 3 substrate has high conductivity, low cost, and good chemical and thermal stability, and ⁇ -Ga 2 O 3 can be used as the substrate.
  • both the first electrode 101 and the second electrode 104 include at least one of Ni, Ti, Al, Au, TiN, W, Pt, Pd, Mo, and ITO.
  • the first electrode 101 and the second electrode 104 may be a metal or a compound, or may be a laminated structure composed of multiple metals or compounds to improve the conductivity of the first electrode 101 and the second electrode 104 performance.
  • the first electrode 101 may include a field plate structure or a terminal protection structure.
  • a floating p-type guard ring may be used to improve the electric field distribution of the Schottky diode, so as to further improve the Schottky diode.
  • the breakdown voltage of the base diode enhances the stability of the Schottky diode.
  • the grooves are periodically arranged, and the grooves are strip-shaped grooves or annular grooves.
  • the trench can be a bar-gate structure, or a concentric ring structure with equal intervals; by providing a periodic trench structure, the difficulty of manufacturing Schottky diodes can be reduced, and the Schottky diode can be further improved.
  • the electric field distribution of the diode makes the electric field distribution in the Schottky diode more uniform and enhances the performance of the Schottky diode.
  • FIG. 2 is a flow chart of a method for manufacturing a Schottky diode according to an embodiment of the application
  • FIGS. 3-6 are diagrams of a film formed by the method for manufacturing a Schottky diode according to an embodiment of the application. Schematic diagram of the structure; the preparation method of the Schottky diode includes step 201 to step 204.
  • Step 201 forming a plurality of trenches on the epitaxial layer of gallium oxide.
  • a gallium oxide substrate including an epitaxial layer can be used, such as a gallium oxide substrate in the related art; if a substrate including a gallium oxide epitaxial layer is not used, a corresponding layer can be grown on the gallium oxide substrate first. For the epitaxial layer, step 201 is performed again.
  • dry etching or wet etching can be used to prepare multiple trenches; since wet etching is generally used to make larger devices, and dry etching has good anisotropic etching properties, So as to ensure the fidelity of small graphics after transfer.
  • dry etching is used to produce multiple trenches, and the gas used in the dry etching is one or a mixture of SF 6 , CF 4 , BCl 3 , Cl 2 , and Ar 2 .
  • Step 202 forming a plurality of p-type material structures in the plurality of trenches.
  • forming a plurality of p-type material structures 105 in a plurality of trenches includes: growing a p-type material film 301 on the epitaxial layer 103 of gallium oxide, and filling the p-type material film 301 with Multiple grooves.
  • the growth method of the p-type material film 301 may be Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), and Hydride Vapor Phase Epitaxy (HVPE). ) Or Atom Layer Deposition (ALD).
  • MOCVD Chemical Vapor Deposition
  • MBE Molecular Beam Epitaxy
  • HVPE Hydride Vapor Phase Epitaxy
  • ALD Atom Layer Deposition
  • the MOCVD method is used to grow p-type gallium nitride
  • the element doped in the p-type material film 301 can be magnesium, and the reaction source and carrier gas used for the growth of the p-type material film 301 are mainly trimethylgallium ( TMGa), trimethylaluminum (TMA), NH 3 , Cp 2 Mg, H 2 , N 2 and so on.
  • TMGa trimethylgallium
  • TMA trimethylaluminum
  • NH 3 trimethylgallium
  • Cp 2 Mg Cp 2
  • the nitrogen source is a nitrogen radio frequency nitrogen plasma source
  • solid gallium is used as a gallium source
  • solid magnesium is used as a magnesium source
  • the V/III ratio is 1/1
  • the growth chamber pressure is 1.1 ⁇ 10 -4 mbar. It is understandable that the above-mentioned p-type material film 301 uses p-type aluminum indium gallium nitride as an example.
  • the p-type material film 301 uses p-type silicon carbide, hot wall CVD or LPCVD (Low Pressure Chemical Vapor Deposition, low-pressure chemical vapor deposition) is used to grow p-type silicon carbide, the reaction gas is pure silane and pure propane, the carrier gas is hydrogen, and the p-type dopant is trimethylaluminum.
  • hot wall CVD or LPCVD Low Pressure Chemical Vapor Deposition, low-pressure chemical vapor deposition
  • the part of the p-type material film 301 outside the trench structure is removed.
  • dry etching or chemical mechanical polishing (Chemical Mechanical Polishing, CMP) or laser lift-off may be used to remove the part of the p-type material film 301 located outside the trench structure, for example, the CMP method is used to expose The gallium oxide epitaxial layer 103 is formed, and a plurality of p-type material structures 105 are formed in the trench.
  • CMP chemical Mechanical Polishing
  • Step 203 forming a first electrode 104 on the epitaxial layer of gallium oxide and the p-type material structure.
  • the first electrode 104 can be fabricated on the gallium oxide epitaxial layer 103 and the p-type material structure 105 by a metal evaporation method; the material of the first electrode 104 can be Ni, Ti, Al, One of Au, TiN, W, Pt, Pd, Mo and ITO, or a laminated structure composed of multiple. Evaporation methods include magnetron sputtering, electron beam evaporation, chemical plating and other programs. The metal of the first electrode 104 and the gallium oxide epitaxial layer 103 and the p-type material structure 105 form a Schottky contact structure.
  • Step 204 forming a second electrode 101 on a side of the gallium oxide substrate away from the epitaxial layer of gallium oxide.
  • the second electrode 101 is made by metal evaporation on the side of the gallium oxide substrate 102 away from the gallium oxide epitaxial layer 103, and the material of the second electrode 101 can be Ni, Ti, Al, Au , TiN, W, Pt, Pd, Mo and ITO, or a laminated structure composed of multiple. Evaporation methods include magnetron sputtering, electron beam evaporation, chemical plating and other programs. Then, the metal of the second electrode 101 is thermally annealed using a high-temperature rapid annealing device, so that the metal of the first electrode 101 and the gallium oxide substrate 102 form an ohmic contact structure.
  • the annealing temperature is generally 500 degrees to 900 degrees, and the annealing environment can be a nitrogen environment. It is understandable that the second electrode 101 can also be fabricated first, and then the first electrode 104 can be fabricated, which is not specifically limited in the embodiment of the present application.
  • the technical solution of this embodiment provides a method for preparing Schottky diodes to form a heterogeneous PN junction structure between the p-type material structure and the gallium oxide epitaxial layer, thereby avoiding the difficulty of forming the p-type material with the gallium oxide material.
  • Doped materials are used to make Schottky diodes with high technical difficulty and high cost.
  • the manufactured Schottky diodes have a lower turn-on voltage under the condition of high voltage and large current, and have a higher reaction. The breakdown voltage improves the stability of the Schottky diode.

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Abstract

一种肖特基二极管及其制备方法。所述肖特基二极管包括:氧化镓衬底(102);位于所述氧化镓衬底(102)上的氧化镓外延层(103),其中,所述氧化镓外延层(103)远离所述氧化镓衬底(102)的一侧设置有多个沟槽;位于所述多个沟槽内的多个p型材料结构(105);覆盖所述p型材料结构(105)及所述氧化镓外延层(103)的第一电极(104);位于所述氧化镓衬底(102)远离所述氧化镓外延层(103)一侧的第二电极(101)。在p型材料结构(105)与氧化镓外延层(103)之间形成异质PN结结构,从而避免了氧化镓材料由于很难形成p型掺杂材料而用于制作高性能的肖特基二极管时伴随的高技术难度以及高成本的情况,同时制作的肖特基二极管在高电压大电流情况下具有较低的开启电压,且具有较高的反向击穿电压,提高了肖特基二极管工作的稳定性。

Description

肖特基二极管及其制备方法
本申请要求在2019年03月19日提交中国专利局、申请号为201910209930.0的中国专利申请的优先权,该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体技术,例如涉及一种肖特基二极管及其制备方法。
背景技术
氧化镓是一种宽禁带半导体材料,β-Ga 2O 3禁带宽度大约是4.85eV,其临界击穿电场高达8MV/cm,且n型掺杂可控,耐辐射,熔点高,非常适合于制作高压电力电子器件。其应用包括功率电子器件,射频电子器件,紫外探测器,气体传感器等,并在固态照明、通讯、消费电子产品,以及新能源汽车、智能电网等领域有广阔的应用前景。氧化镓具有比碳化硅等第三代半导体材料更优异的耐高压等特性,其Baliga优值(Baliga‘s figure merit,BFOM)比氮化镓高大约4倍,比碳化硅高9倍多,且同质衬底可以采用熔体方式加工,因此具有广阔的应用前景,切合国家节能减排、智能制造、通讯与信息安全的要求。
对氧化镓的研究,目前还处于起步阶段,尽管实验表明氧化镓器件的击穿电场测试值已经超过氮化镓和碳化硅的理论值,但是目前工艺条件下氧化镓器件电学特性相比于其他第三代半导体器件仍然有一定的差距。由于氧化镓受主能级较深,且存在空穴自束缚效应,传统的p型受主元素很难掺杂至氧化镓中以构成p型材料,进而相关技术中利用氧化镓材料实现的PN结通常伴随着高技术难度以及高成本的问题。这在很大程度上限制了利用氧化镓材料来制作肖特基二极管,即无法利用氧化镓材料制备高性能的肖特基二极管。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请提供一种肖特基二极管及其制备方法,以利用氧化镓材料实现高性能的肖特基二极管。
第一方面,本申请实施例提供了一种肖特基二极管,所述肖特基二极管包括:氧化镓衬底;位于所述氧化镓衬底上的氧化镓外延层,其中,所述氧化镓外延层远离所述氧化镓衬底的一侧设置有多个沟槽;位于所述多个沟槽内的多个p型材料结构;覆盖所述p型材料结构及所述氧化镓外延层的第一电极;位于所述氧化镓衬底远离所述氧化镓外延层一侧的第二电极。
在一实施例中,所述p型材料结构采用p型In xAl yGa zN单层结构、p型In xAl yGa zN多层交叠结构或p型碳化硅;其中,在所述p型In xAl yGa zN中,X+Y+Z=1。
在一实施例中,所述p型材料结构的厚度范围为20纳米至500纳米。
在一实施例中,所述沟槽呈周期性排布,所述沟槽为条形沟槽或环形沟槽。
在一实施例中,所述氧化镓衬底采用α-Ga 2O 3衬底,β-Ga 2O 3衬底,γ-Ga 2O 3衬底,δ-Ga 2O 3衬底,或ε-Ga 2O 3衬底。
在一实施例中,所述第一电极和所述第二电极均包括Ni、Ti、Al、Au、TiN、W、Pt、Pd、Mo和ITO中的至少一种。
在一实施例中,所述第一电极包括场板结构。
第二方面,本申请实施例还提供了一种肖特基二极管的制备方法,所述方法包括:提供包括外延层的氧化镓衬底;在氧化镓的外延层上形成多个沟槽;在所述多个沟槽内形成多个p型材料结构;在氧化镓的外延层和所述p型材料结构上形成第一电极;在氧化镓衬底远离所述氧化镓的外延层的一侧形成第二电极。
在一实施例中,在所述多个沟槽内形成多个p型材料结构包括:在所述氧化镓的外延层上生长p型材料膜,所述p型材料膜填充所述多个沟槽;去除所述p型材料膜位于所述多个沟槽结构外的部分。
在一实施例中,在氧化镓的外延层和所述p型材料结构上形成第一电极包括:在氧化镓的外延层和所述p型材料结构上通过金属蒸镀法制作所述第一电极;在氧化镓衬底远离所述氧化镓的外延层的一侧形成第二电极包括:在所述氧化镓衬底远离所述氧化镓的外延层的一侧通过金属蒸镀法制作所述第二电极。
在阅读并理解了附图和详细描述后,可以明白其他方面。
附图说明
图1为本申请实施例提供的一种肖特基二极管的结构示意图;
图2为本申请实施例提供的一种肖特基二极管的制备方法的流程图;
图3-6为本申请实施例提供的对应肖特基二极管的制备方法形成的膜层的结构示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是,此处所描述的示例实施例仅仅用于解释本申请,而非对本申请的限定。另外还需要说明的是,为了便于描述,附图中仅示出了与本申请相关的部分而非全部结构。
参考图1,图1为本申请实施例提供的一种肖特基二极管的结构示意图,肖特基二极管包括氧化镓衬底102;位于氧化镓衬底102上的氧化镓外延层103,其中,氧化镓外延层103远离氧化镓衬底102的一侧设置有多个沟槽;位于多个沟槽内的p型材料结构105;覆盖p型材料结构105及氧化镓外延层103的第一电极104;位于氧化镓衬底102远离氧化镓外延层103一侧的第二电极101。
在一实施例中,氧化镓衬底102为n型高掺杂(n+)氧化镓,氧化镓外延层103为n型低掺杂(n-);第二电极101与氧化镓衬底102之间可为欧姆接触,第一电极104与氧化镓外 延层103及多个p型材料结构105之间可为欧姆接触或肖特基接触,且将p型材料结构105设置于沟槽内,电场集中于沟槽的底部,提高了其他部位耗尽区的分压能力,有效地提高了肖特基二极管的反向击穿电压。p型材料结构105中的多数载流子为空穴,而氧化镓外延层103中的多数载流子为电子,p型材料结构105中的多数载流子(空穴)向氧化镓外延层103中移动,而氧化镓外延层103中的多数载流子(电子)向p型材料结构105中移动,p型材料结构105与氧化镓外延层103之间形成异质PN结结构;而第一电极104与氧化镓外延层103之间形成肖特基结结构;且由于p型材料结构105的制作技术难度较低,只需在氧化镓外延层103上生长即可,也即p型材料结构105结构的形成相比利用氧化镓材料形成p型半导体材料具有更低的技术难度和成本,进而大大降低了利用氧化镓材料形成PN结的难度与成本;当肖特基二极管正向工作,并在第一电极104与第二电极101之间施加较小的工作电压时,由于肖特基结具有较小的开启电压,所以肖特基结先导通,随着施加的电压增大,异质PN结也开始导通,N型材料开始向漂移区注入大量电子,进而降低了漂移区内的导通电阻,也即当肖特基二极管工作在大电流情况下,其正向导通电压也较低,同时PN结导通后,PN结压降不变。
本实施例的技术方案,通过采用包括氧化镓衬底、氧化镓外延层、多个p型材料结构、第一电极和第二电极的肖特基二极管,在p型材料结构与氧化镓外延层之间形成异质PN结结构,从而避免了氧化镓材料由于很难形成p型掺杂材料而用于制作肖特基二极管时伴随的高技术难度和高成本的情况,同时制作的肖特基二极管在高电压大电流情况下具有较低的开启电压,且具有较高的反向击穿电压,提高了肖特基二极管工作的稳定性。
在一实施例中,p型材料结构105采用p型In xAl yGa zN单层结构、p型In xAl yGa zN多层交叠结构或p型碳化硅;当p型材料结构105采用p型In xAl yGa zN单层结构或p型In xAl yGa zN多层交叠结构时,p型材料结构105中掺杂有镁元素;当p型材料结构105采用p型碳化硅时,p型材料结构105中掺杂有铝元素。
可以理解的是,当p型材料结构105采用p型In xAl yGa zN单层结构或p型In xAl yGa zN多层交叠结构时,p型材料结构105中掺杂的元素也可以是除镁元素之外的其他元素;当p型材料结构105采用p型碳化硅时,p型材料结构105中掺杂的元素也可以是除铝之外的其他元素。
在一实施例中,p型材料结构105的厚度范围为20纳米至500纳米。若p型材料结构105过薄,则无法提供有效的空穴,而若p型材料结构105过厚,则会引入更多的材料缺陷,增加体电阻和体电容,进而影响肖特基二极管的性能。通过对p型材料结构105厚度的控制,以使p型材料结构105与氧化镓外延层103之间的耗尽层的厚度达到更优的水平,进一步改善肖特基二极管的性能,例如p型材料结构105的厚度可以为100纳米。
在一实施例中,氧化镓衬底102采用α-Ga 2O 3衬底,β-Ga 2O 3衬底,γ-Ga 2O 3衬底,δ-Ga 2O 3衬底,或ε-Ga 2O 3衬底。
示例性的,β-Ga 2O 3衬底具备高导电性、成本低、且具有良好的化学及热稳定性,可以采 用β-Ga 2O 3作为衬底。
在一实施例中,第一电极101和第二电极104均包括Ni、Ti、Al、Au、TiN、W、Pt、Pd、Mo和ITO中的至少一种。
在一实施例中,第一电极101和第二电极104可以是一种金属或者化合物,也可以是多种金属或化合物组成的叠层结构,以提高第一电极101与第二电极104的导电性能。
在一实施例中,第一电极101可包含场板结构,也可包括终端保护结构,示例性的,可采用悬空的p型保护环来改善肖特基二极管的电场分布,以进一步提高肖特基二极管的击穿电压,增强肖特基二极管工作的稳定性。
在一实施例中,沟槽成周期性排布,沟槽为条形沟槽或环形沟槽。
示例性的,沟槽可为条栅型的结构,或者等间距的同心圆环结构;通过设置周期性的沟槽结构,可降低肖特基二极管的制作难度,同时还可进一步改善肖特基二极管的电场分布,使得肖特基二极管内电场分布更为均匀,增强肖特基二极管的性能。
参考图2,图2为本申请实施例提供的一种肖特基二极管的制备方法的流程图;图3-6为本申请实施例提供的对应肖特基二极管的制备方法形成的膜层的结构示意图;肖特基二极管的制备方法包括步骤201至步骤204。
步骤201,在氧化镓的外延层上形成多个沟槽。
示例性的,可采用包括外延层的氧化镓衬底,如相关技术中的氧化镓衬底;若不采用包括氧化镓外延层的衬底,则可首先在氧化镓衬底上生长一层相应外延层,再执行步骤201。
参考图3,可采用干法刻蚀或湿法腐蚀的方法制备多个沟槽;由于湿法腐蚀一般用于制作尺寸较大的器件,且干法刻蚀具有各向异性刻蚀性好,从而保证细小图形转移后的保真性。例如采用干法刻蚀来制作多个沟槽,干法刻蚀中所采用的气体为SF 6、CF 4、BCl 3,Cl 2,Ar 2中的一种或多种气体的混合。
步骤202,在多个沟槽内形成多个p型材料结构。
在一实施例中,参考图4和图5,在多个沟槽内形成多个p型材料结构105包括:在氧化镓的外延层103上生长p型材料膜301,p型材料膜301填充多个沟槽。
示例性的,p型材料膜301生长的方式可为化学气相沉积法(Chemical Vapor Deposition,MOCVD)、分子束外延法(Molecular Beam Epitaxy,MBE)、氢化物气相外延法(Hydride Vapor Phase Epitaxy,HVPE)或原子层外延法(Atom Layer Deposition,ALD)。若采用MOCVD的方法,生长p型的氮化镓时,p型材料膜301中掺杂的元素可为镁元素,p型材料膜301生长所采用的反应源和载气主要有三甲基镓(TMGa),三甲基铝(TMA),NH 3,二茂镁(Cp 2Mg),H 2,N 2等。p型材料膜301生长温度在1000℃-1100℃之间,二茂镁提供p型掺杂剂。若采用MBE的方法,氮源采用氮气射频氮等离子体源,固态镓作为镓源,固态镁作为镁源,V/III比为1/1,生长室压力为1.1×10 -4mbar。可以理解的是,上述的p型材料膜301是以p型的铝铟镓氮为例,若p型材料膜301采用p型的碳化硅,可以采用热壁式CVD或LPCVD(Low Pressure Chemical Vapor Deposition,低压力化学气相沉积法)的方式生长p型的碳化硅,反 应气体为纯硅烷和纯丙烷,载气为氢气,p型掺杂剂为三甲基铝。
去除p型材料膜301位于沟槽结构外的部分。
示例性的,参考图5,可采用干法刻蚀或者化学机械研磨(Chemical Mechanical Polishing,CMP)或激光剥离去除p型材料膜301位于沟槽结构外的部分,例如采用CMP的方法,以暴露出氧化镓外延层103,并在沟槽内形成多个p型材料结构105。
步骤203,在氧化镓的外延层和p型材料结构上形成第一电极104。
在一实施例中,参考图6,可通过金属蒸镀法在氧化镓的外延层103和p型材料结构105上制作第一电极104;第一电极104的材料可为Ni,Ti,Al,Au,TiN,W,Pt,Pd,Mo和ITO中的一种,或多种组成的叠层结构。蒸镀方式包括磁控溅射,电子束蒸发,化学电镀等方案。以使第一电极104金属与氧化镓外延层103及p型材料结构105形成肖特基接触结构。
步骤204,在氧化镓衬底远离氧化镓的外延层的一侧形成第二电极101。
在一实施例中,在氧化镓衬底102远离氧化镓外延层103的一侧上通过金属蒸镀的方法,制作第二电极101,第二电极101的材料可为Ni,Ti,Al,Au,TiN,W,Pt,Pd,Mo和ITO中的一种,或多种组成的叠层结构。蒸镀方式包括磁控溅射,电子束蒸发,化学电镀等方案。接着利用高温快速退火设备对第二电极101金属进行热退火,以使第一电极101金属与氧化镓衬底102形成欧姆接触结构。其中,退火温度一般为500度至900度,退火环境可采用氮气环境。可以理解的是,也可先制作第二电极101,再制作第一电极104,本申请实施例对此不做具体限定。
本实施例的技术方案,通过提供一种肖特基二极管的制备方法,在p型材料结构与氧化镓外延层之间形成异质PN结结构,从而避免了氧化镓材料由于很难形成p型掺杂材料而用于制作肖特基二极管时伴随的高技术难度和高成本的情况,同时制作的肖特基二极管在高电压大电流情况下具有较低的开启电压,且具有较高的反向击穿电压,提高了肖特基二极管工作的稳定性。

Claims (10)

  1. 一种肖特基二极管,所述肖特基二极管包括:
    氧化镓衬底;
    位于所述氧化镓衬底上的氧化镓外延层,其中,所述氧化镓外延层远离所述氧化镓衬底的一侧设置有多个沟槽;
    位于所述多个沟槽内的多个p型材料结构;
    覆盖所述p型材料结构及所述氧化镓外延层的第一电极;
    位于所述氧化镓衬底远离所述氧化镓外延层一侧的第二电极。
  2. 根据权利要求1所述的肖特基二极管,其中,所述p型材料结构采用p型In xAl yGa zN单层结构、p型In xAl yGa zN多层交叠结构或p型碳化硅;
    其中,在所述p型In xAl yGa zN中,X+Y+Z=1。
  3. 根据权利要求2所述的肖特基二极管,其中,所述p型材料结构的厚度范围为20纳米至500纳米。
  4. 根据权利要求1所述的肖特基二极管,其中,所述沟槽呈周期性排布,所述沟槽为条形沟槽或环形沟槽。
  5. 根据权利要求1所述的肖特基二极管,其中,所述氧化镓衬底采用α-Ga 2O 3衬底,β-Ga 2O 3衬底,γ-Ga 2O 3衬底,δ-Ga 2O 3衬底,或ε-Ga 2O 3衬底。
  6. 根据权利要求1所述的肖特基二极管,其中,所述第一电极和所述第二电极均包括Ni、Ti、Al、Au、TiN、W、Pt、Pd、Mo和ITO中的至少一种。
  7. 根据权利要求1所述的肖特基二极管,其中,所述第一电极包括场板结构。
  8. 一种肖特基二极管的制备方法,包括:
    提供包括外延层的氧化镓衬底;
    在氧化镓的外延层上形成多个沟槽;
    在所述多个沟槽内形成多个p型材料结构;
    在氧化镓的外延层和所述p型材料结构上形成第一电极;
    在氧化镓衬底远离所述氧化镓的外延层的一侧形成第二电极。
  9. 根据权利要求8所述的肖特基二极管的制备方法,其中,在所述多个沟槽内形成多个p型材料结构包括:
    在所述氧化镓的外延层上生长p型材料膜,所述p型材料膜填充所述多个沟槽;
    去除所述p型材料膜位于所述多个沟槽结构外的部分。
  10. 根据权利要求8所述的肖特基二极管的制备方法,其中,在氧化镓的外延层和所述p型材料结构上形成第一电极包括:
    在氧化镓的外延层和所述p型材料结构上通过金属蒸镀法制作所述第一电极;
    在氧化镓衬底远离所述氧化镓的外延层的一侧形成第二电极包括:
    在所述氧化镓衬底远离所述氧化镓的外延层的一侧通过金属蒸镀法制作所述第一电极。
PCT/CN2019/103911 2019-03-19 2019-09-02 肖特基二极管及其制备方法 WO2020186700A1 (zh)

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