WO2020177057A1 - Cmos结构及cmos结构的制造方法 - Google Patents
Cmos结构及cmos结构的制造方法 Download PDFInfo
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Definitions
- the present invention relates to the field of display technology. More specifically, it relates to a CMOS structure and a manufacturing method of the CMOS structure.
- CMOS Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor
- LTPS Low Temperature Poly-silicon, low temperature polysilicon
- the embodiment of the present invention provides a CMOS structure and a manufacturing method of the CMOS structure.
- the CMOS structure includes a substrate and N-type TFTs and P-type TFTs on the substrate.
- the N-type TFT includes: a first gate electrode, a first active layer, and a first gate dielectric layer located between the first gate electrode and the first active layer.
- the source layer includes a first semiconductor layer and an N-type second semiconductor layer and an N-type third semiconductor layer that are located at opposite ends of the first semiconductor layer and are sequentially stacked in a direction away from the first gate dielectric layer .
- the N-type doping concentration of the second semiconductor layer is less than the N-type doping concentration of the third semiconductor layer.
- the P-type TFT includes: a second gate electrode, a second active layer, and a second gate dielectric layer located between the second gate electrode and the second active layer, wherein the first
- the two active layers include a fourth semiconductor layer and a P-type fifth semiconductor layer and a P-type sixth semiconductor layer that are located at opposite ends of the fourth semiconductor layer and are stacked in a direction away from the second gate dielectric layer.
- Semiconductor layer wherein, the P-type doping concentration of the fifth semiconductor layer is less than the P-type doping concentration of the sixth semiconductor layer.
- At least a portion of the first semiconductor layer serving as a channel region and a portion of the fourth semiconductor layer serving as a channel region include a polycrystalline semiconductor material.
- the source/drain regions of the first semiconductor layer and the source/drain regions of the fourth semiconductor layer include amorphous semiconductor materials.
- the second semiconductor layer, the third semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer include the polycrystalline semiconductor material.
- the polycrystalline semiconductor material includes polycrystalline silicon
- the amorphous semiconductor material includes amorphous silicon
- the N-type TFT further includes a first etch stop layer located on a side of the first semiconductor layer that is a channel region portion away from the first gate dielectric layer, and The end of the first etch stop layer is located between the first semiconductor layer and the second semiconductor layer.
- the P-type TFT further includes a second etch stop layer located on a side of the fourth semiconductor layer that is a part of the channel region away from the second gate dielectric layer, and the second etch stop layer The end of is located between the fourth semiconductor layer and the fifth semiconductor layer.
- the first gate, the first gate dielectric layer, and the first semiconductor layer are sequentially stacked in a direction away from the substrate, and wherein the second gate, The second gate dielectric layer and the second semiconductor layer are sequentially stacked in a direction away from the substrate.
- the first active layer has a first source/drain region adjacent to the P-type TFT and a second source/drain region far from the P-type TFT
- the second active layer has a third source/drain region adjacent to the N-type TFT and a fourth source/drain region far from the P-type TFT
- the CMOS structure further includes: disposed in the first source/drain region The first source/drain electrode on the upper side; the second source/drain electrode provided on the second source/drain region; the third source/drain electrode provided on the third source/drain region Electrode; a fourth source/drain electrode disposed on the fourth source/drain region, wherein the first source/drain electrode is connected to the third source/drain electrode.
- Another object of the embodiments of the present invention is to provide a method for manufacturing a CMOS structure.
- the manufacturing method of the CMOS structure includes forming N-type TFT and P-type TFT on a substrate.
- forming the N-type TFT includes forming a first gate electrode, a first active layer, and a first gate dielectric layer located between the first gate electrode and the first active layer, so
- the first active layer includes a first semiconductor layer and an N-type second semiconductor layer and an N-type semiconductor layer that are sequentially stacked in a direction away from the first gate dielectric layer at opposite ends of the first semiconductor layer The third semiconductor layer.
- the N-type doping concentration of the second semiconductor layer is less than the N-type doping concentration of the third semiconductor layer.
- Forming the P-type TFT includes forming a second gate electrode, a second active layer, and a second gate dielectric layer located between the second gate electrode and the second active layer.
- the second active layer includes a fourth semiconductor layer and a P-type fifth semiconductor layer located at opposite ends of the fourth semiconductor layer and sequentially stacked in a direction away from the second gate dielectric layer And P-type sixth semiconductor layer.
- the P-type doping concentration of the fifth semiconductor layer is less than the P-type doping concentration of the sixth semiconductor layer.
- At least the channel region of the first semiconductor layer and the channel region of the fourth semiconductor layer include a polycrystalline semiconductor material, and the source/drain regions of the first semiconductor layer and the second semiconductor layer The source/drain regions of the four semiconductor layers include amorphous semiconductor materials.
- forming the first gate dielectric layer and the second gate dielectric layer includes forming a gate dielectric material layer on the first gate electrode and the second gate electrode, wherein , The portion of the gate material dielectric layer located on the first gate electrode constitutes the first gate dielectric layer, and the portion of the gate material dielectric layer located on the second gate electrode constitutes The second gate dielectric layer.
- forming the first semiconductor layer and the second semiconductor layer includes: forming a first amorphous semiconductor material on the gate dielectric material layer; The portions located on the first gate electrode and the second gate electrode are converted into polycrystalline semiconductor materials to form the channel region of the first active layer and the channel of the second active layer Area.
- the conversion includes laser annealing the amorphous semiconductor material.
- the laser annealing includes using a microlens array mask.
- the method of manufacturing the CMOS structure further includes: forming a first etch stop layer on a portion of the first semiconductor layer serving as a channel region; and forming a first etch stop layer on the fourth semiconductor layer A second etch stop layer is formed on part of the channel region.
- forming the second semiconductor layer and the third semiconductor layer includes: forming a second amorphous semiconductor material layer on the first semiconductor layer; on the second amorphous semiconductor material layer Forming a third amorphous semiconductor material layer; etching the second amorphous semiconductor material layer and the third amorphous semiconductor material layer located on the first etch stop layer to form a layer extending to the first etching The first interval of the etch barrier.
- forming the fifth semiconductor layer and the sixth semiconductor layer includes: forming a fifth amorphous semiconductor material layer on the fourth semiconductor layer; on the fifth amorphous semiconductor material layer Forming a sixth amorphous semiconductor material layer; etching the fifth amorphous semiconductor material layer and the sixth amorphous semiconductor material layer located on the second etch stop layer to form a layer extending to the second etching The second interval of the etch barrier.
- forming the second amorphous semiconductor material layer, the third amorphous semiconductor material layer, the fifth amorphous semiconductor material layer, and the sixth amorphous semiconductor material layer includes using CVD.
- the first active layer has a first source/drain region adjacent to the P-type TFT and a second source/drain region far from the P-type TFT, and the second active layer The layer has a third source/drain region adjacent to the N-type TFT and a fourth source/drain region far from the N-type TFT.
- the method further includes: in the third semiconductor layer, the sixth A conductive layer is formed on the semiconductor layer, the first gate dielectric layer and the second gate dielectric layer; the conductive layer is etched to form a first part, a second part and a third part that are isolated from each other, wherein, the first part covers the first source/drain region and the third source/drain region, the second part covers the second source/drain region, and the third part covers all The fourth source/drain region.
- the polycrystalline semiconductor material includes polycrystalline silicon
- the amorphous semiconductor material includes amorphous silicon
- Fig. 1 is a schematic diagram of a CMOS structure according to an embodiment of the present invention.
- FIG. 2 is a schematic diagram of a CMOS structure according to an embodiment of the present invention.
- FIG. 3 is a schematic diagram of a CMOS structure according to an embodiment of the present invention.
- FIG. 4 is a schematic diagram of a manufacturing method of a CMOS structure according to an embodiment of the present invention.
- 5A-5C are schematic diagrams of a method of forming a second semiconductor layer and a third semiconductor layer in a method of manufacturing a CMOS structure according to an embodiment of the present invention
- 6A-6C are schematic diagrams of a method of forming a fifth semiconductor layer and a sixth semiconductor layer in a method of manufacturing a CMOS structure according to an embodiment of the present invention
- FIGS. 7A-7B are schematic diagrams of a manufacturing method of a CMOS structure according to an embodiment of the present invention.
- the terms “overlying”, “on top of”, “positioned on top” or “positioned on top” mean that a first element such as a first structure is present on a second element such as a second structure Above, where there may be an intermediate element such as an interface structure between the first element and the second element.
- the term “contact” means to connect a first element such as a first structure and a second element such as a second structure, and there may or may not be other elements at the interface of the two elements.
- Fig. 1 is a schematic diagram of a CMOS structure according to an embodiment of the present invention.
- the CMOS structure according to the embodiment of the present invention includes a substrate 01 and an N-type thin film transistor (N-type TFT) TFT1 and a P-type thin film transistor (P-type TFT) TFT2 located on the substrate 01.
- the N-type TFT includes: a first gate electrode 11, a first active layer 12, and a first gate dielectric layer 13 located between the first gate electrode 11 and the first active layer 12. .
- the first active layer 12 includes a first semiconductor layer 121 and an N-type second semiconductor layer located at opposite ends (E1, E2) of the first semiconductor layer 121 and sequentially stacked in a direction away from the first gate dielectric layer 13.
- the N-type doping concentration of the second semiconductor layer 122 is less than the N-type doping concentration of the third semiconductor layer 123.
- the P-type TFT includes: a second gate electrode 21, a second active layer 22, and a second gate dielectric layer 23 between the second gate electrode 21 and the second active layer 22.
- the second active layer 22 includes a fourth semiconductor layer 221 and a P-type fifth layer located at opposite ends (E3, E4) of the fourth semiconductor layer 221 and sequentially stacked in a direction away from the second gate dielectric layer 23.
- the P-type doping concentration of the fifth semiconductor layer 222 is less than the P-type doping concentration of the sixth semiconductor layer 223.
- the second semiconductor layer 122 with a lower doping concentration separates the third semiconductor layer 123 with a higher doping concentration from the first semiconductor layer 121
- the fifth semiconductor layer 222 with a lower doping concentration separates
- the sixth semiconductor layer 223 with a higher doping concentration is separated from the first semiconductor layer 221. Therefore, the lightly doped layer (the second semiconductor layer 122 and the fifth semiconductor layer 222) of the embodiment of the present invention can combine the heavily doped layer (the third semiconductor layer 123 and the sixth semiconductor layer 223) for ohmic contact with The channel regions (a part of the first semiconductor layer 121) are separated. Therefore, the embodiments of the present invention can reduce the hot carrier effect and reduce the leakage current.
- the portion P11 of the first semiconductor layer 121 as the channel region and the portion P21 of the fourth semiconductor layer 221 as the channel region may include a polycrystalline semiconductor material.
- the source/drain region P12 of the first semiconductor layer 121 and the source/drain region P22 of the fourth semiconductor layer 221 may include an amorphous semiconductor material.
- the second semiconductor layer 122, the third semiconductor layer 123, the fifth semiconductor layer 222, and the sixth semiconductor layer 223 may include polycrystalline semiconductor materials.
- the polycrystalline semiconductor material may include polycrystalline silicon
- the amorphous semiconductor material may include amorphous silicon.
- Fig. 2 is a schematic diagram of a CMOS structure according to an embodiment of the present invention.
- the N-type TFT (TFT1) further includes a first etch stop layer 14 on the side of the first semiconductor layer 121 that is the channel region portion P11 away from the first gate dielectric layer 13. .
- the 14E end of the first etch stop layer 14 is located between the first semiconductor layer 121 and the second semiconductor layer 122.
- the P-type TFT (TFT2) also includes a second etch stop layer 24 on the side of the fourth semiconductor layer 221 serving as the channel region P21 (see FIG. 1) away from the second gate dielectric layer 23.
- the end 24E of the second etch stop layer 24 is located between the fourth semiconductor layer 221 and the fifth semiconductor layer 222.
- the thin film transistor may have a bottom gate structure, as shown in FIGS. 1 and 2.
- the first gate 11, the first gate dielectric layer 13 and the first semiconductor layer 121 may be sequentially stacked in a direction away from the substrate 01.
- the second gate 21, the second gate dielectric layer 23, and the second semiconductor layer 221 may be sequentially stacked in a direction away from the substrate 01.
- the thin film transistor may also have a top gate structure.
- the first semiconductor layer 121, the first gate dielectric layer 13, and the first gate 11 may be sequentially stacked in a direction away from the substrate 01.
- the second semiconductor layer 221, the second gate dielectric layers 2 and 3, and the second gate 21 may be sequentially stacked in a direction away from the substrate 01.
- Fig. 3 is a schematic diagram of a CMOS structure according to an embodiment of the present invention.
- the first active layer 12 has a first source/drain region R1 adjacent to the P-type TFT (TFT2) and a second source/drain region R2 far from the P-type TFT (TFT2).
- the second active layer 22 has a third source/drain region R3 adjacent to the N-type TFT (TFT1) and a fourth source/drain region R4 far from the P-type TFT (TFT2).
- the CMOS structure further includes: a first source/drain electrode 51 disposed on the first source/drain region R1, and a second source/drain electrode 51 disposed on the second source/drain region R2.
- the first source/drain electrode 51 is connected to the third source/drain electrode 53.
- the second semiconductor layer 122 may be an N-type lightly doped semiconductor layer.
- the N-type doping concentration of the second semiconductor layer 122 may be between 10 17 ions/cm 3 and 10 19 ions/cm 3 .
- the third semiconductor layer 123 may be an N-type heavily doped semiconductor layer.
- the N-type doping concentration of the third semiconductor layer 123 may be between 10 19 ions/cm 3 and 10 21 ions/cm 3 .
- the fifth semiconductor layer 222 may be a P-type lightly doped semiconductor layer.
- the doping concentration of the fifth semiconductor layer 222 may be between 10 17 ions/cm 3 and 10 19 ions/cm 3 .
- the sixth semiconductor layer 223 may be a P-type heavily doped semiconductor layer.
- the P-type doping concentration of the sixth semiconductor layer 223 may be between 10 19 ions/cm 3 and 10 21 ions/cm 3 .
- the N-type TFT (TFT1) and the P-type TFT (TFT2) are connected by the first source/drain electrode 51 and the third source/drain electrode 53, avoiding direct contact between the third semiconductor layer 123 and the sixth semiconductor layer 223 to achieve connection
- the undesirable barriers brought about are conducive to improving the performance of CMOS structures.
- the embodiment of the present invention also provides a method for manufacturing a CMOS structure.
- a method of manufacturing a CMOS structure according to an embodiment of the present invention includes forming an N-type TFT and a P-type TFT on a substrate.
- forming an N-type TFT includes: forming a first gate electrode 11, a first active layer 12, and a first gate located between the first gate electrode 11 and the first active layer 12.
- Medium layer 13 The first active layer 12 includes a first semiconductor layer 121 and an N-type second semiconductor layer located at opposite ends (E1, E2) of the first semiconductor layer 121 and sequentially stacked in a direction away from the first gate dielectric layer 13.
- Layer 122 and an N-type third semiconductor layer 123 The N-type doping concentration of the second semiconductor layer 122 is less than the N-type doping concentration of the third semiconductor layer 123.
- forming a P-type TFT includes forming a second gate electrode 21, a second active layer 22, and a second gate located between the second gate electrode 21 and the second active layer 22 Medium layer 23.
- the second active layer 22 includes a fourth semiconductor layer 221 and a P-type layer located at opposite ends (E3, E4) of the fourth semiconductor layer 221 and stacked in a direction away from the second gate dielectric layer 23.
- the P-type doping concentration of the fifth semiconductor layer 222 is less than the P-type doping concentration of the sixth semiconductor layer 223.
- the channel region P11 of the first semiconductor layer and the channel region P12 of the fourth semiconductor layer may include polycrystalline semiconductor materials, and the source/drain regions P12 of the first semiconductor layer and the fourth semiconductor layer
- the source/drain region P22 of the semiconductor layer may include an amorphous semiconductor material.
- the polycrystalline semiconductor material may include polycrystalline silicon, and the amorphous semiconductor material may include amorphous silicon.
- forming the first gate dielectric layer 13 and the second gate dielectric layer 23 includes forming a gate dielectric on the first gate electrode 11 and the second gate electrode 21.
- Material layer 03. wherein, the portion of the gate material dielectric layer 03 located on the first gate electrode 11 constitutes the first gate dielectric layer 13, and the gate material dielectric layer 03 is located on the second gate electrode 21 The upper part constitutes the second gate dielectric layer 23.
- forming the first semiconductor layer and the second semiconductor layer includes: forming a first amorphous semiconductor material layer 02 on the gate dielectric material layer 03; The portion of the crystalline semiconductor material layer 02 located on the first gate electrode 11 and the second gate electrode 21 is converted into a polycrystalline semiconductor material to form the channel region P11 of the first active layer 12 and the second active layer 22 ⁇ channel area P21.
- the thickness of the first amorphous semiconductor material layer 02 may be 500 angstroms.
- Laser annealing can be used to convert the amorphous semiconductor material into a polycrystalline semiconductor material (that is, to perform a polycrystallization process).
- a Micro Lens Array (MLA) mask can be used for laser annealing.
- MLA annealing has the advantage of high position accuracy.
- the manufacturing method of the CMOS structure may further include: forming a first etch stop layer 14 on a portion P11 of the first semiconductor layer as a channel region; and forming a first etch stop layer 14 on the fourth semiconductor layer A second etch stop layer 24 is formed on the portion P21 of the channel region.
- an etch stop material layer may be deposited on the first amorphous semiconductor material layer 02 that has undergone polycrystallization treatment. Then, the etching stop material layer is etched to form the first etching stop layer 14 and the second etching stop layer 24.
- FIGS. 5A-5C are schematic diagrams of a method of forming a second semiconductor layer and a third semiconductor layer in a method of manufacturing a CMOS structure according to an embodiment of the present invention.
- forming the second semiconductor layer and the third semiconductor layer includes:
- a second amorphous semiconductor material layer 04 on the first semiconductor layer 121.
- lightly doped N-type amorphous silicon with a thickness of 500 angstroms can be deposited on the first semiconductor layer.
- the N-type semiconductor layer may be doped with a pentavalent impurity element of phosphorus.
- a third amorphous semiconductor material layer 05 on the second amorphous semiconductor material layer 122.
- a heavily doped N-type amorphous silicon semiconductor layer with a thickness of 500 angstroms can be deposited on the second amorphous semiconductor material layer.
- FIGS. 6A-6C are schematic diagrams of a method of forming a fifth semiconductor layer and a sixth semiconductor layer in a method of manufacturing a CMOS structure according to an embodiment of the present invention. As shown in FIGS. 6A-6C, in the embodiment of the present invention, forming the fifth semiconductor layer and the sixth semiconductor layer includes:
- a fifth amorphous semiconductor material layer 06 on the fourth semiconductor layer 221.
- lightly doped P-type amorphous silicon with a thickness of 500 angstroms can be deposited on the fourth semiconductor layer.
- the P-type semiconductor layer may be doped with trivalent impurity elements such as boron.
- a sixth amorphous semiconductor material layer 07 on the fifth amorphous semiconductor material layer 06.
- heavily doped P-type amorphous silicon with a thickness of 500 angstroms can be deposited on the fifth amorphous semiconductor material layer 06.
- forming the second amorphous semiconductor material layer, the third amorphous semiconductor material layer, the fifth amorphous semiconductor material layer, and the sixth amorphous semiconductor material layer includes using chemical vapor deposition (CVD).
- CVD chemical vapor deposition
- FIGS. 7A-7B are schematic diagrams of a manufacturing method of a CMOS structure according to an embodiment of the present invention.
- the first active layer 12 has a first source/drain region R1 adjacent to the P-type TFT (TFT2) and a second source/drain region R2 far from the P-type TFT (TFT2).
- the second active layer 22 has a third source/drain region R3 adjacent to the N-type TFT (TFT1) and a fourth source/drain region R4 far from the N-type TFT (TFT2).
- the manufacturing method of the CMOS structure according to the embodiment of the present invention may further include:
- the conductive layer is etched to form a first part 08a (51, 53), a second part 08b (52) and a third part 08c (54) that are isolated from each other.
- first portion 08a covers the first source/drain region R1 and the third source/drain region R3, and the second portion 08b covers the second source/drain region R2.
- the third part 08c covers the fourth source/drain region R4.
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Abstract
本发明涉及一种CMOS结构及其制造方法。该CMOS结构包括衬底和位于衬底上的N型TFT和P型TFT。该N型TFT包括第一栅极电极、第一有源层以及位于二者之间的第一栅极介质层。该第一有源层包括第一半导体层和位于其相对两端的且沿远离第一栅极介质层的方向上依次层叠的N型的第二半导体层和N型的第三半导体层。第二半导体层的N型掺杂浓度小于所述第三半导体层的N型掺杂浓度。该P型TFT包括第二栅极电极、第二有源层以及位于二者之间的第二栅极介质层。第二有源层包括第四半导体层和位于其相对两端的且沿远离第二栅极介质层的方向上依次层叠的P型的第五半导体层和P型的第六半导体层。第五半导体层的P型掺杂浓度小于第六半导体层的P型掺杂浓度。
Description
本发明涉及显示技术领域。更具体地,涉及一种CMOS结构及CMOS结构的制造方法。
随着显示技术与传感技术的结合与升级,新装置对TFT(Thin film transistor,薄膜晶体管)要求越来越高,不仅要求TFT具有简单开关的功能,更要具有逻辑计算和处理功能,因此这就需要TFT形成CMOS(Complementary Metal Oxide Semiconductor,互补金属氧化物半导体)结构。然而,目前采用LTPS(Low Temperature Poly-silicon,低温多晶硅)可以实现采用TFT的CMOS结构的制造,但工艺制作复杂,成本较高。
发明内容
本发明的实施例提供了一种CMOS结构及CMOS结构的制造方法。
本发明的实施例的一个目的在于提供一种CMOS结构。所述CMOS结构包括衬底和位于所述衬底上的N型TFT和P型TFT。所述N型TFT包括:第一栅极电极、第一有源层以及位于所述第一栅极电极和所述第一有源层之间的第一栅极介质层,所述第一有源层包括第一半导体层和位于所述第一半导体层相对两端的且沿远离所述第一栅极介质层的方向上依次层叠的N型的第二半导体层和N型的第三半导体层。其中,所述第二半导体层的N型掺杂浓度小于所述第三半导体层的N型掺杂浓度。所述P型TFT包括:第二栅极电极、第二有源层以及位于所述第二栅极电极和所述第二有源层之间的第二栅极介质层,其中,所述第二有源层包括第四半导体层和位于所述第四半导体层相对两端的且沿远离所述第二栅极介质层的方向上依次层叠的P型的第五半导体层和P型的第六半导体层。其中,所述第五半导体层的P型掺杂浓度小于所述第六半导体层的P型掺杂浓 度。
在一些实施例中,至少所述第一半导体层的作为沟道区的部分和所述第四半导体层的作为沟道区的部分包括多晶半导体材料。
在一些实施例中,所述第一半导体层的源/漏极区域和所述第四半导体层的源/漏极区域包括非晶半导体材料。
在一些实施例中,所述第二半导体层、所述第三半导体层、所述第五半导体层和所述第六半导体层包括所述多晶半导体材料。
在一些实施例中,所述多晶半导体材料包括多晶硅,所述非晶半导体材料包括非晶硅。
在一些实施例中,所述N型TFT还包括位于所述第一半导体层的作为沟道区部分的远离所述第一栅极介质层的一侧上的第一刻蚀阻挡层,所述第一刻蚀阻挡层的端部位于所述第一半导体层和所述第二半导体层之间。所述P型TFT还包括位于所述第四半导体层作为沟道区的部分的远离所述第二栅极介质层的一侧上的第二刻蚀阻挡层,所述第二刻蚀阻挡层的端部位于所述第四半导体层和所述第五半导体层之间。
在一些实施例中,所述第一栅极、所述第一栅极介质层和所述第一半导体层沿远离所述衬底的方向上依次层叠,并且其中,所述第二栅极、所述第二栅极介质层和所述第二半导体层沿远离所述衬底的方向上依次层叠。
在一些实施例中,所述第一有源层具有邻近所述P型TFT的第一源/漏极区和远离所述P型TFT的第二源/漏极区,所述第二有源层具有邻近所述N型TFT的第三源/漏极区和远离所述P型TFT的第四源/漏极区,所述CMOS结构还包括:设置在所述第一源/漏极区上的第一源/漏极电极;设置在所述第二源/漏极区上的第二源/漏极电极;设置在所述第三源/漏极区上的第三源/漏极电极;设置在所述第四源/漏极区上的第四源/漏极电极,其中,所述第一源/漏极电极与所述第三源/漏极电极连接。
本发明的实施例的另一个目的在于提供一种CMOS结构的制造方法。
所述CMOS结构的制造方法包括在衬底上形成N型TFT和P型TFT。 其中,形成所述N型TFT包括:形成第一栅极电极、第一有源层以及位于所述第一栅极电极和所述第一有源层之间的第一栅极介质层,所述第一有源层包括第一半导体层和位于所述第一半导体层相对两端且沿远离所述第一栅极介质层的方向上依次层叠的的N型的第二半导体层和N型的第三半导体层。其中,所述第二半导体层的N型掺杂浓度小于所述第三半导体层的N型掺杂浓度。形成所述P型TFT包括:形成第二栅极电极、第二有源层以及位于所述第二栅极电极和所述第二有源层之间的第二栅极介质层。其中,所述第二有源层包括第四半导体层和位于所述第四半导体层的相对两端的且沿远离所述第二栅极介质层的方向上依次层叠的P型的第五半导体层和P型的第六半导体层。其中,所述第五半导体层的P型掺杂浓度小于所述第六半导体层的P型掺杂浓度。
在一些实施例中,至少所述第一半导体层的沟道区和所述第四半导体层的沟道区包括多晶半导体材料,所述第一半导体层的源/漏极区域和所述第四半导体层的源/漏极区域包括非晶半导体材料。
在一些实施例中,形成所述第一栅极介质层和所述第二栅极介质层包括在所述第一栅极电极和所述第二栅极电极上形成栅极介质材料层,其中,所述栅极材料介质层的位于所述第一栅极电极上的部分构成所述第一栅极介质层,所述栅极材料介质层的位于所述第二栅极电极上的部分构成所述第二栅极介质层。
在一些实施例中,形成所述第一半导体层和所述第二半导体层包括:在所述栅极介质材料层上形成第一非晶半导体材料;将所述第一非晶半导体材料层的位于所述第一栅极电极和所述第二栅极电极上的部分转换成多晶半导体材料,以形成所述第一有源层的沟道区和所述第二有源层的沟道区。
在一些实施例中,所述转换包括对所述非晶半导体材料进行激光退火。
在一些实施例中,所述激光退火包括采用微透镜阵列掩模。
在一些实施例中,所述CMOS结构的制造方法,还包括:在所述第一 半导体层的作为沟道区的部分上形成第一刻蚀阻挡层;以及在所述第四半导体层的作为沟道区的部分上形成第二刻蚀阻挡层。
在一些实施例中,形成所述第二半导体层和所述第三半导体层包括:在所述第一半导体层上形成第二非晶半导体材料层;在所述第二非晶半导体材料层上形成第三非晶半导体材料层;刻蚀位于所述第一刻蚀阻挡层上的所述第二非晶半导体材料层和所述第三非晶半导体材料层以形成延伸到所述第一刻蚀阻挡层的第一间隔。
在一些实施例中,形成所述第五半导体层和所述第六半导体层包括:在所述第四半导体层上形成第五非晶半导体材料层;在所述第五非晶半导体材料层上形成第六非晶半导体材料层;刻蚀位于所述第二刻蚀阻挡层上的所述第五非晶半导体材料层和所述第六非晶半导体材料层以形成延伸到所述第二刻蚀阻挡层的第二间隔。
在一些实施例中,形成第二非晶半导体材料层、第三非晶半导体材料层、第五非晶半导体材料层和第六非晶半导体材料层包括使用CVD。
在一些实施例中,所述第一有源层具有邻近所述P型TFT的第一源/漏极区和远离所述P型TFT的第二源/漏极区,所述第二有源层具有邻近所述N型TFT的第三源/漏极区和远离所述N型TFT的第四源/漏极区,所述方法还包括:在所述第三半导体层、所述第六半导体层、所述第一栅极介质层和所述第二栅极介质层上形成导电层;对所述导电层进行刻蚀,以形成彼此隔离的第一部分、第二部分和第三部分,其中,所述第一部分覆盖所述第一源/漏极区和所述第三源/漏极区,所述第二部分覆盖所述第二源/漏极区,所述第三部分覆盖所述第四源/漏极区。
在一些实施例中,所述多晶半导体材料包括多晶硅,所述非晶半导体材料包括非晶硅。
为了更清楚地说明本发明的实施例的技术方案,下面将对实施例的附图进行简要说明,应当知道,以下描述的附图仅仅涉及本发明的一些实施 例,而非对本发明的限制,其中:
图1为根据本发明的实施例的CMOS结构示意图;
图2为根据本发明的实施例的CMOS结构示意图;
图3为根据本发明的实施例的CMOS结构的示意图;
图4为根据本发明的实施例的CMOS结构的制造方法的示意图;
图5A-5C为根据本发明的实施例的CMOS结构的制造方法的形成第二半导体层和第三半导体层的方法的示意图;
图6A-6C为根据本发明的实施例的CMOS结构的制造方法的形成第五半导体层和第六半导体层的方法的示意图;
图7A-7B为根据本发明的实施例的CMOS结构的制造方法的示意图。
为了使本发明的实施例的目的、技术方案和优点更加清楚,下面将接合附图,对本发明的实施例的技术方案进行清楚、完整的描述。显然,所描述的实施例是本发明的一部分实施例,而不是全部的实施例。基于所描述的本发明的实施例,本领域技术人员在无需创造性劳动的前提下所获得的所有其他实施例,也都属于本发明保护的范围。
当介绍本发明的元素及其实施例时,冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素。用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素。
出于下文表面描述的目的,如其在附图中被标定方向那样,术语“上”、“下”、“左”、“右”“垂直”、“水平”、“顶”、“底”及其派生词应涉及发明。术语“上覆”、“在……顶上”、“定位在……上”或者“定位在……顶上”意味着诸如第一结构的第一要素存在于诸如第二结构的第二要素上,其中,在第一要素和第二要素之间可存在诸如界面结构的中间要素。术语“接触”意味着连接诸如第一结构的第一要素和诸如第二结构的第二要素,而在两个要素的界面处可以有或者没有其它要素。
图1为根据本发明的实施例的CMOS结构示意图。如图1所示,根据 本发明的实施例的CMOS结构包括衬底01和位于衬底01上的N型薄膜晶体管(N型TFT)TFT1和P型薄膜晶体管(P型TFT)TFT2。如图1所示,该N型TFT包括:第一栅极电极11、第一有源层12以及位于第一栅极电极11和第一有源层12之间的第一栅极介质层13。该第一有源层12包括第一半导体层121和位于第一半导体层121相对两端(E1,E2)的且沿远离第一栅极介质层13的方向上依次层叠的N型的第二半导体层122和N型的第三半导体层123。该第二半导体层122的N型掺杂浓度小于该第三半导体层123的N型掺杂浓度。
该P型TFT包括:第二栅极电极21、第二有源层22以及位于第二栅极电极21和第二有源层22之间的第二栅极介质层23。该第二有源层22包括第四半导体层221和位于第四半导体层221相对两端(E3,E4)的且沿远离第二栅极介质层23的方向上依次层叠的P型的第五半导体层222和P型的第六半导体层223。该第五半导体层222的P型掺杂浓度小于该第六半导体层223的P型掺杂浓度。
如图1所示,掺杂浓度较低的第二半导体层122将掺杂浓度较高的第三半导体层123与第一半导体层121隔离开,掺杂浓度较低的第五半导体层222将掺杂浓度较高的第六半导体层223与第一半导体层221隔离开。从而,本发明的实施例的轻掺杂层(第二半导体层122、第五半导体层222)能够将用于欧姆接触的重掺杂层(第三半导体层123、第六半导体层223)与沟道区(第一半导体层121的一部分)相分离。因此,本发明的实施例能够实现减弱热载流子效应并且降低漏电流。
在一些实施例中,至少第一半导体层121的作为沟道区的部分P11和第四半导体层221的作为沟道区的部分P21可以包括多晶半导体材料。在一些实施例中,第一半导体层121的源/漏极区域P12和第四半导体层221的源/漏极区域P22可以包括非晶半导体材料。在一些实施例中,第二半导体层122、第三半导体层123、第五半导体层222和第六半导体层223可以包括多晶半导体材料。例如,多晶半导体材料可以包括多晶硅,非晶半导体材料可以包括非晶硅。
图2为根据本发明的实施例的CMOS结构的示意图。如图2所示,N型TFT(TFT1)还包括位于第一半导体层121的作为沟道区部分P11的远离所述第一栅极介质层13的一侧上的第一刻蚀阻挡层14。该第一刻蚀阻挡层14的14E端部位于第一半导体层121和第二半导体层122之间。P型TFT(TFT2)还包括位于第四半导体层221作为沟道区的部分P21(参见图1)的远离第二栅极介质层23的一侧上的第二刻蚀阻挡层24。该第二刻蚀阻挡层24的端部24E位于第四半导体层221和所述第五半导体层222之间。通过蚀刻阻挡层,可以在蚀刻半导体层期间保护TFT的沟道区不被蚀刻。
根据本发明的实施例中,薄膜晶体管可以为底栅结构,如图1和图2所示。第一栅极11、第一栅极介质层13和第一半导体层121可以沿远离衬底01的方向上依次层叠。第二栅极21、第二栅极介质层23和第二半导体层221可以沿远离衬底01的方向上依次层叠。应该理解,根据本公开的实施例,薄膜晶体管也可以为顶栅结构。在该情况下,第一半导体层121、第一栅极介质层13和第一栅极11和可以沿远离衬底01的方向上依次层叠。第二半导体层221、第二栅极介质层2和3第二栅极21可以沿远离衬底01的方向上依次层叠。
图3为根据本发明的实施例的CMOS结构的示意图。如图3所示,第一有源层12具有邻近该P型TFT(TFT2)的第一源/漏极区R1和远离所述P型TFT(TFT2)的第二源/漏极区R2。第二有源层22具有邻近N型TFT(TFT1)的第三源/漏极区R3和远离P型TFT(TFT2)的第四源/漏极区R4。如图3所示,CMOS结构还包括:设置在所述第一源/漏极区R1上的第一源/漏极电极51、设置在所述第二源/漏极区R2上的第二源/漏极电极52、设置在所述第三源/漏极区R3上的第三源/漏极电极53、设置在所述第四源/漏极区R4上的第四源/漏极电极54。第一源/漏极电极51与第三源/漏极电极53连接。
第二半导体层122可以为N型轻掺杂半导体层。例如,第二半导体层122的N型掺杂浓度可以在10
17ions/cm
3~10
19ions/cm
3之间。第三半导体层 123可以为N型重掺杂半导体层。例如,第三半导体层123的N型掺杂浓度可以在10
19ions/cm
3~10
21ions/cm
3之间。
第五半导体层222可以为P型轻掺杂半导体层。例如,第五半导体层222的掺杂浓度可以在10
17ions/cm
3~10
19ions/cm
3之间。第六半导体层223可以为P型重掺杂半导体层。例如,第六半导体层223的P型掺杂浓度可以在10
19ions/cm
3~10
21ions/cm
3之间。
N型TFT(TFT1)和P型TFT(TFT2)通过第一源/漏极电极51和第三源/漏极电极53连接,避免了第三半导体层123和第六半导体层223直接接触实现连接所带来的不希望的势垒,有利于改善CMOS结构的性能。
本发明的实施例还提供了一种CMOS结构的制造方法。根据本发明的实施例的CMOS结构的制造方法包括在衬底上形成N型TFT和P型TFT。
在本发明的实施例中,形成N型TFT包括:形成第一栅极电极11、第一有源层12以及位于第一栅极电极11和第一有源层12之间的第一栅极介质层13。第一有源层12包括第一半导体层121和位于第一半导体层121相对两端(E1,E2)且沿远离第一栅极介质层13的方向上依次层叠的的N型的第二半导体层122和N型的第三半导体层123。其中,第二半导体层122的N型掺杂浓度小于第三半导体层123的N型掺杂浓度。
在本发明的实施例中,形成P型TFT包括:形成第二栅极电极21、第二有源层22以及位于第二栅极电极21和第二有源层22之间的第二栅极介质层23。其中,第二有源层22包括第四半导体层221和位于第四半导体层221的相对两端(E3,E4)的且沿远离第二栅极介质层23的方向上依次层叠的P型的第五半导体层222和P型的第六半导体层223。其中,第五半导体层222的P型掺杂浓度小于第六半导体层223的P型掺杂浓度。
在本发明的实施例中,所述第一半导体层的沟道区P11和第四半导体层的沟道区P12可以包括多晶半导体材料,第一半导体层的源/漏极区域P12和第四半导体层的源/漏极区域P22可以包括非晶半导体材料。多晶半导体材料可以包括多晶硅,非晶半导体材料可以包括非晶硅。
图4为根据本发明的实施例的CMOS结构的制造方法的示意图。如图4所示,在本发明的实施例中,形成第一栅极介质层13和第二栅极介质层23包括在第一栅极电极11和第二栅极电极21上形成栅极介质材料层03。其中,所述栅极材料介质层03的位于第一栅极电极11上的部分构成所述第一栅极介质层13,所述栅极材料介质层03的位于所述第二栅极电极21上的部分构成所述第二栅极介质层23。
在本发明的实施例中,形成所述第一半导体层和所述第二半导体层包括:在所述栅极介质材料层03上形成第一非晶半导体材料层02;将所述第一非晶半导体材料层02的位于第一栅极电极11和第二栅极电极21上的部分转换成多晶半导体材料,以形成第一有源层12的沟道区P11和第二有源层22的沟道区P21。
第一非晶半导体材料层02的厚度可以为500埃米。可以采用激光退火来将非晶半导体材料来转换成多晶半导体材料(即,进行多晶化处理)。例如,可以采用微透镜阵列(Micro Lens Array,MLA)掩模来进行激光退火。MLA退火具有高位置精度的优势。
在本发明的实施例中,CMOS结构的制造方法还可以包括:在第一半导体层的作为沟道区的部分P11上形成第一刻蚀阻挡层14;以及在所述第四半导体层的作为沟道区的部分P21上形成第二刻蚀阻挡层24。
在实施例中,可以在经过多晶化处理的第一非晶半导体材料层02上沉积刻蚀阻挡材料层。然后,对刻蚀阻挡材料层进行刻蚀,以形成第一刻蚀阻挡层14和第二刻蚀阻挡层24。
图5A-5C为根据本发明的实施例的CMOS结构的制造方法的形成第二半导体层和第三半导体层的方法的示意图。如图5A-5C所示,在本发明的实施例中,形成第二半导体层和第三半导体层包括:
S51、在第一半导体层121上形成第二非晶半导体材料层04。例如,可以在第一半导体层上沉积500埃厚度的轻掺杂的N型非晶硅。N型半导体层可以掺杂有磷的五价杂质元素。
S52、在第二非晶半导体材料层122上形成第三非晶半导体材料层05。 例如,可以在第二非晶半导体材料层上沉积500埃厚度的重掺杂的N型非晶硅半导体层。
S53、刻蚀位于所述第一刻蚀阻挡层14上的所述第二非晶半导体材料层04和所述第三非晶半导体材料层05以形成延伸到所述第一刻蚀阻挡层14的第一间隔G1。
图6A-6C为根据本发明的实施例的CMOS结构的制造方法的形成第五半导体层和第六半导体层的方法的示意图。如图6A-6C所示,在本发明的实施例中,形成第五半导体层和所述第六半导体层包括:
S61、在第四半导体层221上形成第五非晶半导体材料层06。例如,可以在第四半导体层上沉积500埃厚度的轻掺杂的P型非晶硅。P型半导体层可以掺杂有诸如硼的三价杂质元素。
S62、在第五非晶半导体材料层06上形成第六非晶半导体材料层07。例如,可以在第五非晶半导体材料层06上沉积500埃厚度的重掺杂的P型非晶硅。
S63、刻蚀位于所述第二刻蚀阻挡层24上的第五非晶半导体材料层06和第六非晶半导体材料层07以形成延伸到所述第二刻蚀阻挡层24的第二间隔G2。
在本发明的实施例中,形成第二非晶半导体材料层、第三非晶半导体材料层、第五非晶半导体材料层和第六非晶半导体材料层包括使用化学气相沉积(CVD)。
图7A-7B为根据本发明的实施例的CMOS结构的制造方法的示意图。如图7A-7B所示,第一有源层12具有邻近P型TFT(TFT2)的第一源/漏极区R1和远离该P型TFT(TFT2)的第二源/漏极区R2。第二有源层22具有邻近所述N型TFT(TFT1)的第三源/漏极区R3和远离所述N型TFT(TFT2)的第四源/漏极区R4。根据本发明的实施例的CMOS结构的制造方法还可以包括:
S71、在第三半导体层123、第六半导体层223、第一栅极介质层13和第二栅极介质层23上形成导电层08。
S73、对所述导电层进行刻蚀,以形成彼此隔离的第一部分08a(51、53)第二部分08b(52)和第三部分08c(54)。如图7B所示,该所述第一部分08a覆盖所述第一源/漏极区R1和所述第三源/漏极区R3,第二部分08b覆盖第二源/漏极区R2,第三部分08c覆盖所述第四源/漏极区R4。
已经描述了某特定实施例,这些实施例仅通过举例的方式展现,而且不旨在限制本发明的范围。事实上,本文所描述的新颖实施例可以以各种其它形式来实施;此外,可在不脱离本发明的精神下,做出以本文所描述的实施例的形式的各种省略、替代和改变。所附权利要求以及它们的等价物旨在覆盖落在本发明范围和精神内的此类形式或者修改。
Claims (20)
- 一种CMOS结构,包括衬底和位于所述衬底上的N型TFT和P型TFT,其中,所述N型TFT包括:第一栅极电极、第一有源层以及位于所述第一栅极电极和所述第一有源层之间的第一栅极介质层,所述第一有源层包括第一半导体层和位于所述第一半导体层相对两端的且沿远离所述第一栅极介质层的方向上依次层叠的N型的第二半导体层和N型的第三半导体层,其中,所述第二半导体层的N型掺杂浓度小于所述第三半导体层的N型掺杂浓度,并且其中,所述P型TFT包括:第二栅极电极、第二有源层以及位于所述第二栅极电极和所述第二有源层之间的第二栅极介质层,其中,所述第二有源层包括第四半导体层和位于所述第四半导体层相对两端的且沿远离所述第二栅极介质层的方向上依次层叠的P型的第五半导体层和P型的第六半导体层,其中,所述第五半导体层的P型掺杂浓度小于所述第六半导体层的P型掺杂浓度。
- 根据权利要求1所述的CMOS结构,其中,至少所述第一半导体层的作为沟道区的部分和所述第四半导体层的作为沟道区的部分包括多晶半导体材料。
- 根据权利要求2所述的CMOS结构,其中,所述第一半导体层的源/漏极区域和所述第四半导体层的源/漏极区域包括非晶半导体材料。
- 根据权利要求3所述的CMOS结构,其中,所述第二半导体层、所述第三半导体层、所述第五半导体层和所述第六半导体层包括所述多晶半导体材料。
- 根据权利要求4所述的CMOS结构,其中,所述多晶半导体材料包括多晶硅,所述非晶半导体材料包括非晶硅。
- 根据权利要求3所述的CMOS结构,其中,所述N型TFT还包括位于所述第一半导体层的作为沟道区部分的远离所述第一栅极介质层的一侧上的第一刻蚀阻挡层,所述第一刻蚀阻挡层的端部位于所述第一半导体层和所述第二半导体层之间,并且其中,所述P型TFT还包括位于所述第四半导体层作为沟道区的部分的远离所述第二栅极介质层的一侧上的第二刻蚀阻挡层,所述第二刻蚀阻挡层的端部位于所述第四半导体层和所述第五半导体层之间。
- 根据权利要求1-6中任一项所述的CMOS结构,其中,所述第一栅极、所述第一栅极介质层和所述第一半导体层沿远离所述衬底的方向上依次层叠,并且其中,所述第二栅极、所述第二栅极介质层和所述第二半导体层沿远离所述衬底的方向上依次层叠。
- 根据权利要求7所述的CMOS结构,其中,所述第一有源层具有邻近所述P型TFT的第一源/漏极区和远离所述P型TFT的第二源/漏极区,所述第二有源层具有邻近所述N型TFT的第三源/漏极区和远离所述P型TFT的第四源/漏极区,所述CMOS结构还包括:设置在所述第一源/漏极区上的第一源/漏极电极;设置在所述第二源/漏极区上的第二源/漏极电极;设置在所述第三源/漏极区上的第三源/漏极电极;设置在所述第四源/漏极区上的第四源/漏极电极,其中,所述第一源/漏极电极与所述第三源/漏极电极连接。
- 一种CMOS结构的制造方法,包括在衬底上形成N型TFT和P型TFT,其中,形成所述N型TFT包括:形成第一栅极电极、第一有源层以及位于所述第一栅极电极和所述第一有源层之间的第一栅极介质层,所述第一有源层包括第一半导体层和位于所述第一半导体层相对两端且沿远离所述第一栅极介质层的方向上依次层叠的的N型的第二半导体层和N型的第三半导体层,其中,所述第二半导体层的N型掺杂浓度小于所述第三半导体层的N型掺杂浓度,并且其中,形成所述P型TFT包括:形成第二栅极电极、第二有源层以及位于所述第二栅极电极和所述第二有源层之间的第二栅极介质层,其中,所述第二有源层包括第四半导体层和位于所述第四半导体层的相对两端的且沿远离所述第二栅极介质层的方向上依次层叠的P型的第五半导体层和P型的第六半导体层,其中, 所述第五半导体层的P型掺杂浓度小于所述第六半导体层的P型掺杂浓度。
- 根据权利要求9所述的CMOS结构的制造方法,其中,至少所述第一半导体层的沟道区和所述第四半导体层的沟道区包括多晶半导体材料,所述第一半导体层的源/漏极区域和所述第四半导体层的源/漏极区域包括非晶半导体材料。
- 根据权利要求10所述的CMOS结构的制造方法,形成所述第一栅极介质层和所述第二栅极介质层包括在所述第一栅极电极和所述第二栅极电极上形成栅极介质材料层,其中,所述栅极材料介质层的位于所述第一栅极电极上的部分构成所述第一栅极介质层,所述栅极材料介质层的位于所述第二栅极电极上的部分构成所述第二栅极介质层。
- 根据权利要求11所述的CMOS结构的制造方法,形成所述第一半导体层和所述第二半导体层包括:在所述栅极介质材料层上形成第一非晶半导体材料;将所述第一非晶半导体材料层的位于所述第一栅极电极和所述第二栅极电极上的部分转换成多晶半导体材料,以形成所述第一有源层的沟道区和所述第二有源层的沟道区。
- 根据权利要求12所述的CMOS结构的制造方法,所述转换包括对所述非晶半导体材料进行激光退火。
- 根据权利要求13所述的CMOS结构的制造方法,所述激光退火包括采用微透镜阵列掩模。
- 根据权利要求9-14所述的CMOS结构的制造方法,还包括:在所述第一半导体层的作为沟道区的部分上形成第一刻蚀阻挡层;以及在所述第四半导体层的作为沟道区的部分上形成第二刻蚀阻挡层。
- 根据权利要求15所述的CMOS结构的制造方法,其中,形成所述第二半导体层和所述第三半导体层包括:在所述第一半导体层上形成第二非晶半导体材料层;在所述第二非晶半导体材料层上形成第三非晶半导体材料层;刻蚀位于所述第一刻蚀阻挡层上的所述第二非晶半导体材料层和所述第三非晶半导体材料层以形成延伸到所述第一刻蚀阻挡层的第一间隔。
- 根据权利要求15所述的CMOS结构的制造方法,形成所述第五半导体层和所述第六半导体层包括:在所述第四半导体层上形成第五非晶半导体材料层;在所述第五非晶半导体材料层上形成第六非晶半导体材料层;刻蚀位于所述第二刻蚀阻挡层上的所述第五非晶半导体材料层和所述第六非晶半导体材料层以形成延伸到所述第二刻蚀阻挡层的第二间隔。
- 根据权利要求16或17所述的CMOS结构的制造方法,形成第二非晶半导体材料层、第三非晶半导体材料层、第五非晶半导体材料层和第六非晶半导体材料层包括使用CVD。
- 根据权利要求16或17所述的CMOS结构的制造方法,所述第一有源层具有邻近所述P型TFT的第一源/漏极区和远离所述P型TFT的第二源/漏极区,所述第二有源层具有邻近所述N型TFT的第三源/漏极区和远离所述N型TFT的第四源/漏极区,所述方法还包括:在所述第三半导体层、所述第六半导体层、所述第一栅极介质层和所述第二栅极介质层上形成导电层;对所述导电层进行刻蚀,以形成彼此隔离的第一部分、第二部分和第三部分,其中,所述第一部分覆盖所述第一源/漏极区和所述第三源/漏极区,所述第二部分覆盖所述第二源/漏极区,所述第三部分覆盖所述第四源/漏极区。
- 根据权利要求18所述的CMOS结构的制造方法,其中,所述多晶半导体材料包括多晶硅,所述非晶半导体材料包括非晶硅。
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