WO2020170617A1 - SEQUENTIAL-COMPARISON-TYPE AD CONVERTER, Iot SENSOR, AND BIOLOGICAL SENSOR - Google Patents

SEQUENTIAL-COMPARISON-TYPE AD CONVERTER, Iot SENSOR, AND BIOLOGICAL SENSOR Download PDF

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Publication number
WO2020170617A1
WO2020170617A1 PCT/JP2020/000063 JP2020000063W WO2020170617A1 WO 2020170617 A1 WO2020170617 A1 WO 2020170617A1 JP 2020000063 W JP2020000063 W JP 2020000063W WO 2020170617 A1 WO2020170617 A1 WO 2020170617A1
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Prior art keywords
capacitor
polarity
charge
integrated value
switch
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PCT/JP2020/000063
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French (fr)
Japanese (ja)
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一徳 長谷部
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ソニーセミコンダクタソリューションズ株式会社
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Priority to JP2021501660A priority Critical patent/JP7512246B2/en
Publication of WO2020170617A1 publication Critical patent/WO2020170617A1/en

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    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/40—Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type

Definitions

  • the present technology relates to a successive approximation type AD converter, an Iot sensor, and a biometric sensor.
  • SAR ADC Successessive Application Register Analog Analog Converter
  • noise shaping is a technique for reducing quantization noise and comparator noise.
  • SNDR Signal to noise and distortion
  • Non-Patent Document 1 a simple and extremely efficient SAR ADC has been proposed (for example, Non-Patent Document 1).
  • SAR ADC unlike ⁇ ADC, is not suitable for increasing the order of noise shaping, so there is a limit to the accuracy of SNDR that can be achieved.
  • the present technology has been made in view of such a situation, and its main purpose is to provide a successive approximation type AD converter, an Iot sensor, and a biometric sensor that can achieve higher-order noise shaping.
  • the present inventor succeeded in providing a successive approximation type AD converter, an Iot sensor, and a biosensor capable of achieving higher-order noise shaping. , Has come to complete this technology.
  • Each of the first capacitor of the first polarity, the second capacitor of the first polarity, and the third capacitor of the first polarity has substantially the same capacitance
  • the first capacitor having the second polarity, the second capacitor having the second polarity, and the third capacitor having the second polarity have substantially the same capacitance
  • a predetermined charge is accumulated in each of the first capacitor of the first polarity and the first capacitor of the second polarity
  • the second capacitor of the first polarity accumulates the first charge of the input analog voltage and transfers the first charge to the third capacitor of the first polarity
  • the integrator amplifier integrates the first charge transferred to the third capacitor of the first polarity to generate a first integrated value
  • the first polarity may be positive and the second polarity may be negative.
  • the comparator compares the first integral value and the second integral value with respect to the least significant bit of the predetermined resolution, and the second capacitor of the first polarity is used. After the resetting of the second capacitor of the second polarity and before the redistribution of the second capacitor of the first polarity and the second capacitor of the second polarity is completed, the filter circuit is Sampling of the residual voltage may be started.
  • the filter circuit may be driven by the integrator amplifier.
  • the filter circuit may be an active type including an operational amplifier.
  • the filter circuit may be a passive type that includes a capacitor and does not include an operational amplifier.
  • the present technology also provides an IoT sensor including the successive approximation type AD converter.
  • the present technology provides a biometric sensor including the successive approximation type AD converter.
  • the successive approximation type AD converter, the Iot sensor, and the biometric sensor can realize higher-order noise shaping.
  • the effect of the present technology is not necessarily limited to the above effect, and may be any effect described in the present technology.
  • 9 is a timing chart showing the timing at which the Charge Share SAR ADC according to the first embodiment of the present technology turns on the switch. It is a figure showing the noise behavior model of Charge Share SAR ADC of a 1st embodiment concerning this art.
  • It is a circuit diagram in case Charge Charge SAR ADC of a 1st embodiment concerning this art has a filter circuit. It is explanatory drawing shown that the quantization noise located in a low frequency band is moved to a high frequency band by noise shaping. It is an explanatory view showing that the effect of noise shaping becomes high if the order becomes high.
  • FIG. 11 A general SAR ADC (Successive Application Register Analog Digital Converter) is shown in FIG. 11 is a circuit diagram in which a filter circuit FLT1 for executing noise shaping is added to the conventionally known Charge Redistribution SAR ADC.
  • the Charge Redistribution SAR ADC 101 shown in FIG. 11 includes a plurality of capacitors CP0 to CP6 (capacitor CP0, capacitor CP1,... Capacitor CP2, capacitor CP3, capacitor CP4, capacitor CP5, and capacitor CP6), and switches SW1 to SW1.
  • SW7 switch SW1, switch SW2,... Switch SW3, switch SW4, switch SW5, switch SW6, and switch SW7, a filter circuit FLT1, and a comparator CMP1.
  • the plurality of capacitors CP0 to CP6 included in the Charge Redistribution SAR ADC 101 form a capacitance array and have a binary weight configuration. Also, the Charge Redistribution SAR ADC 101 is implemented as a fully differential circuit, but here, for the sake of simplicity of explanation, it is configured as a single end.
  • the binary weight is a set of weights (capacity values) forming a geometric progression with a common ratio of 2.
  • the Charge Redistribution SAR ADC 101 can give the noise transfer function (NTF) a high-pass characteristic by inputting the residual voltage after successive approximation conversion to the filter circuit FLT1.
  • the Charge Redistribution SAR ADC 101 shown in FIG. 11 implements the filter circuit FLT1 shown in FIG. 12 as an example.
  • FIG. 12(A) shows a filter circuit FLT1 implemented in the Charge Redistribution SAR ADC 101. Further, FIG. 12B shows switching timings of the switch ⁇ 7 to the switch ⁇ 12 (the switch ⁇ 7a to the switch ⁇ 12a and the switch ⁇ 7b to the switch ⁇ 12b) included in the filter circuit FLT1.
  • the filter circuit FLT1 shown in FIG. 12A includes a buffer Abuf, a capacitor C41a, a capacitor C42a, a capacitor C43a, a capacitor C41b, a capacitor C42b, a capacitor C43b, a capacitor C5a, a capacitor C5b, a switch ⁇ 7 to a switch ⁇ 12 (a switch ⁇ 7a to a switch ⁇ 12a, and The switch ⁇ 7b to the switch ⁇ 12b) and the integrator amplifier IPF.
  • the capacitors C41a and C41b have substantially the same capacitance.
  • the substantially equal capacities are, for example, capacities that include the same capacity value and are within 95% to 105% of the same capacity value.
  • the capacitors C42a and C43a have a capacitance that is approximately 1/3 of that of the capacitor C41a. Further, the capacitors C42b and C43b have a capacitance that is approximately 1 ⁇ 3 of that of the capacitor C41b.
  • the capacity of about 1/3 means a capacity value including a capacity value of 1/3 and within 95% to 105% of the capacity value of 1/3.
  • FIG. 13 shows a noise behavior model of the Charge Redistribution SAR ADC 101 in this case.
  • FIG. 13 is a diagram showing a noise behavior model of Charge Redistribution SAR ADC 101.
  • the noise behavior model indicates the input/output characteristics of noise.
  • the noise behavior model of the Charge Redistribution SAR ADC 101 includes a subtractor SB1, a filter circuit FLT1, an adder AD1, and a SAR quantizer SQ1. Then, the noise transfer function NTF(z) of the Charge Redistribution SAR ADC 101 is expressed by the following equation (equation (2)).
  • the noise transfer function NTF(z) shown in Expression (2) has a first-order high-pass characteristic. Therefore, high-order Noise Shaping can be realized by making the transfer function L(z) of the filter circuit FLT1 complicated, but in the design of the Charge Redistribution SAR ADC 101, the occupied area, power consumption, and design difficulty are high. Etc. will increase.
  • the reference voltage in order for the Charge Redistribution SAR ADC 101 to obtain a high SNDR, the reference voltage must be stabilized.
  • ⁇ In order to stabilize the reference voltage it is common to improve the performance of the buffer amplifier that generates the reference voltage or to mount multiple capacitors to suppress voltage fluctuations. However, if the performance of the buffer amplifier is increased, or if a plurality of capacitors are mounted, the power consumption and the occupied area increase.
  • FIG. 14 shows the Charge Share SAR ADC 102 configured with a single end.
  • FIG. 14 is a circuit diagram showing the configuration of the Charge Share SAR ADC 102. Note that in FIG. 14, the Charge Share SAR ADC 102 is configured as a single end in order to simplify the description of the operation of the Charge Share SAR ADC.
  • the Charge Share SAR ADC 102 shown in FIG. 14 is a switch ⁇ 1x, a switch ⁇ 1y, a switch ⁇ 1z, a switch ⁇ 2, a switch ⁇ 3, a switch ⁇ 4, a capacitor C1P, a capacitor C1N, a capacitor C2, a capacitor C3, an integrator amplifier IP1, and a comparator CMP2. It is configured with.
  • FIG. 15 is a flowchart for explaining the operation of the Charge Share SAR ADC 102.
  • FIG. 16 shows the state of the circuit of the Charge Share SAR ADC 102 at the time of sampling (step S001).
  • the switch ⁇ 1x, the switch ⁇ 1y, the switch ⁇ 1z, and the switch ⁇ 2 are turned on (closed), and the voltage Vip, the voltage Vrefp, and the voltage Vrefn are sampled.
  • each charge of the capacitor C1P, the capacitor C1N, the capacitor C2, and the capacitor C3 is expressed by the following equations (Equations (3) to (6)).
  • FIG. 17 shows the state of total charge transfer (step S003).
  • the switch ⁇ 1x, the switch ⁇ 1y, the switch ⁇ 1z, and the switch ⁇ 2 are off (open), and the switches ⁇ 3 and ⁇ 4 are on (closed).
  • the electric charge Q2 stored in the capacitor C2 is transferred to the capacitor C3.
  • FIG. 18 shows the state of comparison judgment & C2 reset (step S005).
  • the Charge Share SAR ADC 102 turns off (opens) the switch ⁇ 4 and compares the integrated value of the charge Q3 with the ground potential in the comparator CMP2, and simultaneously turns on the switches ⁇ 2 and ⁇ 3 (closes them). ), and reset the capacitor C2.
  • the comparator CMP2 outputs the determination result D or the determination result DN as a result of comparing the integrated value of the charge Q3 and the ground potential.
  • FIG. 19 shows the state of comparison result feedback (step S007).
  • the Charge Share SAR ADC 102 outputs the determination result D in the comparator CMP2.
  • the switch D ⁇ 5 is turned on (closed).
  • step S009 The state of charge redistribution (step S009) is shown in FIG. In FIG. 20, the Charge Share SAR ADC 102 redistributes the charge Q1P of the capacitor C1P and the charge Q3 of the capacitor C3 in the capacitor C2.
  • the charge Q1P of the capacitor C1P is halved, and the voltage Vo in the formula (12) is the same voltage as the Charge Redistribution SAR ADC 101. Therefore, when the resolution is set to N bits in step 011 of FIG. 15 and the predetermined N-bit resolution is not obtained (No in step S011), the process returns to the comparison determination & C2 reset in step S005, and the steps from step S005 to step S005. By repeating S009, the resolution after (MSB-1) bit is acquired.
  • This active Charge Share SAR ADC 102 holds the previous SAR ADC conversion residual voltage in the capacitor C3, so that the noise transfer function has a first-order high-pass characteristic.
  • the transfer function L(z) of the capacitor C3 and the integrator amplifier IP1 is expressed by the following equation (equation (13)).
  • FIG. 21 shows the behavior model of the Charge Share SAR ADC 102 in this case.
  • FIG. 21 shows a noise behavior model of the Charge Share SAR ADC 102.
  • the Charge Share SAR ADC 102 shown in FIG. 21 includes a subtractor SB1, an integrator ITG1, an adder AD1, and a SAR quantizer SQ2. Then, the noise transfer function NTF(z) of the Charge Share SAR ADC 102 is expressed by the following equation (Equation (14)).
  • a Charge Share SAR ADC that can achieve higher-order noise shaping is provided.
  • the Charge Share SAR ADC can realize a high SNDR.
  • the successive approximation type AD converter according to the first embodiment of the present technology is a first capacitor having a first polarity, a second capacitor having a first polarity, a third capacitor having a first polarity, and a first capacitor having a second polarity.
  • a capacitor, a second capacitor having a second polarity, a third capacitor having a second polarity, an integrator amplifier, a comparator, and a filter circuit are provided.
  • the first capacitor having the first polarity, the second capacitor having the first polarity, and the third capacitor having the first polarity have substantially the same capacitance.
  • the first capacitor of the second polarity, the second capacitor of the second polarity, and the third capacitor of the second polarity have substantially the same capacitance.
  • a predetermined charge is accumulated in each of the first capacitor of the first polarity and the first capacitor of the second polarity.
  • the second capacitor of the first polarity stores the first charge of the input analog voltage and transfers the first charge to the third capacitor of the first polarity.
  • An integrator amplifier integrates the first charge transferred to the third capacitor of the first polarity to generate a first integrated value.
  • the second capacitor of the second polarity stores the second electric charge of the input analog voltage and transfers the second electric charge to the third capacitor of the second polarity.
  • An integrator amplifier integrates the second electric charge transferred to the third capacitor of the second polarity to generate a second integrated value.
  • the comparator compares the first integral value and the second integral value.
  • the second capacitor having the first polarity and the second capacitor having the second polarity are reset.
  • the charges accumulated in the third capacitor of the first polarity and the charges accumulated in the first capacitor of the first polarity are reset to the first polarity.
  • the charge accumulated in the third capacitor of the second polarity and the charge accumulated in the first capacitor of the second polarity are redistributed to the reset second capacitor of the second polarity. To do.
  • the electric charge accumulated in the third capacitor of the first polarity and the electric charge accumulated in the first capacitor of the second polarity are reset. While redistributing to the second capacitor of the first polarity, the charge accumulated in the third capacitor of the second polarity and the charge accumulated in the first capacitor of the first polarity are reset to the second capacitor of the second polarity. Redistribute to 2 capacitors.
  • the comparator compares the first integrated value and the second integrated value until the number of bits of a predetermined resolution is obtained, and the second capacitor of the first polarity and the second capacitor of the second polarity are reset. And redistribute to the reset second capacitors of the first polarity and the second capacitors of the second polarity are repeated.
  • the charge accumulated in the third capacitor of the first polarity by redistributing to the second capacitor of the first polarity and the second capacitor of the second polarity are redistributed in the filter circuit.
  • This is a successive approximation type AD converter that inputs the electric charges that are redistributed and accumulated in the third capacitor of the second polarity as a residual voltage.
  • FIG. 1 shows a Charge Share SAR ADC 100 that is an example of a successive approximation type AD converter according to the first embodiment of the present technology.
  • FIG. 1 is a block diagram showing a configuration example of a Charge Share SAR ADC 100 to which the present technology is applied.
  • the same components as those described above are designated by the same reference numerals, and description thereof will be omitted as appropriate.
  • the Charge Share SAR ADC 100 includes a first capacitor C1a having a first polarity, a second capacitor C2a having a first polarity, and a third capacitor C3a having a first polarity.
  • the first polarity is positive and the second polarity is negative.
  • the integrator ITG includes a switch ⁇ RESTa, a third capacitor having a first polarity, an integrator amplifier IP, a third capacitor C3b having a second polarity, and a switch ⁇ RESTb.
  • the Charge Share SAR ADC 100 performs an initial reset operation. After performing the initial reset operation, the Charge Share SAR ADC 100 turns off (opens) all the switches ⁇ . Note that the switch ⁇ RESTa and the switch ⁇ RESTb are kept off (open) until the Charge Share SAR ADC 100 is reset again after being turned off (after opening) by releasing the initial reset.
  • the Charge Share SAR ADC 100 turns on (closes) the switch ⁇ 1a1, the switch ⁇ 1a2, the switch ⁇ 2a, the switch ⁇ 1b2, and the switch ⁇ 2b, and the voltage Vip and the voltage Vip.
  • the voltages Vrefp, Vrefn, and Vin are sampled.
  • a predetermined charge is accumulated in each of the first capacitor C1a having the first polarity, the first capacitor C1b having the second polarity, the second capacitor C2a having the first polarity, and the second capacitor C2b having the second polarity. It The second capacitor C2a of the first polarity stores the first charge of the input analog voltage, and the second capacitor C2b of the second polarity stores the second charge of the input analog voltage. ..
  • Q1a C1a ⁇ Vrep (15)
  • Q1b C1b ⁇ Vren (16)
  • Q2a C2a ⁇ Vip (17)
  • Q2b C2b ⁇ Vin (18)
  • the Charge Share SAR ADC 100 turns off (opens) the switch ⁇ 1a1, the switch ⁇ 1a2, the switch ⁇ 2a, the switch ⁇ 1b1, the switch ⁇ 1b2, and the switch ⁇ 3a and the switch ⁇ 4a.
  • Switch ⁇ 3b and switch ⁇ 4b are turned on (closed).
  • the first charge stored in the second capacitor C2a of the first polarity is fully transferred to the third capacitor C3a of the first polarity and is stored in the second capacitor C2b of the second polarity.
  • the second charge is completely transferred to the third capacitor C3b having the second polarity.
  • the Charge Share SAR ADC 100 integrates the first charge transferred to the third capacitor C3a of the first polarity by the integrator amplifier IP to obtain the first integrated value.
  • the second charge generated and transferred to the third capacitor C3b of the second polarity is integrated to generate a second integrated value.
  • the comparator CMP compares the first integral value and the second integral value, and outputs the determination result D or the determination result DN as the comparison result.
  • the second capacitor C2a having the first polarity and the second capacitor C2b having the second polarity are reset.
  • step S007 it is assumed that the Charge Share SAR ADC 100 outputs the determination result D indicating that the first integrated value is larger than the second integrated value by the comparator CMP. In this case, the Charge Share SAR ADC 100 turns on (closes) the switch D ⁇ 5a and the switch D ⁇ 5b.
  • the Charge Share SAR ADC 100 resets the charge accumulated in the third capacitor C3a of the first polarity and the charge accumulated in the first capacitor C1a of the first polarity to the first reset state. It is redistributed to the polar second capacitor C2a. At the same time, the Charge Share SAR ADC 100 transfers the electric charge accumulated in the second capacitor C3b of the second polarity and the electric charge accumulated in the first capacitor C1b of the second polarity to the second capacitor C2b of the second polarity reset. Redistribute.
  • the first capacitor C1a having the first polarity, the second capacitor C2a having the first polarity, the third capacitor C3a having the first polarity, the first capacitor C1b having the second polarity, the second capacitor C2b having the second polarity, and the second capacitor C2b The respective charges of the third capacitor C3b having the polarity are expressed by the following formulas (formula (23) to formula (30)).
  • step S007 it is assumed that the Charge Share SAR ADC 100 outputs the determination result DN indicating that the first integrated value is substantially equal to or less than the second integrated value by the comparator CMP. To do. In this case, the Charge Share SAR ADC 100 turns on (closes) the switch DN ⁇ 5a and the switch DN ⁇ 5b.
  • the Charge Share SAR ADC 100 resets the charge accumulated in the third capacitor C3a of the first polarity and the charge accumulated in the first capacitor C1b of the second polarity to the first reset state. It is redistributed to the polar second capacitor C2a. At the same time, the Charge Share SAR ADC 100 transfers the charge accumulated in the third capacitor C3b of the second polarity and the charge accumulated in the first capacitor C1a of the first polarity to the second capacitor C2b of the reset second polarity. Redistribute.
  • the respective charges of the third capacitor C3b are expressed by the following formulas (formula (31) to formula (38)).
  • the comparator CMP compares the first integrated value and the second integrated value (Yes in step S005) until the number of bits with a predetermined resolution is obtained (step S011).
  • the second capacitor C2a and the second capacitor C2b having the second polarity are reset (step S005), and the redistributed to the reset second capacitor C2a having the first polarity and the second capacitor C2b having the second polarity. This is repeated (step S007 and step S009) (step S013).
  • the Charge Share SAR ADC 100 acquires the resolution after (MSB-1) bit by repeating steps S005 to S009.
  • the Charge Share SAR ADC 100 after obtaining the number of bits of the predetermined resolution, is redistributed to the second capacitor C2a of the first polarity and accumulated in the third capacitor C3a of the first polarity in the filter circuit FLT.
  • the charges and the charges redistributed to the second capacitor C2b of the second polarity and accumulated in the third capacitor C3b of the second polarity are input as the residual voltage.
  • FIG. 2 is a timing chart showing a timing at which the Charge Share SAR ADC 100 according to the first embodiment of the present technology turns on (closes) the switch ⁇ 6 (the switch ⁇ 6a and the switch ⁇ 6b).
  • the switch ⁇ 6 (the switch ⁇ 6a and the switch ⁇ 6b) feeds back the determination result of the least significant bit with a predetermined resolution to the Charge Share SAR ADC 100, and turns on (closes) before and after the timing of charge redistribution.
  • the Charge Share SAR ADC 100 turns on (closes) the switch ⁇ 6 (switch ⁇ 6a and switch ⁇ 6b) when the residual voltage after the redistribution of the least significant bit is sampled by the filter circuit FLT.
  • the comparator CMP compares the first integrated value and the second integrated value, and the second capacitor C2a of the first polarity and the second capacitor C2a of the second polarity. After the capacitor C2b is reset and before the redistribution of the second capacitor C2a of the first polarity and the second capacitor C2b of the second polarity is completed, the filter circuit FLT samples the residual voltage. Indicates that it is about to start.
  • the switch ⁇ 6 turns on (closes) the switch ⁇ 2 (switch ⁇ 2a and switch ⁇ 2b) and switch ⁇ 3 (switch ⁇ 3a and switch ⁇ 3b) for the least significant bit (LSB bit) of a predetermined resolution. Then, after the second capacitor C2a having the first polarity and the second capacitor C2b having the second polarity are reset, the switch ⁇ 4 (the switch ⁇ 4a and the switch ⁇ 4b) must be turned on (by opening) before being turned off. All you have to do is close it.
  • the integrator amplifier IP plays the role of a buffer for the input of the filter circuit FLT, there is a degree of freedom in the timing of turning on (closing) the switch ⁇ 6 (switch ⁇ 6a and switch ⁇ 6b). Therefore, in consideration of the voltage resolution and the amplifier buffering ability, the timing (close timing) for turning on the switch ⁇ 6 (switch ⁇ 6a and switch ⁇ 6b) can be optimized so that the settling becomes shortest.
  • FIG. 3 shows a behavior model of the Charge Share SAR ADC 100 shown in FIG.
  • FIG. 3 is a diagram showing a noise behavior model of the Charge Share SAR ADC 100 according to the first embodiment of the present technology.
  • the noise behavior model of the Charge Share SAR ADC 100 includes a subtractor SB, an integrator ITG, a filter circuit FLT, an adder AD, and a SAR quantizer SQ. Then, the noise transfer function NTF(z) of the Charge Share SAR ADC 100 is expressed by the following equation (equation (39)).
  • the Charge Share SAR ADC 100 can increase the order of noise shaping.
  • the transfer function L 1 (z) of the integrator ITG is the same as the expression (13).
  • the filter circuit FLT some embodiments are assumed.
  • the circuit topology of the filter circuit FLT is to directly apply the filter circuit FLT1 implemented in the Charge Redistribution SAR ADC shown in FIG.
  • the Charge Share SAR ADC 100 constitutes an active Charge Share SAR ADC in which the filter circuit FLT1 includes an operational amplifier (integrator amplifier IPF).
  • FIG. 4 is a circuit diagram in the case where the Charge Share SAR ADC 100 according to the first embodiment of the present technology has the filter circuit FLT1 shown in FIG.
  • the transfer function L 2 (z) and the noise transfer function NTF(z) of the filter circuit FLT1 in this case are represented by the following expressions (Expression (40) and Expression (41)).
  • FIG. 5 is an explanatory diagram showing that quantization noise located in a low frequency band is moved to a high frequency band by noise shaping.
  • the noise shaping can reduce the quantization noise and the comparator noise that are uniformly distributed in the frequency band in the low frequency band and increase them in the high frequency band. Note that FIG. 5 shows first-order noise shaping.
  • FIG. 6 is an explanatory diagram showing that the effect of noise shaping becomes higher as the order becomes higher.
  • the order is “q”.
  • the noise transfer function represented by the first order can be increased in order, the effect of removing noise can be enhanced.
  • the secondary can be achieved, more noise components (noise components) can be moved to the high frequency band than in the case of the primary, so a low-pass filter is applied to the output of the Charge Share SAR ADC 100.
  • the noise component (noise component) can be cut by applying.
  • the integrator ITG can be diverted for noise shaping, so that the noise shaping can be performed by one integrator amplifier IPF included in the filter circuit FLT.
  • the Charge Share SAR ADC 100 can remove a noise component (noise component) with high accuracy.
  • the successive approximation type AD converter according to the second embodiment of the present technology is a successive approximation type AD converter in which a filter circuit is driven by an integrator amplifier.
  • FIG. 7 shows a Charge Share SAR ADC 100a that is an example of a successive approximation type AD converter according to the second embodiment of the present technology.
  • FIG. 7 is a block diagram showing a configuration example of the Charge Share SAR ADC 100a to which the present technology is applied.
  • the same components as those described above are designated by the same reference numerals, and description thereof will be omitted as appropriate. Unless otherwise specified, “left” means the left direction in FIG. 7, and “up” means the upper direction in FIG. 7.
  • the Charge Share SAR ADC 100a of the second embodiment shown in FIG. 7 differs from the Charge Share SAR ADC 100 of the first embodiment shown in FIG. 1 in that the filter circuit FLT2 is a buffer Abuf and a switch ⁇ 6. (Switch ⁇ 6a and switch ⁇ 6b) is not provided.
  • the integrator amplifier IP functions as a buffer for the input of the filter circuit FLT2
  • the input buffer in the filter circuit FLT2 can be deleted.
  • the switches ⁇ 7 to ⁇ 12 switches ⁇ 7a to ⁇ 12a and switches ⁇ 7b to ⁇ 12b located on the left side of the sampling capacitors (capacitors C5a and C5b) in the filter circuit FLT2 can be used as sampling switches.
  • the switch ⁇ 6 switch ⁇ 6a and switch ⁇ 6b
  • the transfer function L 2 (z) and the noise transfer function NTF(z) of the filter circuit FLT2 in this case are represented by the following expressions (Expression (42) and Expression (43)).
  • the Charge Share SAR ADC 100a As shown in equation (43), the numerator (1-z ⁇ 1 ) 2 of the noise transfer function NTF(z) is maintained. As a result, the Charge Share SAR ADC 100a according to the second embodiment of the present technology can maintain the order of noise shaping at a high order.
  • the successive approximation type AD converter according to the third embodiment of the present technology is a successive approximation type AD converter in which the filter circuit includes a capacitor and does not include an operational amplifier.
  • FIG. 8 shows a Charge Share SAR ADC 100b that is an example of the successive approximation type AD converter according to the third embodiment of the present technology.
  • FIG. 8 is a block diagram showing a configuration example of the Charge Share SAR ADC 100b to which the present technology is applied.
  • the same components as those described above are designated by the same reference numerals, and description thereof will be omitted as appropriate. Unless otherwise specified, “left” means leftward in FIG. 8 and “upper” means upward in FIG. 8.
  • the difference between the Charge Share SAR ADC 100b of the third embodiment shown in FIG. 8 and the Charge Share SAR ADC 100 of the first embodiment shown in FIG. 1 is that the filter circuit FLT3 is a capacitor (capacitor CAa, capacitor). CAb, capacitor CBa, and capacitor CBb) are included and the operational amplifier is not included.
  • FIG. 8A shows a circuit diagram of the Charge Share SAR ADC 100b of the third embodiment
  • FIG. 8B shows a circuit diagram of the filter circuit FLT3
  • FIG. 8C shows a timing chart of the filter circuit FLT3.
  • the filter circuit FLT3 of the Charge Share SAR ADC 100b is configured to include a capacitor CAa, a capacitor CAb, a capacitor CBa, a capacitor CBb, a switch ⁇ 13 (switch ⁇ 13a and switch ⁇ 13b), and a switch ⁇ 14 (switch ⁇ 14a and switch ⁇ 14b).
  • the filter circuit FLT1 of the Charge Redistribution SAR ADC 101 shown in FIG. 11 is a passive type
  • charge redistribution occurs in the capacitance array (capacitors CP0 to CP6) and the capacitance of the filter circuit FLT1. .. Therefore, in the Charge Redistribution SAR ADC 101, the residual voltage after SAR ADC conversion is attenuated.
  • the integrator amplifier IP serves as a buffer for the input of the filter circuit FLT3, the residual voltage after SAR ADC conversion is attenuated. There is nothing to do. Specifically, since charge redistribution does not occur between the third capacitor C3a of the first polarity and the third capacitor C3b of the second polarity, and the capacitors CAa and CAb, the residual voltage after SAR ADC conversion is attenuated. There is no.
  • the SNDR of the Charge Share SAR ADC 100b according to the third embodiment of the present technology has a more advantageous value than the circuit configuration of the conventional Charge Redistribution SAR ADC 101. Further, in the Charge Share SAR ADC 100b of the third embodiment, the sampling of the filter circuit FLT3 does not depend on the charge redistribution, so that the capacitors CAa and CAb can be reduced within the range where the noise required specifications are satisfied.
  • the transfer function L 2 (z) and the noise transfer function NTF(z) of the filter circuit FLT3 in this case are represented by the following expressions (Expression (44) and Expression (45)).
  • the transfer function L 2 (z) of the filter circuit FLT3 is a first-order passive type, and the noise transfer function NTF(z) is near second-order noise shaping. The characteristics can be obtained.
  • the IoT (Internet of Things) sensor of the fourth embodiment according to the present technology is equipped with a successive approximation type AD converter, and the successive approximation type AD converter includes a first capacitor having a first polarity and a first capacitor having a first polarity. 2 capacitors, 1st polarity 3rd capacitor, 2nd polarity 1st capacitor, 2nd polarity 2nd capacitor, 2nd polarity 3rd capacitor, integrator amplifier, comparator, and filter circuit And IoT sensor. Further, the IoT sensor of the fourth embodiment according to the present technology may be an IoT sensor equipped with any one of the successive approximation type AD converters of the first to third embodiments of the present technology.
  • FIG. 9 shows a schematic configuration of the IoT sensor 200 as an example.
  • FIG. 9 is a block diagram showing a configuration example of an IoT sensor to which the present technology is applied.
  • the IoT sensor 200 includes a sensor element S1, a sensor element S2... A sensor element SN, a MUX (Multiplexer) 210, a PGA AMP (Programmable Gain Amplifier) 220, and a Charge Share SAR ADC 100 ( In FIG. 9, it is represented as ADC 100.), a signal processing block 230, an RF 240, an antenna 250, an LCD driver 260, a display 270, a Power Management 280, and a power supply 290.
  • the IoT sensor 200 has a large number of sensor elements (sensor element S1, sensor element S2... Sensor element SN).
  • the IoT sensor 200 can include a plurality of sensor elements as sensor elements, for example, the sensor element S1 is an acceleration sensor and the sensor element S2 is a gyro sensor. Further, as other sensors, a magnetic sensor, a temperature sensor, an atmospheric pressure sensor, a pressure sensitive sensor, etc. may be provided.
  • the MUX 210 is a multiplexer that selects from data (analog signals) acquired by a plurality of sensors (sensor element S1, sensor element S2... Sensor element SN).
  • the PGA AMP 220 is an amplifier that can adjust the gain required by the user.
  • the Charge Share SAR ADC 100 (ADC 100 in FIG. 9) is the successive approximation type AD converter described in the first embodiment according to the present technology.
  • the signal processing block 230 is a signal processing unit configured with a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), and the like, and processes data (digital signals).
  • DSP Digital Signal Processor
  • FPGA Field Programmable Gate Array
  • RF (Radio Frequency) 240 is a wireless circuit that performs wireless communication at a high frequency.
  • the RF 240 transmits the signal (digital signal) processed by the signal processing block 230 to the communication terminal (not shown) via the antenna 250.
  • the LCD Driver 260 is a module that drives a display 270 including, for example, a liquid crystal display.
  • the LCD Driver 260 causes the display 260 to display the signal processed by the signal processing block 230.
  • the Power Management 280 supplies the power supplied from the power supply 290 to the signal processing block 230.
  • the IoT sensor 200 Since the IoT sensor 200 has such a configuration, the IoT sensor 200 converts data (analog signal) acquired by a large number of sensor elements (sensor element S1, sensor element S2... It is possible to execute the signal processing of (1) and send it to a communication terminal (not shown).
  • the fourth embodiment according to the present technology is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present technology.
  • a biosensor according to a fifth embodiment of the present technology is equipped with a successive approximation type AD converter, and the successive approximation type AD converter includes a first capacitor having a first polarity, a second capacitor having a first polarity, and a second capacitor.
  • the biosensor of the fifth embodiment according to the present technology may be a biosensor equipped with any one of the successive approximation AD converters of the first to third embodiments of the present technology.
  • FIG. 10 shows a schematic configuration of the biosensor 300 as an example thereof.
  • FIG. 10 is a block diagram showing a configuration example of a biosensor 300 to which the present technology is applied.
  • the same components as those of the IoT sensor shown in FIG. 9 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.
  • the difference between the biosensor 00 of the fifth embodiment shown in FIG. 10 and the IoT sensor 200 of the fourth embodiment shown in FIG. 9 is that the PGA AMP 220 is replaced by an Analog Front-End 310, The data processed by the signal processing block 230 is output from the Serial I/F 330 to an information processing terminal (not shown).
  • the Analog Front-End 310 includes an amplifier and a filter, and has a function of adjusting data (analog signal) detected by the sensor elements (sensor element S1, sensor element S2... Sensor element SN). There is.
  • the sensor element S1 detects the body temperature and the sensor element S2 detects the heart rate. Then, the biological sensor 300 adjusts the detected body temperature and heart rate by the Analog Front-End 310, and performs signal processing in the signal processing block 230. Then, the biometric sensor 300 outputs the signal-processed body temperature and heart rate to the information processing terminal (not shown) via the Serial I/F 330.
  • first to fifth embodiments according to the present technology are not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist of the present technology.
  • the present technology may have the following configurations. (1) a first capacitor of a first polarity, A second capacitor of the first polarity, A third capacitor of the first polarity, A first capacitor of the second polarity, A second capacitor of the second polarity, A second capacitor of the second polarity, An integrator amplifier, A comparator, And a filter circuit, Each of the first capacitor of the first polarity, the second capacitor of the first polarity, and the third capacitor of the first polarity has substantially the same capacitance, The first capacitor having the second polarity, the second capacitor having the second polarity, and the third capacitor having the second polarity have substantially the same capacitance, A predetermined charge is accumulated in each of the first capacitor of the first polarity and the first capacitor of the second polarity, The second capacitor of the first polarity accumulates the first charge of the input analog voltage and transfers the first charge to the third capacitor of the first polarity, The integrator amplifier integrates the first charge transferred to the third capacitor of the first polarity to generate
  • the filter circuit After the number of bits of the predetermined resolution is obtained, in the filter circuit, the charge redistributed to the second capacitor of the first polarity and accumulated in the third capacitor of the first polarity, and the second capacitor A successive-approximation-type AD converter that inputs the electric charges accumulated in the third capacitor having the second polarity by being redistributed to the second capacitor having the polarity as a residual voltage.
  • the first polarity is a positive polarity
  • the comparator compares the first integrated value and the second integrated value, and the second capacitor of the first polarity and the second capacitor of the second polarity. After the resetting is performed, the filter circuit starts sampling the residual voltage until the reallocation of the second capacitor of the first polarity and the second capacitor of the second polarity is completed.
  • the successive approximation type AD converter according to (1) or (2) above.

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Abstract

The present invention provides a Charge Share SAR ADC with which it is possible to raise the order of noise shaping.　This sequential-comparison-type AD converter comprises a first-polarity first capacitor, a first-polarity second capacitor, a first-polarity third capacitor, a second-polarity first capacitor, a second-polarity second capacitor, a second-polarity third capacitor, an integrator amplifier, a comparator, and a filter circuit. The integrator amplifier generates a first integrated value and a second integrated value. The comparator compares the first integrated value and the second integrated value, and, on the basis of the comparison result, redistributes a charge accumulated in the first-polarity third capacitor and a charge accumulated in the second-polarity third capacitor to the first-polarity second capacitor or the second-polarity second capacitor. After the redistribution is repeated, the charge accumulated in the first-polarity third capacitor and the charge accumulated in the second-polarity third capacitor are inputted as residual voltage into the filter circuit.

Description

逐次比較型ＡＤコンバータ、Ｉｏｔセンサ、及び生体センサSuccessive Approximation Type AD Converter, Iot Sensor, and Biometric Sensor
　本技術は、逐次比較型ＡＤコンバータ、Ｉｏｔセンサ、及び生体センサに関する。 The present technology relates to a successive approximation type AD converter, an Iot sensor, and a biometric sensor.
　従来、ＳＡＲ　ＡＤＣ（Ｓｕｃｃｅｓｓｉｖｅ　Ａｐｐｒｏｘｉｍａｔｉｏｎ　Ｒｅｓｉｓｔｅｒ　Ａｎａｌｏｇ　Ｄｉｇｉｔａｌ　Ｃｏｎｖｅｒｔｅｒ：逐次比較型ＡＤ変換器）が知られている。ＳＡＲ　ＡＤＣは、容量ＤＡ変換器の残差電圧を保持し、保持した残差電圧を次の変換サイクルで容量ＤＡ変換器に加算してノイズシェーピングを行っている。 Conventionally, SAR ADC (Successive Application Register Analog Analog Converter) is known. The SAR ADC holds the residual voltage of the capacitive DA converter and adds the retained residual voltage to the capacitive DA converter in the next conversion cycle to perform noise shaping.
　ここで、ノイズシェーピングとは、量子化ノイズとコンパレータノイズを削減するための技術である。ノイズシェーピングを行うことにより、信号を測定したときの信号とノイズとの比を示すＳＮＤＲ（Ｓｉｇｎａｌ　ｔｏ　ｎｏｉｓｅ　ａｎｄ　ｄｉｓｔｏｒｔｉｏｎ）が向上する。 Here, noise shaping is a technique for reducing quantization noise and comparator noise. By performing noise shaping, SNDR (Signal to noise and distortion), which indicates the ratio of signal to noise when the signal is measured, is improved.
　ＳＮＤＲの値を高くするためには、ノイズシェーピングの次数を高くすることが望まれる。上述したＳＡＲ　ＡＤＣに関し、単純で、非常に効率的なＳＡＲ　ＡＤＣが提案されている（例えば、非特許文献１）。 In order to increase the value of SNDR, it is desirable to increase the order of noise shaping. Regarding the above-mentioned SAR ADC, a simple and extremely efficient SAR ADC has been proposed (for example, Non-Patent Document 1).
　一般的に、ＳＡＲ　ＡＤＣは、ΔΣＡＤＣと異なり、ノイズシェーピングの次数を上げることが不向きであるため、達成できるＳＮＤＲの精度には限界があった。 Generally, SAR ADC, unlike ΔΣ ADC, is not suitable for increasing the order of noise shaping, so there is a limit to the accuracy of SNDR that can be achieved.
　本技術は、このような状況に鑑みてなされたものであり、ノイズシェーピングの高次化を図ることができる逐次比較型ＡＤコンバータ、Ｉｏｔセンサ、及び生体センサを提供することを主目的とする。 The present technology has been made in view of such a situation, and its main purpose is to provide a successive approximation type AD converter, an Iot sensor, and a biometric sensor that can achieve higher-order noise shaping.
　本発明者は、上述の目的を解決するために鋭意研究を行った結果、ノイズシェーピングの高次化を図ることができる逐次比較型ＡＤコンバータ、Ｉｏｔセンサ、及び生体センサを提供することに成功し、本技術を完成するに至った。 As a result of earnest research for solving the above-mentioned object, the present inventor succeeded in providing a successive approximation type AD converter, an Iot sensor, and a biosensor capable of achieving higher-order noise shaping. , Has come to complete this technology.
　すなわち、本技術では、　第１極性の第１コンデンサと、
　第１極性の第２コンデンサと、
　第１極性の第３コンデンサと、
　第２極性の第１コンデンサと、
　第２極性の第２コンデンサと、
　第２極性の第３コンデンサと、
　積分器アンプと、
　コンパレータと、
　フィルタ回路と、を備え、
　前記第１極性の第１コンデンサと、前記第１極性の第２コンデンサと、前記第１極性の第３コンデンサのそれぞれが、略同一の容量を有し、
　前記第２極性の第１コンデンサと、前記第２極性の第２コンデンサと、前記第２極性の第３コンデンサのそれぞれが、略同一の容量を有し、
前記第１極性の第１コンデンサ及び前記第２極性の第１コンデンサのそれぞれに、所定の電荷が蓄積され、
　前記第１極性の第２コンデンサが、入力されるアナログ電圧の第１電荷を蓄積するとともに、当該第１電荷を前記第１極性の第３コンデンサに転送し、
　前記積分器アンプが、前記第１極性の第３コンデンサに転送された前記第１電荷を積分して、第１積分値を生成し、
　前記第２極性の第２コンデンサが、入力されるアナログ電圧の第２電荷を蓄積するとともに、当該第２電荷を前記第２極性の第３コンデンサに転送し、
　前記積分器アンプが、前記第２極性の第３コンデンサに転送された前記第２電荷を積分して、第２積分値を生成し、
　前記コンパレータが、前記第１積分値と前記第２積分値とを比較し、前記第１極性の第２コンデンサと前記第２極性の第２コンデンサとがリセットされ、
　前記第１積分値が前記第２積分値よりも大きいときは、
　前記第１極性の第３コンデンサに蓄積された電荷と前記第１極性の第１コンデンサに蓄積された電荷とを、リセットされた前記第１極性の第２コンデンサに再配分するとともに、
　前記第２極性の第３コンデンサに蓄積された電荷と前記第２極性の第１コンデンサに蓄積された電荷とを、リセットされた前記第２極性の第２コンデンサに再配分し、
　前記第１積分値が前記第２積分値よりも略同等以下であるときは、
　前記第１極性の第３コンデンサに蓄積された電荷と前記第２極性の第１コンデンサに蓄積された電荷とを、リセットされた前記第１極性の第２のコンデンサに再配分するとともに、
　前記第２極性の第３コンデンサに蓄積された電荷と前記第１極性の第１コンデンサに蓄積された電荷とを、リセットされた前記第２極性の第２コンデンサに再配分し、
　所定の分解能のビット数が得られるまで、前記コンパレータが前記第１積分値と前記第２積分値とを前記比較することと、前記第１極性の第２コンデンサと前記第２極性の第２コンデンサとが前記リセットされることと、前記リセットされた、前記第１極性の第２コンデンサと前記第２極性の第２コンデンサとに前記再配分することと、を繰り返し、
　前記所定の分解能のビット数が得られた後、前記フィルタ回路に、前記第１極性の第２コンデンサに前記再配分して前記第１極性の第３コンデンサに蓄積された電荷と、前記第２極性の第２コンデンサに前記再配分して前記第２極性の第３コンデンサに蓄積された電荷とを、残差電圧として入力する、逐次比較型ＡＤコンバータを提供する。 That is, in the present technology, the first capacitor of the first polarity,
A second capacitor of the first polarity,
A third capacitor of the first polarity,
A first capacitor of the second polarity,
A second capacitor of the second polarity,
A second capacitor of the second polarity,
An integrator amplifier,
A comparator,
And a filter circuit,
Each of the first capacitor of the first polarity, the second capacitor of the first polarity, and the third capacitor of the first polarity has substantially the same capacitance,
The first capacitor having the second polarity, the second capacitor having the second polarity, and the third capacitor having the second polarity have substantially the same capacitance,
A predetermined charge is accumulated in each of the first capacitor of the first polarity and the first capacitor of the second polarity,
The second capacitor of the first polarity accumulates the first charge of the input analog voltage and transfers the first charge to the third capacitor of the first polarity,
The integrator amplifier integrates the first charge transferred to the third capacitor of the first polarity to generate a first integrated value,
The second capacitor of the second polarity accumulates the second charge of the input analog voltage and transfers the second charge to the third capacitor of the second polarity,
The integrator amplifier integrates the second charge transferred to the third capacitor of the second polarity to generate a second integrated value,
The comparator compares the first integrated value with the second integrated value, resets the second capacitor of the first polarity and the second capacitor of the second polarity,
When the first integrated value is larger than the second integrated value,
While redistributing the charge accumulated in the third capacitor of the first polarity and the charge accumulated in the first capacitor of the first polarity to the reset second capacitor of the first polarity,
The charge accumulated in the second capacitor of the second polarity and the charge accumulated in the first capacitor of the second polarity are redistributed to the reset second capacitor of the second polarity,
When the first integrated value is substantially equal to or less than the second integrated value,
The charge accumulated in the third capacitor of the first polarity and the charge accumulated in the first capacitor of the second polarity are redistributed to the reset second capacitor of the first polarity, and
The charge accumulated in the third capacitor of the second polarity and the charge accumulated in the first capacitor of the first polarity are redistributed to the reset second capacitor of the second polarity,
The comparator compares the first integrated value with the second integrated value until a bit number with a predetermined resolution is obtained, and the second capacitor of the first polarity and the second capacitor of the second polarity are compared. Is reset, and the redistributed to the reset second capacitor of the first polarity and the second capacitor of the second polarity,
After the number of bits of the predetermined resolution is obtained, in the filter circuit, the charge redistributed to the second capacitor of the first polarity and accumulated in the third capacitor of the first polarity, and the second capacitor Provided is a successive approximation type AD converter which inputs the electric charges accumulated in the second capacitor of the second polarity which is redistributed to the second capacitor of the polarity as a residual voltage.
　本技術に係る逐次比較型ＡＤコンバータにおいて、前記第１極性が、正極性であって、前記第２極性が、負極性であってもよい。 In the successive approximation type AD converter according to the present technology, the first polarity may be positive and the second polarity may be negative.
　本技術に係る逐次比較型ＡＤコンバータにおいて、前記所定の分解能の最下位ビットについて、前記コンパレータが、前記第１積分値と前記第２積分値とを比較し、前記第１極性の第２コンデンサと前記第２極性の第２コンデンサとが前記リセットされた後、当該第１極性の第２コンデンサと第２極性の第２コンデンサとについて前記再配分が完了するまでの間に、前記フィルタ回路が、前記残差電圧のサンプリングを開始してもよい。 In the successive approximation type AD converter according to the present technology, the comparator compares the first integral value and the second integral value with respect to the least significant bit of the predetermined resolution, and the second capacitor of the first polarity is used. After the resetting of the second capacitor of the second polarity and before the redistribution of the second capacitor of the first polarity and the second capacitor of the second polarity is completed, the filter circuit is Sampling of the residual voltage may be started.
　本技術に係る逐次比較型ＡＤコンバータにおいて、前記フィルタ回路が、前記積分器アンプによって駆動されるようにしてもよい。 In the successive approximation type AD converter according to the present technology, the filter circuit may be driven by the integrator amplifier.
　本技術に係る逐次比較型ＡＤコンバータにおいて、前記フィルタ回路が、オペアンプを含んで構成されるアクティブ型であってもよい。 In the successive approximation type AD converter according to the present technology, the filter circuit may be an active type including an operational amplifier.
　本技術に係る逐次比較型ＡＤコンバータにおいて、前記フィルタ回路が、コンデンサを含み、オペアンプを含まないで構成されるパッシブ型であってもよい。 In the successive approximation type AD converter according to the present technology, the filter circuit may be a passive type that includes a capacitor and does not include an operational amplifier.
　また、本技術では、前記逐次比較型ＡＤコンバータを備える、ＩｏＴセンサを提供する。 The present technology also provides an IoT sensor including the successive approximation type AD converter.
　また、本技術では、前記逐次比較型ＡＤコンバータを備える、生体センサを提供する。 Also, the present technology provides a biometric sensor including the successive approximation type AD converter.
　本技術によれば、逐次比較型ＡＤコンバータ、Ｉｏｔセンサ、及び生体センサは、ノイズシェーピングの高次化を実現することができる。なお、本技術の効果は、必ずしも上記の効果に限定されるものではなく、本技術に記載されたいずれかの効果であってもよい。 According to the present technology, the successive approximation type AD converter, the Iot sensor, and the biometric sensor can realize higher-order noise shaping. Note that the effect of the present technology is not necessarily limited to the above effect, and may be any effect described in the present technology.
本技術に係る第１の実施形態の逐次比較型ＡＤコンバータの一例であるＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣの構成の例を示すブロック図である。It is a block diagram showing an example of composition of Charge Share SAR ADC which is an example of a successive approximation type AD converter of a 1st embodiment concerning this art. 本技術に係る第１の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣが、スイッチをオンにするタイミングを示したタイミングチャートである。9 is a timing chart showing the timing at which the Charge Share SAR ADC according to the first embodiment of the present technology turns on the switch. 本技術に係る第１の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣのノイズビヘイビアモデルを示した図である。It is a figure showing the noise behavior model of Charge Share SAR ADC of a 1st embodiment concerning this art. 本技術に係る第１の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣが、フィルタ回路を有している場合の回路図である。It is a circuit diagram in case Charge Charge SAR ADC of a 1st embodiment concerning this art has a filter circuit. ノイズシェーピングにより、低周波帯域に位置する量子化雑音を高周波帯域に移動させることを示した説明図である。It is explanatory drawing shown that the quantization noise located in a low frequency band is moved to a high frequency band by noise shaping. 次数が高くなると、ノイズシェーピングの効果が高くなることを示した説明図である。It is an explanatory view showing that the effect of noise shaping becomes high if the order becomes high. 本技術を適用したＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣの構成例を示すブロック図である。It is a block diagram showing an example of composition of Charge Share SAR ADC to which this art is applied. 本技術を適用したＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣの構成例を示すブロック図である。It is a block diagram showing an example of composition of Charge Share SAR ADC to which this art is applied. 本技術を適用したＩｏＴセンサの構成例を示すブロック図である。It is a block diagram showing an example of composition of an IoT sensor to which this art is applied. 本技術を適用した生体センサの構成例を示すブロック図である。It is a block diagram showing an example of composition of a living body sensor to which this art is applied. 従来から知られているＣｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣに、ノイズシェーピングを実行するためのフィルタ回路が追加された回路図である。It is a circuit diagram in which a filter circuit for executing noise shaping is added to a conventionally known Charge Redistribution SAR ADC. Ｃｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣに実装されるフィルタ回路の例である。This is an example of a filter circuit implemented in a Charge Redistribution SAR ADC. Ｃｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣのノイズビヘイビアモデルを示した図である。It is the figure which showed the noise behavior model of Charge Redistribution SAR ADC. Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣの構成を示した回路図である。It is a circuit diagram showing a configuration of a Charge Share SAR ADC. Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣの動作を説明するためのフローチャートである。It is a flowchart for explaining the operation of the Charge Share SAR ADC. Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣのサンプリング時の状態を示した回路図である。It is a circuit diagram showing the state at the time of sampling of Charge Share SAR ADC. Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣの全電荷転送の状態を示した回路図である。It is the circuit diagram which showed the state of the total charge transfer of Charge Share SAR ADC. Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣの比較判定＆Ｃ２リセットの状態を示した回路図である。It is a circuit diagram showing the state of comparison judgment & C2 reset of Charge Share SAR ADC. Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣの比較結果フィードバックの状態を示した回路図である。It is the circuit diagram which showed the state of the comparison result feedback of Charge Share SAR ADC. Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣの電荷再配分の状態を示した回路図である。It is a circuit diagram showing the state of charge redistribution of Charge Share SAR ADC. Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣのノイズビヘイビアモデルである。It is a noise behavior model of Charge Share SAR ADC.
　以下、本技術を実施するための好適な形態について図面を参照しながら説明する。なお、以下に説明する実施形態は、本技術の代表的な実施形態の一例を示したものであり、これにより本技術の範囲が狭く解釈されることはない。 Hereinafter, a suitable mode for carrying out the present technology will be described with reference to the drawings. The embodiments described below are examples of typical embodiments of the present technology, and the scope of the present technology should not be construed narrowly.
　なお、説明は以下の順序で行う。
１．本技術の概要
２．第１の実施形態（逐次比較型ＡＤコンバータの例１）
３．第２の実施形態（逐次比較型ＡＤコンバータの例２）
４．第３の実施形態（逐次比較型ＡＤコンバータの例３）
５．第４の実施形態（ＩｏＴセンサの例）
６．第５の実施形態（生体センサの例） The description will be given in the following order.
1. Outline of the present technology 2. First Embodiment (Example 1 of Successive Approximation Type AD Converter)
3. Second embodiment (example 2 of successive approximation type AD converter)
4. Third embodiment (example 3 of successive approximation type AD converter)
5. Fourth embodiment (example of IoT sensor)
6. Fifth embodiment (example of biometric sensor)
＜１．本技術の概要＞
　一般的なＳＡＲ　ＡＤＣ（Ｓｕｃｃｅｓｓｉｖｅ Ａｐｐｒｏｘｉｍａｔｉｏｎ Ｒｅｓｉｓｔｅｒ Ａｎａｌｏｇ Ｄｉｇｉｔａｌ Ｃｏｎｖｅｒｔｅｒ）を、図１１に示す。図１１に示されるＳＡＲ　ＡＤＣは、従来から知られているＣｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣに、ノイズシェーピングを実行するためのフィルタ回路ＦＬＴ１が追加された回路図である。 <1. Overview of this technology>
A general SAR ADC (Successive Application Register Analog Digital Converter) is shown in FIG. The SAR ADC shown in FIG. 11 is a circuit diagram in which a filter circuit FLT1 for executing noise shaping is added to the conventionally known Charge Redistribution SAR ADC.
　図１１に示されるＣｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣ１０１は、複数のコンデンサＣＰ０～コンデンサＣＰ６（コンデンサＣＰ０、コンデンサＣＰ１、・・・コンデンサＣＰ２、コンデンサＣＰ３、コンデンサＣＰ４、コンデンサＣＰ５、及びコンデンサＣＰ６）と、スイッチＳＷ１～スイッチＳＷ７（スイッチＳＷ１、スイッチＳＷ２、・・・スイッチＳＷ３、スイッチＳＷ４、スイッチＳＷ５、スイッチＳＷ６、及びスイッチＳＷ７）と、フィルタ回路ＦＬＴ１と、コンパレータＣＭＰ１とを備えている。 The Charge Redistribution SAR ADC 101 shown in FIG. 11 includes a plurality of capacitors CP0 to CP6 (capacitor CP0, capacitor CP1,... Capacitor CP2, capacitor CP3, capacitor CP4, capacitor CP5, and capacitor CP6), and switches SW1 to SW1. SW7 (switch SW1, switch SW2,... Switch SW3, switch SW4, switch SW5, switch SW6, and switch SW7), a filter circuit FLT1, and a comparator CMP1.
　Ｃｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣ１０１が有する複数のコンデンサＣＰ０～ＣＰ６は、容量アレイを構成し、バイナリウエイト（Ｂｉｎａｒｙ　Ｗｅｉｇｈｔ）構成となっている。また、Ｃｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣ１０１は、完全差動回路で実装されるが、ここでは、説明を簡略化するため、シングルエンドで構成されている。なお、バイナリウエイトとは、公比２の等比数列をなす重み（容量値）の集合である。 The plurality of capacitors CP0 to CP6 included in the Charge Redistribution SAR ADC 101 form a capacitance array and have a binary weight configuration. Also, the Charge Redistribution SAR ADC 101 is implemented as a fully differential circuit, but here, for the sake of simplicity of explanation, it is configured as a single end. The binary weight is a set of weights (capacity values) forming a geometric progression with a common ratio of 2.
　Ｃｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣ１０１は、逐次比較変換後の残差電圧をフィルタ回路ＦＬＴ１に入力することにより、ノイズ伝達関数（ＮＴＦ）にハイパス特性を持たせることができる。図１１に示されるＣｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣ１０１は、一例として、図１２に示されたフィルタ回路ＦＬＴ１を実装する。 The Charge Redistribution SAR ADC 101 can give the noise transfer function (NTF) a high-pass characteristic by inputting the residual voltage after successive approximation conversion to the filter circuit FLT1. The Charge Redistribution SAR ADC 101 shown in FIG. 11 implements the filter circuit FLT1 shown in FIG. 12 as an example.
　図１２（Ａ）に、Ｃｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣ１０１に実装されるフィルタ回路ＦＬＴ１を示す。また、図１２（Ｂ）に、フィルタ回路ＦＬＴ１が有するスイッチΦ７～スイッチΦ１２（スイッチΦ７ａ～スイッチΦ１２ａ、及びスイッチΦ７ｂ～スイッチΦ１２ｂ）の切り替えタイミングを示す。 FIG. 12(A) shows a filter circuit FLT1 implemented in the Charge Redistribution SAR ADC 101. Further, FIG. 12B shows switching timings of the switch Φ7 to the switch Φ12 (the switch Φ7a to the switch Φ12a and the switch Φ7b to the switch Φ12b) included in the filter circuit FLT1.
　図１２Ａに示されるフィルタ回路ＦＬＴ１は、バッファＡｂｕｆ、コンデンサＣ４１ａ、コンデンサＣ４２ａ、コンデンサＣ４３ａ、コンデンサＣ４１ｂ、コンデンサＣ４２ｂ、コンデンサＣ４３ｂ、コンデンサＣ５ａ、コンデンサＣ５ｂ、スイッチΦ７～スイッチΦ１２（スイッチΦ７ａ～スイッチΦ１２ａ、及びスイッチΦ７ｂ～スイッチΦ１２ｂ）、及び積分器アンプＩＰＦを備えて構成されている。なお、コンデンサＣ４１ａ及びコンデンサＣ４１ｂは、略同等の容量となっている。ここで、略同等の容量とは、例えば、同一の容量値を含み、同一の容量値に対して、９５％～１０５％以内にある容量値のことをいう。また、コンデンサＣ４２ａ及びコンデンサＣ４３ａは、コンデンサＣ４１ａの略１／３の容量となっている。また、コンデンサＣ４２ｂ及びコンデンサＣ４３ｂは、コンデンサＣ４１ｂの略１／３の容量となっている。ここで、略１／３の容量とは、１／３の容量値を含み、１／３の容量値に対して、９５％～１０５％以内にある容量値のことをいう。 The filter circuit FLT1 shown in FIG. 12A includes a buffer Abuf, a capacitor C41a, a capacitor C42a, a capacitor C43a, a capacitor C41b, a capacitor C42b, a capacitor C43b, a capacitor C5a, a capacitor C5b, a switch Φ7 to a switch Φ12 (a switch Φ7a to a switch Φ12a, and The switch Φ7b to the switch Φ12b) and the integrator amplifier IPF. The capacitors C41a and C41b have substantially the same capacitance. Here, the substantially equal capacities are, for example, capacities that include the same capacity value and are within 95% to 105% of the same capacity value. Further, the capacitors C42a and C43a have a capacitance that is approximately 1/3 of that of the capacitor C41a. Further, the capacitors C42b and C43b have a capacitance that is approximately ⅓ of that of the capacitor C41b. Here, the capacity of about 1/3 means a capacity value including a capacity value of 1/3 and within 95% to 105% of the capacity value of 1/3.
　この場合、フィルタ回路ＦＬＴ１の伝達関数Ｌ（ｚ）は、次式（式（１））で表される。 In this case, the transfer function L(z) of the filter circuit FLT1 is expressed by the following equation (equation (1)).
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
　また、この場合のＣｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣ１０１のノイズビヘイビアモデルを、図１３に示す。図１３は、Ｃｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣ１０１のノイズビヘイビアモデルを示した図である。なお、ノイズビヘイビアモデルとは、ノイズの入出力特性を示したものである。 Further, FIG. 13 shows a noise behavior model of the Charge Redistribution SAR ADC 101 in this case. FIG. 13 is a diagram showing a noise behavior model of Charge Redistribution SAR ADC 101. The noise behavior model indicates the input/output characteristics of noise.
　Ｃｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣ１０１のノイズビヘイビアモデルは、減算器ＳＢ１、フィルタ回路ＦＬＴ１、加算器ＡＤ１、及びＳＡＲ量子化器ＳＱ１を備えている。そして、Ｃｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣ１０１のノイズ伝達関数ＮＴＦ（ｚ）は、次式（式（２））で表される。 The noise behavior model of the Charge Redistribution SAR ADC 101 includes a subtractor SB1, a filter circuit FLT1, an adder AD1, and a SAR quantizer SQ1. Then, the noise transfer function NTF(z) of the Charge Redistribution SAR ADC 101 is expressed by the following equation (equation (2)).
Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000002
　式（２）に示されたノイズ伝達関数ＮＴＦ（ｚ）は、１次のハイパス特性を有している。このため、フィルタ回路ＦＬＴ１の伝達関数Ｌ（ｚ）を複雑にすることで、高次のＮｏｉｓｅ　Ｓｈａｐｉｎｇを実現することができるが、Ｃｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣ１０１の設計において、占有面積・消費電力・設計難易度等が増加する。 The noise transfer function NTF(z) shown in Expression (2) has a first-order high-pass characteristic. Therefore, high-order Noise Shaping can be realized by making the transfer function L(z) of the filter circuit FLT1 complicated, but in the design of the Charge Redistribution SAR ADC 101, the occupied area, power consumption, and design difficulty are high. Etc. will increase.
　ここで、Ｃｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣ１０１が高いＳＮＤＲを得るためには、リファレンス電圧を安定させなければならない。 Here, in order for the Charge Redistribution SAR ADC 101 to obtain a high SNDR, the reference voltage must be stabilized.
　リファレンス電圧を安定させるためには、リファレンス電圧を生成しているバッファアンプを高性能化するか、又は、コンデンサを複数搭載し、電圧変動を抑えることが一般的である。しかしながら、バッファアンプを高性能化すると、又は、コンデンサを複数搭載すると、消費電力の増加や占有面積の増加が生じてしまう。 ㆍIn order to stabilize the reference voltage, it is common to improve the performance of the buffer amplifier that generates the reference voltage or to mount multiple capacitors to suppress voltage fluctuations. However, if the performance of the buffer amplifier is increased, or if a plurality of capacitors are mounted, the power consumption and the occupied area increase.
　そこで、消費電力の増加や占有面積の増加を回避すべく、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣに関するＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２の回路を用いることを検討する。ここで、シングルエンドで構成されたＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２を、図１４に示す。図１４は、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２の構成を示した回路図である。なお、図１４では、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　　ＡＤＣの動作の説明を簡略化するため、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２が、シングルエンドで構成されている。 Therefore, in order to avoid an increase in power consumption and an increase in occupied area, we will consider using the circuit of the Charge Share SAR ADC 102 related to the Charge Share SAR ADC. Here, FIG. 14 shows the Charge Share SAR ADC 102 configured with a single end. FIG. 14 is a circuit diagram showing the configuration of the Charge Share SAR ADC 102. Note that in FIG. 14, the Charge Share SAR ADC 102 is configured as a single end in order to simplify the description of the operation of the Charge Share SAR ADC.
　図１４に示されたＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２は、スイッチΦ１ｘ、スイッチΦ１ｙ、スイッチΦ１ｚ、スイッチΦ２、スイッチΦ３、スイッチΦ４、コンデンサＣ１Ｐ、コンデンサＣ１Ｎ、コンデンサＣ２、コンデンサＣ３、積分器アンプＩＰ１、及びコンパレータＣＭＰ２を備えて構成されている。 The Charge Share SAR ADC 102 shown in FIG. 14 is a switch Φ1x, a switch Φ1y, a switch Φ1z, a switch Φ2, a switch Φ3, a switch Φ4, a capacitor C1P, a capacitor C1N, a capacitor C2, a capacitor C3, an integrator amplifier IP1, and a comparator CMP2. It is configured with.
　このＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２の動作について、図１５に示されるフローチャートを用いて説明する。図１５は、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２の動作を説明するためのフローチャートである。 The operation of this Charge Share SAR ADC 102 will be described using the flowchart shown in FIG. FIG. 15 is a flowchart for explaining the operation of the Charge Share SAR ADC 102.
　まず、サンプリング時（ステップＳ００１）のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２の回路の状態を、図１６に示す。図１６では、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２は、スイッチΦ１ｘ、スイッチΦ１ｙ、スイッチΦ１ｚ、及びスイッチΦ２がオンとなり（閉じており）、電圧Ｖｉｐ、電圧Ｖｒｅｆｐ、及び電圧Ｖｒｅｆｎの電圧がサンプリングされる。 First, FIG. 16 shows the state of the circuit of the Charge Share SAR ADC 102 at the time of sampling (step S001). In FIG. 16, in the Charge Share SAR ADC 102, the switch Φ1x, the switch Φ1y, the switch Φ1z, and the switch Φ2 are turned on (closed), and the voltage Vip, the voltage Vrefp, and the voltage Vrefn are sampled.
　この場合、コンデンサＣ１Ｐ、コンデンサＣ１Ｎ、コンデンサＣ２、及びコンデンサＣ３の各電荷は、次式（式（３）から式（６））で表される。 In this case, each charge of the capacitor C1P, the capacitor C1N, the capacitor C2, and the capacitor C3 is expressed by the following equations (Equations (3) to (6)).
　Ｑ１Ｐ＝Ｃ１Ｐ　×　Ｖｒｅｐ　　　　　　　　　　　・・・（３）
　Ｑ１Ｎ＝Ｃ１Ｎ　×　Ｖｒｅｎ　　　　　　　　　　　・・・（４）
　Ｑ２　＝Ｃ２　　×　Ｖｉｐ　　　　　　　　　　　　・・・（５）
　Ｑ３　＝０　　　　　　　　　　　　　　　　　　　　・・・（６） Q1P=C1P×Vrep (3)
Q1N=C1N×Vren (4)
Q2=C2×Vip (5)
Q3 =0 (6)
　次に、全電荷転送（ステップＳ００３）の状態を、図１７に示す。図１７では、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２は、スイッチΦ１ｘ、スイッチΦ１ｙ、スイッチΦ１ｚ、及びスイッチΦ２がオフとなり（開き）、スイッチΦ３及びスイッチΦ４がオンとなっている（閉じている）。これにより、コンデンサＣ２に蓄えられていた電荷Ｑ２が、コンデンサＣ３に全電荷転送される。 Next, FIG. 17 shows the state of total charge transfer (step S003). In FIG. 17, in the Charge Share SAR ADC 102, the switch Φ1x, the switch Φ1y, the switch Φ1z, and the switch Φ2 are off (open), and the switches Φ3 and Φ4 are on (closed). As a result, the electric charge Q2 stored in the capacitor C2 is transferred to the capacitor C3.
　この場合、コンデンサＣ１Ｐ、コンデンサＣ１Ｎ、コンデンサＣ２、及びコンデンサＣ３の各電荷は、次式（式（３）、式（４）、式（７）、式（８））のようになる。 In this case, the electric charges of the capacitors C1P, C1N, C2, and C3 are expressed by the following equations (equation (3), equation (4), equation (7), and equation (8)).
　Ｑ１Ｐ＝Ｃ１Ｐ　×　Ｖｒｅｐ　　　　　　　　　　　・・・（３）
　Ｑ１Ｎ＝Ｃ１Ｎ　×　Ｖｒｅｎ　　　　　　　　　　　・・・（４）
　Ｑ２　＝０　　　　　　　　　　　　　　　　　　　　・・・（７）
　Ｑ３　＝Ｃ２　　×　Ｖｉｐ　　　　　　　　　　　　・・・（８）
　∵Ｃ２Ｐ＝Ｃ３Ｐ Q1P=C1P×Vrep (3)
Q1N=C1N×Vren (4)
Q2 =0 (7)
Q3=C2×Vip (8)
∵C2P=C3P
　次に、比較判定＆Ｃ２リセット（ステップＳ００５）の状態を、図１８に示す。図１８では、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２は、スイッチΦ４をオフにして（開いて）、コンパレータＣＭＰ２において、電荷Ｑ３の積分値と接地電位とを比較すると同時に、スイッチΦ２及びスイッチΦ３をオンにして（閉じて）、コンデンサＣ２をリセットする。コンパレータＣＭＰ２は、電荷Ｑ３の積分値と接地電位とを比較した結果として、判定結果Ｄ又は判定結果ＤＮを出力する。 Next, FIG. 18 shows the state of comparison judgment & C2 reset (step S005). In FIG. 18, the Charge Share SAR ADC 102 turns off (opens) the switch Φ4 and compares the integrated value of the charge Q3 with the ground potential in the comparator CMP2, and simultaneously turns on the switches Φ2 and Φ3 (closes them). ), and reset the capacitor C2. The comparator CMP2 outputs the determination result D or the determination result DN as a result of comparing the integrated value of the charge Q3 and the ground potential.
　次に、比較結果フィードバック（ステップＳ００７）の状態を、図１９に示す。図１９では、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２は、コンパレータＣＭＰ２において、判定結果Ｄが出力されたと仮定する。この場合、スイッチＤΦ５がオンとなる（閉じる）。 Next, FIG. 19 shows the state of comparison result feedback (step S007). In FIG. 19, it is assumed that the Charge Share SAR ADC 102 outputs the determination result D in the comparator CMP2. In this case, the switch DΦ5 is turned on (closed).
　電荷再配分（ステップＳ００９）の状態を、図２０に示す。図２０では、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２は、コンデンサＣ２において、コンデンサＣ１Ｐの電荷Ｑ１ＰとコンデンサＣ３の電荷Ｑ３との電荷再配分を行う。 The state of charge redistribution (step S009) is shown in FIG. In FIG. 20, the Charge Share SAR ADC 102 redistributes the charge Q1P of the capacitor C1P and the charge Q3 of the capacitor C3 in the capacitor C2.
　この場合、コンデンサＣ１Ｐ、コンデンサＣ２、及びコンデンサＣ３の各電荷は、次式（式（９）から式（１２））のようになる。 In this case, the electric charges of the capacitors C1P, C2, and C3 are as in the following formulas (formula (9) to formula (12)).
　Ｑ１Ｐ＝　Ｃ１Ｐ　×　Ｖｒｅｆｐ／２　　　　　　　　・・・（９）
　Ｑ２　＝　Ｃ１Ｐ　×　Ｖｒｅｆｐ／２　　　　　　　　・・・（１０）
　Ｑ３　＝　Ｃ２　×　Ｖｉｐ　－　Ｃ１Ｐ　×　Ｖｒｅｆｐ／２
　　　　　　　　　　　　　　　　　　　　　　　　　　　・・・（１１）
　Ｖｏ　＝　Ｑ３／Ｃ３　＝　Ｖｉｐ　－　Ｖｒｅｆｐ／２・・・（１２）
　∵Ｃ１Ｐ＝Ｃ１Ｎ＝Ｃ２＝Ｃ３　 Q1P=C1P×Vrefp/2 (9)
Q2=C1P×Vrefp/2 (10)
Q3=C2×Vip−C1P×Vrefp/2
...(11)
Vo=Q3/C3=Vip−Vrefp/2 (12)
∵ C1P=C1N=C2=C3
　式（９）では、コンデンサＣ１Ｐの電荷Ｑ１Ｐが半分になっており、式（１２）の電圧Ｖｏでは、Ｃｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣ１０１と同じ電圧になっている。そのため、図１５のステップ０１１において、分解能をＮビットとした場合、所定のＮビットの分解能が得られていなければ（ステップＳ０１１のＮｏ）、ステップＳ００５の比較判定＆Ｃ２リセットに戻り、ステップＳ００５からステップＳ００９を繰り返すことにより、（ＭＳＢ－１）ｂｉｔ以降の分解能を取得する。 In the formula (9), the charge Q1P of the capacitor C1P is halved, and the voltage Vo in the formula (12) is the same voltage as the Charge Redistribution SAR ADC 101. Therefore, when the resolution is set to N bits in step 011 of FIG. 15 and the predetermined N-bit resolution is not obtained (No in step S011), the process returns to the comparison determination & C2 reset in step S005, and the steps from step S005 to step S005. By repeating S009, the resolution after (MSB-1) bit is acquired.
　このアクティブ型のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２は、コンデンサＣ３に前回のＳＡＲ　ＡＤＣ変換残差電圧を保持することにより、ノイズ伝達関数は、１次のハイパス特性を有している。コンデンサＣ３と積分器アンプＩＰ１の伝達関数Ｌ（ｚ）は、次式（式（１３））で表される。 This active Charge Share SAR ADC 102 holds the previous SAR ADC conversion residual voltage in the capacitor C3, so that the noise transfer function has a first-order high-pass characteristic. The transfer function L(z) of the capacitor C3 and the integrator amplifier IP1 is expressed by the following equation (equation (13)).
Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-M000003
　また、この場合のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２のビヘイビアモデルを、図２１に示す。図２１は、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２のノイズビヘイビアモデルを示したものである。 Further, FIG. 21 shows the behavior model of the Charge Share SAR ADC 102 in this case. FIG. 21 shows a noise behavior model of the Charge Share SAR ADC 102.
　図２１に示されたＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２は、減算器ＳＢ１、積分器ＩＴＧ１、加算器ＡＤ１、及びＳＡＲ量子化器ＳＱ２を備えている。そして、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２のノイズ伝達関数ＮＴＦ（ｚ）は、次式（式（１４））で表される。 The Charge Share SAR ADC 102 shown in FIG. 21 includes a subtractor SB1, an integrator ITG1, an adder AD1, and a SAR quantizer SQ2. Then, the noise transfer function NTF(z) of the Charge Share SAR ADC 102 is expressed by the following equation (Equation (14)).
Figure JPOXMLDOC01-appb-M000004
Figure JPOXMLDOC01-appb-M000004
　式（１４）に示されるように、アクティブ型のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１０２では、ノイズシェーピングの次数は、１次にとどまっていた。 As shown in the equation (14), in the active type Charge Share SAR ADC 102, the order of noise shaping was limited to the first order.
　そこで、本技術によれば、ノイズシェーピングの高次化を図ることができるＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣを提供する。これにより、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣは、高いＳＮＤＲを実現することができる。 Therefore, according to the present technology, a Charge Share SAR ADC that can achieve higher-order noise shaping is provided. As a result, the Charge Share SAR ADC can realize a high SNDR.
＜２．第１の実施形態（逐次比較型ＡＤコンバータの例１）＞
　本技術に係る第１の実施形態の逐次比較型ＡＤコンバータは、第１極性の第１コンデンサと、第１極性の第２コンデンサと、第１極性の第３コンデンサと、第２極性の第１コンデンサと、第２極性の第２コンデンサと、第２極性の第３コンデンサと、積分器アンプと、コンパレータと、フィルタ回路と、を備えている。 <2. First Embodiment (Example 1 of Successive Approximation Type AD Converter)>
The successive approximation type AD converter according to the first embodiment of the present technology is a first capacitor having a first polarity, a second capacitor having a first polarity, a third capacitor having a first polarity, and a first capacitor having a second polarity. A capacitor, a second capacitor having a second polarity, a third capacitor having a second polarity, an integrator amplifier, a comparator, and a filter circuit are provided.
　本技術に係る第１の実施形態の逐次比較型ＡＤコンバータは、第１極性の第１コンデンサと、第１極性の第２コンデンサと、第１極性の第３コンデンサのそれぞれが、略同一の容量を有し、第２極性の第１コンデンサと、第２極性の第２コンデンサと、第２極性の第３コンデンサのそれぞれが、略同一の容量を有している。第１極性の第１コンデンサ及び第２極性の第１コンデンサのそれぞれに、所定の電荷が蓄積される。 In the successive approximation A/D converter according to the first embodiment of the present technology, the first capacitor having the first polarity, the second capacitor having the first polarity, and the third capacitor having the first polarity have substantially the same capacitance. And the first capacitor of the second polarity, the second capacitor of the second polarity, and the third capacitor of the second polarity have substantially the same capacitance. A predetermined charge is accumulated in each of the first capacitor of the first polarity and the first capacitor of the second polarity.
　第１極性の第２コンデンサが、入力されるアナログ電圧の第１電荷を蓄積するとともに、当該第１電荷を第１極性の第３コンデンサに転送する。積分器アンプが、第１極性の第３コンデンサに転送された第１電荷を積分して、第１積分値を生成する。 The second capacitor of the first polarity stores the first charge of the input analog voltage and transfers the first charge to the third capacitor of the first polarity. An integrator amplifier integrates the first charge transferred to the third capacitor of the first polarity to generate a first integrated value.
　第２極性の第２コンデンサが、入力されるアナログ電圧の第２電荷を蓄積するとともに、当該第２電荷を第２極性の第３コンデンサに転送する。積分器アンプが、第２極性の第３コンデンサに転送された第２電荷を積分して、第２積分値を生成する。 The second capacitor of the second polarity stores the second electric charge of the input analog voltage and transfers the second electric charge to the third capacitor of the second polarity. An integrator amplifier integrates the second electric charge transferred to the third capacitor of the second polarity to generate a second integrated value.
　コンパレータが、第１積分値と第２積分値とを比較する。第１極性の第２コンデンサと第２極性の第２コンデンサとがリセットされる。第１積分値が第２積分値よりも大きいときは、第１極性の第３コンデンサに蓄積された電荷と第１極性の第１コンデンサに蓄積された電荷とを、リセットされた第１極性の第２コンデンサに再配分するとともに、第２極性の第３コンデンサに蓄積された電荷と第２極性の第１コンデンサに蓄積された電荷とを、リセットされた第２極性の第２コンデンサに再配分する。 The comparator compares the first integral value and the second integral value. The second capacitor having the first polarity and the second capacitor having the second polarity are reset. When the first integrated value is larger than the second integrated value, the charges accumulated in the third capacitor of the first polarity and the charges accumulated in the first capacitor of the first polarity are reset to the first polarity. While redistributing to the second capacitor, the charge accumulated in the third capacitor of the second polarity and the charge accumulated in the first capacitor of the second polarity are redistributed to the reset second capacitor of the second polarity. To do.
　第１積分値が第２積分値よりも略同等以下であるときは、第１極性の第３コンデンサに蓄積された電荷と第２極性の第１コンデンサに蓄積された電荷とを、リセットされた第１極性の第２のコンデンサに再配分するとともに、第２極性の第３コンデンサに蓄積された電荷と第１極性の第１コンデンサに蓄積された電荷とを、リセットされた第２極性の第２コンデンサに再配分する。 When the first integrated value is substantially equal to or less than the second integrated value, the electric charge accumulated in the third capacitor of the first polarity and the electric charge accumulated in the first capacitor of the second polarity are reset. While redistributing to the second capacitor of the first polarity, the charge accumulated in the third capacitor of the second polarity and the charge accumulated in the first capacitor of the first polarity are reset to the second capacitor of the second polarity. Redistribute to 2 capacitors.
　所定の分解能のビット数が得られるまで、コンパレータが第１積分値と第２積分値とを比較することと、第１極性の第２コンデンサと第２極性の第２コンデンサとがリセットされることと、リセットされた、第１極性の第２コンデンサと第２極性の第２コンデンサとに再配分することと、を繰り返す。 The comparator compares the first integrated value and the second integrated value until the number of bits of a predetermined resolution is obtained, and the second capacitor of the first polarity and the second capacitor of the second polarity are reset. And redistribute to the reset second capacitors of the first polarity and the second capacitors of the second polarity are repeated.
　所定の分解能のビット数が得られた後、フィルタ回路に、第１極性の第２コンデンサに再配分して第１極性の第３コンデンサに蓄積された電荷と、第２極性の第２コンデンサに再配分して第２極性の第３コンデンサに蓄積された電荷とを、残差電圧として入力する、逐次比較型ＡＤコンバータである。 After the number of bits of a predetermined resolution is obtained, the charge accumulated in the third capacitor of the first polarity by redistributing to the second capacitor of the first polarity and the second capacitor of the second polarity are redistributed in the filter circuit. This is a successive approximation type AD converter that inputs the electric charges that are redistributed and accumulated in the third capacitor of the second polarity as a residual voltage.
　本技術に係る第１の実施形態の逐次比較型ＡＤコンバータによれば、ノイズシェーピングの高次化を図ることができる。 According to the successive approximation type AD converter of the first embodiment according to the present technology, higher order noise shaping can be achieved.
［逐次比較型ＡＤコンバータの構成］
　図１に、本技術に係る第１の実施形態の逐次比較型ＡＤコンバータの一例であるＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００を示す。図１は、本技術を適用したＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００の構成例を示すブロック図である。なお、上述した構成と同一の構成要素については同一の符号を付し、説明を適宜、省略する。 [Configuration of successive approximation type AD converter]
FIG. 1 shows a Charge Share SAR ADC 100 that is an example of a successive approximation type AD converter according to the first embodiment of the present technology. FIG. 1 is a block diagram showing a configuration example of a Charge Share SAR ADC 100 to which the present technology is applied. The same components as those described above are designated by the same reference numerals, and description thereof will be omitted as appropriate.
　図１に示されるように、本技術に係る第１の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、第１極性の第１コンデンサＣ１ａ、第１極性の第２コンデンサＣ２ａ、第１極性の第３コンデンサＣ３ａ、スイッチΦ１ａ１、スイッチΦ１ａ２、スイッチΦ２ａ、スイッチΦ３ａ、スイッチΦ４ａ、スイッチＤΦ５ａ、スイッチＤＮΦ５ａ、スイッチΦ６ａ、スイッチΦＲＥＳＴａ、第２極性の第１コンデンサＣ１ｂ、第２極性の第２コンデンサＣ２ｂ、第２極性の第３コンデンサＣ３ｂ、スイッチΦ１ｂ１、スイッチΦ１ｂ２、スイッチΦ２ｂ、スイッチΦ３ｂ、スイッチΦ４ｂ、スイッチＤΦ５ｂ、スイッチＤＮΦ５ｂ、スイッチΦ６ｂ、スイッチΦＲＥＳＴｂ、積分器アンプＩＰ、フィルタ回路ＦＬＴ、及びコンパレータＣＭＰを備えて構成されている。 As shown in FIG. 1, the Charge Share SAR ADC 100 according to the first embodiment of the present technology includes a first capacitor C1a having a first polarity, a second capacitor C2a having a first polarity, and a third capacitor C3a having a first polarity. , Switch Φ1a1, switch Φ1a2, switch Φ2a, switch Φ3a, switch Φ4a, switch DΦ5a, switch DNΦ5a, switch Φ6a, switch ΦRESTa, second polarity first capacitor C1b, second polarity second capacitor C2b, second polarity. A third capacitor C3b, a switch Φ1b1, a switch Φ1b2, a switch Φ2b, a switch Φ3b, a switch Φ4b, a switch DΦ5b, a switch DNΦ5b, a switch Φ6b, a switch ΦRESTb, an integrator amplifier IP, a filter circuit FLT, and a comparator CMP. There is.
　本技術に係る第１の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、例えば、一例として、第１極性が正極性であって、第２極性が負極性である。また、積分器ＩＴＧは、スイッチΦＲＥＳＴａ、第１極性の第３コンデンサ、積分器アンプＩＰ、第２極性の第３コンデンサＣ３ｂ、スイッチΦＲＥＳＴｂを備えて構成されている。 In the Charge Share SAR ADC 100 of the first embodiment according to the present technology, for example, the first polarity is positive and the second polarity is negative. The integrator ITG includes a switch ΦRESTa, a third capacitor having a first polarity, an integrator amplifier IP, a third capacitor C3b having a second polarity, and a switch ΦRESTb.
［逐次比較型ＡＤコンバータの動作］
　次に、第１の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００の動作について、上述した図１５のフローチャートを用いて説明する。 [Operation of successive approximation type AD converter]
Next, the operation of the Charge Share SAR ADC 100 of the first embodiment will be described using the flowchart of FIG. 15 described above.
　まず、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、初期リセット動作を行う。初期リセット動作を行った後、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、全てのスイッチΦをオフにする（開く）。なお、スイッチΦＲＥＳＴａ及びスイッチΦＲＥＳＴｂは、初期リセットの解除によってオフになった後は（開いた後は）、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００が再びリセットされるまでオフの状態（開いた状態）を継続する。 First, the Charge Share SAR ADC 100 performs an initial reset operation. After performing the initial reset operation, the Charge Share SAR ADC 100 turns off (opens) all the switches Φ. Note that the switch ΦRESTa and the switch ΦRESTb are kept off (open) until the Charge Share SAR ADC 100 is reset again after being turned off (after opening) by releasing the initial reset.
　次に、サンプリング時（図１５のステップＳ００１）において、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、スイッチΦ１ａ１、スイッチΦ１ａ２、スイッチΦ２ａ、スイッチΦ１ｂ１、スイッチΦ１ｂ２、及びスイッチΦ２ｂがオンとなり（閉じて）、電圧Ｖｉｐ、電圧Ｖｒｅｆｐ、電圧Ｖｒｅｆｎ、及び電圧Ｖｉｎの電圧がサンプリングされる。 Next, at the time of sampling (step S001 in FIG. 15), the Charge Share SAR ADC 100 turns on (closes) the switch Φ1a1, the switch Φ1a2, the switch Φ2a, the switch Φ1b2, and the switch Φ2b, and the voltage Vip and the voltage Vip. The voltages Vrefp, Vrefn, and Vin are sampled.
　これにより、第１極性の第１コンデンサＣ１ａ、第２極性の第１コンデンサＣ１ｂ、第１極性の第２のコンデンサＣ２ａ、第２極性の第２のコンデンサＣ２ｂのそれぞれに、所定の電荷が蓄積される。また、第１極性の第２のコンデンサＣ２ａは、入力されるアナログ電圧の第１電荷を蓄積するとともに、第２極性の第２のコンデンサＣ２ｂは、入力されるアナログ電圧の第２電荷を蓄積する。 As a result, a predetermined charge is accumulated in each of the first capacitor C1a having the first polarity, the first capacitor C1b having the second polarity, the second capacitor C2a having the first polarity, and the second capacitor C2b having the second polarity. It The second capacitor C2a of the first polarity stores the first charge of the input analog voltage, and the second capacitor C2b of the second polarity stores the second charge of the input analog voltage. ..
　この場合、第１極性の第１コンデンサＣ１ａ、第２極性の第１コンデンサＣ１ｂ、第１極性の第２のコンデンサＣ２ａ、及び第２極性の第２のコンデンサＣ２ｂの各電荷は、次式（式（１５）から式（１８））のようになる。 In this case, the respective charges of the first capacitor C1a of the first polarity, the first capacitor C1b of the second polarity, the second capacitor C2a of the first polarity, and the second capacitor C2b of the second polarity are expressed by the following formula (equation: From (15), the equation (18) is obtained.
　Ｑ１ａ＝Ｃ１ａ　×　Ｖｒｅｐ　　　　　　　　　　　・・・（１５）
　Ｑ１ｂ＝Ｃ１ｂ　×　Ｖｒｅｎ　　　　　　　　　　　・・・（１６）
　Ｑ２ａ＝Ｃ２ａ　×　Ｖｉｐ　　　　　　　　　　　　・・・（１７）
　Ｑ２ｂ＝Ｃ２ｂ　×　Ｖｉｎ　　　　　　　　　　　　・・・（１８） Q1a=C1a×Vrep (15)
Q1b=C1b×Vren (16)
Q2a=C2a×Vip (17)
Q2b=C2b×Vin (18)
　次に、全電荷転送（ステップＳ００３）において、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、スイッチΦ１ａ１、スイッチΦ１ａ２、スイッチΦ２ａ、スイッチΦ１ｂ１、スイッチΦ１ｂ２、及びスイッチΦ２ｂをオフにする（開く）とともに、スイッチΦ３ａ、スイッチΦ４ａ、スイッチΦ３ｂ、及びスイッチΦ４ｂをオンにする（閉じる）。これにより、第１極性の第２のコンデンサＣ２ａに蓄えられた第１電荷は、第１極性の第３のコンデンサＣ３ａに全電荷転送されるとともに、第２極性の第２のコンデンサＣ２ｂに蓄えられた第２電荷は、第２極性の第３のコンデンサＣ３ｂに全電荷転送される。 Next, in the total charge transfer (step S003), the Charge Share SAR ADC 100 turns off (opens) the switch Φ1a1, the switch Φ1a2, the switch Φ2a, the switch Φ1b1, the switch Φ1b2, and the switch Φ3a and the switch Φ4a. , Switch Φ3b and switch Φ4b are turned on (closed). As a result, the first charge stored in the second capacitor C2a of the first polarity is fully transferred to the third capacitor C3a of the first polarity and is stored in the second capacitor C2b of the second polarity. The second charge is completely transferred to the third capacitor C3b having the second polarity.
　この場合、第１極性の第１コンデンサＣ１ａ、第１極性の第２のコンデンサＣ２ａ、第２極性の第１コンデンサＣ１ｂ、及び第２極性の第２のコンデンサＣ２ｂの各電荷は、次式（式（１５）、式（１６）、式（１９）から式（２２））のようになる。 In this case, the respective charges of the first capacitor C1a of the first polarity, the second capacitor C2a of the first polarity, the first capacitor C1b of the second polarity, and the second capacitor C2b of the second polarity are expressed by the following equation (equation: (15), Expression (16), Expression (19) to Expression (22).
　Ｑ１ａ＝Ｃ１ａ　×　Ｖｒｅｐ　　　　　　　　　　　・・・（１５）
　Ｑ１ｂ＝Ｃ１ｂ　×　Ｖｒｅｎ　　　　　　　　　　　・・・（１６）
　Ｑ２ａ＝０　　　　　　　　　　　　　　　　　　　　・・・（１９）
　Ｑ２ｂ＝０　　　　　　　　　　　　　　　　　　　　・・・（２０）
　Ｑ３ａ＝Ｃ２ａ　×　Ｖｉｎ　　　　　　　　　　　　・・・（２１）
　Ｑ３ｂ＝Ｃ２ｂ　×　Ｖｉｎ　　　　　　　　　　　　・・・（２２）
　∵Ｃ１ａ＝Ｃ２ａ＝Ｃ３ａ＝Ｃ１ｂ＝Ｃ２ｂ＝Ｃ３ｂ Q1a=C1a×Vrep (15)
Q1b=C1b×Vren (16)
Q2a=0 (19)
Q2b=0 (20)
Q3a=C2a×Vin (21)
Q3b=C2b×Vin (22)
∵C1a=C2a=C3a=C1b=C2b=C3b
　次に、比較判定＆Ｃ２リセット（ステップＳ００５）において、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、積分器アンプＩＰにより、第１極性の第３コンデンサＣ３ａに転送された第１電荷を積分して、第１積分値を生成し、第２極性の第３コンデンサＣ３ｂに転送された第２電荷を積分して、第２積分値を生成する。そして、コンパレータＣＭＰは、第１積分値と第２積分値とを比較し、比較した結果として判定結果Ｄ又は判定結果ＤＮを出力する。また、同時に、第１極性の第２コンデンサＣ２ａと第２極性の第２コンデンサＣ２ｂとがリセットされる。 Next, in the comparison determination & C2 reset (step S005), the Charge Share SAR ADC 100 integrates the first charge transferred to the third capacitor C3a of the first polarity by the integrator amplifier IP to obtain the first integrated value. The second charge generated and transferred to the third capacitor C3b of the second polarity is integrated to generate a second integrated value. Then, the comparator CMP compares the first integral value and the second integral value, and outputs the determination result D or the determination result DN as the comparison result. At the same time, the second capacitor C2a having the first polarity and the second capacitor C2b having the second polarity are reset.
　次に、比較結果フィードバック（ステップＳ００７）において、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、コンパレータＣＭＰにより、第１積分値が第２積分値よりも大きいことを示す判定結果Ｄが出力されたと仮定する。この場合、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、スイッチＤΦ５ａ及びスイッチＤΦ５ｂをオンにする（閉じる）。 Next, in the comparison result feedback (step S007), it is assumed that the Charge Share SAR ADC 100 outputs the determination result D indicating that the first integrated value is larger than the second integrated value by the comparator CMP. In this case, the Charge Share SAR ADC 100 turns on (closes) the switch DΦ5a and the switch DΦ5b.
　電荷再配分（ステップＳ００９）において、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、第１極性の第３コンデンサＣ３ａに蓄積された電荷と第１極性の第１コンデンサＣ１ａに蓄積された電荷とを、リセットされた第１極性の第２コンデンサＣ２ａに再配分する。同時に、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、第２極性の第３コンデンサＣ３ｂに蓄積された電荷と第２極性の第１コンデンサＣ１ｂに蓄積された電荷とを、リセットされた第２極性の第２コンデンサＣ２ｂに再配分する。 In the charge redistribution (step S009), the Charge Share SAR ADC 100 resets the charge accumulated in the third capacitor C3a of the first polarity and the charge accumulated in the first capacitor C1a of the first polarity to the first reset state. It is redistributed to the polar second capacitor C2a. At the same time, the Charge Share SAR ADC 100 transfers the electric charge accumulated in the second capacitor C3b of the second polarity and the electric charge accumulated in the first capacitor C1b of the second polarity to the second capacitor C2b of the second polarity reset. Redistribute.
　この場合、第１極性の第１コンデンサＣ１ａ、第１極性の第２コンデンサＣ２ａ、第１極性の第３コンデンサＣ３ａ、第２極性の第１コンデンサＣ１ｂ、第２極性の第２コンデンサＣ２ｂ、第２極性の第３コンデンサＣ３ｂの各電荷は、次式（式（２３）から式（３０））のようになる。 In this case, the first capacitor C1a having the first polarity, the second capacitor C2a having the first polarity, the third capacitor C3a having the first polarity, the first capacitor C1b having the second polarity, the second capacitor C2b having the second polarity, and the second capacitor C2b The respective charges of the third capacitor C3b having the polarity are expressed by the following formulas (formula (23) to formula (30)).
　Ｑ１ａ　＝　Ｃ１ａ　×　Ｖｒｅｆｐ／２　　　　　　　・・・（２３）
　Ｑ１ｂ　＝　Ｃ１ｂ　×　Ｖｒｅｆｎ／２　　　　　　　・・・（２４）
　Ｑ２ａ　＝　Ｃ１ａ　×　Ｖｒｅｆｐ／２　　　　　　　・・・（２５）
　Ｑ２ｂ　＝　Ｃ１ｂ　×　Ｖｒｅｆｎ／２　　　　　　　・・・（２６）
　Ｑ３ａ　＝　Ｃ２ａ　×　Ｖｉｐ　－　Ｃ１ａ　×　Ｖｒｅｆｐ／２
　　　　　　　　　　　　　　　　　　　　　　　　　　　・・・（２７）
　Ｑ３ｂ　＝　Ｃ２ｂ　×　Ｖｉｎ　－　Ｃ１ｂ　×　Ｖｒｅｆｎ／２
　　　　　　　　　　　　　　　　　　　　　　　　　　　・・・（２８）
　Ｖｏｐ　＝　Ｑ３ａ／Ｃ３ａ　＝　Ｖｉｐ　－　Ｖｒｅｆｐ／２
　　　　　　　　　　　　　　　　　　　　　　　　　　　・・・（２９）
　Ｖｏｎ　＝　Ｑ３ｂ／Ｃ３ｂ　＝　Ｖｉｎ　－　Ｖｒｅｆｎ／２
　　　　　　　　　　　　　　　　　　　　　　　　　　　・・・（３０）
　∵Ｃ１ａ＝Ｃ２ａ＝Ｃ３ａ＝Ｃ１ｂ＝Ｃ２ｂ＝Ｃ３ｂ　 Q1a=C1a×Vrefp/2 (23)
Q1b=C1b×Vrefn/2 (24)
Q2a=C1a×Vrefp/2 (25)
Q2b=C1b×Vrefn/2 (26)
Q3a=C2a×Vip−C1a×Vrefp/2
(27)
Q3b=C2b×Vin−C1b×Vrefn/2
(28)
Vop=Q3a/C3a=Vip−Vrefp/2
...(29)
Von = Q3b/C3b = Vin-Vrefn/2
...(30)
∵C1a=C2a=C3a=C1b=C2b=C3b
　これに対し、比較結果フィードバック（ステップＳ００７）において、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、コンパレータＣＭＰにより、第１積分値が第２積分値よりも略同等以下であることを示す判定結果ＤＮが出力されたと仮定する。この場合、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、スイッチＤＮΦ５ａ及びスイッチＤＮΦ５ｂをオンにする（閉じる）。 On the other hand, in the comparison result feedback (step S007), it is assumed that the Charge Share SAR ADC 100 outputs the determination result DN indicating that the first integrated value is substantially equal to or less than the second integrated value by the comparator CMP. To do. In this case, the Charge Share SAR ADC 100 turns on (closes) the switch DNΦ5a and the switch DNΦ5b.
　電荷再配分（ステップＳ００９）において、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、第１極性の第３コンデンサＣ３ａに蓄積された電荷と第２極性の第１コンデンサＣ１ｂに蓄積された電荷とを、リセットされた第１極性の第２コンデンサＣ２ａに再配分する。同時に、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、第２極性の第３コンデンサＣ３ｂに蓄積された電荷と第１極性の第１コンデンサＣ１ａに蓄積された電荷とを、リセットされた第２極性の第２コンデンサＣ２ｂに再配分する。 In the charge redistribution (step S009), the Charge Share SAR ADC 100 resets the charge accumulated in the third capacitor C3a of the first polarity and the charge accumulated in the first capacitor C1b of the second polarity to the first reset state. It is redistributed to the polar second capacitor C2a. At the same time, the Charge Share SAR ADC 100 transfers the charge accumulated in the third capacitor C3b of the second polarity and the charge accumulated in the first capacitor C1a of the first polarity to the second capacitor C2b of the reset second polarity. Redistribute.
　この場合、第１極性の第１コンデンサＣ１ａ、第１極性の第２コンデンサＣ２ａ、第１極性の第３コンデンサＣ３ａ、第２極性の第１コンデンサＣ１ｂ、第２極性の第コンデンサＣ２ｂ、第２極性の第３コンデンサＣ３ｂの各電荷は、次式（式（３１）から式（３８））のようになる。 In this case, the first capacitor C1a of the first polarity, the second capacitor C2a of the first polarity, the third capacitor C3a of the first polarity, the first capacitor C1b of the second polarity, the second capacitor C2b of the second polarity, the second polarity. The respective charges of the third capacitor C3b are expressed by the following formulas (formula (31) to formula (38)).
　Ｑ１ａ　＝　Ｃ１ａ　×　Ｖｒｅｆｐ／２　　　　　　　・・・（３１）
　Ｑ１ｂ　＝　Ｃ１ｂ　×　Ｖｒｅｆｎ／２　　　　　　　・・・（３２）
　Ｑ２ａ　＝　Ｃ１ｂ　×　Ｖｒｅｆｎ／２　　　　　　　・・・（３３）
　Ｑ２ｂ　＝　Ｃ１ａ　×　Ｖｒｅｆｐ／２　　　　　　　・・・（３４）
　Ｑ３ａ　＝　Ｃ２ａ　×　Ｖｉｐ　－　Ｃ１ｂ　×　Ｖｒｅｆｎ／２
　　　　　　　　　　　　　　　　　　　　　　　　　　　・・・（３５）
　Ｑ３ｂ　＝　Ｃ２ｂ　×　Ｖｉｎ　－　Ｃ１ａ　×　Ｖｒｅｆｐ／２
　　　　　　　　　　　　　　　　　　　　　　　　　　　・・・（３６）
　Ｖｏｐ　＝　Ｑ３ａ／Ｃ３ａ　＝　Ｖｉｐ－（Ｖｒｅｆｎ／２）　　
　　　　　　　　　　　　　　　　　　　　　　　　　　　・・・（３７）
　Ｖｏｎ　＝　Ｑ３ｂ／Ｃ３ｂ　＝　Ｖｉｎ－（Ｖｒｅｆｐ／２）
　　　　　　　　　　　　　　　　　　　　　　　　　　　・・・（３８）
　∵Ｃ１ａ＝Ｃ２ａ＝Ｃ３ａ＝Ｃ１ｂ＝Ｃ２ｂ＝Ｃ３ｂ　 Q1a=C1a×Vrefp/2 (31)
Q1b=C1b×Vrefn/2 (32)
Q2a=C1b×Vrefn/2 (33)
Q2b=C1a×Vrefp/2 (34)
Q3a=C2a×Vip−C1b×Vrefn/2
...(35)
Q3b=C2b×Vin−C1a×Vrefp/2
...(36)
Vop = Q3a/C3a = Vip-(Vrefn/2)
...(37)
Von = Q3b/C3b = Vin-(Vrefp/2)
(38)
∵C1a=C2a=C3a=C1b=C2b=C3b
　Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、所定の分解能のビット数が得られるまで（ステップＳ０１１）、コンパレータＣＭＰが第１積分値と第２積分値とを比較することと（ステップＳ００５のＹｅｓ）、第１極性の第２コンデンサＣ２ａと第２極性の第２コンデンサＣ２ｂとがリセットされることと（ステップＳ００５）、リセットされた、第１極性の第２コンデンサＣ２ａと第２極性の第２コンデンサＣ２ｂとに再配分することと（ステップＳ００７及びステップＳ００９）、を繰り返す（ステップＳ０１３）。 In the Charge Share SAR ADC 100, the comparator CMP compares the first integrated value and the second integrated value (Yes in step S005) until the number of bits with a predetermined resolution is obtained (step S011). The second capacitor C2a and the second capacitor C2b having the second polarity are reset (step S005), and the redistributed to the reset second capacitor C2a having the first polarity and the second capacitor C2b having the second polarity. This is repeated (step S007 and step S009) (step S013).
　Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、ステップＳ００５からステップＳ００９を繰り返すことにより、（ＭＳＢ－１）ｂｉｔ以降の分解能を取得する。 The Charge Share SAR ADC 100 acquires the resolution after (MSB-1) bit by repeating steps S005 to S009.
　そして、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、所定の分解能のビット数が得られた後、フィルタ回路ＦＬＴに、第１極性の第２コンデンサＣ２ａに再配分して第１極性の第３コンデンサＣ３ａに蓄積された電荷と、第２極性の第２コンデンサＣ２ｂに再配分して第２極性の第３コンデンサＣ３ｂに蓄積された電荷とを、残差電圧として入力する。 Then, the Charge Share SAR ADC 100, after obtaining the number of bits of the predetermined resolution, is redistributed to the second capacitor C2a of the first polarity and accumulated in the third capacitor C3a of the first polarity in the filter circuit FLT. The charges and the charges redistributed to the second capacitor C2b of the second polarity and accumulated in the third capacitor C3b of the second polarity are input as the residual voltage.
　図２は、本技術に係る第１の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００が、スイッチΦ６（スイッチΦ６ａ及びスイッチΦ６ｂ）をオンにする（閉じる）タイミングを示したタイミングチャートである。スイッチΦ６（スイッチΦ６ａ及びスイッチΦ６ｂ）は、所定の分解能の最下位ビットの判定結果をＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００にフィードバックし、電荷再配分するタイミングの前後でオンになる（閉じられる）。 FIG. 2 is a timing chart showing a timing at which the Charge Share SAR ADC 100 according to the first embodiment of the present technology turns on (closes) the switch Φ6 (the switch Φ6a and the switch Φ6b). The switch Φ6 (the switch Φ6a and the switch Φ6b) feeds back the determination result of the least significant bit with a predetermined resolution to the Charge Share SAR ADC 100, and turns on (closes) before and after the timing of charge redistribution.
　換言すれば、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、スイッチΦ６（スイッチΦ６ａ及びスイッチΦ６ｂ）を、最下位ビットの再配分後の残差電圧をフィルタ回路ＦＬＴでサンプリングする際にオンにする（閉じる）。 In other words, the Charge Share SAR ADC 100 turns on (closes) the switch Φ6 (switch Φ6a and switch Φ6b) when the residual voltage after the redistribution of the least significant bit is sampled by the filter circuit FLT.
　図２では、所定の分解能の最下位ビット（ＬＳＢ　ｂｉｔ）について、コンパレータＣＭＰが、第１積分値と第２積分値とを比較し、第１極性の第２コンデンサＣ２ａと第２極性の第２コンデンサＣ２ｂとがリセットされた後、当該第１極性の第２コンデンサＣ２ａと第２極性の第２コンデンサＣ２ｂとについて再配分が完了するまでの間に、フィルタ回路ＦＬＴが、残差電圧のサンプリングを開始することを示している。 In FIG. 2, for the least significant bit (LSB bit) of a predetermined resolution, the comparator CMP compares the first integrated value and the second integrated value, and the second capacitor C2a of the first polarity and the second capacitor C2a of the second polarity. After the capacitor C2b is reset and before the redistribution of the second capacitor C2a of the first polarity and the second capacitor C2b of the second polarity is completed, the filter circuit FLT samples the residual voltage. Indicates that it is about to start.
　すなわち、スイッチΦ６（スイッチΦ６ａ及びスイッチΦ６ｂ）は、所定の分解能の最下位ビット（ＬＳＢ　ｂｉｔ）について、スイッチΦ２（スイッチΦ２ａ及びスイッチΦ２ｂ）及びスイッチΦ３（スイッチΦ３ａ及びスイッチΦ３ｂ）がオンとなり（閉じて）、第１極性の第２コンデンサＣ２ａと第２極性の第２コンデンサＣ２ｂとがリセットされてから、スイッチΦ４（スイッチΦ４ａ及びスイッチΦ４ｂ）がオフするまでに（開くまでに）、オンになればよい（閉じればよい）。 That is, the switch Φ6 (switch Φ6a and switch Φ6b) turns on (closes) the switch Φ2 (switch Φ2a and switch Φ2b) and switch Φ3 (switch Φ3a and switch Φ3b) for the least significant bit (LSB bit) of a predetermined resolution. Then, after the second capacitor C2a having the first polarity and the second capacitor C2b having the second polarity are reset, the switch Φ4 (the switch Φ4a and the switch Φ4b) must be turned on (by opening) before being turned off. All you have to do is close it.
　また、積分器アンプＩＰは、フィルタ回路ＦＬＴの入力に対してバッファの役割を果たしているため、スイッチΦ６（スイッチΦ６ａ及びスイッチΦ６ｂ）をオンする（閉じる）タイミングには、自由度がある。そのため、電圧分解能やアンプバッファリング能力を考慮して、セトリングが最短となるように、スイッチΦ６（スイッチΦ６ａ及びスイッチΦ６ｂ）をオンにするタイミング（閉じるタイミング）を最適化することができる。 Further, since the integrator amplifier IP plays the role of a buffer for the input of the filter circuit FLT, there is a degree of freedom in the timing of turning on (closing) the switch Φ6 (switch Φ6a and switch Φ6b). Therefore, in consideration of the voltage resolution and the amplifier buffering ability, the timing (close timing) for turning on the switch Φ6 (switch Φ6a and switch Φ6b) can be optimized so that the settling becomes shortest.
　次に、図１に示すＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００のビヘイビアモデルを、図３に示す。図３は、本技術に係る第１の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００のノイズビヘイビアモデルを示した図である。 Next, FIG. 3 shows a behavior model of the Charge Share SAR ADC 100 shown in FIG. FIG. 3 is a diagram showing a noise behavior model of the Charge Share SAR ADC 100 according to the first embodiment of the present technology.
　Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００のノイズビヘイビアモデルは、減算器ＳＢ、積分器ＩＴＧ、フィルタ回路ＦＬＴ、加算器ＡＤ、及びＳＡＲ量子化器ＳＱを備えている。そして、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００のノイズ伝達関数ＮＴＦ（ｚ）は、次式（式（３９））で表される。 The noise behavior model of the Charge Share SAR ADC 100 includes a subtractor SB, an integrator ITG, a filter circuit FLT, an adder AD, and a SAR quantizer SQ. Then, the noise transfer function NTF(z) of the Charge Share SAR ADC 100 is expressed by the following equation (equation (39)).
Figure JPOXMLDOC01-appb-M000005
Figure JPOXMLDOC01-appb-M000005
　これにより、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、ノイズシェーピングの次数を高次にすることができる。例えば、積分器ＩＴＧの伝達関数Ｌ１（ｚ）は、式（１３）と同様である。 As a result, the Charge Share SAR ADC 100 can increase the order of noise shaping. For example, the transfer function L 1 (z) of the integrator ITG is the same as the expression (13).
　一方、フィルタ回路ＦＬＴについては、いくつかの実施形態が想定される。まず、フィルタ回路ＦＬＴの回路トポロジとして考えらえるのは、図１２示されたＣｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣに実装されるフィルタ回路ＦＬＴ１をそのまま適用することである。この場合、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、フィルタ回路ＦＬＴ１が、オペアンプ（積分器アンプＩＰＦ）を含んで構成される、アクティブ型のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣを構成する。 On the other hand, with regard to the filter circuit FLT, some embodiments are assumed. First, what can be considered as the circuit topology of the filter circuit FLT is to directly apply the filter circuit FLT1 implemented in the Charge Redistribution SAR ADC shown in FIG. In this case, the Charge Share SAR ADC 100 constitutes an active Charge Share SAR ADC in which the filter circuit FLT1 includes an operational amplifier (integrator amplifier IPF).
　図４は、本技術に係る第１の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００が、図１２に示されたフィルタ回路ＦＬＴ１を有している場合の回路図を示したものである。この場合のフィルタ回路ＦＬＴ１の伝達関数Ｌ２（ｚ）とノイズ伝達関数ＮＴＦ（ｚ）は、次式（式（４０）、式（４１））で表される。 FIG. 4 is a circuit diagram in the case where the Charge Share SAR ADC 100 according to the first embodiment of the present technology has the filter circuit FLT1 shown in FIG. The transfer function L 2 (z) and the noise transfer function NTF(z) of the filter circuit FLT1 in this case are represented by the following expressions (Expression (40) and Expression (41)).
Figure JPOXMLDOC01-appb-M000006
Figure JPOXMLDOC01-appb-M000006
Figure JPOXMLDOC01-appb-M000007
Figure JPOXMLDOC01-appb-M000007
　よって、アクティブ型のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００で使用している積分器ＩＴＧをノイズシェーピングに流用することにより、フィルタ回路ＦＬＴ１内の積分器アンプＩＰＦ１つでノイズシェーピングを２次化することができる。 Therefore, by diverting the integrator ITG used in the active Charge Share SAR ADC 100 for noise shaping, it is possible to make noise shaping secondary with one integrator amplifier IPF in the filter circuit FLT1.
　図５は、ノイズシェーピングにより、低周波帯域に位置する量子化雑音を高周波帯域に移動させることを示した説明図である。図５に示されるように、ノイズシェーピングは、周波数帯で一様に分布する量子化雑音とコンパレータ雑音を、低周波帯域で減少させるとともに高周波帯域で上昇させることができる。なお、図５では、１次のノイズシェーピングを示している。 FIG. 5 is an explanatory diagram showing that quantization noise located in a low frequency band is moved to a high frequency band by noise shaping. As shown in FIG. 5, the noise shaping can reduce the quantization noise and the comparator noise that are uniformly distributed in the frequency band in the low frequency band and increase them in the high frequency band. Note that FIG. 5 shows first-order noise shaping.
　図６は、次数が高くなると、ノイズシェーピングの効果が高くなることを示した説明図である。なお、図６では、次数を「ｑ」とする。図６に示されるように、１次で示されたノイズ伝達関数を高次化できると、ノイズを除去する効果を高めることができることを示している。例えば、２次化できた場合には、１次の場合よりも、より多くの雑音成分（ノイズ成分）を高周波帯域に移動させることができるので、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００の出力に対して、ローパスフィルタを適用することにより雑音成分（ノイズ成分）をカットすることができる。 FIG. 6 is an explanatory diagram showing that the effect of noise shaping becomes higher as the order becomes higher. In FIG. 6, the order is “q”. As shown in FIG. 6, it is shown that if the noise transfer function represented by the first order can be increased in order, the effect of removing noise can be enhanced. For example, if the secondary can be achieved, more noise components (noise components) can be moved to the high frequency band than in the case of the primary, so a low-pass filter is applied to the output of the Charge Share SAR ADC 100. The noise component (noise component) can be cut by applying.
　以上説明したように、本技術に係る第１の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、積分器ＩＴＧをノイズシェーピングに流用することができるので、フィルタ回路ＦＬＴが有する積分器アンプＩＰＦ１つで、ノイズシェーピングを２次化することができる。 As described above, in the Charge Share SAR ADC 100 according to the first embodiment of the present technology, the integrator ITG can be diverted for noise shaping, so that the noise shaping can be performed by one integrator amplifier IPF included in the filter circuit FLT. Can be quadratic.
　これにより、本技術に係る第１の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００は、高精度に雑音成分（ノイズ成分）を除去することができる。 With this, the Charge Share SAR ADC 100 according to the first embodiment of the present technology can remove a noise component (noise component) with high accuracy.
＜３．第２の実施形態（逐次比較型ＡＤコンバータの例２）＞
　本技術に係る第２の実施形態の逐次比較型ＡＤコンバータは、フィルタ回路が、積分器アンプによって駆動される、逐次比較型ＡＤコンバータである。 <3. Second Embodiment (Example 2 of Successive Approximation Type AD Converter)>
The successive approximation type AD converter according to the second embodiment of the present technology is a successive approximation type AD converter in which a filter circuit is driven by an integrator amplifier.
　図７に、本技術に係る第２の実施形態の逐次比較型ＡＤコンバータの一例であるＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００ａを示す。図７は、本技術を適用したＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００ａの構成例を示すブロック図である。なお、上述した構成と同一の構成要素については同一の符号を付し、説明を適宜、省略する。なお、特に断りがない限り、「左」とは、図７中の左方向を意味し、「上」とは、図７中の上方向を意味するものとする。 FIG. 7 shows a Charge Share SAR ADC 100a that is an example of a successive approximation type AD converter according to the second embodiment of the present technology. FIG. 7 is a block diagram showing a configuration example of the Charge Share SAR ADC 100a to which the present technology is applied. The same components as those described above are designated by the same reference numerals, and description thereof will be omitted as appropriate. Unless otherwise specified, “left” means the left direction in FIG. 7, and “up” means the upper direction in FIG. 7.
　図７に示された第２の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００ａが、図１に示された第１の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００と異なる点は、フィルタ回路ＦＬＴ２が、バッファＡｂｕｆと、スイッチΦ６（スイッチΦ６ａ及びスイッチΦ６ｂ）とを有さない点である。 The Charge Share SAR ADC 100a of the second embodiment shown in FIG. 7 differs from the Charge Share SAR ADC 100 of the first embodiment shown in FIG. 1 in that the filter circuit FLT2 is a buffer Abuf and a switch Φ6. (Switch Φ6a and switch Φ6b) is not provided.
　第２の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００ａは、積分器アンプＩＰがフィルタ回路ＦＬＴ２の入力に対してバッファとして機能するため、フィルタ回路ＦＬＴ２における入力バッファを削除することができる。また、フィルタ回路ＦＬＴ２内のサンプリング容量（コンデンサＣ５ａ、コンデンサＣ５ｂ）の左側に位置するスイッチΦ７～スイッチΦ１２（スイッチΦ７ａ～スイッチΦ１２ａ、及びスイッチΦ７ｂ～スイッチΦ１２ｂ）をサンプリングスイッチとして使うことができるため、スイッチΦ６（スイッチΦ６ａ及びスイッチΦ６ｂ）を削除することができる。 In the Charge Share SAR ADC 100a of the second embodiment, since the integrator amplifier IP functions as a buffer for the input of the filter circuit FLT2, the input buffer in the filter circuit FLT2 can be deleted. Further, the switches Φ7 to Φ12 (switches Φ7a to Φ12a and switches Φ7b to Φ12b) located on the left side of the sampling capacitors (capacitors C5a and C5b) in the filter circuit FLT2 can be used as sampling switches. The switch Φ6 (switch Φ6a and switch Φ6b) can be deleted.
　この場合のフィルタ回路ＦＬＴ２の伝達関数Ｌ２（ｚ）とノイズ伝達関数ＮＴＦ（ｚ）は、次式（式（４２）、式（４３））で表される。 The transfer function L 2 (z) and the noise transfer function NTF(z) of the filter circuit FLT2 in this case are represented by the following expressions (Expression (42) and Expression (43)).
Figure JPOXMLDOC01-appb-M000008
Figure JPOXMLDOC01-appb-M000008
Figure JPOXMLDOC01-appb-M000009
Figure JPOXMLDOC01-appb-M000009
　式（４３）に示されるように、ノイズ伝達関数ＮＴＦ（ｚ）の分子の（１－ｚ－１）２は、維持されている。これにより、本技術に係る第２の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００ａは、ノイズシェーピングの次数を高次で維持することができる。 As shown in equation (43), the numerator (1-z −1 ) 2 of the noise transfer function NTF(z) is maintained. As a result, the Charge Share SAR ADC 100a according to the second embodiment of the present technology can maintain the order of noise shaping at a high order.
＜４．第３の実施形態（逐次比較型ＡＤコンバータの例３）＞
　本技術に係る第３の実施形態の逐次比較型ＡＤコンバータは、フィルタ回路が、コンデンサを含み、オペアンプを含まないで構成されるパッシブ型である、逐次比較型ＡＤコンバータである。 <4. Third Embodiment (Example 3 of Successive Approximation Type AD Converter)>
The successive approximation type AD converter according to the third embodiment of the present technology is a successive approximation type AD converter in which the filter circuit includes a capacitor and does not include an operational amplifier.
　図８に、本技術に係る第３の実施形態の逐次比較型ＡＤコンバータの一例であるＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００ｂを示す。図８は、本技術を適用したＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００ｂの構成例を示すブロック図である。なお、上述した構成と同一の構成要素については同一の符号を付し、説明を適宜、省略する。なお、特に断りがない限り、「左」とは、図８中の左方向を意味し、「上」とは、図８中の上方向を意味するものとする。 FIG. 8 shows a Charge Share SAR ADC 100b that is an example of the successive approximation type AD converter according to the third embodiment of the present technology. FIG. 8 is a block diagram showing a configuration example of the Charge Share SAR ADC 100b to which the present technology is applied. The same components as those described above are designated by the same reference numerals, and description thereof will be omitted as appropriate. Unless otherwise specified, “left” means leftward in FIG. 8 and “upper” means upward in FIG. 8.
　図８に示された第３の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００ｂが、図１に示された第１の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００と異なる点は、フィルタ回路ＦＬＴ３が、コンデンサ（コンデンサＣＡａ、コンデンサＣＡｂ、コンデンサＣＢａ、及びコンデンサＣＢｂ）を含み、オペアンプを含まないで構成されるパッシブ型である点である。 The difference between the Charge Share SAR ADC 100b of the third embodiment shown in FIG. 8 and the Charge Share SAR ADC 100 of the first embodiment shown in FIG. 1 is that the filter circuit FLT3 is a capacitor (capacitor CAa, capacitor). CAb, capacitor CBa, and capacitor CBb) are included and the operational amplifier is not included.
　図８Ａには、第３の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００ｂの回路図を示し、図８Ｂには、フィルタ回路ＦＬＴ３の回路図を示し、図８Ｃには、フィルタ回路ＦＬＴ３のタイミングチャートを示す。 FIG. 8A shows a circuit diagram of the Charge Share SAR ADC 100b of the third embodiment, FIG. 8B shows a circuit diagram of the filter circuit FLT3, and FIG. 8C shows a timing chart of the filter circuit FLT3.
　Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００ｂのフィルタ回路ＦＬＴ３は、コンデンサＣＡａ、コンデンサＣＡｂ、コンデンサＣＢａ、コンデンサＣＢｂ、スイッチΦ１３（スイッチΦ１３ａ及びスイッチΦ１３ｂ）、スイッチΦ１４（スイッチΦ１４ａ及びスイッチΦ１４ｂ）を備えて構成されている。 The filter circuit FLT3 of the Charge Share SAR ADC 100b is configured to include a capacitor CAa, a capacitor CAb, a capacitor CBa, a capacitor CBb, a switch Φ13 (switch Φ13a and switch Φ13b), and a switch Φ14 (switch Φ14a and switch Φ14b).
　ここで、例えば、図１１に示されたＣｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣ１０１のフィルタ回路ＦＬＴ１をパッシブ型にした場合、容量アレイ（複数のコンデンサＣＰ０～ＣＰ６）とフィルタ回路ＦＬＴ１の容量とにおいて、電荷再配分が起こる。このため、Ｃｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣ１０１では、ＳＡＲ　ＡＤＣ変換後の残差電圧が減衰する。 Here, for example, when the filter circuit FLT1 of the Charge Redistribution SAR ADC 101 shown in FIG. 11 is a passive type, charge redistribution occurs in the capacitance array (capacitors CP0 to CP6) and the capacitance of the filter circuit FLT1. .. Therefore, in the Charge Redistribution SAR ADC 101, the residual voltage after SAR ADC conversion is attenuated.
　これに対し、本技術に係る第３の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００ｂは、積分器アンプＩＰがフィルタ回路ＦＬＴ３の入力に対してバッファとなっているため、ＳＡＲ　ＡＤＣ変換後の残差電圧が減衰することがない。具体的には、第１極性の第３コンデンサＣ３ａ及び第２極性の第３コンデンサＣ３ｂと、コンデンサＣＡａ及びコンデンサＣＡｂとにおいて電荷再配分が起らないため、ＳＡＲ　ＡＤＣ変換後の残差電圧に減衰がない。 On the other hand, in the Charge Share SAR ADC 100b according to the third embodiment of the present technology, since the integrator amplifier IP serves as a buffer for the input of the filter circuit FLT3, the residual voltage after SAR ADC conversion is attenuated. There is nothing to do. Specifically, since charge redistribution does not occur between the third capacitor C3a of the first polarity and the third capacitor C3b of the second polarity, and the capacitors CAa and CAb, the residual voltage after SAR ADC conversion is attenuated. There is no.
　このため、ＳＮＤＲは、本技術に係る第３の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００ｂは、従来のＣｈａｒｇｅ　Ｒｅｄｉｓｔｒｉｂｕｔｉｏｎ　ＳＡＲ　ＡＤＣ１０１の回路構成よりも有利な値となる。また、第３の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００ｂは、フィルタ回路ＦＬＴ３のサンプリングが電荷再配分に依存しないため、コンデンサＣＡａ及びコンデンサＣＡｂを、ノイズの要求仕様が満たす範囲で小さくすることができる。 Therefore, the SNDR of the Charge Share SAR ADC 100b according to the third embodiment of the present technology has a more advantageous value than the circuit configuration of the conventional Charge Redistribution SAR ADC 101. Further, in the Charge Share SAR ADC 100b of the third embodiment, the sampling of the filter circuit FLT3 does not depend on the charge redistribution, so that the capacitors CAa and CAb can be reduced within the range where the noise required specifications are satisfied.
　この場合のフィルタ回路ＦＬＴ３の伝達関数Ｌ２（ｚ）とノイズ伝達関数ＮＴＦ（ｚ）は、次式（式（４４）、式（４５））で表される。 The transfer function L 2 (z) and the noise transfer function NTF(z) of the filter circuit FLT3 in this case are represented by the following expressions (Expression (44) and Expression (45)).
Figure JPOXMLDOC01-appb-M000010
Figure JPOXMLDOC01-appb-M000010
Figure JPOXMLDOC01-appb-M000011
Figure JPOXMLDOC01-appb-M000011
　このように、第３の実施形態のＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００ｂは、フィルタ回路ＦＬＴ３の伝達関数Ｌ２（ｚ）が、１次パッシブ型で、ノイズ伝達関数ＮＴＦ（ｚ）が、２次に近いノイズシェーピング特性を得ることができる。 As described above, in the Charge Share SAR ADC 100b of the third embodiment, the transfer function L 2 (z) of the filter circuit FLT3 is a first-order passive type, and the noise transfer function NTF(z) is near second-order noise shaping. The characteristics can be obtained.
＜５．第４の実施形態（ＩｏＴセンサの例）＞
　本技術に係る第４の実施形態のＩｏＴ（Ｉｎｔｅｒｎｅｔ　ｏｆ　Ｔｈｉｎｇｓ）センサは、逐次比較型ＡＤコンバータが搭載されて、逐次比較型ＡＤコンバータが、第１極性の第１コンデンサと、第１極性の第２コンデンサと、第１極性の第３コンデンサと、第２極性の第１コンデンサと、第２極性の第２コンデンサと、第２極性の第３コンデンサと、積分器アンプと、コンパレータと、フィルタ回路と、を備える、ＩｏＴセンサである。また、本技術に係る第４の実施形態のＩｏＴｔセンサは、本技術に係る第１乃至第３の実施形態のいずれか１つの逐次比較型ＡＤコンバータが搭載されたＩｏＴセンサであってもよい。 <5. Fourth embodiment (example of IoT sensor)>
The IoT (Internet of Things) sensor of the fourth embodiment according to the present technology is equipped with a successive approximation type AD converter, and the successive approximation type AD converter includes a first capacitor having a first polarity and a first capacitor having a first polarity. 2 capacitors, 1st polarity 3rd capacitor, 2nd polarity 1st capacitor, 2nd polarity 2nd capacitor, 2nd polarity 3rd capacitor, integrator amplifier, comparator, and filter circuit And IoT sensor. Further, the IoT sensor of the fourth embodiment according to the present technology may be an IoT sensor equipped with any one of the successive approximation type AD converters of the first to third embodiments of the present technology.
　例えば、上述で説明されたＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００を、ＩｏＴセンサに適用することができる。図９に、その一例として、ＩｏＴセンサ２００の概略構成を示す。図９は、本技術を適用したＩｏＴセンサの構成例を示すブロック図である。 For example, the Charge Share SAR ADC 100 described above can be applied to the IoT sensor. FIG. 9 shows a schematic configuration of the IoT sensor 200 as an example. FIG. 9 is a block diagram showing a configuration example of an IoT sensor to which the present technology is applied.
　図９に示される第４の実施形態のＩｏＴセンサ２００は、センサ素子Ｓ１、センサ素子Ｓ２・・・センサ素子ＳＮ、ＭＵＸ（Ｍｕｌｔｉｐｌｅｘｅｒ）２１０、ＰＧＡ　ＡＭＰ（Ｐｒｏｇｒａｍｍａｂｌｅ　Ｇａｉｎ　Ａｍｐｌｉｆｉｅｒ）２２０、Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００（図９では、ＡＤＣ１００と表記する。）、信号処理ブロック２３０、ＲＦ２４０、アンテナ２５０、ＬＣＤ　Ｄｒｉｖｅｒ２６０、ディスプレイ２７０、Ｐｏｗｅｒ　Ｍａｎａｇｅｍｅｎｔ２８０、及び電源２９０を有している。 The IoT sensor 200 according to the fourth embodiment shown in FIG. 9 includes a sensor element S1, a sensor element S2... A sensor element SN, a MUX (Multiplexer) 210, a PGA AMP (Programmable Gain Amplifier) 220, and a Charge Share SAR ADC 100 ( In FIG. 9, it is represented as ADC 100.), a signal processing block 230, an RF 240, an antenna 250, an LCD driver 260, a display 270, a Power Management 280, and a power supply 290.
　ＩｏＴセンサ２００は、多数のセンサ素子（センサ素子Ｓ１、センサ素子Ｓ２・・・センサ素子ＳＮ）を有している。ＩｏＴセンサ２００は、センサ素子として、例えば、センサ素子Ｓ１が加速度センサであり、センサ素子Ｓ２がジャイロセンサとして、複数のセンサ素子を備えることができる。また、他のセンサとして、磁気センサ、温度センサ、気圧センサ、感圧センサなどを備えるようにしてもよい。 The IoT sensor 200 has a large number of sensor elements (sensor element S1, sensor element S2... Sensor element SN). The IoT sensor 200 can include a plurality of sensor elements as sensor elements, for example, the sensor element S1 is an acceleration sensor and the sensor element S2 is a gyro sensor. Further, as other sensors, a magnetic sensor, a temperature sensor, an atmospheric pressure sensor, a pressure sensitive sensor, etc. may be provided.
　ＭＵＸ２１０は、複数のセンサ（センサ素子Ｓ１、センサ素子Ｓ２・・・センサ素子ＳＮ）によって取得したデータ（アナログ信号）の中から選択するマルチプレクサである。 The MUX 210 is a multiplexer that selects from data (analog signals) acquired by a plurality of sensors (sensor element S1, sensor element S2... Sensor element SN).
　ＰＧＡ　ＡＭＰ２２０は、ユーザにより必要なゲインを調整できる増幅器である。 The PGA AMP 220 is an amplifier that can adjust the gain required by the user.
　Ｃｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００（図９のＡＤＣ１００）は、本技術に係る第１の実施形態で説明した逐次比較型ＡＤコンバータである。 The Charge Share SAR ADC 100 (ADC 100 in FIG. 9) is the successive approximation type AD converter described in the first embodiment according to the present technology.
　信号処理ブロック２３０は、ＤＳＰ（Ｄｉｇｉｔａｌ　Ｓｉｇｎａｌ　Ｐｒｏｃｅｓｓｏｒ）やＦＰＧＡ（Ｆｉｅｌｄ　Ｐｒｏｇｒａｍｍａｂｌｅ　Ｇａｔｅ　Ａｒｒａｙ）などで構成され、データ（デジタル信号）を処理する信号処理部である。 The signal processing block 230 is a signal processing unit configured with a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), and the like, and processes data (digital signals).
　ＲＦ（Ｒａｄｉｏ　Ｆｒｅｑｕｅｎｃｙ）２４０は、高周波で無線通信を行う無線回路である。ＲＦ２４０は、アンテナ２５０を介して、信号処理ブロック２３０で処理された信号（デジタル信号）を、図示しない通信端末に送信する。 RF (Radio Frequency) 240 is a wireless circuit that performs wireless communication at a high frequency. The RF 240 transmits the signal (digital signal) processed by the signal processing block 230 to the communication terminal (not shown) via the antenna 250.
　ＬＣＤ　Ｄｒｉｖｅｒ２６０は、例えば、液晶ディスプレイで構成されるディスプレイ２７０を駆動するモジュールである。ＬＣＤ　Ｄｒｉｖｅｒ２６０は、信号処理ブロック２３０で処理された信号をディスプレイ２６０に表示させる。 The LCD Driver 260 is a module that drives a display 270 including, for example, a liquid crystal display. The LCD Driver 260 causes the display 260 to display the signal processed by the signal processing block 230.
　Ｐｏｗｅｒ　Ｍａｎａｇｅｍｅｎｔ２８０は、電源２９０から供給される電力を信号処理ブロック２３０に供給する。 The Power Management 280 supplies the power supplied from the power supply 290 to the signal processing block 230.
　ＩｏＴセンサ２００は、このような構成を備えることにより、多数のセンサ素子（センサ素子Ｓ１、センサ素子Ｓ２・・・センサ素子ＳＮ）で取得したデータ（アナログ信号）をデジタル信号に変換した後に、所定の信号処理を実行し、図示しない通信端末に送信することができるようになっている。 Since the IoT sensor 200 has such a configuration, the IoT sensor 200 converts data (analog signal) acquired by a large number of sensor elements (sensor element S1, sensor element S2... It is possible to execute the signal processing of (1) and send it to a communication terminal (not shown).
　なお、本技術に係る第４の実施形態は、上述した実施形態に限定されるものではなく、本技術の要旨を逸脱しない範囲において種々の変更が可能である。 The fourth embodiment according to the present technology is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present technology.
＜６．第５の実施形態（生体センサの例）＞
　本技術に係る第５の実施形態の生体センサは、逐次比較型ＡＤコンバータが搭載されて、逐次比較型ＡＤコンバータが、第１極性の第１コンデンサと、第１極性の第２コンデンサと、第１極性の第３コンデンサと、第２極性の第１コンデンサと、第２極性の第２コンデンサと、第２極性の第３コンデンサと、積分器アンプと、コンパレータと、フィルタ回路と、を備える、生体センサである。また、本技術に係る第５の実施形態の生体センサは、本技術に係る第１乃至第３の実施形態のいずれか１つの逐次比較型ＡＤコンバータが搭載された生体センサであってもよい。 <6. Fifth embodiment (example of biosensor)>
A biosensor according to a fifth embodiment of the present technology is equipped with a successive approximation type AD converter, and the successive approximation type AD converter includes a first capacitor having a first polarity, a second capacitor having a first polarity, and a second capacitor. A third capacitor having one polarity, a first capacitor having second polarity, a second capacitor having second polarity, a third capacitor having second polarity, an integrator amplifier, a comparator, and a filter circuit, It is a biometric sensor. The biosensor of the fifth embodiment according to the present technology may be a biosensor equipped with any one of the successive approximation AD converters of the first to third embodiments of the present technology.
　例えば、上述で説明されたＣｈａｒｇｅ　Ｓｈａｒｅ　ＳＡＲ　ＡＤＣ１００を、生体センサに適用することができる。図１０に、その一例として、生体センサ３００の概略構成を示す。図１０は、本技術を適用した生体センサ３００の構成例を示すブロック図である。なお、図９に示されたＩｏＴセンサと同一の構成については同一の符号を付し、説明を適宜、省略する。 For example, the Charge Share SAR ADC 100 described above can be applied to a biosensor. FIG. 10 shows a schematic configuration of the biosensor 300 as an example thereof. FIG. 10 is a block diagram showing a configuration example of a biosensor 300 to which the present technology is applied. The same components as those of the IoT sensor shown in FIG. 9 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.
　図１０に示された第５の実施形態の生体センサ００が図９に示された第４の実施形態のＩｏＴセンサ２００と異なる点は、ＰＧＡ　ＡＭＰ２２０の代わりにＡｎａｌｏｇ　Ｆｒｏｎｔ－Ｅｎｄ３１０を備えており、信号処理ブロック２３０で信号処理したデータを、Ｓｅｒｉａｌ　Ｉ／Ｆ３３０から、図示しない情報処理端末に出力するようになっている点である。 The difference between the biosensor 00 of the fifth embodiment shown in FIG. 10 and the IoT sensor 200 of the fourth embodiment shown in FIG. 9 is that the PGA AMP 220 is replaced by an Analog Front-End 310, The data processed by the signal processing block 230 is output from the Serial I/F 330 to an information processing terminal (not shown).
　Ａｎａｌｏｇ　Ｆｒｏｎｔ－Ｅｎｄ３１０は、アンプやフィルタを備えて構成されており、センサ素子（センサ素子Ｓ１、センサ素子Ｓ２・・・センサ素子ＳＮ）で検出したデータ（アナログ信号）を調整する機能を有している。 The Analog Front-End 310 includes an amplifier and a filter, and has a function of adjusting data (analog signal) detected by the sensor elements (sensor element S1, sensor element S2... Sensor element SN). There is.
　生体センサ３００では、例えば、センサ素子Ｓ１に体温を検知させ、センサ素子Ｓ２に心拍数を検知させる。そして、生体センサ３００は、検知された体温や心拍数を、Ａｎａｌｏｇ　Ｆｒｏｎｔ－Ｅｎｄ３１０で調整し、信号処理ブロック２３０において信号処理を行う。そして、生体センサ３００は、信号処理された体温や心拍数を、Ｓｅｒｉａｌ　Ｉ／Ｆ３３０を介して、図示しない情報処理端末に出力する。 In the biometric sensor 300, for example, the sensor element S1 detects the body temperature and the sensor element S2 detects the heart rate. Then, the biological sensor 300 adjusts the detected body temperature and heart rate by the Analog Front-End 310, and performs signal processing in the signal processing block 230. Then, the biometric sensor 300 outputs the signal-processed body temperature and heart rate to the information processing terminal (not shown) via the Serial I/F 330.
　なお、本技術に係る第５の実施形態は、上述した実施形態に限定されるものではなく、本技術の要旨を逸脱しない範囲において種々の変更が可能である。 Note that the fifth embodiment according to the present technology is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present technology.
　また、本技術に係る第１乃至第５の実施形態は、上述した実施形態に限定されるものではなく、本技術の要旨を逸脱しない範囲において種々の変更が可能である。 Further, the first to fifth embodiments according to the present technology are not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist of the present technology.
　また、本明細書に記載された効果はあくまでも例示であって限定されるものではなく、また他の効果があってもよい。 Also, the effects described in the present specification are merely examples and are not limited, and there may be other effects.
　また、本技術は、以下のような構成を取ることができる。
（１）第１極性の第１コンデンサと、
　第１極性の第２コンデンサと、
　第１極性の第３コンデンサと、
　第２極性の第１コンデンサと、
　第２極性の第２コンデンサと、
　第２極性の第３コンデンサと、
　積分器アンプと、
　コンパレータと、
　フィルタ回路と、を備え、
　前記第１極性の第１コンデンサと、前記第１極性の第２コンデンサと、前記第１極性の第３コンデンサのそれぞれが、略同一の容量を有し、
　前記第２極性の第１コンデンサと、前記第２極性の第２コンデンサと、前記第２極性の第３コンデンサのそれぞれが、略同一の容量を有し、
前記第１極性の第１コンデンサ及び前記第２極性の第１コンデンサのそれぞれに、所定の電荷が蓄積され、
　前記第１極性の第２コンデンサが、入力されるアナログ電圧の第１電荷を蓄積するとともに、当該第１電荷を前記第１極性の第３コンデンサに転送し、
　前記積分器アンプが、前記第１極性の第３コンデンサに転送された前記第１電荷を積分して、第１積分値を生成し、
　前記第２極性の第２コンデンサが、入力されるアナログ電圧の第２電荷を蓄積するとともに、当該第２電荷を前記第２極性の第３コンデンサに転送し、
　前記積分器アンプが、前記第２極性の第３コンデンサに転送された前記第２電荷を積分して、第２積分値を生成し、
　前記コンパレータが、前記第１積分値と前記第２積分値とを比較し、前記第１極性の第２コンデンサと前記第２極性の第２コンデンサとがリセットされ、
　前記第１積分値が前記第２積分値よりも大きいときは、
　前記第１極性の第３コンデンサに蓄積された電荷と前記第１極性の第１コンデンサに蓄積された電荷とを、リセットされた前記第１極性の第２コンデンサに再配分するとともに、
　前記第２極性の第３コンデンサに蓄積された電荷と前記第２極性の第１コンデンサに蓄積された電荷とを、リセットされた前記第２極性の第２コンデンサに再配分し、
　前記第１積分値が前記第２積分値よりも略同等以下であるときは、
　前記第１極性の第３コンデンサに蓄積された電荷と前記第２極性の第１コンデンサに蓄積された電荷とを、リセットされた前記第１極性の第２のコンデンサに再配分するとともに、
　前記第２極性の第３コンデンサに蓄積された電荷と前記第１極性の第１コンデンサに蓄積された電荷とを、リセットされた前記第２極性の第２コンデンサに再配分し、
　所定の分解能のビット数が得られるまで、前記コンパレータが前記第１積分値と前記第２積分値とを前記比較することと、前記第１極性の第２コンデンサと前記第２極性の第２コンデンサとが前記リセットされることと、前記リセットされた、前記第１極性の第２コンデンサと前記第２極性の第２コンデンサとに前記再配分することと、を繰り返し、
　前記所定の分解能のビット数が得られた後、前記フィルタ回路に、前記第１極性の第２コンデンサに前記再配分して前記第１極性の第３コンデンサに蓄積された電荷と、前記第２極性の第２コンデンサに前記再配分して前記第２極性の第３コンデンサに蓄積された電荷とを、残差電圧として入力する、逐次比較型ＡＤコンバータ。
（２）前記第１極性が、正極性であって、
　前記第２極性が、負極性である、前記（１）に記載の逐次比較型ＡＤコンバータ。
（３）前記所定の分解能の最下位ビットについて、前記コンパレータが、前記第１積分値と前記第２積分値とを比較し、前記第１極性の第２コンデンサと前記第２極性の第２コンデンサとが前記リセットされた後、当該第１極性の第２コンデンサと第２極性の第２コンデンサとについて前記再配分が完了するまでの間に、前記フィルタ回路が、前記残差電圧のサンプリングを開始する、前記（１）又は（２）に記載の逐次比較型ＡＤコンバータ。
（４）前記フィルタ回路が、前記積分器アンプによって駆動される、前記（１）乃至（３）のいずれか１つに記載の逐次比較型ＡＤコンバータ。
（５）前記フィルタ回路が、オペアンプを含んで構成されるアクティブ型である、前記（１）乃至（４）のいずれか１つに記載の逐次比較型ＡＤコンバータ。
（６）前記フィルタ回路が、コンデンサを含み、オペアンプを含まないで構成されるパッシブ型である、前記（１）乃至（４）のいずれか１つに記載の逐次比較型ＡＤコンバータ。
（７）前記（１）乃至（６）のいずれか１つに記載の逐次比較型ＡＤコンバータを備える、ＩｏＴセンサ。
（８）前記（１）乃至（６）のいずれか１つに記載の逐次比較型ＡＤコンバータを備える、生体センサ。 Further, the present technology may have the following configurations.
(1) a first capacitor of a first polarity,
A second capacitor of the first polarity,
A third capacitor of the first polarity,
A first capacitor of the second polarity,
A second capacitor of the second polarity,
A second capacitor of the second polarity,
An integrator amplifier,
A comparator,
And a filter circuit,
Each of the first capacitor of the first polarity, the second capacitor of the first polarity, and the third capacitor of the first polarity has substantially the same capacitance,
The first capacitor having the second polarity, the second capacitor having the second polarity, and the third capacitor having the second polarity have substantially the same capacitance,
A predetermined charge is accumulated in each of the first capacitor of the first polarity and the first capacitor of the second polarity,
The second capacitor of the first polarity accumulates the first charge of the input analog voltage and transfers the first charge to the third capacitor of the first polarity,
The integrator amplifier integrates the first charge transferred to the third capacitor of the first polarity to generate a first integrated value,
The second capacitor of the second polarity accumulates the second charge of the input analog voltage and transfers the second charge to the third capacitor of the second polarity,
The integrator amplifier integrates the second charge transferred to the third capacitor of the second polarity to generate a second integrated value,
The comparator compares the first integrated value with the second integrated value, resets the second capacitor of the first polarity and the second capacitor of the second polarity,
When the first integrated value is larger than the second integrated value,
While redistributing the charge accumulated in the third capacitor of the first polarity and the charge accumulated in the first capacitor of the first polarity to the reset second capacitor of the first polarity,
The charge accumulated in the second capacitor of the second polarity and the charge accumulated in the first capacitor of the second polarity are redistributed to the reset second capacitor of the second polarity,
When the first integrated value is substantially equal to or less than the second integrated value,
The charge accumulated in the third capacitor of the first polarity and the charge accumulated in the first capacitor of the second polarity are redistributed to the reset second capacitor of the first polarity, and
The charge accumulated in the third capacitor of the second polarity and the charge accumulated in the first capacitor of the first polarity are redistributed to the reset second capacitor of the second polarity,
The comparator compares the first integrated value with the second integrated value until a bit number with a predetermined resolution is obtained, and the second capacitor of the first polarity and the second capacitor of the second polarity are compared. Is reset, and the redistributed to the reset second capacitor of the first polarity and the second capacitor of the second polarity,
After the number of bits of the predetermined resolution is obtained, in the filter circuit, the charge redistributed to the second capacitor of the first polarity and accumulated in the third capacitor of the first polarity, and the second capacitor A successive-approximation-type AD converter that inputs the electric charges accumulated in the third capacitor having the second polarity by being redistributed to the second capacitor having the polarity as a residual voltage.
(2) The first polarity is a positive polarity,
The successive approximation type AD converter according to (1), wherein the second polarity is negative.
(3) For the least significant bit of the predetermined resolution, the comparator compares the first integrated value and the second integrated value, and the second capacitor of the first polarity and the second capacitor of the second polarity. After the resetting is performed, the filter circuit starts sampling the residual voltage until the reallocation of the second capacitor of the first polarity and the second capacitor of the second polarity is completed. The successive approximation type AD converter according to (1) or (2) above.
(4) The successive approximation AD converter according to any one of (1) to (3), wherein the filter circuit is driven by the integrator amplifier.
(5) The successive approximation AD converter according to any one of (1) to (4), wherein the filter circuit is an active type including an operational amplifier.
(6) The successive approximation type AD converter according to any one of (1) to (4), wherein the filter circuit is a passive type including a capacitor and not including an operational amplifier.
(7) An IoT sensor including the successive approximation type AD converter according to any one of (1) to (6).
(8) A biosensor, comprising the successive approximation type AD converter according to any one of (1) to (6).
Ｃ１ａ　第１極性の第１コンデンサ
Ｃ２ａ　第１極性の第２コンデンサ
Ｃ３ａ　第１極性の第３コンデンサ
Ｃ１ｂ　第２極性の第１コンデンサ
Ｃ２ｂ　第２極性の第２コンデンサ
Ｃ３ｂ　第２極性の第３コンデンサ
ＩＰ、ＩＰ１　積分器アンプ
ＣＭＰ、ＣＭＰ１　コンパレータ
ＦＬＴ、ＦＬＴ１　フィルタ回路
ＩＴＧ、ＩＴＧ１　積分器 C1a first capacitor C1a of first polarity second capacitor C3a of first polarity third capacitor C1b of first polarity second capacitor C2b of second polarity second capacitor C3b of second polarity third capacitor IP of second polarity, IP1 integrator amplifier CMP, CMP1 comparator FLT, FLT1 filter circuit ITG, ITG1 integrator

Claims (8)

  1. 　第１極性の第１コンデンサと、
    　第１極性の第２コンデンサと、
    　第１極性の第３コンデンサと、
    　第２極性の第１コンデンサと、
    　第２極性の第２コンデンサと、
    　第２極性の第３コンデンサと、
    　積分器アンプと、
    　コンパレータと、
    　フィルタ回路と、を備え、
    　前記第１極性の第１コンデンサと、前記第１極性の第２コンデンサと、前記第１極性の第３コンデンサのそれぞれが、略同一の容量を有し、
    　前記第２極性の第１コンデンサと、前記第２極性の第２コンデンサと、前記第２極性の第３コンデンサのそれぞれが、略同一の容量を有し、
    　前記第１極性の第１コンデンサ及び前記第２極性の第１コンデンサのそれぞれに、所定の電荷が蓄積され、
    　前記第１極性の第２コンデンサが、入力されるアナログ電圧の第１電荷を蓄積するとともに、当該第１電荷を前記第１極性の第３コンデンサに転送し、
    　前記積分器アンプが、前記第１極性の第３コンデンサに転送された前記第１電荷を積分して、第１積分値を生成し、
    　前記第２極性の第２コンデンサが、入力されるアナログ電圧の第２電荷を蓄積するとともに、当該第２電荷を前記第２極性の第３コンデンサに転送し、
    　前記積分器アンプが、前記第２極性の第３コンデンサに転送された前記第２電荷を積分して、第２積分値を生成し、
    　前記コンパレータが、前記第１積分値と前記第２積分値とを比較し、前記第１極性の第２コンデンサと前記第２極性の第２コンデンサとがリセットされ、
    　前記第１積分値が前記第２積分値よりも大きいときは、
    　前記第１極性の第３コンデンサに蓄積された電荷と前記第１極性の第１コンデンサに蓄積された電荷とを、リセットされた前記第１極性の第２コンデンサに再配分するとともに、
    　前記第２極性の第３コンデンサに蓄積された電荷と前記第２極性の第１コンデンサに蓄積された電荷とを、リセットされた前記第２極性の第２コンデンサに再配分し、
    　前記第１積分値が前記第２積分値よりも略同等以下であるときは、
    　前記第１極性の第３コンデンサに蓄積された電荷と前記第２極性の第１コンデンサに蓄積された電荷とを、リセットされた前記第１極性の第２のコンデンサに再配分するとともに、
    　前記第２極性の第３コンデンサに蓄積された電荷と前記第１極性の第１コンデンサに蓄積された電荷とを、リセットされた前記第２極性の第２コンデンサに再配分し、
    　所定の分解能のビット数が得られるまで、前記コンパレータが前記第１積分値と前記第２積分値とを前記比較することと、前記第１極性の第２コンデンサと前記第２極性の第２コンデンサとが前記リセットされることと、前記リセットされた、前記第１極性の第２コンデンサと前記第２極性の第２コンデンサとに前記再配分することと、を繰り返し、
    　前記所定の分解能のビット数が得られた後、前記フィルタ回路に、前記第１極性の第２コンデンサに前記再配分して前記第１極性の第３コンデンサに蓄積された電荷と、前記第２極性の第２コンデンサに前記再配分して前記第２極性の第３コンデンサに蓄積された電荷とを、残差電圧として入力する、逐次比較型ＡＤコンバータ。     A first capacitor of a first polarity,
    A second capacitor of the first polarity,
    A third capacitor of the first polarity,
    A first capacitor of the second polarity,
    A second capacitor of the second polarity,
    A second capacitor of the second polarity,
    An integrator amplifier,
    A comparator,
    And a filter circuit,
    Each of the first capacitor of the first polarity, the second capacitor of the first polarity, and the third capacitor of the first polarity has substantially the same capacitance,
    The first capacitor having the second polarity, the second capacitor having the second polarity, and the third capacitor having the second polarity have substantially the same capacitance,
    A predetermined charge is accumulated in each of the first capacitor of the first polarity and the first capacitor of the second polarity,
    The second capacitor of the first polarity accumulates the first charge of the input analog voltage and transfers the first charge to the third capacitor of the first polarity,
    The integrator amplifier integrates the first charge transferred to the third capacitor of the first polarity to generate a first integrated value,
    The second capacitor of the second polarity accumulates the second charge of the input analog voltage and transfers the second charge to the third capacitor of the second polarity,
    The integrator amplifier integrates the second charge transferred to the third capacitor of the second polarity to generate a second integrated value,
    The comparator compares the first integrated value with the second integrated value, resets the second capacitor of the first polarity and the second capacitor of the second polarity,
    When the first integrated value is larger than the second integrated value,
    While redistributing the charge accumulated in the third capacitor of the first polarity and the charge accumulated in the first capacitor of the first polarity to the reset second capacitor of the first polarity,
    The charge accumulated in the second capacitor of the second polarity and the charge accumulated in the first capacitor of the second polarity are redistributed to the reset second capacitor of the second polarity,
    When the first integrated value is substantially equal to or less than the second integrated value,
    The charge accumulated in the third capacitor of the first polarity and the charge accumulated in the first capacitor of the second polarity are redistributed to the reset second capacitor of the first polarity, and
    The charge accumulated in the third capacitor of the second polarity and the charge accumulated in the first capacitor of the first polarity are redistributed to the reset second capacitor of the second polarity,
    The comparator compares the first integrated value with the second integrated value until a bit number with a predetermined resolution is obtained, and the second capacitor of the first polarity and the second capacitor of the second polarity are compared. Is reset, and the redistributed to the reset second capacitor of the first polarity and the second capacitor of the second polarity,
    After the number of bits of the predetermined resolution is obtained, in the filter circuit, the charge redistributed to the second capacitor of the first polarity and accumulated in the third capacitor of the first polarity, and the second capacitor A successive-approximation-type AD converter that inputs the electric charges accumulated in the third capacitor having the second polarity by being redistributed to the second capacitor having the polarity as a residual voltage.
  2. 　前記第１極性が、正極性であって、
    　前記第２極性が、負極性である、請求項１に記載の逐次比較型ＡＤコンバータ。     The first polarity is positive,
    The successive approximation type AD converter according to claim 1, wherein the second polarity has a negative polarity.
  3. 　前記所定の分解能の最下位ビットについて、前記コンパレータが、前記第１積分値と前記第２積分値とを比較し、前記第１極性の第２コンデンサと前記第２極性の第２コンデンサとが前記リセットされた後、当該第１極性の第２コンデンサと当該第２極性の第２コンデンサとについて前記再配分が完了するまでの間に、前記フィルタ回路が、前記残差電圧のサンプリングを開始する、請求項１に記載の逐次比較型ＡＤコンバータ。 For the least significant bit of the predetermined resolution, the comparator compares the first integrated value and the second integrated value, and the second capacitor of the first polarity and the second capacitor of the second polarity are the After being reset, the filter circuit starts sampling the residual voltage until the redistribution of the second capacitor of the first polarity and the second capacitor of the second polarity is completed. The successive approximation type AD converter according to claim 1.
  4. 　前記フィルタ回路が、前記積分器アンプによって駆動される、請求項１に記載の逐次比較型ＡＤコンバータ。 The successive approximation type AD converter according to claim 1, wherein the filter circuit is driven by the integrator amplifier.
  5. 　前記フィルタ回路が、オペアンプを含んで構成されるアクティブ型である請求項１に記載の逐次比較型ＡＤコンバータ。 The successive approximation type AD converter according to claim 1, wherein the filter circuit is an active type including an operational amplifier.
  6. 　前記フィルタ回路が、コンデンサを含み、オペアンプを含まないで構成されるパッシブ型である請求項１に記載の逐次比較型ＡＤコンバータ。 The successive approximation type AD converter according to claim 1, wherein the filter circuit is a passive type that includes a capacitor and does not include an operational amplifier.
  7. 　請求項１に記載の逐次比較型ＡＤコンバータを備える、ＩｏＴセンサ。 An IoT sensor including the successive approximation type AD converter according to claim 1.
  8. 　請求項１に記載の逐次比較型ＡＤコンバータを備える、生体センサ。 A biometric sensor comprising the successive approximation type AD converter according to claim 1.
PCT/JP2020/000063 2019-02-20 2020-01-06 SEQUENTIAL-COMPARISON-TYPE AD CONVERTER, Iot SENSOR, AND BIOLOGICAL SENSOR WO2020170617A1 (en)

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