WO2020164554A1 - 一种oled器件及其制备方法 - Google Patents

一种oled器件及其制备方法 Download PDF

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Publication number
WO2020164554A1
WO2020164554A1 PCT/CN2020/075133 CN2020075133W WO2020164554A1 WO 2020164554 A1 WO2020164554 A1 WO 2020164554A1 CN 2020075133 W CN2020075133 W CN 2020075133W WO 2020164554 A1 WO2020164554 A1 WO 2020164554A1
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layer
electrode
buffer layer
encapsulation
auxiliary electrode
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PCT/CN2020/075133
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English (en)
French (fr)
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鲁天星
吴海燕
许显斌
朱映光
谢静
张国辉
胡永岚
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固安翌光科技有限公司
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Priority to US17/430,681 priority Critical patent/US20220158122A1/en
Priority to EP20756386.7A priority patent/EP3926700A4/en
Publication of WO2020164554A1 publication Critical patent/WO2020164554A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/814—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals
    • H10K59/1795—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/173—Passive-matrix OLED displays comprising banks or shadow masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80516—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/341—Short-circuit prevention
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8722—Peripheral sealing arrangements, e.g. adhesives, sealants
    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates

Definitions

  • the invention relates to the field of OLED devices, in particular to an OLED device and a preparation method thereof.
  • OLED devices have more advantages than other lighting methods (such as candles, halogen lamps, LED lamps), such as no ultraviolet, no infrared radiation, soft light, no glare, and no flicker , Rich spectrum and high color rendering quality. And can be used in general lighting, automotive lighting and display fields. Currently, a major bottleneck restricting OLED devices is their service life.
  • the traditional OLED device structure includes a substrate, an anode, an insulating layer, an organic functional layer, a cathode, and a packaging structure.
  • the substrate is usually ordinary alkali-free glass (Glass);
  • the anode is usually transparent conductive oxide (such as indium tin oxide ITO, aluminum doped zinc oxide AZO);
  • the insulating layer is generally photolithographic resin, and the material is phenolic resin or polymethyl Methyl acrylate;
  • the organic functional layer can include a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), etc.
  • the encapsulation layer can be a glass encapsulation cover, which is adhered to the substrate through UV glue to protect the organic functional layer.
  • the traditional device structure includes the following disadvantages:
  • the photolithography resin insulating layer used is usually an organic resin.
  • OLED When the OLED is lit for a long time, it will cause the release of harmful gases (outgas) in the resin, such as water, carbon dioxide, and sulfur compounds. Outgas further chemically reacts with the organic functional layer, affecting the performance of the organic functional layer, and then affecting the life of the OLED;
  • OLED organic materials are easily corroded by water and oxygen.
  • Thin film packaging is a good way.
  • thin film packaging is generally formed by chemical vapor deposition PECVD method, a layer of inorganic materials such as silicon oxide, silicon nitride or silicon oxynitride is formed.
  • Thin film packaging usually has a great stress. When the stress is released, the film will wrinkle or break, which will affect the effect of the thin film packaging, and then cause water and oxygen corrosion and affect the life of the OLED device.
  • the technical problem to be solved by the present invention lies in the problems of poor device life and failure caused by materials or structures in the prior art.
  • the present invention provides an OLED device and a preparation method thereof.
  • a buffer layer can prevent metal ions in the glass from penetrating into the device.
  • the added buffer layer can improve the dry engraving undercut problem of the auxiliary electrode on it, and the Taper angle of the auxiliary electrode is 20-80°, which improves the package life of the device; in addition, by selecting inorganic compounds as the pixel limiting layer, volatile gas outgas can be avoided Released into the pixel, causing the pixel to shrink, improving the reliability of the OLED screen.
  • the pixel defining layer provided on the first electrode layer and the auxiliary electrode is in direct contact with the buffer layer, forming a good surrounding structure for the effective pixel area and/or pixel of the OLED, and reducing the impact of impurities or gases introduced during the process on the pixel area. Erosion.
  • the pixel defining layer and/or buffer layer located in the encapsulation area are patterned.
  • the encapsulation layer on the OLED material directly contacts the patterned pixel defining layer and/or buffer layer to further form a good stress relief structure and increase The interface packaging effect is reduced, the intrusion of water and oxygen is reduced, and the packaging reliability is improved.
  • An OLED device includes a substrate and an encapsulation layer.
  • a first electrode layer, an auxiliary electrode, and a pixel defining layer are arranged in a closed space formed by the substrate and the encapsulation layer,
  • a buffer layer is arranged between the first electrode layer/auxiliary electrode and the substrate, and a number of auxiliary electrodes arranged at intervals are arranged on the buffer layer.
  • the first electrode layer covers the buffer layer and the auxiliary electrode.
  • the pixel defining layer completely covers the first electrode layer on the auxiliary electrode and is patterned with an opening that exposes at least a part of the first electrode layer, and the pixel defining layer and the opening are covered with a continuous organic light-emitting layer and a second electrode Floor.
  • the substrate is divided into a plurality of pixel areas distributed in an array and a packaging area surrounding all the pixel areas, the edge positions of each pixel area are respectively surrounded by the pixel defining layer, and the auxiliary electrodes are distributed in an array
  • the horizontal column position and/or the vertical column position of the distributed pixel area; the first electrode layer and the auxiliary electrode of the encapsulation area are etched away, so that the pixel defining layer and the buffer layer are arranged in direct contact.
  • a continuous patterned structure is formed on the buffer layer located in the packaging area, and the packaging layer is in direct contact with the patterned structure formed on the buffer layer.
  • the patterned structure is a plurality of groove structures and/or dam structures patterned on the buffer layer.
  • the first electrode layer located on one or both sides of the auxiliary electrode is removed by etching, so that the pixel defining layer located in this area is directly in contact with the buffer layer.
  • the width of the direct contact area between the first electrode layer and the buffer layer on one or both sides of each auxiliary electrode is 1 ⁇ m-1 cm.
  • the first electrode layer is patterned with an anti-short-circuit structure layer between two adjacent pixel regions distributed in an array.
  • the anti-short-circuit structure layer is connected to the first electrode on the auxiliary electrode.
  • the electrode layer and one of the two adjacent pixel regions are electrically connected to form a disconnection with the other pixel region; the pixel defining layer located on both sides of the anti-short circuit structure layer is in direct contact with the buffer layer .
  • the width of the direct contact area between the pixel defining layer and the buffer layer located on one or both sides of each auxiliary electrode is 5 ⁇ m-10 mm.
  • Ti titanium
  • Al aluminum
  • Mo molybdenum
  • Cu copper
  • the Taper angle formed by the auxiliary electrode is 10-90°.
  • the etching selection ratio of the material with a low etching rate in the auxiliary electrode to the material of the buffer layer is (0.5-20);
  • the etching selection ratio of the material of the pixel defining layer to the material of the buffer layer (0.5-5).
  • the etching selection ratio of the material of the auxiliary electrode to the material of the buffer layer is (5-7).
  • the thickness of the buffer layer is 10 nm-3 ⁇ m.
  • a planarized auxiliary buffer layer is also provided on the buffer layer between the auxiliary electrodes, and the auxiliary electrode is 0-1 ⁇ m higher than the auxiliary buffer layer.
  • the pixel defining layer, the buffer layer and the encapsulation layer are made of the same or different materials, and are one or a combination of silicon nitride, silicon oxide, or silicon oxynitride.
  • the encapsulation layer is a thin-film encapsulation structure, on which a cover plate is also arranged, and the cover plate is combined with the encapsulation layer through an encapsulation transition layer.
  • the packaging layer is a packaging cover
  • the packaging cover is combined with the buffer layer of the packaging area on the substrate through UV glue.
  • the present invention also provides a method for preparing an OLED device, including the following steps:
  • a first electrode layer is prepared on the basis of step S1, the first electrode layer covers the buffer layer and the auxiliary electrode, and the first electrode layer located between the auxiliary electrode and the encapsulation area is etched away to Expose the buffer layer;
  • step S3 depositing a pixel defining layer on the basis of step S2, the pixel defining layer covering the first electrode layer and the buffer layer, etching the pixel defining layer to form an opening, and the bottom of the opening is the first electrode layer and the buffer layer;
  • step S4 On the basis of step S3, an organic light-emitting layer and a second electrode layer are produced by evaporation, and a continuous organic light-emitting layer and a second electrode layer are formed on the pixel defining layer and in the opening;
  • An encapsulation layer is fabricated on the basis of step S4, the encapsulation layer covers the entire pixel area, and the entire pixel area is sealed and protected in the encapsulation area surrounding the pixel area.
  • the step S2 is: preparing a first electrode layer on the basis of step S1, the first electrode layer covers the buffer layer and the auxiliary electrode, and the first electrode located on one or both sides of the auxiliary electrode is etched away Layer to expose the buffer layer; etching to form a short-circuit prevention structure layer.
  • step S3 a number of patterned groove structures and/or dam structures are formed on the buffer layer located in the packaging area; when packaging in step S5, the packaging layer and the buffer layer are patterned The groove structure and/or the dam structure are in direct contact.
  • the present invention adds a buffer layer on the glass substrate, which can prevent the metal ions of the glass substrate from penetrating into the first electrode layer/auxiliary electrode, avoid electrochemical corrosion, and improve the stability of the OLED device.
  • the present invention introduces a short-circuit prevention structure through the patterning of the first electrode, which can prevent the device from failing due to the short-circuit of the device during long-term aging (such as long-term lighting).
  • inorganic compounds such as silicon oxide, silicon nitride, silicon oxynitride
  • the pixel defining layer provided on the first electrode layer and the auxiliary electrode is in direct contact with the buffer layer, forming a good surrounding structure for the effective pixel area and/or pixel of the OLED, and reducing the impact of impurities or gases introduced during the process on the pixel area. Corrosion, and then improve the life of the screen.
  • a patterned groove structure is made for the buffer layer located in the encapsulation area and/or an embankment structure is arranged on the buffer layer, and the patterned groove structure on the encapsulation layer and the buffer layer and / Or the dam structure is in direct contact, further forming a good stress relief structure, increasing the interface bonding and packaging effect, reducing the intrusion of water and oxygen, and improving the packaging reliability and screen life.
  • the present invention also adds an auxiliary buffer layer of silicon nitride (or silicon oxide) structure on the buffer layer 6 between the auxiliary electrodes, through such as dry etching, grinding, lift-off (Lift- The off) method is used to fabricate and planarize the auxiliary buffer layer structure.
  • the height D of the auxiliary electrode above the auxiliary buffer layer is 0-1 ⁇ m. This makes the subsequent first electrode layer more planar, which helps to improve the uniformity of the overlap resistance (the resistance of the contact between the auxiliary electrode and the first electrode).
  • Figure 1 is a schematic diagram of the OLED device of the present invention.
  • Figure 2 is a cross-sectional view of A-A' in Figure 1;
  • FIG. 3 is a schematic diagram of the structure of the auxiliary electrode of the present invention.
  • FIG. 4 is a schematic diagram of the structure of the auxiliary electrode in the prior art
  • Figure 5 is a schematic diagram of the structure of an auxiliary buffer layer provided on the buffer layer
  • FIG. 6 is a top view of the pixel defining layer after the preparation is completed
  • Fig. 7 is a cross-sectional view of C-C' in Fig. 6;
  • Figure 8 is a cross-sectional view taken along the line D-D' in Figure 6;
  • Figure 9 is a partial enlarged view of Figure 8.
  • Figure 10 is a schematic view of the structure with a cover provided by the present invention.
  • Figure 11 is a schematic diagram of the first partial structure shown in Figure 10;
  • Fig. 12 is a schematic diagram of the second partial structure shown in Fig. 10;
  • FIG. 13 is a schematic diagram of the third partial structure shown in FIG. 10;
  • Fig. 14 is a schematic diagram of the fourth partial structure shown in Fig. 10.
  • an OLED device provided by the present invention includes a substrate 1 and an encapsulation layer 10.
  • the enclosed space formed by the substrate 1 and the encapsulation layer 10 is provided with a first electrode layer 2, an auxiliary electrode 7, and Pixel defining layer 12, a buffer layer 6 is arranged between the first electrode layer and the substrate, and a number of auxiliary electrodes 7 arranged at intervals are arranged on the buffer layer 6.
  • the first electrode layer 2 covers the buffer layer 6 and the auxiliary electrode 7.
  • the defining layer 12 completely covers the first electrode layer 2 on the auxiliary electrode and is patterned with an opening 17 exposing at least a part of the first electrode layer 2.
  • the shape of the opening 17 is a trapezoidal structure.
  • the bottom of the trapezoid is the first electrode layer 2.
  • the limiting layer 12 and the opening 17 are covered with a continuous organic light emitting layer 3, a second electrode layer 4 and an encapsulation layer 10.
  • the substrate 1 is divided into a number of pixel areas 11 and an encapsulation area surrounding all the pixel areas 11.
  • the edge position of each pixel area 11 is respectively surrounded by the pixel defining layer 12, and the auxiliary electrodes are distributed in the row positions and rows of the pixel areas arranged in an array. / Or column position; the first electrode layer 2 and the auxiliary electrode 7 located between the auxiliary electrode 7 and the packaging area are etched away, and the pixel defining layer 12 between the auxiliary electrode 7 and the packaging area is arranged in direct contact with the buffer layer; preferably The width of the direct contact area between the pixel defining layer 12 and the buffer layer 6 is 5 ⁇ m-10 mm.
  • the first electrode layer 2 located on one or both sides of the auxiliary electrode 7 is removed by etching, so that the pixel defining layer 12 located in this area is directly in contact with the buffer layer;
  • the width of the direct contact area between the first electrode layer 2 and the buffer layer 6 on one or both sides of the electrode 7 is 1 ⁇ m-1 cm.
  • the width of the direct contact area between the pixel defining layer 12 and the buffer layer 6 located on one or both sides of each auxiliary electrode 7 is 5 ⁇ m-10 mm.
  • the auxiliary electrode 7 is one or more combinations of titanium (Ti), aluminum (Al), molybdenum (Mo), and copper (Cu).
  • TiAlTi titanium aluminum titanium
  • AlTi aluminum titanium
  • AlMo aluminum molybdenum
  • MoAlMo molybdenum aluminum molybdenum
  • Mo titanium
  • Ti copper
  • Al aluminum
  • the Taper angle of the auxiliary electrode 7 is 10-90°
  • the Taper angle here refers to the Taper angle of the aluminum layer in the auxiliary electrode 7.
  • the etching selection ratio of the material with a low etching rate in the auxiliary electrode 7 to the material of the buffer layer 6 is (0.5-20), preferably (5-7); the Ti or Mo material in the auxiliary electrode has a low etching rate material.
  • the etching selection ratio of the material of the pixel defining layer 12 to the material of the buffer layer 6 is (0.5-5).
  • the thickness of the buffer layer 6 is 10 nm to 3 ⁇ m, preferably 100 nm.
  • the buffer layer 6 between the auxiliary electrodes 7 is also provided with a planarized auxiliary buffer layer, and the auxiliary electrode 7 is 0-1 ⁇ m higher than the auxiliary buffer layer.
  • the pixel defining layer 12, the buffer layer 6 and the encapsulation layer are made of the same or different materials, and are one or a combination of silicon nitride, silicon oxide, or silicon oxynitride.
  • the packaging layer 10 is a glass packaging cover, the glass packaging cover 5 is provided with UV glue 8, and the glass packaging cover 5 is combined with the buffer layer 6 and/or the limiting pixel layer 12 on the substrate 1 through the UV glue 8.
  • the encapsulation layer can also adopt a thin film encapsulation method, and the encapsulation layer 10 can be made by chemical vapor deposition.
  • the organic light emitting layer 3, the second electrode layer 4, and the encapsulation layer are sequentially covered on the pixel defining layer 12 and in the opening from bottom to top.
  • the packaging layer in the packaging area is in direct contact with the buffer layer to form a thin film package; by attaching a packaging transition layer, such as UV glue, OCA glue, to the packaging layer, and then attaching a cover plate to the packaging transition layer for sealing, here
  • the cover plate may include glass, copper foil, aluminum foil, etc.
  • a continuous patterned structure is formed on the buffer layer 6 located in the packaging area, and the packaging layer 10 is in direct contact with the patterned structure formed on the buffer layer 6.
  • the patterned structure here is a number of groove structures 16 and/or dam structures 15 patterned on the buffer layer 6.
  • the encapsulation layer covers the patterned structure, and the encapsulation layer 10 is in direct contact with the patterned groove structure 16 and/or the dam structure 15 on the buffer layer 6, further forming a good stress relief structure, increasing the interface bonding and packaging effect, reducing the intrusion of water and oxygen, and improving the packaging reliability .
  • a method for preparing an OLED device includes the following steps:
  • step S2 Prepare the first electrode layer 2 on the basis of step S1.
  • the first electrode layer 2 covers the buffer layer 6 and the auxiliary electrode 7, and the first electrode layer 2 located between the auxiliary electrode 7 and the encapsulation area 9 is removed by etching to expose Buffer layer 6;
  • step S3. Deposit a pixel defining layer 12 on the basis of step S2.
  • the pixel defining layer 12 covers the first electrode layer 2 and the buffer layer 6, and the pixel defining layer 12 is etched to form a trapezoidal structure opening, and the bottom of the trapezoidal structure is the first electrode layer 2.
  • step S4 On the basis of step S3, an organic light-emitting material layer 3 and a second electrode layer 4 are produced by evaporation, and a continuous organic light-emitting layer 3 and a second electrode layer 4 are formed on the pixel defining layer 12 and in the opening;
  • step S5 On the basis of step S4, an encapsulation layer 10 is fabricated.
  • the encapsulation layer 10 covers the entire pixel area 11, and the entire pixel area 11 is sealed and protected in the encapsulation area 9 surrounding the pixel area 11.
  • step S2 is: preparing the first electrode layer 2 on the basis of step S1, the first electrode layer 2 covers the buffer layer 6 and the auxiliary electrode 7, and is removed by etching
  • the first electrode layer 2 located on one or both sides of the auxiliary electrode 7 exposes the buffer layer 6; the short-circuit prevention structure layer 13 is formed by etching, and the short-circuit prevention structure layer 13 is located under the pixel defining layer and covered by the pixel defining layer.
  • each layer is as follows:
  • the buffer layer is made of inorganic materials, such as silicon nitride, silicon oxide, and silicon oxynitride.
  • the film deposition method can use chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • the buffer layer is preferably silicon nitride, with a thickness of 10 nm to 3 ⁇ m, preferably 100 nm to 150 nm.
  • the auxiliary electrode is a metal or metal alloy, such as titanium aluminum titanium (TiAlTi), aluminum titanium (AlTi), molybdenum aluminum (MoAl), molybdenum aluminum molybdenum (MoAlMo), Mo, Ti, Cu, Al, using dry engraving process Or wet etching process for patterning; preferably TiAlTi three-layer structure, bottom Ti 50-100nm, preferably 75nm, top Ti 50-100nm, preferably 50nm, Al 300-700nm, preferably 300nm; through Cl 2 and BCl 3 (not limited to this Two gases) for dry engraving, 10 ⁇ Taper angle ⁇ 90°, preferably 20-80°.
  • TiAlTi titanium aluminum titanium
  • AlTi aluminum titanium
  • MoAl molybdenum aluminum
  • MoAlMo molybdenum aluminum molybdenum
  • Mo molybdenum aluminum molybdenum
  • the titanium aluminum (AlTi) structure consists of an Al material layer and a Ti material layer from bottom to top, as shown in Figure 3.
  • the molybdenum aluminum molybdenum (MoAlMo) structure consists of Mo material layer, Al material layer and Mo Material layer.
  • the first electrode layer transparent conductive metal oxide, such as ITO, AZO, sputtered by PVD; patterning adopts dry etching or wet etching, preferably wet etching, such as etching with hydrochloric acid, nitric acid, acetic acid, etc. or mixed acids; It is preferable to have a patterned structure to prevent short circuits, that is, pixels can be formed by patterning the first electrode, refer to FIG. 6.
  • Pixel defining layer (or dielectric layer or insulating layer), above the first electrode layer and/or auxiliary electrode, made of silicon oxide, silicon nitride or silicon oxynitride, using the same process as the buffer layer (such as CVD, ALD) ), the thickness is 200nm-500nm, preferably 300nm, and the etching selection ratio of the buffer layer (0.5-5); the formation of "pixels" through the first electrode patterning can make the pixel defining layer directly contact the buffer layer, as shown in the figure H ⁇ 0.5 ⁇ m.
  • the pixel defining layer forms a good surrounding structure for the effective pixel area and/or pixels of the OLED, preventing outgas from being released into the pixel, causing pixel shrinkage, improving the reliability of the OLED screen, and the material of the pixel defining layer and the buffer layer Generally the same, the interface bonding properties are more stable, and the packaging reliability of the screen is further improved.
  • Organic light emitting layer 3 including but not limited to hole injection layer (HIL), hole transport layer (HTL), light emitting layer (EL), electron transport layer (ETL), electron injection layer (EIL), etc.
  • HIL hole injection layer
  • HTL hole transport layer
  • EL light emitting layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the second electrode layer 4 includes an Al electrode, a MgAg electrode, a metal oxide electrode (such as ITO) and the like.
  • a metal oxide electrode such as ITO
  • Encapsulation layer 10 The organic light-emitting layer 3 is encapsulated, and encapsulated by a combination of a traditional encapsulated glass encapsulation cover and UV glue or glass frit. Such as using UV glue to package the substrate and the package cover to avoid water and oxygen corrosion.
  • thin film packaging methods are used, such as inorganic layer/organic layer/inorganic layer.
  • the inorganic layer can be deposited by chemical vapor deposition (CVD), and the organic layer can be deposited by inkjet printing (IJP). print.
  • CVD chemical vapor deposition
  • IJP inkjet printing
  • an OLED device provided by the present invention includes a substrate 1 and an encapsulation layer 10.
  • the substrate 1 is divided into a pixel area 11 and an encapsulation area 9 surrounding the pixel area 11, and the encapsulation area 9 is provided with
  • the UV glue 8 seals and connects the substrate 1 and the encapsulation layer 10 to form a closed space.
  • the encapsulation layer here is a glass encapsulation cover.
  • a drying sheet can be provided on the side of the encapsulation cover close to the substrate 1 to absorb moisture, and UV glue is used as a sealing material
  • the layer encapsulates the substrate and the packaging cover to improve the reliability of the screen body packaging.
  • the thickness of the buffer layer 6 is 10 nm-3 ⁇ m.
  • the light-emitting area of the substrate 1 is provided with a buffer layer 6, and a number of auxiliary electrodes 7 arranged at intervals are provided on the buffer layer 6.
  • the first electrode layer 2 covers the buffer layer 6 and the auxiliary electrode 7, and is located between the auxiliary electrode 7 and the packaging area.
  • the pixel defining layer 12 completely covers the first electrode layer on the auxiliary electrode and is patterned with an opening that exposes at least a part of the first electrode layer.
  • the shape of the opening is a trapezoidal structure.
  • the bottom of the trapezoid is the first electrode layer 2, the pixel defining layer and
  • the opening is covered with a continuous organic light emitting layer 3 and a second electrode layer 4. Since there is no first electrode layer on the buffer layer 6 located between the auxiliary electrode 7 and the encapsulation area 9, the buffer layer 6 in this area is arranged in direct contact with the pixel defining layer 12.
  • the width H of the direct contact area between the pixel defining layer 12 and the buffer layer 6 is 10 ⁇ m.
  • the auxiliary electrode 7 includes an Al material layer and a Ti material layer that are superimposed, and the Ti material layer is located above the Al material layer. As shown in Fig. 3, the Taper angle of the auxiliary electrode 7 is 20-80°. It can be seen from the comparison of Fig. 3 and Fig. 4 that adding a SiN buffer layer can effectively improve the Taper angle of AlTi. This is because the etching options for Al and Ti are relatively large. The rate of etching Al>the rate of etching Ti, without SiN, Side etching will occur on the side of the substrate, leading to undercutting. At the same time, the added buffer layer prevents the metal ions of the glass substrate from penetrating into the ITO layer to avoid electrochemical corrosion of ITO and improve the stability of the OLED device.
  • the etching selection ratio of the material of the auxiliary electrode 7 to the material of the buffer layer 6 is (0.5-20), preferably (5-7);
  • the etching selection ratio of the material of the pixel defining layer 12 to the material of the buffer layer 6 is (0.5-5).
  • the pixel defining layer and the buffer layer are made of the same or different materials, and are one or a combination of silicon nitride, silicon oxide, or silicon oxynitride.
  • a preparation method of an OLED device includes the following steps:
  • the first electrode layer 2 is prepared on the basis of step S1.
  • the first electrode layer 2 covers the buffer layer 6 and the auxiliary electrode 7, and the first electrode layer 2 located between the auxiliary electrode 7 and the encapsulation area is removed by etching to Expose the buffer layer 6;
  • step S3. Depositing a pixel defining layer 12 on the basis of step S2.
  • the pixel defining layer 12 covers the first electrode layer 2 and the buffer layer 6 between the auxiliary electrode 7 and the packaging area.
  • the pixel defining layer 12 is etched to form a trapezoidal structure opening, The bottom of the trapezoidal structure is the first electrode layer 2 and the buffer layer;
  • step S4 On the basis of step S3, the luminescent material layer 2 and the second electrode layer 3 are produced by evaporation, and a continuous organic luminescent layer 3 and the second electrode layer 4 are formed on the pixel defining layer 12 and in the opening;
  • the packaging layer 10 is made on the basis of step S4, where the packaging layer 10 is a glass packaging cover, that is, UV glue is coated on the glass packaging cover, and then it is sealed and connected with the buffer layer at the location of the packaging area on the substrate, thereby To achieve the packaging of the entire pixel area, as shown in Figure 2.
  • Buffer layer 6 (Buffer layer), deposit a layer of silicon nitride 100nm through high temperature CVD process, process temperature 350°C, adhesion to the substrate 5B, refractive index 1.8;
  • the auxiliary electrode 7 is AlTi, the top titanium is 50nm, and the Al is 300nm; dry etching is patterned by Cl 2 and BCl 3 , with a Taper angle of 70°; etching is not limited to dry etching, and wet etching can also be used, using H 3 PO 4. CH 3 COOH, HNO 3 mixed acid is etched according to a certain proportion of the solution;
  • the first electrode layer 2 is sputtered with indium tin oxide (ITO) by PVD, with a thickness of 150 nm, and is patterned by a wet (acid etching) process;
  • ITO indium tin oxide
  • the pixel defining layer 12, above the first electrode layer, is made of SiN, using the same process as the Buffer, with a thickness of 300 nm, and a grid size of 400 ⁇ m*400 ⁇ m.
  • the pixel defining layer is patterned by a dry etching process;
  • Organic light emitting layer 3 including but not limited to hole injection layer (HIL), hole transport layer (HTL), light emitting layer (EL), electron transport layer (ETL), electron injection layer (EIL), etc.;
  • HIL hole injection layer
  • HTL hole transport layer
  • EL light emitting layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the second electrode layer 4 includes an Al electrode, a MgAg electrode, and a metal oxide electrode (such as ITO). Such as sputtering a layer of Al with a thickness of 200nm by thermal evaporation;
  • Encapsulation layer 10 The organic light-emitting layer 3 is encapsulated, and encapsulated by a combination of a traditional encapsulated glass encapsulation cover and UV glue or glass frit.
  • auxiliary electrode 7 materials and buffer layer 6 materials are selected respectively, and the etching selection ratio of the material of the pixel defining layer 12 to the material of the buffer layer 6 is preferably 1.
  • the buffer layer is likely to be etched away, resulting in the side etching problem of Figure 4, so an inverted trapezoid appears;
  • the selection is relatively high (>20)
  • the buffer layer is difficult to etch away, and side etching is also prone to appear, and then an inverted trapezoid shape appears.
  • the preferred etching selection ratio of the auxiliary electrode 7 material and the buffer layer 6 material is 5-7, and the Taper angle of Al can be controlled at 70° ⁇ 3°.
  • the material of the pixel defining layer 12 and the material of the buffer layer 6 are preferably the same or similar, which can well ensure the interface bonding effect, make the subsequent OLED film layers more continuous, have a better packaging effect, and increase the service life of the OLED device.
  • the basic structure of an OLED device provided by the present invention is the same as that of Embodiment 1, and the difference is that the packaging layer in this embodiment adopts a thin film packaging structure, as shown in FIG. 10 and FIG. 11.
  • the first electrode layer 2 is prepared on the basis of step S1.
  • the first electrode layer 2 covers the buffer layer 6 and the auxiliary electrode 7, and the first electrode layer 2 located between the auxiliary electrode 7 and the encapsulation area is removed by etching to Expose the buffer layer 6;
  • step S3. Depositing a pixel defining layer 12 on the basis of step S2.
  • the pixel defining layer 12 covers the first electrode layer 2 and the buffer layer 6 between the auxiliary electrode 7 and the packaging area.
  • the pixel defining layer 12 is etched to form a trapezoidal structure opening, The bottom of the trapezoidal structure is the first electrode layer 2 and the buffer layer;
  • step S4 On the basis of step S3, the luminescent material layer 2 and the second electrode layer 3 are produced by evaporation, and a continuous organic luminescent layer 3 and the second electrode layer 4 are formed on the pixel defining layer 12 and in the opening;
  • the encapsulation layer 10 is fabricated on the basis of step S4.
  • the encapsulation layer 10 here adopts a thin film encapsulation method, such as inorganic layer/organic layer/inorganic layer.
  • the inorganic layer can be deposited by chemical vapor deposition (CVD), and the organic layer can be sprayed.
  • IJP Ink printing
  • film printing For example, use SiO(1 ⁇ m)/IJP(8 ⁇ m)/SiO(1 ⁇ m).
  • the packaging layer 10 covers the entire pixel area 11, and the entire pixel area 11 is sealed and protected in the packaging area 9 surrounding the pixel area 11;
  • the film packaging method can further improve the reliability of the screen body packaging.
  • the short-circuit structure can prevent the device from failing due to the short-circuit of the device during long-term aging (such as long-term lighting).
  • the pixel defining layer 12 completely covers the first electrode layer 2 on the auxiliary electrode and is provided with an opening that exposes at least a part of the first electrode layer 2.
  • the shape of the opening is a trapezoidal structure, and the bottom of the trapezoid is the first electrode.
  • Layer 2, the pixel defining layer 12 and the opening are covered with a continuous organic light emitting layer 3 and a second electrode layer 4. Since there is no first electrode layer on the buffer layer located on one or both sides of the auxiliary electrode 7, the buffer layer 6 in this area and the pixel defining layer 12 are arranged in direct contact.
  • the first electrode layer is patterned with an anti-short-circuit structure layer 13 between two adjacent pixel regions arranged in an array, the anti-short-circuit structure layer 13 and the auxiliary electrode 7
  • the upper first electrode layer 2 and one of the two adjacent pixel areas are electrically connected to form a disconnection with the other pixel area; the pixel defining layers on both sides of the anti-short-circuit structure layer 13 are in direct contact with the buffer layer 6.
  • the current flow in each pixel area is shown by the arrow in Figure 6.
  • the width H of the direct contact area between the pixel defining layer 12 and the buffer layer located on one or both sides of each auxiliary electrode is 10 ⁇ m.
  • the manufacturing method of an OLED device of this embodiment includes the following steps:
  • the first electrode layer 2 is prepared on the basis of step S1, the first electrode layer 2 covers the buffer layer 6 and the auxiliary electrode 7, and the first electrode layer 2 located on one or both sides of the auxiliary electrode 7 is removed by etching to Expose the buffer layer 6; etching to form a short-circuit prevention structure layer 13;
  • step S3. Deposit a pixel defining layer 12 on the basis of step S2.
  • the pixel defining layer 12 covers the first electrode layer 2 and the buffer layer 6 between the auxiliary electrode 7 and the encapsulation area 9, and the pixel defining layer 12 is etched to form a trapezoidal structure opening , The bottom of the trapezoidal structure is the first electrode layer 2 and the buffer layer;
  • step S4 On the basis of step S3, the luminescent material layer 2 and the second electrode layer 3 are produced by evaporation, and a continuous organic luminescent layer 3 and the second electrode layer 4 are formed on the pixel defining layer 12 and in the opening;
  • the encapsulation layer 10 is fabricated on the basis of step S4.
  • the encapsulation layer 10 here adopts a thin film encapsulation method, such as inorganic layer/organic layer/inorganic layer.
  • the inorganic layer can be deposited by chemical vapor deposition (CVD), and the organic layer can be sprayed.
  • IJP Ink printing
  • film printing For example, use SiO(1 ⁇ m)/IJP(8 ⁇ m)/SiO(1 ⁇ m).
  • the packaging layer 10 covers the entire pixel area 11, and the entire pixel area 11 is sealed and protected in the packaging area 9 surrounding the pixel area 11;
  • the basic structure of an OLED device provided by the present invention is the same as that of Embodiment 3.
  • the difference from Embodiment 3 is:
  • the substrate 1 can also be formed with such a structure: a patterned auxiliary electrode 7 is formed on the substrate 1, and an auxiliary buffer layer 14SiN is formed on the buffer layer 6 between the auxiliary electrodes 7 by PECVD (Or SiOx), SiN (or SiOx) is planarized by methods such as dry etching or polishing or lift-off.
  • PECVD Or SiOx
  • SiN or SiOx
  • the auxiliary electrode 7 needs to be higher than the auxiliary buffer layer 14 by a height D of 0 to 1 ⁇ m , In order to facilitate the overlap of the first electrode layer.
  • Figure 3 shows the buffer layer structure provided on the substrate used in Embodiments 1 to 3.
  • the climbing of the first electrode layer can be avoided, although the first electrode layer in this embodiment
  • the overlap area on the auxiliary electrode is smaller than the structure shown in FIG. 3, but compared with Embodiment 1 and Embodiment 2, this embodiment will improve the uniformity of overlap resistance.
  • the substrate 1 is made of alkali-free glass and adopts the conventional substrate structure shown in FIG. 4;
  • the auxiliary electrode 7 is AlTi, the top titanium is 50 nm, and the Al is 300 nm; the structure shown in FIG. 4 is prepared by an etching method;
  • the first electrode layer indium tin oxide (ITO) sputtered by PVD, thickness 150nm;
  • Pixel limiting layer above the first electrode layer, made of SiN, using the same process as Buffer, thickness 300nm, grid size 400 ⁇ m*400 ⁇ m;
  • Organic light emitting layer including HIL, HTL, EL, ETL, EIL;
  • the second electrode includes an Al electrode, and a layer of Al with a thickness of 200 nm is sputtered by thermal evaporation;
  • the encapsulation layer is a glass encapsulation cover, and the encapsulation area of the substrate and the encapsulation cover are glass-encapsulated and combined with UV glue to improve the reliability of the screen body encapsulation.
  • the device of the present invention can increase the life of the OLED device by 5 times due to the addition of the buffer layer. It shows that adding a buffer layer can significantly improve the reliability of the screen. The main reasons are as follows:
  • the dry-etched first electrode or the auxiliary electrode forms a more acute Taper angle, that is, the arrangement of the buffer layer can improve the "undercut” phenomenon of the auxiliary electrode and avoid the occurrence of "side etching".
  • the Taper angle of the auxiliary electrode is better modified, thereby improving the bonding of the subsequent organic/metal/encapsulation film layer.
  • adding a buffer layer can prevent metal ions of the glass substrate from penetrating into the first electrode layer/auxiliary electrode, avoid electrochemical corrosion, and improve the stability of the OLED device.
  • the average life span of the device in Example 1 of the present invention is 500h@1000nit, and the failure rate of the device at 1000H under long-term aging is 20%;
  • the average lifetime of the device of embodiment 2 is 550h@1000nit, and the failure rate of the 1000H device under long-term aging is 10%;
  • the average lifespan of the device of embodiment 3 is 560h@1000nit, and because of the addition of the short-circuit prevention structure, the device has no failure at 1000H under long-term aging;
  • the average lifespan of the device of embodiment 4 is 600h@1000nit, and because of the addition of the short-circuit prevention structure, the device does not fail 1000H under long-term aging;
  • the average lifetime of the device of Comparative Example 1 is 100h@1000nit.
  • the embodiments 1 to 4 used in the present invention can greatly improve the life of the device compared with the prior art.
  • a continuous embankment structure surrounding the entire pixel area is arranged at the buffer layer located in the packaging area, as shown in FIG. 12 in detail.
  • a method for preparing an OLED device includes the following steps:
  • step S2 Prepare the first electrode layer 2 on the basis of step S1.
  • the first electrode layer 2 covers the buffer layer 6 and the auxiliary electrode 7, and the first electrode layer 2 on one or both sides of the auxiliary electrode 7 is etched away to expose the buffer Layer 6, etching to form a short-circuit prevention structure layer 13;
  • step S3. Deposit a pixel defining layer 12 on the basis of step S2.
  • the pixel defining layer 12 covers the first electrode layer 2 and the buffer layer 6 located in the packaging area.
  • the pixel defining layer 12 is etched to form a trapezoidal structure opening, and a protrusion is formed in the packaging area.
  • Dam structure (DAM) Dam structure
  • step S4 On the basis of step S3, an organic light-emitting layer 3 and a second electrode layer 4 are fabricated by evaporation, and a continuous organic light-emitting layer 3 and a second electrode layer 4 are formed on the pixel defining layer 12 and in the opening.
  • step S5 the encapsulation layer 10 is fabricated by chemical vapor deposition.
  • a continuous organic light-emitting layer 3, a second electrode layer 4, and an encapsulation layer are formed on the pixel defining layer 12 and in the opening.
  • the packaging layer in the packaging area is in direct contact with the buffer layer to form a thin film package;
  • step S6 In step S5, a package transition layer, such as UV glue or OCA glue, is attached, and then a cover plate is attached to the package transition layer for sealing, where the cover plate may include glass, copper foil, aluminum foil, etc.
  • a package transition layer such as UV glue or OCA glue
  • Embodiment 5 uses a patterned structure on the buffer layer located in the package area. As shown in FIG. 13, the patterned structure surrounds all the pixel areas in a continuous two groove structure, and also A raised dam structure is set on the inner side of the packaging area.
  • a method for preparing an OLED device includes the following steps:
  • step S2 Prepare the first electrode layer 2 on the basis of step S1.
  • the first electrode layer 2 covers the buffer layer 6 and the auxiliary electrode 7, and the first electrode layer 2 on one or both sides of the auxiliary electrode 7 is etched away to expose the buffer Layer 6; etching to form a short-circuit prevention structure layer 13;
  • step S3. Deposit a pixel defining layer 12 on the basis of step S2.
  • the pixel defining layer 12 covers the first electrode layer 2 and the buffer layer 6 in the encapsulation area.
  • the pixel defining layer 12 is etched to form a trapezoidal structure opening, and it is inside the encapsulation area Form a raised dam structure (DAM);
  • DAM raised dam structure
  • step S4 On the basis of step S3, the luminescent material layer 2 and the second electrode layer 3 are fabricated by evaporation, and a continuous organic luminescent layer 3 and the second electrode layer 4 are formed on the pixel defining layer 12 and in the opening.
  • step S5 On the basis of step S4, a thin film encapsulation layer 10 is fabricated by chemical vapor deposition, and a continuous organic light emitting layer 3, a second electrode layer 4, and an encapsulation layer are formed on the pixel defining layer 12 and in the opening.
  • the packaging layer in the packaging area is in direct contact with the buffer layer to form a thin film package;
  • step S6 In step S5, a package transition layer, such as UV glue or OCA glue, is attached, and then a cover plate is attached to the package transition layer for sealing, where the cover plate may include glass, copper foil, aluminum foil, etc.
  • a package transition layer such as UV glue or OCA glue
  • the patterned structure provided in the packaging area is not limited to the structure shown in FIG. 12 and FIG. 13, and the patterned groove structure may be provided only in the packaging area, as shown in FIG. 14, or not limited to the structure shown in FIG.
  • a method for preparing an OLED device includes the following steps:
  • step S2 Prepare the first electrode layer 2 on the basis of step S1.
  • the first electrode layer 2 covers the buffer layer 6 and the auxiliary electrode 7, and the first electrode layer 2 on one or both sides of the auxiliary electrode 7 is etched away to expose the buffer Layer 6; etching to form a short-circuit prevention structure layer 13;
  • step S3 Depositing a pixel defining layer 12 on the basis of step S2, the pixel defining layer 12 covers the first electrode layer 2 and the buffer layer 6 located in the packaging area, and etching the pixel defining layer 12 to form an opening in a trapezoidal structure;
  • step S4 On the basis of step S3, the luminescent material layer 2 and the second electrode layer 3 are fabricated by evaporation, and a continuous organic luminescent layer 3 and the second electrode layer 4 are formed on the pixel defining layer 12 and in the opening.
  • step S5 the encapsulation layer 10 is produced by chemical vapor deposition.
  • a continuous organic light-emitting layer 3, a second electrode layer 4 and an encapsulation layer are formed on the pixel defining layer 12 and in the opening, and the encapsulation is located in the encapsulation area.
  • the layer is in direct contact with the buffer layer;
  • step S6 a package transition layer, such as UV glue or OCA glue, is attached, and then a cover plate is attached to the package transition layer for film packaging and sealing.
  • the cover plate here may include glass, copper foil, aluminum foil, etc.
  • the average life of the device of Example 5 of the present invention is 1000h@1000nit
  • the average life of the device of Example 6 is 1050h@1000nit
  • the average life of the device of Comparative Example 2 is 580h@1000nit. Therefore, the life of the device is greatly improved. .

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Abstract

本发明提供了一种OLED器件及其制备方法，包括基板和封装层，基板划分为像素区域和封装区域，基板和封装层之间通过密封介质实现连接，在基板上的像素区域叠加设置有第一电极层、有机发光层和第二电极层，第一电极层和基板之间设置有缓冲层。本发明通过设置缓冲层解决干刻辅助电极出现的侧蚀现象，同时阻挡玻璃基板的金属离子渗入到第一电极层/辅助电极，避免发生电化学腐蚀；通过增加辅助电极，提高屏体的亮度均匀性；同时在第一电极层及辅助电极上设置有像素限定层，与缓冲层直接接触，像素限定层的材质与缓冲层的材质均为无机化合物，对OLED有效像素区和/或像素形成很好的包围结构，避免挥发性气体outgas释放进像素内部，引起像素收缩，提高了OLED屏体的可靠性。

Description

一种OLED器件及其制备方法 技术领域
本发明涉及OLED器件领域，具体涉及一种OLED器件及其制备方法。
背景技术
有机电致发光器件(OLED器件)相比其他的照明方式(如蜡烛、卤素灯、LED灯)相比有更多的优点，例如无紫外、无红外辐射，光线柔和、无眩光、无频闪，光谱丰富、显色质量高等。并且可以应用在通用照明、汽车照明和显示领域。目前制约OLED器件的一大瓶颈为其使用寿命。
传统的OLED器件结构包含基板、阳极、绝缘层、有机功能层、阴极和封装结构。其中基板通常为普通的无碱玻璃(Glass)；阳极通常为透明导电氧化物(如氧化铟锡ITO，铝掺氧化锌AZO)；绝缘层一般为光刻树脂，材质为酚醛树脂或者聚甲基丙烯酸甲酯；有机功能层又可以包含空穴注入层(HIL)、空穴传输层(HTL)、发光层(EML)、电子传输层(ETL)、电子注入层(EIL)等。封装层可以玻璃封装盖，通过UV胶与基板进行粘合，起到保护有机功能层的作用。传统的器件结构包含以下劣势：
(1)由于基板与阳极直接接触，基板中的某些离子(如钾离子、钙离子等)会渗透到阳极中发生电化学腐蚀，进而影响阳极的功函数，增加OLED的功耗，进而导致OLED寿命降低；
(2)采用的光刻树脂绝缘层，因为通常为有机树脂，OLED在长时间点亮下会导致树脂中释放有害气体(outgas),如水、二氧化碳、硫化合物等。Outgas进一步与有机功能层起化学反应，影响有机功能层的性能，进而影响OLED寿命；
(3)通常大面积OLED器件会存在亮度不均匀现象，可以通过增加辅助电极(如钼铝钼)提高亮度均匀性。但业界采用干刻方法进行蚀刻，在干刻过程中容易产生图4底切(Undercut)问题，主要原因是在干刻过程， 干刻气体在纵向蚀刻过程中，在基板侧发生的“侧蚀”所致，“底切”并不是所预期的，因为会导致后续OLED膜层的不连续、断裂，进而导致封装失效和点亮异常，从而影响器件使用寿命；
(4)OLED在制备过程中不可避免的引入杂质(Particle),由于器件膜层相对比较薄(＜500nm),Particle的引入可能导致器件的阳极和阴极接触，形成短路点。电流流经短路点，形成黑斑，黑斑扩大进而导致整屏失效；
(5)OLED有机材料易受水氧侵蚀，薄膜封装是一种很好的方式，但是由于薄膜封装一般由化学气相沉积PECVD方法形成一层无机材料如氧化硅、氮化硅或氮氧化硅，薄膜封装通常具有很大的应力，当应力释放后，会导致薄膜起皱或者断裂，影响薄膜封装效果，进而导致水氧侵蚀，影响OLED器件的寿命。
发明内容
因此，本发明要解决的技术问题在于现有技术中因材料或者结构所导致的器件寿命差及失效的问题，为此本发明提供了一种OLED器件及其制备方法，通过在基板上增加一层缓冲层，可以阻挡玻璃中的金属离子渗透进器件中。同时增加的缓冲层可以改善其上辅助电极的干刻底切问题，且辅助电极的Taper角为20-80°，提高器件封装寿命；此外通过选择无机化合物作为像素限定层，避免挥发性气体outgas释放进像素内部，引起像素收缩，提高了OLED屏体的可靠性。且在第一电极层及辅助电极上设置的像素限定层，与缓冲层直接接触，对OLED有效像素区和/或像素形成很好的包围结构，降低工艺过程中引入的杂质或气体对像素区的侵蚀。同时对位于封装区的像素限定层和/或缓冲层进行图形化，OLED材料上面的封装层与经过图形化的像素限定层和/或缓冲层直接接触，进一步形成很好的应力释放结构，增加了界面封装效果，降低水氧的侵入，提升了封装可靠性。
为实现上述发明目的，本发明采用如下技术方案：
一种OLED器件，包括基板和封装层，所述基板与所述封装层所形成 的密闭空间内设置有第一电极层、辅助电极和像素限定层，
所述第一电极层/辅助电极和基板之间设置有缓冲层，所述缓冲层上设置有若干间隔排布的辅助电极，所述第一电极层覆盖所述缓冲层和辅助电极，所述像素限定层完全覆盖所述辅助电极上的第一电极层且图形化有使第一电极层的至少一部分露出的开口，所述像素限定层和开口内覆盖有连续的有机发光层和第二电极层。
所述基板上划分有若干个呈阵列分布的像素区和包围所有所述像素区的封装区，每个所述像素区边缘位置分别被所述像素限定层包围，所述辅助电极分布于呈阵列分布的像素区的横列位置和/或纵列位置；蚀刻去除所述封装区的第一电极层和辅助电极，使像素限定层与所述缓冲层直接接触设置。
位于所述封装区内的所述缓冲层上成型有连续设置的图形化结构，所述封装层与所述缓冲层上所成型的图形化结构直接接触。
所述图形化结构为在所述缓冲层上图形化的若干个凹槽结构和/或堤坝结构。
蚀刻去除位于辅助电极一侧或两侧的第一电极层，使位于该区域的像素限定层与所述缓冲层直接接触设置。
位于每一辅助电极一侧或两侧的所述第一电极层与所述缓冲层直接接触区域的宽度为1μm-1㎝。
与辅助电极相垂直的方向上，呈阵列分布的相邻两像素区之间使所述第一电极层图形化有防短路结构层，所述防短路结构层与所述辅助电极上的第一电极层及两相邻所述像素区中的其中一个所述像素区电性连接，与另一像素区形成断路；位于所述防短路结构层两侧的像素限定层与所述缓冲层直接接触。
进一步地，所述像素限定层与位于每一辅助电极一侧或两侧的所述缓冲层直接接触区域的宽度为5μm-10mm。
钛(Ti)、铝(Al)、钼(Mo)、铜(Cu)几种金属之间的一种或多种组合。
所述辅助电极所形成的Taper角度为10-90°。
所述辅助电极中刻蚀速率小的材料与所述缓冲层的材料的蚀刻选择比为(0.5-20)；
所述像素限定层的材料与所述缓冲层的材料的蚀刻选择比(0.5-5)。
进一步优选地，所述辅助电极的材料与所述缓冲层的材料的蚀刻选择比为(5-7)。
所述缓冲层的厚度10nm-3μm。
位于所述辅助电极之间的所述缓冲层上还设有平坦化的辅助缓冲层，所述辅助电极高出所述辅助缓冲层0-1μm。
所述像素限定层、缓冲层与封装层的材料相同或不同，为氮化硅、氧化硅或氮氧化硅中的一种或几种的组合。
所述封装层为薄膜封装结构，其上还设有盖板，所述盖板通过封装过渡层与所述封装层相结合。
或者，所述封装层为一封装盖，所述封装盖通过UV胶与所述基板上封装区域的缓冲层相结合。
同时，本发明还提供了一种OLED器件的制备方法，包括下述步骤：
S1、在基板上划分像素区和包围所述像素区的封装区，在基板上沉积缓冲层，所述缓冲层上制备辅助电极，经蚀刻形成若干间隔排布的辅助电极，辅助电极的Taper角度为10-90°；
S2、在步骤S1的基础上制备第一电极层，所述第一电极层覆盖所述缓冲层和辅助电极，蚀刻去除位于所述辅助电极与所述封装区之间的第一电极层，以露出缓冲层；
S3、在步骤S2的基础上沉积像素限定层，所述像素限定层覆盖所述第一电极层和缓冲层，蚀刻像素限定层形成开口，所述开口的底部为第一电极层与缓冲层；
S4、在步骤S3基础上通过蒸镀方式制作有机发光层和第二电极层，所述像素限定层上和开口内形成有连续的有机发光层和第二电极层；
S5、在步骤S4基础上制作封装层，封装层覆盖整个像素区，在包围像素区的封装区将整个像素区进行密封防护。
所述的步骤S2为：在步骤S1的基础上制备第一电极层，所述第一 电极层覆盖所述缓冲层和辅助电极，蚀刻去除位于所述辅助电极一侧或两侧的第一电极层，以露出缓冲层；蚀刻形成防短路结构层。
所述的步骤S3中，将位于所述封装区内的缓冲层上成型若干个图形化的凹槽结构和/或堤坝结构；在步骤S5中封装时，所述封装层与缓冲层上图形化的凹槽结构和/或堤坝结构直接接触。
与现有技术相比，本发明的技术方案具有如下有益效果：
(1)本发明在玻璃基板上增加一缓冲层，可以阻挡玻璃基板的金属离子渗入到第一电极层/辅助电极，避免发生电化学腐蚀，提高OLED器件的稳定性。
(2)通过增加的缓冲层结构，可以避免在干刻或蚀刻形成辅助电极过程中出现的侧蚀，进而有效解决了“底切”(undercut)现象的发生。改善了后续有机/金属/封装膜层连续性，进而提高了封装可靠性及屏体寿命。
(3)本发明通过第一电极的图形化引入防短路结构，可以使得器件在长期老化(如长期点亮)不发生因为器件短路所导致的屏体失效。
(4)本发明通过选择无机化合物(如氧化硅，氮化硅，氮氧化硅)作为像素限定层，避免挥发性气体outgas释放进像素内部，引起像素收缩，提高了OLED屏体的可靠性。且在第一电极层及辅助电极上设置的像素限定层，与缓冲层直接接触，对OLED有效像素区和/或像素形成很好的包围结构，降低工艺过程中引入的杂质或气体对像素区的侵蚀，进而提高了屏体的寿命。
(5)本发明提供的OLED器件，对位于封装区内的缓冲层进行图形化的凹槽结构制作和/或在缓冲层上设置堤坝结构，封装层与缓冲层上图形化的凹槽结构和/或堤坝结构直接接触，进一步形成很好的应力释放结构，增加了界面键合封装效果，降低水氧的侵入，提升了封装可靠性及屏体寿命。
(6)作为本发明的一种特殊结构，本发明还在辅助电极之间的缓冲层6上增加辅助缓冲层氮化硅(或氧化硅)结构，通过诸如干刻、研磨、剥离(Lift-off)方法进行辅助缓冲层结构制作及平坦化，辅助电极高出辅助 缓冲层的高度D为0-1μm。这样使得后续的第一电极层更加平面化，有助于提高搭接电阻(辅助电极与第一电极的接触的电阻)的均匀性。
附图说明
为了更清楚地说明本发明具体实具有指纹识别功能的液晶二极管施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明OLED器件示意图；
图2为图1的A-A'剖视图；
图3为本发明辅助电极的结构示意图；
图4为现有技术辅助电极的结构示意图；
图5为在缓冲层上设置辅助缓冲层结构示意图；
图6为制备完成像素限定层后的俯视图；
图7为图6的C-C'剖视图；
图8为图6的D-D'剖视图；
图9为图8的局部放大图；
图10为本发明所提供的带有盖板的结构示意图；
图11为图10所示第一种局部结构示意图；
图12为图10所示第二种局部结构示意图；
图13为图10所示第三种局部结构示意图；
图14为图10所示第四种局部结构示意图。
附图标记说明：1-基板，2-第一电极层，3-有机发光层，4-第二电极层，5-盖板，6-缓冲层，7-辅助电极，8-UV胶，9-封装区，10-封装层，11-像素区，12-像素限定层，13-防短路结构层，14-辅助缓冲层，15-堤坝结构，16-凹槽结构，17-开口；18-封装过渡层。
具体实施方式
下面将结合附图对本发明的技术方案进行清楚、完整地描述，显然， 所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
本发明可以以许多不同的形式实施，而不应该被理解为限于在此阐述的实施例。相反，提供这些实施例，使得本公开将是彻底和完整的，并且将把本发明的构思充分传达给本领域技术人员，本发明将仅由权利要求来限定。在附图中，为了清晰起见，会夸大层和区域的尺寸和相对尺寸。应当理解的是，当元件例如层、区域或基板被称作“形成在”或“设置在”另一元件“上”时，该元件可以直接设置在所述另一元件上，或者也可以存在中间元件。相反，当元件被称作“直接形成在”或“直接设置在”另一元件上时，不存在中间元件。
此外，下面所描述的本发明不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
如图1和图2所示，本发明提供的一种OLED器件，包括基板1和封装层10，基板1与封装层10所形成的密闭空间内设置有第一电极层2、辅助电极7和像素限定层12，第一电极层/和基板之间设置有缓冲层6，缓冲层6上设置有若干间隔排布的辅助电极7，第一电极层2覆盖缓冲层6和辅助电极7，像素限定层12完全覆盖辅助电极上的第一电极层2且图形化有使第一电极层2的至少一部分露出的开口17，开口17形状为梯形结构，梯形的底部为第一电极层2，像素限定层12和开口17内覆盖有连续的有机发光层3、第二电极层4和封装层10。
在基板1上划分有若干个像素区11和包围所有像素区11的封装区，每个像素区11边缘位置分别被像素限定层12包围，辅助电极分布于呈 阵列分布的像素区的横列位置和/或纵列位置；蚀刻去除位于辅助电极7与封装区之间的第一电极层2和辅助电极7，位于辅助电极7与封装区之间的像素限定层12与缓冲层直接接触设置；优选，像素限定层12与缓冲层6直接接触区域的宽度为5μm-10mm。
作为优选的实施方式，如图6所示，蚀刻去除位于辅助电极7一侧或两侧的第一电极层2，使位于该区域的像素限定层12与缓冲层直接接触设置；位于每一辅助电极7一侧或两侧的第一电极层2与缓冲层6直接接触区域的宽度为1μm-1㎝。像素限定层12与位于每一辅助电极7一侧或两侧的缓冲层6直接接触区域的宽度为5μm-10mm。
辅助电极7为钛(Ti)、铝(Al)、钼(Mo)、铜(Cu)几种金属之间的一种或多种组合。比如采用钛铝钛(TiAlTi)、铝钛(AlTi)、铝钼(AlMo)、钼铝钼(MoAlMo)、钼(Mo)、钛(Ti)、铜(Cu)和铝(Al)，如图3所示，辅助电极7的Taper角度为10-90°，此处的Taper角度是指辅助电极7中铝层的Taper角。
辅助电极7中刻蚀速率小的材料与缓冲层6的材料的蚀刻选择比为(0.5-20)，优选为(5-7)；辅助电极中的Ti材料或Mo材料为刻蚀速率小的材料。
像素限定层12的材料与缓冲层6的材料的蚀刻选择比(0.5-5)。
缓冲层6的厚度10nm-3μm，优选100nm。
辅助电极7之间的缓冲层6上还设有平坦化的辅助缓冲层，辅助电极7高出辅助缓冲层0-1μm。
像素限定层12、缓冲层6与封装层的材料相同或不同，为氮化硅、氧化硅或氮氧化硅中的一种或几种的组合。
封装层10为一玻璃封装盖，玻璃封装盖5设置有UV胶8，玻璃封装盖5与基板1上的缓冲层6和/或限定像素层12通过UV胶8结合。
当然，封装层还可以采用薄膜封装方式，通过化学气相沉积的方式制作封装层10。像素限定层12上和开口内由下至上依次覆盖有机发光层3、第二电极层4以及封装层。同时位于封装区的封装层与缓冲层直接接触，形成薄膜封装；通过在封装层上贴附封装过渡层，比如UV胶，OCA 胶，然后在封装过渡层上贴附盖板进行密封，这里的盖板可以包含玻璃，铜箔、铝箔等。
为了使OLED封装区的封装效果更佳，位于封装区内的缓冲层6上成型有连续设置的图形化结构，封装层10与缓冲层6上所成型的图形化结构直接接触。如图12、图13和图14所示，这里的图形化结构为在缓冲层6上图形化的若干个凹槽结构16和/或堤坝结构15，封装层覆盖在图形化结构上，封装层10与缓冲层6上图形化的凹槽结构16和/或堤坝结构15直接接触，进一步形成很好的应力释放结构，增加了界面键合封装效果，降低水氧的侵入，提升了封装可靠性。
一种OLED器件的制备方法，如图1至图2所示，包括下述步骤：
S1、在基板1上划分像素区11和包围像素区11的封装区，在像素区上沉积缓冲层6，缓冲层6上制备辅助电极7，经蚀刻形成若干间隔排布的辅助电极7，辅助电极7的Taper角度为10-90°；
S2、在步骤S1的基础上制备第一电极层2，第一电极层2覆盖缓冲层6和辅助电极7，蚀刻去除位于辅助电极7与封装区9之间的第一电极层2，以露出缓冲层6；
S3、在步骤S2的基础上沉积像素限定层12，像素限定层12覆盖第一电极层2和缓冲层6，蚀刻像素限定层12形成梯形结构的开口，梯形结构的底部为第一电极层2与缓冲层6；
S4、在步骤S3基础上通过蒸镀方式制作有机发光材料层3和第二电极层4，像素限定层12上和开口内形成有连续的有机发光层3和第二电极层4；
S5、在步骤S4基础上制作封装层10，封装层10覆盖整个像素区11，在包围像素区11的封装区9将整个像素区11进行密封防护。
如图6至图9所示结构制备时，其他步骤同上，其中步骤S2为：在步骤S1的基础上制备第一电极层2，第一电极层2覆盖缓冲层6和辅助电极7，蚀刻去除位于辅助电极7一侧或两侧的第一电极层2，以露出缓冲层6；蚀刻形成防短路结构层13，防短路结构层13位于像素限定层下方并被像素限定层覆盖。
各层所用材料及厚度如下：
缓冲层：所述缓冲层为无机材料，如氮化硅、氧化硅、氮氧化硅，膜层沉积方式可以利用化学气相沉积(CVD)，原子层沉积(ALD)。缓冲层优选氮化硅，厚度为10nm-3μm，优选100nm-150nm。
辅助电极：辅助电极为金属或者金属合金，如钛铝钛(TiAlTi)、铝钛(AlTi)、钼铝(MoAl)、钼铝钼(MoAlMo)、Mo、Ti、Cu、Al，采用干刻工艺或者湿刻工艺进行图形化；优选TiAlTi三层结构，底Ti50-100nm，优选75nm，顶钛50-100nm，优选50nm，Al为300-700nm，优选300nm；通过Cl 2与BCl 3(不限于此两种气体)进行干刻，10≤Taper角度≤90°，优选为20-80°。其中钛铝(AlTi)结构自下而上依次为Al材料层和Ti材料层,如图3所示；其中钼铝钼(MoAlMo)结构自下而上依次为Mo材料层，Al材料层和Mo材料层。
第一电极层：透明导电金属氧化物，如ITO、AZO，通过PVD溅射；图形化采用干刻或湿法蚀刻，优选湿法蚀刻，如采用盐酸、硝酸、醋酸等或其混酸进行蚀刻；优选具有防短路的图形化结构，即通过对第一电极的图形化，可以形成像素，参考附图6。
像素限定层(或称介电层或绝缘层)，在第一电极层和/或辅助电极以上，材质为氧化硅、氮化硅或者氮氧化硅，采用与缓冲层相同工艺(如CVD、ALD)，厚度200nm-500nm，优选300nm，与缓冲层的蚀刻选择比(0.5-5)；通过第一电极图形化形成“像素”，可以使得像素限定层与缓冲层直接接触，如附图中H≥0.5μm。进而使得像素限定层对OLED有效像素区和/或像素形成很好的包围结构，避免outgas释放进像素内部，引起像素收缩，提高了OLED屏体的可靠性，且像素限定层与缓冲层的材质大体相同，界面键合性质更稳固，进一步提高了屏体的封装可靠性。
有机发光层3：包括但不限于空穴注入层(HIL)、空穴传输层(HTL)、发光层(EL)、电子传输层(ETL)、电子注入层(EIL)等。
第二电极层4，包括Al电极，MgAg电极，金属氧化物电极(如ITO)等。如通过热蒸发溅射一层厚度为200nm的Al；
封装层10：将有机发光层3进行封装，通过传统封装的玻璃封装盖 与UV胶或玻璃料的组合进行封装。如利用UV胶将基板和封装盖进行封装，避免水氧侵蚀。
当然，为了提高屏体封装可靠性，采用薄膜封装方式，如无机层/有机层/无机层，无机层可以采用化学气相沉积(CVD)进行薄膜沉积，有机层采用喷墨打印(IJP)进行薄膜打印。如采用SiO(1μm)/IJP(8μm)/SiO(1μm)。
本发明具有下述实施例：
实施例1
如图1和图2所示，本发明提供的一种OLED器件，包括基板1和封装层10，基板1上划分有像素区11和包围像素区11的封装区9，封装区9内设置有UV胶8将基板1和封装层10密封连接后形成密闭空间，这里的封装层为一玻璃封装盖，可在封装盖靠近基板1的一侧设置有干燥片吸收水汽，利用UV胶作为密封材料层将基板和封装盖进行封装，提高屏体封装可靠性。缓冲层6的厚度10nm-3μm。
基板1的发光区设置有缓冲层6，缓冲层6上设置若干间隔排布的辅助电极7，第一电极层2覆盖缓冲层6和辅助电极7，蚀刻去除位于辅助电极7与封装区之间的第一电极层2，蚀刻去除的第一电极层2的宽度H＝10μm，以露出缓冲层6；
像素限定层12完全覆盖辅助电极上的第一电极层且图形化有使第一电极层的至少一部分露出的开口，开口形状为梯形结构，梯形的底部为第一电极层2，像素限定层和开口内覆盖有连续的有机发光层3和第二电极层4。由于位于辅助电极7与封装区9之间的缓冲层6上无第一电极层，因此，此区域的缓冲层6与像素限定层12直接接触设置。
像素限定层12与缓冲层6直接接触区域的宽度H为10μm。
辅助电极7包括叠加设置的Al材料层、Ti材料层，Ti材料层位于Al材料层的上方。如图3所示，辅助电极7的Taper角度为20-80°。由图3与图4对比可以看出，增加SiN缓冲层可以有效的改善AlTi的Taper角，这是因为Al与Ti的蚀刻选择比较大，蚀刻Al的速率＞蚀刻Ti的速率，未加SiN，会在基板侧发生侧蚀，导致底切的现象。同时，由于增加的缓 冲层Buffer Layer阻挡玻璃基板的金属离子渗入到ITO层，避免ITO发生电化学腐蚀，提高OLED器件的稳定性。
辅助电极7的材料与缓冲层6的材料的蚀刻选择比为(0.5-20)，优选为(5-7)；
像素限定层12的材料与缓冲层6的材料的蚀刻选择比(0.5-5)。
蚀刻选择比，意味着不同膜在同一条件下蚀刻速度的比值。即：A膜蚀刻速度为E a，B膜同一条件下的蚀刻速度为E b，这时的蚀刻选择比是S A/B＝E a/E b
像素限定层与缓冲层的材料相同或不同，为氮化硅、氧化硅或氮氧化硅中的一种或几种的组合。
一种OLED器件的制备方法，如图6至图9所示，包括下述步骤：
S1、在基板1上划分像素区11和包围像素区11的封装区，在像素区上沉积缓冲层6，缓冲层6上制备辅助电极，经蚀刻形成若干间隔排布的辅助电极7，辅助电极7的Taper角度为20-80°；
S2、在步骤S1的基础上制备第一电极层2，所述第一电极层2覆盖缓冲层6和辅助电极7，蚀刻去除位于辅助电极7与封装区之间的第一电极层2，以露出缓冲层6；
S3、在步骤S2的基础上沉积像素限定层12，像素限定层12覆盖第一电极层2和位于辅助电极7与封装区之间的缓冲层6，蚀刻像素限定层12形成梯形结构的开口，梯形结构的底部为第一电极层2和缓冲层；
S4、在步骤S3基础上通过蒸镀方式制作发光材料层2和第二电极层3，像素限定层12上和开口内形成有连续的有机发光层3和第二电极层4；
S5、在步骤S4基础上制作封装层10，这里的封装层10为一玻璃封装盖，即在玻璃封装盖上涂覆UV胶，然后将其与基板上封装区位置的缓冲层密封连接，从而实现对整个像素区的封装，如图2所示。
本实施例中各层所采用的材料及厚度如下：
基板1，材质为无碱玻璃；
缓冲层6(Buffer层)，通过高温CVD工艺沉积一层氮化硅100nm，工艺温度350℃，与基板的附着力5B，折射率1.8；
辅助电极7为AlTi，顶钛50nm，Al为300nm；通过Cl 2与BCl 3进行干刻图形化，Taper角度70°；蚀刻并不限于干刻，也可以选用湿刻方式进行，选用H 3PO 4、CH 3COOH、HNO 3混酸按照一定配比溶液进行蚀刻；
第一电极层2，通过PVD溅射氧化铟锡(ITO)，厚度150nm，采用湿法(酸刻)工艺进行图形化；
像素限定层12，在第一电极层以上，材质为SiN，采用与Buffer相同工艺，厚度300nm，栅格大小400μm*400μm，采用干刻工艺进行图形化形成像素限定层；
有机发光层3：包括但不限于空穴注入层(HIL)、空穴传输层(HTL)、发光层(EL)、电子传输层(ETL)、电子注入层(EIL)等；
第二电极层4，包括Al电极，MgAg电极，金属氧化物电极(如ITO)。如通过热蒸发溅射一层厚度为200nm的Al；
封装层10：将有机发光层3进行封装，通过传统封装的玻璃封装盖与UV胶或玻璃料的组合进行封装。
在实施例1的基础上，分别选用不同的辅助电极7材料和缓冲层6材料，像素限定层12的材料与缓冲层6的材料的蚀刻选择比优选为1。
不同的辅助电极和缓冲层之间的蚀刻选择比所产生的效果如下表所示：
辅助电极层7与缓冲层6的蚀刻选择比 Al的Taper Al的侧蚀
<0.5 \ 有
0.5-20 70 无
>20 \ 有
由上表可知，辅助电极7的材料与缓冲层6的材料的蚀刻选择比较小(<0.5)时，容易导致缓冲层被蚀刻掉，产生图4的侧蚀问题，因此出现倒梯形；当蚀刻选择比较高(>20)时，缓冲层很难蚀刻掉，也容易出现侧蚀，进而出现倒梯形。本发明中优选的辅助电极7材料和缓冲层6材料的蚀刻选择比为5-7，可以将Al的Taper角度控制在70°±3°，同时， 像素限定层12的材料与缓冲层6的材料优选相同或者相近，可以很好地保证界面键合效果，使后续OLED膜层更加连续，封装效果更好，提高OLED器件的使用寿命。
实施例2
本发明提供的一种OLED器件基本结构同实施例1，其不同之处在于：本实施例中的封装层采用薄膜封装结构，如图10和图11所示。
S1、在基板1上划分像素区11和包围像素区11的封装区，在像素区上沉积缓冲层6，缓冲层6上制备辅助电极，经蚀刻形成若干间隔排布的辅助电极7，辅助电极7的Taper角度为10°；
S2、在步骤S1的基础上制备第一电极层2，所述第一电极层2覆盖缓冲层6和辅助电极7，蚀刻去除位于辅助电极7与封装区之间的第一电极层2，以露出缓冲层6；
S3、在步骤S2的基础上沉积像素限定层12，像素限定层12覆盖第一电极层2和位于辅助电极7与封装区之间的缓冲层6，蚀刻像素限定层12形成梯形结构的开口，梯形结构的底部为第一电极层2和缓冲层；
S4、在步骤S3基础上通过蒸镀方式制作发光材料层2和第二电极层3，像素限定层12上和开口内形成有连续的有机发光层3和第二电极层4；
S5、在步骤S4基础上制作封装层10，这里的封装层10采用薄膜封装方式，如无机层/有机层/无机层，无机层可以采用化学气相沉积(CVD)进行薄膜沉积，有机层采用喷墨打印(IJP)进行薄膜打印。如采用SiO(1μm)/IJP(8μm)/SiO(1μm)。封装层10覆盖整个像素区11，在包围像素区11的封装区9将整个像素区11进行密封防护；
S6、在盖板5上涂覆封装过渡层18，然后将盖板5盖置于封装层上，从而实现对整个像素区的封装。
与实施例1相比，采用薄膜封装方式，可以进一步提高屏体封装可靠性。
实施例3
如图6至图9所示，本发明提供的一种OLED器件基本结构同实施例 2，其不同之处在于：
基板1的发光区设置有缓冲层6，缓冲层6上设置有由第一电极层形成的防短路结构层13，若干间隔排布的辅助电极7，第一电极层2覆盖缓冲层6和辅助电极7，蚀刻去除位于辅助电极7一侧或两侧的第一电极层2，蚀刻去除的第一电极层2的宽度H＝10μm，以露出缓冲层6；通过第一电极的图形化引入防短路结构，可以使得器件在长期老化(如长期点亮)不发生因为器件短路所导致的屏体失效。
如图7所示，像素限定层12完全覆盖辅助电极上的第一电极层2且设置有使第一电极层2的至少一部分露出的开口，开口形状为梯形结构，梯形的底部为第一电极层2，像素限定层12和开口内覆盖有连续的有机发光层3和第二电极层4。由于位于辅助电极7一侧或两侧的缓冲层上无第一电极层，因此，此区域的缓冲层6与像素限定层12直接接触设置。
结合图6和图7，与辅助电极相垂直的方向上，呈阵列分布的相邻两像素区之间使第一电极层图形化有防短路结构层13，防短路结构层13与辅助电极7上的第一电极层2及两相邻像素区中的其中一个像素区电性连接，与另一像素区形成断路；位于防短路结构层13两侧的像素限定层与缓冲层6直接接触。每个像素区中的电流流向如图6箭头走向所示。
像素限定层12与位于每一辅助电极一侧或两侧的缓冲层直接接触区域的宽度H为10μm。
本实施例的一种OLED器件的制备方法，如图6、图7、图8、图9和图11所示，包括下述步骤：
S1、在基板1上划分像素区11和包围所述像素区11的封装区，在像素区上沉积缓冲层6，缓冲层6上制备辅助电极，经蚀刻形成若干间隔排布的辅助电极7，辅助电极7的Taper角度为70°；
S2、在步骤S1的基础上制备第一电极层2，第一电极层2覆盖所述缓冲层6和辅助电极7，蚀刻去除位于辅助电极7一侧或两侧的第一电极层2，以露出缓冲层6；蚀刻形成防短路结构层13；
S3、在步骤S2的基础上沉积像素限定层12，像素限定层12覆盖第一电极层2和位于辅助电极7与封装区9之间的缓冲层6，蚀刻像素限定 层12形成梯形结构的开口，梯形结构的底部为第一电极层2和缓冲层；
S4、在步骤S3基础上通过蒸镀方式制作发光材料层2和第二电极层3，像素限定层12上和开口内形成有连续的有机发光层3和第二电极层4；
S5、在步骤S4基础上制作封装层10，这里的封装层10采用薄膜封装方式，如无机层/有机层/无机层，无机层可以采用化学气相沉积(CVD)进行薄膜沉积，有机层采用喷墨打印(IJP)进行薄膜打印。如采用SiO(1μm)/IJP(8μm)/SiO(1μm)。封装层10覆盖整个像素区11，在包围像素区11的封装区9将整个像素区11进行密封防护；
S6、在盖板5上涂覆封装过渡层18，然后将盖板5盖置于封装层上，从而实现对整个像素区的封装。
实施例4
本发明提供的一种OLED器件，其基本结构同实施例3，与实施例3存在的不同之处是：
如图5所示，在基板1上还可以形成这样的结构：在基板1上形成一图形化的辅助电极7，在辅助电极7之间的缓冲层6上通过PECVD做一层辅助缓冲层14SiN(或SiOx)，通过诸如干刻或者研磨或者剥离(Lift-off)方法进行SiN(或SiOx)平坦化，需要强调的是，辅助电极7需要高出辅助缓冲层14的高度D为0～1μm，以利于第一电极层的搭接。图3所示为实施例1至实施例3中所采用的在基板上所设置的缓冲层结构，本实施例中可以避免第一电极层的爬坡，尽管本实施例中的第一电极层在辅助电极上的搭接面积小于图3中所示结构，但与实施例1和实施例2相比，本实施例在搭接电阻均匀性上会提高。
对比例1
基板1，材质为无碱玻璃，采用常规的图4所示基板结构；
辅助电极7为AlTi，顶钛50nm，Al为300nm；通过蚀刻方法制备图4所示结构；
第一电极层，通过PVD溅射氧化铟锡(ITO)，厚度150nm；
像素限定层，在第一电极层以上，材质为SiN，采用与Buffer相同工 艺，厚度300nm，栅格大小400μm*400μm；
有机发光层，包括HIL、HTL、EL、ETL、EIL；
第二电极，包括Al电极，通过热蒸发溅射一层厚度为200nm的Al；
封装层，为一玻璃封装盖，利用UV胶将基板的封装区和封装盖进行玻璃封装结合，提高屏体封装可靠性。
实验测试结果如下：
在1000亮度下，采用寿命测试进行测试，可以看出本发明的器件由于增加了缓冲层可以提升5倍的OLED器件的寿命。说明增加缓冲层可以明显提高屏体可靠性。主要原因如下：
由于缓冲层的存在，使得干刻第一电极或者辅助电极形成更加锐角的Taper角，即由于缓冲层的设置可以很好的改善上述辅助电极的“底切”现象，避免出现“侧蚀”，更好的修饰辅助电极的Taper角，从而提高后续有机/金属/封装膜层的搭接性。
更进一步地，增加缓冲层可以阻挡玻璃基板的金属离子渗入到第一电极层/辅助电极，避免发生电化学腐蚀，提高OLED器件的稳定性。
经测试，本发明实施例1的器件的平均寿命为500h@1000nit，器件在长期老化下1000H的失效率为20％；
实施例2的器件的平均寿命为550h@1000nit器件在长期老化下1000H的失效率为10％；
实施例3的器件的平均寿命为560h@1000nit，且因为增加了防短路结构，器件在长期老化下1000H无失效；
实施例4的器件的平均寿命为600h@1000nit，且因为增加了防短路结构，器件在长期老化下1000H无失效；
对比例1的器件的平均寿命为100h@1000nit。
通过比对，本发明所采用的实施例1至实施例4相较于现有技术，可以大大提高器件寿命。
实施例5
本实施例是在实施例3的基础上，在位于封装区内的缓冲层处设置 了环绕整个像素区的连续的堤坝结构，具体如图12所示。
一种OLED器件的制备方法，包括下述步骤：
S1、在基板1上划分像素区11和包围所述像素区11的封装区，在像素区上沉积缓冲层6，所述缓冲层6上制备辅助电极7，经蚀刻形成若干间隔排布的辅助电极7，辅助电极7的Taper角度为70°；
S2、在步骤S1的基础上制备第一电极层2，第一电极层2覆盖缓冲层6和辅助电极7，蚀刻去除位于辅助电极7一侧或两侧的第一电极层2，以露出缓冲层6，蚀刻形成防短路结构层13；
S3、在步骤S2的基础上沉积像素限定层12，像素限定层12覆盖第一电极层2和位于封装区的缓冲层6，蚀刻像素限定层12形成梯形结构的开口，且在封装区形成凸起的堤坝结构(DAM)；
S4、在步骤S3基础上通过蒸镀方式制作有机发光层3和第二电极层4，像素限定层12上和开口内形成有连续的有机发光层3和第二电极层4。
S5、在步骤S4基础上通过化学气相沉积的方式制作封装层10，像素限定层12上和开口内形成有连续的有机发光层3和第二电极层4以及封装层。同时位于封装区的封装层与缓冲层直接接触，形成薄膜封装；
S6、通过在步骤S5上贴附封装过渡层，比如UV胶，OCA胶，然后在封装过渡层上贴附盖板进行密封，这里的盖板可以包含玻璃，铜箔、铝箔等。
实施例6
与实施例5不同的是，本实施例对位于封装区内的缓冲层进行图形化结构，具体如图13所示，图形化结构围绕所有像素区的呈连续设置的两凹槽结构，同时还在封装区的内侧设置了凸起的堤坝结构。
一种OLED器件的制备方法，包括下述步骤：
S1、在基板1上划分像素区11和包围所述像素区11的封装区，在像素区上沉积缓冲层6，在封装区对缓冲层6进行图形化，形成两个凹槽结构16，在缓冲层6上制备辅助电极，经蚀刻形成若干间隔排布的辅助电极7，辅助电极7的Taper角度为70°；
S2、在步骤S1的基础上制备第一电极层2，第一电极层2覆盖缓冲层6和辅助电极7，蚀刻去除位于辅助电极7一侧或两侧的第一电极层2，以露出缓冲层6；蚀刻形成防短路结构层13；
S3、在步骤S2的基础上沉积像素限定层12，像素限定层12覆盖第一电极层2和位于封装区的缓冲层6，蚀刻像素限定层12形成梯形结构的开口，且在封装区的内侧形成一个凸起的堤坝结构(DAM)；
S4、在步骤S3基础上通过蒸镀方式制作发光材料层2和第二电极层3，像素限定层12上和开口内形成有连续的有机发光层3和第二电极层4。
S5、在步骤S4基础上通过化学气相沉积的方式制作薄膜封装层10，像素限定层12上和开口内形成有连续的有机发光层3和第二电极层4以及封装层。同时位于封装区的封装层与缓冲层直接接触，形成薄膜封装；
S6、通过在步骤S5上贴附封装过渡层，比如UV胶，OCA胶，然后在封装过渡层上贴附盖板进行密封，这里的盖板可以包含玻璃，铜箔、铝箔等。
当然，在封装区设置的图形化结构不限于图12和图13所示结构，还可以仅在封装区内设置图形化的凹槽结构，如图14所示，或者不局限于图13所示凹槽结构与堤坝结构的组合顺序，以及所图形化的凹槽结构数量和堤坝结构数量。这里不再赘述。
对比例2(实施例5与实施例6的对比例)
一种OLED器件的制备方法，如图10和图11所示，包括下述步骤：
S1、在基板1上划分像素区11和包围像素区11的封装区，在像素区上沉积缓冲层6，缓冲层6上制备辅助电极，经蚀刻形成若干间隔排布的辅助电极7，辅助电极7的Taper角度为70°；
S2、在步骤S1的基础上制备第一电极层2，第一电极层2覆盖缓冲层6和辅助电极7，蚀刻去除位于辅助电极7一侧或两侧的第一电极层2，以露出缓冲层6；蚀刻形成防短路结构层13；
S3、在步骤S2的基础上沉积像素限定层12，像素限定层12覆盖第一电极层2和位于封装区的缓冲层6，蚀刻像素限定层12形成梯形结构 的开口；
S4、在步骤S3基础上通过蒸镀方式制作发光材料层2和第二电极层3，像素限定层12上和开口内形成有连续的有机发光层3和第二电极层4。
S5、在步骤S4基础上通过化学气相沉积的方式制作封装层10，像素限定层12上和开口内形成有连续的有机发光层3和第二电极层4以及封装层，同时位于封装区的封装层与缓冲层直接接触；
S6、通过在步骤S5上贴附封装过渡层，比如UV胶，OCA胶，然后在封装过渡层上贴附盖板进行薄膜封装密封，这里的盖板可以包含玻璃，铜箔、铝箔等。
经测试，本发明实施例5的器件的平均寿命为1000h@1000nit，实施例6的器件的平均寿命为1050h@1000nit，而对比例2器件的平均寿命为580h@1000nit.因此大大提高了器件寿命。
因此，说明在封装区对缓冲层以及像素限定层进行图形化可以大大提高器件的寿命。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本发明创造的保护范围之中。

Claims (20)

  1. 一种OLED器件，包括基板(1)和封装层(10)，所述基板(1)与所述封装层(10)所形成的密闭空间内设置有第一电极层、辅助电极和像素限定层(12)，其特征在于，
    所述第一电极层/辅助电极和基板(1)之间设置有缓冲层(6)，所述缓冲层(6)上设置有若干间隔排布的辅助电极(7)，所述第一电极层(2)覆盖所述缓冲层(6)和辅助电极(7)，所述像素限定层(12)完全覆盖所述辅助电极(7)上的第一电极层(2)且图形化有使第一电极层(2)的至少一部分露出的开口，所述像素限定层(12)和开口内覆盖有连续的有机发光层(3)和第二电极层(4)。
  2. 根据权利要求1所述OLED器件，其特征在于，所述基板(1)上划分有若干个呈阵列分布的像素区(11)和包围所有所述像素区(11)的封装区(9)，每个所述像素区(11)边缘位置分别被所述像素限定层(12)包围，所述辅助电极分布于呈阵列分布的像素区的横列位置和/或纵列位置；蚀刻去除所述封装区(9)的第一电极层(2)和辅助电极(7)，使像素限定层(12)与所述缓冲层(6)直接接触设置。
  3. 根据权利要求1或2所述OLED器件，其特征在于，位于所述封装区内的所述缓冲层(6)上成型有连续设置的图形化结构，所述封装层(10)与所述缓冲层(6)上所成型的图形化结构直接接触。
  4. 根据权利要求3所述OLED器件，其特征在于，所述图形化结构为在所述缓冲层(6)上图形化的若干个凹槽结构(16)和/或堤坝结构(15)。
  5. 根据权利要求4所述OLED器件，其特征在于，蚀刻去除位于辅助电极(7)一侧或两侧的第一电极层(2)，使位于该区域的像素限定层(12)与所述缓冲层(6)直接接触设置。
  6. 根据权利要求5所述OLED器件，其特征在于，位于每一辅助电极(7)一侧或两侧的所述第一电极层(2)与所述缓冲层(6)直接接触 区域的宽度为1μm-1㎝。
  7. 根据权利要求6所述OLED器件，其特征在于，与辅助电极相垂直的方向上，呈阵列分布的相邻两像素区之间，使所述第一电极层图形化有防短路结构层(13)，所述防短路结构层(13)与所述辅助电极(7)上的第一电极层(2)及两相邻所述像素区中的其中一个所述像素区电性连接，与另一像素区形成断路；位于所述防短路结构层(13)两侧的像素限定层与所述缓冲层(6)直接接触。
  8. 根据权利要求7所述OLED器件，其特征在于，所述像素限定层(12)与位于每一辅助电极(7)一侧或两侧的所述缓冲层直接接触区域的宽度为5μm-10mm。
  9. 根据权利要求1所述OLED器件，其特征在于，所述辅助电极(7)为钛(Ti)、铝(Al)、钼(Mo)、铜(Cu)几种金属之间的一种或多种组合。
  10. 根据权利要求1所述OLED器件，其特征在于，所述辅助电极(7)所形成的Taper角度为10-90°。
  11. 根据权利要求1所述OLED器件，其特征在于，
    所述辅助电极(7)中刻蚀速率小的材料与所述缓冲层(6)的材料的蚀刻选择比为(0.5-20)；
    所述像素限定层(12)的材料与所述缓冲层(6)的材料的蚀刻选择比(0.5-5)。
  12. 根据权利要求11所述OLED器件，其特征在于，所述辅助电极(7)的材料与所述缓冲层(6)的材料的蚀刻选择比为(5-7)。
  13. 根据权利要求1所述OLED器件，其特征在于，所述缓冲层(6)的厚度10nm-3μm。
  14. 根据权利要求12所述OLED器件，其特征在于，位于所述辅助电极(7)之间的所述缓冲层(6)上还设有平坦化的辅助缓冲层(14)，所述辅助电极(7)高出所述辅助缓冲层(14)0-1μm。
  15. 根据权利要求1所述OLED器件，其特征在于，所述像素限定层(12)、缓冲层(6)与封装层(10)的材料相同或不同，为氮化硅、氧化硅或氮氧化硅中的一种或几种的组合。
  16. 根据权利要求1所述OLED器件，其特征在于，所述封装层(10)为薄膜封装结构，其上还设有盖板(5)，所述盖板(5)通过封装过渡层(18)与所述封装层(10)相结合。
  17. 根据权利要求1所述OLED器件，其特征在于，所述封装层(10)为一封装盖，所述封装盖通过UV胶(8)与所述基板(1)上封装区域的缓冲层(6)相结合。
  18. 一种OLED器件的制备方法，其特征在于，包括下述步骤：
    S1、在基板(1)上划分像素区(11)和包围所述像素区(11)的封装区，在基板上沉积缓冲层(6)，所述缓冲层(6)上制备辅助电极层辅助电极，经蚀刻形成若干间隔排布的辅助电极(7)，辅助电极(7)的Taper角度为10-90°；
    S2、在步骤S1的基础上制备第一电极层(2)，所述第一电极层(2)覆盖所述缓冲层(6)和辅助电极(7)，蚀刻去除位于所述辅助电极(7)与所述封装区之间的第一电极层(2)，以露出缓冲层(6)；
    S3、在步骤S2的基础上沉积像素限定层(12)，所述像素限定层(12)覆盖所述第一电极层(2)和缓冲层(6)，蚀刻像素限定层(12)形成开口，所述开口的底部为第一电极层(2)与缓冲层(6)；
    S4、在步骤S3基础上通过蒸镀方式制作有机发光层(3)和第二电极层(4)，所述像素限定层(12)上和开口内形成有连续的有机发光层(3)和第二电极层(4)；
    S5、在步骤S4基础上制作封装层，封装层覆盖整个像素区，在包围像素区(11)的封装区将整个像素区(11)进行密封防护。
  19. 根据权利要求18所述OLED器件的制备方法，其特征在于，所 述的步骤S2为：在步骤S1的基础上制备第一电极层(2)，所述第一电极层(2)覆盖所述缓冲层(6)和辅助电极(7)，蚀刻去除位于所述辅助电极(7)一侧或两侧的第一电极层(2)，以露出缓冲层(6)；蚀刻形成防短路结构层(13)。
  20. 根据权利要求18所述OLED器件的制备方法，其特征在于，所述的步骤S3中，将位于所述封装区内的缓冲层(6)上成型若干个图形化的凹槽结构和/或堤坝结构；在步骤S5中封装时，所述封装层(10)与缓冲层(6)上图形化的凹槽结构(16)和/或堤坝结构(15)直接接触。
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