WO2020156160A1 - 升压芯片及其短路保护电路 - Google Patents

升压芯片及其短路保护电路 Download PDF

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Publication number
WO2020156160A1
WO2020156160A1 PCT/CN2020/072163 CN2020072163W WO2020156160A1 WO 2020156160 A1 WO2020156160 A1 WO 2020156160A1 CN 2020072163 W CN2020072163 W CN 2020072163W WO 2020156160 A1 WO2020156160 A1 WO 2020156160A1
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Prior art keywords
short
circuit
gate
tube
switch
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PCT/CN2020/072163
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English (en)
French (fr)
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黄建刚
程剑涛
王云松
吴传奎
董渊
孙洪军
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上海艾为电子技术股份有限公司
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Publication of WO2020156160A1 publication Critical patent/WO2020156160A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
    • H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Definitions

  • the present invention relates to the technical field of integrated circuits, and more specifically, to a boost chip and a short circuit protection circuit thereof.
  • the popularity of portable electronic products has promoted the rapid development of chips that use lithium-ion batteries as power sources.
  • DCDC chips are used in various scenarios.
  • the boost chip is a kind of DCDC chip, which realizes that the output DC level is higher than the input DC level.
  • OTG (On the Going) circuit is a typical application of boost chips, and the market is extremely large. Because portable electronic products support driving external devices, for example, mobile phones can drive USB electric fans, can light up USB lights, and can also charge another mobile phone. These are all manifestations of OTG applications.
  • Boost chips are also used inside electronic devices, such as providing power to modules such as power amplifiers.
  • the output of the boost chip is prone to short-circuit failure, especially when used as an OTG circuit. Because the output of the boost chip is the USB port that we usually see, there is a high probability that the output terminal will have a short circuit when we are operating.
  • the technical solution of the present invention provides a boost chip and a short-circuit protection circuit thereof, which avoids the problem of burnout of the internal switch tube when the boost chip has a short-circuit fault.
  • a short-circuit protection circuit for a boost chip includes:
  • the first switch tube, the second switch tube and the current source module are connected to
  • the first electrode of the first switch tube is connected to a first node, and the second electrode is grounded.
  • the first node is connected to one end of an inductor, and its gate is used to input a first control signal; the other end of the inductor Used to input power supply voltage;
  • the first electrode of the second switch tube is connected to the first node, and the second electrode is connected to the output terminal of the boost chip;
  • the output terminal When a short-circuit fault occurs at the output terminal of the boost chip, the output terminal is grounded, the first control signal is used to turn off the first switch tube, and the current source module is used to control the second switch
  • the gate potential of the tube gradually transitions from its gate-on potential to the target control potential, so that the current in the second switch tube gradually decreases.
  • the current source module includes: a third switch tube and a preset current source;
  • the grid of the third switch tube is connected to its first electrode, the first electrode is grounded through the preset current source, and the second electrode is used to input the power supply voltage;
  • the gate of the third switch tube and the gate of the second switch tube are turned on, so that the second switch is turned on by the preset current source.
  • the gate potential of the tube transitions from its gate on potential to the target control potential.
  • the gate of the second switching tube and the gate of the third switching tube are connected through a switching element;
  • the switching element has a first switching state and a second switching state.
  • the switching element When no short-circuit fault occurs at the output terminal of the boost chip, the switching element is in the first switching state, and the gate of the second switching tube Used to input a second control signal.
  • the switching element When a short-circuit fault occurs at the output terminal of the boost chip, the switching element is in the second switching state, and the gate of the second switching tube is connected to the third switching tube. The gate is turned on.
  • the third switch tube and the second switch tube are both PMOS tubes, and the second switch tube has a larger gate-to-ground capacitance.
  • the first switch tube is an NMOS tube, and when a short-circuit fault occurs at the output terminal of the boost chip, the first control signal is at a low level to control the first switch tube. A switch tube is turned off.
  • the target control potential is located between the gate-on potential and the gate-off potential of the second switch tube.
  • the substrate of the second switch tube is connected to the first electrode.
  • the substrate of the second switch tube is connected with a switch component, the switch component has a first switch state and a second switch state, and when the boost chip is in a short-circuit state , The switch component is in the first switch state, the substrate of the second switch tube and its first electrode are in conduction, when the boost chip is in the non-short-circuit state, the switch component is in the second switch state, so The substrate of the second switch tube is connected to the first electrode.
  • the present invention also provides a boost chip, characterized in that the boost chip includes: any one of the above-mentioned short-circuit protection circuits.
  • the boost chip includes a detection circuit and a BST loop control circuit, and the detection circuit is used to compare the output voltage at the output terminal of the boost chip with a set reference voltage to output As a result of the comparison, the BST loop control circuit is configured to provide a control signal for the gate of the first switch tube and the gate of the second switch tube of the short circuit protection circuit based on the comparison result.
  • the first switching tube can be turned off by the short-circuit protection circuit, so that the gate potential of the second switching tube gradually transitions from the gate-on potential of the gate to the target control potential.
  • the current in the second switching tube is gradually reduced, and the second electrode of the second switching tube is grounded through the output terminal.
  • the short-circuit current can be released through the loop formed by the second switching tube, thereby avoiding complete disconnection when a short-circuit fault occurs.
  • the voltage overshoot problem of the first node caused by turning on the first switching tube and the second switching tube prevents the inductor current from breaking down the first switching tube. Therefore, the technical solution of the present invention can avoid the short-circuit failure of the boost chip
  • the internal switch tube burned out.
  • Figure 1 is a circuit diagram of a conventional boost chip
  • FIG. 2 is a timing diagram of internal control of the boost chip shown in Figure 1;
  • FIG. 3 is an enlarged view of a partial timing sequence when a short-circuit fault occurs at the output terminal of the boost chip shown in FIG. 1;
  • FIG. 4 is a schematic diagram of the control principle when a short-circuit fault occurs at the output terminal of the boost chip shown in FIG. 1;
  • FIG. 5 is a schematic structural diagram of a short circuit protection circuit of a boost chip provided by an embodiment of the present invention.
  • Figure 6 is the equivalent circuit of the short-circuit protection circuit shown in Figure 5 when a short-circuit fault occurs;
  • Figure 7 is a timing diagram of the short-circuit protection circuit shown in Figure 5 when a short-circuit fault occurs;
  • FIG. 8 is a schematic structural diagram of a boost chip provided by an embodiment of the present invention.
  • FIG. 1 is a circuit diagram of a conventional boost chip.
  • the boost chip at least includes: a first port, a second port, an enable terminal, a ground terminal, and an output terminal.
  • the positive pole of the power source E is connected to the first port through the inductor L, the positive pole of the power source E is directly connected to the second port, and the positive pole of the power source E is connected to the enable terminal through a resistor R.
  • the first port corresponds to the voltage signal SW
  • the second port corresponds to the power supply voltage VIN of the power supply E
  • the enable terminal corresponds to the enable signal EN
  • the ground terminal is grounded to GND
  • the output terminal corresponds to the output voltage VOUT.
  • the chip at least includes: a BST (BOOST) loop control circuit 11, a first switching tube M1, a second switching tube M2, and a detection circuit 12.
  • the detection circuit 12 is used to collect the output voltage VOUT of the output terminal, and compare the output voltage VOUT to a reference voltage.
  • the reference voltage can be set as required, and is generally less than the power supply voltage VIN, for example, it can be 0.9*VIN.
  • the value of the reference voltage can be set according to requirements, and is not limited to 0.9*VIN. Among them, the output terminal is grounded through the capacitor Cout.
  • the 12-channel detection circuit is a comparator with a negative phase input terminal, a positive phase input terminal and a comparison output terminal.
  • the collected output voltage VOUT is input as the feedback signal en_det to the negative phase input terminal, and the reference voltage is input to the positive phase input terminal.
  • the feedback signal en_det is less than 0.9*VIN
  • the signal vout_short is output, and the BST loop control circuit 11 determines that the output terminal of the chip has a short-circuit fault based on the signal vout_short, and then controls both the first switching tube M1 and the second switching tube M2 to be turned off.
  • One switch is controlled by the switch signal sel_vout to disconnect the substrate of the second switch tube M2 from the second electrode, and the other switch is controlled by the switch signal sel_voutb to make the substrate of the second switch tube M2 conductive with the first electrode.
  • Fig. 1 The timing diagram of the boost chip shown in Fig. 1 is shown in Figs. 2 and 3.
  • Fig. 2 is the internal control timing diagram of the boost chip shown in Fig. 1
  • Fig. 3 is a short circuit at the output terminal of the boost chip shown in Fig. 1
  • Fig. 4 is a schematic diagram of the control principle when the output terminal of the boost chip shown in Fig. 1 has a short-circuit fault.
  • the first switching tube M1 is an NMOS tube, and its gate input voltage signal is ngate
  • the second switching tube M2 is a PMOS tube, and its gate input voltage signal is pgate.
  • the substrate of the second switching tube M2 When a short-circuit fault occurs, the substrate of the second switching tube M2 is disconnected from its first electrode, and the substrate of the second switching tube M2 is connected to the first electrode through the switching signal sel_voutb, so that the body diode of the second switching tube M2 points to The first port prevents the inductor current IL corresponding to the first port from continuously increasing to an uncontrollable degree.
  • the inductor current IL can not continue to increase, reducing the probability of damage to the boost chip, but the boost chip may still be damaged This is because after the detection circuit 12 detects that the output port has a short-circuit fault, since the body diode of the second switching tube M2 points to the first port, both the first switching tube M1 and the second switching tube M2 are turned off, making the inductor L momentarily open , The inductor has the characteristic that the current cannot be changed suddenly, and there is no current discharge path, the inductor current IL will impact the first port, which will increase the potential of the first node SW, making the potential of the voltage signal SW of the first port rise very high, which will cause The first switching tube M1 can easily reach the breakdown voltage, and all current flows away from the first switching tube M1, which causes the first switching tube M1 to bear a large amount of power and is easily burned out.
  • the technical solution of the present invention provides a short-circuit protection circuit for the boost chip.
  • the first switching tube M1 is turned off, the second switching tube M2 is turned on, and the gate of the second switching tube M2 is turned off.
  • the potential gradually transitions from the gate-on potential to the target control potential of the preset current source, so that the current flowing through it gradually decreases, so that no matter whether the short-circuit fault occurs during the conduction period of the first switch tube M1 or the second switch During the conduction period of the tube, the overshoot problem of the voltage signal SW of the first port can be avoided, which fundamentally solves the problem that the boost chip burns out when a short-circuit fault occurs at the output terminal.
  • FIG. 5 is a schematic structural diagram of a short-circuit protection circuit of a boost chip provided by an embodiment of the present invention.
  • the short-circuit protection circuit includes: a first switch tube M1, a second switch tube M2, and a current source module 21.
  • the first electrode of the first switch tube M1 is connected to the first node A, and the second electrode thereof is grounded.
  • the first node A is connected to one end of an inductor L, and its gate is used to input the first control signal V1;
  • the other end of the inductor L is used to input the power supply voltage VIN.
  • the first electrode of the second switch tube M2 is connected to the first node A, and the second electrode is connected to the output terminal of the boost chip.
  • the output terminal corresponds to the output voltage VOUT.
  • the first node A corresponds to the voltage signal SW.
  • the output terminal of the boost chip is grounded through a capacitor Cout.
  • the inductor L is connected to the power supply E to input the power supply voltage VIN.
  • Both the first switching tube M1 and the second switching tube M2 are power switching tubes.
  • the second switch tube M2 has a large gate-to-ground capacitance, which can gradually reduce the conduction degree and gradually increase the current limiting effect when the gate turn-on potential gradually transitions to the target control potential, so that current can flow through it Gradually decreases.
  • the gate potential of the second switching tube M2 is a continuous and gradual change process, and the current is continuously and gradually reduced.
  • this solution has a circuit that releases the short-circuit current, so that the inductor current is released according to the set path, so it prevents the inductor current IL from going to undesired places, such as raising the first node SW , Resulting in the breakdown of the first switch tube M1.
  • the output terminal When a short-circuit fault occurs at the output terminal of the boost chip, the output terminal is grounded, the first control signal V1 is used to turn off the first switching tube M1, and the current source module 21 is used to control the
  • the gate potential of the second switch tube M2 gradually transitions from its gate-on potential to the target control potential, so that the current in the second switch tube M2 gradually decreases.
  • Each switch tube is a MOS tube, and the switch state of each switch tube can be controlled by controlling its gate potential.
  • the current source module 21 includes: a third switch tube M3 and a preset current source I0; the gate of the third switch tube M3 is connected to its first electrode, and its first electrode passes through the preset current source I0. It is assumed that the current source I0 is grounded, and its second electrode is used to input the power supply voltage VIN.
  • the gate of the third switching tube M3 and the gate of the second switching tube M2 are turned on, so that the preset current source I0 can
  • the gate potential of the second switch tube M2 transitions from its gate on potential to the target control potential.
  • the gate of the second switching tube M2 and the gate of the third switching tube M3 are connected through a switching element K1; the switching element K1 has a first switching state and a second switching state, and When the output terminal of the boost chip does not have a short-circuit fault, the switching element is in the first switching state, the gate of the second switch tube is used to input a second control signal V2, and the output terminal of the boost chip When a short-circuit fault occurs, the switching element K1 is in the second switching state, and the gate of the second switching tube M2 is connected to the gate of the third switching tube M3.
  • the third switching tube M3 and the second switching tube M2 are both PMOS tubes, and the second switching tube M2 has a larger gate-to-ground capacitance.
  • the first switch tube M1 is an NMOS tube.
  • the first switching tube is an NMOS tube, when a short-circuit fault occurs at the output terminal of the boost chip, the first control signal V1 is at a low level to control the first switching tube M1 to turn off.
  • each switch tube is not limited to the method shown in FIG. 5, and each switch tube can be set as NMOS tube or PMOS tube according to requirements.
  • the first One switch tube M1 is turned off, and the second switch tube M2 gradually transitions from its gate on potential to the target control potential, so that the current flowing through it gradually decreases, which can achieve the purpose of preventing the first switch tube M1 from burning out.
  • the substrate of the second switch tube M2 is connected to the first electrode. It can be arranged that the substrate of the second switch tube M2 is connected with a switch component, the switch component has a first switch state and a second switch state, and when the boost chip is in a short-circuit state, the switch component is in the first state. In the switching state, the substrate of the second switching tube M2 is connected to the first electrode. When the boost chip is in the non-short-circuit state, the switching assembly is in the second switching state, and the second switching tube M2 The substrate is connected to the first electrode.
  • the switch assembly includes a switch element K2 and a switch element K3, the substrate of the second switch tube M2 and its first electrode are connected with a switch element K2, and the substrate and its second electrode are connected with a switch element K2.
  • the switching element K3 when the switch assembly is in the first switching state, the switching element K2 is turned on and the switching element K3 is turned off, and when the switch assembly is in the second switching state, the switching element K2 is turned off and the switching element K3 is turned on.
  • the protection circuit shown in FIG. 6 when a short-circuit fault occurs at the output terminal of the boost chip, the protection circuit shown in FIG.
  • the effective circuit is shown in Figure 6, and the timing diagram when a short-circuit fault occurs is shown in Figure 7.
  • FIG. 6 is an equivalent circuit of the short-circuit protection circuit shown in FIG. 5 when a short-circuit fault occurs
  • FIG. 7 is a timing diagram of the short-circuit protection circuit shown in FIG. 5 when a short-circuit fault occurs.
  • the gate of the first switching tube M1 inputs a low potential, and the first switching tube M1 is turned off, which is equivalent to being connected to its second electrode, and both are grounded; the substrate of the second switching tube M2 is connected to its first electrode , Its gate is connected to the gate of the third switching tube M3, the gate potential of the second switching tube M2 gradually transitions from its gate-on potential to the target control potential, the output terminal of the boost chip is directly grounded, and the power supply E positive in turn
  • the first node A and the second switch tube M2 form a loop with the ground to release current.
  • the location of the output short circuit fault is shown by the dotted line in Figure 7.
  • the output voltage VOUT is less than the reference voltage, which can be 0.9VIN as described above.
  • the detection circuit output signal vout_short continues to be at a high level, indicating that a short-circuit fault occurs, the voltage signal "ngate” continues to be at a low level, the first switch tube M1 is turned off, and the gate voltage signal pgate of the second switch tube M2 is at the gate no matter when the short circuit occurs.
  • the pole-on potential set a low potential, such as 0 potential
  • the gate off potential set a high potential
  • the boost chip is a low-voltage boost chip, and the substrate potential of the second switch tube M2 can be switched.
  • the technical scheme of the present invention only needs to change the turn-off sequence of the switch tube and control the gate potential of the second switch tube M2 through a current source module 21.
  • the circuit is easy to implement, has low cost, and is convenient. Promote use.
  • FIG. 8 is a schematic structural diagram of a boost chip provided by an embodiment of the present invention.
  • the boost chip includes the short circuit protection circuit described in the above embodiment.
  • the boost chip includes a detection circuit 12 and a BST loop control circuit 11.
  • the detection circuit 12 is used to compare the output voltage at the output terminal of the boost chip with a set reference voltage and output the comparison result.
  • the BST loop The control circuit 11 is configured to provide control signals for the gate of the first switching tube M1 and the gate of the second switching tube M2 of the short-circuit protection circuit based on the comparison result.
  • the method shown in FIG. 8 is based on the method shown in FIG. 1 by adding a switching element K1 and a current source module 21 to construct the above-mentioned short-circuit protection circuit inside the chip.
  • the BST loop control circuit 11 provides a first control signal V1 for the gate of the first switching tube M1 and a second control signal V2 for the gate of the second switching tube M2.
  • the BST loop control circuit 11 can be used as a BST voltage generating module to generate a periodically changing voltage signal SW when no short-circuit fault occurs.
  • a short-circuit fault occurs, within the duration of the fault, it continuously controls the first switching tube M1 to turn off through the first control signal V1, and after inputting the gate-on potential for the second switching tube M2, the switching element K2 is switched to the second switch status.
  • the control of the gate potential of the switch tube and the control of the switching state of the switching element can be achieved by controlling the internal control timing of the BST loop control circuit 11.
  • the boost chip in the embodiment of the present invention adopts the short-circuit protection circuit described in the above-mentioned embodiment, and only needs to change the turn-off sequence of the switch tube and control the gate potential of the second switch tube M2 through a current source module 21. It is easy to implement, low cost, and easy to promote and use.

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Abstract

一种升压芯片及其短路保护电路，在升压芯片的输出端发生短路故障时，通过所述短路保护电路可以使得第一开关管（M1）关断，使得第二开关管（M2）的栅极电位由其栅极开启电位逐渐过渡到目标控制电位，以使得所述第二开关管（M2）中的电流逐渐降低，而且第二开关管（M2）的第二电极通过输出端接地，这样，短路电流可以通过第二开关管（M2）形成的回路释放，从而避免发生短路故障时完全断开所述第一开关管（M1）以及所述第二开关管（M2）导致的第一节点（A）电压过冲问题，避免电感（L）电流击穿第一开关管（M1），所述短路保护电路可以在升压芯片发生短路故障时，避免其内部开关管发生烧坏的问题。

Description

升压芯片及其短路保护电路
本申请要求于2019年01月30日提交中国专利局、申请号为201910091785.0、发明创造名称为“升压芯片及其短路保护电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及集成电路技术领域，更具体的说，涉及一种升压芯片及其短路保护电路。
背景技术
便携式电子产品的流行，促进了以锂离子电池作为供电源的芯片的快速发展，其中DCDC类芯片更是被应用在各种场景中。升压芯片是DCDC芯片的一种，实现输出直流电平比输入直流电平高。OTG(On the going)电路是升压类芯片的一种典型应用，而且市场极其广大。因为便携式电子产品都支持驱动外置设备了，比如手机可以驱动USB电风扇，可以点亮USB灯，还可以给另外一个手机进行充电等这些都是OTG应用的体现。升压芯片还应用在电子设备的内部，比如给功放类等模块提供电源等。
升压芯片的输出容易发生短路故障，尤其是作为OTG电路使用时。因为升压芯片的输出就是我们通常见到的USB端口，那么我们在进行操作时，是有很大概率导致其输出端发生短路故障的。
发生短路故障时如何保护芯片不被损坏是一个越来越引起重视的话题，现有技术是芯片内部检测到输出端发生短路故障了，直接关闭芯片内部的开关 管，但是这样会导致芯片内部开关管的烧坏。
发明内容
有鉴于此，本发明技术方案提供了一种升压芯片及其短路保护电路，避免了升压芯片发生短路故障时，内部开关管发生烧坏的问题。
为了实现上述目的，本发明提供如下技术方案：
一种升压芯片的短路保护电路，所述短路保护电路包括：
第一开关管、第二开关管以及电流源模块；
所述第一开关管的第一电极连接第一节点，其第二电极接地，所述第一节点与一电感的一端连接，其栅极用于输入第一控制信号；所述电感的另一端用于输入电源电压；
所述第二开关管的第一电极连接所述第一节点，其第二电极连接所述升压芯片的输出端；
在所述升压芯片的输出端发生短路故障时，所述输出端接地，所述第一控制信号用于所述第一开关管关断，所述电流源模块用于控制所述第二开关管的栅极电位由其栅极开启电位逐渐过渡到目标控制电位，以使得所述第二开关管中的电流逐渐降低。
可选的，在上述短路保护电路中，所述电流源模块包括：第三开关管以及预设电流源；
所述第三开关管的栅极与其第一电极连接，其第一电极通过所述预设电流源接地，其第二电极用于输入所述电源电压；
在所述升压芯片的输出端发生短路故障时，所述第三开关管的栅极与所述第二开关管的栅极导通，以通过所述预设电流源将所述第二开关管的栅极电位由其栅极开启电位过渡到所述目标控制电位。
可选的，在上述短路保护电路中，所述第二开关管的栅极与所述第三开关管的栅极通过一开关元件连接；
所述开关元件具有第一开关状态以及第二开关状态，所述升压芯片的输出端未发生短路故障时，所述开关元件处于所述第一开关状态，所述第二开关管的栅极用于输入第二控制信号，所述升压芯片的输出端发生短路故障时，所述开关元件处于所述第二开关状态，所述第二开关管的栅极与所述第三开关管的栅极导通。
可选的，在上述短路保护电路中，所述第三开关管与所述第二开关管均为PMOS管，且所述第二开关管具有较大的栅极对地电容。
可选的，在上述短路保护电路中，所述第一开关管为NMOS管，在所述升压芯片的输出端发生短路故障时，所述第一控制信号为低电位，以控制所述第一开关管关断。
可选的，在上述短路保护电路中，所述目标控制电位位于所述第二开关管的栅极开启电位与所述栅极截止电位之间。
可选的，在上述短路保护电路中，所述升压芯片的输出端发生短路故障时，所述第二开关管的衬底与其第一电极导通。
可选的，在上述短路保护电路中，所述第二开关管的衬底连接有开关组件，所述开关组件具有第一开关状态和第二开关状态，当所述升压芯片处于短路状态时，所述开关组件处于第一开关状态，所述第二开关管的衬底与其第一电极 导通，当所述升压芯片处于非短路状态时，所述开关组件处于第二开关状态，所述第二开关管的衬底与其第一电极导通。
本发明还提供了一种升压芯片，其特征在于，所述升压芯片包括：上述任一项所述的短路保护电路。
可选的，在上述升压芯片中，所述升压芯片包括检测电路以及BST环路控制电路，所述检测电路用于将所述升压芯片输出端的输出电压与设定参考电压比较，输出比较结果，所述BST环路控制电路用于基于所述比较结果为所述短路保护电路的第一开关管的栅极以及第二开关管的栅极提供控制信号。
通过上述描述可知，本发明技术方案提供的升压芯片及其短路保护电路至少具有如下有益效果：
在升压芯片的输出端发生短路故障时，通过所述短路保护电路可以使得第一开关管关断，使得第二开关管的栅极电位由其栅极开启电位逐渐过渡到目标控制电位，以使得所述第二开关管中的电流逐渐降低，而且第二开关管的第二电极通过输出端接地，这样，短路电流可以通过第二开关管形成的回路释放，从而避免发生短路故障时完全断开所述第一开关管以及所述第二开关管导致的第一节点电压过冲问题，避免电感电流击穿第一开关管，故本发明技术方案可以在升压芯片发生短路故障时，避免其内部开关管发生烧坏的问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创 造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为常规升压芯片的电路图；
图2为图1所示升压芯片的内部控制时序图；
图3为图1所示升压芯片的输出端发生短路故障时的局部时序放大图；
图4为图1所示升压芯片的输出端发生短路故障时的控制原理示意图；
图5为本发明实施例提供的一种升压芯片的短路保护电路的结构示意图；
图6为图5所示短路保护电路在发生短路故障时的等效电路；
图7为图5所示短路保护电路在发生短路故障时的时序图；
图8为本发明实施例提供的一种升压芯片的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
发明人对现有技术的分析如下。
参考图1，图1为常规升压芯片的电路图，该升压芯片至少包括：第一端口、第二端口、使能端、接地端以及输出端。电源E的正极通过电感L连接第一端口，电源E的正极直接与第二端口连接，电源E的正极通过一电阻R与使能端连接。第一端口对应电压信号SW，第二端口对应电源E的电源电压VIN，使能端对应使能信号EN，接地端接地GND，输出端对应输出电压VOUT。
芯片内部至少包括：BST(BOOST，升压)环路控制电路11、第一开关管M1、 第二开关管M2和检测电路12。检测电路12用于采集输出端的输出电压VOUT，将输出电压VOUT与一参考电压。该参考电压可以根据需设定，一般小于电源电压VIN，如可以为0.9*VIN。可以根据需求设定参考电压的值，不限于为0.9*VIN。其中，输出端通过电容Cout接地。
检测电12路为比较器，具有负相输入端、正相输入端以及比较输出端，其采集输出电压VOUT作为反馈信号en_det输入负相输入端，参考电压输入正相输入端。在反馈信号en_det小于0.9*VIN时，输出信号vout_short，BST环路控制电路11基于该信号vout_short确定芯片的输出端发生短路故障，进而控制第一开关管M1和第二开关管M2均关断，并通过开关信号sel_vout控制一个开关使得第二开关管M2的衬底与其第二电极断开，通过开关信号sel_voutb控制另一个开关使得第二开关管M2的衬底与其第一电极导通。
图1所示升压芯片的时序图如图2和图3所示，图2为图1所示升压芯片的内部控制时序图，图3为图1所示升压芯片的输出端发生短路故障时的局部时序放大图。发生短路故障时，等效电路图如图4所示，图4为图1所示升压芯片的输出端发生短路故障时的控制原理示意图。
第一开关管M1为NMOS管，其栅极输入电压信号为ngate，第二开关管M2为PMOS管，其栅极输入电压信号为pgate。
由图2-图4可知，发生短路故障时，如图3中虚线位置所示时刻发生短路故障，输出电压VOUT小于参考电压(如参考电压为0.9*VIN)，信号vout_short持续为高电位，表明出现短路故障，开关信号sel_vout持续为低电位，以使得第二开关管M2的衬底与其第一电极断开，电压信号ngate持续为低电位，电压信号pgate持续为高电位，以使得第一开关管M1和第二开关管M2均关断。
发生短路故障时，第二开关管M2的衬底与其第一电极断开，通过开关信号sel_voutb使得第二开关管M2的衬底与其第一电极导通，使得第二开关管M2的体二极管指向第一端口，防止第一端口对应电感电流IL持续增大到不可控制的程度。
虽然，发生短路故障时，通过同时关断第一开关管M1和第二开关管M2，可以使得电感电流IL不会持续增大，减少了升压芯片损坏的概率，但是升压芯片还是可能损坏，这是由于检测电路12检测到输出端口发生短路故障后，由于第二开关管M2的体二极管指向第一端口，第一开关管M1和第二开关管M2均关断，使得电感L瞬间断路，电感具有电流不能突变的特性，没有电流泄放通路，电感电流IL会冲击第一端口，会将第一节点SW电位冲高，使得第一端口的电压信号SW的电位抬升很高，会使得第一开关管M1很容易到达击穿电压，所有电流从第一开关管M1流走，导致第一开关管M1承受很大的功率，容易被烧坏。
通过上述描述可知，当发生短路故障时，如果完全切断电流的回路，将导致开关管烧坏。
基于此，本发明技术方案提供了一种升压芯片的短路保护电路，当发生短路故障时，第一开关管M1关断，第二开关管M2开启，并将第二开关管M2的栅极电位逐步从其栅极开启电位过渡到预设电流源的目标控制电位，使得其流过的电流逐渐降低，这样，无论短路故障发生在第一开关管M1的导通期间还是发生在第二开关管的导通期间，都可以避免第一端口的电压信号SW发生过冲问题，从根本上解决了输出端发生短路故障时导致升压芯片烧坏的问题。
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本发明作进一步详细的说明。
参考图5，图5为本发明实施例提供的一种升压芯片的短路保护电路的结构示意图，所述短路保护电路包括：第一开关管M1、第二开关管M2以及电流源模块21。所述第一开关管M1的第一电极连接第一节点A，其第二电极接地，所述第一节点A与一电感L的一端连接，其栅极用于输入第一控制信号V1；所述电感L的另一端用于输入电源电压VIN。所述第二开关管M2的第一电极连接所述第一节点A，其第二电极连接所述升压芯片的输出端。输出端对应输出电压VOUT。第一节点A对应电压信号SW。
其中，所述升压芯片的输出端通过一电容Cout接地。如图5所示，电感L与电源E连接，以输入电源电压VIN。第一开关管M1和第二开关管M2均为功率开关管。第二开关管M2具有较大的栅极对地电容，可以在由栅极开启电位逐步过渡到目标控制电位时，导通程度逐渐降低，限流作用逐渐增大，故可以使得其流过电流逐渐降低。发生短路故障时，第二开关管M2的栅极电位是连续的逐渐变换过程，电流是连续的逐渐减小，短路故障时相当于与芯片的输出端接地，故可以实现释放短路电流的目的。而且相对于直接关断所有开关管，本方案具有释放短路电流的回路，使得电感电流按照设定的通路释放，故避免了电感电流IL走到不希望走的地方，如冲高第一节点SW，导致第一开关管M1击穿。
在所述升压芯片的输出端发生短路故障时，所述输出端接地，所述第一控制信号V1用于所述第一开关管M1关断，所述电流源模块21用于控制所述第二开关管M2的栅极电位由其栅极开启电位逐渐过渡到目标控制电位，以使得所述第二开关管M2中的电流逐渐降低。各个开关管均为MOS管，可以通过 控制其栅极电位实现各个开关管开关状态的控制。
如图5所示，所述电流源模块21包括：第三开关管M3以及预设电流源I0；所述第三开关管M3的栅极与其第一电极连接，其第一电极通过所述预设电流源I0接地，其第二电极用于输入所述电源电压VIN。
在所述升压芯片的输出端发生短路故障时，所述第三开关管M3的栅极与所述第二开关管M2的栅极导通，以通过所述预设电流源I0将所述第二开关管M2的栅极电位由其栅极开启电位过渡到所述目标控制电位。
可选的，所述第二开关管M2的栅极与所述第三开关管M3的栅极通过一开关元件K1连接；所述开关元件K1具有第一开关状态以及第二开关状态，所述升压芯片的输出端未发生短路故障时，所述开关元件处于所述第一开关状态，所述第二开关管的栅极用于输入第二控制信号V2，所述升压芯片的输出端发生短路故障时，所述开关元件K1处于所述第二开关状态，所述第二开关管M2的栅极与所述第三开关管M3的栅极导通。
图5所示实施例中，所述第三开关管M3与所述第二开关管M2均为PMOS管，且所述第二开关管M2具有较大的栅极对地电容。所述第一开关管M1为NMOS管。当所述第一开关管为NMOS管时，在所述升压芯片的输出端发生短路故障时，所述第一控制信号V1为低电位，以控制所述第一开关管M1关断。
本发明实施例中，各个开关管的类型不局限于图5所示方式，可以根据需求设定各个开关管为NMOS管或是PMOS管，通过对应的栅极电压信号控制发生短路故障时，第一开关管M1断开，第二开关管M2由其栅极开启电位逐渐过渡到目标控制电位，以使得其流过电流逐渐降低，即可以实现防止第一开 关管M1烧坏的目的。
可选的，所述升压芯片的输出端发生短路故障时，所述第二开关管M2的衬底与其第一电极导通。可以设置所述第二开关管M2的衬底连接有开关组件，所述开关组件具有第一开关状态和第二开关状态，当所述升压芯片处于短路状态时，所述开关组件处于第一开关状态，所述第二开关管M2的衬底与其第一电极导通，当所述升压芯片处于非短路状态时，所述开关组件处于第二开关状态，所述第二开关管M2的衬底与其第一电极导通。例如，可以设置所述开关组件包括开关元件K2和开关元件K3，所述第二开关管M2的衬底与其第一电极之间连接有开关元件K2，其衬底与其第二电极之间连接有开关元件K3，开关组件处于第一开关状态时，开关元件K2导通，开关元件K3断开，开关组件处于第二开关状态时，开关元件K2断开，开关元件K3导通。
以第一开关管为NMOS管，第二开关管M2和第三开关管M3均为PMOS管为例，当所述升压芯片发生的输出端发生短路故障时，图5所示保护电路的等效电路如图6所示，其发生短路故障时的时序图如图7所示。
参考图6和图7，图6为图5所示短路保护电路在发生短路故障时的等效电路，图7为图5所示短路保护电路在发生短路故障时的时序图。发生短路故障时：第一开关管M1的栅极输入低电位，第一开关管M1关断，相当于与其第二电极连接，二者接地；第二开关管M2的衬底与其第一电极连接，其栅极与第三开关管M3的栅极连接，第二开关管M2的栅极电位由其栅极开启电位逐步过渡到目标控制电位，升压芯片的输出端直接接地，电源E正极依次通过第一节点A、第二开关管M2，与地形成回路，释放电流。
输出端发生短路故障的位置如图7中虚线所示，输出电压VOUT小于参 考电压，如上述可以为0.9VIN。检测电路输出信号vout_short持续为高电位，表明出现短路故障，电压信号ngate持续为低电位，第一开关管M1关断，第二开关管M2的栅极电压信号pgate无论在发生短路时刻是处于栅极开启电位(设定低电位，如可以为0电位)还是处于栅极关断电位(设定高电位)，均转换为0电位，并在电流源模块21控制下由0电位逐渐上升到目标控制电位。所述目标控制电位位于所述第二开关管M2的栅极开启电位与所述栅极截止电位之间，在该过渡变化过程中，第二开关管处于导通状态，且导通程度逐渐降低，流过电流逐渐减小。
可选的，本发明实施例中，所述升压芯片为低压升压芯片，第二开关管M2的衬底电位可以切换。相比于传统短路保护方案，本发明技术方案只需要改变开关管的关闭时序，并通过一电流源模块21控制第二开关管M2的栅极电位就可以实现，电路易于实现，成本低，便于推广使用。
基于上述实施例，本发明另一实施例还提供了一种升压芯片，该升压芯片如图8所示，图8为本发明实施例提供的一种升压芯片的结构示意图，所示升压芯片包括上述实施例所述短路保护电路。所述升压芯片包括检测电路12以及BST环路控制电路11，所述检测电路12用于将所述升压芯片输出端的输出电压与设定参考电压比较，输出比较结果，所述BST环路控制电路11用于基于所述比较结果为所述短路保护电路的第一开关管M1的栅极以及第二开关管M2的栅极提供控制信号。
图8所示方式在图1所示方式基础上，增加开关元件K1以及电流源模块21，以在芯片内部构建上述短路保护电路。通过BST环路控制电路11为第一 开关管M1的栅极提供第一控制信号V1，为第二开关管M2的栅极提供第二控制信号V2。
BST环路控制电路11可以作为一BST电压产生模块，在未发生短路故障时，用于以产生周期性变化的电压信号SW。发生短路故障时，在故障持续时间内，其通过第一控制信号V1持续控制第一开关管M1关断，为第二开关管M2输入栅极开启电位后，将开关元件K2切换到第二开关状态。可以通过控制BST环路控制电路11内部控制时序实现其对开关管栅极电位的控制以及开关元件的开关状态的控制。
本发明实施例所述升压芯片采用上述实施例所述短路保护电路，只需要改变开关管的关闭时序，并通过一电流源模块21控制第二开关管M2的栅极电位就可以实现，电路易于实现，成本低，便于推广使用。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的升压芯片而言，由于其与实施例公开的短路保护电路相对应，所以描述的比较简单，相关之处参见短路保护电路对应部分说明即可。
还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种物品或者设备所固有的要素。在没有更多限制的情况下，由 语句“包括一个……”限定的要素，并不排除在包括上述要素的物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种升压芯片的短路保护电路，其特征在于，所述短路保护电路包括：
    第一开关管、第二开关管以及电流源模块；
    所述第一开关管的第一电极连接第一节点，其第二电极接地，所述第一节点与一电感的一端连接，所述第一开关管的栅极用于输入第一控制信号；所述电感的另一端用于输入电源电压；
    所述第二开关管的第一电极连接所述第一节点，其第二电极连接所述升压芯片的输出端；
    在所述升压芯片的输出端发生短路故障时，所述输出端接地，所述第一控制信号用于控制所述第一开关管关断，所述电流源模块用于控制所述第二开关管的栅极电位由所述第二开关管的栅极开启电位逐渐过渡到目标控制电位，以使得所述第二开关管中的电流逐渐降低。
  2. 根据权利要求1所述的短路保护电路，其特征在于，所述电流源模块包括：第三开关管以及预设电流源；
    所述第三开关管的栅极与其第一电极连接，其第一电极通过所述预设电流源接地，其第二电极用于输入所述电源电压；
    在所述升压芯片的输出端发生短路故障时，所述第三开关管的栅极与所述第二开关管的栅极导通，以通过所述预设电流源将所述第二开关管的栅极电位由所述第二开关管的栅极开启电位过渡到所述目标控制电位。
  3. 根据权利要求2所述的短路保护电路，其特征在于，所述第二开关管的栅极与所述第三开关管的栅极通过一开关元件连接；
    所述开关元件具有第一开关状态以及第二开关状态，所述升压芯片的输出端未发生短路故障时，所述开关元件处于所述第一开关状态，所述第二开关管的栅极用于输入第二控制信号，所述升压芯片的输出端发生短路故障时，所述开关元件处于所述第二开关状态，所述第二开关管的栅极与所述第三开关管的栅极导通。
  4. 根据权利要求2所述的短路保护电路，其特征在于，所述第三开关管与所述第二开关管均为PMOS管，且所述第二开关管具有较大的栅极对地电容。
  5. 根据权利要求1所述的短路保护电路，其特征在于，所述第一开关管为NMOS管，在所述升压芯片的输出端发生短路故障时，所述第一控制信号为低电位，以控制所述第一开关管关断。
  6. 根据权利要求1所述的短路保护电路，其特征在于，所述目标控制电位位于所述第二开关管的栅极开启电位与所述栅极截止电位之间。
  7. 根据权利要求1所述的短路保护电路，其特征在于，所述升压芯片的输出端发生短路故障时，所述第二开关管的衬底与其第一电极导通。
  8. 根据权利要求7所述的短路保护电路，其特征在于，所述第二开关管的衬底连接有开关组件，所述开关组件具有第一开关状态和第二开关状态，当所述升压芯片处于短路状态时，所述开关组件处于第一开关状态，所述第二开关管的衬底与其第一电极导通，当所述升压芯片处于非短路状态时，所述开关组件处于第二开关状态，所述第二开关管的衬底与其第一电极导通。
  9. 一种升压芯片，其特征在于，所述升压芯片包括：如权利要求1-8任一项所述的短路保护电路。
  10. 根据权利要求9所述的升压芯片，其特征在于，所述升压芯片包括检测电路以及BST环路控制电路，所述检测电路用于将所述升压芯片输出端的输出电压与设定参考电压比较，输出比较结果，所述BST环路控制电路用于基于所述比较结果为所述短路保护电路的第一开关管的栅极以及第二开关管的栅极提供控制信号。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109756116B (zh) * 2019-01-30 2024-03-01 上海艾为电子技术股份有限公司 升压芯片及其短路保护电路
CN114039481A (zh) * 2021-10-14 2022-02-11 嘉兴禾润电子科技有限公司 集成输出电压保护dcdc芯片的d类功放器及其保护方法
CN115021215B (zh) * 2022-08-05 2022-11-15 禹创半导体(深圳)有限公司 一种降低电源电路输入电压过冲现象的方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100123978A1 (en) * 2008-11-20 2010-05-20 Shui-Mu Lin Short circuit and open circuit protection for a boost converter
CN103001475A (zh) * 2012-11-19 2013-03-27 西安三馀半导体有限公司 应用于同步升压型dc-dc转换器的短路保护电路
CN103607009A (zh) * 2013-11-22 2014-02-26 钰泰科技（上海）有限公司 一种带自动保护功能的充放电电路
US20150200536A1 (en) * 2014-01-10 2015-07-16 Chengdu Monolithic Power Systems Co., Ltd. Boost converter with short-circuit protection and method thereof
CN108847654A (zh) * 2018-06-26 2018-11-20 南京微盟电子有限公司 一种pfm同步升压dc-dc转换器的关断和保护电路
CN109756116A (zh) * 2019-01-30 2019-05-14 上海艾为电子技术股份有限公司 升压芯片及其短路保护电路
CN209233727U (zh) * 2019-01-30 2019-08-09 上海艾为电子技术股份有限公司 升压芯片及其短路保护电路

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5485341A (en) * 1992-09-21 1996-01-16 Kabushiki Kaisha Toshiba Power transistor overcurrent protection circuit
JP2000323974A (ja) * 1999-05-12 2000-11-24 Fuji Electric Co Ltd 半導体素子の短絡保護回路
JP3911175B2 (ja) * 2002-03-13 2007-05-09 三菱電機株式会社 電圧変動補償装置
JP2004222367A (ja) * 2003-01-10 2004-08-05 Toshiba Corp ゲート駆動装置及び電力変換装置
JP2009213305A (ja) * 2008-03-05 2009-09-17 Denso Corp 電力変換装置
US8513986B2 (en) * 2009-10-26 2013-08-20 Nissan Motor Co., Ltd. Driving circuit for switching element and power converter
KR101835662B1 (ko) * 2012-01-17 2018-03-08 인피니언 테크놀로지스 오스트리아 아게 전력 컨버터 회로, 전력 공급 시스템 및 방법
JP2014127728A (ja) * 2012-12-25 2014-07-07 Nissan Motor Co Ltd 短絡故障保護装置及び短絡故障保護方法
DE102014214490A1 (de) * 2014-07-24 2016-01-28 Robert Bosch Gmbh Schaltwandler und Verfahren zum Wandeln einer Eingangsspannung in eine Ausgangsspannung
CN106549568B (zh) * 2016-12-09 2019-07-09 芯洲科技（北京）有限公司 一种开关器件驱动电路、方法及自举电路
CN206249131U (zh) * 2016-12-13 2017-06-13 深圳Tcl数字技术有限公司 电源保护电路及电源装置
CN206517295U (zh) * 2016-12-20 2017-09-22 杰华特微电子（张家港）有限公司 一种开关电路

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100123978A1 (en) * 2008-11-20 2010-05-20 Shui-Mu Lin Short circuit and open circuit protection for a boost converter
CN103001475A (zh) * 2012-11-19 2013-03-27 西安三馀半导体有限公司 应用于同步升压型dc-dc转换器的短路保护电路
CN103607009A (zh) * 2013-11-22 2014-02-26 钰泰科技（上海）有限公司 一种带自动保护功能的充放电电路
US20150200536A1 (en) * 2014-01-10 2015-07-16 Chengdu Monolithic Power Systems Co., Ltd. Boost converter with short-circuit protection and method thereof
CN108847654A (zh) * 2018-06-26 2018-11-20 南京微盟电子有限公司 一种pfm同步升压dc-dc转换器的关断和保护电路
CN109756116A (zh) * 2019-01-30 2019-05-14 上海艾为电子技术股份有限公司 升压芯片及其短路保护电路
CN209233727U (zh) * 2019-01-30 2019-08-09 上海艾为电子技术股份有限公司 升压芯片及其短路保护电路

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