WO2020155469A1 - 显示面板及其制作方法 - Google Patents

显示面板及其制作方法 Download PDF

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Publication number
WO2020155469A1
WO2020155469A1 PCT/CN2019/087337 CN2019087337W WO2020155469A1 WO 2020155469 A1 WO2020155469 A1 WO 2020155469A1 CN 2019087337 W CN2019087337 W CN 2019087337W WO 2020155469 A1 WO2020155469 A1 WO 2020155469A1
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WO
WIPO (PCT)
Prior art keywords
layer
leads
display panel
data lines
transparent conductive
Prior art date
Application number
PCT/CN2019/087337
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English (en)
French (fr)
Inventor
陈泽升
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/640,068 priority Critical patent/US11079641B2/en
Publication of WO2020155469A1 publication Critical patent/WO2020155469A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Definitions

  • the present invention relates to the field of display technology, in particular to a display panel and a manufacturing method thereof.
  • the purpose of the present invention is to provide a display panel, which can not only further reduce the width of the lateral frame, but also be compatible with the current manufacturing process, thereby reducing the subsequent reconstruction cost or production cost.
  • the present invention also provides a display panel including:
  • a light-transmitting substrate with a semiconductor film structure on the light-transmitting substrate the semiconductor film structure forming an array substrate row drive area (GOA), an active display area (AA) and an integrated circuit area (IC) ,
  • the array substrate row drive area is opposite to the integrated circuit area, and the active display area is located between the array substrate row drive area and the integrated circuit area
  • the semiconductor film layer structure includes: a first A metal layer, an interlayer insulating layer, a second metal layer, and a planarization layer, the interlayer insulating layer is disposed between the first metal layer and the second metal layer, the planarization layer Disposed on the second metal layer, and the planarization layer has a plurality of conductive holes;
  • a plurality of scan lines are arranged on the active display area on the transparent substrate, and the plurality of scan lines are perpendicular to the plurality of data lines, wherein the plurality of scan lines are the first metal
  • the layer is formed by a patterning process
  • a lower transparent conductive layer is disposed on the planarization layer, the lower transparent conductive layer is patterned to form a plurality of leads, and the plurality of leads are electrically connected to the corresponding ones through the plurality of conductive holes Scan lines, and the directions of the plurality of leads are parallel to the plurality of data lines.
  • At least one of the plurality of leads is arranged between two adjacent data lines.
  • the display panel further includes an insulating layer and an upper transparent conductive layer, the insulating layer is disposed on the plurality of leads, the upper transparent conductive layer is disposed on the insulating layer and The multiple data lines are electrically connected.
  • the lower transparent conductive layer and the upper transparent conductive layer are made of a transparent conductive material.
  • one of the plurality of leads does not overlap with one of the plurality of data lines.
  • the present invention also provides a manufacturing method of a display panel, including:
  • the semiconductor film layer structure being a light shielding layer, a buffer layer, a semiconductor layer and a gate insulating layer in sequence;
  • planarization layer Forming a planarization layer on the second metal layer and the interlayer insulating layer, and the planarization layer has a plurality of conductive holes;
  • a lower transparent conductive layer is formed on the planarization layer, the lower transparent conductive layer is patterned to form the plurality of leads, wherein the leads are electrically connected to the corresponding scan lines through the conductive holes, and The lead does not coincide with the data line;
  • An upper transparent conductive layer is formed on the insulating layer, and the upper transparent conductive layer is electrically connected to the corresponding data line through the conductive hole.
  • the lead is arranged between two adjacent data lines.
  • the planarization layer is patterned to form a first conductive hole and a second conductive hole, wherein the first conductive hole is electrically connected to the lead and the corresponding scan line , The second conductive hole electrically connects the upper transparent conductive layer and the corresponding data line.
  • an array substrate row driving area, an active display area, and an integrated circuit area are formed on the semiconductor film structure, the array substrate row driving area is opposite to the integrated circuit area, and the The active display area is located between the row driving area of the array substrate and the integrated circuit area.
  • the plurality of scan lines and the row driving area of the array substrate are electrically connected through the plurality of leads.
  • the present invention also provides a display panel, which includes:
  • the row driving area of the array substrate is opposite to the integrated circuit area, and the active display area is located between the row driving area of the array substrate and the integrated circuit area;
  • a plurality of data lines arranged on the active display area on the transparent substrate;
  • a plurality of scan lines are arranged on the active display area on the transparent substrate, and the plurality of scan lines are perpendicular to the plurality of data lines;
  • a plurality of leads are electrically connected to the corresponding scanning lines and the row driving area of the array substrate, and the plurality of leads are parallel to the plurality of data lines.
  • At least one of the plurality of leads is arranged between two adjacent data lines.
  • the display panel further includes an insulating layer and an upper transparent conductive layer, the insulating layer is disposed on the plurality of leads, the upper transparent conductive layer is disposed on the insulating layer and The data line is electrically connected.
  • the plurality of leads and the transparent conductive layer are made of a transparent conductive material.
  • one of the plurality of leads does not overlap with one of the plurality of data lines.
  • the present invention also provides a display panel, which includes:
  • a plurality of data lines arranged on the active display area on the transparent substrate;
  • a plurality of scan lines are arranged on the active display area on the transparent substrate, and the plurality of scan lines are perpendicular to the plurality of data lines;
  • a plurality of leads are electrically connected to the corresponding plurality of scan lines, and the plurality of leads are parallel to the plurality of data lines.
  • the semiconductor film layer structure includes: a first metal layer, an interlayer insulating layer, a second metal layer, and a planarization layer, and the interlayer insulating layer is disposed on the first Between the metal layer and the second metal layer, the planarization layer is disposed on the second metal layer, and the planarization layer has a plurality of conductive holes.
  • the multiple scan lines are formed by the first metal layer through a patterning process
  • the multiple data lines are formed by the second metal layer through a patterning process
  • the multiple Each lead is electrically connected to the corresponding plurality of scan lines through the plurality of conductive holes.
  • the plurality of leads are made of a transparent conductive material.
  • At least one of the plurality of leads is disposed between two adjacent data lines, and one of the plurality of leads does not overlap with one of the plurality of data lines.
  • the beneficial effect of the present invention is that the patterned transparent conductive material is used as the lead to transmit the signal of the scanning line, and the transparent conductive lead does not need to be additionally wound to the frame, thereby realizing the reduction of the lateral frame of the display panel. Moreover, it is highly compatible with the current manufacturing process and does not require additional photomasks and related photolithography process steps, which can reduce subsequent transformation costs or production costs. In addition, the lead wire does not overlap with the data line can effectively reduce the parasitic capacitance.
  • FIG. 1 is a schematic diagram of the configuration of a display panel according to an embodiment of the invention.
  • Fig. 2 is a partial enlarged view of the embodiment of Fig. 1.
  • Fig. 3 is a cross-sectional view of the line A-A of the embodiment in Fig. 2.
  • FIG. 4 is a flowchart of a manufacturing method of a display panel according to an embodiment of the invention.
  • FIG. 1 is a schematic diagram of a display panel configuration according to an embodiment of the present invention.
  • Fig. 2 is a partial enlarged view of the embodiment of Fig. 1.
  • Fig. 3 is a cross-sectional view of the line A-A of the embodiment in Fig. 2.
  • This embodiment provides a display panel 100.
  • the display panel 100 includes a light-transmitting substrate 110, a plurality of scan lines 161, 162, 163, a plurality of data lines 181, 182, 183, and a plurality of leads 201, 202 , 203.
  • the light-transmitting substrate 110 has a semiconductor film structure formed on the array substrate row drive area (GOA) 10, an active display area (AA) 20, and an integrated circuit area (IC) 30,
  • the array substrate row driving area 10 is opposite to the integrated circuit area 30, and the active display area 20 is located between the array substrate row driving area 10 and the integrated circuit area 30.
  • the row driving area 10 of the array substrate and the integrated circuit area 30 are opposite to each other up and down via the active display area 20.
  • the transparent substrate 110 may be a glass substrate or a substrate made of other transparent materials.
  • the plurality of data lines 181, 182, and 183 are disposed on the active display area 20 on the transparent substrate 110.
  • the multiple scan lines 161, 162, 163 are disposed on the active display area 20 on the light-transmissive substrate 110, and the multiple scan lines 161, 162, 163 are perpendicular to the multiple data lines 181 , 182, 183.
  • the plurality of leads 201, 202, 203 are electrically connected to the corresponding plurality of scan lines 161, 162, 163 and the array substrate row driving area 10, and the plurality of leads 201, 202, 203 are parallel to all
  • the multiple data lines 181, 182, and 183 are described. As shown in FIG.
  • the leads 201, 202, and 203 are respectively arranged between two adjacent data lines 181, 182, and 183. According to the direction of the embodiment in FIG. 1, the multiple scan lines 161, 162, and 163 can be guided by multiple leads 201, 202, and 203 (parallel to the multiple data lines 181, 182, and 183).
  • the array substrate row driving area 10 opposite to the integrated circuit area 30, that is, the array substrate row driving area 10 and the integrated circuit area 30 can be arranged above and below the active display area 20, which greatly reduces The width of the lateral frame (left and right frame) of the display panel 100.
  • the semiconductor film layer structure on the light-transmitting substrate 110 includes in sequence: a light shielding layer 120, a buffer layer 130, a semiconductor layer 140, a gate insulating layer 150, and a first metal layer 160, an interlayer insulating layer 170, a second metal layer 180, a planarization layer 190, a lower transparent conductive layer 200, an insulating layer 210, and an upper transparent conductive layer 220.
  • the light-shielding layer 120 is disposed on the light-transmitting substrate 110, and the light-shielding layer 120 may be made of a metal material, such as Mo, Al, Cu, Ti or alloys thereof.
  • the buffer layer 130 may be disposed on the transparent substrate 110 and the light shielding layer 120 by a deposition technique.
  • the buffer layer 130 may be a SiOx, SiNx single-layer film or a laminated structure film.
  • the semiconductor layer 140 may be formed on the buffer layer 130 by a deposition technique.
  • the semiconductor layer 140 can define an active area through a patterning process.
  • the material of the semiconductor layer 140 may be polysilicon or other suitable materials.
  • the gate insulating layer 150 is disposed on the semiconductor layer 140 by a deposition technique.
  • the gate insulating layer 150 may be a SiOx, SiNx film or a laminated structure film.
  • the first metal layer 160 is disposed on the gate insulating layer 150, and the first metal layer 160 is patterned to form the scan lines 161, 162, and 163.
  • the material of the first metal layer 160 may include Mo, Al, Cu or alloys thereof.
  • the interlayer insulating layer 170 is disposed on the first metal layer 160, and the interlayer insulating layer 170 may be a SiOx, SiNx film or a laminated structure film.
  • the second metal layer 180 is disposed on the interlayer insulating layer 170, and the second metal layer 180 is patterned to form the plurality of data lines 181, 182, and 183.
  • the material of the second metal layer 180 may include Mo, Al, Cu or alloys thereof.
  • the planarization layer 190 is disposed on the second metal layer 180 and the interlayer insulating layer 170.
  • the planarization layer 190 has a plurality of conductive holes 192 and 194.
  • the lower transparent conductive layer 200 is disposed on the planarization layer 190, and the lower transparent conductive layer 200 is patterned to form the plurality of leads 201, 202, 203.
  • the lead 202 is electrically connected to the corresponding scan line 162 through the conductive hole 192, thereby guiding the scan line 162 to the array substrate row above the active display area 20 Drive area 10 (shown in Figure 1).
  • the lead 202 does not overlap with the data line 182.
  • the lower transparent conductive layer 200 is made of a transparent conductive material, such as indium tin oxide (ITO) or other transparent conductive materials with similar characteristics.
  • ITO indium tin oxide
  • using the transparent conductive material as the plurality of leads 201, 202, 203 does not require additional deposition steps, and can also maintain a higher aperture ratio.
  • the insulating layer 210 is disposed on the plurality of leads 201, 202, 203 of the lower transparent conductive layer 200, and the upper transparent conductive layer 220 is disposed on the insulating layer 210 and is electrically connected to the data line 181, 182, 183. As shown in FIG. 3, the upper transparent conductive layer 220 is electrically connected to one of the plurality of data lines through the conductive hole 194.
  • the insulating layer 210 may also include a passivation layer.
  • the upper transparent conductive layer 220 is made of a transparent conductive material, such as indium tin oxide (ITO) or other transparent conductive materials with similar characteristics.
  • ITO indium tin oxide
  • the semiconductor film structure described herein can be formed through a patterning process, such as photolithography technology combined with etching technology, or similar technology that can be applied in the semiconductor industry.
  • the semiconductor film structure can be formed by vapor deposition, evaporation, sputtering and other techniques.
  • the plurality of leads 201, 202, and 203 formed by the patterned lower transparent conductive layer 200 are used as the plurality of scan lines 161, 162, and 163 to be connected to the The wiring of the row driving area 10 of the array substrate; plus the plurality of leads 201, 202, 203 and the plurality of data lines 181, 182, 183 parallel, thereby connecting the row driving area 10 of the array substrate to the
  • the integrated circuit area 30 is disposed above and below the active display area 20. In this way, the width of the lateral frames (left and right frames) of the display panel 100 can be greatly reduced, and a display panel with a very narrow frame can be realized.
  • FIG. 4 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present invention.
  • the manufacturing method of the display panel of this embodiment includes:
  • a substrate is provided, and a semiconductor film structure is formed on the substrate.
  • the semiconductor film structure includes a light shielding layer, a buffer layer, a semiconductor layer, and a gate insulating layer in sequence.
  • an array substrate row driving area, an active display area, and an integrated circuit area are formed in the semiconductor film layer structure, the array substrate row driving area is opposite to the integrated circuit area, and the active display area is located at all Between the array substrate row driving area and the integrated circuit area.
  • step S120 a first metal layer is formed on the gate insulating layer, and the first metal layer is patterned to form a plurality of scan lines.
  • Step S130 forming an interlayer insulating layer on the first metal layer.
  • step S140 a second metal layer is formed on the interlayer insulating layer, and the second metal layer is patterned to form a plurality of data lines.
  • Step S150 forming a planarization layer on the second metal layer and the interlayer insulating layer, and the planarization layer has a plurality of conductive holes.
  • the planarization layer is patterned to form a first conductive hole and a second conductive hole, wherein the first conductive hole is electrically connected to the lead and the corresponding scan line, and the second conductive hole The hole electrically connects the upper transparent conductive layer and the corresponding data line.
  • a lower transparent conductive layer is formed on the planarization layer, and the lower transparent conductive layer is patterned to form the plurality of leads, wherein the leads are electrically connected to the corresponding scanning through the conductive holes Line, and the lead does not coincide with the data line.
  • the lead can be arranged between two adjacent data lines.
  • the plurality of scan lines and the row driving area of the array substrate are electrically connected through the plurality of leads.
  • Step S170 forming an insulating layer on the lower transparent conductive layer.
  • Step S180 forming an upper transparent conductive layer on the insulating layer, and the upper transparent conductive layer is electrically connected to the corresponding data line through the conductive hole.
  • the beneficial effect of the present invention is that the patterned transparent conductive material is used as the lead to transmit the signal of the scanning line, and the transparent conductive lead does not need to be additionally wound to the frame, thereby realizing the reduction of the lateral frame of the display panel. Moreover, it is highly compatible with the current manufacturing process and does not require additional photomasks and related photolithography process steps, which can reduce subsequent transformation costs or production costs. In addition, the lead wire does not overlap with the data line can effectively reduce the parasitic capacitance.

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Abstract

一种显示面板，包括：一透光基板（110），透光基板（110）上具有一半导体膜层结构，半导体膜层结构形成一主动显示区（20）；多个数据线（181、182、183），设置于透光基板（110）上的主动显示区（20）上；多个扫描线（161、162、163），设置于透光基板（110）上的主动显示区（20）上，并且多个扫描线（161、162、163）垂直于多个数据线（181、182、183）；及多个引线（201、202、203），电性连接对应的多个扫描线（161、162、163），并且多个引线（201、202、203）平行于多个数据线（181、182、183）。

Description

显示面板及其制作方法 技术领域
本发明涉及显示技术领域，特别是涉及一种显示面板及其制作方法。
 背景技术
随着液晶面板技术的不断更新，小尺寸面板，特别是4-7寸的手机面板，正逐渐朝着超窄边框乃至无边框化发展
 技术问题
随着液晶面板技术的不断更新，小尺寸面板，特别是4-7寸的手机面板，正逐渐朝着超窄边框乃至无边框化发展，传统显示面板技术通过压缩阵列基板行驱动(Gate Driver On Array, GOA)电路尺寸、缩小应用触控与显示驱动集成芯片(Touch and Display Driver Integration，TDDI)的IC芯片以及缩小走线间的距离等方式来达成缩小边框，目前边框的宽度已经接近了0.7mm至0.8mm，然而为了保证GOA有效工作、面板的信赖性测试及各种信号线之间相互隔断，边框(特别是侧向边框)的压缩已经接近了极限。
故，有必要提供一种窄边框显示面板，以解决现有技术所存在的问题。
 技术解决方案
本发明的目的在于提供一种显示面板，不但可以进一步的缩小侧向边框的宽度，还可以与现行制程工艺相容，进而降低后续沿生的改造成本或生产成本。
为达成本发明的前述目的，本发明还提供一种显示面板，所述显示面板包括：
一透光基板，所述透光基板上具有一半导体膜层结构，所述半导体膜层结构形成一阵列基板行驱动区(GOA)、一主动显示区(AA)及一集成电路区(IC)，所述阵列基板行驱动区与所述集成电路区相对，并且所述主动显示区位于所述阵列基板行驱动区及所述集成电路区之间，其中所述半导体膜层结构包括：一第一金属层、一层间绝缘层、一第二金属层及一平坦化层，所述层间绝缘层设置于所述第一金属层与所述第二金属层之间，所述平坦化层设置于所述第二金属层上，且所述平坦化层具有多个导电孔；
多个数据线，设置于所述透光基板上的所述主动显示区上，其中所述多个数据线是所述第二金属层经图案化制程所形成；
多个扫描线，设置于所述透光基板上的所述主动显示区上，并且所述多个扫描线垂直于所述多个数据线，其中所述多个扫描线是所述第一金属层经图案化制程所形成；及
一下透明导电层，设置于所述平坦化层上，所述下透明导电层经图案化制程形成多个引线，所述多个引线通过所述多个导电孔电性连接对应的所述多个扫描线，并且所述多个引线的走向平行于所述多个数据线。
根据本发明一实施例，至少一个所述多个引线设置于相邻的两个所述数据线之间。
根据本发明一实施例，所述显示面板还包括一绝缘层及一上透明导电层，所述绝缘层设置于所述多个引线上，所述上透明导电层设置于所述绝缘层上并且电性连接所述多个数据线。
根据本发明一实施例，所述下透明导电层及所述上透明导电层是由一透明导电材料所制成。
根据本发明一实施例，多个引线的其中之一不与所述多个数据线之一重合。
本发明还提供一种显示面板的制作方法，包含：
提供一基板，在所述基板上形成一半导体膜层结构，所述半导体膜层结构依序为一遮光层、一缓冲层、一半导体层及一栅极绝缘层；
形成一第一金属层于所述栅极绝缘层上，并且所述第一金属层经图案化制程形成多个扫描线；
形成一层间绝缘层于所述第一金属层上；
形成一第二金属层于所述层间绝缘层上，并且所述第二金属层经图案化制程形成多个数据线；
形成一平坦化层于所述第二金属层及所述层间绝缘层上，并且所述平坦化层具有多个导电孔；
形成一下透明导电层于所述平坦化层上，所述下透明导电层经图案化制程形成所述多个引线，其中所述引线通过所述导电孔电性连接对应的所述扫描线，且所述引线不与所述数据线重合；
形成一绝缘层于所述下透明导电层上；及
形成一上透明导电层于所述绝缘层上，并且所述上透明导电层通过所述导电孔电性连接对应的所述数据线。
根据本发明一实施例，将所述引线设置于相邻的两个所述数据线之间。
根据本发明一实施例，所述平坦化层经经图案化制程形成一第一导电孔及一第二导电孔，其中所述第一导电孔电性连接所述引线与对应的所述扫描线，所述第二导电孔电性连接所述上透明导电层与对应的所述数据线。
根据本发明一实施例，在所述半导体膜层结构形成一阵列基板行驱动区、一主动显示区及一集成电路区，所述阵列基板行驱动区与所述集成电路区相对，并且所述主动显示区位于所述阵列基板行驱动区及所述集成电路区之间。
根据本发明一实施例，通过所述多个引线电性连接所述多个扫描线与所述阵列基板行驱动区。
本发明还提供一种显示面板，所述显示面板包括：
一透光基板，所述透光基板上具有一半导体膜层结构，所述半导体膜层结构形成一阵列基板行驱动区(GOA)、一主动显示区(AA)及一集成电路区(IC)，所述阵列基板行驱动区与所述集成电路区相对，并且所述主动显示区位于所述阵列基板行驱动区及所述集成电路区之间；
多个数据线，设置于所述透光基板上的所述主动显示区上；
多个扫描线，设置于所述透光基板上的所述主动显示区上，并且所述多个扫描线垂直于所述多个数据线；及
多个引线，电性连接对应的所述多个扫描线与所述阵列基板行驱动区，并且所述多个引线平行于所述多个数据线。
根据本发明一实施例，至少一个所述多个引线设置于相邻的两个所述数据线之间。
根据本发明一实施例，所述显示面板还包括一绝缘层及一上透明导电层，所述绝缘层设置于所述多个引线上，所述上透明导电层设置于所述绝缘层上并且电性连接所述数据线。
根据本发明一实施例，所述多个引线及所述透明导电层是由一透明导电材料所制成。
根据本发明一实施例，多个引线的其中之一不与所述多个数据线之一重合。
本发明还提供一种显示面板，所述显示面板包括：
一透光基板，所述透光基板上具有一半导体膜层结构，所述半导体膜层结构形成一主动显示区；
多个数据线，设置于所述透光基板上的所述主动显示区上；
多个扫描线，设置于所述透光基板上的所述主动显示区上，并且所述多个扫描线垂直于所述多个数据线；及
多个引线，电性连接对应的所述多个扫描线，并且所述多个引线平行于所述多个数据线。
根据本发明一实施例，所述半导体膜层结构包括：一第一金属层、一层间绝缘层、一第二金属层及一平坦化层，所述层间绝缘层设置于所述第一金属层与所述第二金属层之间，所述平坦化层设置于所述第二金属层上，且所述平坦化层具有多个导电孔。
根据本发明一实施例，所述多个扫描线是所述第一金属层经图案化制程所形成，所述多个数据线是所述第二金属层经图案化制程所形成，所述多个引线通过所述多个导电孔电性连接对应的所述多个扫描线。
根据本发明一实施例，所述多个引线是由一透明导电材料所制成。
根据本发明一实施例，至少一个所述多个引线设置于相邻的两个所述数据线之间，并且多个引线的其中之一不与所述多个数据线之一重合。
 有益效果
本发明的有益效果为：利用图形化的透明导电材料作为引线，传递扫描线的信号，透明导电的引线不需要额外绕至边框，进而实现缩小显示面板的侧向边框。而且与现行的制程工艺高度相容，不需要增加额外的光罩及相关的光刻工艺步骤，可以降低后续沿生的改造成本或生产成本。此外，引线不与数据线重合还可以有效地降低寄生电容。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
图1是本发明一实施例的一种显示面板的配置示意图。
图2是图1实施例的局部放大视图。
图3是图2实施例A-A线段的截面图。
图4是本发明一实施例的一种显示面板的制作方法的流程图。
 本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。再者，本发明所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧面、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参照图1、图2及图3，图1是本发明一实施例的一种显示面板的配置示意图。图2是图1实施例的局部放大视图。图3是图2实施例A-A线段的截面图。本实施例提供了一种显示面板100，所述显示面板100包括：一透光基板110、多个扫描线161、162、163、多个数据线181、182、183及多个引线201、202、203。
所述透光基板110上具有一半导体膜层结构，所述半导体膜层结构形成一阵列基板行驱动区(GOA)10、一主动显示区(AA)20及一集成电路区(IC)30，所述阵列基板行驱动区10与所述集成电路区30相对，并且所述主动显示区20位于所述阵列基板行驱动区10及所述集成电路区30之间。依图1实施例的方向来说明，所述阵列基板行驱动区10与所述集成电路区30隔着所述主动显示区20上下相对。所述透光基板110可以是玻璃基板或是由其它透光材料所制程的基板。
所述多个数据线181、182、183设置于所述透光基板110上的所述主动显示区20上。所述多个扫描线161、162、163设置于所述透光基板110上的所述主动显示区20上，并且所述多个扫描线161、162、163垂直于所述多个数据线181、182、183。所述多个引线201、202、203电性连接对应的所述多个扫描线161、162、163与所述阵列基板行驱动区10，并且所述多个引线201、202、203平行于所述多个数据线181、182、183。如图2所示，所述引线201、202、203分别设置于相邻的两个所述数据线181、182、183之间。依图1实施例的方向来说明，通过多个引线201、202、203(平行于所述多个数据线181、182、183)可以将多个扫描线161、162、163引导至与所述集成电路区30相对的所述阵列基板行驱动区10，也就是说，所述阵列基板行驱动区10及所述集成电路区30可以配置在所述主动显示区20上方及下方，大幅地降低所述显示面板100侧向边框(左右边框)的宽度。
请参照图3，所述透光基板110上的所述半导体膜层结构依序包括：一遮光层120、一缓冲层130、一半导体层140、一栅极绝缘层150、一第一金属层160、一层间绝缘层170、一第二金属层180、一平坦化层190、一下透明导电层200、一绝缘层210及一上透明导电层220。
所述遮光层120设置于所述透光基板110上，遮光层120可以由金属材料所制成，例如Mo、Al、Cu、Ti或其合金。所述缓冲层130可以通过沉积技术设置于所述透光基板110及所述遮光层120上。所述缓冲层130可以是SiOx、SiNx单层薄膜或叠层结构薄膜。所述半导体层140可以通过沉积技术形成于所述缓冲层130上。所述半导体层140可以通过图形化制程来定义有源区。所述半导体层140的材料可以是多晶硅或其他适合的材料。所述栅极绝缘层150通过沉积技术设置于所述半导体层140上。所述栅极绝缘层150可以是SiOx、SiNx薄膜或叠层结构薄膜。
所述第一金属层160设置于所述栅极绝缘层150上，并且所述第一金属层160经图案化制程形成所述多个扫描线161、162、163。所述第一金属层160的材料可以包含Mo、Al、Cu或者其合金。所述层间绝缘层170设置于所述第一金属层160上，所述层间绝缘层170可以是SiOx、SiNx薄膜或叠层结构薄膜。所述第二金属层180设置于所述层间绝缘层170上，所述第二金属层180经图案化制程形成所述多个数据线181、182、183。所述第二金属层180的材料可以包含Mo、Al、Cu或者其合金。
所述平坦化层190设置于所述第二金属层180及所述层间绝缘层170上。所述平坦化层190具有多个导电孔192、194。
所述下透明导电层200设置在所述平坦化层190上，并且所述下透明导电层200经图案化制程形成所述多个引线201、202、203。如图3所示，所述引线202通过所述导电孔192电性连接对应的所述扫描线162，藉此将所述扫描线162引导至所述主动显示区20上方的所述阵列基板行驱动区10(如图1所示)。此外，所述引线202不与所述数据线182重合。所述下透明导电层200是由一透明导电材料所制成，例如氧化铟锡(ITO)或是其他具有类似特性的透明导电材料。而且利用所述透明导电材料作为所述多个引线201、202、203不需要额外的沉积步骤，还可以抱持较高的开口率。
所述绝缘层210设置于所述下透明导电层200的所述多个引线201、202、203上，所述上透明导电层220设置于所述绝缘层210上并且电性连接所述数据线181、182、183。如图3所示，所述上透明导电层220通过所述导电孔194电性连接所述多个数据线的其中一个。所述绝缘层210也可以包括一钝化层。所述上透明导电层220是由一透明导电材料所制成，例如氧化铟锡(ITO)或是其他具有类似特性的透明导电材料。
本文中所述半导体膜层结构可以透过图案化制程形成，例如光刻技术搭配蚀刻技术，或相似可以应用在半导体产业中的技术。而半导体膜层结构可以通过气相沉积、蒸镀、溅镀等技术形成膜层。
依图1实施例的方向来说明，利用图案化后的所述下透明导电层200所形成所述多个引线201、202、203作为所述多个扫描线161、162、163连接到所述阵列基板行驱动区10的走线；再加上所述多个引线201、202、203与所述多个数据线181、182、183平行，藉此将所述阵列基板行驱动区10及所述集成电路区30配置在所述主动显示区20上方及下方。如此，可以大幅地降低所述显示面板100侧向边框(左右边框)的宽度，实现极窄边框的显示面板。
请参照图4，图4是本发明一实施例的一种显示面板的制作方法的流程图。本实施例的一种显示面板的制作方法，包含：
步骤S110，提供一基板，在所述基板上形成一半导体膜层结构，所述半导体膜层结构依序为一遮光层、一缓冲层、一半导体层及一栅极绝缘层。此外，在所述半导体膜层结构形成一阵列基板行驱动区、一主动显示区及一集成电路区，所述阵列基板行驱动区与所述集成电路区相对，并且所述主动显示区位于所述阵列基板行驱动区及所述集成电路区之间。
步骤S120，形成一第一金属层于所述栅极绝缘层上，并且所述第一金属层经图案化制程形成多个扫描线。
步骤S130，形成一层间绝缘层于所述第一金属层上。
步骤S140，形成一第二金属层于所述层间绝缘层上，并且所述第二金属层经图案化制程形成多个数据线。
步骤S150，形成一平坦化层于所述第二金属层及所述层间绝缘层上，并且所述平坦化层具有多个导电孔。例如所述平坦化层经经图案化制程形成一第一导电孔及一第二导电孔，其中所述第一导电孔电性连接所述引线与对应的所述扫描线，所述第二导电孔电性连接所述上透明导电层与对应的所述数据线。
步骤S160，形成一下透明导电层于所述平坦化层上，所述下透明导电层经图案化制程形成所述多个引线，其中所述引线通过所述导电孔电性连接对应的所述扫描线，且所述引线不与所述数据线重合。而且所述引线可以设置于相邻的两个所述数据线之间。此外，通过所述多个引线电性连接所述多个扫描线与所述阵列基板行驱动区。
步骤S170，形成一绝缘层于所述下透明导电层上。
步骤S180，形成一上透明导电层于所述绝缘层上，并且所述上透明导电层通过所述导电孔电性连接对应的所述数据线。本发明的有益效果为：利用图形化的透明导电材料作为引线，传递扫描线的信号，透明导电的引线不需要额外绕至边框，进而实现缩小显示面板的侧向边框。而且与现行的制程工艺高度相容，不需要增加额外的光罩及相关的光刻工艺步骤，可以降低后续沿生的改造成本或生产成本。此外，引线不与数据线重合还可以有效地降低寄生电容。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其包含：
    一基板，所述基板上具有一半导体膜层结构，所述半导体膜层结构形成一阵列基板行驱动区、一主动显示区及一集成电路区，所述阵列基板行驱动区与所述集成电路区相对，并且所述主动显示区位于所述阵列基板行驱动区及所述集成电路区之间，其中所述半导体膜层结构包括：一第一金属层、一层间绝缘层、一第二金属层及一平坦化层，所述层间绝缘层设置于所述第一金属层与所述第二金属层之间，所述平坦化层设置于所述第二金属层上，且所述平坦化层具有多个导电孔；
    多个数据线，设置于所述透光基板上的所述主动显示区上，其中所述多个数据线是所述第二金属层经图案化制程所形成；
    多个扫描线，设置于所述透光基板上的所述主动显示区上，并且所述多个扫描线垂直于所述多个数据线，其中所述多个扫描线是所述第一金属层经图案化制程所形成；及
    一下透明导电层，设置于所述平坦化层上，所述下透明导电层经图案化制程形成多个引线，所述多个引线通过所述多个导电孔电性连接对应的所述多个扫描线，并且所述多个引线的走向平行于所述多个数据线。
  2. 如权利要求1所述的显示面板，其中至少一个所述多个引线设置于相邻的两个所述数据线之间。
  3. 如权利要求1所述的显示面板，还包括一绝缘层及一上透明导电层，所述绝缘层设置于所述多个引线上，所述上透明导电层设置于所述绝缘层上并且电性连接所述多个数据线。
  4. 如权利要求3所述的显示面板，其中所述下透明导电层及所述上透明导电层是由一透明导电材料所制成。
  5. 如权利要求4所述的显示面板，其中多个引线的其中之一不与所述多个数据线之一重合。
  6. 一种显示面板的制作方法，其包含：
    提供一基板，在所述基板上形成一半导体膜层结构，所述半导体膜层结构依序为一遮光层、一缓冲层、一半导体层及一栅极绝缘层；
    形成一第一金属层于所述栅极绝缘层上，并且所述第一金属层经图案化制程形成多个扫描线；
    形成一层间绝缘层于所述第一金属层上；
    形成一第二金属层于所述层间绝缘层上，并且所述第二金属层经图案化制程形成多个数据线；
    形成一平坦化层于所述第二金属层及所述层间绝缘层上，并且所述平坦化层具有多个导电孔；
    形成一下透明导电层于所述平坦化层上，所述下透明导电层经图案化制程形成所述多个引线，其中所述引线通过所述导电孔电性连接对应的所述扫描线，且所述引线不与所述数据线重合；
    形成一绝缘层于所述下透明导电层上；及
    形成一上透明导电层于所述绝缘层上，并且所述上透明导电层通过所述导电孔电性连接对应的所述数据线。
  7. 如权利要求6所述的显示面板的制作方法，其中将所述引线设置于相邻的两个所述数据线之间。
  8. 如权利要求6所述的显示面板的制作方法，其中所述平坦化层经经图案化制程形成一第一导电孔及一第二导电孔，其中所述第一导电孔电性连接所述引线与对应的所述扫描线，所述第二导电孔电性连接所述上透明导电层与对应的所述数据线。
  9. 如权利要求6所述的显示面板的制作方法，其中在所述半导体膜层结构形成一阵列基板行驱动区、一主动显示区及一集成电路区，所述阵列基板行驱动区与所述集成电路区相对，并且所述主动显示区位于所述阵列基板行驱动区及所述集成电路区之间。
  10. 如权利要求6所述的显示面板的制作方法，其中通过所述多个引线电性连接所述多个扫描线与所述阵列基板行驱动区。
  11. 一种显示面板，其包含：
    一基板，所述基板上具有一半导体膜层结构，所述半导体膜层结构形成一阵列基板行驱动区、一主动显示区及一集成电路区，所述阵列基板行驱动区与所述集成电路区相对，并且所述主动显示区位于所述阵列基板行驱动区及所述集成电路区之间；
    多个数据线，设置于所述透光基板上的所述主动显示区上；
    多个扫描线，设置于所述透光基板上的所述主动显示区上，并且所述多个扫描线垂直于所述多个数据线；及
    多个引线，电性连接对应的所述多个扫描线与所述阵列基板行驱动区，并且所述多个引线平行于所述多个数据线。
  12. 如权利要求11所述的显示面板，其中至少一个所述多个引线设置于相邻的两个所述数据线之间。
  13. 如权利要求11所述的显示面板，还包括一绝缘层及一上透明导电层，所述绝缘层设置于所述多个引线上，所述上透明导电层设置于所述绝缘层上并且电性连接所述数据线。
  14. 如权利要求13所述的显示面板，其中所述多个引线及所述上透明导电层是由一透明导电材料所制成。
  15. 如权利要求11所述的显示面板，其中多个引线的其中之一不与所述多个数据线之一重合。
  16. 一种显示面板，其包含：
    一基板，所述透光基板上具有一半导体膜层结构，所述半导体膜层结构形成一主动显示区；
    多个数据线，设置于所述透光基板上的所述主动显示区上；
    多个扫描线，设置于所述透光基板上的所述主动显示区上，并且所述多个扫描线垂直于所述多个数据线；及
    多个引线，电性连接对应的所述多个扫描线，并且所述多个引线平行于所述多个数据线。
  17. 如权利要求16所述的显示面板，其中所述半导体膜层结构包括：一第一金属层、一层间绝缘层、一第二金属层及一平坦化层，所述层间绝缘层设置于所述第一金属层与所述第二金属层之间，所述平坦化层设置于所述第二金属层上，且所述平坦化层具有多个导电孔。
  18. 如权利要求17所述的显示面板，其中所述多个扫描线是所述第一金属层经图案化制程所形成，所述多个数据线是所述第二金属层经图案化制程所形成，所述多个引线通过所述多个导电孔电性连接对应的所述多个扫描线。
  19. 如权利要求18所述的显示面板，其中所述多个引线是由一透明导电材料所制成。
  20. 如权利要求19所述的显示面板，其中至少一个所述多个引线设置于相邻的两个所述数据线之间，并且多个引线的其中之一不与所述多个数据线之一重合。
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