WO2020151193A1 - Command-based method for monitoring bandwidth efficiency of dram controller - Google Patents
Command-based method for monitoring bandwidth efficiency of dram controller Download PDFInfo
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- the invention relates to a method for detecting the bandwidth efficiency of a DRAM controller, in particular to a method for detecting the bandwidth efficiency of a DRAM controller based on instructions, and belongs to the field of memory bandwidth efficiency detection.
- the technical problem to be solved by the present invention is to provide a command-based DRAM controller bandwidth efficiency detection method, which can automatically capture the number of transmission data more accurately according to the transmission mode, and has a better monitoring effect.
- the technical solution adopted by the present invention is: an instruction-based DRAM controller bandwidth efficiency detection method, which captures the read and write instructions and clock signal lines between the main controller and the DRAM particles according to the DRAM interface timing.
- Monitor read and write instructions grab BC4 read instructions, BC4 write instructions, BL8 read instructions, and BL8 write instructions from the read and write instructions, grab the number of DRAM clock cycles in the detection period from the clock signal line, and then formula
- monitoring read and write commands is simplified to the monitoring of the four signals of CS, ACT, RAS, and CAS, and then the A12 signal is used to distinguish the BC4 command or the BL8 command.
- A12 is 0 for the BC4 command, and vice versa for the BL8 command.
- the monitored command is a read or write command for BC4.
- a monitor made in systemverilog or verilog language is used to capture the read and write instructions and clock signal lines between the main controller and the DRAM particles.
- the present invention can automatically capture the number of transmission data more accurately according to the transmission mode, and the monitoring and improvement of bandwidth efficiency is particularly obvious when BC4 and BL8 (on the fly) are mixed transmission; and the monitor is more versatile, Any host controller/DRAM particle that conforms to the DDR4 protocol standard can accurately capture the number of data instructions transmitted in any transmission mode; it does not have to be compared with a fixed transmission mode (such as fixed BL8) like a simplified monitor. Good monitoring effect.
- Figure 1 is a schematic diagram of DDR4 standard burst length configuration
- Figure 2 is the truth table of DDR4 standard commands
- Figure 3 is a schematic diagram of part of the monitor code.
- DRAM particles all contain Mode Register (hereinafter referred to as MR), and the DRAM main controller needs to configure the transmission characteristics of the DRAM particles through the MR setting command; MR0 can control the burst length of the transmission, as shown in Figure 1 on the following page ;
- A1 two bits can also be configured as 01, that is, BC4or 8 (on the fly); in this way, each DRAM read and write command transmits 4 or 8 beats of data;
- the DRAM burst length in the above formula is equal to 8 (divided by 2 because both DDR rising and falling edges transmit data, that is, two numbers per beat), that is, the numerator in the formula is "4 times The total number of read and write instructions"; this method is more accurate when the measured simulation process is full BL8 transmission; but once the BC4 and BL8 mixed data transmission occurs during the monitored simulation process, the DRAM burst length in the traditional monitoring method is If it is fixed equal to 8, it will inevitably cause the result of a larger numerator, that is, the bandwidth of the grabbing calculation is falsely high.
- the code is written into a monitor (usually using systemverilog or verilog language).
- the monitor is connected to the connection between the main controller and the DRAM particles, and the read and write instructions are captured according to the DRAM interface timing.
- the fetched instructions are counted to complete the numerator part of the formula, and the monitor also grabs the clock, which is the clock signal line, and writes down the number of clock cycles during the period to complete the denominator part of the formula; calculate the bandwidth utilization rate according to the formula and print it out in the simulation result ; In this way, the effect of automatically monitoring bandwidth utilization while running simulation can be achieved.
- the key is how to accurately capture the number of BC4 instructions and the number of BL8 instructions respectively; as shown in Figure 2, based on the truth table of the DDR4 standard instructions, the read and write instructions are monitored after the interface signals are captured.
- the logic of can be simplified into the monitoring of the four signals of CS, ACT, RAS, and CAS.
- BC4 and BL8 are mainly based on A12 in the fifth column from the bottom of Figure 2 (that is, the 12th bit of the address address); if A12 is 0, it is BC4 instruction, and vice versa, BL8 instruction; in the specific implementation of the simulation monitor, the code for the above monitoring and distinguishing between BC4 instruction and BL8 instruction is shown in Figure 3: where cas_cnt is the read/write times of the instruction, the first in Figure 3 One if judgment logic condition is the simplified monitoring of all read and write commands (the monitoring of the four signals of CS, ACT, RAS, and CAS mentioned above, meeting this condition represents a read or write command), when A12 is equal to 1 When this instruction is a BL8 (read or write), so cas_cnt plus 4 (corresponding to the formula 2 (BL8 read instructions + BL8 write instructions) * (8/2)); on the contrary, when A12 is equal to 0, this instruction It is a BC4 (read or write), so cas_cnt adds 2 (
- the present invention can automatically capture the number of transmission data more accurately according to the transmission mode, and the monitoring improvement of bandwidth efficiency is particularly obvious when BC4 and BL8 (on the fly) are mixed transmission; and the monitor is more versatile, and is suitable for any DDR-compliant monitor.
- the protocol-standard main controller/DRAM particles can accurately capture the number of data instructions transmitted in any transmission mode; it does not need to be like a simplified monitor and can only be monitored in a fixed transmission mode (such as fixed BL8) effect.
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Abstract
A command-based method for monitoring the bandwidth efficiency of a DRAM controller. The method comprises: fetching, according to DRAM interface timing, read and write commands and a clock signal line between a main controller and a DRAM chip; monitoring the read and write commands; fetching, from the read and write commands, a BC4 read command count, a BC4 write command count, a BL8 read command count, and a BL8 write command count; fetching, from the clock signal line, a DRAM clock cycle count in a detection period; and calculating the bandwidth efficiency of the controller according to the fetched information. The present method automatically uses transmission modes as a reference basis so as to fetch transmission data counts accurately, thereby achieving good monitoring effects.
Description
本发明涉及一种DRAM控制器带宽效率检测方法，具体的说，是一种基于指令的DRAM控制器带宽效率检测方法，属于存储器带宽效率检测领域。The invention relates to a method for detecting the bandwidth efficiency of a DRAM controller, in particular to a method for detecting the bandwidth efficiency of a DRAM controller based on instructions, and belongs to the field of memory bandwidth efficiency detection.
在数字前端研发过程中，现在的SOC很多都要在内部集成DRAM主控制器，作为代码和数据的主要缓存，DRAM的带宽利用效率往往是整个***的性能关键。通常进行数字前端架构设计时，要进行***的性能效率仿真，其中包括DRAM的带宽仿真；最早的传统仿真方法是dump仿真波形，在波形上人工观测DRAM的数据读写情况进而统计出DRAM的使用效率，耗时耗力；可以采用基于DRAM读写指令次数的统计方法估算带宽利用率，不过因为通常DRAM在使用时多设置成固定的突发长度(如BL8)故监测方法大多也都简化为指令数乘以固定突发长度(如BL8，即4拍)，但作为被动的监测装置如monitor如果按照固定突发长度(BL8)监测在某些情况下会导致带宽利用率监测不准。In the digital front-end research and development process, many of the current SOCs need to integrate a DRAM main controller internally as the main buffer for code and data. The bandwidth utilization efficiency of DRAM is often the key to the performance of the entire system. Usually when designing a digital front-end architecture, it is necessary to perform system performance and efficiency simulation, including DRAM bandwidth simulation; the earliest traditional simulation method is to dump the simulation waveform, and manually observe the DRAM data read and write conditions on the waveform and then count the DRAM usage Efficiency, time-consuming and labor-intensive; statistical methods based on the number of DRAM read and write instructions can be used to estimate bandwidth utilization, but because DRAM is usually set to a fixed burst length (such as BL8) when in use, most of the monitoring methods are also simplified to The number of instructions is multiplied by a fixed burst length (for example, BL8, that is 4 beats), but as a passive monitoring device such as a monitor, if the fixed burst length (BL8) is used for monitoring, the bandwidth utilization rate will be inaccurate in some cases.
发明内容Summary of the invention
本发明要解决的技术问题是提供一种基于指令的DRAM控制器带宽效率检测方法，能够自动的根据传输模式更准确的抓取传输数据个数，具有较好的监测效果。The technical problem to be solved by the present invention is to provide a command-based DRAM controller bandwidth efficiency detection method, which can automatically capture the number of transmission data more accurately according to the transmission mode, and has a better monitoring effect.
为了解决所述技术问题，本发明采用的技术方案是：一种基于指令的DRAM控制器带宽效率检测方法，按照DRAM接口时序抓取主控制器与DRAM颗粒间的读写指令和时钟信号线，监测读写指令，从读写指令中抓取BC4读指令数、BC4写指令数、BL8读指令数、BL8写指令数，从时钟信号线中抓取检测时段内的DRAM时钟周期数，然后根据公式In order to solve the technical problem, the technical solution adopted by the present invention is: an instruction-based DRAM controller bandwidth efficiency detection method, which captures the read and write instructions and clock signal lines between the main controller and the DRAM particles according to the DRAM interface timing. Monitor read and write instructions, grab BC4 read instructions, BC4 write instructions, BL8 read instructions, and BL8 write instructions from the read and write instructions, grab the number of DRAM clock cycles in the detection period from the clock signal line, and then formula
计算控制器的带宽效率。Calculate the bandwidth efficiency of the controller.
进一步的，监测读写指令逻辑简化成对CS、ACT、RAS、CAS四个信号的监测，然后通过A12信号区别BC4指令或者BL8指令，A12为0则为BC4指令，反之则为BL8指令。Further, the logic of monitoring read and write commands is simplified to the monitoring of the four signals of CS, ACT, RAS, and CAS, and then the A12 signal is used to distinguish the BC4 command or the BL8 command. A12 is 0 for the BC4 command, and vice versa for the BL8 command.
进一步的，当CS＝0、ACT＝1、RAS＝1、CAS＝0，并且A12＝0时，监测到的指令为一次针对BC4的读或写指令，此时在BC4读/写指令数基础上加2；当CS＝0、ACT＝1、RAS＝1、CAS＝0，并且A12＝1时，监测到的指令为一次针对BL8的读或写指令，此时在 BL8读/写指令数基础上加4。Further, when CS=0, ACT=1, RAS=1, CAS=0, and A12=0, the monitored command is a read or write command for BC4. At this time, the number of read/write commands is based on BC4. Add 2 to the top; when CS=0, ACT=1, RAS=1, CAS=0, and A12=1, the monitored command is a read or write command for BL8. At this time, the number of read/write commands in BL8 Add 4 on the basis.
进一步的，利用systemverilog或verilog语言做成的monitor抓取主控制器与DRAM颗粒间的读写指令和时钟信号线。Further, a monitor made in systemverilog or verilog language is used to capture the read and write instructions and clock signal lines between the main controller and the DRAM particles.
有益效果：本发明能够自动的根据传输模式更准确的抓取传输数据个数，在BC4和BL8(on the fly)混合传输时对于带宽效率的监测提升尤为明显；且该monitor更为通用，对任何符合DDR4协议标准的主控制器/DRAM颗粒工作在任何传输模式下都能准确抓取数据指令传输个数；不必像简化的monitor那样只能在固定传输模式下(如fixed BL8)才有较好的监测效果。Beneficial effects: The present invention can automatically capture the number of transmission data more accurately according to the transmission mode, and the monitoring and improvement of bandwidth efficiency is particularly obvious when BC4 and BL8 (on the fly) are mixed transmission; and the monitor is more versatile, Any host controller/DRAM particle that conforms to the DDR4 protocol standard can accurately capture the number of data instructions transmitted in any transmission mode; it does not have to be compared with a fixed transmission mode (such as fixed BL8) like a simplified monitor. Good monitoring effect.
图1为DDR4标准突发长度配置示意图；Figure 1 is a schematic diagram of DDR4 standard burst length configuration;
图2为DDR4标准指令真值表；Figure 2 is the truth table of DDR4 standard commands;
图3为monitor的部分代码示意图。Figure 3 is a schematic diagram of part of the monitor code.
下面结合附图和具体实施例对本发明作进一步的说明。The present invention will be further described below in conjunction with the drawings and specific embodiments.
实施例1Example 1
根据JEDEC标准，DRAM颗粒都含有Mode Register(以下简称MR)，DRAM主控制器需要通过MR设置指令配置DRAM颗粒的传输特性；其中MR0可以控制传输的突发长度(burst length)，如下页图1；According to the JEDEC standard, DRAM particles all contain Mode Register (hereinafter referred to as MR), and the DRAM main controller needs to configure the transmission characteristics of the DRAM particles through the MR setting command; MR0 can control the burst length of the transmission, as shown in Figure 1 on the following page ；
通常DRAM在使用时多设置成固定的突发长度，即A1:A0＝00fixed BL8(图1圈出部分的第一行)；此为比较常用的DRAM颗粒使用方式，这样每一次DRAM读写指令均传输8拍数据；Usually DRAM is set to a fixed burst length when in use, that is, A1:A0=00fixed BL8 (the first line of the circled part in Figure 1); this is a more common way to use DRAM particles, so every DRAM read and write command Both transmit 8 beats of data;
但A0：A1两位同样也可配置成01，即BC4or 8(on the fly)；这样每一次DRAM读写指令传输4拍或8拍数据；But A0: A1 two bits can also be configured as 01, that is, BC4or 8 (on the fly); in this way, each DRAM read and write command transmits 4 or 8 beats of data;
传统的粗略估算方法如下公式所示(分子：实际用于传输的时钟周期数，分母：总时钟周期数)：The traditional rough estimation method is shown in the following formula (numerator: the number of clock cycles actually used for transmission, denominator: the total number of clock cycles):
由于突发长度常配置为fixed BL8，所以上面公式中的DRAM突发长度等于8(除以2是因为DDR上升下降沿都传输数据即一拍两个数)，即公式中分子为“4倍的读写指令总 数”；这样的方法在所测仿真过程为全BL8传输时较为准确；不过一旦所监测的仿真过程中出现BC4和BL8混合的数据传输，传统监测方法中的DRAM突发长度却固定等于8，难免会造成分子较大的结果，即抓取测算的带宽虚高。Since the burst length is often configured as fixed BL8, the DRAM burst length in the above formula is equal to 8 (divided by 2 because both DDR rising and falling edges transmit data, that is, two numbers per beat), that is, the numerator in the formula is "4 times The total number of read and write instructions"; this method is more accurate when the measured simulation process is full BL8 transmission; but once the BC4 and BL8 mixed data transmission occurs during the monitored simulation process, the DRAM burst length in the traditional monitoring method is If it is fixed equal to 8, it will inevitably cause the result of a larger numerator, that is, the bandwidth of the grabbing calculation is falsely high.
结合以上，测算方法改进为：In combination with the above, the calculation method is improved as:
具体实现时，编写代码做成monitor(通常用systemverilog或verilog语言)，在仿真平台中将monitor连接在主控制器和DRAM颗粒间的连线上，按照DRAM接口时序抓取读写指令，根据抓取的指令进行计数完成公式中分子部分，同时monitor也抓取clock也就是时钟信号线，记下期间时钟周期数即完成公式中分母部分；按照公式计算出带宽利用率并在仿真结果中打印出来；这样就可达成跑仿真的同时自动监测带宽利用率的效果。In the specific implementation, the code is written into a monitor (usually using systemverilog or verilog language). In the simulation platform, the monitor is connected to the connection between the main controller and the DRAM particles, and the read and write instructions are captured according to the DRAM interface timing. The fetched instructions are counted to complete the numerator part of the formula, and the monitor also grabs the clock, which is the clock signal line, and writes down the number of clock cycles during the period to complete the denominator part of the formula; calculate the bandwidth utilization rate according to the formula and print it out in the simulation result ; In this way, the effect of automatically monitoring bandwidth utilization while running simulation can be achieved.
具体到公式2的改进在具体实现时，关键是如何分别准确抓取BC4指令数和BL8指令数；如图2所示，基于DDR4标准指令的真值表，抓取接口信号后监测读写指令的逻辑可化简成对于CS、ACT、RAS、CAS四个信号的监测，之后区分BC4和BL8主要是依靠图2倒数第5列的A12(即address地址第12位)；A12为0则为BC4指令，反之则为BL8指令；该仿真monitor的具体实现中关于上述监测以及区分BC4指令和BL8指令的代码如图3所示：其中cas_cnt为指令的读/写次数，图3中的第一个if判断逻辑条件即简化后的全部读写指令的监测(上文中提到的CS、ACT、RAS、CAS四个信号的监测，满足此条件代表是一次读或者写指令)，当A12等于1时，此指令为一次BL8(读或写)，所以cas_cnt加4(对应公式2中(BL8读指令数+BL8写指令数)*(8/2))；反之当A12等于0时，此指令为一次BC4(读或写)，所以cas_cnt加2(对应公式2中(BC4读指令数+BC4写指令数)*(4/2))。Specific to the improvement of formula 2 in the specific implementation, the key is how to accurately capture the number of BC4 instructions and the number of BL8 instructions respectively; as shown in Figure 2, based on the truth table of the DDR4 standard instructions, the read and write instructions are monitored after the interface signals are captured. The logic of can be simplified into the monitoring of the four signals of CS, ACT, RAS, and CAS. After that, the distinction between BC4 and BL8 is mainly based on A12 in the fifth column from the bottom of Figure 2 (that is, the 12th bit of the address address); if A12 is 0, it is BC4 instruction, and vice versa, BL8 instruction; in the specific implementation of the simulation monitor, the code for the above monitoring and distinguishing between BC4 instruction and BL8 instruction is shown in Figure 3: where cas_cnt is the read/write times of the instruction, the first in Figure 3 One if judgment logic condition is the simplified monitoring of all read and write commands (the monitoring of the four signals of CS, ACT, RAS, and CAS mentioned above, meeting this condition represents a read or write command), when A12 is equal to 1 When this instruction is a BL8 (read or write), so cas_cnt plus 4 (corresponding to the formula 2 (BL8 read instructions + BL8 write instructions) * (8/2)); on the contrary, when A12 is equal to 0, this instruction It is a BC4 (read or write), so cas_cnt adds 2 (corresponding to the formula 2 (BC4 read instructions + BC4 write instructions)*(4/2)).
本实施例中，当满足CS＝0、ACT＝1、RAS＝1、CAS＝0，并且A12＝0时，为一次针对BC4的读或写指令；当CS＝0、ACT＝1、RAS＝1、CAS＝0，并且A12＝1时，为一次针对BL8的读或写指令。In this embodiment, when CS=0, ACT=1, RAS=1, CAS=0, and A12=0, it is a read or write command for BC4; when CS=0, ACT=1, RAS= 1. When CAS=0 and A12=1, it is a read or write command for BL8.
Monitor可以根据仿真中DRAM初始化的过程中MR的配置情况(抓取MR指令)来确定后续的传输时工作于哪种模式下(图1中A1:A0＝00、01、10的三种情况)，从而更准确的抓取和监测实际的数据传输数量，进而随着仿真自动的打印出带宽效率。Monitor can determine in which mode the subsequent transmission works according to the configuration of MR during the DRAM initialization process in the simulation (grabbing MR instruction) (the three cases of A1: A0 = 00, 01, 10 in Figure 1) , So as to more accurately capture and monitor the actual data transmission quantity, and then automatically print out the bandwidth efficiency with the simulation.
本发明能够自动的根据传输模式更准确的抓取传输数据个数，在BC4和BL8(on the fly)混合传输时对于带宽效率的监测提升尤为明显；且该monitor更为通用，对任何符合DDR协议标准的主控制器/DRAM颗粒工作在任何传输模式下都能准确抓取数据指令传输个数；不必像简化的monitor那样只能在固定传输模式下(如fixed BL8)才有较好的监测效果。The present invention can automatically capture the number of transmission data more accurately according to the transmission mode, and the monitoring improvement of bandwidth efficiency is particularly obvious when BC4 and BL8 (on the fly) are mixed transmission; and the monitor is more versatile, and is suitable for any DDR-compliant monitor. The protocol-standard main controller/DRAM particles can accurately capture the number of data instructions transmitted in any transmission mode; it does not need to be like a simplified monitor and can only be monitored in a fixed transmission mode (such as fixed BL8) effect.
以上描述的仅是本发明的基本原理和优选实施例，本领域技术人员根据本发明做出的改进和替换，属于本发明的保护范围。What has been described above are only the basic principles and preferred embodiments of the present invention. Improvements and replacements made by those skilled in the art based on the present invention belong to the protection scope of the present invention.
Claims (4)
- 一种基于指令的DRAM控制器带宽效率检测方法，其特征在于：按照DRAM接口时序抓取主控制器与DRAM颗粒间的读写指令和时钟信号线，监测读写指令，从读写指令中抓取BC4读指令数、BC4写指令数、BL8读指令数、BL8写指令数，从时钟信号线中抓取检测时段内的[A1]时钟周期数，然后根据公式An instruction-based method for detecting bandwidth efficiency of DRAM controllers, which is characterized by: capturing read and write instructions and clock signal lines between the main controller and DRAM particles according to the DRAM interface timing, monitor the read and write instructions, and capture from the read and write instructions. Take the number of BC4 read instructions, the number of BC4 write instructions, the number of BL8 read instructions, and the number of BL8 write instructions. Grab the number of [A1] clock cycles in the detection period from the clock signal line, and then follow the formula
计算控制器的带宽效率。Calculate the bandwidth efficiency of the controller. - 根据权利要求1所述的基于指令的DRAM控制器带宽效率检测方法，其特征在于：监测读写指令逻辑简化成对CS、ACT、RAS、CAS四个信号的监测，然后通过A12信号区别BC4指令或者BL8指令，A12为0则为BC4指令，反之则为BL8指令。The instruction-based bandwidth efficiency detection method of a DRAM controller according to claim 1, characterized in that the logic of monitoring read and write instructions is simplified into the monitoring of four signals of CS, ACT, RAS, and CAS, and then the BC4 instructions are distinguished by the A12 signal Or BL8 instruction, A12 is 0, it is BC4 instruction, otherwise it is BL8 instruction.
- 根据权利要求2所述的基于指令的DRAM控制器带宽效率检测方法，其特征在于：当CS＝0、ACT＝1、RAS＝1、CAS＝0，并且A12＝0时，监测到的指令为一次针对BC4的读或写指令，此时在BC4读/写指令数基础上加2；当CS＝0、ACT＝1、RAS＝1、CAS＝0，并且A12＝1时，监测到的指令为一次针对BL8的读或写指令，此时在BL8读/写指令数基础上加4。The command-based DRAM controller bandwidth efficiency detection method according to claim 2, characterized in that: when CS=0, ACT=1, RAS=1, CAS=0, and A12=0, the monitored command is A read or write instruction for BC4, at this time, add 2 to the number of read/write instructions for BC4; when CS=0, ACT=1, RAS=1, CAS=0, and A12=1, the monitored instruction It is a read or write instruction for BL8, at this time, 4 is added to the number of BL8 read/write instructions.
- 根据权利要求1所述的基于指令的DRAM控制器带宽效率检测方法，其特征在于：利用systemverilog或verilog语言做成的monitor抓取主控制器与DRAM颗粒间的读写指令和时钟信号线。The instruction-based method for detecting bandwidth efficiency of a DRAM controller according to claim 1, characterized in that a monitor made in system verilog or verilog language is used to capture read and write instructions and clock signal lines between the main controller and the DRAM particles.
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