WO2020147199A1 - Method for fabricating asymmetric surface-channel field-effect transistor and power device - Google Patents

Method for fabricating asymmetric surface-channel field-effect transistor and power device Download PDF

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Publication number
WO2020147199A1
WO2020147199A1 PCT/CN2019/080066 CN2019080066W WO2020147199A1 WO 2020147199 A1 WO2020147199 A1 WO 2020147199A1 CN 2019080066 W CN2019080066 W CN 2019080066W WO 2020147199 A1 WO2020147199 A1 WO 2020147199A1
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layer
metal
gate
metal layer
drain
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PCT/CN2019/080066
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French (fr)
Chinese (zh)
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吕元杰
王元刚
冯志红
蔚翠
周闯杰
宋旭波
何泽召
梁士雄
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中国电子科技集团公司第十三研究所
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Publication of WO2020147199A1 publication Critical patent/WO2020147199A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • This application belongs to the technical field of microwave power devices, and more specifically, relates to a method for preparing an asymmetric surface channel field effect transistor and a power device.
  • surface channel devices have great advantages in high speed and high limit, they have attracted much attention in the high frequency field.
  • surface channel materials include p-type surface channels formed by hydrogen plasma treatment of diamond, and two-dimensional materials such as graphene, BN, black phosphorus, and two-dimensional GaN.
  • the characteristics of surface channel devices are greatly affected by the surface state.
  • the self-aligned process developed in recent years has effectively solved the above-mentioned problems.
  • the self-aligned process can only achieve a device structure with equal spacing between the gate source and the gate drain.
  • the saturation voltage is generally low. Therefore, it is difficult for the self-aligned process to take into account both the breakdown voltage and the saturation current.
  • the purpose of this application is to provide a method for manufacturing an asymmetric surface channel field effect transistor, which aims to solve the technical problem of low breakdown voltage in the prior art.
  • the technical solution adopted in this application is to provide a method for manufacturing an asymmetric surface channel field effect transistor, which includes the following steps:
  • the gate corrosion window pattern corresponds to the deposited gate metal layer
  • the field plate metal window pattern corresponds to the deposited field plate metal layer
  • the gate metal layer and the field plate metal layer are not connected
  • the distance between the two sides of the gate metal layer and the uncorroded metal mask layer on the corresponding side is not equal, and the distance between the gate metal layer and the uncorroded metal mask layer on the side of the source metal layer is the effective gate Source spacing, the spacing between the gate metal layer and the uncorroded metal mask layer on the side of the drain metal layer is the effective gate-drain spacing, and the effective gate-source spacing is smaller than the effective gate-drain spacing.
  • An under-gate dielectric layer is deposited on the surface channel epitaxial layer, and the gate metal layer and the field plate metal are respectively deposited on the under-gate dielectric layer.
  • the dielectric layer under the gate is a single-layer dielectric
  • the dielectric layer under the gate is a multilayer dielectric.
  • the structures of the gate etching window patterns are the same;
  • the structure of at least one of the gate etch window patterns is different from the structure of other gate etch window patterns;
  • the structures of the gate etching window patterns are all different.
  • the structure of the gate metal layer is straight gate, T-type gate, TT-type gate, TTT-type gate, U-type gate, and Y-type gate.
  • One or more combinations of gates are straight gate, T-type gate, TT-type gate, TTT-type gate, U-type gate, and Y-type gate.
  • the structure of the field plate metal window patterns is the same;
  • the structure of at least one of the field plate metal window patterns is different from the structure of other field plate metal window patterns
  • the structures of the metal window patterns of the field plates are all different.
  • the metal mask layer has the same metal type as the source metal layer and the drain metal layer;
  • the metal mask layer and the source metal layer and the drain metal layer have different metal types.
  • the metal mask layer, the source metal layer, the drain metal layer, the gate metal layer and the field plate metal layer are all a single layer of metal;
  • At least one single-layer metal and one multi-layer metal are included.
  • Another objective of the present application is to provide an asymmetric surface channel field effect transistor, which is prepared by the method described above.
  • the effective gate-source spacing is not equal to the effective gate-drain spacing, and devices with the effective gate-source spacing smaller than the effective gate-drain spacing can take into account saturation current and effectively increase breakdown voltage And working voltage, improve the power density of the device.
  • FIG. 1 is a schematic structural diagram of preparing a metal mask layer in a method for preparing an asymmetric surface channel field effect transistor according to an embodiment of the application;
  • FIG. 2 is a schematic structural diagram of preparing a first photoresist layer in a method for preparing an asymmetric surface channel field effect transistor according to an embodiment of the application;
  • FIG. 3 is a schematic diagram of the structure of the source and drain metal layers in the method for preparing an asymmetric surface channel field effect transistor provided by an embodiment of the application;
  • FIG. 4 is a schematic structural diagram of preparing a photoresist layer in a method for preparing an asymmetric surface channel field effect transistor provided by an embodiment of the application;
  • FIG. 5 is a schematic structural diagram of a photolithographic pattern of a method for manufacturing an asymmetric surface channel field effect transistor provided by an embodiment of the application;
  • FIG. 6 is a schematic structural diagram of an asymmetric surface channel field effect transistor prepared in an embodiment of the application.
  • FIG. 7 is a top view of an asymmetric surface channel field effect transistor prepared in an embodiment of the application.
  • the manufacturing method of the asymmetric surface channel field effect transistor includes the following steps:
  • a metal mask layer 2 is deposited on the surface trench epitaxial layer 1, see FIG. 1;
  • a first photoresist layer 12 is prepared on the metal mask layer 2, see FIG. 2;
  • At least one gate etch window pattern 10 and at least one field plate metal window pattern 11 are photoetched between the source metal layer 3 and the drain metal layer 8, and the metal mask layer 2 at the corresponding part is etched, see FIG. 5;
  • the gate corrosion window pattern 10 corresponds to the deposited gate metal layer 6, the field plate metal window pattern 11 corresponds to the deposited field plate metal layer 7, and the gate metal layer 6 and the field plate metal layer 7 are not connected , See Figure 6;
  • the distances between the two sides of the gate metal layer 6 and the uncorroded metal mask layer 2 on the corresponding side are not equal, and the gate metal layer 6 is opposite to the uncorroded metal mask layer 2 on the side of the source metal layer 3.
  • the effective gate-source spacing the spacing between the gate metal layer 6 and the uncorroded metal mask layer 2 on the side of the drain metal layer 8 is the effective gate-drain spacing, that is, the effective gate-source spacing and the effective gate-drain spacing are not equal, For devices with an effective gate-source spacing smaller than the effective gate-drain spacing, see Figure 6.
  • the method for preparing an asymmetric surface channel field effect transistor provided by the present application has an effective gate-source spacing and an effective gate-drain spacing that are not equal, and a device with an effective gate-source spacing smaller than the effective gate-drain spacing takes into account saturation current , Effectively improve the breakdown voltage and working voltage, and improve the power density of the device.
  • the mesa isolation process can be performed after any of the above steps, and the function is to separate the device prepared in this application from other parts.
  • a gate metal layer 6 is deposited at the gate etching window pattern 10, and the field plate metal window pattern Before the field plate metal is deposited at 11 places: the under-gate dielectric layer 5 is deposited on the surface trench epitaxial layer 1, and the gate metal layer 6 and the field plate metal are respectively deposited on the under-gate dielectric layer 5 . That is, the gate metal layer 6 and the field plate metal layer 7 may be provided with a sub-gate dielectric layer 5, see FIG. 6, or the gate metal layer 6 and the field plate metal layer 7 may be directly prepared on the surface channel epitaxial layer 1. .
  • the under-gate dielectric layer 5 is a single-layer dielectric; or, the under-gate dielectric layer 5 is a multi Layer medium.
  • the gate etching window patterns 10 when the number of the gate etching window patterns 10 is two or more, the gate etching window
  • the structures of the patterns 10 are the same; or, the structure of at least one of the gate etch window patterns 10 is different from the structure of the other gate etch window patterns 10; or, the structures of the gate etch window patterns 10 are all different.
  • FIG. 5 shows a gate etch window pattern 10, and two or three patterns can also be lithographically etched at the same time.
  • the structures and sizes of these patterns may be identical or not identical, depending on actual needs.
  • the structure of the gate metal layer 6 is straight One or more combinations of gates, T-type gates, TT-type gates, TTT-type gates, U-type gates and Y-type gates.
  • the gate metal layer 6 in the figure of this embodiment is a T-shaped gate. See FIG. 6.
  • the T-shaped gate helps to balance the gate parasitic capacitance and gate resistance characteristics and improve the frequency characteristics of the device.
  • the structure and number of the gate metal layer 6 are based on photolithography.
  • the gate etching window pattern 10 depends on the structure and number.
  • FIG. 5 shows a field plate metal window pattern 11. According to actual needs, two, three, four, etc. can be lithographically engraved. The structures of these patterns may be identical or not identical, as shown in Fig. 6
  • the structure of the field plate metal layer 7 is a T-shaped structure.
  • the asymmetric surface channel field effect transistor provided by the present application, no voltage is applied to the field plate metal layer 7; or, a separate voltage is applied.
  • the role of the field plate metal layer 7 is to facilitate the formation of an asymmetric structure, and in addition, it can form a field plate structure.
  • the metal mask layer 2 and the metal of the source metal layer 3 and the drain metal layer 8 The type is the same; or, the metal mask layer 2 and the source metal layer 3 and the drain metal layer 8 have different metal types.
  • the metals of the metal mask layer 2, the source metal layer 3 and the drain metal layer 8 are all metals conventionally used in the preparation of existing semiconductor devices.
  • the metal mask layer 2, the source metal layer 3, the drain metal layer 8, the The gate metal layer 6 and the field plate metal layer 7 are both single-layer metal; or, both are multi-layer metals; or, they include at least one single-layer metal and one multi-layer metal.
  • the surface channel epitaxial layer 1 is a diamond p-type surface channel, or is graphene, BN, black phosphorus, GaN, etc.
  • the substrate used is diamond, SiC, GaN, sapphire, Si, Au, quartz, SiO2, SiN, copper, etc., or a composite substrate of a combination of multiple materials.
  • two photoresist layers are used to form the gate corrosion window pattern 10 and the field plate metal window pattern 11 through exposure and development, which can be developed in one exposure or in multiple exposures and multiple developments.
  • the number of layers of a layer of photoresist can also be two or more layers.
  • a passivation layer is prepared to protect the device, and the passivation layer is a single-layer or multi-layer dielectric.
  • this application also provides a power device manufactured by the method described.
  • S represents the source metal layer 3
  • D represents the gate metal layer 6
  • G represents the drain metal layer 8.
  • the gate is biased toward the source instead of between the source and drain, that is, the source metal layer 3 and the drain metal layer 8 are asymmetrically distributed relative to the gate metal layer 6, and are located between the source and gate or between the gate and drain Increase the field plate metal window, the gate bias source device can take into account the saturation current, effectively increase the breakdown voltage and working voltage, and improve the power density of the device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
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  • Junction Field-Effect Transistors (AREA)

Abstract

The present application provides a method for fabricating an asymmetric surface-channel field-effect transistor and power device, belonging to the technical field of microwave power devices, comprising the following steps: depositing a metal mask layer; preparing a first photoresist layer; forming a source region pattern and a drain region pattern; depositing a source metal layer and a drain metal layer at the source region pattern and the drain region pattern; lifting off and removing the first photoresist; applying two photoresist layers; photolithographically etching a gate-etching window pattern and a field plate metal window pattern, and etching the metal mask layer at the corresponding location; depositing a gate metal layer and a field plate metal layer, the distance between the two sides of the gate metal layer and the corresponding unetched metal mask layer being different; the effective gate–source spacing of the device is smaller than the effective gate–drain spacing. The method for fabricating the asymmetric surface-channel field-effect transistor, and device having an effective gate–source spacing which is smaller than the effective gate–drain spacing, provided by the present application, are capable of taking into account the saturation current and effectively improving breakdown voltage and operating voltage to increase the power density of the device.

Description

非对称表面沟道场效应晶体管的制备方法及功率器件Method for preparing asymmetric surface channel field effect transistor and power device 技术领域Technical field
本申请属于微波功率器件技术领域，更具体地说，是涉及一种非对称表面沟道场效应晶体管的制备方法及功率器件。This application belongs to the technical field of microwave power devices, and more specifically, relates to a method for preparing an asymmetric surface channel field effect transistor and a power device.
背景技术Background technique
由于表面沟道器件在高速、高限域性等方面具有较大优势，在高频领域备受关注。目前常用的表面沟道材料包括氢等离子体处理金刚石形成的p型表面沟道，以及石墨烯、BN、黑磷、二维GaN等二维材料。表面沟道器件特性受表面态影响大，近些年开发的自对准工艺，有效解决了上述问题。但是自对准工艺仅能实现栅源和栅漏等间距器件结构，为了兼顾饱和电流，击穿电压普遍较低，因此自对准工艺难以兼顾击穿电压和饱和电流。Because surface channel devices have great advantages in high speed and high limit, they have attracted much attention in the high frequency field. Currently commonly used surface channel materials include p-type surface channels formed by hydrogen plasma treatment of diamond, and two-dimensional materials such as graphene, BN, black phosphorus, and two-dimensional GaN. The characteristics of surface channel devices are greatly affected by the surface state. The self-aligned process developed in recent years has effectively solved the above-mentioned problems. However, the self-aligned process can only achieve a device structure with equal spacing between the gate source and the gate drain. In order to take into account the saturation current, the breakdown voltage is generally low. Therefore, it is difficult for the self-aligned process to take into account both the breakdown voltage and the saturation current.
技术问题technical problem
本申请的目的在于提供一种非对称表面沟道场效应晶体管的制备方法，旨在解决现有技术中存在的击穿电压低的技术问题。The purpose of this application is to provide a method for manufacturing an asymmetric surface channel field effect transistor, which aims to solve the technical problem of low breakdown voltage in the prior art.
技术解决方案Technical solution
为实现上述目的，本申请采用的技术方案是：提供一种非对称表面沟道场效应晶体管的制备方法，包括以下步骤：In order to achieve the above objective, the technical solution adopted in this application is to provide a method for manufacturing an asymmetric surface channel field effect transistor, which includes the following steps:
在表面沟道外延层上淀积金属掩膜层；Depositing a metal mask layer on the surface trench epitaxial layer;
在金属掩膜层上制备第一光刻胶层；Preparing a first photoresist layer on the metal mask layer;
曝光、显影，形成源区域图形和漏区域图形；Exposure and development to form source area patterns and drain area patterns;
湿法腐蚀去除所述源区域图形和所述漏区域图形部位的第一光刻胶层；Wet etching to remove the first photoresist layer at the source area pattern and the drain area pattern portion;
在所述源区域图形和所述漏区域图形部位淀积源金属层和漏金属层；Depositing a source metal layer and a drain metal layer on the portion of the source region pattern and the drain region pattern;
在所述金属掩膜层、所述源金属层和所述漏金属层上涂覆第二光刻胶层和第三光刻胶层；Coating a second photoresist layer and a third photoresist layer on the metal mask layer, the source metal layer and the drain metal layer;
在所述源金属层和所述漏金属层之间光刻至少一个栅腐蚀窗口图形和至少一个场板金属窗口图形，并腐蚀对应部位的金属掩膜层；Photoetching at least one gate etching window pattern and at least one field plate metal window pattern between the source metal layer and the drain metal layer, and etching the metal mask layer at the corresponding part;
所述栅腐蚀窗口图形处对应淀积栅金属层，所述场板金属窗口图形处对应淀积场板金属层，所述栅金属层和所述场板金属层不相连；The gate corrosion window pattern corresponds to the deposited gate metal layer, the field plate metal window pattern corresponds to the deposited field plate metal layer, and the gate metal layer and the field plate metal layer are not connected;
其中，所述栅金属层的两侧与对应侧未腐蚀的金属掩膜层的间距不等，所述栅金属层与偏向所述源金属层一侧未腐蚀金属掩膜层的间距为有效栅源间距，所述栅金属层与偏向漏金属层一侧未腐蚀金属掩膜层的间距为有效栅漏间距，有效栅源间距小于有效栅漏间距的器件。Wherein, the distance between the two sides of the gate metal layer and the uncorroded metal mask layer on the corresponding side is not equal, and the distance between the gate metal layer and the uncorroded metal mask layer on the side of the source metal layer is the effective gate Source spacing, the spacing between the gate metal layer and the uncorroded metal mask layer on the side of the drain metal layer is the effective gate-drain spacing, and the effective gate-source spacing is smaller than the effective gate-drain spacing.
进一步地，在所述栅腐蚀窗口图形处淀积栅金属层，所述场板金属窗口图形处淀积场板金属之前：Further, depositing a gate metal layer at the gate etching window pattern, before depositing the field plate metal at the field plate metal window pattern:
所述表面沟道外延层上淀积栅下介质层，所述栅金属层和所述场板金属分别淀积在所述栅下介质层上。An under-gate dielectric layer is deposited on the surface channel epitaxial layer, and the gate metal layer and the field plate metal are respectively deposited on the under-gate dielectric layer.
进一步地，所述栅下介质层为单层介质；Further, the dielectric layer under the gate is a single-layer dielectric;
或者，所述栅下介质层为多层介质。Alternatively, the dielectric layer under the gate is a multilayer dielectric.
进一步地，当所述栅腐蚀窗口图形的数量为两个或两个以上时，所述栅腐蚀窗口图形的结构相同；Further, when the number of the gate etching window patterns is two or more, the structures of the gate etching window patterns are the same;
或者，至少一个所述栅腐蚀窗口图形的结构与其他的所述栅腐蚀窗口图形的结构不同；Alternatively, the structure of at least one of the gate etch window patterns is different from the structure of other gate etch window patterns;
或者，各所述栅腐蚀窗口图形的结构均不相同。Or, the structures of the gate etching window patterns are all different.
进一步地，当所述栅金属层的数量为两个或两个以上时，所述栅金属层的结构为直栅、T型栅、TT型栅、TTT型栅、U型栅和Y型栅中的一种或多种栅组合。Further, when the number of the gate metal layer is two or more, the structure of the gate metal layer is straight gate, T-type gate, TT-type gate, TTT-type gate, U-type gate, and Y-type gate. One or more combinations of gates.
进一步地，所述场板金属窗口图形的数量为两个或两个以上时，所述场板金属窗口图形的结构相同；Further, when the number of the field plate metal window patterns is two or more, the structure of the field plate metal window patterns is the same;
或者，至少一个所述场板金属窗口图形的结构与其他的所述场板金属窗口图形的结构不同；Or, the structure of at least one of the field plate metal window patterns is different from the structure of other field plate metal window patterns;
或者，各所述场板金属窗口图形的结构均不相同。Alternatively, the structures of the metal window patterns of the field plates are all different.
进一步地，所述场板金属层不加电压；Further, no voltage is applied to the metal layer of the field plate;
或者，外加单独电压。Or, apply a separate voltage.
进一步地，所述金属掩膜层与所述源金属层和所述漏金属层的金属类型相同；Further, the metal mask layer has the same metal type as the source metal layer and the drain metal layer;
或者，所述金属掩膜层与所述源金属层和所述漏金属层的金属类型不同。Alternatively, the metal mask layer and the source metal layer and the drain metal layer have different metal types.
进一步地，所述金属掩膜层、所述源金属层、所述漏金属层、所述栅金属层和所述场板金属层均为单层金属；Further, the metal mask layer, the source metal layer, the drain metal layer, the gate metal layer and the field plate metal layer are all a single layer of metal;
或者，均为多层金属；Or, both are multilayer metals;
或者，至少包括一个单层金属和一个多层金属。Or, at least one single-layer metal and one multi-layer metal are included.
本申请另一目的在于提供一种非对称表面沟道场效应晶体管，利用所述的方法制备。Another objective of the present application is to provide an asymmetric surface channel field effect transistor, which is prepared by the method described above.
有益效果Beneficial effect
本申请提供的非对称表面沟道场效应晶体管的制备方法，有效栅源间距与有效栅漏间距不相等，其中有效栅源间距小于有效栅漏间距的器件，可以兼顾饱和电流，有效提高击穿电压和工作电压，提高器件的功率密度。In the method for preparing an asymmetric surface channel field effect transistor provided in the present application, the effective gate-source spacing is not equal to the effective gate-drain spacing, and devices with the effective gate-source spacing smaller than the effective gate-drain spacing can take into account saturation current and effectively increase breakdown voltage And working voltage, improve the power density of the device.
附图说明BRIEF DESCRIPTION
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。In order to more clearly explain the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only for the application For some embodiments, those of ordinary skill in the art can obtain other drawings based on these drawings without creative labor.
图1为本申请实施例提供的非对称表面沟道场效应晶体管的制备方法的制备金属掩膜层的结构示意图；FIG. 1 is a schematic structural diagram of preparing a metal mask layer in a method for preparing an asymmetric surface channel field effect transistor according to an embodiment of the application;
图2为本申请实施例提供的非对称表面沟道场效应晶体管的制备方法的制备第一光刻胶层的结构示意图；2 is a schematic structural diagram of preparing a first photoresist layer in a method for preparing an asymmetric surface channel field effect transistor according to an embodiment of the application;
图3为本申请实施例提供的非对称表面沟道场效应晶体管的制备方法的制备源漏金属层的结构示意图；3 is a schematic diagram of the structure of the source and drain metal layers in the method for preparing an asymmetric surface channel field effect transistor provided by an embodiment of the application;
图4为本申请实施例提供的非对称表面沟道场效应晶体管的制备方法的制备光刻胶层的结构示意图；4 is a schematic structural diagram of preparing a photoresist layer in a method for preparing an asymmetric surface channel field effect transistor provided by an embodiment of the application;
图5为本申请实施例提供的非对称表面沟道场效应晶体管的制备方法的光刻图形的结构示意图；5 is a schematic structural diagram of a photolithographic pattern of a method for manufacturing an asymmetric surface channel field effect transistor provided by an embodiment of the application;
图6为本申请实施例制备的非对称表面沟道场效应晶体管的结构示意图；6 is a schematic structural diagram of an asymmetric surface channel field effect transistor prepared in an embodiment of the application;
图7为本申请实施例制备的非对称表面沟道场效应晶体管的俯视图。FIG. 7 is a top view of an asymmetric surface channel field effect transistor prepared in an embodiment of the application.
其中，图中标记：Among them, the mark in the figure:
1-表面沟道外延层；2-金属掩膜层；3-源金属层；4-第二光刻胶层；5-栅下介质层；6-栅金属层；7-场板金属层；8-漏金属层；9-第三光刻胶层；10-栅腐蚀窗口图形；11-场板金属窗口图形；12-第一光刻胶层。1- surface channel epitaxial layer; 2- metal mask layer; 3- source metal layer; 4- second photoresist layer; 5- gate lower dielectric layer; 6-gate metal layer; 7- field plate metal layer; 8-drain metal layer; 9-third photoresist layer; 10-gate etching window pattern; 11-field plate metal window pattern; 12-first photoresist layer.
本申请的实施方式Implementation of this application
为了使本申请所要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clear, the following describes the present application in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.
请一并参阅图1至图5，现对本申请提供的非对称表面沟道场效应晶体管的制备方法进行说明。所述非对称表面沟道场效应晶体管的制备方法，包括以下步骤：Please refer to FIGS. 1 to 5 together. Now, the method for manufacturing the asymmetric surface channel field effect transistor provided by the present application will be described. The manufacturing method of the asymmetric surface channel field effect transistor includes the following steps:
在表面沟道外延层1上淀积金属掩膜层2，参见图1；A metal mask layer 2 is deposited on the surface trench epitaxial layer 1, see FIG. 1;
在金属掩膜层2上制备第一光刻胶层12，参见图2；A first photoresist layer 12 is prepared on the metal mask layer 2, see FIG. 2;
曝光、显影，形成源区域图形和漏区域图形，参见图2；Expose and develop to form source area patterns and drain area patterns, see Figure 2;
湿法腐蚀去除所述源区域图形和所述漏区域图形部位的第一光刻胶层12，参见图2；Wet etching to remove the first photoresist layer 12 at the source area pattern and the drain area pattern portion, see FIG. 2;
在所述源区域图形和所述漏区域图形部位淀积源金属层3和漏金属层8，参见图3；Depositing a source metal layer 3 and a drain metal layer 8 on the source region pattern and the drain region pattern portion, see FIG. 3;
在所述金属掩膜层2、所述源金属层3和所述漏金属层8上涂覆第二光刻胶层4和第三光刻胶层9，参见图4；Coating a second photoresist layer 4 and a third photoresist layer 9 on the metal mask layer 2, the source metal layer 3 and the drain metal layer 8, see FIG. 4;
在所述源金属层3和所述漏金属层8之间光刻至少一个栅腐蚀窗口图形10和至少一个场板金属窗口图形11，并腐蚀对应部位的金属掩膜层2，参见图5；At least one gate etch window pattern 10 and at least one field plate metal window pattern 11 are photoetched between the source metal layer 3 and the drain metal layer 8, and the metal mask layer 2 at the corresponding part is etched, see FIG. 5;
所述栅腐蚀窗口图形10处对应淀积栅金属层6，所述场板金属窗口图形11处对应淀积场板金属层7，所述栅金属层6和所述场板金属层7不相连，参见图6；The gate corrosion window pattern 10 corresponds to the deposited gate metal layer 6, the field plate metal window pattern 11 corresponds to the deposited field plate metal layer 7, and the gate metal layer 6 and the field plate metal layer 7 are not connected , See Figure 6;
其中，所述栅金属层6的两侧与对应侧未腐蚀的金属掩膜层2的间距不等，所述栅金属层6与偏向所述源金属层3一侧未腐蚀金属掩膜层2的间距为有效栅源间距，所述栅金属层6与偏向漏金属层8一侧未腐蚀金属掩膜层2的间距为有效栅漏间距，即有效栅源间距与有效栅漏间距不相等，有效栅源间距小于有效栅漏间距的器件，参见图6。Wherein, the distances between the two sides of the gate metal layer 6 and the uncorroded metal mask layer 2 on the corresponding side are not equal, and the gate metal layer 6 is opposite to the uncorroded metal mask layer 2 on the side of the source metal layer 3. Is the effective gate-source spacing, the spacing between the gate metal layer 6 and the uncorroded metal mask layer 2 on the side of the drain metal layer 8 is the effective gate-drain spacing, that is, the effective gate-source spacing and the effective gate-drain spacing are not equal, For devices with an effective gate-source spacing smaller than the effective gate-drain spacing, see Figure 6.
本申请提供的非对称表面沟道场效应晶体管的制备方法，与现有技术相比，有效栅源间距与有效栅漏间距不相等，其中有效栅源间距小于有效栅漏间距的器件，兼顾饱和电流，有效提高击穿电压和工作电压，提高器件的功率密度。Compared with the prior art, the method for preparing an asymmetric surface channel field effect transistor provided by the present application has an effective gate-source spacing and an effective gate-drain spacing that are not equal, and a device with an effective gate-source spacing smaller than the effective gate-drain spacing takes into account saturation current , Effectively improve the breakdown voltage and working voltage, and improve the power density of the device.
其中，台面隔离工艺可以在上述的任一步骤之后进行，作用是将本申请制备的器件与其他的部分分隔。Among them, the mesa isolation process can be performed after any of the above steps, and the function is to separate the device prepared in this application from other parts.
请参阅图6，作为本申请提供的非对称表面沟道场效应晶体管的制备方法的一种具体实施方式，在所述栅腐蚀窗口图形10处淀积栅金属层6，所述场板金属窗口图形11处淀积场板金属之前：所述表面沟道外延层1上淀积栅下介质层5，所述栅金属层6和所述场板金属分别淀积在所述栅下介质层5上。也即，栅金属层6和场板金属层7下方可以设有栅下介质层5，参见图6，也可以是栅金属层6和场板金属层7直接制备在表面沟道外延层1上。Please refer to FIG. 6, as a specific embodiment of the method for preparing an asymmetric surface channel field effect transistor provided by the present application, a gate metal layer 6 is deposited at the gate etching window pattern 10, and the field plate metal window pattern Before the field plate metal is deposited at 11 places: the under-gate dielectric layer 5 is deposited on the surface trench epitaxial layer 1, and the gate metal layer 6 and the field plate metal are respectively deposited on the under-gate dielectric layer 5 . That is, the gate metal layer 6 and the field plate metal layer 7 may be provided with a sub-gate dielectric layer 5, see FIG. 6, or the gate metal layer 6 and the field plate metal layer 7 may be directly prepared on the surface channel epitaxial layer 1. .
请参阅图6，作为本申请提供的非对称表面沟道场效应晶体管的制备方法的一种具体实施方式，所述栅下介质层5为单层介质；或者，所述栅下介质层5为多层介质。Please refer to FIG. 6, as a specific embodiment of the method for preparing the asymmetric surface channel field effect transistor provided by the present application, the under-gate dielectric layer 5 is a single-layer dielectric; or, the under-gate dielectric layer 5 is a multi Layer medium.
参阅图5，作为本申请提供的非对称表面沟道场效应晶体管的制备方法的一种具体实施方式，当所述栅腐蚀窗口图形10的数量为两个或两个以上时，所述栅腐蚀窗口图形10的结构相同；或者，至少一个所述栅腐蚀窗口图形10的结构与其他的所述栅腐蚀窗口图形10的结构不同；或者，各所述栅腐蚀窗口图形10的结构均不相同。其中，图5给出的是一个栅腐蚀窗口图形10，也可以同时光刻两个、三个等，这些图形的结构、尺寸可以完全相同也可以不完全相同，根据实际需要而定。Referring to FIG. 5, as a specific embodiment of the method for manufacturing the asymmetric surface channel field effect transistor provided by the present application, when the number of the gate etching window patterns 10 is two or more, the gate etching window The structures of the patterns 10 are the same; or, the structure of at least one of the gate etch window patterns 10 is different from the structure of the other gate etch window patterns 10; or, the structures of the gate etch window patterns 10 are all different. Wherein, FIG. 5 shows a gate etch window pattern 10, and two or three patterns can also be lithographically etched at the same time. The structures and sizes of these patterns may be identical or not identical, depending on actual needs.
作为本申请提供的非对称表面沟道场效应晶体管的制备方法的一种具体实施方式，当所述栅金属层6的数量为两个或两个以上时，所述栅金属层6的结构为直栅、T型栅、TT型栅、TTT型栅、U型栅和Y型栅中的一种或多种栅组合。本实施例图中的栅金属层6为T型栅，参见图6，T型栅有助于兼顾栅寄生电容和栅电阻特性，提高器件频率特性，栅金属层6的结构和数量根据光刻的栅腐蚀窗口图形10的结构和数量而定。As a specific embodiment of the method for preparing the asymmetric surface channel field effect transistor provided by the present application, when the number of the gate metal layer 6 is two or more, the structure of the gate metal layer 6 is straight One or more combinations of gates, T-type gates, TT-type gates, TTT-type gates, U-type gates and Y-type gates. The gate metal layer 6 in the figure of this embodiment is a T-shaped gate. See FIG. 6. The T-shaped gate helps to balance the gate parasitic capacitance and gate resistance characteristics and improve the frequency characteristics of the device. The structure and number of the gate metal layer 6 are based on photolithography. The gate etching window pattern 10 depends on the structure and number.
请参阅图5，作为本申请提供的非对称表面沟道场效应晶体管的制备方法的一种具体实施方式，所述场板金属窗口图形11的数量为两个或两个以上时，所述场板金属窗口图形11的结构相同；或者，至少一个所述场板金属窗口图形11的结构与其他的所述场板金属窗口图形11的结构不同；或者，各所述场板金属窗口图形11的结构均不相同。图5中示出的是一个场板金属窗口图形11，根据实际需要，可以光刻两个、三个、四个等，这些图形的结构可以完全相同，也可以不完全相同，图6中给出的场板金属层7的结构为T型结构。Please refer to FIG. 5, as a specific embodiment of the method for manufacturing the asymmetric surface channel field effect transistor provided by the present application, when the number of the field plate metal window patterns 11 is two or more, the field plate The structure of the metal window patterns 11 is the same; or, the structure of at least one of the field plate metal window patterns 11 is different from the structure of the other field plate metal window patterns 11; or, the structure of each of the field plate metal window patterns 11 All are different. Figure 5 shows a field plate metal window pattern 11. According to actual needs, two, three, four, etc. can be lithographically engraved. The structures of these patterns may be identical or not identical, as shown in Fig. 6 The structure of the field plate metal layer 7 is a T-shaped structure.
其中，作为本申请提供的非对称表面沟道场效应晶体管的制备方法的一种具体实施方式，所述场板金属层7不加电压；或者，外加单独电压。场板金属层7的作用是利于形成非对称结构，另外，可以形成场板结构。Among them, as a specific implementation of the method for manufacturing the asymmetric surface channel field effect transistor provided by the present application, no voltage is applied to the field plate metal layer 7; or, a separate voltage is applied. The role of the field plate metal layer 7 is to facilitate the formation of an asymmetric structure, and in addition, it can form a field plate structure.
请参阅图3，作为本申请提供的非对称表面沟道场效应晶体管的制备方法的一种具体实施方式，所述金属掩膜层2与所述源金属层3和所述漏金属层8的金属类型相同；或者，所述金属掩膜层2与所述源金属层3和所述漏金属层8的金属类型不同。其中，金属掩膜层2、所述源金属层3和所述漏金属层8的金属均为现有半导体器件制备常规使用的金属。Please refer to FIG. 3, as a specific embodiment of the method for preparing the asymmetric surface channel field effect transistor provided by this application, the metal mask layer 2 and the metal of the source metal layer 3 and the drain metal layer 8 The type is the same; or, the metal mask layer 2 and the source metal layer 3 and the drain metal layer 8 have different metal types. The metals of the metal mask layer 2, the source metal layer 3 and the drain metal layer 8 are all metals conventionally used in the preparation of existing semiconductor devices.
请参阅图6，作为本申请提供的非对称表面沟道场效应晶体管的制备方法的一种具体实施方式，所述金属掩膜层2、所述源金属层3、所述漏金属层8、所述栅金属层6和所述场板金属层7均为单层金属；或者，均为多层金属；或者，至少包括一个单层金属和一个多层金属。Please refer to FIG. 6, as a specific embodiment of the method for manufacturing the asymmetric surface channel field effect transistor provided by this application, the metal mask layer 2, the source metal layer 3, the drain metal layer 8, the The gate metal layer 6 and the field plate metal layer 7 are both single-layer metal; or, both are multi-layer metals; or, they include at least one single-layer metal and one multi-layer metal.
作为本申请提供的非对称表面沟道场效应晶体管的制备方法的一种具体实施方式，所述表面沟道外延层1为金刚石p型表面沟道，或者为石墨烯、BN、黑磷、GaN等二维材料，所用衬底为金刚石、SiC、GaN、蓝宝石、Si、Au、石英、SiO2、SiN、铜等材料，或者为多种材料组合的复合衬底。As a specific embodiment of the method for preparing the asymmetric surface channel field effect transistor provided by the present application, the surface channel epitaxial layer 1 is a diamond p-type surface channel, or is graphene, BN, black phosphorus, GaN, etc. Two-dimensional materials, the substrate used is diamond, SiC, GaN, sapphire, Si, Au, quartz, SiO2, SiN, copper, etc., or a composite substrate of a combination of multiple materials.
其中，本实施例采用两层光刻胶层，通过曝光显影形成栅腐蚀窗口图形10和场板金属窗口图形11，可以是一次曝光一次显影，也可以是多次曝光多次显影，其中，每一层光刻胶的层数也可以是两层及以上层数。Among them, in this embodiment, two photoresist layers are used to form the gate corrosion window pattern 10 and the field plate metal window pattern 11 through exposure and development, which can be developed in one exposure or in multiple exposures and multiple developments. The number of layers of a layer of photoresist can also be two or more layers.
其中，在栅金属层6和场板金属层7之后，制备钝化层，对器件进行保护，钝化层为单层或者多层介质。Wherein, after the gate metal layer 6 and the field plate metal layer 7, a passivation layer is prepared to protect the device, and the passivation layer is a single-layer or multi-layer dielectric.
请参阅图6至图7，本申请还提供一种功率器件，利用所述的方法制备。其中，图7中，S代表源金属层3，D代表栅金属层6，G代表漏金属层8。利用上述方法制备的晶体管，栅偏向源，而不是在源漏中间，也即源金属层3和漏金属层8相对于栅金属层6为非对称分布，并在源栅之间或栅漏之间增加场板金属窗口，栅偏向源器件能够兼顾饱和电流，有效提高击穿电压和工作电压，提高器件的功率密度。Please refer to FIG. 6 to FIG. 7, this application also provides a power device manufactured by the method described. Among them, in FIG. 7, S represents the source metal layer 3, D represents the gate metal layer 6, and G represents the drain metal layer 8. In the transistor fabricated by the above method, the gate is biased toward the source instead of between the source and drain, that is, the source metal layer 3 and the drain metal layer 8 are asymmetrically distributed relative to the gate metal layer 6, and are located between the source and gate or between the gate and drain Increase the field plate metal window, the gate bias source device can take into account the saturation current, effectively increase the breakdown voltage and working voltage, and improve the power density of the device.
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。The above are only the preferred embodiments of this application and are not intended to limit this application. Any modification, equivalent replacement and improvement made within the spirit and principle of this application should be included in the protection of this application Within range.

Claims (10)

  1. 非对称表面沟道场效应晶体管的制备方法，其特征在于，包括以下步骤：The method for preparing an asymmetric surface channel field effect transistor is characterized in that it comprises the following steps:
    在表面沟道外延层上淀积金属掩膜层；Depositing a metal mask layer on the surface trench epitaxial layer;
    在金属掩膜层上制备第一光刻胶层；Preparing a first photoresist layer on the metal mask layer;
    曝光、显影，形成源区域图形和漏区域图形；Exposure and development to form source area patterns and drain area patterns;
    湿法腐蚀去除所述源区域图形和所述漏区域图形部位的第一光刻胶层；Wet etching to remove the first photoresist layer at the source area pattern and the drain area pattern portion;
    在所述源区域图形和所述漏区域图形部位淀积源金属层和漏金属层；Depositing a source metal layer and a drain metal layer on the portion of the source region pattern and the drain region pattern;
    在所述金属掩膜层、所述源金属层和所述漏金属层上涂覆第二光刻胶层和第三光刻胶层；Coating a second photoresist layer and a third photoresist layer on the metal mask layer, the source metal layer and the drain metal layer;
    在所述源金属层和所述漏金属层之间光刻至少一个栅腐蚀窗口图形和至少一个场板金属窗口图形，并腐蚀对应部位的金属掩膜层；Photoetching at least one gate etching window pattern and at least one field plate metal window pattern between the source metal layer and the drain metal layer, and etching the metal mask layer at the corresponding part;
    所述栅腐蚀窗口图形处对应淀积栅金属层，所述场板金属窗口图形处对应淀积场板金属层，所述栅金属层和所述场板金属层不相连；The gate corrosion window pattern corresponds to the deposited gate metal layer, the field plate metal window pattern corresponds to the deposited field plate metal layer, and the gate metal layer and the field plate metal layer are not connected;
    其中，所述栅金属层的两侧与对应侧未腐蚀的金属掩膜层的间距不等，所述栅金属层与偏向所述源金属层一侧未腐蚀金属掩膜层的间距为有效栅源间距，所述栅金属层与偏向漏金属层一侧未腐蚀金属掩膜层的间距为有效栅漏间距，所述有效栅源间距小于所述有效栅漏间距的器件。Wherein, the distance between the two sides of the gate metal layer and the uncorroded metal mask layer on the corresponding side is not equal, and the distance between the gate metal layer and the uncorroded metal mask layer on the side of the source metal layer is the effective gate Source spacing, the spacing between the gate metal layer and the uncorroded metal mask layer on the side of the drain metal layer is the effective gate-drain spacing, and the effective gate-source spacing is smaller than the effective gate-drain spacing for devices.
  2. 如权利要求1所述的非对称表面沟道场效应晶体管的制备方法，其特征在于，在所述栅腐蚀窗口图形处淀积栅金属层，所述场板金属窗口图形处淀积场板金属之前：The method for preparing an asymmetric surface channel field effect transistor according to claim 1, wherein a gate metal layer is deposited at the gate etching window pattern, and before the field plate metal is deposited at the field plate metal window pattern :
    所述表面沟道外延层上淀积栅下介质层，所述栅金属层和所述场板金属分别淀积在所述栅下介质层上。An under-gate dielectric layer is deposited on the surface channel epitaxial layer, and the gate metal layer and the field plate metal are respectively deposited on the under-gate dielectric layer.
  3. 如权利要求2所述的非对称表面沟道场效应晶体管的制备方法，其特征在于：所述栅下介质层为单层介质；3. The method for manufacturing an asymmetric surface channel field effect transistor according to claim 2, wherein the under-gate dielectric layer is a single-layer dielectric;
    或者，所述栅下介质层为多层介质。Alternatively, the dielectric layer under the gate is a multilayer dielectric.
  4. 如权利要求1所述的非对称表面沟道场效应晶体管的制备方法，其特征在于：当所述栅腐蚀窗口图形的数量为两个或两个以上时，所述栅腐蚀窗口图形的结构相同；4. The method for manufacturing an asymmetric surface channel field effect transistor according to claim 1, wherein when the number of gate etching window patterns is two or more, the structures of the gate etching window patterns are the same;
    或者，至少一个所述栅腐蚀窗口图形的结构与其他的所述栅腐蚀窗口图形的结构不同；Alternatively, the structure of at least one of the gate etch window patterns is different from the structure of other gate etch window patterns;
    或者，各所述栅腐蚀窗口图形的结构均不相同。Or, the structures of the gate etching window patterns are all different.
  5. 如权利要求4所述的非对称表面沟道场效应晶体管的制备方法，其特征在于：当所述栅金属层的数量为两个或两个以上时，所述栅金属层的结构为直栅、T型栅、TT型栅、TTT型栅、U型栅和Y型栅中的一种或多种栅组合。4. The method for manufacturing an asymmetric surface channel field effect transistor according to claim 4, wherein when the number of the gate metal layer is two or more, the structure of the gate metal layer is a straight gate, One or more combinations of T-type gates, TT-type gates, TTT-type gates, U-type gates and Y-type gates.
  6. 如权利要求1-5任一项所述的非对称表面沟道场效应晶体管的制备方法，其特征在于：所述场板金属窗口图形的数量为两个或两个以上时，所述场板金属窗口图形的结构相同；The method for manufacturing an asymmetric surface channel field effect transistor according to any one of claims 1-5, wherein when the number of the field plate metal window patterns is two or more, the field plate metal The structure of the window graphics is the same;
    或者，至少一个所述场板金属窗口图形的结构与其他的所述场板金属窗口图形的结构不同；Or, the structure of at least one of the field plate metal window patterns is different from the structure of other field plate metal window patterns;
    或者，各所述场板金属窗口图形的结构均不相同。Alternatively, the structures of the metal window patterns of the field plates are all different.
  7. 如权利要求6所述的非对称表面沟道场效应晶体管的制备方法，其特征在于：所述场板金属层不加电压；7. The method for manufacturing an asymmetric surface channel field effect transistor according to claim 6, wherein no voltage is applied to the metal layer of the field plate;
    或者，外加单独电压。Or, apply a separate voltage.
  8. 如权利要求1所述的非对称表面沟道场效应晶体管的制备方法，其特征在于：所述金属掩膜层与所述源金属层和所述漏金属层的金属类型相同；4. The method for manufacturing an asymmetric surface channel field effect transistor according to claim 1, wherein the metal mask layer is the same metal type as the source metal layer and the drain metal layer;
    或者，所述金属掩膜层与所述源金属层和所述漏金属层的金属类型不同。Alternatively, the metal mask layer and the source metal layer and the drain metal layer have different metal types.
  9. 如权利要求1所述的非对称表面沟道场效应晶体管的制备方法，其特征在于：所述金属掩膜层、所述源金属层、所述漏金属层、所述栅金属层和所述场板金属层均为单层金属；4. The method for manufacturing an asymmetric surface channel field effect transistor according to claim 1, wherein the metal mask layer, the source metal layer, the drain metal layer, the gate metal layer and the field The sheet metal layers are all single-layer metal;
    或者，均为多层金属；Or, both are multilayer metals;
    或者，至少包括一个单层金属和一个多层金属。Or, at least one single-layer metal and one multi-layer metal are included.
  10. 功率器件，其特征在于：利用如权利要求1-9任一项所述的方法制备。The power device is characterized by being prepared by the method according to any one of claims 1-9.
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