WO2020143521A1 - 数字音频信号的采样频率的检测方法及装置 - Google Patents

数字音频信号的采样频率的检测方法及装置 Download PDF

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WO2020143521A1
WO2020143521A1 PCT/CN2020/070061 CN2020070061W WO2020143521A1 WO 2020143521 A1 WO2020143521 A1 WO 2020143521A1 CN 2020070061 W CN2020070061 W CN 2020070061W WO 2020143521 A1 WO2020143521 A1 WO 2020143521A1
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clock signal
frequency
reference clock
sampling rate
sampling
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PCT/CN2020/070061
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English (en)
French (fr)
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蒋松鹰
姚炜
管少钧
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上海艾为电子技术股份有限公司
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
    • G01R23/10—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage by converting frequency into a train of pulses, which are then counted, i.e. converting the signal into a square wave
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
    • G01R23/15—Indicating that frequency of pulses is either above or below a predetermined value or within or outside a predetermined range of values, by making use of non-linear or digital elements (indicating that pulse width is above or below a certain limit)

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  • the invention relates to the technical field of integrated circuits, in particular to a method and device for detecting the sampling frequency of digital audio signals.
  • the audio amplifier chip plays the role of receiving digital audio signals sent by music software and controlling the speakers to play the corresponding audio.
  • Music software usually supports multiple audio formats, and the sampling frequencies of audio signals corresponding to different audio formats are also different.
  • the software needs to configure a theoretical sampling frequency matching the sampling frequency of the actually transmitted audio signal.
  • the theoretical sampling frequency does not match the sampling frequency of the actually transmitted audio signal At this time, the audio amplifier chip is prone to damage.
  • the present invention proposes a method and device for detecting the sampling frequency of digital audio signals to prevent the audio amplifier chip from being damaged when the sampling frequency of the software configuration is wrong.
  • the first aspect of the present application provides a method for detecting a sampling frequency of a digital audio signal, including:
  • the judgment result indicates that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency, the judgment result is output.
  • the method before calculating the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal, the method further includes:
  • the method before calculating the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal, the method further includes:
  • the calculating the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal includes:
  • the judging whether the sampling frequency of the digital audio signal matches the pre-configured theoretical sampling frequency to obtain a judgment result includes:
  • the absolute value of the difference is greater than or equal to the threshold, it is determined that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency; if the absolute value of the difference is less than the threshold, then It is determined that the sampling frequency of the digital audio signal matches the theoretical sampling frequency.
  • the second aspect of the present application provides a detection device for a sampling frequency of a digital audio signal, including:
  • a calculation unit configured to acquire a reference clock signal and a sampling rate clock signal, and calculate the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal;
  • the comparison unit is used to calculate the sampling frequency of the digital audio signal according to the number of pulses and the frequency of the reference clock signal, and determine whether the sampling frequency of the digital audio signal matches the pre-configured theoretical sampling frequency to obtain a judgment As a result, if the judgment result indicates that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency, the judgment result is output.
  • the counting unit is used to obtain the reference clock signal and the sampling rate clock signal, and calculate the pulse number of the sampling rate clock signal within one cycle of the reference clock signal;
  • the latch unit is used to store the calculated pulse number.
  • the calculation unit includes:
  • the counting unit is used to obtain a reference clock signal and a sampling rate clock signal, and calculate the total number of pulses of the sampling rate clock signal in N cycles of the reference clock signal, where N is a preset positive integer;
  • a counting and averaging unit is used to obtain the total number of pulses, and divide the total number of pulses by N to obtain the number of pulses of the sampling rate clock signal within one cycle of the reference clock signal.
  • the device further includes:
  • a frequency divider configured to obtain the reference clock signal and divide the reference clock signal to obtain a reference clock signal whose frequency is less than the frequency of the sampling rate clock signal
  • the reference clock signal acquired by the calculation unit is: a reference clock signal whose frequency is less than the frequency of the sampling rate clock signal obtained by the frequency divider.
  • the device further includes:
  • a synchronization unit configured to obtain a reference clock signal and a sampling rate clock signal, and adjust the reference clock signal to obtain a reference clock signal synchronized with the sampling rate clock signal;
  • the invention provides a method and a device for detecting the sampling frequency of a digital audio signal, which uses a reference clock signal and a sampling rate clock signal of a digital audio signal to detect the sampling frequency of the digital audio signal.
  • the output of the detection result can enable the software to adjust the sampling frequency of the digital audio signal in time or adjust the theoretical sampling frequency, which can prevent the audio amplification chip
  • the damage occurs when the sampling frequency of the software configuration is wrong.
  • FIG. 1 is a schematic flowchart of a method for detecting a sampling frequency of a digital audio signal disclosed in an embodiment of the present invention
  • FIG. 2 is a schematic flowchart of a method for detecting a sampling frequency of a digital audio signal disclosed in another embodiment of the present invention
  • FIG. 4 is a schematic diagram of a device for detecting a sampling frequency of a digital audio signal disclosed in another embodiment of the present invention.
  • the reference clock signal is a clock signal whose frequency is known and stable.
  • the reference clock signal should be a clock signal whose frequency is less than the frequency of the sampling rate clock signal, or should be a slow clock signal relative to the sampling rate clock signal .
  • the reference clock signal is a clock signal synchronized with the sampling rate clock signal.
  • the sampling frequency of the digital audio signal is generally between 8KHz and 48KHz, therefore, the reference clock signal may be a 1KHz clock signal.
  • sampling rate clock signal is a clock signal transmitted to the audio amplification chip together with the digital audio signal, and the frequency of the sampling rate clock signal is the sampling frequency of the digital audio signal, or, The frequency of the sampling rate clock signal is always equal to the sampling frequency of the digital audio signal.
  • the synchronization of the reference clock signal and the sampling rate clock signal means that one rising edge of each reference clock corresponds exactly to the rising edge of one sampling rate clock. It is not difficult to understand that the frequency of the reference clock signal and the sampling rate clock signal may be different.
  • the calculated pulse number of the sampling rate clock signal in one cycle of the reference clock signal may be regarded as a ratio of the frequency of the sampling rate clock signal to the frequency of the reference clock signal.
  • S103 Calculate the sampling frequency of the digital audio signal according to the number of pulses and the frequency of the reference clock signal.
  • step S103 actually calculates the sampling rate clock signal frequency.
  • sampling frequency is the sampling frequency configured by the software.
  • the judgment whether the sampling frequency of the digital audio signal (which can also be understood as the actual sampling frequency) matches the pre-configured theoretical sampling frequency can be strictly judged whether the actual sampling frequency is equal to the theoretical sampling frequency, if If they are not equal, it is considered that the two frequencies do not match, or an error range can be set. If the error between the actual sampling frequency and the theoretical sampling frequency is within the range, the two frequencies are considered to match. Frequencies do not match.
  • the method for detecting the sampling frequency of a digital audio signal calculates the sampling frequency of the digital audio signal using a reference clock signal and a sampling rate clock signal of the digital audio signal, thereby realizing the sampling frequency of the digital audio signal Real-time detection of, when the detected sampling frequency of the digital audio signal does not match the preset theoretical sampling frequency, the detection result is output, so that the control software can timely adjust the sampling frequency of the digital audio signal or adjust the theory Sampling frequency. Therefore, the method provided by the embodiments of the present application can output the detection result when the sampling frequency of the digital audio signal does not match the pre-configured theoretical sampling frequency, thereby preventing the audio amplifier chip from being damaged when the sampling frequency of the software configuration is wrong effect.
  • Another embodiment of the present application also provides a method for detecting the sampling frequency of a digital audio signal, please refer to FIG. 2, the method includes the following steps:
  • the embodiment of the present application does not require an initial reference clock signal to be acquired, that is to say, the initial reference clock signal acquired in step S201 of the embodiment of the present application may be relative to all
  • the fast clock signal of the sampling rate clock signal that is, the clock signal having a frequency greater than the frequency of the sampling rate clock signal, may not be synchronized with the sampling rate clock signal.
  • the initial reference clock signal obtained in this embodiment of the present application is usually a standard clock signal of an audio playback device integrated with the digital audio amplifier chip, and the frequency of the standard clock signal is relatively high, usually 1 MHz, which is much higher than
  • the common sampling frequency range of digital audio signals ie 8KHz to 48KHz
  • the phase of the standard clock signal is fixed after the audio playback device is started, so it is usually not synchronized with the sampling rate clock signal of the digital audio signal .
  • the first reference clock signal is a reference clock signal obtained by dividing the initial reference clock signal and having a frequency less than the frequency of the sampling rate clock signal.
  • the frequency division processing of the initial reference clock signal is implemented by a frequency divider, that is, the initial reference clock signal is input to the frequency divider, and after the frequency divider processing, the first Reference clock signal.
  • the frequency division processing of the initial reference clock signal to obtain a reference clock signal whose frequency is less than the frequency of the sampling rate clock signal may be considered to be a frequency higher than a preset frequency (or a preset threshold)
  • the reference clock signal is divided by frequency to obtain a reference clock signal whose frequency is a preset frequency (ie, the first reference clock signal), where the preset frequency is less than the frequency of the sampling rate clock signal.
  • the initial reference clock signal with a frequency greater than 1 KHz may be divided to obtain a first reference clock signal with a frequency of 1 KHz.
  • the frequency of the input initial reference clock signal is less than or equal to 1 KHz, no frequency division processing is performed.
  • the above step of determining whether the input initial reference clock signal is less than the preset frequency is actually realized automatically by the frequency divider, or in other words, when the frequency divider is working, the input signal will be automatically performed according to the preset frequency For screening, only the signal with a frequency greater than the preset frequency is subjected to frequency division processing.
  • the above-mentioned preset frequency may also be other values greater than 1 KHz or less than 1 KHz, as long as the preset frequency is lower than or equal to the lower limit of the sampling frequency range of the digital audio signal to be detected.
  • the sampling frequency is usually between 8KHz and 48KHz, so the preset sampling frequency may be less than or equal to 8KHz.
  • it is recommended to set the preset frequency to the sampling frequency range The lower limit of is kept at a certain difference. For example, for a sampling frequency in the range of 8KHz to 48KHz, it is recommended to make the preset frequency less than or equal to 5KHz.
  • the second reference clock signal is a reference clock signal synchronized with the sampling rate clock signal.
  • the synchronization of the second reference clock signal and the sampling rate clock signal means that when the second reference clock signal transitions from low level to high level, the sampling rate clock signal also changes from low level Jump to a high level, or each rising edge of the second reference clock signal simultaneously corresponds to a rising edge of the sampling rate clock signal.
  • steps S202 and S203 are not necessary for implementing the detection method provided by the present invention.
  • steps S202 and S203 may not Execution, and the initial reference clock signal is directly used as the second reference clock signal.
  • step S202 and step S203 the scope of application of the frequency detection method provided by the embodiment of the present application can be expanded, so that the reference clock signal with a sufficiently low frequency and synchronized with the sampling rate clock signal cannot be obtained in the embodiment of the present application It can also work normally when the real-time detection of the sampling frequency of digital audio signals is completed.
  • the N is a preset positive integer.
  • the N may be set to 32 or 64, or may be set to other positive integers.
  • Steps S204 and S205 can be understood as averaging the total number of pulses of the sampling rate clock signal in multiple cycles of the second reference clock signal, and using the obtained average value as the sampling rate clock signal in the first The number of pulses in one cycle of the reference clock signal.
  • step S204 and step S205 are optional. Steps S204 and S205 are performed because there is a certain error in the second reference clock signal, or there may be fluctuations, so the total number of pulses in multiple cycles is averaged to calculate the number of pulses in one cycle to Avoid misjudgment due to fluctuations in the second reference clock signal. If the second reference clock signal fluctuates to a low degree, does not generate or does not generate misjudgments frequently, or allows misjudgments to occur during the execution of the method, then step S204 and step S205 may not be performed and a sample rate clock signal may be directly counted The number of pulses in a cycle is sufficient, instead of averaging the total number of pulses in multiple cycles.
  • the calculation of the pulse number of the sampling rate clock signal within one cycle of the second reference clock signal can also be considered as the calculation of the sampling rate after the second reference clock signal has passed one cycle
  • the number of cycles elapsed by the clock signal that is, the calculated pulse number of the sampling rate clock signal within one cycle of the second reference clock signal can be considered as the frequency of the sampling rate clock signal and the second reference The ratio of the frequency of the clock signal.
  • S206 Calculate the sampling frequency of the digital audio signal according to the number of pulses and the frequency of the second reference clock signal.
  • step S206 may be: multiplying the number of pulses by the frequency of the second reference clock signal, and the result obtained is the frequency of the sampling rate clock signal, that is, the number The sampling frequency of the audio signal (or the actual sampling frequency).
  • the theoretical sampling frequency is a sampling frequency obtained after the sampling rate decoding unit decodes the sampling rate code, and the sampling rate code is pre-configured by software through a register.
  • the absolute value of the difference is greater than or equal to the threshold, it is determined that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency; if the absolute value of the difference is less than the threshold, then It is determined that the sampling frequency of the digital audio signal matches the theoretical sampling frequency.
  • the threshold may be set to 50 Hz or other values, and the recommended value range is 0 Hz to 100 Hz.
  • the method provided by the embodiment of the present application on the basis of real-time detection of the sampling frequency of the digital audio signal, extends the scope of application of the method provided by the embodiment of the present application by adding steps S202 and S203, and utilizes the statistical reference
  • the method of sampling the total pulse number of the clock signal in multiple cycles of the clock signal and then averaging effectively avoids the misjudgment caused by the fluctuation of the reference clock signal.
  • the device includes:
  • the calculating unit 301 is configured to acquire a reference clock signal and a sampling rate clock signal, and calculate the pulse number of the sampling rate clock signal within one cycle of the reference clock signal.
  • the frequency of the reference clock signal is less than the frequency of the sampling rate clock signal, and the reference clock signal and the sampling rate clock signal are synchronized.
  • the comparing unit 302 is used to calculate the sampling frequency of the digital audio signal according to the number of pulses and the frequency of the reference clock signal, and determine whether the sampling frequency of the digital audio signal matches the pre-configured theoretical sampling frequency to obtain Judgment result, if the judgment result indicates that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency, the judgment result is output.
  • the calculation unit 301 and the comparison unit 302 calculate the sampling rate of the digital audio signal according to the frequency of the reference clock signal, that is, the sampling frequency of the digital audio signal, and then the comparison unit 302 determines Whether the sampling frequency of the digital audio signal matches the theoretical sampling frequency pre-configured by the software, and outputs a judgment result when the two frequencies do not match, so that the software can adjust the sampling frequency of the digital audio signal in time, or modify the theoretical sampling frequency, Thereby, real-time detection of the sampling frequency of the digital audio signal is realized, and the damage of the audio amplification chip caused by the mismatch of the sampling frequency of the digital audio signal and the theoretical sampling frequency is effectively avoided.
  • An embodiment of the present application further provides a device for detecting the sampling frequency of a digital audio signal, please refer to FIG. 4, the device includes:
  • the frequency divider 401 is used to obtain the reference clock signal OSC, and divide the reference clock signal OSC to obtain a reference clock signal CLK_REF (denoted as a first reference signal) whose frequency is less than the frequency of the sampling rate clock signal.
  • the synchronization unit 402 is used to obtain the reference clock signal CLK_REF and the sampling rate clock signal WCK whose frequency output from the frequency divider 401 is less than the sampling rate clock signal, and adjust the reference clock signal CLK_REF to obtain a reference synchronized with the sampling rate clock signal WCK Clock signal CLK_REF_SYNC (denoted as synchronization reference signal).
  • the synchronization unit 402 can be implemented by flip-flops, such as T flip-flops and D flip-flops.
  • the frequency divider 401 and the synchronization unit 402 are optional. If the frequency of the reference clock signal OSC is less than the sampling rate clock signal WCK, and the reference clock signal OSC is a signal synchronized with the sampling rate clock signal WCK, the reference clock signal OSC can be directly input without being processed by the frequency divider 401 and the synchronization unit 402 Calculation unit 403.
  • the calculation unit 403 is configured to acquire the reference clock signal CLK_REF_SYNC and the sampling rate clock signal WCK output by the synchronization unit 402, and calculate the number of pulses of the sampling rate clock signal WCK within one cycle of the reference clock signal CLK_REF_SYNC.
  • the calculation unit 403 may use a counter with synchronization enabling and latching functions, and may also use a shift register and a device with latching functions.
  • the calculation unit 403 includes:
  • the counting unit is used to acquire the reference clock signal and the sampling rate clock signal, and calculate the pulse number of the sampling rate clock signal within one cycle of the reference clock signal.
  • the latch unit is used to store the calculated pulse number.
  • the calculation unit 403 includes:
  • the counting unit is used to obtain a reference clock signal and a sampling rate clock signal, and to count the total number of pulses of the sampling rate clock signal in N cycles of the reference clock signal, where N is a preset positive integer.
  • the latch unit is used to store the calculated pulse number.
  • the counting and averaging unit is used to obtain the total pulse number and divide the total pulse number by N to obtain the pulse number of the sampling rate clock signal within one cycle of the reference clock signal WCK_AVG[5:0]( Recorded as the average number of pulses).
  • the counting and averaging unit is generally implemented by a shifted adder.
  • the comparing unit 404 is used to calculate the sampling frequency of the digital audio signal according to the number of pulses and the frequency of the reference clock signal, and determine whether the sampling frequency of the digital audio signal matches the pre-configured theoretical sampling frequency to obtain Judgment result, if the judgment result indicates that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency, the judgment result is output.
  • the comparison unit 404 can basically be implemented by a comparator with a calculation function, or a combination of a calculator and an XOR gate array.
  • the working principle of the comparison unit 404 is to calculate the sampling frequency of the digital audio signal according to the frequency of the reference clock signal and the number of pulses input by the calculation unit 403, and then calculate the digital audio signal The difference between the sampling frequency and the theoretical sampling frequency, and comparing the absolute value of the difference with a preset threshold, if the absolute value of the difference is less than or equal to the threshold, the sampling frequency of the digital audio signal is determined Matches the theoretical frequency, otherwise, it is determined that the sampling frequency of the digital audio signal does not match the theoretical frequency, and if it is determined that the sampling frequency of the digital audio signal does not match the theoretical sampling frequency, the judgment is output result.
  • the device further includes:
  • the sampling rate decoding unit 405 is used to decode the sampling rate code I2SSR[3:0] pre-configured by the software through the register to obtain the theoretical sampling frequency SR_CODE[5:0].
  • the sampling rate decoding unit 405 is connected to the comparison unit 404, and sends the decoded theoretical sampling frequency SR_CODE[5:0] to the comparison unit 404.
  • sampling rate decoding unit may be a sampling decoder.
  • the device provided by the embodiment of the present application effectively expands the scope of application of the device provided by the embodiment of the present application on the basis of effectively detecting the sampling frequency of the digital audio signal in real time, by adding a frequency divider and a synchronization unit before the computing unit
  • a counting and averaging unit is provided in the calculation unit to average the total number of pulses in multiple cycles of the reference clock signal to obtain the number of pulses in one cycle of the reference clock signal, thereby avoiding Misjudgment caused by reference clock signal fluctuations.

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Abstract

一种数字音频信号的采样频率的检测方法及装置，所述方法利用参考时钟信号和数字音频信号的采样率时钟信号对所述数字音频信号的采样频率进行检测，当检测到的所述数字音频信号的采样频率与预设的理论采样频率不匹配时，输出检测结果，使得软件能够及时调节所述数字音频信号的采样频率或调节所述理论采样频率，从而达到防止音频放大芯片在软件配置采样频率错误时发生损坏的效果。

Description

数字音频信号的采样频率的检测方法及装置
本申请要求于2019年01月09日提交中国专利局、申请号为201910020489.1、申请名称为“数字音频信号的采样频率的检测方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及集成电路技术领域，特别涉及一种数字音频信号的采样频率的检测方法及装置。
背景技术
随着个人电脑的普及，越来越多的用户使用电脑上的音乐软件以及外设的音频播放设备播放音乐。音频放大芯片作为播放设备的重要部件，起到接收音乐软件发送的数字音频信号，并控制喇叭播放对应音频的作用。
音乐软件通常都支持多种音频格式，不同的音频格式对应的音频信号的采样频率也不同。音频放大芯片工作时，需要软件为其配置一个与实际传输的音频信号的采样频率相匹配的理论采样频率，当软件配置错误，使得所述理论采样频率与实际传输的音频信号的采样频率不匹配时，音频放大芯片容易发生损坏。
申请内容
基于上述现有技术的不足，本发明提出一种数字音频信号的采样频率的检测方法及装置，以防止音频放大芯片在软件配置采样频率错误时发生损坏。
为解决上述问题，现提出的方案如下：
本申请第一方面提供了一种数字音频信号的采样频率的检测方法，包括：
获取参考时钟信号和采样率时钟信号；
计算所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数；
根据所述脉冲数和所述参考时钟信号的频率，计算所述数字音频信号的采样频率；
判断所述数字音频信号的采样频率与预先配置的理论采样频率是否匹配，得到判断结果；
若所述判断结果表明所述数字音频信号的采样频率与所述理论采样频率不匹配，则输出所述判断结果。
可选的，所述计算所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数之前，还包括：
对所述参考时钟信号进行分频处理，得到频率小于所述采样率时钟信号的频率的参考时钟信号。
可选的，所述计算所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数之前，还包括：
对所述参考时钟信号进行调整，得到与所述采样率时钟信号同步的参考时钟信号。
可选的，所述计算所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数，包括：
计算所述参考时钟信号的N个周期内，所述采样率时钟信号的总脉冲数，所述N是预设的正整数；
用所述总脉冲数除以N，得到所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数。
可选的，所述判断所述数字音频信号的采样频率与预先配置的理论采样频率是否匹配，得到判断结果，包括：
计算所述数字音频信号的采样频率与理论采样频率的差值；
判断所述差值的绝对值是否小于预设的阈值；
其中，若所述差值的绝对值大于或等于所述阈值，则确定所述数字音频信号的采样频率与所述理论采样频率不匹配；若所述差值的绝对值小于所述阈值，则确定所述数字音频信号的采样频率与所述理论采样频率匹配。
本申请第二方面提供了一种数字音频信号的采样频率的检测装置，包括：
计算单元，用于获取参考时钟信号和采样率时钟信号，并计算所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数；
比较单元，用于根据所述脉冲数和所述参考时钟信号的频率计算所述数字音频信号的采样频率，并判断所述数字音频信号的采样频率与预先配置的理论 采样频率是否匹配，得到判断结果，若所述判断结果表明所述数字音频信号的采样频率与所述理论采样频率不匹配，则输出所述判断结果。
可选的，所述计算单元，包括：
计数单元，用于获取参考时钟信号和采样率时钟信号，并计算所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数；
锁存单元，用于保存计算得到的脉冲数。
可选的，所述计算单元，包括：
计数单元，用于获取参考时钟信号和采样率时钟信号，并计算所述参考时钟信号的N个周期内，所述采样率时钟信号的总脉冲数，所述N是预设的正整数；
锁存单元，用于保存计算得到的总脉冲数；
计数平均单元，用于获取所述总脉冲数，并用所述总脉冲数除以N，得到所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数。
可选的，所述装置还包括：
分频器，用于获取所述参考时钟信号，并对所述参考时钟信号进行分频处理，得到频率小于采样率时钟信号的频率的参考时钟信号；
其中，所述计算单元获取的参考时钟信号是：所述分频器得到的频率小于所述采样率时钟信号的频率的参考时钟信号。
可选的，所述装置还包括：
同步单元，用于获取参考时钟信号和采样率时钟信号，并对所述参考时钟信号进行调整，得到与所述采样率时钟信号同步的参考时钟信号；
其中，所述计算单元获取的参考时钟信号是：与所述采样率时钟信号同步的参考时钟信号。
本发明提供了一种数字音频信号的采样频率的检测方法及装置，利用参考时钟信号和数字音频信号的采样率时钟信号，对所述数字音频信号的采样频率进行检测，当检测到的所述数字音频信号的采样频率与预设的理论采样频率不匹配时，输出检测结果，可以使得软件能够及时调节所述数字音频信号的采样频率或调节所述理论采样频率，能够起到防止音频放大芯片在软件配置采样频 率错误时发生损坏的作用。
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为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1是本发明一个实施例公开的数字音频信号的采样频率的检测方法的流程示意图；
图2是本发明另一实施例公开的数字音频信号的采样频率的检测方法的流程示意图；
图3是本发明一个实施例公开的数字音频信号的采样频率的检测装置的示意图；
图4是本发明另一实施例公开的数字音频信号的采样频率的检测装置的示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供的数字音频信号的采样频率的检测方法，请参考图1，包括以下步骤：
S101、获取参考时钟信号和采样率时钟信号。
需要说明的是，在一个可选方案中，所述参考时钟信号是，频率已知且稳定不变的时钟信号。为了实现本申请实施例提供的检测方法，所述参考时钟信号应该是频率小于所述采样率时钟信号的频率的时钟信号，或者说，应该是相对于所述采样率时钟信号的慢速时钟信号。并且，所述参考时钟信号是与所述采样率时钟信号同步的时钟信号。具体的，通常数字音频信号的采样频率在8KHz到48KHz之间，因此，所述参考时钟信号可以是1KHz的时钟信号。
需要说明的是，所述采样率时钟信号，是与数字音频信号一起向音频放大芯片传输的一个时钟信号，所述采样率时钟信号的频率，就是所述数字音频信号的采样频率，或者说，所述采样率时钟信号的频率，总是等于所述数字音频信号的采样频率。
本实施例中，参考时钟信号和采样率时钟信号同步，是指，每一个参考时钟的一个上升沿恰好对应一个采样率时钟的上升沿。不难理解，参考时钟信号和采样率时钟信号的频率是可以不一样的。
S102、计算所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数。
需要说明的是，计算得到的所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数，可以认为是所述采样率时钟信号的频率与所述参考时钟信号的频率的比值。
S103、根据所述脉冲数和所述参考时钟信号的频率，计算所述数字音频信号的采样频率。
需要说明的是，由于所述采样率时钟信号的频率总是等于所述数字音频信号的采样频率，步骤S103中计算所述数字音频信号的采样频率，实际上也是计算所述采样率时钟信号的频率。
S104、判断所述数字音频信号的采样频率与预先配置的理论采样频率是否匹配，得到判断结果。
需要说明的是，所述理论采样频率，就是软件配置的采样频率。
需要说明的是，所述判断数字音频信号的采样频率(也可以理解成实际采样频率)与所述预先配置的理论采样频率是否匹配，可以是严格地判断实际采样频率是否等于理论采样频率，若不相等则认为两个频率不匹配，也可以是设定一个误差范围，若实际采样频率与理论采样频率的误差在所述范围内，则认为两个频率匹配，若在范围外，则认为两个频率不匹配。
S105、若所述判断结果表明所述数字音频信号的采样频率与所述理论采样频率不匹配，则输出所述判断结果。
需要说明的是，所述在判断结果表明实际采样频率与理论采样频率不匹配时输出采样结果，可以采用下述方式实现，当然具体实现方式可以有多种，包 括下述实现方式在内的所有能够达到如步骤S105所述的效果的具体实现方式，都在本申请保护范围内：
第一种方式，若所述实际采样频率与所述理论采样频率匹配，则不输出任何信号，当实际采样频率与理论采样频率不匹配时，向软件输出报警信号。
第二种方式，在所述实际采样频率与所述理论采样频率匹配时，向软件输出信号1，当所述实际采样频率与所述理论采样频率不匹配时，向软件输出信号0，从而向软件表明目前配置的理论采样频率与实际采样频率不匹配。当然也可以在匹配时输出0，不匹配时输出1。
本申请实施例提供的数字音频信号的采样频率的检测方法，利用参考时钟信号和数字音频信号的采样率时钟信号计算所述数字音频信号的采样频率，从而实现对所述数字音频信号的采样频率的实时检测，当检测到的所述数字音频信号的采样频率与预设的理论采样频率不匹配时，输出检测结果，使得控制软件能够及时调节所述数字音频信号的采样频率或调节所述理论采样频率。因此，本申请实施例提供的方法，能够在所述数字音频信号的采样频率与预先配置的理论采样频率不匹配时输出检测结果，起到防止音频放大芯片在软件配置采样频率错误时发生损坏的作用。
本申请另一实施例还提供了一种数字音频信号的采样频率的检测方法，请参考图2，所述方法包括以下步骤：
S201、获取初始参考时钟信号和采样率时钟信号。
需要说明的是，不同于上述实施例，本申请实施例对于获取的初始参考时钟信号不做要求，也就是说，本申请实施例的步骤S201中获取的初始参考时钟信号，可以是相对于所述采样率时钟信号的快速时钟信号，也就是频率大于所述采样率时钟信号的频率的时钟信号，也可以不与所述采样率时钟信号同步。
实际上，本申请实施例获取的初始参考时钟信号，通常是集成了所述数字音频放大芯片的音频播放设备的标准时钟信号，所述标准时钟信号的频率较高，通常为1MHz，远高于数字音频信号常见的采样频率范围(即8KHz到48KHz)，且所述标准时钟信号的相位是所述音频播放设备启动后就固定的，因此通常也不会与数字音频信号的采样率时钟信号同步。
S202、对初始参考时钟信号进行分频处理，得到第一参考时钟信号。
上述第一参考时钟信号为对初始参考时钟信号分频后得到的，频率小于采样率时钟信号的频率的参考时钟信号。
需要说明的是，所述对初始参考时钟信号进行分频处理，是通过分频器实现的，也就是将所述初始参考时钟信号输入分频器，经过分频器处理后，就得到第一参考时钟信号。
所述分频器的结构及其工作原理属于现有技术，此处不再赘述。
需要说明的是，所述对初始参考时钟信号进行分频处理，得到频率小于所述采样率时钟信号的频率的参考时钟信号，可以认为是对频率高于预设频率(或者说预设阈值)的参考时钟信号进行分频处理，得到频率为预设频率的参考时钟信号(即第一参考时钟信号)，其中所述预设频率是小于所述采样率时钟信号的频率。
具体的，可以是对频率大于1KHz的初始参考时钟信号进行分频，得到频率为1KHz的第一参考时钟信号，当输入的初始参考时钟信号频率小于或等于1KHz时，不进行分频处理。上述判断输入的初始参考时钟信号是否小于预设频率的步骤，实际上是由分频器自动实现的，或者说，分频器工作时，会根据所述预设的频率自动对输入的信号进行筛选，仅对筛选出的频率大于所述预设的频率的信号进行分频处理。
需要说明的是，上述预设的频率也可以是大于1KHz或小于1KHz的其他值，只要保证所述预设频率低于或等于需要检测的数字音频信号的采样频率范围的下限即可。例如，对于常见的数字音频信号，其采样频率通常在8KHz到48KHz之间，因此所述预设的采样频率可以小于或等于8KHz。但为了避免采样频率出现波动，并更准确的计算所述采样率时钟信号在所述参考时钟信号的一个周期的脉冲数，推荐在设定所述预设频率时使其与所述采样频率范围的下限保持一定的差值，例如，对于8KHz到48KHz范围内的采样频率，推荐使所述预设频率小于或等于5KHz。
S203、对第一参考时钟信号进行调整，得到第二参考时钟信号。
第二参考时钟信号为与所述采样率时钟信号同步的参考时钟信号。
需要说明的是，所述第二参考时钟信号与采样率时钟信号同步是指，当所 述第二参考时钟信号从低电平跳变至高电平，所述采样率时钟信号也从低电平跳变至高电平，或者说，第二参考时钟信号的每一个上升沿都同时对应一个所述采样率时钟信号的上升沿。
需要说明的是，步骤S202和S203对于实现本发明提供的检测方法并不是必须的。如本申请提供的上一个实施例所述，当获取的初始参考时钟信号相对于所述采样率时钟信号是慢速时钟信号，且与所述采样率时钟信号同步时，步骤S202和S203可以不执行，而直接将初始参考时钟信号作为第二参考时钟信号。当然，也可以只执行S202或S203中的任意一步而不执行另一步，然后将处理后的参考时钟信号作为第二参考时钟信号，只要获取的初始参考时钟信号是满足对应的需要的参考时钟信号即可。
通过增加步骤S202和步骤S203，可以扩宽本申请实施例提供的频率检测方法的适用范围，使本申请实施例可以在无法获取到频率足够低且与所述采样率时钟信号同步的参考时钟信号时也能正常工作，完成对数字音频信号的采样频率的实时检测。
S204、统计第二参考时钟信号的N个周期内，所述采样率时钟信号的总脉冲数。
所述N是预设的正整数。
可选的，所述N可以设置为32或64，也可以设置为其他正整数。
S205、用总脉冲数除以N，得到采样率时钟信号在第二参考时钟信号的一个周期内的脉冲数。
步骤S204和步骤S205可以理解成是，对所述第二参考时钟信号的多个周期内采样率时钟信号的总脉冲数进行平均，将得到的平均值作为所述采样率时钟信号在所述第二参考时钟信号的一个周期内的脉冲数。
需要说明的是，步骤S204和步骤S205是可选的。执行步骤S204和步骤S205是因为，所述第二参考时钟信号存在一定的误差，或者说可能会产生波动，因此通过多个周期内的总脉冲数取平均以计算一个周期内的脉冲数，以避免由于第二参考时钟信号的波动导致的误判。如果第二参考时钟信号波动程度较低，不会产生或不会频繁产生误判，又或者允许方法执行过程中出现误判，那么可以不执行步骤S204和步骤S205，直接统计采样率时钟信号一个周期内的脉冲数 即可，而不必对多个周期内的总脉冲数取平均。
需要说明的是，所述计算采样率时钟信号在第二参考时钟信号的一个周期内的脉冲数，也可以认为是，计算在所述第二参考时钟信号经过了一个周期后，所述采样率时钟信号经过的周期数，也就是说，计算得到的所述第二参考时钟信号一个周期内的采样率时钟信号的脉冲数，可以认为是所述采样率时钟信号的频率与所述第二参考时钟信号的频率的比值。
S206、根据所述脉冲数和第二参考时钟信号的频率，计算所述数字音频信号的采样频率。
需要说明的是，步骤S206的具体实现方式可以是，用所述脉冲数乘以所述第二参考时钟信号的频率，得到的结果即为所述采样率时钟信号的频率，也就是所述数字音频信号的采样频率(或者说实际采样频率)。
S207、计算所述数字音频信号的采样频率与理论采样频率的差值。
需要说明的是，所述理论采样频率是，采样率译码单元对采样率编码进行译码后得到的采样频率，所述采样率编码由软件通过寄存器预先配置。
S208、判断所述差值的绝对值是否小于预设的阈值，得到判断结果。
其中，若所述差值的绝对值大于或等于所述阈值，则确定所述数字音频信号的采样频率与所述理论采样频率不匹配；若所述差值的绝对值小于所述阈值，则确定所述数字音频信号的采样频率与所述理论采样频率匹配。
可选的，所述阈值可以设定为50Hz，也可以设定为其他值，推荐取值范围在0Hz到100Hz。
S209、若判断结果表明数字音频信号的采样频率与理论采样频率不匹配，则输出判断结果。
本申请实施例提供的方法，在实现对数字音频信号的采样频率的实时检测的基础上，通过增设步骤S202和步骤S203扩展了本申请实施例提供的方法的适用范围，并利用统计所述参考时钟信号的多个周期内的采样率时钟信号的总脉冲数然后取平均的方法有效避免了因为参考时钟信号的波动导致的误判。
基于上述数字音频信号的采样频率的检测方法，本申请另一实施例提供了一种数字音频信号的采样频率的采样装置，请参考图3，所述装置包括：
计算单元301，用于获取参考时钟信号和采样率时钟信号，并计算所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数。
需要说明的是，上述参考时钟信号的频率小于采样率时钟信号的频率，并且，参考时钟信号和采样率时钟信号同步。
比较单元302，用于根据所述脉冲数和所述参考时钟信号的频率计算所述数字音频信号的采样频率，并判断所述数字音频信号的采样频率与预先配置的理论采样频率是否匹配，得到判断结果，若所述判断结果表明所述数字音频信号的采样频率与所述理论采样频率不匹配，则输出所述判断结果。
本申请实施例提供的装置的工作原理与上述本申请第一个实施例提供的频率检测方法一致，此处不再赘述。
本申请实施例提供的检测装置中，计算单元301和比较单元302根据参考时钟信号的频率计算出数字音频信号的采样率时钟信号的频率，也就是数字音频信号的采样频率，然后比较单元302判断所述数字音频信号的采样频率和软件预先配置的理论采样频率是否匹配，在两个频率不匹配时输出判断结果，使得软件能够及时调整数字音频信号的采样频率，或者修正所述理论采样频率，从而实现对数字音频信号的采样频率的实时检测，有效避免了数字音频信号的采样频率与所述理论采样频率不匹配导致的音频放大芯片的损坏。
本申请实施例还提供了一种数字音频信号的采样频率的检测装置，请参考图4，所述装置包括：
分频器401，用于获取参考时钟信号OSC，并对参考时钟信号OSC进行分频处理，得到频率小于采样率时钟信号的频率的参考时钟信号CLK_REF(记为第一参考信号)。
同步单元402，用于获取分频器401输出的频率小于采样率时钟信号的参考时钟信号CLK_REF和采样率时钟信号WCK，并对参考时钟信号CLK_REF进行调整，得到与采样率时钟信号WCK同步的参考时钟信号CLK_REF_SYNC(记为同步参考信号)。
其中，同步单元402可以采用触发器来实现，例如T触发器，D触发器等。
需要说明的是，分频器401和同步单元402是可选的。若参考时钟信号OSC 的频率小于采样率时钟信号WCK，且参考时钟信号OSC是与采样率时钟信号WCK同步的信号，则参考时钟信号OSC可以不经过分频器401和同步单元402处理，直接输入计算单元403。
计算单元403，用于获取同步单元402输出的参考时钟信号CLK_REF_SYNC和采样率时钟信号WCK，并计算所述采样率时钟信号WCK在参考时钟信号CLK_REF_SYNC的一个周期内的脉冲数。
其中，计算单元403可以采用带有同步使能和锁存功能的计数器，也可以采用移位寄存器和具有锁存功能的器件。
可选的，本申请的另一实施例中，计算单元403，包括：
计数单元，用于获取参考时钟信号和采样率时钟信号，并计算所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数。
锁存单元，用于保存计算得到的脉冲数。
可选的，本申请的另一实施例中，计算单元403，包括：
计数单元，用于获取参考时钟信号和采样率时钟信号，并统计所述参考时钟信号的N个周期内，所述采样率时钟信号的总脉冲数，所述N是预设的正整数。
锁存单元，用于保存计算得到的脉冲数。
计数平均单元，用于获取所述总脉冲数，并用所述总脉冲数除以N，得到所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数WCK_AVG[5:0](记为平均脉冲数)。
其中，计数平均单元，一般采用移位的加法器来实现。
比较单元404，用于根据所述脉冲数和所述参考时钟信号的频率计算所述数字音频信号的采样频率，并判断所述数字音频信号的采样频率与预先配置的理论采样频率是否匹配，得到判断结果，若所述判断结果表明所述数字音频信号的采样频率与所述理论采样频率不匹配，则输出所述判断结果。
其中，比较单元404基本上可以采用带有计算功能的比较器，或者计算器与异或门阵列组合来实现。
可选的，本申请的另一实施例中，比较单元404的工作原理是，根据参考时钟信号的频率和计算单元403输入的脉冲数计算数字音频信号的采样频率， 然后计算所述数字音频信号的采样频率和理论采样频率的差值，并对比所述差值的绝对值和预设的阈值，若所述差值的绝对值小于或等于阈值，则判断出所述数字音频信号的采样频率与所述理论频率匹配，否则，判断出所述数字音频信号的采样频率与所述理论频率不匹配，若判断出所述数字音频信号的采样频率和所述理论采样频率不匹配，则输出判断结果。
可选的，本申请另一实施例中，同样还参见图4，所述装置还包括：
采样率译码单元405，用于对软件通过寄存器预先配置的采样率编码I2SSR[3:0]进行译码，得到理论采样频率SR_CODE[5:0]。
其中，采样率译码单元405与比较单元404相连，将译码得到的理论采样频率SR_CODE[5:0]发送至比较单元404。
需要指出的是采样率译码单元可以是采样译码器。
本申请实施例提供的装置，在有效地实时检测数字音频信号的采样频率的基础上，通过在计算单元之前增设分频器和同步单元，有效扩宽了本申请实施例提供的装置的适用范围，同时在所述计算单元中设置计数平均单元，对所述参考时钟信号的多个周期内的总脉冲数进行平均，得到所述参考时钟信号的一个周期内的脉冲数，从而避免由于所述参考时钟信号波动导致的误判。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (13)

  1. 一种数字音频信号的采样频率的检测方法，其特征在于，包括：
    获取参考时钟信号和采样率时钟信号；
    计算所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数；
    根据所述脉冲数和所述参考时钟信号的频率，计算所述数字音频信号的采样频率；
    判断所述数字音频信号的采样频率与预先配置的理论采样频率是否匹配，得到判断结果；
    若所述判断结果表明所述数字音频信号的采样频率与所述理论采样频率不匹配，则输出所述判断结果。
  2. 根据权利要求1所述的方法，其特征在于，所述计算所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数之前，还包括：
    对所述参考时钟信号进行分频处理，得到频率小于所述采样率时钟信号的频率的参考时钟信号。
  3. 根据权利要求1所述的方法，其特征在于，所述计算所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数之前，还包括：
    对所述参考时钟信号进行调整，得到与所述采样率时钟信号同步的参考时钟信号。
  4. 根据权利要求1所述的方法，其特征在于，所述计算所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数，包括：
    计算所述参考时钟信号的N个周期内，所述采样率时钟信号的总脉冲数，所述N是预设的正整数；
    用所述总脉冲数除以N，得到所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数。
  5. 根据权利要求1所述的方法，其特征在于，所述判断所述数字音频信号的采样频率与预先配置的理论采样频率是否匹配，得到判断结果，包括：
    计算所述数字音频信号的采样频率与理论采样频率的差值；
    判断所述差值的绝对值是否小于预设的阈值；
    其中，若所述差值的绝对值大于或等于所述阈值，则确定所述数字音频信 号的采样频率与所述理论采样频率不匹配；若所述差值的绝对值小于所述阈值，则确定所述数字音频信号的采样频率与所述理论采样频率匹配。
  6. 根据权利要求1所述的方法，其特征在于，所述参考时钟信号的频率小于所述采样率时钟信号的频率，且与所述采样率时钟信号同步。
  7. 一种数字音频信号的采样频率的检测装置，其特征在于，包括：
    计算单元，用于获取参考时钟信号和采样率时钟信号，并计算所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数；
    比较单元，用于根据所述脉冲数和所述参考时钟信号的频率计算所述数字音频信号的采样频率，并判断所述数字音频信号的采样频率与预先配置的理论采样频率是否匹配，得到判断结果，若所述判断结果表明所述数字音频信号的采样频率与所述理论采样频率不匹配，则输出所述判断结果。
  8. 根据权利要求7所述的装置，其特征在于，所述计算单元，包括：
    计数单元，用于获取参考时钟信号和采样率时钟信号，并计算所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数；
    锁存单元，用于保存计算得到的脉冲数。
  9. 根据权利要求7所述的装置，其特征在于，所述计算单元，包括：
    计数单元，用于获取参考时钟信号和采样率时钟信号，并计算所述参考时钟信号的N个周期内，所述采样率时钟信号的总脉冲数，所述N是预设的正整数；
    锁存单元，用于保存计算得到的总脉冲数；
    计数平均单元，用于获取所述总脉冲数，并用所述总脉冲数除以N，得到所述采样率时钟信号在所述参考时钟信号的一个周期内的脉冲数。
  10. 根据权利要求7所述的装置，其特征在于，还包括：
    分频器，用于获取所述参考时钟信号，并对所述参考时钟信号进行分频处理，得到频率小于采样率时钟信号的频率的参考时钟信号；
    其中，所述计算单元获取的参考时钟信号是：所述分频器输出的频率小于所述采样率时钟信号的频率的参考时钟信号。
  11. 根据权利要求7所述的装置，其特征在于，还包括：
    同步单元，用于获取参考时钟信号和采样率时钟信号，并对所述参考时钟 信号进行调整，得到与所述采样率时钟信号同步的参考时钟信号；
    其中，所述计算单元获取的参考时钟信号是：所述同步单元输出的与所述采样率时钟信号同步的参考时钟信号。
  12. 根据权利要求7所述的装置，其特征在于，还包括：
    采样率译码单元，用于对预先配置的采样率编码进行译码，得到所述理论采样频率。
  13. 根据权利要求7所述的装置，其特征在于，所述参考时钟信号的频率小于所述采样率时钟信号的频率，且与所述采样率时钟信号同步。
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