WO2020142877A1 - Oled显示结构及电子设备 - Google Patents

Oled显示结构及电子设备 Download PDF

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Publication number
WO2020142877A1
WO2020142877A1 PCT/CN2019/070693 CN2019070693W WO2020142877A1 WO 2020142877 A1 WO2020142877 A1 WO 2020142877A1 CN 2019070693 W CN2019070693 W CN 2019070693W WO 2020142877 A1 WO2020142877 A1 WO 2020142877A1
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Prior art keywords
film transistor
thin film
drain
sub
pixel
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PCT/CN2019/070693
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English (en)
French (fr)
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黄强灿
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深圳市柔宇科技有限公司
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Priority to PCT/CN2019/070693 priority Critical patent/WO2020142877A1/zh
Priority to CN201980073522.5A priority patent/CN113261110B/zh
Priority to US17/421,304 priority patent/US20220109032A1/en
Publication of WO2020142877A1 publication Critical patent/WO2020142877A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • the invention relates to the field of display technology, in particular to an OLED display structure and electronic equipment.
  • the threshold voltage (V th ) of the thin film transistor (TFT) is prone to drift when a positive voltage is applied for a long time.
  • the change in V th will eventually cause the current of the OLED to change.
  • the OLED current of the three colors R/G/B changes with V th
  • the speed is not consistent, and the resulting R/G/B brightness changes are also inconsistent, which may easily lead to the problem of color shift of the OLED display structure.
  • the technical solution of the present invention discloses an OLED display structure and electronic equipment with uniform color development.
  • An OLED display structure includes pixels.
  • the pixels include a first subpixel, a second subpixel, and a third subpixel.
  • the first subpixel includes a first storage capacitor, a first auxiliary capacitor, and a first light-emitting area.
  • the second sub-pixel includes a second storage capacitor, a second auxiliary capacitor, and a second light-emitting area
  • the third sub-pixel includes a third storage capacitor, a third auxiliary capacitor, and a third light-emitting area, which define the first light emission
  • the area of the area is S(1), the area of the second light emitting area is defined as S(2), the area of the third sub light emitting area is defined as S(3), and the capacitance value of the first auxiliary capacitor is defined Is C2(1), the capacitance value of the second auxiliary capacitor is defined as C2(2), and the capacitance value of the third auxiliary capacitor is defined as C2(3), where S(1) ⁇ S(2) ⁇ S (3), and C2(1)>C2(2)>C2(3).
  • An electronic device including the OLED display structure as described above.
  • FIG. 1 is a schematic structural diagram of an OLED display structure in the first embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a 4T2C pixel driving circuit of a sub-pixel of the OLED display structure in the first embodiment of the present invention.
  • FIG 3 is a schematic diagram of another 4T2C pixel driving circuit of a sub-pixel of the OLED display structure in the first embodiment of the present invention.
  • FIG. 4 is a schematic diagram of an electronic device including an OLED display structure in a second embodiment of the invention.
  • FIG. 5 is a schematic diagram of the change speed of the R/G/B OLED current at different V th in the prior art.
  • FIG. 6 is a schematic diagram of the change speed of the OLED current of R/G/B under different V th in the technical solution.
  • the first embodiment of the present technical solution provides an OLED display structure 100.
  • the OLED display structure 100 includes a plurality of pixels 10 (only two pixels 10 are shown in the figure), and each pixel 10 includes a A sub-pixel 11, a second sub-pixel 12, and a third sub-pixel 13.
  • Each sub-pixel includes a storage capacitor, an auxiliary capacitor, and an organic light-emitting diode.
  • Each sub-pixel also has a light-emitting area, wherein the areas of the light-emitting areas of the three sub-pixels are different. Among the three sub-pixels, the larger the area of the light-emitting area The smaller the auxiliary capacitor value.
  • the first sub-pixel 11 includes a first storage capacitor 111, a first auxiliary capacitor 112, and a first organic light-emitting diode (not shown).
  • the diode makes the first sub-pixel 11 have a first light-emitting area 114, or the first organic light-emitting diode is formed in the first light-emitting area 114;
  • the second sub-pixel 12 includes a second storage capacitor 121.
  • the second organic light emitting diode enables the second sub-pixel 12 to have a second light emitting area 124, or the second organic light emitting diode A light emitting diode is formed in the second light emitting region 124;
  • the third sub-pixel 13 includes a third storage capacitor 131, a third auxiliary capacitor 132, and a third organic light emitting diode (not shown), the third organic light emitting The diode enables the third sub-pixel 13 to have a third light emitting area 134, or the third organic light emitting diode is formed in the third light emitting area 134. It can be understood that, in other embodiments, the structure of each sub-pixel is not limited to this embodiment.
  • the area of the first light emitting region 114 of the first sub-pixel 11 is defined as S(1)
  • the area of the second light emitting region 124 of the second sub-pixel 12 is defined as S(2)
  • the area of the third light-emitting area 134 of the pixel 13 is S(3), which defines the capacitance value of the first auxiliary capacitor 112 corresponding to the first sub-pixel 11 as C2(1), which defines the corresponding value of the second sub-pixel 12
  • the capacitance value of the second auxiliary capacitor 122 is C2(2)
  • the capacitance value of the third auxiliary capacitor 132 corresponding to the third sub-pixel 13 is defined as C2(3), then, S(1) ⁇ S(2) ⁇ S(3), and C2(1)>C2(2)>C2(3).
  • the capacitance value of the first storage capacitor 111 corresponding to the first sub-pixel 11 is defined as C1(1)
  • the capacitance value of the first storage capacitor 121 corresponding to the second sub-pixel 12 is defined as C1(2)
  • the capacitance value of the capacitor is adjusted by adjusting the area of the capacitor.
  • the areas of the first, second, and third auxiliary capacitors shown are different, and thus the capacitance values are also different.
  • the area of the first auxiliary capacitor 112 is the largest.
  • the area of the third auxiliary capacitor 132 is the smallest, so that the capacitance value C2(1) of the first auxiliary capacitor 112 is the largest, and the capacitance value C2(3) of the third auxiliary capacitor 132 is the smallest, that is, the first
  • the area of an auxiliary capacitor 112 is larger than the area of the second auxiliary capacitor 122, and the area of the second auxiliary capacitor 122 is larger than the area of the third auxiliary capacitor 132; the first, second, and third storage capacitors 111
  • the shapes of 121, 131 are different, the area is the same, so the capacitance value is the same.
  • the first sub-pixel 11, the second sub-pixel 12 and the third sub-pixel 13 may be three primary color sub-pixels, namely one of red, green and blue sub-pixels.
  • the first sub-pixel 11 is a red sub-pixel
  • the second sub-pixel 12 is a green sub-pixel
  • the third sub-pixel 13 is a blue sub-pixel.
  • Each sub-pixel also includes a plurality of transistors.
  • each sub-pixel includes at least 4 thin film transistors.
  • each sub-pixel includes four thin-film transistors, a storage capacitor, an auxiliary capacitor, and at least one organic light-emitting diode, that is to say, in this embodiment, the pixel driving circuit of each sub-pixel is a 4T2C pixel Drive circuit.
  • the four thin film transistors are a driving thin film transistor and three switching thin film transistors, respectively.
  • the driving thin film transistor includes a gate, a source, and a drain, and the storage capacitor is connected between the gate and drain of the driving thin film transistor.
  • the auxiliary capacitor is connected between an opening thin film transistor and the driving thin film transistor, and the switching thin film transistor can be used to receive a reference voltage; for example, the auxiliary capacitor is connected to the source of the switching thin film transistor Between the drain of the driving thin film transistor or the drain of the switching thin film transistor and the source of the driving thin film transistor.
  • the anode of the organic light emitting diode is electrically connected to the drain of the driving thin film transistor.
  • the thin film transistors of the present technical solution have a top gate structure, that is, the gate is on the upper side of the channel layer, and the source and drain electrodes are on the lower side of the channel layer.
  • a 4T2C pixel driving circuit 20 includes a first switching thin-film transistor SW1, a second switching thin-film transistor SW2, a third switching thin-film transistor SW3, a driving thin-film transistor DR, a storage capacitor C1, a Auxiliary capacitor C2 and an organic light emitting diode OLED.
  • the first, second, and third switching thin film transistors SW1, SW2, and SW3 and the driving thin film transistor DR all include a gate, a drain, and a source.
  • the gate of the first switching thin-film transistor SW1 is used to receive the gate signal Gn-1 of the previous stage
  • the source is used to receive an input signal Int
  • the drain is electrically connected to the node A.
  • the gate of the second switching thin film transistor SW2 is used to receive the gate signal Gn
  • the drain is electrically connected to the gate of the driving thin film transistor DR
  • the source is used to receive a data signal Data, wherein the data signal has a data Voltage.
  • the gate of the third switching thin film transistor SW3 is used to electrically connect the control main line En, the drain is electrically connected to the source of the driving thin film transistor DR, and the drain is electrically connected to a first reference voltage ELVDD.
  • the gate of the driving thin film transistor DR is electrically connected to the drain of the second switching thin film transistor SW2, the drain is electrically connected to the node A, and the source is electrically connected to the source of the third switching thin film transistor SW3 pole.
  • the storage capacitor C1 is connected between the gate and the drain of the driving thin film transistor DR.
  • the auxiliary capacitor C2 is connected between the source of the third switching thin film transistor SW3 and the node A (the drain of the driving thin film transistor DR).
  • the organic light emitting diode OLED includes an anode and a cathode.
  • the anode of the organic light emitting diode OLED is electrically connected to the drain of the driving thin film transistor DR, and the cathode is electrically connected to a second reference voltage ELVSS.
  • a filter capacitor C3 is also connected in parallel between the anode and the cathode of the organic light emitting diode OLED.
  • a 4T2C pixel driving circuit 30 includes a first switching thin film transistor T1, a driving thin film transistor T2, a second switching thin film transistor T3, a third switching thin film transistor T4, a storage capacitor C1, and an auxiliary Capacitor C2 and an organic light emitting diode OLED.
  • the driving thin film transistor T2 and the first, second, and third switching thin film transistors T1, T3, and T4 are all N-type thin film transistors.
  • the gate of the first switching thin film transistor T1 is used to receive a scan signal (Scan), the source is used to receive a data signal Data (the data signal Data represents a data voltage), and the drain is electrically connected to the node G.
  • the gate of the driving thin film transistor T2 is electrically connected to the drain of the first switching thin film transistor T1 and the node G, the drain is electrically connected to the drain of the second switching thin film transistor T3 and the node D, and the drain is electrically connected to the node S.
  • the gate of the second switching thin film transistor T3 receives a switching signal EM, and the source is electrically connected to a first reference voltage OVDD.
  • the gate of the third switching thin film transistor T4 receives a reset signal RESET, the source receives a sustain voltage signal Vsus, and the drain is electrically connected to the node S.
  • the anode of the organic light emitting diode OLED is electrically connected to the node S (the drain of the driving thin film transistor T2), and the cathode is electrically connected to a second reference voltage OVSS, wherein the first reference voltage OVDD is greater than the second reference voltage OVSS.
  • the storage capacitor C1 is connected between the node G (the gate of the driving thin film transistor T2) and the node S (the drain of the driving thin film transistor T2); the auxiliary capacitor C2 is connected across the second switching thin film transistor T3 Between the source and the node S (the drain of the driving thin film transistor T2).
  • each of the sub-pixels may also include five thin-film transistors, and may also include six thin-film transistors, or even more, that is, the pixel driving circuit of the sub-pixel may also be a 5T2C pixel driving circuit, 6T2C pixel drive circuit, etc.
  • the second embodiment of the present technical solution also provides an electronic device 2 that includes the aforementioned OLED display structure 100.
  • the electronic device 2 may be a mobile phone, a tablet computer, an e-book, etc.
  • the R/G/B OLED current changes at different V th are inconsistent, as shown in FIG. 5 (the abscissa is the threshold voltage V th , the unit is volt V, and the ordinate is the current I OLED , The unit is nanoampere nA; the same in Figure 6), especially between 0V and 0.8V, the R/G/B OLED current change speed is obviously different; in the OLED display structure of this technical solution, by setting C2(1 )>C2(2)>C2(3), which can make up for the difference in the OLED current change speed of R/G/B under different V th , as shown in FIG.

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Abstract

本申请公开一种OLED显示结构，包括像素(10)。像素(10)包括第一子像素(11)、第二子像素(12)及第三子像素(13)。第一子像素(11)包括第一存储电容(111)、第一辅助电容(112)及第一发光区域(114)。第二子像素(12)包括第二存储电容(121)、第二辅助电容(122)及第二发光区域(124)。第三子像素(13)包括第三存储电容(131)、第三辅助电容(132)及第三发光区域(134)。定义第一、第二及第三发光区域(114,124,134)的面积分别为S(1)、S(2)及S(3)，第一、第二及第三辅助电容的电容值分别为C2(1)、C2(2)及C2(3)。其中S(1)＜S(2)＜S(3)，且C2(1)＞C2(2)＞C2(3)。本申请的OLED显示结构不易出现色偏问题。

Description

OLED显示结构及电子设备 技术领域
本发明涉及显示技术领域，尤其涉及一种OLED显示结构及电子设备。
背景技术
现有的OLED显示结构中，薄膜晶体管(TFT)的阈值电压(V th)在长时间加正电压的情况下，容易出现漂移现象，V th变化最终将导致OLED的电流发生变化，而对于OLED显示结构的三种颜色红绿蓝(R/G/B)来说，由于R/G/B三种颜色的发光面积不同，R/G/B三种颜色的OLED电流随着V th的变化快慢并不一致，最终体现出来的R/G/B亮度变化快慢也不一致，容易导致OLED显示结构的色偏问题的产生。
发明内容
本发明技术方案揭示一种显色均匀的OLED显示结构及电子设备。
一种OLED显示结构，包括像素，所述像素包括第一子像素、第二子像素及第三子像素，所述第一子像素包括第一存储电容、第一辅助电容及第一发光区域，所述第二子像素包括第二存储电容、第二辅助电容及第二发光区域，所述第三子像素包括第三存储电容、第三辅助电容及第三发光区域，定义所述第一发光区域的面积为S(1)，定义所述第二发光区域的面积为S(2)，定义所述第三子发光区域的面积为S(3)，定义所述第一辅助电容的电容值为C2(1)，定义所述第二辅助电容的电容值为C2(2)，定义所述第三辅助电容的电容值为C2(3)，其中S(1)＜S(2)＜S(3)，且C2(1)＞C2(2)＞C2(3)。
一种电子设备，所述电子设备包括如上述的OLED显示结构。
本发明的OLED显示结构及电子设备中，通过设置C2(1)＞C2(2)＞C2(3)，从而可以弥补不同的V th下的R/G/B的OLED电流变化快慢 差异，从而不易出现色偏问题。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明第一实施例中的OLED显示结构的结构示意图。
图2为本发明第一实施例中的OLED显示结构的一子像素的一种4T2C像素驱动电路示意图。
图3为本发明第一实施例中的OLED显示结构的一子像素的另一种4T2C像素驱动电路示意图。
图4为本发明第二实施例中的包含OLED显示结构的电子设备的示意图。
图5为现有技术中的不同的V th下的R/G/B的OLED电流变化快慢示意图。
图6为本技术方案中的不同的V th下的R/G/B的OLED电流变化快慢示意图。
具体实施方式
下面将结合本发明技术方案实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，本技术方案第一实施例提供一种OLED显示结构100， 所述OLED显示结构100包括有多个像素10(图中仅示出两个像素10)，每个像素10包括第一子像素11、第二子像素12及第三子像素13。
每个子像素均包括存储电容、辅助电容及有机发光二极管，每个子像素还均具有一发光区域，其中，三个子像素的发光区域的面积不同，三个子像素中，发光区域面积越大的子像素的辅助电容值越小。
具体地，如本实施例的图1所示，所述第一子像素11包括第一存储电容111、第一辅助电容112及第一有机发光二极管(图未示)，所述第一有机发光二极管使所述第一子像素11具有一第一发光区域114，或者说，所述第一有机发光二极管形成于所述第一发光区域114中；所述第二子像素12包括第二存储电容121、第二辅助电容122及第二有机发光二极管(图未示)，所述第二有机发光二极管使所述第二子像素12具有一第二发光区域124，或者说，所述第二有机发光二极管形成于所述第二发光区域124中；所述第三子像素13包括第三存储电容131、第三辅助电容132及第三有机发光二极管(图未示)，所述第三有机发光二极管使所述第三子像素13具有一第三发光区域134，或者说，所述第三有机发光二极管形成于所述第三发光区域134中。可以理解，在其他实施例中，所述各子像素的结构并不以本实施例为限。
定义所述第一子像素11的第一发光区域114的面积为S(1)，定义所述第二子像素12的第二发光区域124的面积为S(2)，定义所述第三子像素13的第三发光区域134的面积为S(3)，定义所述第一子像素11对应的第一辅助电容112的电容值为C2(1)，定义所述第二子像素12对应的第二辅助电容122的电容值为C2(2)，定义所述第三子像素13对应的第三辅助电容132的电容值为C2(3)，则，S(1)＜S(2)＜S(3)，且C2(1)＞C2(2)＞C2(3)。
进一步，定义所述第一子像素11对应的第一存储电容111的电容值为C1(1)，定义所述第二子像素12对应的第一存储电容121的电容值为C1(2)，定义所述第三子像素13对应的第一存储电容131的电容值 为C1(3)，则，C1(1)＝C1(2)＝C1(3)。
本实施例中，通过调整电容的面积以调整电容的电容值。
如图1所示，所示第一、第二及第三辅助电容的面积不同，从而电容值也不同，每个像素10的三个子像素中，所述第一辅助电容112的面积最大，所述第三辅助电容132的面积最小，从而，所述第一辅助电容112的电容值C2(1)最大，所述第三辅助电容132的电容值C2(3)最小，也即，所述第一辅助电容112的面积大于所述第二辅助电容122的面积，所述第二辅助电容122的面积大于所述第三辅助电容132的面积；所述第一、第二及第三存储电容111、121、131的形状虽然不同，但面积相同，从而电容值也相同。
所述第一子像素11、第二子像素12及第三子像素13可以分别为三原色子像素，即红色、绿色及蓝色子像素中的一个。
在本实施例中，所述第一子像素11为红色子像素，所述第二子像素12为绿色子像素，所述第三子像素13为蓝色子像素。
每个子像素还包含多个晶体管，优选地，每个子像素均至少包含4个薄膜晶体管。
本实施例中，每个子像素均包括有四个薄膜晶体管、一个存储电容、一个辅助电容及至少一个有机发光二极管，也就是说，本实施例中，每个子像素的像素驱动电路均为4T2C像素驱动电路。
在一实施例中，四个薄膜晶体管分别为一驱动薄膜晶体管及三个开关薄膜晶体管。
在一实施例中，所述驱动薄膜晶体管包括栅极、源极及漏极，所述存储电容连接于所述驱动薄膜晶体管的栅极及漏极之间。
在一实施例中，所述辅助电容连接于一开光薄膜晶体管与该驱动薄膜晶体管之间，该开关薄膜晶体管可用于接收一参考电压；例如，所述辅助电容连接于该开关薄膜晶体管的源极与该驱动薄膜晶体管的漏极之间，或连接于该开关薄膜晶体管的漏极与该驱动薄膜晶体管的源极之间。
在一实施例中，所述有机发光二极管的阳极电性连接于所述驱动薄膜晶体管的漏极。
优选地，本技术方案的薄膜晶体管均为顶栅结构，即栅极在通道层上侧，源、漏电极在通道层下侧。
以下以一实施例中来进行详细的说明一子像素的一种4T2C像素驱动电路：
请参阅图2，一种4T2C像素驱动电路20，包括一第一开关薄膜晶体管SW1、一第二开关薄膜晶体管SW2、一第三开关薄膜晶体管SW3、一驱动薄膜晶体管DR、一存储电容C1、一辅助电容C2及一有机发光二极管OLED。
所述第一、第二、第三开关薄膜晶体管SW1、SW2及SW3及驱动薄膜晶体管DR均包括栅极、漏极及源极。其中，所述第一开关薄膜晶体管SW1的栅极用于接收上一级栅极信号Gn-1，源极用于接收一输入信号Int，漏极电性连接至节点A。所述第二开关薄膜晶体管SW2的栅极用于接收栅极信号Gn，漏极电性连接所述驱动薄膜晶体管DR的栅极，源极用于接收一数据信号Data，其中数据信号具有一数据电压。所述第三开关薄膜晶体管SW3的栅极用于电性连接控制主线En，漏极电性连接所述驱动薄膜晶体管DR的源极，漏极电性连接一第一参考电压ELVDD。所述驱动薄膜晶体管DR的栅极电性连接所述第二开关薄膜晶体管SW2的漏极，漏极电性连接至所述节点A，源极电性连接所述第三开关薄膜晶体管SW3的源极。
所述存储电容C1跨接于所述驱动薄膜晶体管DR的栅极与漏极之间。所述辅助电容C2跨接于所述第三开关薄膜晶体管SW3的源极与节点A(所述驱动薄膜晶体管DR的漏极)之间。
所述有机发光二极管OLED包括阳极及阴极，所述有机发光二极管OLED的阳极电性连接至所述驱动薄膜晶体管DR的漏极，阴极电性连接至一第二参考电压ELVSS。本实施例中，所述有机发光二极管OLED的 阳极与阴极之间还并联有一滤波电容C3。
以下以另一实施例中来进行详细的说明一子像素的另一种4T2C像素驱动电路：
请参阅图3，一4T2C像素驱动电路30，包括一第一开关薄膜晶体管T1、一驱动薄膜晶体管T2、一第二开关薄膜晶体管T3、一第三开关薄膜晶体管T4、一存储电容C1、一辅助电容C2及一有机发光二极管OLED。
在一实施例中，所述驱动薄膜晶体管T2及所述第一、第二、第三开关薄膜晶体管T1、T3、T4均为N型薄膜晶体管。
所述第一开关薄膜晶体管T1的栅极用于接收一扫描信号(Scan)，源极用于接收一数据信号Data(数据信号Data代表一数据电压)，漏极电性连接节点G。驱动薄膜晶体管T2的栅极电性连接至第一开关薄膜晶体管T1的漏极及节点G，漏极电性连接所述第二开关薄膜晶体管T3的漏极与节点D，漏极电性连接节点S。第二开关薄膜晶体管T3的栅极接收一开关信号EM，源极电性连接至一第一参考电压OVDD。第三开关薄膜晶体管T4的栅极接收一复位信号RESET，源极接收一维持电压信号Vsus，漏极电性连接至节点S。
所述有机发光二极管OLED的阳极电性连接至节点S(驱动薄膜晶体管T2的漏极)，阴极电性连接至一第二参考电压OVSS，其中，第一参考电压OVDD大于第二参考电压OVSS。
所述存储电容C1跨接于节点G(驱动薄膜晶体管T2的栅极)与节点S(驱动薄膜晶体管T2的漏极)之间；所述辅助电容C2跨接于所述第二开关薄膜晶体管T3的源极与节点S(驱动薄膜晶体管T2的漏极)之间。
在其他实施例中，各所述子像素也可以包括五个薄膜晶体管，还可以包括六个薄膜晶体管，甚至更多，也即，所述子像素的像素驱动电路也可以为5T2C像素驱动电路、6T2C像素驱动电路等。
请参阅图4，本技术方案第二实施例还提供一种电子设备2，所述电 子设备2包括前述的OLED显示结构100。
其中，所述电子设备2可以为手机、平板电脑、电子书等。
现有技术中的不同的V th下的R/G/B的OLED电流变化快慢不一致，如图5所示的(横坐标为阈值电压V th，单位为伏V，纵坐标为电流I OLED，单位为纳米安培nA；图6亦同)，尤其是在0V至0.8V之间，R/G/B的OLED电流变化快慢明显不一样；本技术方案的OLED显示结构中，通过设置C2(1)＞C2(2)＞C2(3)，从而可以弥补不同的V th下的R/G/B的OLED电流变化快慢差异，如图6所示的，本技术方案的仿真实验中，不同的V th下的R/G/B的OLED电流变化的一致性均较好，在0V至0.8V之间，R/G/B的OLED电流变化快慢也基本一样。从而，本技术方案的OLED显示结构不易出现色偏问题。
以上所述是本发明的优选实施例，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (20)

  1. 一种OLED显示结构，包括像素，所述像素包括第一子像素、第二子像素及第三子像素，所述第一子像素包括第一存储电容、第一辅助电容及第一发光区域，所述第二子像素包括第二存储电容、第二辅助电容及第二发光区域，所述第三子像素包括第三存储电容、第三辅助电容及第三发光区域，定义所述第一发光区域的面积为S(1)，定义所述第二发光区域的面积为S(2)，定义所述第三子发光区域的面积为S(3)，定义所述第一辅助电容的电容值为C2(1)，定义所述第二辅助电容的电容值为C2(2)，定义所述第三辅助电容的电容值为C2(3)，其中S(1)＜S(2)＜S(3)，且C2(1)＞C2(2)＞C2(3)。
  2. 如权利要求1所述的OLED显示结构，其特征在于，所述第一辅助电容的面积大于所述第二辅助电容的面积，所述第二辅助电容的面积大于所述第三辅助电容的面积。
  3. 如权利要求1所述的OLED显示结构，其特征在于，定义所述第一存储电容的电容值为C1(1)，定义所述第二存储电容的电容值为C1(2)，定义所述第三存储电容的电容值为C1(3)，其中C1(1)＝C1(2)＝C1(3)。
  4. 如权利要求3所述的OLED显示结构，其特征在于，所述第一存储电容、所述第二存储电容、所述第三存储电容的面积相同。
  5. 如权利要求4所述的OLED显示结构，其特征在于，所述第一存储电容、所述第二存储电容、所述第三存储电容的形状不同。
  6. 如权利要求1所述的OLED显示结构，其特征在于，所述第一为红色子像素，所述第二子像素为绿色子像素，所述第三子像素为蓝色子像素。
  7. 如权利要求1所述的OLED显示结构，其特征在于，所述第一子像素、所述第二子像素、所述第三子像素均包括有四个薄膜晶体管、一个存储电容、一个辅助电容及至少一个有机发光二极管，其中，所述四个薄膜晶体管的其中一个为驱动薄膜晶体管。
  8. 如权利要求7所述的OLED显示结构，其特征在于，所述驱动薄膜晶体管包括栅极、源极及漏极，所述存储电容连接于所述驱动薄膜晶体管的栅极及漏极之间。
  9. 如权利要求7所述的OLED显示结构，其特征在于，所述辅助电容连接于一开光薄膜晶体管与该驱动薄膜晶体管之间，该开关薄膜晶体管用于接收一参考电压。
  10. 如权利要求9所述的OLED显示结构，其特征在于，所述辅助电容连接于该开关薄膜晶体管的源极与该驱动薄膜晶体管的源极之间，或连接于该开关薄膜晶体管的漏极与该驱动薄膜晶体管的源极之间。
  11. 如权利要求7所述的OLED显示结构，其特征在于，所述有机发光二极管的阳极电性连接于所述驱动薄膜晶体管的漏极。
  12. 如权利要求7所述的OLED显示结构，其特征在于，所述第一子像素、所述第二子像素、所述第三子像素均包括第一开关薄膜晶体管、第二开关薄膜晶体管、第三开关薄膜晶体管、所述驱动薄膜晶体管、所述存储电容、所述辅助电容及所述有机发光二极管；所述第一开关薄膜晶体管、第二开关薄膜晶体管及第三开关薄膜晶体管均包括栅极、漏极及源极；其中，所述第一开关薄膜晶体管的栅极用于接收上一级栅极信号，源极用于接收一输入信号，漏极电性连接至一节点；所述第二开关薄膜晶体管的栅极用于接收栅极信号，源极用于接收一数据信号，漏极电性连接所述驱动薄膜晶体管的栅极，其中数据信号具有一数据电压；所述第三开关薄膜晶体管的栅极用于电性连接控制主线，源极电性连接一第一参考电压，漏极电性连接所述驱动薄膜晶体管的源极；所述驱动薄膜晶体管也包括栅极、漏极及源极，所述驱动薄膜晶体管的栅极电性连接所述第二开关薄膜晶体管的漏极，源极电性连接所述第三开关薄膜晶体管的漏极，漏极电性连接至所述节点。
  13. 如权利要求12所述的OLED显示结构，其特征在于，所述存储电容跨接于所述驱动薄膜晶体管的栅极与漏极之间；所述辅助电容跨接于所述第三开关薄膜晶体管的源极与所述驱动薄膜晶体管DR的漏极之间。
  14. 如权利要求12所述的OLED显示结构，其特征在于，所述有机发光二极管包括阳极及阴极，所述有机发光二极管的阳极电性连接至所述驱动薄膜晶体管的漏极，阴极电性连接至一第二参考电压。
  15. 如权利要求12所述的OLED显示结构，其特征在于，所述有机发光二极管的阳极与阴极之间还并联一滤波电容。
  16. 如权利要求7所述的OLED显示结构，其特征在于，所述第一子像素、所述第二子像素、所述第三子像素均包括第一开关薄膜晶体管、所述驱动薄膜晶体管、第二开关薄膜晶体管、第三开关薄膜晶体管、所述存储电容、所述辅助电容及所述有机发光二极管；所述第一开关薄膜晶体管、驱动薄膜晶体管、第二开关薄膜晶体管及第三开关薄膜晶体管均包括栅极、漏极及源极；所述第一开关薄膜晶体管的栅极用于接收一扫描信号，源极接收一数据信号；驱动薄膜晶体的栅极电性连接至第一开关薄膜晶体管的漏极，并电性连接所述存储电容，源极电性连接所述第二开关薄膜晶体管的漏极；第二开关薄膜晶体管的栅极接收一开关信号，源极电性连接至一第一参考电压；第三开关薄膜晶体管的栅极接收一复位信号，源极接收一维持电压信号，漏极电性连接至驱动薄膜晶体管的漏极。
  17. 如权利要求16所述的OLED显示结构，其特征在于，所述存储电容跨接于所述驱动薄膜晶体管的栅极与漏极之间；所述辅助电容跨接于所述第二开关薄膜晶体管的源极与驱动薄膜晶体管的漏极之间。
  18. 如权利要求16所述的OLED显示结构，其特征在于，所述有机发光二极管包括阳极及阴极，所述有机发光二极管的阳极电性连接至所述驱动薄膜晶体管的漏极，阴极电性连接至一第二参考电压。
  19. 一种电子设备，所述电子设备包括如权利要求1至18任一项所述的OLED显示结构。
  20. 如权利要求19所述的电子设备，其特征在于，所述电子设备为手机、平板电脑、电子书。
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