WO2020140727A1 - Led显示装置 - Google Patents

Led显示装置 Download PDF

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Publication number
WO2020140727A1
WO2020140727A1 PCT/CN2019/125098 CN2019125098W WO2020140727A1 WO 2020140727 A1 WO2020140727 A1 WO 2020140727A1 CN 2019125098 W CN2019125098 W CN 2019125098W WO 2020140727 A1 WO2020140727 A1 WO 2020140727A1
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WO
WIPO (PCT)
Prior art keywords
conductive connection
selected area
connection elements
substrate
led
Prior art date
Application number
PCT/CN2019/125098
Other languages
English (en)
French (fr)
Inventor
曹鹏军
翟明
李沛
王志远
李金鹏
李丹
李健
张腾
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/961,761 priority Critical patent/US11302247B2/en
Publication of WO2020140727A1 publication Critical patent/WO2020140727A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to the field of display technology, and particularly to an LED display device.
  • Light emitting diode (Light Emitting Diode, LED for short) display panel is the core device of the LED display device, wherein the LED display panel includes: a printed circuit board (Printed Circuit Board, PCB board for short), an LED chip packaged on the PCB board and To drive the control device, signal traces need to be designed on the PCB board to provide electrical signals for the positive and negative LEDs.
  • a printed circuit board Printed Circuit Board, PCB board for short
  • LED chip packaged on the PCB board To drive the control device, signal traces need to be designed on the PCB board to provide electrical signals for the positive and negative LEDs.
  • an LED display device including: an LED display substrate and a drive substrate that are oppositely arranged; the LED display substrate includes: a substrate and a plurality of LED chips, the plurality of LED chips are located in the The substrate is away from the side of the drive substrate; the drive substrate includes: a PCB board and a drive control device, the drive control device is located on the PCB board, the drive control device through a plurality of first signal traces and The plurality of LED chips are electrically connected to provide driving signals to each LED chip.
  • the plurality of first signal traces are located on a side of the substrate away from the driving substrate.
  • the LED display substrate further includes a plurality of first conductive connection elements, the plurality of first conductive connection elements are located on the substrate and correspond one-to-one with the plurality of first signal traces Electrical connection;
  • the driving substrate further includes a plurality of second conductive connection elements, the plurality of second conductive connection elements are located on a side of the PCB board facing the substrate, and the plurality of second conductive connection elements Electrically connected to the drive control device; wherein the plurality of second conductive connection elements and the plurality of first conductive connection elements are electrically connected in one-to-one correspondence.
  • the plurality of first conductive connection elements are located on a side of the substrate facing the PCB board, and the LED display substrate further includes a plurality of intermediate conductive connection elements, wherein the plurality of first connection elements The conductive connection elements are electrically connected to the plurality of first signal traces through the plurality of intermediate conductive connection elements, respectively.
  • the plurality of intermediate conductive connection elements include at least one of conductive glue, metal traces, and FPC board.
  • the surface of the substrate facing the side of the PCB includes a first selected area, a second selected area, a third selected area, and a fourth selected area separated from each other , wherein the first selected region, the second selected region, the third selected region, and the fourth selected region all have a uniformly distributed selected number of first conductive connection elements, And the selected number of first conductive connection elements in each selected area are electrically connected to the selected number of first signal traces through the intermediate conductive connection elements, respectively.
  • the first selected area and the second selected area are respectively adjacent to two opposite edges of the surface on which they are located, and the third selected area and the fourth selected area are respectively adjacent The other two edges on the opposite surface.
  • the LED display device further includes a protective adhesive layer, wherein the protective adhesive layer covers the plurality of LED chips, the plurality of first signal traces, and the plurality of intermediate conductive connection elements Part of the substrate located on the side of the substrate away from the PCB board.
  • the PCB board includes a first central region and a first peripheral region surrounding the first central region, and the LED display substrate is located in the first central region of the PCB board.
  • the second conductive connection element is located in the first peripheral area, and the plurality of first conductive connections are electrically connected to the plurality of second conductive connection elements through conductive jumpers, respectively.
  • the LED display substrate includes a second central area and a second peripheral area, the plurality of LED chips are located in the second central area, and the first conductive connection element is located in the second In the peripheral area, wherein the second peripheral area includes a first selected area, a second selected area, a third selected area, and a fourth selected area separated from each other, the first selected area, The second selected area, the third selected area, and the fourth selected area all have a uniformly distributed selected number of first conductive connection elements, and the selected number in each selected area
  • the first conductive connection element is electrically connected to a selected number of first signal traces through conductive jumpers, wherein the first selected area and the second selected area are respectively adjacent to the opposite Two edges, the third selected area and the fourth selected area are respectively adjacent to the other two edges of the surface where they are located.
  • the LED display device further includes a protective adhesive layer, wherein the protective adhesive layer covers the plurality of LED chips, the plurality of first signal traces, and the plurality of first conductive connections Element, the plurality of second conductive connection elements and the conductive jumper.
  • the plurality of first signal traces includes a plurality of first pole signal traces connected to the first poles of the plurality of LED chips, and a second pole connected to the plurality of LED chips Connected multiple second-pole signal traces; all the multiple first-pole signal traces are arranged in the same layer, all the multiple second-pole signal traces are arranged in the same layer, and the multiple first-pole signal traces are arranged in the same layer The wires are arranged in different layers from the plurality of second-pole signal traces.
  • the plurality of LED chips constitute a pixel array
  • the pixel array includes a total of M*N pixel units in M rows and N columns, and the number of LED chips in each of the pixel units is the same and Different LED chips in the same pixel unit emit different colors of light
  • the plurality of first pole signal traces extend along the row direction of the pixel unit
  • the plurality of second pole signal traces extend along the The column direction of the pixel unit extends
  • the first pole of the LED chip in each row of pixel units in the first to m-th row of pixel units of the pixel array is connected to the same first pole signal trace, and is connected to the
  • a plurality of first-pole signal traces connected to the pixel units in the first row to the m-th row of the pixel array are electrically connected to the first conductive connection elements in the first selected area through corresponding connection elements
  • the first pole of the LED chip in each row of pixel units in the m+1th row to the Mth row of pixel units is connected to a
  • a plurality of first-pole signal traces connected to the pixel units in the m+1th row to the Mth row are electrically connected to the first conductive connection elements in the second selected area through corresponding connection elements; the first in the pixel array
  • the second pole of the LED chips emitting the same color light among the LED chips in each column of the pixel units in the pixel unit of the row to the m-th row of pixel units is connected to the same second-pole signal trace and is connected to the first of the pixel array
  • a plurality of second-pole signal traces connected to the pixel units in the row to the m-th row are electrically connected to the first conductive connection element in the third selected area through corresponding connection elements; the m+1th row of the pixel array ⁇ LED chip in the pixel unit of the Mth row pixel unit
  • the second pole of the LED chip in each column of the pixel unit that emits the same color light is connected to the same second pole signal trace, and is connected to the A plurality of second-pole signal traces connected to the
  • m INT(M/2), and INT(M/2) means rounding the value of M/2.
  • the LED chip is an LED flip chip.
  • both the first conductive connection element and the second conductive connection element are pads.
  • the substrate is a glass substrate.
  • FIG. 1 is a schematic cross-sectional view of a display device provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view of a display device provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional view of a display device provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic cross-sectional view of a display device provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of an arrangement of the first conductive connection element and the second conductive connection element in the display device shown in FIG. 4;
  • FIG. 6 is a schematic diagram of an arrangement of LED chips and first-pole signal traces provided by an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of an arrangement of LED chips and second-pole signal traces provided by an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of an arrangement of first conductive connection elements provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic cross-sectional view of a display device provided by an embodiment of the present disclosure.
  • the display device includes: an LED display substrate 1 and a drive substrate 2 that are oppositely arranged.
  • the LED display substrate 1 includes: a substrate 3 and a plurality of LED chips 5.
  • the multiple LED chips 5 are located on the side of the substrate 3 away from the driving substrate 2.
  • the LED display substrate 1 further includes a plurality of first signal traces 6 on the side of the substrate 3 away from the driving substrate 2.
  • the substrate 3 is a glass substrate, and the substrate 3 may also be other substrates suitable for the technical solutions of the present disclosure.
  • one of the first and second poles of the LED chip 5 in the present disclosure is the positive electrode of the LED chip 5 and the other is the negative electrode of the LED chip 5.
  • the first pole of the LED chip 5 and the second pole of the LED chip 5 are taken as an example for description.
  • the driving substrate 2 includes a PCB board 4 and a driving control device 11.
  • the driving control device 11 is located on the PCB board 4 and is usually packaged on the side of the PCB board 4 away from the glass substrate 3.
  • the drive control device 11 is electrically connected to the LED chips 5 through the first signal traces 6 and is used to provide corresponding drive signals to the LED chips 5.
  • the packaging process of packaging the drive control device 11 on the PCB 4 belongs to the conventional technology, and the specific situation is not described in detail here.
  • the LED chip 5 and the first signal trace 6 for providing signals to the LED chip 5 are located on the glass substrate 3.
  • the first signal trace 6 is prepared by the patterning process using the glass substrate 3 as the substrate, since the precision of the patterning process for the thin film using the glass substrate 3 as the substrate is high, the line width can be prepared Small first signal trace 6.
  • the "patterning process” in the present disclosure refers to processes including photoresist coating, exposure, development, thin film etching, photoresist stripping, and the like.
  • the specific process is as follows. First, a thin film of conductive material is formed on the glass substrate 3 by a sputtering process, where the conductive material may be a metal material (for example, copper). A large adhesion force can be formed between the conductive material film that can be formed through the sputtering process and the glass substrate 3. In addition, the thickness of the conductive material film formed on the glass substrate 3 using the above process may be much smaller than the thickness of the copper foil formed using conventional techniques. Next, a patterning process is performed on the conductive material film to obtain the pattern of the first signal trace 6.
  • a sputtering process where the conductive material may be a metal material (for example, copper).
  • a large adhesion force can be formed between the conductive material film that can be formed through the sputtering process and the glass substrate 3.
  • the thickness of the conductive material film formed on the glass substrate 3 using the above process may be much smaller than the thickness of the copper foil formed using conventional techniques.
  • a patterning process is performed on the
  • the minimum line width of the first signal trace 6 prepared by the above process steps is about 3 ⁇ m, which is much smaller than the minimum line width of the signal trace prepared based on the PCB board in the conventional technology.
  • the technical solution of the present disclosure can reduce the line width of the first signal trace 6 used to provide a signal to the LED chip 5, so the size of the LED chip 5 matching the first signal trace 6 is also Can be reduced accordingly.
  • the spacing between adjacent LED chips 5 on both sides of the first signal trace 6 can also be reduced. Therefore, in the area of the same area, the number of LED chips 5 that can be provided in the technical solution of the present disclosure is greater, which is beneficial to achieve high resolution of the LED display device.
  • the production cost can be reduced accordingly.
  • the smallest LED chip 5 size that can be used when the PCB board is the substrate is 8 mil*12 mil
  • the size of the smallest LED chip 5 that can be used is 4 mil*8 mil.
  • the cost of LED chips the former costs about 37,500 yuan per square meter
  • the latter costs about 12,500 yuan per square meter
  • the latter costs about one-third of the former.
  • the LED chip 5 is an LED flip chip.
  • the LED flip chip refers to an LED chip that can be packaged on a substrate based on a flip packaging process.
  • the light emitting layer of the LED chip 5 is located on the side of the first and second poles away from the substrate.
  • the first pole and the second pole are directly in contact with the signal trace on the substrate.
  • the first pole and the second pole are located on the non-light-exiting side of the light-emitting layer, the light-emitting brightness of the LED will not be affected.
  • the LED flip chip When the LED flip chip is used, all LED chips 5 on the glass substrate 3 can be flip-packaged at the same time. Specifically, the first pole and the second pole of each LED chip 5 are electrically connected to the corresponding first signal trace 6 (generally, the first pole and the second pole of the LED chip 5 are connected to the corresponding signal trace After soldering), a transparent silicone protective glue 15 with a certain thickness is coated on the entire surface of the side where the LED chip 5 is provided on the glass substrate 3.
  • the silicone protective adhesive 15 adopts professional LED packaging adhesive, has excellent characteristics such as heat resistance, weather resistance, UV aging resistance and nearly 100% light transmittance, which can protect the LED flip chip without Affect its optical properties.
  • the LED chip used can only be an LED chip (when it is packaged on the substrate, the first pole and the second pole of the LED chip 5 are located away from the light-emitting layer Side of the substrate).
  • the LED front-mounted chip is packaged on the PCB board through the positive packaging process, not only the protective glue 15 but also the bracket packaging and the metal bonding wire need to be used, which makes the process of the positive packaging process complicated and costly.
  • the first and second poles of the LED chip are located on the light-emitting side of the light-emitting layer, the light emitted by the light-emitting layer is blocked, thereby responding to the light-emitting brightness of the LED chip.
  • LED chip 5 is an LED flip chip is an embodiment in the present disclosure, which does not limit the technical solution of the present disclosure.
  • the LED chip 5 is a Mini-LED chip, where the Mini-LED chip refers to an LED chip with a length and width between 80 ⁇ m and 300 ⁇ m, and the Mini-LED chip is generally an LED flip chip.
  • the LED display substrate 1 further includes: a plurality of first conductive connection elements 7 disposed on the glass substrate 3 and corresponding to the plurality of first signal traces 6 in one-to-one correspondence.
  • the driving substrate 2 further includes: a plurality of second conductive connection elements 8 provided on the PCB board 4 and connected in a one-to-one correspondence with the plurality of first conductive connection elements 7.
  • the plurality of first conductive connection elements 7 are respectively adapted to and electrically connected to the plurality of second conductive connection elements 8.
  • the drive control device 11 is electrically connected to each second conductive connection element 8.
  • the driving control device 11 is specifically used to provide corresponding driving signals to the LED chip 5 through the second conductive connection element 8, the first conductive connection element 7, and the first signal trace 6 in sequence.
  • both the first conductive connection element 7 and the second conductive connection element 8 are pads, in which case the first conductive connection element 7 and its corresponding second conductive connection element 8 may be directly soldered to achieve electrical connection, or The electrical connection is achieved by other means (for example, one is a conductive plug and the other is a conductive socket adapted to the conductive plug).
  • the second conductive connection element 8 is located on the side of the PCB board 4 facing the glass substrate 3, and the drive control device 11 is connected to the corresponding second conductive connection element through a via hole (not shown) on the PCB board 4 8 Electrical connection.
  • the first conductive connection element 7 is located on the side of the glass substrate 3 facing the PCB board 4.
  • the LED display substrate 1 further includes a plurality of intermediate conductive connection elements, and the first conductive connection element 7 is connected to the corresponding first signal trace 6 through the intermediate conductive connection element.
  • the first conductive connection element 7 and the corresponding second conductive connection element 8 face each other, at this time, the first conductive connection element 7 and the corresponding second conductive connection element 8 may be directly connected .
  • first conductive connection element 7 and the second conductive connection element 8 are both pads, and the first conductive connection element 7 and the second conductive connection element 8 are welded and fixed.
  • the electrical connection between the connection element 7 and the second conductive connection element 8 can also achieve the overall fixation of the LED display substrate 1 and the drive substrate 2.
  • the first conductive connection element 7 is located on the side surface of the glass substrate 3 facing the PCB board 4, and the LED display substrate 1 may further include: a plurality of second links corresponding to the plurality of first conductive connection elements 7 Signal trace 9.
  • the second signal traces 9 are located on the side surface of the glass substrate 3 facing the PCB board 4 and are respectively disposed between the plurality of intermediate conductive connection elements and the plurality of first conductive connection elements 7. The first end of the second signal trace 9 is connected to the corresponding first conductive connection element 7.
  • the second signal trace 9 can also be prepared by a patterning process using the glass substrate 3 as a substrate.
  • the first end of the first signal trace 6 extends to the edge of the side surface of the glass substrate 3 away from the PCB board 4, and the middle conductive connection element may include a conductive adhesive, which extends along the side of the glass substrate 3
  • a conductive glue channel 10 is established between the first signal traces 6 and the plurality of first conductive connection elements 7 (or the plurality of second signal traces 9, if present).
  • the conductive glue channel 10 includes a first portion located on the side of the glass substrate 3 and a second portion extending to the surface of the glass substrate 3 facing the PCB 4.
  • the first part of the conductive adhesive channel 10 is connected to the first end of a first signal trace 6, and the second part of the conductive adhesive channel 10 corresponds to a first signal trace 6 connected to the first part of the conductive adhesive channel 10
  • the second end of the first conductive connection element 7 (or a second signal trace 9, if present) is connected.
  • the conductive adhesive is conductive silver adhesive.
  • the conductive adhesive channel 10 needs to extend from the side of the glass substrate 3 to the surface of the glass substrate 3 facing the PCB board 4, in order to reduce the conductive adhesive channel 10 on the side of the glass substrate 3 and the glass substrate 3 toward the PCB board 4 There is a risk of a short line at the junction of the side surfaces.
  • a chamfer is formed at the junction of the side of the glass substrate 3 where the conductive silver paste is provided and the side of the glass substrate 3 facing the PCB board 4
  • the conductive glue channel 10 can smoothly transition from the side of the glass substrate 3 to the surface of the glass substrate 3 facing the side of the PCB board 4.
  • the corresponding first signal can be passed through the corresponding first conductive connection element 7, the second signal trace 9 (if present), and the conductive adhesive channel 10 Line 6 makes electrical connection.
  • FIG. 2 is a schematic cross-sectional view of a display device provided by an embodiment of the present disclosure.
  • the first end of the first signal trace 6 extends to a portion of the glass substrate 3 that is far from the PCB board 4
  • the edge of the side surface, and the second end of the middle conductive connection element extends to the edge of the side surface of the glass substrate 3 facing the PCB 4.
  • the intermediate conductive connection element includes multiple metal traces 12.
  • Each of the plurality of metal traces 12 extends along the side of the glass substrate 3 to connect the plurality of first signal traces 6 to the plurality of first conductive connection elements 7 (or the plurality of second signal traces 9, respectively) If present) electrical connection. That is, the first end of the metal trace 12 is connected to the first end of a first signal trace 6, and the second end of the metal trace 12 is connected to a first signal trace connected to the first end of the metal trace 12 A plurality of first conductive connection elements 7 (second ends of the second signal traces 9) corresponding to the line 6 are connected.
  • the materials of the metal trace 12, the first signal trace 6, and the second signal trace 9 are the same.
  • the metal trace 12, the first signal trace 6 and the second signal trace 9 are all copper wires, because the copper wires have high conductivity and low production cost.
  • the intermediate conductive connection element in FIG. 3 includes an FPC board 13, which is bent along the side of the glass substrate 3 and extends to the glass lining The bottom 3 faces the side of the PCB 4.
  • the first conductive connection element 7 is located on the FPC board 13.
  • the FPC board 13 includes multiple conductive channels in parallel, and the first end of each conductive channel is connected to the first end of a corresponding first signal trace 6.
  • the first end of the conductive channel is connected to the first end of a corresponding first signal trace 6 through a bonding process, and the second end of each conductive channel is connected to the first end of the conductive channel
  • the first conductive connection elements 7 corresponding to the first signal traces 6 are connected.
  • the second end of the conductive path is located at the portion of the FPC board 13 that is bent to the side of the glass substrate 3 facing the PCB board 4.
  • the first conductive connection element 7 is located on the side of the FPC board 13 facing the PCB board 4 and is connected to the second end of the corresponding conductive channel on the FPC board 4.
  • the first conductive connection element 7 may be directly located at the second end of the corresponding conductive channel and facing a side surface of the PCB board 4.
  • the production process steps can be reduced and the production cycle can be shortened.
  • the number of FPC boards used can be selected according to the number of first signal traces 6 and the number of conductive channels in the FPC board 14, that is, multiple FPC boards 14 can be selected.
  • FIG. 4 is a schematic cross-sectional view of a display device provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of an arrangement of first conductive connection elements and second conductive connection elements in the display substrate shown in FIG. 4.
  • the difference from FIGS. 1 to 3 is that the size of the glass substrate 3 in FIG. 4 is smaller than the size of the PCB board 4, that is, the PCB board 4 includes a first central area and surrounding In the first peripheral area of the first central area, the LED display substrate 1 is located in the first central area of the PCB board 4.
  • the surface of the glass substrate 3 facing the PCB board 4 is bonded to the surface of the PCB board 4 facing the glass substrate 3.
  • the drive control device 11 is located on the side of the PCB board 4 away from the glass substrate 3.
  • the second conductive connection element 8 is located in the first peripheral area of the PCB 4.
  • the LED display substrate 1 includes a second central area and a second peripheral area, a plurality of LED chips 5 are located in the second central area, and the first conductive connection element 7 is located in the second peripheral area.
  • the first conductive connection element 7 and the corresponding second conductive connection element 8 are electrically connected by a conductive jumper 14.
  • the conductive jumper 14 is a gold wire.
  • the second peripheral area includes a first selected area, a second selected area, a third selected area, and a fourth selected area that are separated from each other.
  • the first selected area, the second selected area, the third selected area, and the fourth selected area are all provided with a uniformly distributed selected number of first conductive connection elements 7, and the selected in each selected area A certain number of first conductive connection elements 7 are electrically connected to a selected number of first signal traces through conductive jumpers 14, respectively.
  • the first selected area and the second selected area are respectively adjacent to two opposite edges of the surface where they are located, and the third selected area and the fourth selected area are respectively adjacent to the other two opposite edges of the surface where they are located.
  • the first conductive connection element 7 is located on the side surface of the glass substrate 3 far away from the PCB board 4 and close to the edge of the side of the second conductive connection element 8 corresponding to the first conductive connection element 7, which can be effectively shortened at this time
  • the distance between the first conductive connection element 7 and its corresponding second conductive connection element 8 reduces the length of the conductive jumper 14 that needs to be configured, thereby reducing the resistance of the conductive jumper 14 and reducing production costs.
  • the second conductive connection element 8 and the conductive jumper 14 may be packaged together to The conductive connection element 8 and the conductive jumper 14 are protected.
  • FIG. 6 is a schematic diagram of an arrangement of LED chips and first pole signal traces in the present disclosure
  • FIG. 7 is a schematic diagram of an arrangement of LED chips and second pole signal traces in the present disclosure.
  • the multiple first signal traces 6 are specifically divided into multiple first pole signal traces 6 a and multiple second pole signal traces 6 b.
  • the first signal connected to the first pole of all LED chips including LED chips emitting red color light (R), LED chips emitting green color light (G), and LED chips emitting blue color light (B)
  • the trace 6 is a first pole signal trace 6a
  • the first signal trace 6 connected to the second poles of all LED chips is a second pole signal trace 6b.
  • All the first pole signal traces 6a are arranged in the same layer, and all the second pole signal traces 6b are arranged in the same layer, and the first pole signal traces 6a and the second pole signal traces 6b are arranged in different layers.
  • An insulating layer is provided between the layer where the first signal trace 6 is provided and the layer where the second electrode signal trace 6b is provided.
  • all LED chips constitute a pixel array
  • the pixel array includes M rows and N columns in total M*N pixel units.
  • Each pixel unit includes: the same number of LED chips, and different LED chips in the same pixel unit emit different colors of light, for example, each pixel unit includes three LED chips, and the three LED chips respectively emit red Light, green light and blue light.
  • a plurality of first pole signal traces 6a extend along the row direction of the pixel unit, and a plurality of second pole signal traces 6b extend along the column direction of the pixel unit.
  • the first poles of the LED chips R/G/B in the pixel units in the same row are connected to the same first-pole signal trace 6a, and the LED chips R in the pixel units in different rows /G/B connects different first-pole signal traces 6a.
  • the second poles of the LED chips R/G/B that are located in the same column of pixel units and emit the same color are connected to the same second pole signal trace 6b.
  • the LED chips R/G/B located in different columns of pixel units are connected to different second-pole signal traces 6b.
  • M and N are integers, and m is an integer less than M.
  • the second poles of the LED chips R/G/B that are located in the same column of pixel cells and emit the same color are connected to the same second pole signal trace 6b,
  • the LED chips R/G/B located in different columns of pixel units are connected to different second-pole signal traces 6b.
  • the second pole signal trace 6b connected to the second pole of the LED chip R/G/B in the pixel unit of the 1st to mth rows and the LED in the pixel unit of the m+1th to Mth rows is a different signal trace.
  • the drawing only schematically shows that the pixel array includes 4 rows and 4 columns, a total of 16 pixel units PX, and each pixel unit PX includes three LED chips R/G/B and three LED chips R/G/B is the case of the red LED chip R, the green LED chip G, and the blue LED chip B, respectively, which does not limit the technical solution of the present disclosure.
  • the green LED chip G and the blue LED chip B are arranged along the column direction, and the case where the green LED chip G and the blue LED chip B are located on the left side of the red LED chip R only serves as a schematic It also does not limit the technical solutions of the present disclosure.
  • the number of LED chips included in one pixel unit and the arrangement of each LED chip are not limited.
  • the pixel array includes 3M*N LED chips R/G/B, and M first pole signal traces 6a and 6N second pole signal traces 6b need to be arranged.
  • the first electrode signal trace 6a connected to the LED chips R/G/B in the pixel units in the first to mth rows extends to the first end of the side surface of the glass substrate 3 away from the PCB board 4 Side edges (connected to the first conductive connection element in the corresponding first selected area through the corresponding connection element).
  • the first pole signal trace 6a connected to the LED chip R/G/B in the pixel unit of the m+1th row to the Mth row extends from the first end to the side of the glass substrate 3 away from the PCB board 4
  • the second side edge (connected to the second conductive connection element in the corresponding first selected area through the corresponding connection element).
  • the second electrode signal trace 6b connected to the LED chips R/G/B located in the pixel units in the first row to the mth row extends to the third end of the glass substrate 3 on the side surface away from the PCB board 4 Side edges (connected to the first conductive connection element in the corresponding third selected area through the corresponding connection element).
  • the second electrode signal trace 6b connected to the LED chip R/G/B in the pixel unit of the m+1th row to the Mth row extends from the first end to the side of the glass substrate 3 away from the PCB board 4
  • the fourth side edge (connected to the fourth conductive connection element in the corresponding first selected area through the corresponding connection element).
  • the first side edge and the second side edge are opposite side edges in the row direction
  • the third side edge and the fourth side edge are opposite side edges in the column direction.
  • first side edge and the second side edge are the left side edge and the right side edge in the drawing
  • third side edge and the fourth side edge are the upper side edge and the lower side edge in the drawing, respectively .
  • the first signal trace 6 all four edges of the glass substrate 3 are led out by the first signal trace 6. Specifically, among the M first-pole signal traces 6a, half of the first-pole signal traces 6a are drawn from the left edge of the glass substrate 3, and the other half of the first-pole signal traces 6a are drawn from the glass substrate 3 Leading to the right edge. Of the 6N second-pole signal traces 6b, half of the second-pole signal traces 6b are drawn from the upper edge of the glass substrate 3, and the other half of the second-pole signal traces 6b are drawn from the lower side of the glass substrate 3 The edge leads.
  • the number of wirings on the left and right edge regions of the glass substrate 3 can be equalized, and the number of wirings on the upper and lower edge regions of the glass substrate 3 can be the same, thereby improving the edge region of the glass substrate 3 Wiring uniformity.
  • the wiring length of the second-pole signal traces 6b can be effectively shortened, thereby reducing the number of The resistance of the two-pole signal trace 6b further improves the signal transmission quality of the second-pole signal trace 6b.
  • the first conductive connection element 7 is a top view of the first conductive connection element in the present disclosure. As shown in FIG. 8, further, when the LED display substrate 1 has the first conductive connection element 7 and the first conductive connection element 7 is located on the glass substrate 3 When facing the side surface of the PCB board 4 (that is, the LED display substrate 1 is the LED display substrate 1 in the display device shown in FIGS. 1-2), the first conductive connection elements 7 may be arranged as follows.
  • the surface of the glass substrate 3 on the side facing the PCB board 4 is divided into at least a first selected area, a second selected area, a third selected area, and a fourth selected area that are separated from each other.
  • the first selected area, the second selected area, the third selected area, and the fourth selected area are all provided with a uniformly distributed selected number of first conductive connection elements, and the selected in each selected area
  • the number of first conductive connection elements is electrically connected to the selected number of first signal traces through corresponding intermediate conductive connection elements (or through intermediate conductive connection elements and second signal traces), respectively.
  • the first selected area and the second selected area are located on the edges of the surface of the glass substrate 3 on the side facing the PCB board 4 near the opposite sides of the glass substrate 3.
  • the first selected area and the second selected area are respectively adjacent to two opposite edges of the surface on which they are located, that is, the third selected area and the fourth selected area are located on the surface of the glass substrate 3 on the side facing the PCB 4 Near the opposite sides of the glass substrate 3.
  • the third selected area and the fourth selected area are respectively adjacent to the other two opposite edges of the surface on which they are located, that is, the opposite sides of the glass substrate near the first selected area and the second selected area (along the pixel array)
  • the edge in the row direction is different from the edge on opposite sides (along the column direction of the pixel array) of the glass substrate where the third selected area and the fourth selected area are close.
  • a first conductive connection element 7 a corresponding to the first electrode signal trace 6 a connecting the LED chips 5 located in the pixel units in the first to mth rows is located on the glass substrate 3 toward the PCB board 4 In a first selected area 16a on one side and close to the first side edge of the glass substrate 3.
  • the first conductive connection element 7b corresponding to the first electrode signal trace 6a connecting the LED chips 5 located in the pixel units in the m+1th row to the Mth row is located on the side of the glass substrate 3 facing the PCB board 4 And in the second selected region 16b near the second side edge of the glass substrate 3.
  • the first conductive connection element 7c corresponding to the second electrode signal trace 6b connecting the LED chips 5 located in the pixel units in the first to mth rows is located on the side of the glass substrate 3 facing the PCB board 4 and close to In the third selected region 16c of the third side edge of the glass substrate 3.
  • the first conductive connection element 7d corresponding to the second electrode signal trace 6b connecting the LED chips 5 located in the pixel units in the m+1th row to the Mth row is located on the side of the glass substrate 3 facing the PCB board 4 And in the fourth selected region 16d near the fourth side edge of the glass substrate 3.
  • the first end of the first signal trace 6 electrically connected to the first conductive connection element 7a/7b/7c/7d and the first conductive connection element 7a/7b/7c/7d is located on the glass substrate
  • the same side edge on 3 can effectively shorten the length of the middle conductive connecting element 17 used to electrically connect the first end of the first signal trace 6 to the corresponding first conductive connecting element 7a/7b/7c/7d, thereby enabling reduce manufacturing cost.
  • all the first conductive connection elements 7a located on the side of the glass substrate 3 facing the PCB board 4 and close to the first side edge of the glass substrate 3 are evenly arranged in the first selected area 16a.
  • All the first conductive connection elements 7b on the side of the glass substrate 3 facing the PCB board 4 and close to the second side edge of the glass substrate 3 are evenly arranged in the second selected area 16b.
  • All the first conductive connection elements 7c located on the side of the glass substrate 3 facing the PCB board 4 and close to the third side edge of the glass substrate 3 are evenly arranged in the third selected area 16c.
  • All the first conductive connection elements 7d located on the side surface of the glass substrate 3 facing the PCB board 4 and close to the fourth side edge are evenly arranged in the fourth selected area 16d.
  • the present disclosure by evenly arranging all the first conductive connection elements 7a near the first side edge in the first selected area 16a, all the first conductive connection elements 7b near the second side edge are placed in the second selection Evenly arranged in the fixed area 16b, all the first conductive connection elements 7c near the third side edge are evenly arranged in the third selected area 16c, and all the first conductive connection elements 7d near the fourth side edge are located in the The four selected areas 16d are evenly arranged, so that the first conductive connecting elements 7a/7b/7c/7d in each selected area are evenly arranged.
  • Such a design can make the size of the first conductive connection element 7a/7b/7c/7d larger, so as to improve the problem of short circuit or virtual connection caused by the misalignment of the glass substrate 3 and the PCB board 4.
  • the first conductive connection elements 7a/7b are arranged in a row and adjacent to the first connected conductive connection element
  • the case where the distance between them is equal is only an optional way to achieve uniform arrangement, which does not limit the technical solution of the present disclosure.
  • the first conductive connecting elements 7c/7d are arranged in three rows, and the adjacent first conductive connecting structures are dislocated in adjacent rows.
  • the situation is only an optional way to achieve uniform arrangement, which does not limit the technical solution of the present disclosure.
  • the arrangement of the first conductive connection elements on the side of the LED display substrate away from the PCB board 4 may also be as shown in FIG. 8
  • the situation shown is different in that the first selected area, the second selected area, the third selected area, and the fourth selected area are located in the second peripheral area of the LED display substrate 1, which will not be repeated here.
  • the display substrate in the present disclosure may include a plurality of LED display substrates, and the plurality of LED display substrates are located on the same plane to constitute a spliced LED display device.
  • the number of driving substrates may be one or more.
  • the number of driving substrates is one, and multiple LED display substrates correspond to the same large-sized driving substrate.
  • the number of the driving substrates is multiple, and the multiple LED display substrates correspond to the multiple driving substrates one-to-one. For other cases, we will not describe them one by one here.
  • these LED display substrates can be packaged using the same layer of protective glue.

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Abstract

一种LED显示装置，包括：相对设置的LED显示基板(1)和驱动基板(2)；LED显示基板(1)包括：衬底(3)和多个LED芯片(5)，多个LED芯片(5)位于衬底(3)远离驱动基板(2)的一侧；驱动基板(2)包括：PCB板(4)和驱动控制器件(11)，驱动控制器件(11)位于PCB板(4)上，驱动控制器件(11)通过多条第一信号走线(6)与多个LED芯片(5)电连接以向各LED芯片(5)提供驱动信号。

Description

LED显示装置
相关申请的交叉引用
本申请要求于2019年1月4日在中国知识产权局提交的申请号为201910008987.4、名称为“显示装置”的中国专利申请的优先权，该中国专利申请的全部公开内容通过引用合并于此。
技术领域
本公开涉及显示技术领域，特别涉及一种LED显示装置。
背景技术
发光二极管(Light Emitting Diode，简称LED)显示面板是LED显示装置的核心器件，其中LED显示面板包括：印制电路板(Printed Circuit Board，简称PCB板)、封装于该PCB板上的LED芯片和驱动控制器件，PCB板上需设计信号走线用于为LED的正、负极提供电信号。
发明内容
在一些实施例中，提供了一种LED显示装置，包括：相对设置的LED显示基板和驱动基板；所述LED显示基板包括：衬底和多个LED芯片，所述多个LED芯片位于所述衬底远离所述驱动基板的一侧；所述驱动基板包括：PCB板和驱动控制器件，所述驱动控制器件位于所述PCB板上，所述驱动控制器件通过多条第一信号走线与所述多个LED芯片电连接以向各LED芯片提供驱动信号。
在一些实施例中，所述多条第一信号走线位于所述衬底的远离所述驱动基板的一侧上。
在一些实施例中，所述LED显示基板还包括多个第一导电连接元件，所述多个第一导电连接元件位于所述衬底上并且与所述多条第一信号走线一一对应电连接；所述驱动基板还包括多个第二导电连接元件，所述多个第二导电连接元件位于所述PCB板朝向所述衬底的一 侧，并且所述多个第二导电连接元件与所述驱动控制器件电连接；其中，所述多个第二导电连接元件与所述多个第一导电连接元件一一对应电连接。
在一些实施例中，所述多个第一导电连接元件位于所述衬底朝向所述PCB板的一侧，所述LED显示基板还包括多个中间导电连接元件，其中所述多个第一导电连接元件分别通过所述多个中间导电连接元件与所述多条第一信号走线电连接。
在一些实施例中，所述多个中间导电连接元件包括导电胶、金属走线和FPC板中的至少一种。
在一些实施例中，所述衬底的朝向所述PCB板的一侧的表面包括彼此分隔开的第一选定区域、第二选定区域、第三选定区域和第四选定区域，其中，所述第一选定区域、所述第二选定区域、所述第三选定区域和所述第四选定区域中均具有均匀分布的选定数量的第一导电连接元件，并且每个选定区域中的选定数量的第一导电连接元件分别通过所述中间导电连接元件而与选定数量的第一信号走线电连接。
在一些实施例中，所述第一选定区域和所述第二选定区域分别邻近其所在表面的相对的两个边缘，所述第三选定区域和所述第四选定区域分别邻近其所在表面的相对的另外两个边缘。
在一些实施例中，所述LED显示装置还包括保护胶层，其中，所述保护胶层覆盖所述多个LED芯片、所述多条第一信号走线和所述多个中间导电连接元件的位于所述衬底远离所述PCB板的一侧的部分。
在一些实施例中，所述PCB板包括第一中心区域和围绕所述第一中心区域的第一周边区域，所述LED显示基板位于在所述PCB板的第一中心区域中。
在一些实施例中，所述第二导电连接元件位于所述第一周边区域中，且所述多个第一导电连接分别与所述多个第二导电连接元件通过导电跳线电连接。
在一些实施例中，所述LED显示基板包括第二中心区域和第二 周边区域，所述多个LED芯片位于所述第二中心区域中，并且所述第一导电连接元件位于所述第二周边区域中，其中，所述第二周边区域包括彼此分隔开的第一选定区域、第二选定区域、第三选定区域和第四选定区域，所述第一选定区域、所述第二选定区域、所述第三选定区域和所述第四选定区域中均具有均匀分布的选定数量的第一导电连接元件，并且每个选定区域中的选定数量的第一导电连接元件通过导电跳线而分别与选定数量的第一信号走线电连接，其中，所述第一选定区域和所述第二选定区域分别邻近其所在表面的相对的两个边缘，所述第三选定区域和所述第四选定区域分别邻近其所在表面的相对的另外两个边缘。
在一些实施例中，所述LED显示装置还包括保护胶层，其中，所述保护胶层覆盖所述多个LED芯片、所述多条第一信号走线、所述多个第一导电连接元件、所述多个第二导电连接元件以及所述导电跳线。
在一些实施例中，所述多条第一信号走线包括与所述多个LED芯片的第一极连接的多条第一极信号走线，以及与所述多个LED芯片的第二极连接的多条第二极信号走线；全部所述多条第一极信号走线同层设置，全部所述多条第二极信号走线同层设置，所述多条第一极信号走线与所述多条第二极信号走线异层设置。
在一些实施例中，所述多个LED芯片构成像素阵列，所述像素阵列包括M行、N列总计M*N个像素单元，所述像素单元中的每一个中的LED芯片的数量相同并且位于同一像素单元中的不同LED芯片发出不同颜色的光；所述多条第一极信号走线沿所述像素单元的行方向延伸，所述多条第二极信号走线沿所述所述像素单元的列方向延伸，所述像素阵列的第1行～第m行像素单元中的每一行像素单元中的LED芯片的第一极连接至同一条第一极信号走线，并且与所述像素阵列的第1行～第m行像素单元连接的多条第一极信号走线通过相应的连接元件与所述第一选定区域中的第一导电连接元件电连接；所述像素阵列的第m+1行～第M行像素单元中的每一行像素单元中的LED芯片的第一极均连接所述多条第一极信号走线中的相应一条，并且与 所述像素阵列的第m+1行～第M行像素单元连接的多条第一极信号走线通过相应的连接元件与所述第二选定区域中的第一导电连接元件电连接；所述像素阵列的第1行～第m行像素单元中的每一列像素单元中的LED芯片中的发相同颜色光的LED芯片的第二极连接至同一条第二极信号走线，并且与所述像素阵列的第1行～第m行像素单元连接的多条第二极信号走线通过相应的连接元件与所述第三选定区域中的第一导电连接元件电连接；所述像素阵列的第m+1行～第M行像素单元中的LED芯片每一列像素单元中的LED芯片中的发相同颜色光的LED芯片的第二极连接至同一条第二极信号走线，并且与所述像素阵列的第m+1行～第M行像素单元连接的多条第二极信号走线通过相应的连接元件与所述第四选定区域中的第一导电连接元件电连接，其中，M、N为整数，m为小于M的整数。
在一些实施例中，m＝INT(M/2)，INT(M/2)表示对M/2的值进行取整。
在一些实施例中，所述LED芯片为LED倒装芯片。
在一些实施例中，所述第一导电连接元件和所述第二导电连接元件均为焊盘。
在一些实施例中，所述衬底为玻璃衬底。
附图说明
图1为本公开实施例提供的显示装置的截面示意图；
图2为本公开实施例提供的显示装置的截面示意图；
图3为本公开实施例提供的显示装置的截面示意图；
图4为本公开实施例提供的显示装置的截面示意图；
图5为图4所示显示装置中第一导电连接元件和第二导电连接元件的一种排布示意图；
图6为本公开实施例提供的LED芯片和第一极信号走线的排布示意图；
图7为本公开实施例提供的LED芯片和第二极信号走线的排布示意图；
图8为本公开实施例提供的第一导电连接元件的排布示意图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的一种显示装置进行详细描述。
在PCB板上制备信号走线时，通常采用多层设计。受限于干膜解析度低、干膜厚度大、铜厚度大、曝光和蚀刻设备精度不高等因素的影响，使得在PCB板上所能形成的信号走线的线宽较大(可进行量产的最小线宽在85μm左右)，导致该信号走线所需搭配的LED芯片尺寸较大。另外，部分相邻LED之间需要布置信号走线时，由于配置的信号走线的线宽较大，也会导致相邻LED芯片之间的间距较大。基于上述问题，导致目前的LED显示面板难以实现高分辨率。
图1为本公开实施例提供的一种显示装置的截面示意图，如图1所示，该显示装置包括：相对设置的LED显示基板1和驱动基板2。该LED显示基板1包括：衬底3和多个LED芯片5。多个LED芯片5位于衬底3远离驱动基板2的一侧。该LED显示基板1还包括位于衬底3的远离驱动基板2的一侧上的多条第一信号走线6。对于任一LED芯片5，该LED芯片5的第一极和第二极分别连接不同的两条第一信号走线6。在一些实施例中，衬底3为玻璃衬底，衬底3还可以为其它适于本公开技术方案的衬底。
需要说明的是，本公开中的LED芯片5的第一极和第二极中之一为LED芯片5的正极，另一为LED芯片5的负极。为方便描述，本公开中以LED芯片5的第一极为正极，LED芯片5的第二极为负极为例进行示例描述。
驱动基板2包括：PCB板4和驱动控制器件11，驱动控制器件11位于于PCB板4上，并且通常封装在PCB板4的远离玻璃衬底3的一侧。驱动控制器件11通过各第一信号走线6与各LED芯片5电连接，用于向各LED芯片5提供相应的驱动信号。
将驱动控制器件11封装于PCB板4上的封装工艺属于常规技术，具体情况此处不进行详细描述。
在本公开中，LED芯片5和用于为LED芯片5提供信号的第一信号走线6位于玻璃衬底3上。其中，在以玻璃衬底3作为衬底通过构图工艺来制备第一信号走线6时，由于以玻璃衬底3作为衬底的对薄膜进行构图工艺的精度较高，因此能够制备出线宽较小的第一信号走线6。需要说明的是，本公开中的“构图工艺”是指包括光刻胶涂布、曝光、显影、薄膜刻蚀、光刻胶剥离等工艺。
作为本公开中的一种制备第一信号走线6的工艺，具体过程如下。首先，在玻璃衬底3上通过溅射(Sputter)工艺形成一层导电材料薄膜，其中导电材料可以为金属材料(例如，铜)。通过溅射工艺所能形成的导电材料薄膜与玻璃衬底3之间可以形成较大的附着力。另外，采用上述工艺在玻璃衬底3上形成的导电材料薄膜的厚度可以远小于采用常规技术形成的铜箔的厚度。接着，对导电材料薄膜进行构图工艺，以制得第一信号走线6的图案。
通过上述工艺步骤制备出的第一信号走线6的最小线宽在3μm左右，远小于常规技术中基于PCB板所制备出的信号走线的最小线宽。
与相关技术相比，本公开的技术方案可以减小用于为LED芯片5提供信号的第一信号走线6的线宽，因此与第一信号走线6相匹配的LED芯片5的尺寸也可以相应减小。与此同时，位于第一信号走线6两侧且相邻的LED芯片5之间的间距也可以减小。因此，在相同面积的区域内，本公开的技术方案可以设置的LED芯片5数量更多，有利于LED显示装置实现高分辨率。
另外，随着所使用的LED芯片5尺寸的降低，生产成本也可以相应降低。具体地，在像素点间距为P1.0(相邻LED芯片5中心点之间的距离为1.0mm)前提下，以PCB板作为衬底时可用最小LED芯片5的尺寸为8mil*12mil，而本公开中以玻璃衬底3为衬底时可用最小LED芯片5的尺寸为4mil*8mil。就LED芯片成本而言，前者每平方米的造价约为37500元，后者每平方米的造价约为12500元，后者约为前者的三分之一。
可选地，LED芯片5选用LED倒装芯片。其中LED倒装芯片是指 能够基于倒封装工艺而被封装在衬底上的LED芯片。LED芯片5被封装在衬底上时，LED芯片5的发光层位于第一极和第二极的远离衬底的一侧。第一极和第二极直接与位于衬底上的信号走线相接触，此时由于第一极和第二极位于发光层的非出光侧，因而不会影响LED的出光亮度。
当采用LED倒装芯片时，可以对玻璃衬底3上的所有LED芯片5同时进行倒封装。具体地，在各LED芯片5的第一极和第二极均与相应的第一信号走线6完成电连接(一般是将LED芯片5的第一极、第二极与对应的信号走线焊接)后，在玻璃衬底3上设置有LED芯片5的一侧整面涂覆一定厚度的透明有机硅保护胶15。该有机硅保护胶15采用专业的LED封装用胶，具备很好的耐热性、耐候性、抗紫外老化及接近100％的透光性等优异特性，可将LED倒装芯片保护起来而不影响其光学特性。
在相关技术中，以PCB板作为衬底时，所使用的LED芯片仅能为LED正装芯片(其被封装在衬底上时，LED芯片5的第一极和第二极位于发光层的远离衬底的一侧)。LED正装芯片通过正封装工艺封装于PCB板上时，不但需要使用保护胶15，还需要使用支架封装和金属打线，使得正封装工艺的工艺复杂、成本高。另外，由于LED芯片的第一极和第二极位于发光层的发光侧，因此会阻挡发光层所射出的光线，从而响应LED芯片的发光亮度。
通过上述对比可见，本公开中通过使用LED倒装芯片，可有效降低封装工艺难度、封装成本，提升发光亮度。
需要说明的是，上述LED芯片5选用LED倒装芯片的情况，为本公开中的一种实施方案，其不会对本公开的技术方案产生限制。
可选地，LED芯片5为Mini-LED芯片，其中Mini-LED芯片是指长、宽均在80μm～300μm之间的LED芯片，Mini-LED芯片一般为LED倒装芯片。
在本公开中，LED显示基板1还包括：设置在玻璃衬底3上的与多条第一信号走线6一一对应连接的多个第一导电连接元件7。驱动基板2还包括：设置在PCB板4上的与多个第一导电连接元件7一一 对应连接的多个第二导电连接元件8。多个第一导电连接元件7分别与多个第二导电连接元件8适配且电连接。驱动控制器件11与各第二导电连接元件8电连接。驱动控制器件11具体用于依次通过第二导电连接元件8、第一导电连接元件7、第一信号走线6向LED芯片5提供相应的驱动信号。
在一些实施例中，第一导电连接元件7和第二导电连接元件8均为焊盘，此时第一导电连接元件7与其对应的第二导电连接元件8可以直接焊接以实现电连接，或是通过其他方式(例如一者为导电插头，另一者为与导电插头适配的导电插口)实现电连接。
在一些实施例中，第二导电连接元件8位于PCB板4朝向玻璃衬底3的一侧，驱动控制器件11通过PCB板4上的导孔(未示出)与对应的第二导电连接元件8电连接。
可选地，第一导电连接元件7位于玻璃衬底3朝向PCB板4的一侧。LED显示基板1还包括多个中间导电连接元件，第一导电连接元件7通过中间导电连接元件与对应的第一信号走线6连接。
可选地，如图1所示，第一导电连接元件7与对应的第二导电连接元件8正对，此时可便于第一导电连接元件7与对应的第二导电连接元件8直接进行连接。
作为一种可选实施方案，第一导电连接元件7和第二导电连接元件8均为焊盘，第一导电连接元件7和第二导电连接元件8焊接固定，此时不仅能实现第一导电连接元件7与第二导电连接元件8的电连接，也可实现LED显示基板1与驱动基板2的整体固定。
继续参见图1，第一导电连接元件7位于玻璃衬底3朝向PCB板4的一侧表面，LED显示基板1还可以包括：与多个第一导电连接元件7一一对应的多条第二信号走线9。第二信号走线9位于玻璃衬底3朝向PCB板4的一侧表面并且分别设置在多个中间导电连接元件与多个第一导电连接元件7之间。第二信号走线9的第一端与对应的第一导电连接元件7连接。
其中，第二信号走线9也可以采用以玻璃衬底3作为衬底的构图工艺进行制备。
第一信号走线6的第一端延伸至玻璃衬底3的远离PCB板4的一侧表面的边缘，中间导电连接元件可包括导电胶，导电胶沿玻璃衬底3的侧面延伸、在多条第一信号走线6与多个第一导电连接元件7(或多条第二信号走线9，如存在)之间建立导电胶通道10。导电胶通道10包括：位于玻璃衬底3的侧面的第一部分以及延伸至玻璃衬底3朝向PCB板4一侧表面的第二部分。导电胶通道10的第一部分与一条第一信号走线6的第一端连接，导电胶通道10的第二部分与该导电胶通道10的第一部分所连接的一条第一信号走线6对应的第一导电连接元件7(或一条第二信号走线9，如存在)的第二端连接。
作为导电胶的一种可选方案，导电胶为导电银胶。
由于导电胶通道10需要从玻璃衬底3的侧面延伸至玻璃衬底3朝向PCB板4一侧表面，为降低导电胶通道10在玻璃衬底3的侧面与玻璃衬底3朝向PCB板4一侧表面的交接处出现短线的风险，在一些实施例中，在玻璃衬底3上设置有导电银胶的侧面与玻璃衬底3朝向PCB板4一侧表面交接处形成有倒角，以使得导电胶通道10能够从玻璃衬底3的侧面平缓的过渡至玻璃衬底3朝向PCB板4一侧表面。
此时，对于每一个第二导电连接元件8而言，均可通过对应的第一导电连接元件7、第二信号走线9(如存在)、导电胶通道10来与对应的第一信号走线6实现电连接。
图2为本公开实施例提供的一种显示装置的截面示意图。如图2所示，与图1中所示情况不同是，在图2所示的显示装置中，不仅第一信号走线6的第一端延伸至玻璃衬底3的远离PCB板4的一侧表面的边缘，而且中间导电连接元件(或第二信号走线9，如存在)的第二端延伸至玻璃衬底3的朝向PCB板4的一侧表面的边缘。此时，中间导电连接元件包括多条金属走线12。多条金属走线12中的每一条沿玻璃衬底3的侧面延伸，以将多条第一信号走线6分别与多个第一导电连接元件7(或多条第二信号走线9，如存在)电连接。即，金属走线12的第一端与一条第一信号走线6的第一端连接，金属走线12的第二端与该金属走线12的第一端所连接的一条第一信号走线6 对应的一条多个第一导电连接元件7(第二信号走线9的第二端)连接。
其中，金属走线12、第一信号走线6、第二信号走线9的材料相同。作为一种具体可选方案，金属走线12、第一信号走线6和第二信号走线9均为铜线，因为铜线的导电率高、生产成本低。
图3为本公开实施例提供的一种显示装置的截面示意图。如图3所示，与图1和图2所示情况不同的是，图3中的中间导电连接元件包括FPC板13，FPC板13中沿玻璃衬底3的侧面弯折并延伸至玻璃衬底3朝向PCB板4的一侧。第一导电连接元件7位于FPC板13上。具体地，FPC板13包括并行的多个导电通道，各导电通道的第一端与对应的一条第一信号走线6的第一端连接。具体地，导电通道的第一端通过绑定(Bonding)工艺与对应的一条第一信号走线6的第一端连接，各导电通道的第二端与该导电通道的第一端所连接的第一信号走线6对应的第一导电连接元件7连接。导电通道的第二端位于FPC板13的弯折至玻璃衬底3朝向PCB板4的一侧的部分。第一导电连接元件7位于FPC板13的朝向PCB板4的一侧并与FPC板4上相应导电通道的第二端连接。第一导电连接元件7可直接位于对应的导电通道的第二端处且朝向PCB板4的一侧表面。
在图3所示方案中，由于无需制备第二信号走线9，因此可减少生产工艺步骤，缩短生产周期。并且，可以根据第一信号走线6的数量以及FPC板14中导电通道的数量选择使用的FPC板的数量，即可以选择多个FPC板14。
图4为本公开实施例提供的一种显示装置的截面示意图，图5为图4所示显示基板中第一导电连接元件和第二导电连接元件的一种排布示意图。如图4和图5所示，与图1～图3中所示不同的是，图4中玻璃衬底3的尺寸小于PCB板4的尺寸，即，PCB板4包括第一中心区域和围绕第一中心区域的第一周边区域，LED显示基板1位于在PCB板4的第一中心区域中。玻璃衬底3朝向PCB板4的一侧表面与PCB板4朝向玻璃衬底3的一侧表面粘接。驱动控制器件11位于PCB板4的远离玻璃衬底3的一侧。第二导电连接元件8位于PCB 板4第一周边区域中。LED显示基板1包括第二中心区域和第二周边区域，多个LED芯片5位于第二中心区域中，第一导电连接元件7位于第二周边区域中。第一导电连接元件7与对应的第二导电连接元件8通过导电跳线14电连接。其中，可选地，导电跳线14为金线。
参见图5，可选地，第二周边区域包括彼此分隔开的第一选定区域、第二选定区域、第三选定区域和第四选定区域。第一选定区域、第二选定区域、第三选定区域和第四选定区域中均设置有均匀分布的选定数量的第一导电连接元件7，并且每个选定区域中的选定数量的第一导电连接元件7通过导电跳线14而分别与选定数量的第一信号走线电连接。第一选定区域和第二选定区域分别邻近其所在表面的相对的两个边缘，第三选定区域和第四选定区域分别邻近其所在表面的相对的另外两个边缘。即，第一导电连接元件7位于玻璃衬底3远离PCB板4的一侧表面且靠近该第一导电连接元件7所对应的第二导电连接元件8的所在一侧边缘，此时可有效缩短第一导电连接元件7与其对应的第二导电连接元件8之间的距离，减小所需配置的导电跳线14的长度，从而能降低导电跳线14的电阻以及降低生产成本。
需要说明的是，在图4所示的显示装置中，在利用保护胶15对LED芯片5进行封装时，可对第二导电连接元件8和导电跳线14一并进行封装，以对第二导电连接元件8和导电跳线14进行保护。
图6为本公开中LED芯片和第一极信号走线的一种排布示意图，图7为本公开中LED芯片和第二极信号走线的一种排布示意图。如图6和图7所示，在一些实施例中，多条第一信号走线6具体划分为多条第一极信号走线6a和多条第二极信号走线6b。其中，与所有LED芯片(包括发红颜色光的LED芯片(R)、发绿颜色光的LED芯片(G)、发蓝颜色光的LED芯片(B))的第一极连接的第一信号走线6为第一极信号走线6a，与所有LED芯片的第二极连接的第一信号走线6为第二极信号走线6b。全部第一极信号走线6a同层设置，全部第二极信号走线6b同层设置，第一极信号走线6a与第二极信号走线6b异层设置。设置第一信号走线6的层与设置第二极信号走线6b的层之间设置有绝缘层。
在一些实施例中，全部LED芯片构成像素阵列，像素阵列包括M行、N列总计M*N个像素单元。每个像素单元均包括：相同数量的LED芯片，并且位于同一像素单元中不同LED芯片发出不同颜色光，例如，每个像素单元中均包括三个LED芯片，并且该三个LED芯片分别发出红光、绿光和蓝光。多条第一极信号走线6a沿像素单元的行方向延伸，多条第二极信号走线6b沿所述像素单元的列方向延伸。
参见图6，在像素阵列中，位于同一行的像素单元中的LED芯片R/G/B的第一极连接同一条第一极信号走线6a，位于不同行的像素单元中的LED芯片R/G/B连接不同的第一极信号走线6a。
参见图7，在像素阵列的第1行～第m行像素单元中，位于同一列像素单元中且发出相同颜色的LED芯片R/G/B的第二极连接同一条第二极信号走线6b，位于不同列像素单元中的LED芯片R/G/B连接不同第二极信号走线6b。其中，M、N为整数，m为小于M的整数。
在像素阵列的第m+1行～第M行像素单元中，位于同一列像素单元中且发出相同颜色的LED芯片R/G/B的第二极连接同一条第二极信号走线6b，位于不同列像素单元中的LED芯片R/G/B连接不同第二极信号走线6b。
位于第1行～第m行像素单元中的LED芯片R/G/B的第二极所连接的第二极信号走线6b，与位于第m+1行～第M行像素单元中的LED芯片5的第二极所连接的第二极信号走线6b为不同的信号走线。
需要说明的是，附图中仅示意性画出了像素阵列包括4行、4列共计16个像素单元PX，且每个像素单元PX包括三个LED芯片R/G/B且三个LED芯片R/G/B分别为红色LED芯片R、绿色LED芯片G和蓝色LED芯片B的情况，其不会对本公开的技术方案产生限制。另外，在一个像素单元中，绿色LED芯片G和蓝色LED芯片B沿列方向设置，且绿色LED芯片G和蓝色LED芯片B位于红色LED芯片R左侧的情况，仅起到示意性作用，其也不会对本公开的技术方案产生限制。在本公开中，对于一个像素单元所包括的LED芯片的数量以及各LED芯片的排布方式均不作限定。
以6和图7中所示情况为例，像素阵列中包括3M*N个LED芯片 R/G/B，需要布置M条第一极信号走线6a和6N条第二极信号走线6b。
可选地，m＝INT(M/2)，INT(M/2)表示对M/2的值进行取整。
连接位于第1行～第m行像素单元中的LED芯片R/G/B的第一极信号走线6a，其第一端延伸至玻璃衬底3远离PCB板4的一侧表面的第一侧边缘(通过相应连接元件连接至对应第一选定区域中的第一导电连接元件)。连接位于第m+1行～第M行像素单元中的LED芯片R/G/B的第一极信号走线6a，其第一端延伸至玻璃衬底3远离PCB板4的一侧表面的第二侧边缘(通过相应连接元件连接至对应第一选定区域中的第二导电连接元件)。连接位于第1行～第m行像素单元中的LED芯片R/G/B的第二极信号走线6b，其第一端延伸至玻璃衬底3远离PCB板4的一侧表面的第三侧边缘(通过相应连接元件连接至对应第三选定区域中的第一导电连接元件)。连接位于第m+1行～第M行像素单元中的LED芯片R/G/B的第二极信号走线6b，其第一端延伸至玻璃衬底3远离PCB板4的一侧表面的第四侧边缘(通过相应连接元件连接至对应第一选定区域中的第四导电连接元件)。其中，第一侧边缘和第二侧边缘为在行方向上相对的两侧边缘，第三侧边缘和第四侧边缘为在列方向上相对的两侧边缘。
在附图中，第一侧边缘和第二侧边缘分别为附图中的左侧边缘和右侧边缘，第三侧边缘和第四侧边缘分别为附图中的上侧边缘和下侧边缘。
此时，玻璃衬底3的四侧边缘均有第一信号走线6引出。具体地，在M条第一极信号走线6a中，一半的第一极信号走线6a从玻璃衬底3的左侧边缘引出，另一半的第一极信号走线6a从玻璃衬底3的右侧边缘引出。在6N条第二极信号走线6b中，一半的第二极信号走线6b从玻璃衬底3的上侧边缘引出，另一半的第二极信号走线6b从玻璃衬底3的下侧边缘引出。
基于上述布线方式，可使得玻璃衬底3左边边缘区域与右侧边缘区域布线数量相等，玻璃衬底3上侧边缘区域和下侧边缘区域布线数量相同，从而能效提升玻璃衬底3的边缘区域的布线均匀性。
另外，通过将显示基板的上半部分区域和下半部分区域配置不 同的第二极信号走线6b进行信号传输，可有效缩短各第二极信号走线6b的布线长度，从而能降低各第二极信号走线6b的电阻，进而提升第二极信号走线6b的信号传输质量。
图8为本公开中第一导电连接元件的一种俯视图，如图8所示，进一步地，当LED显示基板1中存在第一导电连接元件7且第一导电连接元件7位于玻璃衬底3朝向PCB板4的一侧表面时(即LED显示基板1为图1-图2中所示显示装置中的LED显示基板1)，第一导电连接元件7的可采用如下排布方式。
在玻璃衬底3的朝向PCB板4的一侧的表面至少划分为彼此分隔开的第一选定区域、第二选定区域、第三选定区域和第四选定区域。第一选定区域、第二选定区域、第三选定区域和第四选定区域中均设置有均匀分布的选定数量的第一导电连接元件，并且每个选定区域中的选定数量的第一导电连接元件分别通过对应中间导电连接元件(或通过中间导电连接元件和第二信号走线)而与选定数量的第一信号走线电连接。第一选定区域和第二选定区域位于玻璃衬底3的朝向PCB板4的一侧的表面的靠近玻璃衬底3的相对两侧的边缘。第一选定区域和第二选定区域分别邻近其所在表面的相对的两个边缘，即第三选定区域和第四选定区域位于玻璃衬底3的朝向PCB板4的一侧的表面的靠近玻璃衬底3的相对两侧的边缘。第三选定区域和第四选定区域分别邻近其所在表面的相对的另外两个边缘，即第一选定区域和第二选定区域靠近的玻璃衬底的相对两侧(沿像素阵列的行方向)的边缘不同于第三选定区域和第四选定区域靠近的玻璃衬底的相对两侧(沿像素阵列的列方向)的边缘。
参见图8，与连接位于第1行～第m行像素单元中的LED芯片5的第一极信号走线6a相对应的第一导电连接元件7a，其位于玻璃衬底3朝向PCB板4的一侧且靠近玻璃衬底3的第一侧边缘的第一选定区域16a内。与连接位于第m+1行～第M行像素单元中的LED芯片5的第一极信号走线6a相对应的第一导电连接元件7b，其位于玻璃衬底3朝向PCB板4的一侧且靠近玻璃衬底3的第二侧边缘的第二选定区域16b内。与连接位于第1行～第m行像素单元中的LED芯片5 的第二极信号走线6b相对应的第一导电连接元件7c，其位于玻璃衬底3朝向PCB板4的一侧且靠近玻璃衬底3的第三侧边缘的第三选定区域16c内。与连接位于第m+1行～第M行像素单元中的LED芯片5的第二极信号走线6b相对应的第一导电连接元件7d，其位于玻璃衬底3朝向PCB板4的一侧且靠近玻璃衬底3的第四侧边缘的第四选定区域16d内。
在本公开中，将第一导电连接元件7a/7b/7c/7d和该第一导电连接元件7a/7b/7c/7d所电连接的第一信号走线6的第一端位于玻璃衬底3上的相同侧边缘，可有效缩短用于电连接第一信号走线6的第一端与对应的第一导电连接元件7a/7b/7c/7d的中间导电连接元件17的长度，从而能降低生产成本。
另外，在将玻璃衬底3上的第一导电连接元件7a/7b/7c/7d与位于PCB板4上的第二导电连接元件8连接时，玻璃衬底3的四侧边缘均会与PCB板4进行固定，从而能提升LED显示基板1与驱动基板2之间连接的牢固度。
进一步可选地，位于玻璃衬底3朝向PCB板4的一侧且靠近玻璃衬底3的第一侧边缘的全部第一导电连接元件7a在第一选定区域16a内均匀排布。
位于玻璃衬底3朝向PCB板4的一侧且靠近玻璃衬底3的第二侧边缘的全部第一导电连接元件7b在第二选定区域16b内均匀排布。
位于玻璃衬底3朝向PCB板4的一侧且靠近玻璃衬底3的第三侧边缘的全部第一导电连接元件7c在第三选定区域16c内均匀排布。
位于玻璃衬底3朝向PCB板4的一侧表面且靠近第四侧边缘的区域的全部第一导电连接元件7d在第四选定区域16d内均匀排布。
在本公开中，通过将靠近第一侧边缘的全部第一导电连接元件7a在第一选定区域16a内均匀排布，将靠近第二侧边缘的全部第一导电连接元件7b在第二选定区域16b内均匀排布，将靠近第三侧边缘的全部第一导电连接元件7c在第三选定区域16c内均匀排布，将靠近第四侧边缘的全部第一导电连接元件7d在第四选定区域16d内均匀排布，可使得各选定区域内的第一导电连接元件7a/7b/7c/7d 均是均匀排布的。这样的设计，可以使得第一导电连接元件7a/7b/7c/7d的尺寸可以做大一些，以改善因玻璃衬底3与PCB板4对位偏差造成的短接或虚接的问题。
需要说明的是，图8中所示在第一选定区域16a内和第二选定区域16b内，第一导电连接元件7a/7b沿列方式排布且相邻第一连接导电连接元件之间距离相等的情况，仅为实现均匀排布的一种可选方式，其不会对本公开的技术方案产生限制。
另外，图8中所示在第三选定区域16c和第四选定区域16d内，第一导电连接元件7c/7d排布呈三行，且相邻行中第一连接导电连接结构错位的情况，仅为实现均匀排布的一种可选方式，其不会对本公开的技术方案产生限制。
需要说明的是，当LED显示基板1为图4所示显示装置中的LED显示基板1时，位于LED显示基板远离PCB板4一侧的第一导电连接元件的排布也可以为图8中所示情况,不同之处在于第一选定区域、第二选定区域、第三选定区域和第四选定区域位于LED显示基板1的第二周边区域中，此处不再赘述。
另外，本公开中的显示基板可以包括多个LED显示基板，多个LED显示基板位于同一平面上，以构成拼接LED显示装置。同理，驱动基板的数量可以为1个或多个。作为一种可选实施方案，驱动基板的数量为1个，多个LED显示基板对应同一个大尺寸的驱动基板。作为另一种可选实施方案，驱动基板的数量为多个，多个LED显示基板与多个驱动基板一一对应。对于其他情况，此处不再一一举例描述。
当LED显示基板数量为多个时，这些LED显示基板可使用同一层保护胶以进行封装。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (18)

  1. 一种LED显示装置，包括：相对设置的LED显示基板和驱动基板；
    所述LED显示基板包括：衬底和多个LED芯片，所述多个LED芯片位于所述衬底远离所述驱动基板的一侧；
    所述驱动基板包括：PCB板和驱动控制器件，所述驱动控制器件位于所述PCB板上，所述驱动控制器件通过多条第一信号走线与所述多个LED芯片电连接以向各LED芯片提供驱动信号。
  2. 根据权利要求1所述的LED显示装置，其中，所述多条第一信号走线位于所述衬底的远离所述驱动基板的一侧上。
  3. 根据权利要求2所述的LED显示装置，其中，所述LED显示基板还包括多个第一导电连接元件，所述多个第一导电连接元件位于所述衬底上并且与所述多条第一信号走线一一对应电连接；
    所述驱动基板还包括多个第二导电连接元件，所述多个第二导电连接元件位于所述PCB板朝向所述衬底的一侧的多个第二导电连接元件，并且所述多个第二导电连接元件与所述驱动控制器件电连接；
    其中，所述多个第二导电连接元件与所述多个第一导电连接元件一一对应电连接。
  4. 根据权利要求3所述的LED显示装置，其中，所述多个第一导电连接元件位于所述衬底朝向所述PCB板的一侧，
    所述LED显示基板还包括多个中间导电连接元件，其中所述多个第一导电连接元件分别通过所述多个中间导电连接元件与所述多条第一信号走线电连接。
  5. 根据权利要求4所述的LED显示装置，其中，所述多个中间 导电连接元件包括导电胶、金属走线和FPC板中的至少一种。
  6. 根据权利要求4所述的LED显示装置，其中，所述衬底的朝向所述PCB板的一侧的表面包括彼此分隔开的第一选定区域、第二选定区域、第三选定区域和第四选定区域，
    其中，所述第一选定区域、所述第二选定区域、所述第三选定区域和所述第四选定区域中均具有均匀分布的选定数量的第一导电连接元件，并且每个选定区域中的选定数量的第一导电连接元件分别通过所述中间导电连接元件而与选定数量的第一信号走线电连接。
  7. 根据权利要求6所述的LED显示装置，其中，
    所述第一选定区域和所述第二选定区域分别邻近其所在表面的相对的两个边缘，
    所述第三选定区域和所述第四选定区域分别邻近其所在表面的相对的另外两个边缘。
  8. 根据权利要求4-7中任一项所述的LED显示装置，还包括保护胶层，其中，所述保护胶层覆盖所述多个LED芯片、所述多条第一信号走线和所述多个中间导电连接元件的位于所述衬底远离所述PCB板的一侧的部分。
  9. 根据权利要求3所述的LED显示装置，其中，所述PCB板包括第一中心区域和围绕所述第一中心区域的第一周边区域，所述LED显示基板位于在所述PCB板的第一中心区域中。
  10. 根据权利要求9所述的LED显示装置，其中，所述第二导电连接元件位于所述第一周边区域中，且所述多个第一导电连接分别与所述多个第二导电连接元件通过导电跳线电连接。
  11. 根据权利要求10所述的LED显示装置，其中，所述LED显 示基板包括第二中心区域和第二周边区域，所述多个LED芯片位于所述第二中心区域中，并且所述第一导电连接元件位于所述第二周边区域中，
    其中，所述第二周边区域包括彼此分隔开的第一选定区域、第二选定区域、第三选定区域和第四选定区域，
    所述第一选定区域、所述第二选定区域、所述第三选定区域和所述第四选定区域中均具有均匀分布的选定数量的第一导电连接元件，并且每个选定区域中的选定数量的第一导电连接元件通过导电跳线而分别与选定数量的第一信号走线电连接，
    其中，所述第一选定区域和所述第二选定区域分别邻近其所在表面的相对的两个边缘，所述第三选定区域和所述第四选定区域分别邻近其所在表面的相对的另外两个边缘。
  12. 根据权利要求11所述的LED显示装置，还包括保护胶层，其中，所述保护胶层覆盖所述多个LED芯片、所述多条第一信号走线、所述多个第一导电连接元件、所述多个第二导电连接元件以及所述导电跳线。
  13. 根据权利要求7或11所述的LED显示装置，其中，所述多条第一信号走线包括与所述多个LED芯片的第一极连接的多条第一极信号走线，以及与所述多个LED芯片的第二极连接的多条第二极信号走线；
    全部所述多条第一极信号走线同层设置，全部所述多条第二极信号走线同层设置，所述多条第一极信号走线与所述多条第二极信号走线异层设置。
  14. 根据权利要求13所述的LED显示装置，其中，所述多个LED芯片构成像素阵列，所述像素阵列包括M行、N列总计M*N个像素单元，所述像素单元中的每一个中的LED芯片的数量相同并且位于同一像素单元中的不同LED芯片发出不同颜色的光；所述多条第一极信号 走线沿所述像素单元的行方向延伸，所述多条第二极信号走线沿所述所述像素单元的列方向延伸，
    所述像素阵列的第1行～第m行像素单元中的每一行像素单元中的LED芯片的第一极连接至同一条第一极信号走线，并且与所述像素阵列的第1行～第m行像素单元连接的多条第一极信号走线通过相应的连接元件与所述第一选定区域中的第一导电连接元件电连接；
    所述像素阵列的第m+1行～第M行像素单元中的每一行像素单元中的LED芯片的第一极均连接所述多条第一极信号走线中的相应一条，并且与所述像素阵列的第m+1行～第M行像素单元连接的多条第一极信号走线通过相应的连接元件与所述第二选定区域中的第一导电连接元件电连接；
    所述像素阵列的第1行～第m行像素单元中的每一列像素单元中的LED芯片中的发相同颜色光的LED芯片的第二极连接至同一条第二极信号走线，并且与所述像素阵列的第1行～第m行像素单元连接的多条第二极信号走线通过相应的连接元件与所述第三选定区域中的第一导电连接元件电连接；
    所述像素阵列的第m+1行～第M行像素单元中的LED芯片每一列像素单元中的LED芯片中的发相同颜色光的LED芯片的第二极连接至同一条第二极信号走线，并且与所述像素阵列的第m+1行～第M行像素单元连接的多条第二极信号走线通过相应的连接元件与所述第四选定区域中的第一导电连接元件电连接，其中，M、N为整数，m为小于M的整数。
  15. 根据权利要求14所述的LED显示装置，其中，m＝INT(M/2)，INT(M/2)表示对M/2的值进行取整。
  16. 根据权利要求1所述的LED显示装置，其中，所述LED芯片为LED倒装芯片。
  17. 根据权利要求3所述的LED显示装置，其中，所述第一导电 连接元件和所述第二导电连接元件均为焊盘。
  18. 根据权利要求1所述的LED显示装置，其中，所述衬底为玻璃衬底。
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