WO2020140618A1 - 显示基板及其制造方法、修复方法、显示装置 - Google Patents

显示基板及其制造方法、修复方法、显示装置 Download PDF

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Publication number
WO2020140618A1
WO2020140618A1 PCT/CN2019/117621 CN2019117621W WO2020140618A1 WO 2020140618 A1 WO2020140618 A1 WO 2020140618A1 CN 2019117621 W CN2019117621 W CN 2019117621W WO 2020140618 A1 WO2020140618 A1 WO 2020140618A1
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Prior art keywords
line
common electrode
target
gate
lines
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PCT/CN2019/117621
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English (en)
French (fr)
Inventor
欧阳义
于冰洋
朱金伟
权南仁
王桂兵
白同举
何志瑞
杨斌
刘群
薛国彬
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US16/761,830 priority Critical patent/US11131893B2/en
Publication of WO2020140618A1 publication Critical patent/WO2020140618A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/166—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect
    • G02F1/167—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect by electrophoresis
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present application relates to a display substrate, its manufacturing method, repair method, and display device.
  • the main display component of the display device is a display substrate, and the performance of the display substrate directly affects the performance of the display device.
  • the present application provides a display substrate, a manufacturing method thereof, a repair method, and a display device.
  • the technical solution is as follows:
  • a display substrate including:
  • a base substrate and multiple gate lines, multiple data lines, multiple common electrode lines, and multiple common electrodes on the base substrate;
  • the plurality of gate lines and the plurality of data lines intersect to define a plurality of pixel areas, the plurality of common electrodes are located in the plurality of pixel areas in a one-to-one correspondence, the plurality of gate lines and the plurality of data lines
  • the extension directions of the common electrode lines are parallel, and the plurality of grid lines and the plurality of common electrode lines are arranged at intervals;
  • the common electrode line includes a plurality of target lead segments and a non-target lead segment, each segment of the target lead segment is a lead segment where the common electrode line crosses one data line, and the non-target lead segment is the common
  • the distance between any position point on the target wire segment and the target grid line is less than the non-target wire segment and all The distance between the target grid lines, the target grid lines being the grid lines closest to the common electrode lines, the common electrodes located on both sides of the target grid lines and adjacent to the target grid lines Both are connected to the common electrode line.
  • the target wire segment is bent toward the target grid line.
  • the target wire segment is an arc-shaped wire segment.
  • the plurality of common electrodes are arranged in multiple rows along the scanning direction of the data line, and for each common electrode line: the common electrode line is connected to the target common electrode and passes through the target gate line
  • the bridge line is connected to the common electrode adjacent to the target common electrode and located in the same row.
  • the target common electrode and the common electrode line are in the same pixel area.
  • the distance between one of the gate lines and the common electrode line is smaller than the other of the gate lines and the common electrode The distance between lines.
  • the display substrate further includes: a plurality of thin film transistors and a plurality of pixel electrodes, and the plurality of thin film transistors and the plurality of pixel electrodes are respectively located in the plurality of pixel regions in one-to-one correspondence, and the thin film
  • the transistor includes a gate, a source, and a drain, the gate is connected to the gate line closest to the gate, the source is connected to the data line closest to the source, and the drain The electrode is connected to the pixel electrode in the same pixel area as the thin film transistor.
  • the thin film transistor includes: the gate, the gate insulating layer, the active layer, the interlayer dielectric layer, and the source and drain that are sequentially distributed in a direction away from the base substrate
  • the source electrode and the drain electrode, the source electrode and the drain electrode are not in contact, and the source electrode and the drain electrode are in active layer contact;
  • the array substrate further includes: an insulating layer between the common electrode and the gate line, and a passivation layer between the source and drain electrodes and the pixel electrode.
  • the distance between one of the gate lines and the common electrode line is smaller than the other of the gate lines and the common electrode
  • the distance between the lines, the plurality of common electrodes are arranged in multiple lines along the data line scanning direction, and for each of the common electrode lines: the target wire segment is an arc curved toward the target grid line Shaped wire section, the common electrode line is connected to the target common electrode, and is connected to the common electrode adjacent to the target common electrode and located in the same row through a bridge line crossing the target gate line, the target common electrode is connected to The common electrode lines are in the same pixel area;
  • the display substrate further includes: a plurality of thin film transistors, a plurality of pixel electrodes, an insulating layer, and a passivation layer, and the plurality of thin film transistors and the plurality of pixel electrodes are respectively located in the plurality of pixel regions in one-to-one correspondence,
  • the thin film transistor includes a gate, a gate insulating layer, an active layer, an interlayer dielectric layer, and a source and drain that are sequentially distributed in a direction away from the base substrate.
  • the source and drain include a source and a drain.
  • the source electrode and the drain electrode are not in contact, the source electrode and the drain electrode are in contact with the active layer, the gate is connected to the gate line closest to the gate, and the source An electrode is connected to the data line closest to the source, the drain is connected to the pixel electrode in the same pixel area as the thin film transistor, and the insulating layer is located at the common electrode and the gate line Between, the passivation layer is located between the source and drain and the pixel electrode.
  • a method for manufacturing a display substrate includes:
  • Multiple gate lines, multiple data lines, multiple common electrode lines and multiple common electrodes are formed on the base substrate;
  • the plurality of gate lines and the plurality of data lines intersect to define a plurality of pixel areas, the plurality of common electrodes are located in the plurality of pixel areas in a one-to-one correspondence, the plurality of gate lines and the plurality of data lines
  • the extending direction of the common electrode line is parallel, and the plurality of grid lines and the plurality of common electrode lines are arranged at intervals;
  • the common electrode line includes a plurality of target lead segments and a non-target lead segment, each segment of the target lead A segment is a wire segment where the common electrode line crosses one data line, and the non-target wire segment is a wire segment other than the target wire segment on the common electrode line, for each of the common electrodes Line: the distance between any point on the target wire segment and the target grid line is less than the distance between the non-target wire segment and the target grid line, the target grid line is the closest to the common electrode line Of the gate lines, the common electrodes located on both sides of the target gate line and adjacent to the target gate line are connected to
  • the formation of multiple gate lines, multiple data lines, multiple common electrode lines and multiple common electrodes on the base substrate includes:
  • the plurality of data lines are formed on the base substrate on which the gate lines and the common electrode lines are formed, the plurality of data lines and each of the plurality of target lead segments of each of the common electrode lines A cross.
  • the target wire segment is curved toward the target grid line.
  • the target wire segment is an arc-shaped wire segment.
  • the plurality of common electrodes are also arranged in multiple rows in an array, and for each common electrode line: the common electrode line is connected to the target common electrode, and is connected by a bridge line that crosses the target gate line and The common electrodes adjacent to the target common electrode and located in the same row are connected, and the target common electrode and the common electrode line are in the same pixel area.
  • the distance between one of the gate lines and the common electrode line is smaller than the other of the gate lines and the common electrode The distance between lines.
  • the method further includes:
  • a plurality of thin film transistors and a plurality of pixel electrodes are formed on the base substrate, the plurality of thin film transistors and the plurality of pixel electrodes are respectively located in the plurality of pixel regions in one-to-one correspondence, and the thin film transistor includes a gate Electrode, source and drain, the gate is connected to the gate line closest to the gate, the source is connected to the data line closest to the source, the drain is connected to The pixel electrodes of the thin film transistors located in the same pixel area are connected.
  • the thin film transistor includes: the gate, the gate insulating layer, the active layer, the interlayer dielectric layer, and the source and drain that are sequentially distributed in a direction away from the base substrate
  • the source electrode and the drain electrode, the source electrode and the drain electrode are not in contact, and the source electrode and the drain electrode are in active layer contact;
  • the method also includes:
  • a passivation layer is formed between the source and drain electrodes and the pixel electrode.
  • a method for repairing a display substrate for the display substrate described in the above aspect or any optional manner of the aspect, the method including:
  • the first repair point and the second repair point are determined according to the break point of the first data line, the first repair point is the intersection of the first common electrode line and the first data line , The second repair point is the intersection of the second common electrode line and the first data line, the first common electrode line is adjacent to the second common electrode line and arranged in sequence along the scanning direction of the gate line, The breaking point is between the first common electrode line and the second common electrode line;
  • a plurality of cutting points are determined according to the first repair point and the second repair point, the plurality of cutting points including: a first cutting point on two segments of the first target wire segment, and a second cutting point on the two segments of the second target wire segment Two cutting points, a third cutting point on the connection line between the first common electrode line and the first common electrode, and a fourth cutting point on the connection line between the third common electrode line and the second common electrode, the two The first target wire segment is a target wire segment where the first data line crosses the first common electrode line and a target wire segment where the first data line crosses the second common electrode line, the two The second target wire segment is a target wire segment where a second data line crosses the first common electrode line and a target wire segment where the second data line crosses the second common electrode line, the second data The line is the last data line of the first data line, the first common electrode, the third common electrode, and the second common electrode are adjacent to each other and are sequentially arranged in the same row along the scanning direction of the gate line.
  • the third common electrode is located in the pixel area surrounded by the first gate line, the second gate line, the first data line and the second data line, the first gate line corresponds to the first common electrode line Target gate line, the second gate line is the target gate line corresponding to the second common electrode line, the second common electrode line is adjacent to the third common electrode line and is sequentially arranged along the scanning direction of the gate line cloth;
  • a corresponding common wire is cut from each of the cutting points, and the common wire includes the first target wire segment, the second target wire segment, and the connection line.
  • the first cutting point is located on the two first target wire segments and behind the first data line;
  • the second cutting point is located on the two segments of the second target wire segment and behind the second data line;
  • the third cutting point is located on the bridge line between the first common electrode line and the first common electrode;
  • the fourth cutting point is located on the bridge line between the third common electrode line and the second common electrode.
  • the connecting the first data line with the first common electrode line from the first repair point includes:
  • the connecting the first data line and the second common electrode line from the second repair point includes:
  • the first data line and the second common electrode line are welded from the second repair point.
  • cutting the corresponding common wire from each of the cutting points includes: cutting the corresponding common wire from each of the cutting points through a laser cutting process.
  • a display device including the display substrate described in the above aspect or any optional manner of the aspect.
  • FIG. 1 is a front view of a display substrate involved in an embodiment of the present application
  • FIG. 2 is a front view of another display substrate involved in an embodiment of the present application.
  • FIG. 3 is a front view of a display substrate provided by an embodiment of the present application.
  • FIG. 4 is an enlarged view of the area Q of the display substrate shown in FIG. 3;
  • FIG. 5 is a cross-sectional view of a display substrate provided by an embodiment of the present application.
  • FIG. 6 is a front view of another display substrate provided by an embodiment of the present application.
  • FIG. 7 is a flowchart of a method for manufacturing a display substrate provided by an embodiment of the present application.
  • FIG. 8 is a flowchart of another method for manufacturing a display substrate provided by an embodiment of the present application.
  • FIG. 9 is a flowchart of a method for repairing a display substrate provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of repairing a display substrate provided by an embodiment of the present application.
  • FIG. 11 is a front view of a repaired display substrate provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a transmission path of a signal on a data line after repair provided by an embodiment of the present application.
  • FIG. 1 shows a schematic diagram of a front view structure of a display substrate 1 according to an embodiment of the present application.
  • the display substrate 1 includes a base substrate 10, and a plurality of strips located on the base substrate 10
  • the gate lines 11, the plurality of data lines 12, and the plurality of common electrode lines 13, the plurality of common electrode lines 13 are parallel to the plurality of gate lines 11, and the common electrode lines 13 and the gate lines 11 are arranged at intervals, and the plurality of gate lines 11 crosses a plurality of data lines 12 to define a plurality of pixel regions (not shown in FIG.
  • the display substrate 1 further includes a plurality of common electrodes 14 and a plurality of thin film transistors corresponding to each of the plurality of pixel regions ( English: Thin Film Transistor; TFT for short) 15 and multiple pixel electrodes (not shown in FIG. 1).
  • the data line 12 and the common electrode line 13 can be welded at the intersection of the data line 12 and the common electrode line 13 so that the signal on the data line 12 is wound through the common electrode line 13 Transmission through the break point, so as to achieve the effect of repairing the data line 12.
  • the distance between the common electrode 14 and the intersection position is small, and the distance is usually 3.5 um (micrometers), which results in insufficient welding work space and difficult welding work. Therefore, the success rate of data line repair is low.
  • FIG. 2 illustrates a schematic front view of another display substrate 2 according to an embodiment of the present application.
  • the display substrate 2 includes a base substrate 20, and, A plurality of gate lines 21, a plurality of data lines 22, a plurality of common electrode lines 23, a plurality of common electrodes 24, a plurality of TFT 25 and a plurality of pixel electrodes (not shown in FIG. 2) on the base substrate 20, each A corner of the common electrode 24 near the intersection of the common electrode line 23 and the data line 22 has a gap K, so that the distance between each common electrode 24 and the intersection position is relatively large, which is usually 7.0 Um can facilitate the implementation of welding work.
  • the aperture ratio of the display substrate is directly related to the effective display area of the common electrode (for example, the area facing the common electrode and the pixel electrode).
  • the gap K will cause the effective display area of the common electrode 24 Since it is small, the aperture ratio of the display substrate 2 is low.
  • Embodiments of the present application provide a display substrate, a manufacturing method, a repair method, and a display device.
  • the distance between any point on the target wire segment and the target grid line is less than The distance between the target wire segment and the target grid line
  • the target wire segment is a wire segment that crosses the common electrode line and the data line
  • the non-target wire segment is a wire other than the target wire segment on the common electrode line
  • the distance between the common electrode and the target conductive line can be made larger, so that the common electrode and the intersection position (referring to the intersection of the common electrode line and the data line The distance between positions) is large, which is convenient for the implementation of welding work, the success rate of repairing the data line is high, and the opening rate of the display substrate is high.
  • the following embodiments please refer to the following embodiments.
  • FIG. 3 is a front view of a display substrate 3 provided by an embodiment of the present application
  • FIG. 4 is an enlarged view of a region Q of the display substrate 3 shown in FIG. 3
  • FIG. 5 is a display substrate 3 provided by an embodiment of the present application 3 to 5
  • the display substrate 3 includes: a base substrate 30, and a plurality of gate lines 31, a plurality of data lines 32, a plurality of common electrode lines 33 and a plurality of gate lines 31 on the base substrate 30 A common electrode 34; a plurality of gate lines 31 and a plurality of data lines 32 intersect to define a plurality of pixel regions (not shown in FIGS.
  • each pixel region is composed of two adjacent gate lines 31 and Two adjacent data lines 32 are enclosed, a plurality of common electrodes 34 are correspondingly located in the plurality of pixel regions, a plurality of gate lines 31 and a plurality of common electrode lines 33 extend in parallel, a plurality of gate lines 31 are A plurality of common electrode lines 33 are arranged at intervals.
  • each common electrode line 33 includes a plurality of target lead segments 331 and a non-target lead segment (not shown in FIGS. 3 and 4 ), and each target lead segment 331 is the common electrode line 33 is a wire segment crossing a data line 32, and the non-target wire segment is a wire segment on the common electrode line 33 except for the plurality of target wire segments 331.
  • the distance L1 between any point on the target wire segment 331 and the target grid line is less than the distance L2 between the non-target wire segment and the target grid line
  • the target grid line is the distance from the common electrode
  • the gate line 31 closest to the line 33 is connected to the common electrode line 33 on both sides of the target gate line and the common electrode 34 adjacent to the target gate line.
  • the target lead segment 331 is connected to the non-target lead segment, and the distance between the position on the target lead segment 331 at the connection location and the target grid line may be the target The maximum distance between the wire segment 331 and the target grid line, and at this connection location, the distance between the target wire segment 331 and the target grid line may be equal to the distance between the non-target wire segment and the target grid line, embodiments of the present application.
  • any position on the target wire segment 331 refers to a position on the target wire segment 331 except for the connection point with the non-target wire segment
  • FIG. 6 shows a front view of another display substrate 3 provided by an embodiment of the present application.
  • the target gate line is the gate line 31a
  • the The common electrode line 33a includes a plurality of target lead segments 331a and non-non-target lead segments (none of which are marked in FIG. 6), and the distance between any point on the target lead segment 331a and the gate line 31a (none in FIG. 6) (Marked) is less than the distance between the non-target wire segment on the common electrode line 33a and the gate line 31a (neither marked in FIG. 6), and the common electrode 34 located on both sides of the gate line 31a and adjacent to the gate line 31a Both are connected to the common electrode line 33a.
  • the display substrate for each common electrode line, the distance between any point on the target wire segment and the target grid line is less than the distance between the non-target wire segment and the target grid line Distance, the target wire segment is the wire segment where the common electrode line crosses the data line, and the non-target wire segment is the wire segment other than the target wire segment on the common electrode line, so the display substrate does not change the area of the common electrode Under the premise of, the distance between the common electrode and the target conductive line is large, so that the distance between the common electrode and the intersection position (referring to the intersection position of the common electrode line and the data line) is relatively large, which is convenient for welding Implemented, the success rate of repairing the data line is high and the aperture ratio of the display substrate is high.
  • the distance between one gate line 31 and the common electrode line 33 is smaller than the other gate line 31 and the common The distance between the electrode wires 33.
  • the two gate lines adjacent to the common electrode line 33a include a gate line 31a and a gate line 31b, and among the two gate lines, the distance between the gate line 31a and the common electrode line 33a Less than the distance between the gate line 31b and the common electrode line 33a.
  • the target wire segment 331 is bent toward the target grid line; alternatively, the target wire segment 331 may be an arc-shaped wire segment.
  • the multiple common electrodes 34 are arranged in multiple columns along the gate line scanning direction x, and are arranged in multiple rows along the data line scanning direction y, and the column direction is perpendicular to the gate line scanning direction x, The row direction is perpendicular to the data line scanning direction y.
  • the common electrode line 33 is connected to the target common electrode, and is adjacent to and located in the same row as the target common electrode through a bridge line 39 crossing the target gate line
  • the common electrode 34 is connected.
  • each part of the common electrode line 33 is in the pixel area, and the part of each common electrode line 33 in the pixel area is connected to the target common electrode, and is adjacent to the target common electrode through a bridge line 39 crossing the target gate line and The common electrodes 34 in the same row are connected, and the target common electrode is a common electrode in the same pixel area as the common electrode line 33.
  • the display substrate 3 further includes: a plurality of TFTs 35 and a plurality of pixel electrodes 36, and the plurality of TFTs 35 and the plurality of pixel electrodes 36 respectively correspond to the plurality of pixel regions 5, as shown in FIG.
  • each TFT 35 includes a gate 351, a gate insulating layer 352, an active layer 353, an interlayer dielectric layer 354, and a source and drain that are sequentially distributed in a direction away from the base substrate 30 Including source 355 and drain 356, source 355 and drain 356 are not in contact, source 355 and drain 356 are respectively in contact with active layer 353, gate 351 is connected to gate line 31 closest to the gate 351, the source The electrode 355 is connected to the data line 32 closest to the source electrode 355, and the drain electrode 356 is connected to the pixel electrode 36 of the TFT 35 located in the same pixel region.
  • the gate line 31, the common electrode line 33 and the gate 351 are distributed in the same layer.
  • the display substrate 3 further includes an insulating layer 37 between the common electrode 34 and the gate line 31, and The passivation layer 38 between the source and drain and the pixel electrode 36.
  • the structure of the different layer distribution may be connected through vias, for example, the common electrode line 33 and the common electrode 34 are distributed in different layers, and the common electrode line 33 may be connected to the common electrode 34 through the via on the insulating layer 37 (Not shown in FIG.
  • the source and drain are distributed in different layers from the active layer 353, and the source 355 and the drain 356 are connected to the active layer 353 through vias in the interlayer dielectric layer 354, and
  • the pixel electrode 36 and the drain electrode 356 are distributed in different layers, and the pixel electrode 36 is connected to the drain electrode 356 through the via hole in the passivation layer 38.
  • the embodiments of the present application will not list them here.
  • the display substrate 3 may be an advanced super-dimensional field conversion (English: Advanced Super Dimension Switch; abbreviated: ADS) type display substrate, as shown in FIG. 5, the pixel electrode 36 may be a slit electrode (that is, a pixel electrode 36 has a slit), the existence of the slit can facilitate the formation of a voltage between the common electrode 34 and the pixel electrode 36.
  • ADS Advanced Super Dimension Switch
  • the base substrate 30 may be a transparent substrate, for example, it may be a rigid substrate made of glass, quartz, transparent resin, or other light-guiding and non-metallic materials with certain rigidity, or the base substrate 30 may be Flexible substrate made of flexible materials such as polyimide (English: Polyimide; abbreviation: PI); the gate line 31, the common electrode line 33 and the gate 351 can be made by the same patterning process, and the gate line 31 and the common electrode line The materials of the 33 and the gate 351 can be the same.
  • polyimide English: Polyimide; abbreviation: PI
  • the gate line 31, the common electrode line 33 and the gate 351 can be made by the same patterning process, and the gate line 31 and the common electrode line
  • the materials of the 33 and the gate 351 can be the same.
  • the materials of the gate line 31, the common electrode line 33, and the gate 351 can all be metal Mo (Chinese: molybdenum), metal Cu (Chinese: copper), Metal Al (Chinese: aluminum), metal Ti (Chinese: titanium) and their alloy materials;
  • the data line 32, the source electrode 355, the drain electrode 356, and the bridge wiring 39 can be made by the same patterning process, and the data line 32, the source electrode The materials of the four of 355, the drain 356, and the bridge 39 can be the same.
  • the materials of the four of the data line 32, the source 355, the drain 356, and the bridge 39 can be metal Mo, metal Cu, metal Al, Metal Ti and its alloy materials; both the common electrode 34 and the pixel electrode 36 may be transparent electrodes, and the materials of the common electrode 34 and the pixel electrode 36 may be the same or different, for example, the materials of the common electrode 34 and the pixel electrode 36 may be oxidized Indium tin (English: Indium tin oxide; referred to as: ITO), indium zinc oxide (English: Indium zinc oxide; referred to as: IZO) or aluminum-doped zinc oxide (English: aluminum-doped zinc oxide; referred to as: ZnO: Al) and other metals Oxide; the active layer 353 may be a semiconductor active layer or an oxide active layer, for example, the active layer 353 is a semiconductor active layer made of semiconductor materials such as amorphous silicon or polycrystalline silicon, or the active layer 353 Active oxide layer made of semiconductor oxides such as indium gallium zinc oxide (
  • the display substrate for each common electrode line, the distance between any point on the target wire segment and the target grid line is less than the distance between the non-target wire segment and the target grid line Distance, the target wire segment is the wire segment where the common electrode line crosses the data line, and the non-target wire segment is the wire segment other than the target wire segment on the common electrode line, so the display substrate does not change the area of the common electrode Under the premise of, the distance between the common electrode and the target conductive line is large, so that the distance between the common electrode and the intersection position (referring to the intersection position of the common electrode line and the data line) is relatively large, which is convenient for welding Implemented, the success rate of repairing the data line is high and the aperture ratio of the display substrate is high.
  • the display substrate provided by the embodiments of the present application can satisfy the photoelectric performance of the product, increase the success rate of data line repair, and improve the product yield.
  • An embodiment of the present application provides a method for manufacturing a display substrate.
  • the method includes:
  • Multiple gate lines, multiple data lines, multiple common electrode lines and multiple common electrodes are formed on the base substrate;
  • a plurality of gate lines and a plurality of data lines intersect to define a plurality of pixel areas, a plurality of common electrodes are correspondingly located in the plurality of pixel areas, a plurality of gate lines and a plurality of common electrode lines extend in parallel, a plurality of gate lines Arranged one by one with multiple common electrode wires;
  • the common electrode wire includes multiple target wire segments and non-target wire segments, each target wire segment is a wire segment where the common electrode wire crosses a data line, and the non-target wire segment is common
  • FIG. 7 shows a method flowchart of a method for manufacturing a display substrate provided by an embodiment of the present application.
  • the method may include the following steps:
  • Step 701 Form a plurality of common electrodes on the base substrate, and the plurality of common electrode arrays are arranged in multiple columns.
  • Step 702 Form a plurality of gate lines and a plurality of common electrode lines on the base substrate on which the common electrodes are formed, the plurality of gate lines and the extension directions of the plurality of common electrode lines are parallel, the plurality of gate lines and the plurality of common electrode lines Arranged one by one, there is a column of common electrodes between each adjacent two grid lines, each common electrode line includes multiple target lead segments and non-target lead segments, each target lead segment is the common electrode line and a data The wire segment where the line crosses, the non-target wire segment is a wire segment other than the target wire segment on the common electrode line.
  • the distance between any point on the target wire segment and the target grid line is less than the non-target wire segment
  • the distance between the target wire segment and the target grid line, the target grid line is the closest grid line to the common electrode line
  • the common electrodes located on both sides of the target grid line and adjacent to the target grid line are both common electrodes ⁇ Line connection.
  • Step 703 Form a plurality of data lines on the base substrate on which the gate lines and the common electrode lines are formed.
  • the plurality of gate lines and the plurality of data lines cross to define a plurality of pixel areas. In the pixel area, the multiple data lines cross the multiple target wire segments of each common electrode line one by one.
  • the distance between any point on the target lead segment and the target grid line is less than that of the non-target lead segment.
  • the distance between the target grid lines, the target wire segment is a wire segment that crosses the common electrode line and the data line
  • the non-target wire segment is a wire segment other than the target wire segment on the common electrode line, so the display substrate Without changing the area of the common electrode, make the distance between the common electrode and the target conductive line larger, so that the distance between the common electrode and the intersection position (referring to the intersection position of the common electrode line and the data line) is relatively
  • the larger size is convenient for the implementation of welding work, the success rate of repairing the data line is higher and the opening rate of the display substrate is higher.
  • the target wire segment is bent toward the target grid line.
  • the target wire segment is an arc-shaped wire segment.
  • the multiple common electrodes are also arranged in multiple rows in an array, and for each common electrode line: the common electrode line is connected to the target common electrode, and is adjacent to the target common electrode through a bridge line crossing the target gate line and The common electrodes in the same row are connected, and the target common electrode and the common electrode line are in the same pixel area.
  • the distance between one gate line and the common electrode line is smaller than the distance between the other gate line and the common electrode line.
  • the method further includes: forming a plurality of TFTs and a plurality of pixel electrodes on the base substrate, and the plurality of TFTs and the plurality of pixel electrodes are respectively located in the plurality of pixel regions one-to-one, and the TFT includes a gate and a source For the electrode and the drain, the gate is connected to the gate line closest to the gate, the source is connected to the data line closest to the source, and the drain is connected to the pixel electrode in the same pixel area as the TFT.
  • the TFT includes: a gate, a gate insulating layer, an active layer, an interlayer dielectric layer, and a source and drain that are sequentially distributed in a direction away from the base substrate.
  • the source and drain include a source and a drain, and the source and The drain is not in contact, and the active layers of the source and drain are in contact;
  • the method further includes: forming an insulating layer between the common electrode and the gate line;
  • a passivation layer is formed between the source and drain electrodes and the pixel electrode.
  • FIG. 8 shows a flowchart of another method for manufacturing a display substrate provided by an embodiment of the present application.
  • the manufacturing method of the display substrate may be used to manufacture the display substrate 3 provided in the above embodiment, see FIG. 8 ,
  • the method may include the following steps:
  • Step 801 Form a plurality of common electrodes on the base substrate, and the plurality of common electrode arrays are arranged in multiple columns.
  • a plurality of common electrodes 34 are arrayed on the base substrate 30 in multiple rows and multiple columns, the column direction may be the direction y, the row direction may be the direction x, and the row direction x is perpendicular to the column direction y.
  • the material of the common electrode 34 may be a transparent conductive material, and the transparent conductive material may be a metal oxide such as ITO, IZO, or ZnO:Al.
  • any one of the processes such as magnetron sputtering, thermal evaporation or plasma enhanced chemical vapor deposition (English: Plasma Enhanced Chemical Vapor Deposition; abbreviation: PECVD) can be used.
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • a layer of ITO is deposited on the base substrate 30 to obtain an ITO material layer, and the ITO material layer is processed through a patterning process to obtain multiple common electrodes 34.
  • Step 802 Form an insulating layer on the base substrate on which the common electrode is formed.
  • the material of the insulating layer may be a transparent insulating material, and the transparent insulating material may be an inorganic material such as SiOx, SiNx, Al 2 O 3 or SiOxNx.
  • the transparent insulating material may be an inorganic material such as SiOx, SiNx, Al 2 O 3 or SiOxNx.
  • a layer of SiOx can be deposited on the base substrate 30 on which the common electrode 34 is formed by any of processes such as magnetron sputtering, thermal evaporation, or PECVD
  • a SiOx material layer is obtained, and the SiOx material layer is processed through a patterning process to obtain an insulating layer 37.
  • Step 803 forming a plurality of gates, a plurality of gate lines and a plurality of common electrode lines on the base substrate on which the insulating layer is formed, the plurality of gate lines and the extension direction of the plurality of common electrode lines are parallel, and the plurality of gate lines are A plurality of common electrode lines are arranged at intervals, and a column of common electrodes is provided between each adjacent two grid lines.
  • the common electrode line includes a plurality of target lead segments and a non-target lead segment, and the non-target lead segment is the common electrode
  • the target The grid line is the grid line closest to the common electrode line among the multiple grid lines, and the common electrodes located on both sides of the target grid line and adjacent to the target grid line are connected to the common electrode line.
  • each common electrode line 33 includes multiple target lead segments 331 and non-target lead segments (not shown in FIG. 3).
  • the target grid line is the grid closest to the common electrode line 33 among the multiple grid lines 31
  • the common electrodes 34 located on both sides of the target gate line and adjacent to the target gate line are connected to the common electrode line 33.
  • the non-target lead segment on each common electrode line 33 is a lead segment on the common electrode line 33 except for multiple target lead segments 331.
  • the common electrode line 33 may be connected to the common electrode 34 through a bridge line 39. Exemplarily, as shown in FIG.
  • the distance between the gate line 31a and the common electrode line 33a is smaller than the distance between the gate line 31b and the common electrode line 33a.
  • the electrode line 33a includes multiple target lead segments 331a and non-target lead segments, so for the common electrode line 33a, the target grid line is the grid line 31a, and the distance between any point on the target lead segment 331a and the grid line 31a is less than the non-target lead. The distance between the segment and the gate line 31a, the common electrodes 34 located on both sides of the gate line 31a and adjacent to the gate line 31a are connected to the common electrode line 33a.
  • the gate line 31, the common electrode line 33 and the gate 351 can be fabricated through the same patterning process, and the gate line 31, the common electrode line 33 and the gate 351 are The materials of the three may be the same.
  • the materials of the gate line 31, the common electrode line 33, and the gate 351 may all be metal Mo, metal Cu, metal Al, metal Ti, and alloy materials thereof. Taking the gate line 31, the common electrode line 33, and the gate 351 through the same patterning process, and the material of the gate line 31, the common electrode line 33, and the gate 351 are all metal Mo, as shown in FIG.
  • the metal Mo material layer can be obtained by depositing a layer of metal Mo on the base substrate 30 on which the insulating layer 37 is formed by any one of processes such as magnetron sputtering, thermal evaporation, or PECVD, etc.
  • the layer is processed to obtain a plurality of gate electrodes 351, a plurality of gate lines 31 and a plurality of common electrode lines 33, and each gate 351 is connected to the gate line 31 closest to the gate electrode 351.
  • the embodiments of the present application are described by taking the gate line 31, the common electrode line 33, and the gate 351 produced by the same patterning process as an example.
  • the gate line 31 may be fabricated by three patterning processes , The common electrode line 33 and the gate electrode 351, which are not limited in this embodiment of the present application.
  • Step 804 Form a gate insulating layer on the base substrate on which the gate, the gate line, and the common electrode line are formed.
  • the material of the gate insulating layer may be a transparent insulating material, and the transparent insulating material may be an inorganic material such as SiOx, SiNx, Al 2 O 3 or SiOxNx.
  • the process of forming the gate insulating layer reference may be made to the process of forming the insulating layer 37 in step 802, and details are not described herein again in the embodiments of the present application.
  • Step 805 Form a plurality of active layers on the base substrate on which the gate insulating layer is formed, and the plurality of active layers correspond to the plurality of gates in one-to-one correspondence.
  • the material of the active layer may be a semiconductor material such as amorphous silicon or polycrystalline silicon, or the material of the active layer may be a semiconductor oxide such as IGZO or ITZO.
  • the material of the active layer as IGZO as an example, as shown in FIG. 5, one of the processes such as magnetron sputtering, thermal evaporation, or PECVD can be deposited on the base substrate 30 on which the gate insulating layer 352 is formed.
  • the IGZO layer obtains an IGZO material layer, and the IGZO material layer is processed through a patterning process to obtain a plurality of active layers 353, and the plurality of active layers 353 correspond to the plurality of gates 351 one by one.
  • Step 806 Form an interlayer dielectric layer on the base substrate on which the active layer is formed.
  • the material of the interlayer dielectric layer may be a transparent insulating material, and the transparent insulating material may be an inorganic material such as SiOx, SiNx, Al 2 O 3 or SiOxNx.
  • the process of forming the interlayer dielectric layer reference may be made to the process of forming the insulating layer 37 in step 802, and the embodiments of the present application will not repeat them here.
  • Step 807 forming a plurality of data lines and a plurality of source and drain electrodes corresponding to the plurality of active layers on the base substrate on which the interlayer dielectric layer is formed, and a plurality of data lines and a plurality of gate lines intersect to define a plurality of In a pixel area, a plurality of common electrodes, a plurality of active layers, and a plurality of source and drain electrodes are correspondingly located in the plurality of pixel areas, and a plurality of data lines cross a plurality of target wire segments of each common electrode line one by one.
  • a plurality of data lines 32 are parallel, and a plurality of data lines 32 and a plurality of gate lines 31 cross to define a plurality of pixel areas.
  • a plurality of common electrodes 34 and a plurality of active layers 353 and the plurality of source and drain are located in the plurality of pixel regions on a one-to-one basis, and the plurality of data lines 32 cross each of the plurality of target conductive line segments 331 of each common electrode line 33 one by one.
  • the source and drain include a source electrode 355 and a drain electrode 356.
  • the materials of the data line 32, the source electrode 355 and the drain electrode 356 may be the same.
  • the data line 32 and the source electrode The 355 and the drain 356 can be fabricated through the same patterning process.
  • the materials of the data line 32, the source 355, and the drain 356 can all be metal Mo, metal Cu, metal Al, metal Ti, and their alloy materials. Taking the data line 32, the source 355 and the drain 356 through the same patterning process, and the material of the data line 32, the source 355 and the drain 356 are all metal Cu as an example, as shown in FIG.
  • each source and drain includes a source 355 and a drain 356, the source 355 and the drain 356 are not in contact, the source 355 and the drain 356 respectively pass through the layer
  • the via hole of the interlayer dielectric layer 354 is in contact with the corresponding active layer 353, and each source electrode 355 is connected to the data line 32 closest to the source electrode 355.
  • the common electrode line may be connected to the common electrode through a bridge line, and the bridge line may be made through the same patterning process as the data line, so in the process of performing this step 807, a bridge line may also be formed, of course
  • the bridge wiring can also be made with data lines through different patterning processes.
  • the embodiments of the present application are described by taking the data line 32, the source electrode 355 and the drain electrode 356 manufactured by the same patterning process as an example. Those skilled in the art can easily understand that the data line 32 can be formed by at least two patterning processes. The source electrode 355 and the drain electrode 356 are not limited in this embodiment of the present application.
  • Step 808 Form a passivation layer on the base substrate forming the active drain and the data line.
  • the material of the passivation layer may be a transparent insulating material, and the transparent insulating material may be an inorganic material such as SiOx, SiNx, Al 2 O 3 or SiOxNx.
  • the process of forming the passivation layer reference may be made to the process of forming the insulating layer 37 in step 802, and the embodiments of the present application will not repeat them here.
  • Step 809 Form a plurality of pixel electrodes corresponding to a plurality of source and drain electrodes, a plurality of common electrodes, a plurality of active layers, a plurality of source and drain electrodes, and a plurality of pixels on the base substrate on which the passivation layer is formed
  • the electrodes are located in a plurality of pixel regions in one-to-one correspondence.
  • the material of the pixel electrode may be a transparent conductive material, and the transparent conductive material may be a metal oxide such as ITO, IZO, or ZnO:Al.
  • the transparent conductive material may be a metal oxide such as ITO, IZO, or ZnO:Al.
  • a layer may be deposited on the base substrate 30 on which the passivation layer 38 is formed by any one of processes such as magnetron sputtering, thermal evaporation, or PECVD.
  • ITO obtains an ITO material layer, and processes the ITO material layer through a patterning process to obtain a plurality of pixel electrodes 36, which correspond to a plurality of source and drain electrodes, a plurality of common electrodes 34, and a plurality of active layers 353
  • a plurality of source and drain electrodes and a plurality of pixel electrodes 36 are located in the plurality of pixel regions in a one-to-one correspondence.
  • the gate 351, the gate insulating layer 352, the active layer 353, the interlayer dielectric layer 354, and the source and drain located in the same pixel area constitute a TFT.
  • the one-time patterning process includes photoresist coating, exposure, development, etching, and photoresist stripping, and the material layer (such as the ITO material layer) is processed through the one-time patterning process Including: first, coat a layer of photoresist on the material layer (for example, ITO material layer) to form a photoresist layer, and then, use a mask to expose the photoresist layer, so that the photoresist layer forms a fully exposed area And the non-exposed area, and then use a development process to process the exposed photoresist layer, so that the photoresist in the fully exposed area is completely removed, and the photoresist in the non-exposed area is completely retained.
  • the material layer such as the ITO material layer
  • the material layer (for example, the ITO material layer) is etched in an area corresponding to the fully exposed area, and finally, the photoresist in the non-exposed area is stripped to obtain a corresponding structure (for example, the pixel electrode 36).
  • the photoresist is used as a positive photoresist as an example for description.
  • the process of one patterning process can refer to the description in this paragraph, and the embodiments of the present application will not be described here. Repeat.
  • the display substrate manufacturing method in the display substrate, for each common electrode line, the distance between any point on the target lead segment and the target grid line is less than that of the non-target lead segment.
  • the distance between the target grid lines, the target wire segment is a wire segment that crosses the common electrode line and the data line
  • the non-target wire segment is a wire segment other than the target wire segment on the common electrode line, so the display substrate Without changing the area of the common electrode, make the distance between the common electrode and the target conductive line larger, so that the distance between the common electrode and the intersection position (referring to the intersection position of the common electrode line and the data line) is relatively
  • the larger size is convenient for the implementation of welding work, the success rate of repairing the data line is higher and the opening rate of the display substrate is higher.
  • the display substrate manufactured by the method provided in the embodiments of the present application can satisfy the photoelectric performance of the product, and at the same time improve the success rate of data line repair and improve the product yield.
  • FIG. 9 shows a flow chart of a method for repairing a display substrate provided by an embodiment of the present application.
  • the repair method can be used to repair the breakage of a data line in the display substrate.
  • the method may include the following steps:
  • Step 901 When the first data line is broken, determine the first repair point and the second repair point according to the break point of the first data line, the first repair point is the intersection of the first common electrode line and the first data line, the second The repair point is the intersection of the second common electrode line and the first data line.
  • the first common electrode line is adjacent to the second common electrode line and arranged in sequence along the scanning direction of the gate line.
  • the break point is located between the first common electrode line and the second Between common electrode wires.
  • the first data line may be any data line in the display substrate.
  • the first data line breaks, the first target wire segment of the first common electrode line and the first The intersection of the data lines is determined as the first repair point, and the intersection of the first target wire segment of the second common electrode line and the first data line is determined as the second repair point, the first common electrode line is adjacent to the second common electrode line Furthermore, they are sequentially arranged along the scanning direction of the gate line, and the break point is located between the first common electrode line and the second common electrode line.
  • FIG. 10 shows a schematic diagram of repairing a display substrate provided by an embodiment of the present application.
  • the first data line 32c is broken, the breaking point is point G, and the first common electrode line 33c Adjacent to the second common electrode line 33d and sequentially arranged along the gate line scanning direction x, the break point G is located between the first common electrode line 33c and the second common electrode line 33d, so the first common electrode line 33c
  • the intersection S1 with the first data line 32c is determined as the first repair point
  • the intersection S2 with the second common electrode line 33d and the first data line 32c is determined as the second repair point.
  • Step 902 Determine multiple cutting points according to the first repair point and the second repair point.
  • the multiple cutting points include: first cutting points on two segments of the first target wire segment, and second segments on two segments of the second target wire segment The cutting point, the third cutting point on the connecting line of the first common electrode line and the first common electrode, and the fourth cutting point on the connecting line of the third common electrode line and the second common electrode, two first target wires
  • the segment is a target wire segment where the first data line crosses the first common electrode line and a target wire segment where the first data line crosses the second common electrode line, and two second target wire segments are the second data line and the first common
  • the target lead segment where the electrode line crosses and the target lead segment where the second data line crosses the second common electrode line, the second data line is the previous data line of the first data line, the first common electrode, the third common electrode and the first
  • the two common electrodes are adjacent and arranged in the same row in sequence along the scanning direction of the gate line, and the third common electrode is located in the pixel area surrounded by the
  • multiple cutting points can be determined according to the first repair point and the second repair point.
  • the multiple cutting points include the first cutting point, the second cutting point, the third cutting point, and the first Four cutting points, the first cutting point is located on the two first target wire segments and after the first data line, the second cutting point is located on the two second target wire segments and after the second data line, the third cutting point It is located on the connection line between the first common electrode line and the first common electrode, and the fourth cutting point is located on the connection line between the third common electrode line and the second common electrode.
  • the cutting point after the data line refers to the cutting point after the data line along the scanning direction of the data line.
  • the first cutting point is located on two first target wire segments and after the first data line means: A cutting point is located on two first target wire segments, and is located behind the first data line in the scanning direction of the data line, and a second cutting point is located on two second target wire segments and after the second data line.
  • the second cutting point is located on two second target wire segments, and is located behind the second data line in the scanning direction of the data line.
  • the previous data line of the first data line refers to a data line located before the first data line and adjacent to the first data line in the scanning direction of the data line.
  • the first common electrode line 33c, the second common electrode line 33d and the third common electrode line 33e are sequentially arranged along the gate line scanning direction x
  • the second data line 32d is the first data line 32c
  • the first gate line 31c is the target gate line corresponding to the first common electrode line 33c (that is, the gate line closest to the first common electrode line 33c)
  • the second gate line 31d is the second common electrode
  • the target gate line corresponding to the line 33d ie, the gate line closest to the second common electrode line 33d
  • the third common electrode 34e is located on the first gate line 31c, the second gate line 31d, the first data line 32c, and the second In the pixel area surrounded by the data line 32d
  • the first common electrode 34c, the third common electrode 34e, and the second common electrode 34d are arranged in sequence along the gate line scanning direction x
  • the multiple cutting points include: two first target wire segments (The target wire segment where the first common electrode line 33c crosses the first
  • Cutting points P1 and P2 two second target wire segments (a target wire segment where the first common electrode line 33c crosses the second data line 32d, and a target wire where the second common electrode line 33d crosses the second data line 32d 10, the second cutting points P3 and P4, the third cutting point P5 on the bridge line 39 of the first common electrode line 33c and the first common electrode 34c, and the third common electrode line
  • the fourth cutting point P6 on the bridge line 39 of the 33e and the second common electrode 34d, the first cutting points P1 and P2 are located behind the first data line 32c along the data line scanning direction y, and the second cutting points P3 and P4 are along the data line
  • the scanning direction y is located behind the second data line 32d.
  • Step 903 Connect the first data line and the first common electrode line from the first repair point, and connect the first data line and the second common electrode line from the second repair point.
  • connecting the first data line and the first common electrode line from the first repair point may include: welding the first data line and the first common electrode line from the first repair point through a laser welding process; from the second
  • the connection between the first data line and the second common electrode line at the repair point may include: welding the first data line and the second common electrode line from the second repair point through a laser welding process.
  • a first welding hole may be formed on the film layer between the first data line and the first common electrode line from the first repair point, and the first data line and the first common electrode line may be connected from the first welding hole welding.
  • a second welding hole is formed in the film layer between the first data line and the second common electrode line, and the first data line and the second common electrode line are welded from the second welding hole.
  • a first welding hole (not shown in FIG. 10) may be formed on the film layer between the first data line 32c and the first common electrode line 33c from the first repair point S1, Then, through the laser welding process, the first data line 32c and the first common electrode line 33c are welded from the first welding hole; from the second repair point S2, between the first data line 32c and the second common electrode line 33d
  • a second welding hole (not shown in FIG. 10) is formed on the film layer, and then the first data line 32c and the second common electrode line 33d are welded from the second welding hole through a laser welding process.
  • Step 904 Cut the corresponding common wire from each cutting point.
  • the common wire includes the first target wire segment, the second target wire segment, and the connecting wire.
  • cutting the corresponding common wire from each cutting point may include: cutting the corresponding common wire from each cutting point through a laser cutting process.
  • the common wire refers to a first target wire segment, a second target wire segment, and a connecting wire (such as a bridge 39) connecting the common electrode wire and the common electrode.
  • the corresponding common wire can be cut from each of the cutting points P1 to P6, for example, from the first cutting points P1 and P2 respectively to the corresponding first target wire segment Cutting, cutting the corresponding second target wire segment from the second cutting point P3 and P4 respectively, cutting the bridge line 39 of the first common electrode line 33c and the first common electrode 34c from the third cutting point P5, from the The four cutting points P6 cut the bridge 39 between the third common electrode line 33e and the second common electrode 34d.
  • the data lines of the first repairing point S1 and the second repairing point S2 are welded to the common electrode line, and the cutting points P1 to The common wire at each cutting point in P6 is cut.
  • the repair of the first data line is completed, and after the repair of the first data line, when the display substrate is in use, the signal on the first data line is transmitted to the break point Transmission from the first repair point to the first common electrode line, through the first common electrode line, the third common electrode and the second common electrode line to the second repair point, and from the second repair point back to the first data line .
  • FIG. 12 shows a schematic diagram of the transmission path of the signal on the first data line 32c after repairing the display substrate shown in FIG. 10, where the bold arrow indicates the signal on the first data line 32c.
  • FIG. 12 shows a schematic diagram of the transmission path of the signal on the first data line 32c after repairing the display substrate shown in FIG. 10, where the bold arrow indicates the signal on the first data line 32c.
  • the signal transmitted to the break point G on the first data line 32c is transmitted from the first repair point S1 to the first common electrode line 33c, and then passes through the first common electrode line 33c and the third
  • the common electrode 34e and the second common electrode line 33d are transmitted to the second repair point S2, and from the second repair point S2 back to the first data line 32c, so that the signal on the data line can bypass the break point and transmit data back Line, so you can achieve the effect of repairing the data line.
  • repair points and cutting points shown in FIG. 10 are only exemplary, and the repair points and cutting points can also be located at other positions, as long as the signal on the data line can be guaranteed to bypass the break point and be transmitted back to the data line That's it.
  • the signal on the data line is actually transmitted through the common electrode line and the common electrode to bypass the break point, so that the signal on the data line will affect the signal on the common electrode line and the common electrode , Which in turn affects the display of the display substrate, so if the repair point and the cutting point are set at other positions, the signal on the data line has a greater influence on the display substrate display, and if the repair point and the cutting point are set according to FIG.
  • the maximum The effect of the signal on the control data line on the display substrate For example, referring to FIG. 12 and in conjunction with FIG. 10, the signal on the first data line 32c will only affect the display of the pixel area where the third common electrode 34e and the third common electrode 34d are located, but will not affect the display of other pixel areas, so The repair of the first data line 32c has little effect on the display substrate.
  • the distance between any position on the target lead segment and the target grid line is less than that of the non-target lead segment.
  • the distance between the target grid lines, the target wire segment is a wire segment that crosses the common electrode line and the data line
  • the non-target wire segment is a wire segment other than the target wire segment on the common electrode line, so the display substrate Without changing the area of the common electrode, make the distance between the common electrode and the target conductive line larger, so that the distance between the common electrode and the intersection position (referring to the intersection position of the common electrode line and the data line) is relatively
  • the larger size is convenient for the implementation of welding work, the success rate of repairing the data line is higher and the opening rate of the display substrate is higher.
  • An embodiment of the present application further provides a display device including the display substrate 3 provided in the above embodiment.
  • the display device may be: a display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, Any product or part with display function such as digital photo frame, navigator or wearable device.

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Abstract

一种显示基板(3)及其制造方法、修复方法、显示装置。显示基板(3)包括衬底基板(30)以及位于衬底基板(30)上的栅线(31)、数据线(32)、公共电极线(33)和公共电极(34)；栅线(31)与数据线(32)交叉限定出像素区，公共电极(34)位于像素区中，栅线(31)与公共电极线(33)间隔排布且延伸方向平行；公共电极线(33)包括目标导线段(331)和非目标导线段，目标导线段(331)为公共电极线(33)与数据线(32)交叉的导线段，非目标导线段为公共电极线(33)上除目标导线段(331)之外的导线段，对于每条公共电极线(33)：目标导线段(331)上任一位置点与目标栅线(31)之间的距离小于非目标导线段与目标栅线(31)之间的距离，目标栅线(31)为距离公共电极线(33)最近的栅线(31)，位于目标栅线(31)两侧且与目标栅线(31)相邻的公共电极(34)均与公共电极线(33)连接。有助于提高显示基板(3)的开口率。

Description

显示基板及其制造方法、修复方法、显示装置
本申请要求于2019年01月03日提交的申请号为201910005155.7、发明名称为“显示基板及其制造方法、修复方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及一种显示基板及其制造方法、修复方法、显示装置。
背景技术
随着显示技术的不断发展，显示装置广泛应用于显示领域。显示装置的主要显示部件为显示基板，显示基板的性能直接影响显示装置的性能。
发明内容
本申请提供一种显示基板及其制造方法、修复方法、显示装置。技术方案如下：
一方面，提供一种显示基板，包括：
衬底基板，以及，位于所述衬底基板上的多条栅线、多条数据线、多条公共电极线和多个公共电极；
所述多条栅线与所述多条数据线交叉限定出多个像素区，所述多个公共电极一一对应位于所述多个像素区中，所述多条栅线与所述多条公共电极线的延伸方向平行，所述多条栅线与所述多条公共电极线一一间隔排布；
所述公共电极线包括多段目标导线段和非目标导线段，每段所述目标导线段为所述公共电极线与一条所述数据线交叉的导线段，所述非目标导线段为所述公共电极线上除所述目标导线段之外的导线段，对于每条所述公共电极线：所述目标导线段上任一位置点与目标栅线之间的距离小于所述非目标导线段与所述目标栅线之间的距离，所述目标栅线为距离所述公共电极线最近的所述栅线，位于所述目标栅线两侧且与所述目标栅线相邻的所述公共电极均与所述公共电极线连接。
可选地，对于每条所述公共电极线：所述目标导线段向靠近所述目标栅线 的方向弯曲。
可选地，所述目标导线段为弧形导线段。
可选地，所述多个公共电极沿数据线扫描方向排布为多行，对于每条所述公共电极线：所述公共电极线和目标公共电极连接，并通过跨越所述目标栅线的桥接线和与所述目标公共电极相邻且位于同一行的公共电极连接，所述目标公共电极与所述公共电极线处于同一像素区。
可选地，与每条所述公共电极线相邻的两条所述栅线中，一条所述栅线与所述公共电极线之间的距离小于另一条所述栅线与所述公共电极线之间的距离。
可选地，所述显示基板还包括：多个薄膜晶体管和多个像素电极，所述多个薄膜晶体管和所述多个像素电极分别一一对应位于所述多个像素区中，所述薄膜晶体管包括栅极、源极和漏极，所述栅极与距离所述栅极最近的所述栅线连接，所述源极与距离所述源极最近的所述数据线连接，所述漏极与所述薄膜晶体管位于同一像素区中的所述像素电极连接。
可选地，所述薄膜晶体管包括：沿远离所述衬底基板的方向依次分布的所述栅极、栅绝缘层、有源层、层间介质层和源漏极，所述源漏极包括所述源极和所述漏极，所述源极和所述漏极不接触，所述源极和所述漏极分别有源层接触；
所述阵列基板还包括：位于所述公共电极与所述栅线之间的绝缘层，以及，位于所述源漏极与所述像素电极之间的钝化层。
可选地，与每条所述公共电极线相邻的两条所述栅线中，一条所述栅线与所述公共电极线之间的距离小于另一条所述栅线与所述公共电极线之间的距离，所述多个公共电极沿数据线扫描方向排布为多行，对于每条所述公共电极线：所述目标导线段为向靠近所述目标栅线的方向弯曲的弧形导线段，所述公共电极线和目标公共电极连接，并通过跨越所述目标栅线的桥接线和与所述目标公共电极相邻且位于同一行的公共电极连接，所述目标公共电极与所述公共电极线处于同一像素区；
所述显示基板还包括：多个薄膜晶体管、多个像素电极、绝缘层和钝化层，所述多个薄膜晶体管和所述多个像素电极分别一一对应位于所述多个像素区中，所述薄膜晶体管包括沿远离所述衬底基板的方向依次分布的栅极、栅绝缘层、有源层、层间介质层和源漏极，所述源漏极包括源极和漏极，所述源极和 所述漏极不接触，所述源极和所述漏极分别与所述有源层接触，所述栅极与距离所述栅极最近的所述栅线连接，所述源极与距离所述源极最近的所述数据线连接，所述漏极与所述薄膜晶体管位于同一像素区中的所述像素电极连接，所述绝缘层位于所述公共电极与所述栅线之间，所述钝化层位于所述源漏极与所述像素电极之间。
另一方面，提供一种显示基板的制造方法，所述方法包括：
在衬底基板上形成多条栅线、多条数据线、多条公共电极线和多个公共电极；
所述多条栅线与所述多条数据线交叉限定出多个像素区，所述多个公共电极一一对应位于所述多个像素区中，所述多条栅线与所述多条公共电极线的延伸方向平行，所述多条栅线与所述多条公共电极线一一间隔排布；所述公共电极线包括多段目标导线段和非目标导线段，每段所述目标导线段为所述公共电极线与一条所述数据线交叉的导线段，所述非目标导线段为所述公共电极线上除所述目标导线段之外的导线段，对于每条所述公共电极线：所述目标导线段上任一位置点与目标栅线之间的距离小于所述非目标导线段与所述目标栅线之间的距离，所述目标栅线为距离所述公共电极线最近的所述栅线，位于所述目标栅线两侧且与所述目标栅线相邻的公共电极均与所述公共电极线连接。
可选地，所述在衬底基板上形成多条栅线、多条数据线、多条公共电极线和多个公共电极，包括：
在所述衬底基板上形成所述多个公共电极，所述多个公共电极阵列排布为多列；
在形成有所述公共电极的所述衬底基板上形成所述多条栅线和所述多条公共电极线，每相邻的两条所述栅线之间具有一列所述公共电极；
在形成有所述栅线和所述公共电极线的所述衬底基板上形成所述多条数据线，所述多条数据线与每条所述公共电极线的多段所述目标导线段一一交叉。
可选地，对于每条所述公共电极线：所述目标导线段向靠近所述目标栅线的方向弯曲。
可选地，所述目标导线段为弧形导线段。
可选地，所述多个公共电极还阵列排布为多行，对于每条所述公共电极线：所述公共电极线和目标公共电极连接，并通过跨越所述目标栅线的桥接线和与所述目标公共电极相邻且位于同一行的公共电极连接，所述目标公共电极与所 述公共电极线处于同一像素区。
可选地，与每条所述公共电极线相邻的两条所述栅线中，一条所述栅线与所述公共电极线之间的距离小于另一条所述栅线与所述公共电极线之间的距离。
可选地，所述方法还包括：
在所述衬底基板上形成多个薄膜晶体管和多个像素电极，所述多个薄膜晶体管和所述多个像素电极分别一一对应位于所述多个像素区中，所述薄膜晶体管包括栅极、源极和漏极，所述栅极与距离所述栅极最近的所述栅线连接，所述源极与距离所述源极最近的所述数据线连接，所述漏极与所述薄膜晶体管位于同一像素区中的所述像素电极连接。
可选地，所述薄膜晶体管包括：沿远离所述衬底基板的方向依次分布的所述栅极、栅绝缘层、有源层、层间介质层和源漏极，所述源漏极包括所述源极和所述漏极，所述源极和所述漏极不接触，且所述源极和所述漏极分别有源层接触；
所述方法还包括：
在所述公共电极与所述栅线之间形成绝缘层；
在所述源漏极与所述像素电极之间形成钝化层。
再一方面，提供一种显示基板的修复方法，用于上述一方面或一方面的任一可选方式所述的显示基板，所述方法包括：
在第一数据线断裂时，根据所述第一数据线的断裂点确定第一修复点和第二修复点，所述第一修复点为第一公共电极线与所述第一数据线的交点，所述第二修复点为第二公共电极线与所述第一数据线的交点，所述第一公共电极线与所述第二公共电极线相邻且沿栅线扫描方向依次排布，所述断裂点位于所述第一公共电极线与所述第二公共电极线之间；
根据所述第一修复点和第二修复点确定多个切割点，所述多个切割点包括：两段第一目标导线段上的第一切割点，两段第二目标导线段上的第二切割点、所述第一公共电极线与第一公共电极的连接线上的第三切割点，以及第三公共电极线与第二公共电极的连接线上的第四切割点，所述两段第一目标导线段为所述第一数据线与所述第一公共电极线交叉的目标导线段以及所述第一数据线与所述第二公共电极线交叉的目标导线段，所述两段第二目标导线段为第二数据线与所述第一公共电极线交叉的目标导线段以及所述第二数据线与所述第二 公共电极线交叉的目标导线段，所述第二数据线为所述第一数据线的上一条数据线，所述第一公共电极、第三公共电极和所述第二公共电极相邻且沿栅线扫描方向依次排布在同一行中，所述第三公共电极位于第一栅线、第二栅线、所述第一数据线和所述第二数据线围成的像素区中，所述第一栅线为所述第一公共电极线对应的目标栅线，所述第二栅线为所述第二公共电极线对应的目标栅线，所述第二公共电极线与所述第三公共电极线相邻且沿栅线扫描方向依次排布；
从所述第一修复点将所述第一数据线与所述第一公共电极线连接，并从所述第二修复点将所述第一数据线与所述第二公共电极线连接；
从每个所述切割点对相应的公共导线进行切割，所述公共导线包括所述第一目标导线段、所述第二目标导线段和所述连接线。
可选地，所述第一切割点位于所述两段第一目标导线段上且位于所述第一数据线之后；
所述第二切割点位于所述两段第二目标导线段上且位于所述第二数据线之后；
所述第三切割点位于所述第一公共电极线与所述第一公共电极的桥接线上；
所述第四切割点位于所述第三公共电极线与所述第二公共电极的桥接线上。
可选地，所述从所述第一修复点将所述第一数据线与所述第一公共电极线连接，包括：
通过激光焊接工艺，从所述第一修复点将所述第一数据线与所述第一公共电极线焊接；
所述从所述第二修复点将所述第一数据线与所述第二公共电极线连接，包括：
通过激光焊接工艺，从所述第二修复点将所述第一数据线与所述第二公共电极线焊接。
可选地，所述从每个所述切割点对相应的公共导线进行切割，包括：通过激光切割工艺，从每个所述切割点对相应的公共导线进行切割。
又一方面，提供一种显示装置，包括上述一方面或一方面的任一可选方式所述的显示基板。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例所涉及的一种显示基板的正视图；
图2是本申请实施例所涉及的另一种显示基板的正视图；
图3是本申请实施例提供的一种显示基板的正视图；
图4是图3所示的显示基板的区域Q的放大图；
图5是本申请实施例提供的一种显示基板的剖视图；
图6是本申请实施例提供的另一种显示基板的正视图；
图7是本申请实施例提供的一种显示基板的制造方法的方法流程图；
图8是本申请实施例提供的另一种显示基板的制造方法的方法流程图；
图9是本申请实施例提供的一种显示基板的修复方法的方法流程图；
图10是本申请实施例提供的一种显示基板的修复示意图；
图11是本申请实施例提供的一种修复后的显示基板的正视图；
图12是本申请实施例提供的一种修复后数据线上信号的传输路径示意图。
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本申请的实施例，并与说明书一起用于解释本申请的原理。
具体实施方式
为了使本申请的原理、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。
请参考图1，其示出了本申请实施例所涉及的一种显示基板1的正视结构示意图，参见图1，显示基板1包括衬底基板10，以及，位于衬底基板10上的多条栅线11、多条数据线12和多条公共电极线13，多条公共电极线13与多条栅线11平行，且公共电极线13与栅线11一一间隔排布，多条栅线11与多条数据线12交叉限定出多个像素区(图1中未标出)，该显示基板1还包括一一对应 位于多个像素区中的多个公共电极14、多个薄膜晶体管(英文：Thin Film Transistor；简称：TFT)15和多个像素电极(图1中未示出)。在任一数据线12断裂时，可以在该数据线12与公共电极线13的交叉位置将该数据线12与该公共电极线13焊接，使该数据线12上的信号通过该公共电极线13绕过断裂点传输，从而达到对该数据线12修复的效果。但是，在如图1所示的显示基板1中，公共电极14与所述交叉位置之间的距离较小，该距离通常为3.5um(微米)，导致焊接作业空间不足，焊接工作难以实施，因此对数据线修复的成功率较低。
请参考图2，其示出了本申请实施例所涉及的另一种显示基板2的正视结构示意图，与图1所示的显示基板1类似，该显示基板2包括衬底基板20，以及，位于衬底基板20上的多条栅线21、多条数据线22、多条公共电极线23、多个公共电极24、多个TFT25和多个像素电极(图2中未示出)，每个公共电极24上靠近公共电极线23与数据线22的交叉位置的一角具有缺口K，这样一来，每个公共电极24和所述交叉位置之间的距离相对较大，该距离通常为7.0um，可以便于焊接工作的实施。但是，显示基板的开口率与公共电极的有效显示面积(例如公共电极与像素电极的正对面积)正相关，在如图2的显示基板2中，缺口K会导致公共电极24的有效显示面积较小，因此显示基板2的开口率较低。
本申请实施例提供了一种显示基板及其制造方法、修复方法、显示装置，在显示基板中，对于每条公共电极线，目标导线段上任一位置点与目标栅线之间的距离小于非目标导线段与该目标栅线之间的距离，该目标导线段为该公共电极线与数据线交叉的导线段，该非目标导线段为该公共电极线上除该目标导线段之外的导线段，这样一来，在不改变公共电极的面积的前提下，可以使公共电极与目标导电线之间的距离较大，从而公共电极和交叉位置(指的是公共电极线与数据线的交叉位置)之间的距离较大，便于焊接工作的实施，对数据线修复的成功率较高且显示基板的开口率较高。本申请的方案请参考下述实施例。
图3是本申请实施例提供的一种显示基板3的正视图，图4是图3所示的显示基板3的区域Q的放大图，图5是本申请实施例提供的一种显示基板3的剖视图，参见图3至图5，该显示基板3包括：衬底基板30，以及，位于衬底基板30上的多条栅线31、多条数据线32、多条公共电极线33和多个公共电极34；多条栅线31与多条数据线32交叉限定出多个像素区(图3至图5中均未 标出)，每个像素区由相邻的两条栅线31和相邻的两条数据线32围成，多个公共电极34一一对应位于该多个像素区中，多条栅线31与多条公共电极线33的延伸方向平行，多条栅线31与多条公共电极线33一一间隔排布。
如图3和图4所示，每条公共电极线33包括多段目标导线段331和非目标导线段(图3和图4中均未标出)，每段目标导线段331为该公共电极线33与一条数据线32交叉的导线段，非目标导线段为该公共电极线33上除该多条目标导线段331之外的导线段。对于每条公共电极线33：目标导线段331上任一位置点与目标栅线之间的距离L1小于非目标导线段与该目标栅线之间的距离L2，该目标栅线为距离该公共电极线33最近的栅线31，位于该目标栅线两侧且与该目标栅线相邻的公共电极34均与该公共电极线33连接。本领域技术人员容易理解，对于每条公共电极线33，目标导线段331与非目标导线段连接，目标导线段331上位于该连接部位的位置点与目标栅线之间的距离可以是该目标导线段331与目标栅线之间最大距离，并且在该连接部位，目标导线段331与目标栅线之间的距离可以等于非目标导线段与该目标栅线之间的距离，本申请实施例中，除另有说明外，该目标导线段331上任一位置点指的是该目标导线段331上除与非目标导线段连接部位之外的位置点
示例地，请参考图6，其示出了本申请实施例提供的另一种显示基板3的正视图，如图6所示，对于该公共电极线33a，目标栅线为栅线31a，该公共电极线33a包括多段目标导线段331a和非非目标导线段(图6中均未标出)，目标导线段331a上的任一位置点与栅线31a之间的距离(图6中均未标出)小于该公共电极线33a上的非目标导线段与栅线31a之间的距离(图6中均未标出)，位于栅线31a两侧且与栅线31a相邻的公共电极34均与该公共电极线33a连接。
综上所述，本申请实施例提供的显示基板中，对于每条公共电极线，目标导线段上任一位置点与目标栅线之间的距离小于非目标导线段与该目标栅线之间的距离，目标导线段为该公共电极线与数据线交叉的导线段，非目标导线段为该公共电极线上除该目标导线段之外的导线段，因此该显示基板在不改变公共电极的面积的前提下，使公共电极与目标导电线之间的距离较大，从而公共电极和交叉位置(指的是公共电极线与数据线的交叉位置)之间的距离相对较大，便于焊接工作的实施，对数据线修复的成功率较高且显示基板的开口率较高。
可选地，如图3所示，与每条公共电极线33相邻的两条栅线31中，一条 栅线31与该公共电极线33之间的距离小于另一条栅线31与该公共电极线33之间的距离。例如，如图6所示，与公共电极线33a相邻的两条栅线包括栅线31a和栅线31b，在该两条栅线中，栅线31a与该公共电极线33a之间的距离小于栅线31b与该公共电极线33a之间的距离。
可选地，如图3、图4和图6所示，对于每条公共电极线33：目标导线段331向靠近目标栅线的方向弯曲；可选地，目标导线段331可以为弧形导线段。
可选地，如图3所示，多个公共电极34沿栅线扫描方向x排布为多列，且沿数据线扫描方向y排布为多行，列方向与栅线扫描方向x垂直，行方向与数据线扫描方向y垂直，对于每条公共电极线33：该公共电极线33和目标公共电极连接，并通过跨越目标栅线的桥接线39和与目标公共电极相邻且位于同一行的公共电极34连接。其中，每条公共电极线33部分处于像素区中，每条公共电极线33处于像素区中的部分和目标公共电极连接，并通过跨越目标栅线的桥接线39和与目标公共电极相邻且位于同一行的公共电极34连接，该目标公共电极为与公共电极线33处于同一像素区的公共电极。
可选地，请继续参考图3至图5，该显示基板3还包括：多个TFT35和多个像素电极36，该多个TFT35和多个像素电极36分别一一对应位于该多个像素区中，如图5所示，每个TFT35包括沿远离衬底基板30的方向依次分布的栅极351、栅绝缘层352、有源层353、层间介质层354和源漏极，源漏极包括源极355和漏极356，源极355和漏极356不接触，源极355和漏极356分别有源层353接触，栅极351与距离该栅极351最近的栅线31连接，源极355与距离该源极355最近的数据线32连接，漏极356与该TFT35位于同一像素区中的像素电极36连接。可选地，如图5所示，栅线31、公共电极线33以及栅极351同层分布，该显示基板3还包括位于公共电极34与栅线31之间的绝缘层37，以及，位于源漏极与像素电极36之间的钝化层38。在本申请实施例中，异层分布的结构可以通过过孔连接，例如，公共电极线33与公共电极34异层分布，公共电极线33可以通过绝缘层37上的过孔与公共电极34连接(图5中未示出)，再例如，源漏极与有源层353异层分布，源极355和漏极356分别通过层间介质层354上的过孔与有源层353连接，又例如，像素电极36与漏极356异层分布，像素电极36通过钝化层38上的过孔与漏极356连接，本申请实施例在此不再一一列举。
可选地，显示基板3可以为高级超维场转换(英文：Advanced Super  Dimension Switch；简称：ADS)型显示基板，如图5所示，像素电极36可以为狭缝电极(也即是像素电极36上具有狭缝)，狭缝的存在可以便于在公共电极34与像素电极36之间形成电压。
可选地，衬底基板30可以是透明基板，例如其可以是采用玻璃、石英或透明树脂等具有一定坚固性的导光且非金属材料制成的刚性基板，或者，衬底基板30为采用聚酰亚胺(英文：Polyimide；简称：PI)等柔性材料制成的柔性基板；栅线31、公共电极线33和栅极351可以通过同一次构图工艺制作，且栅线31、公共电极线33和栅极351这三者的材料可以相同，例如栅线31、公共电极线33和栅极351这三者的材料均可以为金属Mo(中文：钼)、金属Cu(中文：铜)、金属Al(中文：铝)、金属Ti(中文：钛)及其合金材料；数据线32、源极355、漏极356以及桥接线39可以通过同一次构图工艺制作，且数据线32、源极355、漏极356以及桥接线39这四者的材料可以相同，例如数据线32、源极355、漏极356以及桥接线39这四者的材料均可以为金属Mo、金属Cu、金属Al、金属Ti及其合金材料；公共电极34和像素电极36均可以为透明电极，且公共电极34和像素电极36的材料可以相同或不同，例如，公共电极34和像素电极36的材料均可以为氧化铟锡(英文：Indium tin oxide；简称：ITO)、氧化铟锌(英文：Indium zinc oxide；简称：IZO)或掺铝氧化锌(英文：aluminum-doped zinc oxide；简称：ZnO:Al)等金属氧化物；有源层353可以为半导体有源层或氧化物有源层，例如，有源层353为采用非晶硅或多晶硅等半导体材料制成的半导体有源层，或者，有源层353为采用铟镓锌氧化物(英文：indium gallium zinc oxide；简称：IGZO)或铟锡锌氧化物(英文：indium tin zinc oxide；简称：ITZO)等半导体氧化物制成的氧化物有源层；栅绝缘层352、层间介质层354、绝缘层37和钝化层38的材料均可以是采用SiOx(中文：氧化硅)、SiNx(中文：氮化硅)、Al 2O 3(中文：氧化铝)或SiOxNx(中文：氮氧化硅)等无机材料，且栅绝缘层352、层间介质层354、绝缘层37和钝化层38这四者的材料可以相同或不同，本申请实施例不对各个膜层的制作工艺以及材料进行限定。
综上所述，本申请实施例提供的显示基板中，对于每条公共电极线，目标导线段上任一位置点与目标栅线之间的距离小于非目标导线段与该目标栅线之间的距离，目标导线段为该公共电极线与数据线交叉的导线段，非目标导线段为该公共电极线上除该目标导线段之外的导线段，因此该显示基板在不改变公共电极的面积的前提下，使公共电极与目标导电线之间的距离较大，从而公共 电极和交叉位置(指的是公共电极线与数据线的交叉位置)之间的距离相对较大，便于焊接工作的实施，对数据线修复的成功率较高且显示基板的开口率较高。本申请实施例提供的显示基板可以在满足产品光电性能的同时，提高数据线修复的成功率，提升产品良率。
下述为本申请实施例提供的显示基板的制造方法的实施例，本申请实施例中显示基板的制造方法和制造原理可以参见下文各实施例中的描述。
本申请实施例提供了一种显示基板的制造方法，该方法包括：
在衬底基板上形成多条栅线、多条数据线、多条公共电极线和多个公共电极；
多条栅线与多条数据线交叉限定出多个像素区，多个公共电极一一对应位于多个像素区中，多条栅线与多条公共电极线的延伸方向平行，多条栅线与多条公共电极线一一间隔排布；公共电极线包括多段目标导线段和非目标导线段，每段目标导线段为公共电极线与一条数据线交叉的导线段，非目标导线段为公共电极线上除目标导线段之外的导线段，对于每条公共电极线：目标导线段上任一位置点与目标栅线之间的距离小于非目标导线段与目标栅线之间的距离，目标栅线为多条栅线中距离公共电极线最近的栅线，位于目标栅线两侧且与目标栅线相邻的公共电极均与公共电极线连接。
示例地，请参考图7，其示出了本申请实施例提供的一种显示基板的制造方法的方法流程图，参见图7，该方法可以包括如下步骤：
步骤701、在衬底基板上形成多个公共电极，多个公共电极阵列排布为多列。
步骤702、在形成有公共电极的衬底基板上形成多条栅线和多条公共电极线，多条栅线与多条公共电极线的延伸方向平行，多条栅线与多条公共电极线一一间隔排布，每相邻的两条栅线之间具有一列公共电极，每条公共电极线包括多段目标导线段和非目标导线段，每段目标导线段为该公共电极线与一条数据线交叉的导线段，非目标导线段为该公共电极线上除目标导线段之外的导线段，对于每条公共电极线：目标导线段上任一位置点与目标栅线之间的距离小于非目标导线段与该目标栅线之间的距离，该目标栅线为距离该公共电极线最近的栅线，位于该目标栅线两侧且与该目标栅线相邻的公共电极均与公共电极线连接。
步骤703、在形成有栅线和公共电极线的衬底基板上形成多条数据线，多条 栅线与多条数据线交叉限定出多个像素区，多个公共电极一一对应位于多个像素区中，该多条数据线与每条公共电极线的多段目标导线段一一交叉。
综上所述，本申请实施例提供的显示基板的制造方法，在显示基板中，对于每条公共电极线，目标导线段上任一位置点与目标栅线之间的距离小于非目标导线段与该目标栅线之间的距离，目标导线段为该公共电极线与数据线交叉的导线段，非目标导线段为该公共电极线上除该目标导线段之外的导线段，因此该显示基板在不改变公共电极的面积的前提下，使公共电极与目标导电线之间的距离较大，从而公共电极和交叉位置(指的是公共电极线与数据线的交叉位置)之间的距离相对较大，便于焊接工作的实施，对数据线修复的成功率较高且显示基板的开口率较高。
可选地，对于每条公共电极线：目标导线段向靠近目标栅线的方向弯曲。
可选地，目标导线段为弧形导线段。
可选地，多个公共电极还阵列排布为多行，对于每条公共电极线：该公共电极线和目标公共电极连接，并通过跨越目标栅线的桥接线和与目标公共电极相邻且位于同一行的公共电极连接，该目标公共电极与该公共电极线处于同一像素区。
可选地，与每条公共电极线相邻的两条栅线中，一条栅线与该公共电极线之间的距离小于另一条栅线与该公共电极线之间的距离。
可选地，该方法还包括：在衬底基板上形成多个TFT和多个像素电极，多个TFT和多个像素电极分别一一对应位于多个像素区中，该TFT包括栅极、源极和漏极，该栅极与距离该栅极最近的栅线连接，该源极与距离该源极最近的数据线连接，该漏极与该TFT位于同一像素区中的像素电极连接。
可选地，TFT包括：沿远离衬底基板的方向依次分布的栅极、栅绝缘层、有源层、层间介质层和源漏极，源漏极包括源极和漏极，源极和漏极不接触，且源极和漏极分别有源层接触；
该方法还包括：在公共电极与栅线之间形成绝缘层；
在源漏极与像素电极之间形成钝化层。
上述所有可选技术方案，可以采用任意结合形成本申请的可选实施例，在此不再一一赘述。
请参考图8，其示出了本申请实施例提供的另一种显示基板的制造方法的方 法流程图，该显示基板的制造方法可以用于制造上述实施例提供的显示基板3，参见图8，该方法可以包括如下步骤：
步骤801、在衬底基板上形成多个公共电极，多个公共电极阵列排布为多列。
如图3所示，多个公共电极34在衬底基板30上阵列排布为多行和多列，列方向可以为方向y，行方向可以为方向x，行方向x与列方向y垂直。在本申请实施例中，公共电极34的材料可以为透明导电材料，该透明导电材料可以为ITO、IZO或ZnO:Al等金属氧化物。以公共电极34的材料为ITO为例，可以通过磁控溅射、热蒸发或者等离子体增强化学气相沉积法(英文：Plasma Enhanced Chemical Vapor Deposition；简称：PECVD)等工艺中的任一种在衬底基板30上沉积一层ITO得到ITO材质层，通过一次构图工艺对ITO材质层进行处理得到多个公共电极34。
步骤802、在形成有公共电极的衬底基板上形成绝缘层。
其中，绝缘层的材料可以为透明绝缘材料，该透明绝缘材料可以为SiOx、SiNx、Al 2O 3或SiOxNx等无机材料。以绝缘层的材料为SiOx为例，如图5所示，可以通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在形成有公共电极34的衬底基板30上沉积一层SiOx得到SiOx材质层，通过一次构图工艺对SiOx材质层进行处理得到绝缘层37。
步骤803、在形成有绝缘层的衬底基板上形成多个栅极、多条栅线和多条公共电极线，多条栅线与多条公共电极线的延伸方向平行，多条栅线与多条公共电极线一一间隔排布，每相邻的两条栅线之间具有一列公共电极，该公共电极线包括多段目标导线段和非目标导线段，该非目标导线段为该公共电极线上除该目标导线段之外的导线段，对于每条公共电极线：目标导线段上任一位置点与目标栅线之间的距离小于非目标导线段与目标栅线之间的距离，目标栅线为多条栅线中距离该公共电极线最近的栅线，位于目标栅线两侧且与目标栅线相邻的公共电极均与公共电极线连接。
如图3所示，多条栅线31与多条公共电极线33的延伸方向(又可以称为长度方向)平行，多条栅线31与多条公共电极线33一一间隔排布，每相邻的两条栅线31之间具有一列公共电极34，与每条公共电极线33相邻的两条栅线31中，其中一条栅线31与该公共电极线33之间的距离小于另一条栅线31与该公共电极线33之间的距离，每条公共电极线33包括多段目标导线段331和非目标导线段(图3中未标出)，对于每条公共电极线33，目标导线段331上任一 位置点与目标栅线之间的距离小于非目标导线段与该目标栅线之间的距离，该目标栅线为多条栅线31中距离该公共电极线33最近的栅线，位于目标栅线两侧且与目标栅线相邻的公共电极34均与公共电极线33连接。其中，每条公共电极线33上的非目标导线段为该公共电极线33上除多段目标导线段331之外的导线段，公共电极线33可以通过桥接线39与公共电极34连接。示例地，如图6所示，与公共电极线33a相邻的两条栅线中，栅线31a与公共电极线33a之间的距离小于栅线31b与公共电极线33a之间的距离，公共电极线33a包括多段目标导线段331a和非目标导线段，因此对于公共电极线33a，目标栅线为栅线31a，目标导线段331a上任一位置点与栅线31a之间的距离小于非目标导线段与栅线31a之间的距离，位于栅线31a两侧且与栅线31a相邻的公共电极34均与公共电极线33a连接。
在本申请实施例中，如图3至图6所示，栅线31、公共电极线33和栅极351可以通过同一次构图工艺制作，且栅线31、公共电极线33和栅极351这三者的材料可以相同，例如栅线31、公共电极线33和栅极351这三者的材料均可以为金属Mo、金属Cu、金属Al、金属Ti及其合金材料。以栅线31、公共电极线33和栅极351通过同一次构图工艺制作，且栅线31、公共电极线33和栅极351这三者的材料均为金属Mo为例，如图5所示，可以通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在形成有绝缘层37的衬底基板30上沉积一层金属Mo得到金属Mo材质层，通过一次构图工艺对金属Mo材质层进行处理得到多个栅极351、多条栅线31和多条公共电极线33，每个栅极351距离该栅极351最近的栅线31连接。
本领域技术人员容易理解，本申请实施例是以栅线31、公共电极线33和栅极351通过同一次构图工艺制作为例进行说明的，实际应用中，可以通过三次构图工艺制作栅线31、公共电极线33和栅极351，本申请实施例对此不做限定。
步骤804、在形成有栅极、栅线和公共电极线的衬底基板上形成栅绝缘层。
其中，栅绝缘层的材料可以为透明绝缘材料，该透明绝缘材料可以为SiOx、SiNx、Al 2O 3或SiOxNx等无机材料。形成栅绝缘层的过程可以参考步骤802中形成绝缘层37的过程，本申请实施例在此不再赘述。
步骤805、在形成有栅绝缘层的衬底基板上形成与多个有源层，多个有源层与多个栅极一一对应。
其中，有源层的材料可以为非晶硅或多晶硅等半导体材料，或者，有源层 的材料为IGZO或ITZO等半导体氧化物。以有源层的材料为IGZO为例，如图5所示，可以通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在形成有栅绝缘层352的衬底基板30上沉积一层IGZO得到IGZO材质层，通过一次构图工艺对IGZO材质层进行处理得到多个有源层353，多个有源层353与多个栅极351一一对应。
步骤806、在形成有有源层的衬底基板上形成层间介质层。
其中，层间介质层的材料可以为透明绝缘材料，该透明绝缘材料可以为SiOx、SiNx、Al 2O 3或SiOxNx等无机材料。形成层间介质层的过程可以参考步骤802中形成绝缘层37的过程，本申请实施例在此不再赘述。
步骤807、在形成有层间介质层的衬底基板上形成多条数据线以及与多个有源层一一对应的多个源漏极，多条数据线和多条栅线交叉限定出多个像素区，多个公共电极、多个有源层和多个源漏极一一对应位于多个像素区中，多条数据线与每条公共电极线的多条目标导线段一一交叉。
如图3所示，多条数据线32平行，多条数据线32与多条栅线31交叉限定出多个像素区，结合图3和图5，多个公共电极34、多个有源层353和多个源漏极一一对应位于多个像素区中，多条数据线32与每条公共电极线33的多条目标导线段331一一交叉。
如图5所示，源漏极包括源极355和漏极356，在本申请实施例中，数据线32、源极355和漏极356这三者的材料可以相同，数据线32、源极355和漏极356可以通过同一次构图工艺制作，例如，数据线32、源极355和漏极356这三者的材料均可以为金属Mo、金属Cu、金属Al、金属Ti及其合金材料。以数据线32、源极355和漏极356通过同一次构图工艺制作，且数据线32、源极355和漏极356这三者的材料均为金属Cu为例，如图5所示，可以通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在形成有层间介质层354的衬底基板30上沉积一层金属Cu得到金属Cu材质层，通过一次构图工艺对金属Cu材质层进行处理得到多条数据线32以及多个源漏极，每个源漏极包括源极355和漏极356，源极355与漏极356不接触，源极355和漏极356分别通过层间介质层354的过孔与相应的有源层353接触，每个源极355与距离该源极355最近的数据线32连接。
在本申请实施例中，公共电极线可以通过桥接线与公共电极连接，该桥接线可以与数据线通过同一次构图工艺制作，因此在执行该步骤807的过程中， 还可以形成桥接线，当然，桥接线也可以与数据线通过不同的构图工艺制作。当桥接线与数据线通过同一次构图工艺制作时，容易理解，在执行上述步骤803之后，公共电极线可以未与公共电极连接，而在执行该步骤807之后，公共电极线通过桥接线与公共电极连接，本申请实施例对此不做限定。此外，本申请实施例是以数据线32、源极355和漏极356通过同一次构图工艺制作为例进行说明的，本领域技术人员容易理解，可以通过至少两次构图工艺形成数据线32、源极355和漏极356，本申请实施例对此不做限定。
步骤808、在形成有源漏极和数据线的衬底基板上形成钝化层。
其中，钝化层的材料可以为透明绝缘材料，该透明绝缘材料可以为SiOx、SiNx、Al 2O 3或SiOxNx等无机材料。形成钝化层的过程可以参考步骤802中形成绝缘层37的过程，本申请实施例在此不再赘述。
步骤809、在形成有钝化层的衬底基板上形成与多个源漏极一一对应的多个像素电极，多个公共电极、多个有源层、多个源漏极和多个像素电极一一对应位于多个像素区中。
其中，像素电极的材料可以为透明导电材料，该透明导电材料可以为ITO、IZO或ZnO:Al等金属氧化物。以像素电极的材料为ITO为例，如图5所示，可以通过磁控溅射、热蒸发或者PECVD等工艺中的任一种在形成有钝化层38的衬底基板30上沉积一层ITO得到ITO材质层，通过一次构图工艺对ITO材质层进行处理得到多个像素电极36，多个像素电极36与多个源漏极一一对应，多个公共电极34、多个有源层353、多个源漏极和多个像素电极36一一对应位于多个像素区中。其中，位于同一像素区中的栅极351、栅绝缘层352、有源层353、层间介质层354和源漏极构成一个TFT。
本申请实施例提供的显示基板的制造方法中，一次构图工艺包括光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离，通过一次构图工艺对材质层(例如ITO材质层)进行处理包括：首先，在材质层(例如ITO材质层)上涂覆一层光刻胶形成光刻胶层，接着，采用掩膜版对光刻胶层进行曝光，使得光刻胶层形成完全曝光区和非曝光区，然后，采用显影工艺对曝光后的光刻胶层进行处理，使完全曝光区的光刻胶被完全去除，非曝光区的光刻胶全部保留，之后，采用刻蚀工艺对材质层(例如ITO材质层)上完全曝光区对应的区域进行刻蚀，最后，剥离非曝光区的光刻胶得到相应的结构(例如像素电极36)。这里是以光刻胶为正性光刻胶为例进行说明的，当光刻胶为负性光刻胶时，一次构图工艺的 过程可以参考本段的描述，本申请实施例在此不再赘述。
综上所述，本申请实施例提供的显示基板的制造方法，在显示基板中，对于每条公共电极线，目标导线段上任一位置点与目标栅线之间的距离小于非目标导线段与该目标栅线之间的距离，目标导线段为该公共电极线与数据线交叉的导线段，非目标导线段为该公共电极线上除该目标导线段之外的导线段，因此该显示基板在不改变公共电极的面积的前提下，使公共电极与目标导电线之间的距离较大，从而公共电极和交叉位置(指的是公共电极线与数据线的交叉位置)之间的距离相对较大，便于焊接工作的实施，对数据线修复的成功率较高且显示基板的开口率较高。本申请实施例提供的方法制造的显示基板可以在满足产品光电性能的同时，提高数据线修复的成功率，提升产品良率。
下述为本申请实施例提供的显示基板的修复方法的实施例，本申请实施例中显示基板的修复方法和原理可以参见下文各实施例中的描述。
请参考图9，其示出了本申请实施例提供的一种显示基板的修复方法的方法流程图，该修复方法可以用于对显示基板中数据线的断裂进行修复，本申请实施例以对图3所示的显示基板3中的数据线的断裂进行修复为例，参见图9，该方法可以包括如下步骤：
步骤901、在第一数据线断裂时，根据第一数据线的断裂点确定第一修复点和第二修复点，第一修复点为第一公共电极线与第一数据线的交点，第二修复点为第二公共电极线与第一数据线的交点，第一公共电极线与第二公共电极线相邻且沿栅线扫描方向依次排布，断裂点位于第一公共电极线与第二公共电极线之间。
其中，第一数据线可以为显示基板中的任一数据线，在第一数据线断裂时，可以根据第一数据线的断裂点，将第一公共电极线的第一目标导线段与第一数据线的交点确定为第一修复点，将第二公共电极线的第一目标导线段与第一数据线的交点确定为第二修复点，第一公共电极线与第二公共电极线相邻且沿栅线扫描方向依次排布，断裂点位于第一公共电极线与第二公共电极线之间。
示例地，请参考图10，其示出了本申请实施例提供的一种显示基板的修复示意图，参见图10，第一数据线32c发生断裂，断裂点为点G，第一公共电极线33c和第二公共电极线33d相邻且沿栅线扫描方向x依次排布，该断裂点G位于第一公共电极线33c与第二公共电极线33d之间，因此可以将第一公共电 极线33c与第一数据线32c的交点S1确定为第一修复点，将第二公共电极线33d与第一数据线32c的交点S2确定为第二修复点。
步骤902、根据第一修复点和第二修复点确定多个切割点，多个切割点包括：两段第一目标导线段上的第一切割点，两段第二目标导线段上的第二切割点、第一公共电极线与第一公共电极的连接线上的第三切割点，以及第三公共电极线与第二公共电极的连接线上的第四切割点，两段第一目标导线段为第一数据线与第一公共电极线交叉的目标导线段以及第一数据线与第二公共电极线交叉的目标导线段，两段第二目标导线段为第二数据线与第一公共电极线交叉的目标导线段以及第二数据线与第二公共电极线交叉的目标导线段，第二数据线为第一数据线的上一条数据线，第一公共电极、第三公共电极和第二公共电极相邻且沿栅线扫描方向依次排布在同一行中，第三公共电极位于第一栅线、第二栅线、第一数据线和第二数据线围成的像素区中，第一栅线为第一公共电极线对应的目标栅线，第二栅线为第二公共电极线对应的目标栅线，第二公共电极线与第三公共电极线相邻且沿栅线扫描方向依次排布。
确定第一修复点和第二修复点后，可以根据第一修复点和第二修复点确定多个切割点，多个切割点包括第一切割点、第二切割点、第三切割点和第四切割点，第一切割点位于两段第一目标导线段上且位于第一数据线之后，第二切割点位于两段第二目标导线段上且位于第二数据线之后，第三切割点位于第一公共电极线与第一公共电极的连接线上，第四切割点位于第三公共电极线与第二公共电极的连接线上。其中，切割点位于数据线之后指的是切割点沿数据线扫描方向位于数据线之后，例如，第一切割点位于两段第一目标导线段上且位于第一数据线之后指的是：第一切割点位于两段第一目标导线段上，且沿数据线扫描方向位于第一数据线之后，第二切割点位于两段第二目标导线段上且位于第二数据线之后指的是：第二切割点位于两段第二目标导线段上，且沿数据线扫描方向位于第二数据线之后。第一数据线的上一条数据线指的是沿数据线扫描方向位于第一数据线之前且与第一数据线相邻的一条数据线。
示例地，请继续参考图10，第一公共电极线33c、第二公共电极线33d和第三公共电极线33e沿栅线扫描方向x依次排布，第二数据线32d为第一数据线32c的上一数据线，第一栅线31c为第一公共电极线33c对应的目标栅线(也即是距离第一公共电极线33c最近的栅线)，第二栅线31d为第二公共电极线33d对应的目标栅线(也即是距离第二公共电极线33d最近的栅线)，第三公共电极 34e位于第一栅线31c、第二栅线31d、第一数据线32c和第二数据线32d围成的像素区中，第一公共电极34c、第三公共电极34e和第二公共电极34d沿栅线扫描方向x依次排布，多个切割点包括：两段第一目标导线段(第一公共电极线33c与第一数据线32c交叉的目标导线段，以及，第二公共电极线33d与第一数据线32c交叉的目标导线段，图10中未标出)上的第一切割点P1和P2，两段第二目标导线段(第一公共电极线33c与第二数据线32d交叉的目标导线段，以及，第二公共电极线33d与第二数据线32d交叉的目标导线段，图10中未标出)上的第二切割点P3和P4，第一公共电极线33c与第一公共电极34c的桥接线39上的第三切割点P5，以及，第三公共电极线33e与第二公共电极34d的桥接线39上的第四切割点P6，第一切割点P1和P2沿数据线扫描方向y位于第一数据线32c之后，第二切割点P3和P4沿数据线扫描方向y位于第二数据线32d之后。
步骤903、从第一修复点将第一数据线与第一公共电极线连接，并从第二修复点将第一数据线与第二公共电极线连接。
可选地，从第一修复点将第一数据线与第一公共电极线连接可以包括：通过激光焊接工艺，从第一修复点将第一数据线与第一公共电极线焊接；从第二修复点将第一数据线与第二公共电极线连接可以包括：通过激光焊接工艺，从第二修复点将第一数据线与第二公共电极线焊接。
由于数据线与公共电极线异层分布，因此可以先在数据线与公共电极线之间的膜层上打孔，并通过数据线与公共电极线之间的膜层上的孔将数据线与公共电极线焊接。可选地，可以从第一修复点，在第一数据线与第一公共电极线之间的膜层上形成第一焊接孔，从第一焊接孔将第一数据线与第一公共电极线焊接。从第二修复点，在第一数据线与第二公共电极线之间的膜层上形成第二焊接孔，从第二焊接孔将第一数据线与第二公共电极线焊接。
示例地，如图10所示，可以从第一修复点S1，在第一数据线32c与第一公共电极线33c之间的膜层上形成第一焊接孔(图10中未示出)，然后通过激光焊接工艺，从该第一焊接孔将第一数据线32c与第一公共电极线33c焊接；从第二修复点S2，在第一数据线32c与第二公共电极线33d之间的膜层上形成第二焊接孔(图10中未示出)，然后通过激光焊接工艺，从该第二焊接孔将第一数据线32c与第二公共电极线33d焊接。
步骤904、从每个切割点对相应的公共导线进行切割，公共导线包括第一目 标导线段、第二目标导线段和连接线。
可选地，从每个切割点对相应的公共导线进行切割可以包括：通过激光切割工艺，从每个切割点对相应的公共导线进行切割。其中，该公共导线指的是第一目标导线段、第二目标导线段以及连接公共电极线与公共电极的连接线(例如桥接线39)。
示例地，如图10所示，可以从切割点P1至P6中的每个切割点对相应的公共导线进行切割，例如，从第一切割点P1和P2分别对相应的第一目标导线段进行切割，从第二切割点P3和P4分别对相应的第二目标导线段进行切割，从第三切割点P5对第一公共电极线33c与第一公共电极34c的桥接线39进行切割，从第四切割点P6对第三公共电极线33e与第二公共电极34d的桥接线39进行切割。其中，对图10所示的显示基板修复后的示意图可以参考图11，结合图10和图11，第一修复点S1和第二修复点S2的数据线与公共电极线焊接，切割点P1至P6中的每个切割点的公共导线被切断。
在本申请实施例中，在执行上述步骤901至904之后，第一数据线的修复完成，对第一数据线修复之后，该显示基板在使用时，第一数据线上传输至断裂点的信号从第一修复点传输至第一公共电极线，依次通过第一公共电极线、第三公共电极和第二公共电极线传输至第二修复点，并从第二修复点传输回第一数据线。示例地，请参考图12，其示出了对图10所示的显示基板修复后第一数据线32c上的信号的传输路径示意图，其中，加粗箭头表示第一数据线32c上的信号的传输路径，参见图12并结合图10，第一数据线32c上传输至断裂点G的信号从第一修复点S1传输至第一公共电极线33c，依次通过第一公共电极线33c、第三公共电极34e和第二公共电极线33d传输至第二修复点S2，并从第二修复点S2传输回第一数据线32c，这样一来，数据线上的信号可以绕过断裂点传输回数据线，因此可以达到对数据线修复的效果。
本领域技术人员容易理解，图10所示的修复点和切割点仅仅是示例性的，修复点和切割点还可以位于其他位置，只要保证数据线上的信号可以绕过断裂点传输回数据线即可。但是，由于修复之后，数据线上的信号实际上是通过公共电极线和公共电极绕过断裂点传输的，这样一来，数据线上的信号会对公共电极线和公共电极上的信号产生影响，进而影响显示基板的显示，因此若将修复点和切割点设置在其他位置，数据线上的信号对显示基板的显示影响较大，而若根据图10设置修复点和切割点，可以最大限度的控制数据线上的信号对显 示基板的影响。示例地，参见图12并结合图10，第一数据线32c上的信号仅仅会影响第三公共电极34e和第三公共电极34d所在像素区的显示，而不会影响其他像素区的显示，因此第一数据线32c的修复对显示基板的影响较小。
综上所述，本申请实施例提供的显示基板的修复方法，在显示基板中，对于每条公共电极线，目标导线段上任一位置点与目标栅线之间的距离小于非目标导线段与该目标栅线之间的距离，目标导线段为该公共电极线与数据线交叉的导线段，非目标导线段为该公共电极线上除该目标导线段之外的导线段，因此该显示基板在不改变公共电极的面积的前提下，使公共电极与目标导电线之间的距离较大，从而公共电极和交叉位置(指的是公共电极线与数据线的交叉位置)之间的距离相对较大，便于焊接工作的实施，对数据线修复的成功率较高且显示基板的开口率较高。
本申请实施例还提供了一种显示装置，该显示装置包括上述实施例提供的显示基板3，该显示装置可以为：显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪或穿戴设备等任何具有显示功能的产品或部件。
在本申请中，术语“第一”、“第二”、“第三”和“第四”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (21)

  1. 一种显示基板，包括：
    衬底基板，以及，位于所述衬底基板上的多条栅线、多条数据线、多条公共电极线和多个公共电极；
    所述多条栅线与所述多条数据线交叉限定出多个像素区，所述多个公共电极一一对应位于所述多个像素区中，所述多条栅线与所述多条公共电极线的延伸方向平行，所述多条栅线与所述多条公共电极线一一间隔排布；
    所述公共电极线包括多段目标导线段和非目标导线段，每段所述目标导线段为所述公共电极线与一条所述数据线交叉的导线段，所述非目标导线段为所述公共电极线上除所述目标导线段之外的导线段，对于每条所述公共电极线：所述目标导线段上任一位置点与目标栅线之间的距离小于所述非目标导线段与所述目标栅线之间的距离，所述目标栅线为距离所述公共电极线最近的所述栅线，位于所述目标栅线两侧且与所述目标栅线相邻的所述公共电极均与所述公共电极线连接。
  2. 根据权利要求1所述的显示基板，其中，
    对于每条所述公共电极线：所述目标导线段向靠近所述目标栅线的方向弯曲。
  3. 根据权利要求1或2所述的显示基板，其中，
    所述目标导线段为弧形导线段。
  4. 根据权利要求1至3任一所述的显示基板，其中，
    所述多个公共电极沿数据线扫描方向排布为多行，对于每条所述公共电极线：所述公共电极线和目标公共电极连接，并通过跨越所述目标栅线的桥接线和与所述目标公共电极相邻且位于同一行的公共电极连接，所述目标公共电极与所述公共电极线处于同一像素区。
  5. 根据权利要求1至4任一所述的显示基板，其中，
    与每条所述公共电极线相邻的两条所述栅线中，一条所述栅线与所述公共 电极线之间的距离小于另一条所述栅线与所述公共电极线之间的距离。
  6. 根据权利要求1至5任一所述的显示基板，其中，所述显示基板还包括：
    多个薄膜晶体管和多个像素电极，所述多个薄膜晶体管和所述多个像素电极分别一一对应位于所述多个像素区中，所述薄膜晶体管包括栅极、源极和漏极，所述栅极与距离所述栅极最近的所述栅线连接，所述源极与距离所述源极最近的所述数据线连接，所述漏极与所述薄膜晶体管位于同一像素区中的所述像素电极连接。
  7. 根据权利要求6所述的显示基板，其中，
    所述薄膜晶体管包括：沿远离所述衬底基板的方向依次分布的所述栅极、栅绝缘层、有源层、层间介质层和源漏极，所述源漏极包括所述源极和所述漏极，所述源极和所述漏极不接触，所述源极和所述漏极分别有源层接触；
    所述阵列基板还包括：位于所述公共电极与所述栅线之间的绝缘层，以及，位于所述源漏极与所述像素电极之间的钝化层。
  8. 根据权利要求1所述的显示基板，其中，
    与每条所述公共电极线相邻的两条所述栅线中，一条所述栅线与所述公共电极线之间的距离小于另一条所述栅线与所述公共电极线之间的距离，所述多个公共电极沿数据线扫描方向排布为多行，对于每条所述公共电极线：所述目标导线段为向靠近所述目标栅线的方向弯曲的弧形导线段，所述公共电极线和目标公共电极连接，并通过跨越所述目标栅线的桥接线和与所述目标公共电极相邻且位于同一行的公共电极连接，所述目标公共电极与所述公共电极线处于同一像素区；
    所述显示基板还包括：多个薄膜晶体管、多个像素电极、绝缘层和钝化层，所述多个薄膜晶体管和所述多个像素电极分别一一对应位于所述多个像素区中，所述薄膜晶体管包括沿远离所述衬底基板的方向依次分布的栅极、栅绝缘层、有源层、层间介质层和源漏极，所述源漏极包括源极和漏极，所述源极和所述漏极不接触，所述源极和所述漏极分别与所述有源层接触，所述栅极与距离所述栅极最近的所述栅线连接，所述源极与距离所述源极最近的所述数据线 连接，所述漏极与所述薄膜晶体管位于同一像素区中的所述像素电极连接，所述绝缘层位于所述公共电极与所述栅线之间，所述钝化层位于所述源漏极与所述像素电极之间。
  9. 一种显示基板的制造方法，所述方法包括：
    在衬底基板上形成多条栅线、多条数据线、多条公共电极线和多个公共电极；
    所述多条栅线与所述多条数据线交叉限定出多个像素区，所述多个公共电极一一对应位于所述多个像素区中，所述多条栅线与所述多条公共电极线的延伸方向平行，所述多条栅线与所述多条公共电极线一一间隔排布；所述公共电极线包括多段目标导线段和非目标导线段，每段所述目标导线段为所述公共电极线与一条所述数据线交叉的导线段，所述非目标导线段为所述公共电极线上除所述目标导线段之外的导线段，对于每条所述公共电极线：所述目标导线段上任一位置点与目标栅线之间的距离小于所述非目标导线段与所述目标栅线之间的距离，所述目标栅线为距离所述公共电极线最近的所述栅线，位于所述目标栅线两侧且与所述目标栅线相邻的公共电极均与所述公共电极线连接。
  10. 根据权利要求9所述的方法，其中，
    所述在衬底基板上形成多条栅线、多条数据线、多条公共电极线和多个公共电极，包括：
    在所述衬底基板上形成所述多个公共电极，所述多个公共电极阵列排布为多列；
    在形成有所述公共电极的所述衬底基板上形成所述多条栅线和所述多条公共电极线，每相邻的两条所述栅线之间具有一列所述公共电极；
    在形成有所述栅线和所述公共电极线的所述衬底基板上形成所述多条数据线，所述多条数据线与每条所述公共电极线的多段所述目标导线段一一交叉。
  11. 根据权利要求9或10所述的方法，其中，
    对于每条所述公共电极线：所述目标导线段向靠近所述目标栅线的方向弯曲。
  12. 根据权利要求9至11任一所述的方法，其中，
    所述目标导线段为弧形导线段。
  13. 根据权利要求9至12任一所述的方法，其中，
    所述多个公共电极还阵列排布为多行，对于每条所述公共电极线：所述公共电极线和目标公共电极连接，并通过跨越所述目标栅线的桥接线和与所述目标公共电极相邻且位于同一行的公共电极连接，所述目标公共电极与所述公共电极线处于同一像素区。
  14. 根据权利要求9至13任一所述的方法，其中，
    与每条所述公共电极线相邻的两条所述栅线中，一条所述栅线与所述公共电极线之间的距离小于另一条所述栅线与所述公共电极线之间的距离。
  15. 根据权利要求9至14任一所述的方法，其中，所述方法还包括：
    在所述衬底基板上形成多个薄膜晶体管和多个像素电极，所述多个薄膜晶体管和所述多个像素电极分别一一对应位于所述多个像素区中，所述薄膜晶体管包括栅极、源极和漏极，所述栅极与距离所述栅极最近的所述栅线连接，所述源极与距离所述源极最近的所述数据线连接，所述漏极与所述薄膜晶体管位于同一像素区中的所述像素电极连接。
  16. 根据权利要求15所述的方法，其中，
    所述薄膜晶体管包括：沿远离所述衬底基板的方向依次分布的所述栅极、栅绝缘层、有源层、层间介质层和源漏极，所述源漏极包括所述源极和所述漏极，所述源极和所述漏极不接触，所述源极和所述漏极分别有源层接触；
    所述方法还包括：
    在所述公共电极与所述栅线之间形成绝缘层；
    在所述源漏极与所述像素电极之间形成钝化层。
  17. 一种显示基板的修复方法，用于权利要求1至8任一项所述的显示基 板，所述方法包括：
    在第一数据线断裂时，根据所述第一数据线的断裂点确定第一修复点和第二修复点，所述第一修复点为第一公共电极线与所述第一数据线的交点，所述第二修复点为第二公共电极线与所述第一数据线的交点，所述第一公共电极线与所述第二公共电极线相邻且沿栅线扫描方向依次排布，所述断裂点位于所述第一公共电极线与所述第二公共电极线之间；
    根据所述第一修复点和所述第二修复点确定多个切割点，所述多个切割点包括：两段第一目标导线段上的第一切割点，两段第二目标导线段上的第二切割点、所述第一公共电极线与第一公共电极的连接线上的第三切割点，以及第三公共电极线与第二公共电极的连接线上的第四切割点，所述两段第一目标导线段为所述第一数据线与所述第一公共电极线交叉的目标导线段以及所述第一数据线与所述第二公共电极线交叉的目标导线段，所述两段第二目标导线段为第二数据线与所述第一公共电极线交叉的目标导线段以及所述第二数据线与所述第二公共电极线交叉的目标导线段，所述第二数据线为所述第一数据线的上一条数据线，所述第一公共电极、第三公共电极和所述第二公共电极相邻且沿栅线扫描方向依次排布在同一行中，所述第三公共电极位于第一栅线、第二栅线、所述第一数据线和所述第二数据线围成的像素区中，所述第一栅线为所述第一公共电极线对应的目标栅线，所述第二栅线为所述第二公共电极线对应的目标栅线，所述第二公共电极线与所述第三公共电极线相邻且沿所述栅线扫描方向依次排布；
    从所述第一修复点将所述第一数据线与所述第一公共电极线连接，并从所述第二修复点将所述第一数据线与所述第二公共电极线连接；
    从每个所述切割点对相应的公共导线进行切割，所述公共导线包括所述第一目标导线段、所述第二目标导线段和所述连接线。
  18. 根据权利要求17所述的方法，其中，
    所述第一切割点位于所述两段第一目标导线段上且位于所述第一数据线之后；
    所述第二切割点位于所述两段第二目标导线段上且位于所述第二数据线之后；
    所述第三切割点位于所述第一公共电极线与所述第一公共电极的桥接线上；
    所述第四切割点位于所述第三公共电极线与所述第二公共电极的桥接线上。
  19. 根据权利要求17或18所述的方法，其中，
    所述从所述第一修复点将所述第一数据线与所述第一公共电极线连接，包括：
    通过激光焊接工艺，从所述第一修复点将所述第一数据线与所述第一公共电极线焊接；
    所述从所述第二修复点将所述第一数据线与所述第二公共电极线连接，包括：
    通过激光焊接工艺，从所述第二修复点将所述第一数据线与所述第二公共电极线焊接。
  20. 根据权利要求17至19任一项所述的方法，其中，
    所述从每个所述切割点对相应的公共导线进行切割，包括：
    通过激光切割工艺，从每个所述切割点对相应的公共导线进行切割。
  21. 一种显示装置，包括权利要求1至8任一项所述的显示基板。
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