WO2020134861A1 - 显示基板、显示装置和显示基板的测试方法 - Google Patents

显示基板、显示装置和显示基板的测试方法 Download PDF

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Publication number
WO2020134861A1
WO2020134861A1 PCT/CN2019/121997 CN2019121997W WO2020134861A1 WO 2020134861 A1 WO2020134861 A1 WO 2020134861A1 CN 2019121997 W CN2019121997 W CN 2019121997W WO 2020134861 A1 WO2020134861 A1 WO 2020134861A1
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WIPO (PCT)
Prior art keywords
test
guide
signal lines
group
display substrate
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PCT/CN2019/121997
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English (en)
French (fr)
Inventor
陈宇霆
杨通
木素真
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/767,472 priority Critical patent/US11640076B2/en
Priority to EP19904630.1A priority patent/EP3904951A4/en
Publication of WO2020134861A1 publication Critical patent/WO2020134861A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/10—Dealing with defective pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the embodiments of the present disclosure relate to a display substrate, a display device, and a test method of a display substrate.
  • the liquid crystal display device In order to improve the yield of the display device and reduce the production cost of the display device, a defect detection process and a repair process are provided in a number of key process links in the production of the display device.
  • the liquid crystal display device will be described as an example below.
  • the manufacturing process of the liquid crystal display device includes an array substrate manufacturing process, a counter substrate manufacturing process, a liquid crystal cell manufacturing process, and a liquid crystal module manufacturing process.
  • the liquid crystal cell will be tested (for example, defective detection) to prevent the defective liquid crystal cell from entering the subsequent liquid crystal module manufacturing process as much as possible.
  • defective detection for example, defective detection
  • improving the defective detection rate at the stage of the liquid crystal cell test (Cell Test) has a greater impact on the production cost and production yield of the liquid crystal module manufacturing process stage.
  • At least one embodiment of the present disclosure provides a display substrate.
  • the display substrate includes a display area and a peripheral area provided outside the display area.
  • a first guide wire extending in the first direction is provided in the peripheral area, and the first guide wire includes a first end and a second end; a first test wire is also provided in the peripheral area, the The first position of the first test line on the first guide trace is electrically connected to the first guide trace, the first position is between the first end and the second end; and
  • the display area includes a plurality of first signal lines extending in a second direction different from the first direction and arranged in parallel, and the plurality of first signal lines of the first group are arranged along the first direction
  • the two first signal lines on the outermost side are respectively connected to the first end and the second end, and the remaining first signal lines of the plurality of first group of first signal lines are at the first end and
  • the second guide wires are connected between the second ends.
  • the first position is the midpoint of the resistance between the first end and the second end of the first guide trace.
  • the first test wire is also electrically connected to the first guide wire at a second position on the first guide wire, the second position is located at the first end and the second end Between and different from the first position.
  • first position and the second position are respectively located at a resistance 1/3 point and a resistance 2/3 point between the first end and the second end of the first guide trace.
  • the display area further includes a plurality of second signal lines extending in the first direction and arranged in parallel; the plurality of second signal lines cross and are insulated from the first group of first signal lines; and The first guide trace and the plurality of second signal lines are arranged on the same layer.
  • the first test line includes a first part extending in the second direction and a first extension part other than the first part, one end of the first part is electrically connected to the first guide trace, And the other end of the first portion is electrically connected to the first extension portion; the first portion and the plurality of first signal lines of the first group are provided in the same layer; and the first extension portion, the first The guide wiring and the plurality of second signal lines are arranged on the same layer.
  • the peripheral area includes a bonding area and a bonding opposing area; the bonding area and the bonding opposing area are respectively located on both sides of the display area along the second direction; and the first A guide wire is set in the bonding opposing area.
  • the bonding area includes a first test pad, one end of the first test line is electrically connected to the first test pad, and the other end of the first test line is connected to the first test line at the first position
  • the first guide trace is electrically connected.
  • the bonding area includes a plurality of first signal pads of a first group, and the plurality of first signal lines are connected to the plurality of first signal pads in a one-to-one correspondence.
  • the peripheral area is also provided with a test control line;
  • the bonding opposing area further includes a plurality of first group of control switches, the first ends of the plurality of first group of control switches and the plurality of first
  • the first signal lines of the group correspond to one-to-one electrical connection, the second ends of the plurality of first group of control switches are electrically connected to the first guide traces, and the control ends of the plurality of first group of control switches are connected to the Test the electrical connection of the control wire.
  • the bonding opposing area is further provided with a second guide trace, which extends along the first direction and includes a third end and a fourth end;
  • the peripheral area is also provided with A second test line, the second test line is electrically connected to the second guide trace at a third position on the second guide trace, the third position is located at the third end and the first Between the four ends;
  • the display area further includes a plurality of second groups of first signal lines extending in parallel along the second direction and of the plurality of second groups of first signal lines along the first The two first signal lines arranged on the outermost side are respectively connected to the third end and the fourth end, and the remaining first signal lines of the plurality of second group of first signal lines are located at the third Between the end and the fourth end is connected to the second guide trace; and the bonding area further includes a second test pad, one end of the second test line is electrically connected to the second test pad, And the other end of the second test line is electrically connected to the second guide trace at the third position.
  • the bonding opposing area is also provided with a third guide trace, which extends along the first direction and includes a fifth end and a sixth end;
  • the peripheral area is also provided with a third guide trace Three test wires, a fourth position of the third test wire on the third guide wire is electrically connected to the third guide wire, the fourth position is located at the fifth end and the sixth Between the ends;
  • the display area further includes a plurality of third groups of first signal lines extending in parallel along the second direction, and the plurality of third groups of first signal lines are arranged along the first direction The two outermost first signal lines are respectively connected to the fifth end and the sixth end, and the remaining first signal lines of the third plurality of first signal lines are at the fifth end and all The sixth end is connected to the third guide trace; and the bonding area further includes a third test pad, one end of the third test line is electrically connected to the third test pad, and the The other end of the third test line is electrically connected to the third guide trace at the fourth position.
  • a control guide wire extending along the first direction is provided in the bonding opposing area, the control guide wire includes a seventh end and an eighth end; the test control wire is in the control guide
  • the wiring is connected to the control guide wiring at a connection point between the seventh end and the eighth end; the plurality of first group of control switches are arranged on the outermost side along the first direction
  • the two control switches are connected to the seventh end and the eighth end respectively, and the remaining control switches of the first plurality of control switches are connected between the seventh end and the eighth end.
  • the control guide wiring connection is described.
  • the bonding opposing area further includes a plurality of second-group control switches, and the first ends of the plurality of second-group control switches are electrically connected to the plurality of second-group first signal lines in one-to-one correspondence, The second ends of the plurality of second groups of control switches are electrically connected to the second guide wiring, the control ends of the plurality of second groups of control switches are electrically connected to the test control lines; and the bonding The opposite area further includes a plurality of third group control switches, the first ends of the plurality of third group control switches are electrically connected to the plurality of third group first signal lines in one-to-one correspondence, and the plurality of third groups The second end of the group control switch is electrically connected to the third guide wiring, and the control ends of the plurality of third group control switches are electrically connected to the test control line.
  • the bonding area is also provided with a control signal pad electrically connected to the test control line; the first test pad and the second test pad are located on one side of the display area in the first direction , The third test pad and the control signal pad are located on the other side of the display area in the first direction.
  • the first resistance ratio, the second resistance ratio, and the third resistance ratio are equal to each other;
  • the first resistance ratio is the resistance value between the first end of the first guide trace and the first position The ratio of the resistance value between the first position and the second end of the first guide trace;
  • the second resistance ratio is the third end of the second guide trace and the A ratio of the resistance value between the third position to the resistance value between the third position and the fourth end of the second guide trace;
  • the third resistance ratio is the third guide The ratio of the resistance value between the fifth end and the fourth position of the trace to the resistance value between the fourth position and the sixth end of the third guide trace.
  • the first position is the midpoint of the resistance between the first end and the second end of the first guide trace;
  • the third position is the The midpoint of the resistance between the third end and the fourth end; and
  • the fourth position is the midpoint of the resistance between the fifth end and the sixth end of the third guide trace.
  • the plurality of first signal lines of the first group, the first signal lines of the second group, and the first signal lines of the third group are respectively used for transmitting sub-pixels displaying different colors of light Data signal.
  • the resistances of the first test line, the second test line, and the third test line are equal to each other.
  • At least one embodiment of the present disclosure provides a display device including the display substrate as described above and a main control circuit electrically connected to the display substrate.
  • At least one embodiment of the present disclosure provides a test method for a display substrate as described above, the method including: sending the first group of first signals to the plurality of first signals via the first test line and the first guide trace The line applies a first signal and detects based on the display of the display substrate.
  • FIG. 1 is a schematic plan view of a display substrate according to a technology
  • 2A is a test timing diagram of voltage signals at the first position and the third position on the second test line of the display substrate shown in FIG. 1;
  • FIG. 2B is an enlarged view of the voltage signal of the local area shown in FIG. 2A;
  • FIG. 3 is a simulation timing diagram of voltage signals at the first position and the third position on the second test line of the display substrate shown in FIG. 1;
  • FIG. 4 is a luminance distribution diagram of a first display sub-pixel, a second display sub-pixel, and a third display sub-pixel of the display substrate shown in FIG. 1 and a color distribution diagram of display pixels of the display substrate shown in FIG. 1;
  • FIG. 5 is a schematic plan view of a display substrate provided by some embodiments of the present disclosure.
  • FIG. 6 is a graph showing changes in voltage signals of the first end and the second end of the first guide trace of the display substrate shown in FIG. 5 with time;
  • FIG. 7 is a luminance distribution diagram of a first display sub-pixel, a second display sub-pixel, and a third display sub-pixel of the display substrate shown in FIG. 5 and a display pixel color and luminance distribution diagram of the display substrate shown in FIG. 5;
  • FIG. 9 is an exemplary block diagram of a display device provided by some embodiments of the present disclosure.
  • FIG. 10 is a schematic plan view of another display substrate provided by some embodiments of the present disclosure.
  • FIG. 11 is a cross-sectional view of the display substrate shown in FIG. 5;
  • FIG. 12 is another cross-sectional view of the display substrate shown in FIG. 5.
  • the inventor of the present disclosure has noticed that the current test traces of the display substrate are designed such that, during the test (eg, defective detection), the display substrate is caused by the test traces (eg, resistance and parasitic capacitance of the test trace) Brightness unevenness and/or color shift issues. Therefore, the defects related to the brightness and/or color shift existing in the display substrate are easily masked by the difference in brightness and/or color shift caused by the test wiring design of the display substrate, or the testing personnel and/or testing device (for example, optical automatic The detection device) tends to ignore the defects related to brightness and/or color misregistration in the display sub-pixels. This reduces the defective detection rate of the display substrate test (ie, increases the defective miss detection rate), increases the waste of resources in subsequent processes, and thus increases the manufacturing cost of the display substrate and the display device including the display substrate.
  • the test traces eg, resistance and parasitic capacitance of the test trace
  • the display substrate 500 may be a liquid crystal display substrate (for example, an array substrate of a liquid crystal display panel) or a self-luminous display substrate (for example, an array of organic light emitting diode display panels Substrate).
  • a liquid crystal display substrate for example, an array substrate of a liquid crystal display panel
  • a self-luminous display substrate for example, an array of organic light emitting diode display panels Substrate.
  • the display substrate 500 includes a display area 540 and a peripheral area provided outside the display area 540 (for example, around the display area 540 ).
  • the peripheral area includes the bonding area 530 and the bonding opposing area 520 opposite to the bonding area 530, and the bonding area 530 and the bonding opposing area 520 are respectively located along the second direction D2 different from the first direction D1.
  • the bonding region 530 extends in the first direction D1
  • the bonding opposite region 520 extends in the first direction D1.
  • the display area 540 includes a plurality of first signal lines 541 extending in parallel along the second direction D2 and a plurality of first signal lines extending in parallel along the second direction D2 542 and a plurality of third signal lines 543 extending in the second direction D2 and arranged in parallel.
  • the plurality of first signal lines 541 of the first group, the first signal lines 542 of the second group and the first signal lines 543 of the third group are respectively used to transmit data signals of sub-pixels displaying light of different colors.
  • the first signal line is a data line.
  • a plurality of first signal lines 541 of the first group are used to transmit data signals of the sub-pixels displaying green light
  • a plurality of first signal lines 542 of the second group are used to transmit data signals of the sub-pixels displaying red light
  • the third group of first signal lines 543 is used to transmit data signals of sub-pixels displaying blue light.
  • the display area 540 further includes a plurality of second signal lines 544 extending parallel to the first direction D1, the plurality of second signal lines 544 and the plurality of first signal lines (that is, the plurality of first signal lines A group of first signal lines 541, a plurality of second group first signal lines 542, and a plurality of third group first signal lines 543) cross and are insulated, thereby defining a plurality of display sub-pixels arranged in an array.
  • the second signal line 544 is a gate line, and the second signal line 544 is used to transmit a scan signal.
  • the display area 540 includes a plurality of display pixels (not shown in FIG. 1) arranged in an array, and each display pixel includes a first display sub-pixel, a second display sub-pixel, and a third display sub-pixel.
  • the first display sub-pixel The pixel, the second display sub-pixel, and the third display sub-pixel are electrically connected to the first set of first signal lines 541, the second set of first signal lines 542, and the third set of first signal lines 543, respectively, based on the first set of The data signals provided by a signal line 541, the second set of first signal lines 542, and the third set of first signal lines 543 emit light.
  • the first display sub-pixel, the second display sub-pixel, and the third display sub-pixel are used to emit green light, red light, and blue light, respectively.
  • the bonding area 530 includes a plurality of first group first signal pads 535, a plurality of second group first signal pads 536, and a plurality of third group first signal pads 537;
  • a signal line 541 is connected in a one-to-one correspondence with a plurality of first groups of first signal pads 535;
  • a plurality of second group of first signal lines 542 is connected in a one-to-one correspondence with a plurality of second groups of first signal pads 536;
  • a plurality of third The first signal lines 543 and the third signal pads 537 of the third group are connected in a one-to-one correspondence.
  • the first plurality of first signal pads 535, the second group of first signal pads 536, and the third group of first signal pads 537 are used to connect to the data driver through, for example, a flexible circuit board in a subsequent process To receive multiple data signals from the data driver and provide the multiple data signals to the corresponding first signal line.
  • the bonding area 530 further includes a plurality of second signal pads 538, and the plurality of second signal lines 544 are connected to the plurality of second signal pads 538 in a one-to-one correspondence.
  • the plurality of second signal pads 538 described above are used to connect to the gate driver through a flexible circuit board, for example, to receive a plurality of scan signals from the gate driver and provide the plurality of scan signals to the corresponding second ⁇ 544.
  • the bonding area 530 further includes a first test pad 531, a second test pad 532, a third test pad 533 and a control signal pad 534.
  • the peripheral area is provided with a first test line 511, a second test line 512, a third test line 513, and a test control line 514.
  • the first test line 511 is connected to the first test pad 531 and included in bonding
  • the first portion of the opposing region 520 extending along the first direction D1 is connected to the second test pad 532 and includes the second portion of the bonding opposing region 520 extending along the first direction D1
  • the third test line 513 is connected to the third test pad 533 and includes a third portion extending along the first direction D1 in the bonding opposing region 520
  • the test control line 514 is connected to the control signal pad 534 and including the first along the bonding opposing region 520 The fourth part extending in the direction D1.
  • the bonding area 530 further includes a scan test pad (not shown in the figure), and a scan test line (not shown in the figure) is also provided in the peripheral area. The two ends of the scan test line are respectively connected to the scan test pad and the second data ⁇ Wire electrical connection.
  • the bonding opposing area 520 further includes a plurality of first group control switches 524, a plurality of second group control switches 525 and a plurality of third group control switches 526.
  • the first ends of the plurality of first-group control switches 524 are electrically connected to the plurality of first-group first signal lines 541 in one-to-one correspondence, and the second ends of the plurality of first-group control switches 524 are connected to the first
  • the first part of the test line 511 is electrically connected; the third ends (control terminals) of the plurality of first set of control switches 524 are electrically connected to the fourth part of the test control line 514 to control the control signal based on the control signal pad 534
  • a first group of control switches 524 is turned on and off, thereby controlling whether the first test data signal applied to the first test pad 531 is applied to the plurality of first group of first signals via the first portion of the first test line 511 On line 541.
  • the first ends of the plurality of second group control switches 525 are electrically connected to the plurality of second group first signal lines 542 in one-to-one correspondence, and the second ends of the plurality of second group control switches 525 and the second
  • the second part of the test line 512 is electrically connected;
  • the third terminals (control terminals) of the plurality of second sets of control switches 525 are electrically connected to the fourth part of the test control line 514 to control based on the control signal applied to the control signal pad 534
  • a plurality of second group control switches 525 are turned on and off, thereby controlling whether the second test data signal applied to the second test pad 532 is applied to the plurality of second group second groups via the second part of the second test line 512
  • the first ends of the plurality of third group control switches 526 are electrically connected to the plurality of third group first signal lines 543 in one-to-one correspondence, and the second ends of the plurality of third group control switches 526 are connected to the third
  • the third part of the test line 513 is electrically connected; the third ends (control terminals) of the plurality of third sets of control switches 526 are electrically connected to the fourth part of the test control line 514 to control based on the control signal applied to the control signal pad 534
  • a plurality of third group control switches 526 are turned on and off, thereby controlling whether the third test data signal applied to the third test pad 533 is applied to the plurality of third group third groups via the third portion of the third test line 513 A signal line 543.
  • an invalid signal may be applied to the control signal pad 534 to make the control switch off.
  • the control switch is an N-type transistor, the invalid signal is Low level signal, or the control signal pad 534 is grounded or left floating. Turning off the control switch can prevent the first test line 511, the second test line 512 and the third test line 513 from adversely affecting the display device.
  • a data signal may be applied to at least one of the first test pad 531, the second test pad 532, and the third test pad 533, and the control signal pad 534 Apply a valid signal (that is, a level signal that causes the control switch to turn on) to turn on the control switch so that the data signal applied to at least one of the first test pad 531, the second test pad 532, and the third test pad 533 Can be transmitted to the corresponding signal line (data line).
  • a gate scan signal is applied to the scan signal pad so that the data signal transmitted to the corresponding signal line (data line) can be written into the display sub-pixel to drive the corresponding display sub-pixel to emit light.
  • the first test pad 531 and the second test pad 532 are located on the side of the display area 540 in the first direction D1, and the third test pad 533 and the control signal pad 534 are located in the first direction D1
  • the other side of the display area 540 the first test line 511 and the second test line 512 extend from the lower left corner of the display substrate 500 to the upper right corner of the display substrate 500, and the third test line 513 and the test control line 514 are formed by the display substrate 500 The lower right corner extends to the upper left corner of the display substrate 500.
  • the inventor of the present disclosure has noticed that disposing the first test pad 531, the second test pad 532, and the third test pad 533 on both sides of the display area 540 in the first direction D1, respectively, can satisfy a specific display substrate (for example, The wiring requirements of the display substrate with integrated gate driver (for example, small wiring space) can also increase the selection range of the test equipment (for example, the requirement for the number of test signal channels of the test equipment is reduced).
  • a specific display substrate for example, The wiring requirements of the display substrate with integrated gate driver (for example, small wiring space) can also increase the selection range of the test equipment (for example, the requirement for the number of test signal channels of the test equipment is reduced).
  • the inventors of the present disclosure have noted in research that for the same test line (eg, the first test line 511, the second test line 512, or the third test line 513), due to the presence of, for example, resistance and parasitic capacitance in the test line, the After the current flows through the test line, there is a difference in the phase delay and signal amplitude (or voltage drop) of the signal at different positions of the test line, which results in the brightness difference of the display area 540 at different positions at the same time, that is, in During the test of the display substrate, the display area 540 has a problem of uneven brightness.
  • the phase delay of the signal at different positions of the test line is different, so that the brightness changes of the display sub-pixels at different positions of the display area 540 are inconsistent, for example, making the display area 540 part of the position
  • the brightness of the display sub-pixel at the position reaches or delays to reach the maximum brightness or the minimum brightness in advance.
  • the voltage drops of the signals at different positions of the test line are different so that the brightness of the display sub-pixels at different positions of the display area 540 (brightness in a stable state of brightness) is inconsistent.
  • the gradient direction of the voltage drop (IR) of different test lines is different, for example, the first test line 511
  • the voltage drop on the second test line 512 gradually increases from left to right
  • the voltage drop on the third test line 513 gradually decreases from left to right.
  • the luminous intensity of the first display sub-pixel, the second display sub-pixel and the third display sub-pixel of the same display pixel of the display substrate 500 do not match, for example, they are respectively applied with a data signal with a value of 255 (value range is 0 to 255), the emitted red light, green light and blue light cannot be mixed to form a desired white light, thereby causing a color shift in at least part of the display area 540 of the display substrate 500.
  • the first portion of the first test line 511 includes a first position 5111 of the first test line 511, a second position 5112 of the first test line 511, and a first The third position 5113 of the test line 511.
  • the second part of the second test line 512 includes a first position 5121 of the second test line 512 arranged in sequence in the first direction D1, a second position 5122 of the second test line 512, and a second position of the second test line 512 Three positions 5123.
  • the third part of the third test line 513 includes a first position 5131 of the third test line 513 arranged sequentially in the first direction D1, a second position 5132 of the third test line 513, and a third position of the third test line 513 Three positions 5133.
  • FIG. 2A shows a timing diagram of the voltage signal 551 taken from the first position 5121 of the second test line 512 and the voltage signal 552 taken from the third position 5123 of the second test line 512 (the horizontal direction in FIG. 2A is time, The longitudinal direction is voltage).
  • FIG. 2B shows an enlarged view of the voltage signal (that is, the rising edge of the voltage signal) in the local area shown in FIG. 2A (the dotted frame area in FIG. 2A).
  • the amplitude of the voltage signal 551 taken from the first position 5121 of the second test line 512 is slightly larger than the amplitude of the voltage signal 552 taken from the third position 5123 of the second test line 512, which indicates that the phase Compared to the first position 5121 of the second test line 512, the voltage drop at the third position 5123 of the second test line 512 is larger; as shown in FIG.
  • the voltage taken from the first position 5121 of the second test line 512 The steepness of the rising edge of the signal 551 is greater than the steepness of the rising edge of the voltage signal 552 taken from the third position 5123 of the second test line 512, which indicates that For the voltage signal, the time delay of the voltage signal taken from the third position 5123 of the second test line 512 is relatively large.
  • the time-varying characteristics of the voltage signal taken from a position 5121 and the voltage signal taken from the third position 5123 of the second test line 512 were simulated.
  • the simulation results are shown in FIG. 3.
  • the horizontal axis of FIG. 3 is time, where u represents microseconds and m represents milliseconds.
  • the rising edge of the voltage signal 571 taken out from the first position 5121 of the second test line 512 is steeper than that from the second test line
  • the steepness of the rising edge of the voltage signal 572 taken from the third position 5123 of 512, and the amplitude of the voltage signal 571 taken from the first position 5121 of the second test line 512 is greater than the third position 5123 of the second test line 512
  • the amplitude of the extracted voltage signal 572 indicates that the voltage drop and the time delay at the third position 5123 of the second test line 512 are larger than the first position 5121 of the second test line 512. For example, as shown in FIG.
  • the rise time of the voltage signal taken from the first position 5121 of the second test line 512 is about 162 microseconds
  • the rise time of the voltage signal taken from the third position 5123 of the second test line 512 about 224 microseconds
  • the difference between the amplitude of the voltage signal 571 taken from the first position 5121 of the second test line 512 and the amplitude of the voltage signal 572 taken from the third position 5123 of the second test line 512 is about 213 millivolt.
  • the signal taken out from the first test line 511 and the signal taken out from the third test line 513 have similar voltage drop characteristics and time delay characteristics, which will not be repeated here.
  • the voltage drop at the first position 5111 of the first test line 511, the second position 5112 of the first test line 511, and the third position 5113 of the first test line 511 gradually increases, so The amplitude of the voltage signal taken from the first position 5111 of the first test line 511, the amplitude of the voltage signal taken from the second position 5112 of the first test line 511, and the third position 5113 of the first test line 511 The amplitude of the voltage signal gradually decreases.
  • the voltage drop at the first position 5131 of the third test line 513, the second position 5132 of the third test line 513, and the third position 5133 of the third test line 513 gradually decreases, so the extracted voltage gradually increases.
  • the time delay of the voltage signal at the first position 5111 of the first test line 511, the second position 5112 of the first test line 511, and the third position 5113 of the first test line 511 gradually increases;
  • the time delay of the voltage signals at the first position 5131 of the third test line 513, the second position 5132 of the third test line 513, and the third position 5133 of the third test line 513 gradually decreases.
  • the light emission luminance of the display sub-pixels is unevenly distributed along the first direction D1 (eg, gradually decreasing).
  • the following is an exemplary description with reference to FIG. 4.
  • FIG. 4 shows the brightness distribution map 561 of the first display sub-pixel in the first direction D1, the brightness distribution map 562 of the second display sub-pixel in the first direction D1, and the third display sub-pixel in the first direction D1
  • the brightness distribution diagram 563 here, the size of the brightness distribution diagram in the longitudinal direction represents the brightness of the display sub-pixel corresponding to the brightness distribution diagram.
  • the brightness distribution diagram shown in FIG. 4 is obtained based on the ideal situation, that is, a plurality of display sub-pixels (eg, the first display sub-pixel) receive a predetermined data signal (eg, received data In the case where the signals are equal to each other, the plurality of display sub-pixels (for example, the first display sub-pixels) distributed in the first direction D1 have the same brightness.
  • the brightness of the first display sub-pixel (ie, the first display sub-pixel corresponding to the first position) driven by the test data signal taken from the first position 5111 of the first test line 511 is determined by The brightness of the first display sub-pixel (ie, the first display sub-pixel corresponding to the second position) driven by the test data signal taken from the second position 5112 of the first test line 511, and the brightness from the first test line 511
  • the brightness of the first display sub-pixel (ie, the first display sub-pixel corresponding to the third position) driven by the test data signal taken at the third position 5113 gradually decreases.
  • the brightness of the second display sub-pixel driven by the test data signal taken from the first position 5121 of the second test line 512, and the second display sub-pixel driven by the test data signal taken from the second position 5122 of the second test line 512 The brightness of the pixel and the brightness of the second display sub-pixel driven by the test data signal taken from the third position 5123 of the second test line 512 gradually decrease.
  • the brightness of the third display sub-pixel driven by the test data signal taken from the first position 5131 of the third test line 513, and the third display sub-pixel driven by the test data signal taken from the second position 5132 of the third test line 513 The brightness of the pixel and the brightness of the third display sub-pixel driven by the test data signal taken from the third position 5133 of the third test line 513 gradually increase.
  • the design of the test line of the display substrate 500 shown in FIG. 1 causes the display substrate 500 shown in FIG. 1 to have a problem of uneven brightness in the test.
  • FIG. 4 also shows a distribution map 564 of the colors displayed by the display substrate 500 along the first direction D1, where it is assumed that the first display sub-pixel, the second display sub-pixel, and the third display sub-pixel emit green light, red light, and red light, respectively. Blu-ray.
  • the design of the test line of the display substrate 500 shown in FIG. 1 causes the display substrate 500 shown in FIG. 1 to have a color shift problem in the test.
  • the display substrate 500 shown in FIG. 1 has a problem of uneven brightness and/or color misregistration due to the design of the test wiring during the test (eg, poor detection), which may cause the display substrate 500 to exist for other reasons.
  • the brightness-related defects are masked by the difference in brightness and/or color shift caused by the design of the test traces of the display substrate 500, or the inspectors and/or detection devices (eg, optical automatic detection devices) tend to ignore the presence of the display substrate 500 Related to brightness and/or color cast.
  • This reduces the defective detection rate in the test of the display substrate 500 that is, increases the defective miss detection rate
  • increases the waste of resources in subsequent processes and increases the display substrate 500 and the display including the display substrate 500
  • the production cost of the device For example, when the amplitude of the test data signal is weak, the problem of uneven brightness and/or color shift in the display substrate 500 during the test (eg, poor detection) will be more obvious.
  • At least one embodiment of the present disclosure provides a display substrate, a display device, and a display substrate testing method.
  • the display substrate includes a display area and a peripheral area provided outside the display area.
  • a first guide wire extending in the first direction is provided in the peripheral area, and the first guide wire includes a first end and a second end; a first test wire is also provided in the peripheral area, and the first test wire is located in the first guide
  • the first position on the trace is electrically connected to the first guide trace, the first position is between the first end and the second end;
  • the display area includes a plurality of strips extending in parallel in a second direction different from the first direction and arranged in parallel
  • the first signal lines of the first group, the two first signal lines arranged on the outermost side in the first direction among the plurality of first signal lines of the first group are respectively connected to the first end and the second end, and the plurality of first groups
  • the remaining first signal lines of the first signal lines are connected to the first guide trace between the first end and the second end
  • the display substrate can reduce the brightness difference of the display substrate in the test, improve the uniformity of the display substrate display brightness, thereby can reduce the missed detection caused by the uneven brightness of the display substrate, and improve the defect of the display substrate test stage The detection rate.
  • the display substrate can also reduce the color deviation of the display substrate during the test, so it can reduce the missed detection caused by the color deviation of the display substrate, and can further increase the defective detection rate of the display substrate during the test stage.
  • the display substrate 100 may be a liquid crystal display substrate (for example, an array substrate of a liquid crystal display panel) or a self-luminous display substrate (for example, organic light-emitting Array substrate of diode (OLED) display panel).
  • the display substrate is formed through a semiconductor manufacturing process and includes a stacked structure.
  • the display substrate 100 includes a display area 140 and a peripheral area provided outside the display area 140; the peripheral area is provided with a first guide trace 121 extending along the first direction D1, the first guide trace 121 Including the first end 1211 and the second end 1212; a first test line 111 is also provided in the surrounding area, and the first position of the first test line 111 on the first guide trace 121 is electrically connected to the first guide trace 121
  • the first position 1213 is located between the first end 1211 and the second end 1212.
  • the first guide trace by providing the first guide trace 121 extending in the first direction D1 and connecting the first test line 111 to the first position 1213 of the first guide trace 121, the first guide trace can be made
  • the amplitude of the voltage signal on 121 increases first and then decreases along the first direction D1, that is, the amplitude of the voltage signal at the first position 1213 of the first guide trace 121 is the largest, and the amplitude of the voltage signal changes from the first position 1213 gradually decreases toward both sides of the first position 1213, so that the phase delay of the voltage signal on the first guide trace 121 decreases first and then increases along the first direction D1. Therefore, compared to the solution in which the amplitude and the signal delay of the voltage signal on the test line in the display substrate 500 shown in FIG.
  • the display substrate 100 shown in FIG. 5 can reduce the first guide The difference in the amplitude and phase delay of the voltage signal on the line 121, and thus can reduce the brightness difference of the display substrate 100 along the first direction D1, improve the brightness uniformity of the display substrate 100, thereby reducing the brightness unevenness caused by the display substrate 100
  • the resulting missed inspections increase the defective detection rate of the display board during the test phase.
  • the following is an exemplary description with reference to the display substrate 100 shown in FIG. 5.
  • a second guide trace 122 is also provided in the peripheral area, and the second guide trace 122 extends along the first direction D1 and includes a third end 1221 and a fourth end 1222;
  • the second test line 112, the third position 1223 of the second test line 112 on the second guide trace 122 is electrically connected to the second guide trace 122, and the third position 1223 is located between the third end 1221 and the fourth end 1222.
  • a third guide trace 123 is also provided in the peripheral area.
  • the third guide trace 123 extends along the first direction D1 and includes a fifth end 1231 and a sixth end 1232; the peripheral area is also provided with a third
  • the fourth position 1233 of the third test line 113 on the third guide trace 123 is electrically connected to the third guide trace 123, and the fourth position 1233 is located between the fifth end 1231 and the sixth end 1232.
  • the first end 1211 and the second end 1212 may or may not be physical ends of the first guide trace 121.
  • the first guide trace 121 may have an extended portion beyond the first end 1211 and the second end 1212, since this portion does not participate in transmitting signals, the technical effect of the above wiring is not affected.
  • FIG. 5 exaggerates the spacing between adjacent signal lines, so that the first end 1211 and the second end 1212 shown in FIG. 5 do not look like the first guide trace 121 Physical end.
  • the extension portion eg, a few hundred microns
  • the first end 1211 and the second end 1212 can be used as the physical ends of the first guide trace 121.
  • the third end 1221 and the fourth end 1222 may also serve as the physical ends of the second guide trace 122
  • the fifth end 1231 and the sixth end 1232 may also serve as the third guide trace 123. Physical end.
  • first end 1211 and the second end 1212 may not be the physical ends of the first guide trace 121
  • third end 1221 and the fourth end 1222 may not be the physical ends of the second guide trace 122
  • the fifth end 1231 and the sixth end 1232 may not be the physical end of the third guide trace 123.
  • this example will be elaborated later and will not be repeated here.
  • the first guide trace 121, the second guide trace 122, and the third guide trace 123 are arranged in the same layer.
  • the same patterning process can be used to pattern the same film layer to obtain the first guide trace 121 2.
  • the second guide trace 122 and the third guide trace 123 thereby simplifying the manufacturing process of the display substrate 100.
  • the settings on the same layer may be located in the same horizontal plane, or may not be located in the same horizontal plane.
  • the arrangement of the first guide trace 121, the second guide trace 122 and the third guide trace 123 in the same layer means that the first guide trace 121 and the second guide trace 122 are in a direction perpendicular to the display substrate There are no other layers, there is no other layer between the first guide trace 121 and the third guide trace 123, and there is no other layer between the second guide trace 122 and the third guide trace 123.
  • other same-layer settings in some embodiments of the present disclosure may also have similar definitions, which will not be described in detail later.
  • the first guide trace 121, the second guide trace 122, and the third guide trace 123 may also be located in at least two structural layers, respectively.
  • the first guide trace 121 and the second guide trace 122 are located in the same structural layer, and the third guide trace 123 is located in another structural layer.
  • the first guide trace 121, the second guide trace 122, and the third guide trace 123 may also be located in different structural layers, in this case, the first guide trace 121 is located in the first structural layer
  • the second guide trace 122 is located in the second structure layer
  • the third guide trace 123 is located in the third structure layer.
  • the first test line 111 includes a first portion 1111 extending along the second direction D2, and a first portion including an end extending from the first test pad 131 to the first portion 1111 and connected to an end of the first portion 1111 Extending part 1112.
  • the second test line 112 includes a second portion 1121 extending along the second direction D2, and includes a second extension portion 1122 extending from the second test pad 132 to one end of the second portion 1121 and connected to one end of the second portion 1121 .
  • the third test line 113 includes a third portion 1131 extending along the second direction D2, and includes a third extension portion 1132 extending from the third test pad 133 to one end of the third portion 1131 and connected to one end of the third portion 1131 .
  • the first part 1111, the second part 1121 and the third part 1131 are in the same layer and are arranged parallel to each other, for example, the second part 1121 and the third part 1131 are arranged on the first part 1111 in the first direction D1 On both sides.
  • the distance between the second portion 1121 and the first portion 1111 in the first direction D1 and the distance between the third portion 1131 and the first portion 1111 in the first direction D1 (for example, about several microns to several tens of microns)
  • the length of the guide traces (first guide trace 121, second guide trace 122, and third guide trace 123) in the first direction D1 is negligible.
  • the distance between the second portion 1121 and the first portion 1111 in the first direction D1 is equal to the distance between the third portion 1131 and the first portion 1111 in the first direction D1.
  • the resistance value between the first end 1211 and the first position 1213 of the first guide trace 121 and the resistance value between the first position 1213 and the second end 1212 of the first guide trace 121 Ratio (ie, the first resistance ratio), the resistance between the third end 1221 and the third position 1223 of the second guide trace 122 and the third position 1223 and the fourth end 1222 of the second guide trace 122
  • the ratio of the resistance between (ie, the second resistance ratio), and the resistance between the fifth end 1231 of the third guide trace 123 and the fourth position 1233 and the fourth position of the third guide trace 123 The ratio of the resistance values between 1233 and the sixth end 1232 (that is, the third resistance ratio) is equal to each other.
  • the first extension portion 1112 of the first test line 111 includes a first laterally extending portion and a first longitudinal extension portion that are in contact with each other
  • the second extension portion 1122 of the second test line 112 includes each other
  • the second laterally extending portion and the second longitudinally extending portion, the third test line 113 and the third extending portion 1132 include a third laterally extending portion and a third longitudinally extending portion that are in contact with each other.
  • the first laterally extending portion, the second laterally extending portion, and the third laterally extending portion respectively extend along the first direction D1, and the first longitudinally extending portion, the second longitudinally extending portion, and the third longitudinally extending portion Each extends in the second direction D2.
  • the structures of the first extension portion 1112, the second extension portion 1122, and the third extension portion 1132 are not limited to the structures shown in FIG. 5 and will not be repeated here.
  • the first extension portion 1112, the second extension portion 1122, and the third extension portion 1132 are provided in the same layer.
  • the first test line 111, the second test line 112, and the third test line 113 are electrically insulated from each other.
  • the first test line 111, the second test line 112 and the third test line 113 are all made of metal (for example, aluminum or aluminum alloy, copper or copper alloy, etc.) to reduce the first test line 111 and the second test The resistance of the line 112 and the third test line 113 and the voltage drop caused by the first test line 111, the second test line 112, and the third test line 113.
  • the surrounding area includes the bonding area 130 and the bonding opposing area 120 opposite to the bonding area, the bonding area 130 and the bonding opposing area 120 are along the second direction different from the first direction D1
  • the directions D2 are respectively located on opposite sides of the display area 140, and the bonding area 130 and the bonding opposing area 120 extend along the first direction D1.
  • the first direction D1 and the second direction D2 are perpendicular to each other.
  • the first guide trace 121, the second guide trace 122 and the third guide trace 123 are provided in the bonding opposing area 120.
  • the embodiments of the present disclosure are described below by taking the first guide trace 121, the second guide trace 122, and the third guide trace 123 provided in the bonding opposing area 120 as examples, but the embodiments of the disclosure are not limited to this.
  • the display area 140 includes a plurality of first signal lines 141 extending in parallel along the second direction D2 and a plurality of first signal lines extending in parallel along the second direction D2 142 and a plurality of third signal lines 143 extending in the third direction and arranged in parallel.
  • the two first signal lines arranged on the outermost side along the first direction D1 are connected to the first end 1211 and the second end 1212, respectively.
  • the remaining first signal lines in the group of first signal lines 141 are connected to the first guide trace 121 between the first end 1211 and the second end 1212.
  • the first end 1211 and the second end 1212 refer to the two first signals that are arranged on the outermost side along the first direction D1 of the first guide trace 121 and the plurality of first signal lines 141 of the first group
  • the first end 1211 and the second end 1212 may be the physical end of the first guide trace 121 or may not be the physical end of the first guide trace 121.
  • the two first signal lines arranged on the outermost side in the first direction D1 among the plurality of second group first signal lines 142 are respectively connected to the third end 1221 and the fourth end 1222, and the plurality of second The remaining first signal lines of the group of first signal lines 142 are connected to the second guide trace 122 between the third end 1221 and the fourth end 1222.
  • the third end 1221 and the fourth end 1222 refer to the two first signals that are arranged on the outermost side along the first direction D1 among the plurality of second signal lines 142 of the second guide trace 122 and the plurality of first signal lines 142 At the point where the line is connected, the third end 1221 and the fourth end 1222 may be the physical end of the second guide trace 122 or may not be the physical end of the second guide trace 122.
  • the two first signal lines arranged on the outermost side along the first direction D1 are respectively connected to the fifth end 1231 and the sixth end 1232, and the plurality of third The remaining first signal lines in the group of first signal lines 143 are connected to the third guide trace 123 between the fifth end 1231 and the sixth end 1232.
  • the fifth end 1231 and the sixth end 1232 refer to the two first signals of the third guide trace 123 and the third group of the first signal lines 143 arranged on the outermost side in the first direction D1
  • the fifth end 1231 and the sixth end 1232 may be the physical end of the third guide trace 123 or may not be the physical end of the third guide trace 123.
  • connection of the second group of first signal lines 142 and the second guide trace 122 The points, the connection points of the first set of first signal lines 141 and the first guide trace 121, and the connection points of the third set of first signal lines 143 and the third guide trace 123 are arranged in sequence in the first direction D1 In addition, there is no other connection point between the guide trace and the first signal line between the three connection points.
  • the distance between the connection point of the first set of first signal lines 141 and the first guide trace 121 and the connection point of the second set of first signal lines 142 and the second guide trace 122 is different from the guide trace 121-
  • the length of 123 is negligible compared to that between the connection point of the first group of first signal lines 141 and the first guide trace 121 and the connection point of the third group of first signal lines 143 and the third guide trace 123
  • the distance is negligible compared to the length of the guide traces 121-123, so the data received by the adjacent first group of first signal lines 141, second group of first signal lines 142, and third group of first signal lines 143
  • the signals can match each other.
  • the distance between the connection point of the first group of first signal lines 141 and the first guide trace 121 and the connection point of the second group of first signal lines 142 and the second guide trace 122 is equal to that of the first group
  • the data signals received by the adjacent first group of first signal lines 141, second group of first signal lines 142, and third group of first signal lines 143 may be the same as the first display sub-pixels in the same display pixel,
  • the second display sub-pixel and the third display sub-pixel are connected, so that the data signals received by the first display sub-pixel, the second display sub-pixel and the third display sub-pixel can match each other, and then the first display sub-pixel and the second display
  • the light emitted by the sub-pixel and the third display sub-pixel may be mixed into white light.
  • the guide trace is a conductive structure that extends with a uniform thickness and a uniform width.
  • the first signal line is a data line; a plurality of first signal lines 141, a plurality of second signal lines 142, and a plurality of first signal lines 143 of a third group are respectively used to transmit different colors.
  • Light sub-pixel data signal For example, a plurality of first signal lines 141 of the first group are used to transmit data signals of the sub-pixels displaying green light, and a plurality of first signal lines 142 of the second group are used to transmit data signals of the sub-pixels displaying red light.
  • the third set of first signal lines 143 is used to transmit data signals of sub-pixels displaying blue light.
  • the display area 140 further includes a plurality of second signal lines 144 extending in the first direction D1 and arranged in parallel.
  • the plurality of second signal lines 144 cross and are insulated from the plurality of first signal lines. The intersection defines Multiple display sub-pixels arranged in an array.
  • the second signal line 144 is a gate line; a plurality of second signal lines 144 are used to transmit scan signals.
  • an insulating layer is provided between the structural layer where the first signal lines are located and the structural layer where the second signal lines 144 are located.
  • each display sub-pixel includes a pixel driving circuit, and the pixel driving circuit may include devices such as transistors and capacitors.
  • each display sub-pixel may further include a light-emitting device.
  • the display area 140 includes a plurality of display pixels (not shown in FIG. 5) arranged in an array, and each display pixel includes a first display sub-pixel 1451, a second display sub-pixel 1452, and a third display sub-pixel 1453.
  • a display sub-pixel 1451, a second display sub-pixel 1452, and a third display sub-pixel 1453 are electrically connected to the first set of first signal lines 141, the second set of first signal lines 142, and the third set of first signal lines 143, respectively.
  • Light is emitted based on the data signals provided by the first group of first signal lines 141, the second group of first signal lines 142, and the third group of first signal lines 143.
  • the first display sub-pixel 1451, the second display sub-pixel 1452, and the third display sub-pixel 1453 are used to emit green light, red light, and blue light, respectively.
  • the arrangement manner of the first display sub-pixel 1451, the second display sub-pixel 1452 and the third display sub-pixel 1453 can be set according to actual application requirements.
  • the arrangement of the first display sub-pixel 1451, the second display sub-pixel 1452, and the third display sub-pixel 1453 can adopt an island-type (Island Type) arrangement, a stripe (Stipe Type) arrangement, and a triangular shape (Delta-shaped) arrangement, Mosaic (Mosaic Type) arrangement
  • the arrangement of the signal lines can be based on the arrangement of the signal lines shown in FIG. 5 according to the first display sub-pixel 1451, the second The arrangement of the display sub-pixels 1452 and the third display sub-pixels 1453 is adaptively adjusted, and will not be repeated here.
  • the first portion 1111, the second portion 1121, the third portion 1131 and the first signal line are arranged in the same layer
  • the third The third extension portion 1132 of the test line 113, the first guide trace 121, the second guide trace 122, and the third guide trace 123 are disposed in the same layer as the second signal line 144, thereby further simplifying the display substrate 100 Craftsmanship.
  • the first extension portion 1112 of the first test line 111, the second extension portion 1122 of the second test line 112, and the third extension portion 1132 of the third test line 113 are respectively The two parts 1121 and the third part 1131 are connected, and the first part 1111, the second part 1121 and the third part 1131 are connected to the first guide trace 121, the second guide trace 122 and the third guide trace 123 via via holes, respectively, And the first signal line is connected to the first guide trace 121, the second guide trace 122, and the third guide trace 123 via via holes, respectively.
  • 11 shows the connection between the first extension portion 1112 of the first test line 111, the first portion 1111 of the first test line 111, the first guide trace 121 and the first group of first signal lines 141 .
  • 11 is a cross-sectional view taken along the wiring path of the first extension portion 1112 of the first test line 111, the first portion 1111 of the first test line 111, the first guide trace 121, and the first group of first signal lines 141.
  • the display substrate 100 includes a base substrate 1001; on the base substrate 1001, the first portion 1111 of the first test line 111 and the first group of first signal lines 141 are arranged in the same layer, and the first test line 111 The first extension portion 1112 and the first guide trace 121 are arranged in the same layer.
  • the first portion 1111 of the first test line 111 and the first group of first signal lines 141 are connected to the first extension portion 1112 of the first test line 111 through the insulating layer 1003 Insulated from the first guide trace 121; the first extension portion 1112 of the first test line 111 is connected to the first portion 1111 of the first test line 111 through the first via 10031, and the first portion 1111 of the first test line 111 passes through the second
  • the via 10032 is connected to the first guide trace 121, and the first guide trace 121 is connected to the first group of first signal lines 141 through the third via 10033; the first via 10031, the second via 10032, and the third via 10033 are all disposed in the insulating layer 1003 and are conductive vias.
  • the first portion 1111 of the first test line 111 and the first group of first signal lines 141 are insulated from the base substrate 1001 by the insulating layer 1002; however, the embodiments of the present disclosure are not limited to this, and the insulating layer 1002 may be provided without The first portion 1111 of the first test line 111 and the first group of first signal lines 141 are directly formed on the base substrate 1001. In FIG.
  • the first extension portion 1112 and the first guide trace 121 of the first test line 111 are located above the first portion 1111 of the first test line 111 and the first group of first signal lines 141; however, the present disclosure implements The example is not limited thereto, and the first portion 1111 of the first test line 111 and the first group of first signal lines 141 may be disposed above the first extension portion 1112 of the first test line 111 and the first guide trace 121.
  • the second extension portion 1122 of the second test line 112, the second portion 1121 of the second test line 112, the second guide trace 122 and the second group of first signal lines 142 can be used in a similar manner to FIG. 11 Connect.
  • the third extension portion 1132 of the third test line 113, the third portion 1131 of the third test line 113, the third guide trace 123, and the third group of first signal lines 143 can be used in a similar manner to FIG. Connect.
  • the first extension portion 1112 of the first test line 111, the second extension portion 1122 of the second test line 112, and the third extension portion 1132 of the third test line 113 may also be different from the first portion 1111, the second portion 1121 and the third part 1131 and the first signal line are arranged on the same layer.
  • the first extension portion 1112 of the first test line 111, the second extension portion 1122 of the second test line 112, and the third extension portion 1132 of the third test line 113 can be directly connected to the first portion 1111 by direct overlap ,
  • the second part 1121 and the third part 1131 are electrically connected without vias.
  • the three guide traces 123 are connected, and the first signal lines are connected to the first guide trace 121, the second guide trace 122, and the third guide trace 123 via via holes, respectively.
  • 12 is another cross-section taken along the routing path of the first extension portion 1112 of the first test line 111, the first portion 1111 of the first test line 111, the first guide trace 121 and the first group of first signal lines 141 Figure. As shown in FIG. 12, the first extension portion 1112 of the first test line 111 directly overlaps the first portion 1111 of the first test line 111, so that it is not necessary to provide the first via hole 10031 shown in FIG. 11; 12, the other structure of FIG. 12 is the same as that of FIG. 11 and will not be repeated here.
  • the second extension portion 1122 of the second test line 112 and the second portion 1121 of the second test line 112 may directly overlap in a similar manner to FIG. 12.
  • the third extension portion 1132 of the third test line 113 and the third portion 1131 of the third test line 113 may directly overlap in a similar manner to FIG. 12.
  • the bonding area 130 further includes a plurality of first group first signal pads 135, a plurality of second group first signal pads 136, and a plurality of third group first signal pads 137; a plurality of first groups
  • the first signal lines 141 are correspondingly connected to the plurality of first groups of first signal pads 135;
  • the plurality of second group of first signal lines 142 are correspondingly connected to the plurality of second groups of first signal pads 136;
  • the three sets of first signal lines 143 are connected to the plurality of third sets of first signal pads 137 in one-to-one correspondence.
  • the first plurality of first signal pads 135, the second group of first signal pads 136, and the third group of first signal pads 137 are used to connect to the data driver through, for example, a flexible circuit board in a subsequent process To receive multiple data signals from the data driver and provide the multiple data signals to the corresponding first signal line.
  • the bonding area 130 further includes a plurality of second signal pads 138, and the plurality of second signal lines 144 are connected to the plurality of second signal pads 138 in one-to-one correspondence.
  • the above plurality of second signal pads 138 are used to connect to the gate driver through, for example, a flexible circuit board in a subsequent process to receive a plurality of scan signals from the gate driver and provide the plurality of scan signals to the corresponding second ⁇ 144.
  • Signal line 144 a gate driving circuit (ie, GOA) is integrated on the display substrate, and accordingly, the bonding area 130 further includes a scan start signal (STV), a clock signal, etc. for the gate driving circuit Signal pad.
  • STV scan start signal
  • clock signal etc.
  • the bonding area 130 may not be provided with the first signal pads 135-137 and the second signal pad 138.
  • multiple traces may be used to connect the first signal line and the second signal line.
  • the plurality of traces are connected to the gate driver and the data driver.
  • the bonding area 130 further includes a first test pad 131, a second test pad 132, and a third test pad 133, which are used to contact the test probe during the test to receive corresponding test data signals.
  • the bonding area 130 may further include a scanning signal test pad (not shown in the figure).
  • one end of the first test line 111 is electrically connected to the first test pad 131 and the other end of the first test line 111 is electrically connected to the first position 1213, thereby applying the first test pad 131 on the first test pad 131
  • a test data signal can be applied to the plurality of first signal lines 141 via the first test line 111 and the first guide trace 121.
  • One end of the second test line 112 is electrically connected to the second test pad 132 and the other end of the second test line 112 is electrically connected to the third position 1223, whereby the second test data signal applied to the second test pad 132 can pass
  • the second test line 112 and the second guide trace 122 are applied to the plurality of second signal lines 142 of the second group.
  • One end of the third test line 113 is electrically connected to the third test pad 133 and the other end of the third test line 113 is electrically connected to the fourth position 1233, whereby the third test data signal applied to the third test pad 133 can pass
  • the third test line 113 and the third guide trace 123 are applied to the plurality of third signal lines 143 of the third group.
  • the overall resistances of the first test line 111, the second test line 112, and the third test line 113 are equal to each other, thereby making the voltage drops caused by the first test line 111, the second test line 112, and the third test line 113 mutually equal.
  • the widths, thicknesses and manufacturing materials of the first test line 111, the second test line 112 and the third test line 113 are the same, the first test line 111, the second test line 112 and the third test line 113 The length is also equal.
  • the amplitude of the first test data signal applied on the first test pad 131, the amplitude of the second test data signal applied on the second test pad 132, and the third applied on the third test pad 133 When the amplitudes of the test data signals are equal to each other, since the voltage drops caused by the first test line 111, the second test line 112, and the third test line 113 are equal to each other, the amplitude of the data signal at the first position 1213, The amplitude of the data signal at the third position 1223 and the amplitude of the data signal at the fourth position 1233 match each other (eg, equal).
  • the overall resistance and length of the first test line 111, the second test line 112, and the third test line 113 may not be equal to each other.
  • the first test line 111, the second test The resistance difference information of the line 112 and the third test line 113 acquires the voltage drop difference between the first test line 111, the second test line 112, and the third test line 113, and obtains the corrected first test based on the above voltage drop difference
  • the data signal, the corrected second test data signal, and the corrected third test data signal, so that the corrected first test data signal, the corrected second test data signal, and the corrected third test data signal are respectively After being applied to the first test pad 131, the second test pad 132, and the third test pad 133, the amplitude of the data signal at the first position 1213, the amplitude of the data signal at the third position 1223, and the fourth position 1233
  • the amplitudes of the data signals at match eg, equal to) each other.
  • the requirements for the first test line 111, the second test line 112, and the third test line 113 e.g., Resistance consistency or length consistency requirements, which can improve the design flexibility of the test line and the difficulty of wiring.
  • the bonding area 130 further includes a control signal pad 134, and a test control line 114 is also provided in the peripheral area.
  • the test control line 114 is connected to the control signal pad 134 and included in the bonding opposing area 120 along the first direction D1 extended lateral portion 1141.
  • the bonding opposing area 120 further includes a plurality of first group control switches 124, a plurality of second group control switches 125 and a plurality of third group control switches 126.
  • the first ends of the plurality of first-group control switches 124 are electrically connected to the plurality of first-group first signal lines 141 in one-to-one correspondence, and the second ends of the plurality of first-group control switches 124 are connected to the first
  • the guide wire 121 is electrically connected;
  • the third end (control end) of the plurality of first group of control switches 124 is electrically connected to the lateral portion 1141 of the test control line 114 to control the plurality of first wires based on the control signal applied to the control signal pad 134
  • a group of control switches 124 is turned on and off, thereby controlling whether the first test data signal applied to the first test pad 131 is applied to the plurality of first group of first groups via the first test line 111 and the first guide trace 121
  • One signal line 141 One signal line 141.
  • the first ends of the plurality of second-group control switches 125 are electrically connected to the plurality of second-group first signal lines 142 in one-to-one correspondence, and the second ends of the plurality of second-group control switches 125 are connected to the second
  • the guide wire 122 is electrically connected;
  • the third end (control end) of the plurality of second sets of control switches 125 is electrically connected to the lateral portion 1141 of the test control line 114 to control the plurality of first wires based on the control signal applied to the control signal pad 134
  • the two sets of control switches 125 are turned on and off, thereby controlling whether the second test data signal applied to the second test pad 132 is applied to the plurality of second sets of the second test line 112 and the second guide trace 122 A signal line 142.
  • the first ends of the plurality of third group control switches 126 are electrically connected to the plurality of third group first signal lines 143 in one-to-one correspondence, and the second ends of the plurality of third group control switches 126 are connected to the third
  • the guide wire 123 is electrically connected; the third end (control end) of the plurality of third sets of control switches 126 is electrically connected to the lateral portion 1141 of the test control line 114 to control the plurality of first switches based on the control signal applied to the control signal pad 134
  • the three groups of control switches 126 are turned on and off, thereby controlling whether the third test data signal applied to the third test pad 133 is applied to the plurality of third groups of third groups via the third test line 113 and the third guide trace 123 A signal line 143.
  • control switches 124-126 may be transistors, such as N-type transistors or P-type transistors, one of the first and second terminals may be a source, the other is a drain, and the third terminal is a gate.
  • the transistors as the control switches 124 to 126 can be formed together with the transistors in the display sub-pixels in the display area during the preparation of the display substrate, for example, thereby simplifying the preparation process. For example, when a display device including the display substrate 100 shown in FIG.
  • an invalid signal (a level signal that causes the control switch to turn off) may be applied to the control signal pad 134 to cause the control switch to turn off, thereby avoiding
  • the first test line 111, the second test line 112, and the third test line 113 adversely affect the normal display of the display device.
  • the display substrate 100 may not be provided with a control switch, a control signal pad, and a control line. In this case, after completing the test of the display substrate 100, pass The cutting removes the first guide trace 121, the second guide trace 122, and the third guide trace 123 located in the bonding opposing area 120, which will not be repeated here.
  • a test data signal may be applied to at least one of the first test pad 131, the second test pad 132, and the third test pad 133, and the control signal pad
  • An effective signal (a level signal that causes the control switch to turn on) is applied to 134, so that the control switch is turned on, so that the test data signal applied to at least one of the first test pad 131, the second test pad 132, and the third test pad 133 It can be transmitted to the corresponding first signal line (data line), and a gate scan signal is applied to the scanning signal pad, so that the test data signal transmitted to the corresponding first signal line (data line) can drive the corresponding display
  • the sub-pixel emits light.
  • the first test pad 131 and the second test pad 132 are located on the side of the display area 140 in the first direction D1
  • the third test pad 133 and the control signal pad 134 are located in the display area in the first direction D1 140 on the other side.
  • placing the first test pad 131, the second test pad 132, and the third test pad 133 in the first direction D1 on both sides of the display area 140 may satisfy a specific display substrate 100 (eg, a GOA-based display substrate 100 ) Wiring requirements (for example, small wiring space) and/or increase the selection range of the test equipment (for example, lower requirements for the number of test signal channels of the test equipment).
  • the first test line 111 and the second test line 112 may extend from the bonding area 130 (eg, the lower left corner of the display substrate 100) to the middle area of the bonding opposing area 120, and the third test line 113 may be bonded
  • the area 130 (for example, the lower right corner of the display substrate 100) extends to the middle area of the bonding opposite area 120
  • the test control line 114 may extend from the bonding area 130 (for example, the lower right corner of the display substrate 100) to the bonding opposite The left side of the area 120 (for example, the upper left corner of the display substrate 100).
  • the display substrate 100 further includes control guide traces 190.
  • the test control lines 114 may also extend from the bonding area 130 (eg, the lower right corner of the display substrate 100) to the bonding opposing area The middle area of 120, in this case, the control guide wire 190 includes a seventh end 191 and an eighth end 192, and the test control wire 114 is located between the seventh end 191 and the eighth end 192 via the control guide wire 190 Is connected to the control guide trace 190.
  • the seventh end 191 and the eighth end 192 refer to the points of the control guide trace 190 connected to the two control switches located on the outermost side in the first direction D1 among the plurality of control switches 124-126, and the seventh end 191 and the eighth end 192 may or may not be physical end points that control the guide trace 190.
  • the time delay of the control signal (valid signal or invalid signal) received by different control switches can be reduced, thereby making the brightness changes of the display sub-pixels at different positions more consistent, and Improve the instantaneous brightness uniformity of the display substrate.
  • control guide wire 190 the specific design of the control guide wire 190 and the connection relationship between the test control wire 114 and the control guide wire 190 can be designed with reference to the first guide wire 121 and the first test wire 111, which will not be repeated here.
  • control guide trace 190 is located in the bonding opposing area 120 and is arranged in parallel with the first guide trace 121, the second guide trace 122, and the third guide trace 123.
  • the first position 1213 is the “resistance midpoint” of the first guide trace 121 between the first end 1211 and the second end 1212 (hereinafter referred to as the midpoint of resistance of the first guide trace 121).
  • the “resistance midpoint” refers to a point between two points on the trace that makes the resistance to the two points equal; accordingly, the “resistance 1/3 point” referred to in the following description Is the point between the two points on the trace (starting point and end point) such that the resistance to the start point is equal to 1/3 of the resistance between the start point and the end point, “resistance 2/3 point” refers to the two points on the trace (starting point And the end point) such that the resistance to the start point is equal to 2/3 of the resistance between the start point and the end point.
  • the amplitude of the voltage signal at the first end 1211 is equal to the amplitude of the voltage signal at the second end 1212, and the maximum voltage on the first guide trace 121 It decreases to the difference between the amplitude of the voltage signal at the first position 1213 and the amplitude of the voltage signal at the first end 1211 (or at the second end 1212). Therefore, the maximum voltage drop on the first guide trace 121 of the display substrate 100 shown in FIG. 5 is, for example, half of the maximum voltage drop on the first portion of the first test line 511 of the display substrate 500 shown in FIG. 1. Furthermore, the voltage drop on the first guide trace 121 of the display substrate 100 shown in FIG. 5 is, for example, symmetrically distributed with respect to the first position 1213. The following is an exemplary description with reference to FIGS. 6 and 7.
  • FIG. 6 shows a simulation curve of voltage signals of the first terminal 1211 and the second terminal 1212 on the first guide trace 121 of the display substrate 100 shown in FIG. 5 with time.
  • the horizontal axis of FIG. 6 is time, where u represents microseconds and m represents milliseconds; the vertical axis of FIG. 6 represents the amplitude of the voltage signal.
  • FIG. 7 shows the brightness distribution map 161 of the first display sub-pixel in the first direction D1, the brightness distribution map 162 of the second display sub-pixel in the first direction D1, and the third display sub-pixel in the first direction D1 163 of the luminance distribution diagram, here, the size of the luminance distribution diagram in the longitudinal direction represents the luminance of the display sub-pixel corresponding to the luminance distribution diagram.
  • the steepness of the rising edge of the voltage signal 171 at the first end 1211 of the first guide trace 121 is the same as that of the first guide trace 121
  • the steepness of the rising edge of the voltage signal 172 of the second terminal 1212 has a good matching degree (ie, substantially the same), and the amplitude of the voltage signal 171 of the first terminal 1211 of the first guide trace 121 is the same as that of the first
  • the amplitude of the voltage signal 172 at the second end 1212 of the guide trace 121 has a good match (ie, is substantially equal), which indicates that the first end 1211 of the first guide trace 121 and the first guide trace 121
  • the second terminal 1212 has a similar voltage drop and time delay, and thus the display substrate 100 shown in FIG.
  • the rise time of the rising edge of the voltage signal 171 at the first end 1211 of the first guide trace 121 is about 199 microseconds, and the voltage signal 172 at the second end 1212 of the first guide trace 121 The rise time of is about 211 microseconds, the difference between the two is only 12 microseconds; the amplitude of the voltage signal 171 at the first end 1211 of the first guide trace 121 is the same as that of the second end 1212 of the first guide trace 121 The difference in amplitude of the voltage signal 172 is only about 53 mV.
  • the signal of the second guide trace 122 and the signal of the third guide trace 123 have similar voltage drop characteristics and time delay characteristics, which will not be repeated here.
  • the amplitude of the voltage signal on the first guide trace 121 increases first and then decreases along the first direction D1 (that is, the amplitude of the voltage signal at the first position 1213 of the first guide trace 121 is the largest, and the voltage signal ) Gradually decreases from the first position 1213 to both sides of the first position 1213), the phase delay of the voltage signal on the first guide trace 121 decreases first and then increases along the first direction D1.
  • the first direction D1 the light emission luminance of the first sub-pixel increases first and then decreases (see FIG. 7).
  • the maximum voltage drop on the first guide trace 121 can be reduced, thereby reducing the value shown in FIG. 5
  • the brightness difference of the first display sub-pixel of the display substrate 100 in the first direction D1 is shown, that is, at the same time, the first display sub-pixel with the largest light-emitting luminance and the first display sub-pixel with the smallest light-emitting luminance
  • the difference between the luminous brightness decreases. This improves the brightness uniformity of the display substrate 100, and thus can reduce the missed detection caused by the uneven brightness caused by the test line design of the display substrate 100, and improve the defective detection rate of the display substrate during the test stage.
  • the third position 1223 may be the midpoint of the resistance between the third end 1221 and the fourth end 1222 of the second guide trace 122 (hereinafter referred to as the midpoint of the resistance of the second guide trace 122), the fourth position 1233 It may be the midpoint of the resistance between the fifth end 1231 and the sixth end 1232 of the third guide trace 123 (hereinafter referred to as the midpoint of the resistance of the third guide trace 123).
  • the maximum voltage drop on the second guide trace 122 and the maximum voltage drop on the third guide trace 123 of the display substrate 100 shown in FIG. 5 can be respectively the display substrate shown in FIG.
  • the maximum voltage drop on the second part of the second test line 512 of 500 and the maximum voltage drop on the third part of the third test line 513 are, for example, half, and makes the second guide trace of the display substrate 100 shown in FIG. 5
  • the voltage drop at 122 is, for example, symmetrically distributed about the third position 1223
  • the voltage drop at the third guide trace 123 is, for example, symmetrically distributed about the fourth position 1233.
  • the amplitude of the voltage signal on the second guide trace 122 and the amplitude of the voltage signal on the third guide trace 123 increase and then decrease in the first direction D1
  • the second guide trace 122 and the third guide trace The phase delay of the voltage signal on line 123 decreases first and then increases along the first direction D1.
  • the light emission luminance of the second sub-pixel and the light emission luminance of the third sub-pixel first increase and then decrease (see FIG. 7).
  • the second guide trace 122 and the third guide trace 123 can be reduced
  • the maximum voltage drop on the display thereby reducing the brightness difference of the second display sub-pixel in the first direction D1 and the brightness difference of the third display sub-pixel in the first direction D1 of the display substrate 100 shown in FIG. 5, Improving the brightness uniformity of the display substrate 100 can further reduce the missed detection caused by the uneven brightness caused by the test line design of the display substrate 100 and improve the defective detection rate of the display substrate during the test stage.
  • the first guide trace 121, the second guide trace 122, and the third guide trace 123 have uniform thickness, width, and material distribution, respectively, and the first resistance ratio, second resistance ratio, and third resistance ratio are equal to each other
  • the voltage drops on the first guide trace 121, the second guide trace 122, and the third guide trace 123 are consistent and match each other, thereby making the first display sub-pixel 1451 and the second display in the same display pixel
  • the data signals received by the sub-pixel 1452 and the third display sub-pixel 1453 match each other and cause the first display sub-pixel 1451, the second display sub-pixel 1452 and the third display sub-pixel 1453 of the same display pixel of the display substrate 100 to emit light
  • the intensity is matched (for example, white light can be mixed to form), whereby the color shift problem of the display substrate 100 can be suppressed.
  • the first position 1213 is the midpoint of the resistance between the first end 1211 and the second end 1212 of the first guide trace 121 (hereinafter referred to as the midpoint of the resistance of the first guide trace 121), and the third position 1223 Is the midpoint of the resistance between the third end 1221 and the fourth end 1222 of the second guide trace 122, and the fourth position 1233 is the resistance between the fifth end 1231 and the sixth end 1232 of the third guide trace 123
  • the midpoint of the resistance between the first end 1211 and the second end 1212 of the first guide trace 121 that is, the first position 1213
  • the midpoint of the resistance between the third end 1221 and the fourth end 1222 of the second guide trace 122 ie, the third position 1223 is the midpoint between the third end 1221 and the fourth end 1222
  • the third guide trace The midpoint of the resistance between the fifth end 1231 and the sixth end 1232 of the
  • FIG. 7 also shows a distribution diagram 160 of colors displayed by the display substrate 100 along the first direction D1, where it is assumed that the first display sub-pixel 1451, the second display sub-pixel 1452, and the third display sub-pixel 1453 respectively emit green light, Red light and blue light.
  • the first display sub-pixel 1451 and the second display sub-pixel 1452 of the same display pixel of the display substrate 100 Matches the luminous intensity of the third display sub-pixel 1453.
  • the emitted red, green, and blue light can be mixed to form white light, as shown in the distribution diagram 160 of FIG. 7. Thereby, the problem of color shift of the display substrate 100 can be suppressed.
  • the light emission brightness eg, white light brightness
  • the position corresponding to the midpoint of the resistance in 140 gradually decreases toward both sides of the display area 140 (both sides in the first direction D1).
  • the display substrate 100 shown in FIG. 5 can suppress the color shift problem of the display substrate 100, it is possible to reduce the missed detection caused by the color shift caused by the test line design of the display substrate 100, and further improve the display substrate testing stage The rate of bad detection.
  • the first position 1213 is not limited to the midpoint of the resistance between the first end 1211 and the second end 1212 of the first guide trace 121.
  • the first position 1213 may also be the first position of the first guide trace 121 At any other position between the end 1211 and the second end 1212, at this time, the corresponding display substrate 100 also has a certain technical effect of reducing the brightness difference.
  • the third position 1223 can also be any other position between the third end 1221 and the fourth end 1222 of the second guide trace 122, and the fourth position 1233 can also be the fifth end 1231 of the third guide trace 123 At any other position from the sixth end 1232, the corresponding display substrate 100 also has a certain technical effect of reducing the brightness difference.
  • the first resistance ratio, the second resistance ratio and the third resistance ratio are not limited to be set equal to each other. According to the actual application requirements, the first resistance ratio, the second resistance ratio and the third resistance ratio may also have a certain The difference is that in this case, the display substrate 100 shown in FIG. 5 has a certain degree of color shift, but the color shift of the display substrate 100 shown in FIG. 5 may still be weaker than that of the display substrate 500 shown in FIG. 1.
  • the first test pad 131, the second test pad 132, and the third test pad 133 are not limited to being disposed on both sides of the display area 140 in the first direction D1. According to actual application requirements, the first test pad 131 The second test pad 132 and the third test pad 133 may be disposed on the same side of the display area 140 in the first direction D1. In this case, by providing the first guide trace 121, the second guide trace 122, and the third guide trace 123, the brightness difference of the display substrate 100 in the first direction D1 can also be reduced, and the uniform brightness of the display substrate 100 can be improved This can reduce the missed detection caused by the uneven brightness of the display substrate, and improve the defective detection rate of the display substrate during the test stage.
  • the display substrate 100 may be an array substrate.
  • the size of the array substrate is larger than the size of the color filter substrate facing the box, and the bonding area 130 is located
  • the area where the array substrate does not overlap with the color filter substrate that is, the area where the array substrate is exposed by the color filter substrate
  • the test data signal is applied to the pad 133, and in a subsequent process, the first signal line and the second signal line may be connected to the gate driver and the data driver, respectively.
  • the first test line 111 is also electrically connected to the first guide trace 121 at the second position 1214 on the first guide trace 121, and the second position 1214 is located between the first end 1211 and the second end 1212 It is different from the first position 1213, which can further reduce the brightness difference of the first display sub-pixels along the first direction D1, improve the brightness uniformity of the display substrate 100 and the defective detection rate of the display substrate during the test stage.
  • the first position 1213 and the second position 1214 are located between the resistance 1/3 point and the resistance 2/3 point between the first end 1211 and the second end 1212 of the first guide trace 121, respectively, which can be further reduced
  • the brightness difference of the first display sub-pixels along the first direction D1 improves the brightness uniformity of the display substrate 100 and the defective detection rate of the display substrate during the test stage.
  • the first test line 111 shown in FIG. 8 will be exemplarily described below.
  • the first test line 111 includes a first portion 1111 extending in the second direction D2 and a first extension extending from the first test pad 131 to one end of the first portion 1111 and connected to one end of the first portion 1111
  • the first test line 111 further includes a first sub-trace 1113, a second sub-trace 1114, and a third sub-trace 1115.
  • the line segment surrounded by the upper dotted frame is the first sub-trace 1113
  • the line segment surrounded by the left dotted frame is the second sub-trace 1114
  • the line segment surrounded by the right dotted frame is the third sub-trace 1115.
  • the first sub-trace 1113 extends along the first direction D1 and includes a first end 11131 of the first sub-trace 1113, a second end 11133 of the first sub-trace 1113, and a first sub-trace
  • the first position of 1113 is 11132.
  • the other end of the first part 1111 is connected to the first sub-trace 1113 via the first position 11132 of the first sub-trace 1113; one end of the second sub-trace 1114 is connected to the first end 11131 of the first sub-trace 1113.
  • the other end of the second sub-trace 1114 is connected to the first position 1213 of the first guide trace 121; one end of the third sub-trace 1115 is connected to the second end 11133 of the first sub-trace 1113, and the third sub-trace 1115 The other end of is connected to the second position 1214 of the first guide trace 121.
  • the first position 11132 of the first sub-trace 1113 is the midpoint of the resistance of the first sub-trace 1113 between the first end 11131 of the first sub-trace 1113 and the second end 11133 of the first sub-trace 1113 ,
  • the amplitudes of the voltage signals at the first end 11131 of the first sub-trace 1113 and the second end 11133 of the first sub-trace 1113 are equal; the resistance values of the second sub-trace 1114 and the third sub-trace 1115
  • the amplitude of the voltage signal at the first position 1213 of the first guide trace 121 is equal to the amplitude of the voltage signal at the second position 1214 of the first guide trace 121
  • the first The maximum voltage drop on the guide trace 121 is, for example, one-third of the maximum voltage drop on the first portion of the first test line 511 of the display substrate 500 shown in FIG. 1.
  • the first sub-trace 1113 may be electrically connected to the first guide trace 121 through more (
  • the amplitude and the voltage signal on the first guide trace 121 can be further reduced.
  • the difference in phase delay, and therefore, the brightness difference of the display substrate 100 along the first direction D1 can be further reduced, and the brightness uniformity of the display substrate 100 can be improved, thereby further reducing the missed detection caused by the uneven brightness of the display substrate 100.
  • the first test wire 111 may also be electrically connected to the first guide wire 121 at more positions on the first guide wire 121, for example, to the first end of the first guide wire 121
  • the resistance 1/5 points, resistance 2/5 points, resistance 3/5 points and resistance 4/5 points between 1211 and the second end 1212 are electrically connected, thereby the brightness uniformity of the display substrate 100 can be further improved, and The defective detection rate of the display board during the test stage is not repeated here.
  • the second test line 112 and the second guide trace 122 and the third test line 113 and the third guide trace 123 in the display substrate 100 shown in FIG. 5 may also be similar to those shown in FIG. 8
  • the difference in amplitude and phase delay of the voltage signal on the second guide trace 122 and the third guide trace 123 can be further reduced, and thus the difference in brightness of the display substrate 100 along the first direction D1 can be further reduced To improve the defective detection rate of the display board during the test stage.
  • the above embodiment mainly illustrates that the difference in the amplitude of the voltage signal on the guide traces of the display substrate 100 (for example, the first guide trace 121) is reduced to enhance the uniformity of the brightness of the display substrate 100. And the effect of suppressing color shift, however, the reduction of the time delay difference of the voltage signals on the guide traces also has a certain effect on improving the brightness uniformity of the display substrate 100 and suppressing color shift, which will not be repeated here.
  • At least one embodiment of the present disclosure also provides a display device including the display substrate 1 provided by any embodiment of the present disclosure.
  • FIG. 9 shows a display device 10 provided by some embodiments of the present disclosure.
  • the display device 10 includes the display substrate 100 and the main control circuit 200 provided by any embodiment of the present disclosure.
  • the display substrate 100 is electrically connected to the main control circuit 200.
  • the display substrate 100 realizes a display function.
  • the main control circuit 200 is a central processing unit.
  • the display device 10 may be a product or component having a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital camera, a navigator, and the like.
  • Some embodiments of the present disclosure further provide a test method for the above display substrate, which includes: applying a first signal to a plurality of first signal lines of a first group via a first test line and a first guide trace, and based on Check the display of the display board.
  • test method for a display substrate provided by at least one embodiment of the present disclosure will be exemplarily described below.
  • test method of the display substrate includes at least one step from step S101 to step S103.
  • Step S101 Apply a first signal to a plurality of first signal lines of the first group via the first test line and the first guide trace, and perform detection based on the display condition of the display substrate.
  • Step S102 Apply a second signal to a plurality of second group of first signal lines via a second test line and a second guide trace, and perform detection based on the display condition of the display substrate.
  • Step S103 Apply a third signal to the plurality of third signal lines of the third group via the third test line and the third guide trace, and perform detection based on the display condition of the display substrate.
  • a first signal (that is, a test data signal) may be applied to the first test pad, and a valid signal (eg, a level signal that causes the control switch to be turned on) may be applied to the control signal pad, so that the A test data signal applied on a test pad can be transmitted to a plurality of first signal lines of the first group, and a gate scan signal is applied to the scan signal pad so as to be transmitted to the first of the plurality of first signal lines of the first group
  • the signal can drive the corresponding first display sub-pixel to emit light. Then, detection may be performed based on the light emission of the first display sub-pixel.
  • MURA uneven brightness
  • step S102 and step S103 are similar to step S101, and will not be repeated here.
  • steps S101-S103 may be performed as required; when performing multiple steps in steps S101-step S103, the multiple steps may be performed sequentially or simultaneously Execution, the following is an exemplary description by simultaneously performing steps S101-step S103.
  • the first signal, the second signal, and the third signal can be applied to the first test pad, the second test pad, and the third test pad, respectively, and the effective signal can be applied to the control signal pad.
  • Level signal that causes the control switch to turn on to enable the control switch to turn on and enable the first, second, and third signals applied to the first, second, and third test pads to be transmitted to
  • a gate scanning signal is applied to the scanning signal pad, so that the signal transmitted to the corresponding signal line can drive the corresponding display sub-pixel to emit light.
  • the display substrate provided by some embodiments of the present disclosure can reduce the brightness difference and/or color shift caused by the test leads of the display substrate, it can reduce the missed detection caused by the test leads of the display substrate and improve the defects of the display substrate during the test stage The detection rate.

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Abstract

一种显示基板、显示装置和显示基板的测试方法。显示基板（100）包括显示区域（140）以及设置在显示区域（140）外的周边区域。周边区域中设置有沿第一方向（D1）延伸的第一引导走线（121），第一引导走线（121）包括第一端（1211）和第二端（1212）；周边区域中还设置有第一测试线（111），第一测试线（111）在第一引导走线（121）上的第一位置（1213）与第一引导走线（121）电连接，第一位置（1213）位于第一端（1211）和第二端（1212）之间；显示区域（140）包括沿不同于第一方向（D1）的第二方向（D2）延伸且平行设置的多条第一组第一信号线（141），多条第一组第一信号线（141）中沿第一方向（D1）排在最外侧的两条第一信号线分别与第一端（1211）和第二端（1212）连接，多条第一组第一信号线（141）中其余的第一信号线在第一端（1211）和第二端（1212）之间与第一引导走线（121）连接。

Description

显示基板、显示装置和显示基板的测试方法
本申请要求于2018年12月25日递交的第201811591919.7号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板、显示装置和显示基板的测试方法。
背景技术
为了提升显示装置的良率，降低显示装置的生产成本，在显示装置制作的多个关键工艺环节设置了不良检测工序和修复工序。下面以液晶显示装置为例进行阐述。液晶显示装置的制作工序包括阵列基板制作工序、对置基板制作工序、液晶盒制作工序以及液晶模组制作工序。例如，为提升液晶模组制作工序阶段的良率，降低液晶模组制作工序阶段的生产成本，在从母板(Q panel)上切割获取液晶盒后(也即，液晶盒制作工序完成之后)，会对液晶盒进行检测(例如，不良检测)，以尽可能的避免存在不良的液晶盒进入后续的液晶模组制作工序中。并且，提升液晶盒检测(Cell Test)阶段的不良检出率对液晶模组制作工序阶段的生产成本和制作良率有较大的影响。
发明内容
本公开的至少一个实施例提供一种显示基板。该显示基板包括显示区域以及设置在所述显示区域外的周边区域。所述周边区域中设置有沿第一方向延伸的第一引导走线，所述第一引导走线包括第一端和第二端；所述周边区域中还设置有第一测试线，所述第一测试线在所述第一引导走线上的第一位置与所述第一引导走线电连接，所述第一位置位于所述第一端和所述第二端之间；以及所述显示区域包括沿不同于所述第一方向的第二方向延伸且平行设置的多条第一组第一信号线，所述多条第一组第一信号线中沿所述第一方向排在最外侧的两条第一信号线分别与所述第一端和所述第二端连接，所述 多条第一组第一信号线中其余的第一信号线在所述第一端和所述第二端之间与所述第一引导走线连接。
例如，所述第一位置为所述第一引导走线的第一端和第二端之间的电阻中点。
例如，所述第一测试线还在所述第一引导走线上的第二位置与所述第一引导走线电连接，所述第二位置位于所述第一端和所述第二端之间且与所述第一位置不同。
例如，所述第一位置和所述第二位置分别位于所述第一引导走线的第一端和第二端之间的电阻1/3点和电阻2/3点。
例如，所述显示区域还包括沿所述第一方向延伸且平行设置的多条第二信号线；所述多条第二信号线与所述第一组第一信号线交叉且绝缘；并且所述第一引导走线和所述多条第二信号线同层设置。
例如，所述第一测试线包括沿所述第二方向延伸的第一部分以及除所述第一部分之外的第一延伸部分，所述第一部分的一端与所述第一引导走线电连接，且所述第一部分的另一端与所述第一延伸部分电连接；所述第一部分和所述多条第一组第一信号线同层设置；并且所述第一延伸部分、所述第一引导走线和所述多条第二信号线同层设置。
例如，所述周边区域包括邦定区和邦定对置区；所述邦定区和所述邦定对置区沿所述第二方向分别位于所述显示区域的两侧；并且所述第一引导走线设置在所述邦定对置区中。
例如，所述邦定区包括第一测试垫，所述第一测试线的一端与所述第一测试垫电连接且所述第一测试线的另一端在所述第一位置处与所述第一引导走线电连接。
例如，所述邦定区包括多个第一组第一信号垫，所述多条第一信号线与所述多个第一组第一信号垫一一对应连接。
例如，所述周边区域还设置有测试控制线；所述邦定对置区还包括多个第一组控制开关，所述多个第一组控制开关的第一端与所述多条第一组第一信号线一一对应电连接，所述多个第一组控制开关的第二端与所述第一引导走线电连接，所述多个第一组控制开关的控制端与所述测试控制线电连接。
例如，所述邦定对置区还设置有第二引导走线，所述第二引导走线沿所 述第一方向延伸且包括第三端和第四端；所述周边区域中还设置有第二测试线，所述第二测试线在所述第二引导走线上的第三位置与所述第二引导走线电连接，所述第三位置位于所述第三端和所述第四端之间；以及所述显示区域还包括沿所述第二方向延伸且平行设置的多条第二组第一信号线，所述多条第二组第一信号线中沿所述第一方向排在最外侧的两条第一信号线分别与所述第三端和所述第四端连接，所述多条第二组第一信号线中其余的第一信号线在所述第三端和所述第四端之间与所述第二引导走线连接；以及所述邦定区还包括第二测试垫，所述第二测试线的一端与所述第二测试垫电连接，且所述第二测试线的另一端在所述第三位置处与所述第二引导走线电连接。
例如，所述邦定对置区还设置有第三引导走线，所述第三引导走线沿所述第一方向延伸且包括第五端和第六端；所述周边区域还设置有第三测试线，所述第三测试线在所述第三引导走线上的第四位置与所述第三引导走线电连接，所述第四位置位于所述第五端和所述第六端之间；所述显示区域还包括沿所述第二方向延伸且平行的多条第三组第一信号线，所述多条第三组第一信号线中沿所述第一方向排在最外侧的两条第一信号线分别与所述第五端和所述第六端连接，所述多条第三组第一信号线中其余的第一信号线在所述第五端和所述第六端之间与所述第三引导走线连接；以及所述邦定区还包括第三测试垫，所述第三测试线的一端与所述第三测试垫电连接，且所述第三测试线的另一端在所述第四位置与所述第三引导走线电连接。
例如，所述邦定对置区中设置有沿所述第一方向延伸的控制引导走线，所述控制引导走线包括第七端和第八端；所述测试控制线在所述控制引导走线上位于所述第七端和所述第八端之间的连接点处与所述控制引导走线连接；所述多个第一组控制开关中沿所述第一方向排在最外侧的两个控制开关分别与所述第七端和所述第八端连接，所述多个第一组控制开关中其余的控制开关在所述第七端和所述第八端之间与所述控制引导走线连接。
例如，所述邦定对置区还包括多个第二组控制开关，所述多个第二组控制开关的第一端与所述多条第二组第一信号线一一对应电连接，所述多个第二组控制开关的第二端与所述第二引导走线电连接，所述多个第二组控制开关的控制端与所述测试控制线电连接；并且所述邦定对置区还包括多个第三组控制开关，所述多个第三组控制开关的第一端与所述多条第三组第一信号 线一一对应电连接，所述多个第三组控制开关的第二端与所述第三引导走线电连接，所述多个第三组控制开关的控制端与所述测试控制线电连接。
例如，所述邦定区还设置与所述测试控制线电连接的控制信号垫；所述第一测试垫和所述第二测试垫在所述第一方向上位于所述显示区域的一侧，所述第三测试垫和所述控制信号垫在所述第一方向上位于所述显示区域的另一侧。
例如，第一电阻比值、第二电阻比值和第三电阻比值彼此相等；所述第一电阻比值为所述第一引导走线的所述第一端与所述第一位置之间的电阻值与所述第一引导走线的所述第一位置与所述第二端之间的电阻值的比值；所述第二电阻比值为所述第二引导走线的所述第三端与所述第三位置之间的电阻值与所述第二引导走线的所述第三位置与所述第四端之间的电阻值的比值；以及所述第三电阻比值为所述第三引导走线的所述第五端与所述第四位置之间的电阻值与所述第三引导走线的所述第四位置与所述第六端之间的电阻值的比值。
例如，所述第一位置为所述第一引导走线的所述第一端和所述第二端之间的电阻中点；所述第三位置为所述第二引导走线的所述第三端和所述第四端之间的电阻中点；以及所述第四位置为所述第三引导走线的所述第五端和所述第六端之间的电阻中点。
例如，所述多条第一组第一信号线、所述多条第二组第一信号线和所述多条第三组第一信号线分别用于传输显示不同颜色的光的子像素的数据信号。
例如，所述第一测试线、所述第二测试线和所述第三测试线的电阻彼此相等。
本公开的至少一个实施例提供一种显示装置，该显示装置包括如上所述的显示基板以及与该显示基板电连接的主控电路。
本公开的至少一个实施例提供一种如上所述的显示基板的测试方法，该方法包括：经由所述第一测试线和所述第一引导走线向所述多条第一组第一信号线施加第一信号，并基于所述显示基板的显示情况进行检测。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是根据一种技术的显示基板的平面示意图；
图2A是图1所示的显示基板的第二测试线上第一位置和第三位置的电压信号的测试时序图；
图2B是图2A所示的局部区域的电压信号的放大图；
图3是图1所示的显示基板的第二测试线上第一位置和第三位置的电压信号的仿真时序图；
图4是图1所示的显示基板的第一显示子像素、第二显示子像素以及第三显示子像素的亮度分布图以及图1所示的显示基板的显示像素的颜色分布图；
图5是本公开的一些实施例提供的显示基板的平面示意图；
图6是图5所示的显示基板的第一引导走线上的第一端和第二端的电压信号随时间变化的曲线；
图7是图5所示的显示基板的第一显示子像素、第二显示子像素以及第三显示子像素的亮度分布图以及图5所示的显示基板的显示像素颜色和亮度分布图；
图8是本公开的一些实施例提供的另一种第一测试线和第一引导走线的结构；
图9是本公开的一些实施例提供的显示装置的示例性框图；
图10是本公开的一些实施例提供的另一种显示基板的平面示意图；
图11为图5所示的显示基板的截面图；以及
图12为图5所示的显示基板的另一截面图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开的发明人注意到，当前的显示基板的测试走线设计为使得，在测试(例如，不良检测)中，显示基板存在因测试走线(例如，测试走线的电阻和寄生电容)导致的亮度不均匀问题和/或色偏问题。因此，显示基板中存在的与亮度和/或色偏相关的不良容易被显示基板的测试走线设计导致亮度差异和/或色偏所掩盖，或者检测人员和/或检测装置(例如，光学自动检测装置)倾向于忽略显示子像素存在的与亮度和/或色偏相关的不良。这降低了显示基板测试的不良检出率(也即，增加了不良漏检率)，增加了后续工序中的资源浪费，并因此增加了显示基板以及包括该显示基板的显示装置的制作成本。
下面结合图1示出的显示基板做示例性说明。
图1示出了一种显示基板500的平面示意图，该显示基板500可以为液晶显示基板(例如，液晶显示面板的阵列基板)或者自发光显示基板(例如，有机发光二级管显示面板的阵列基板)。
如图1所示，该显示基板500包括显示区域540以及设置在显示区域540外(例如，显示区域540的四周)的周边区域。周边区域包括邦定区530和与邦定区530相对设置的邦定对置区520，且邦定区530和邦定对置区520沿不同于第一方向D1的第二方向D2分别位于显示区域540相对的两侧(例如，分别位于图1中的下侧和上侧)，邦定区530沿第一方向D1延伸，邦定对置区520沿第一方向D1延伸。
如图1所示，显示区域540包括沿第二方向D2延伸且平行设置的多条 第一组第一信号线541，沿第二方向D2延伸且平行设置的多条第二组第一信号线542以及沿第二方向D2延伸且平行设置的多条第三组第一信号线543。多条第一组第一信号线541、多条第二组第一信号线542和多条第三组第一信号线543分别用于传输显示不同颜色的光的子像素的数据信号。
例如，第一信号线为数据线。例如，多条第一组第一信号线541用于传输显示绿光的子像素的数据信号，多条第二组第一信号线542用于传输显示红光的子像素的数据信号，多条第三组第一信号线543用于传输显示蓝光的子像素的数据信号。
如图1所示，显示区域540还包括沿第一方向D1延伸且平行设置的多条第二信号线544，多条第二信号线544与多条第一信号线(也即，多条第一组第一信号线541、多条第二组第一信号线542以及多条第三组第一信号线543)交叉且绝缘，由此界定了阵列排布的多个显示子像素。例如，第二信号线544为栅线，第二信号线544用于传输扫描信号。
例如，显示区域540包括阵列排布的多个显示像素(图1中未示出)，每个显示像素包括第一显示子像素、第二显示子像素和第三显示子像素，第一显示子像素、第二显示子像素和第三显示子像素分别与第一组第一信号线541、第二组第一信号线542和第三组第一信号线543电连接，以基于第一组第一信号线541、第二组第一信号线542和第三组第一信号线543提供的数据信号发光。例如，第一显示子像素、第二显示子像素和第三显示子像素分别用于发射绿光、红光和蓝光。
如图1所示，邦定区530包括多个第一组第一信号垫535、多个第二组第一信号垫536以及多个第三组第一信号垫537；多条第一组第一信号线541与多个第一组第一信号垫535一一对应连接；多条第二组第一信号线542与多个第二组第一信号垫536一一对应连接；多条第三组第一信号线543与多个第三组第一信号垫537一一对应连接。例如，上述多个第一组第一信号垫535、多个第二组第一信号垫536以及多个第三组第一信号垫537用于在后续工序中通过例如柔性电路板与数据驱动器连接，以从数据驱动器接收多个数据信号，并将多个数据信号提供给对应的第一信号线。
如图1所示，邦定区530还包括多个第二信号垫538，多条第二信号线544与多个第二信号垫538一一对应连接。例如，上述多个第二信号垫538 用于在后续工序中通过例如柔性电路板与栅极驱动器连接，以从栅极驱动器接收多个扫描信号，并将多个扫描信号提供给对应的第二信号线544。
如图1所示，邦定区530还包括第一测试垫531、第二测试垫532、第三测试垫533和控制信号垫534。
如图1所示，周边区域设置有第一测试线511、第二测试线512、第三测试线513和测试控制线514，第一测试线511与第一测试垫531连接并包括在邦定对置区520沿第一方向D1延伸的第一部分，第二测试线512与第二测试垫532连接并包括在邦定对置区520沿第一方向D1延伸的第二部分，第三测试线513与第三测试垫533连接并包括在邦定对置区520沿第一方向D1延伸的第三部分，测试控制线514与控制信号垫534连接并包括在邦定对置区520沿第一方向D1延伸的第四部分。
例如，邦定区530还包括扫描测试垫(图中未示出)，周边区域还设置有扫描测试线(图中未示出)，扫描测试线的两端分别与扫描测试垫和第二数据线电连接。
如图1所示，邦定对置区520还包括多个第一组控制开关524、多个第二组控制开关525以及多个第三组控制开关526。
如图1所示，多个第一组控制开关524的第一端与多条第一组第一信号线541一一对应电连接，多个第一组控制开关524的第二端与第一测试线511的第一部分电连接；多个第一组控制开关524的第三端(控制端)与测试控制线514的第四部分电连接，以基于施加在控制信号垫534的控制信号控制多个第一组控制开关524的开启和关闭，由此控制是否将施加在第一测试垫531上的第一测试数据信号经由第一测试线511的第一部分施加到多条第一组第一信号线541上。
如图1所示，多个第二组控制开关525的第一端与多条第二组第一信号线542一一对应电连接，多个第二组控制开关525的第二端与第二测试线512的第二部分电连接；多个第二组控制开关525的第三端(控制端)与测试控制线514的第四部分电连接，以基于施加在控制信号垫534的控制信号控制多个第二组控制开关525的开启和关闭，由此控制是否将施加在第二测试垫532上的第二测试数据信号经由第二测试线512的第二部分施加到多条第二组第一信号线542上。
如图1所示，多个第三组控制开关526的第一端与多条第三组第一信号线543一一对应电连接，多个第三组控制开关526的第二端与第三测试线513的第三部分电连接；多个第三组控制开关526的第三端(控制端)与测试控制线514的第四部分电连接，以基于施加在控制信号垫534的控制信号控制多个第三组控制开关526的开启和关闭，由此控制是否将施加在第三测试垫533上的第三测试数据信号经由第三测试线513的第三部分施加到多条第三组第一信号线543上。
例如，在包括图1示出的显示基板500的显示装置进行正常显示时，可以向控制信号垫534施加无效信号，使得控制开关关闭，例如，当控制开关为N型晶体管时，该无效信号为低电平信号，或将控制信号垫534接地或悬空。将控制开关关闭可以避免第一测试线511、第二测试线512和第三测试线513对显示装置产生不利影响。
例如，在对显示基板500进行测试(例如，液晶盒测试)中，可以在第一测试垫531、第二测试垫532和第三测试垫533的至少一个上施加数据信号，在控制信号垫534上施加有效信号(也就是，使得控制开关开启的电平信号)，使控制开关开启，使得在第一测试垫531、第二测试垫532和第三测试垫533的至少一个上施加的数据信号能够传输到对应的信号线(数据线)上。同时，在扫描信号垫施加栅极扫描信号，使得传输到对应的信号线(数据线)上的数据信号能够写入显示子像素中以驱动对应的显示子像素发光。
例如，如图1所示，第一测试垫531和第二测试垫532在第一方向D1上位于显示区域540的一侧，第三测试垫533和控制信号垫534在第一方向D1上位于显示区域540的另一侧。例如，如图1所示，第一测试线511和第二测试线512由显示基板500的左下角延伸至显示基板500的右上角，第三测试线513和测试控制线514由显示基板500的右下角延伸至显示基板500的左上角。
本公开的发明人注意到，将第一测试垫531、第二测试垫532和第三测试垫533在第一方向D1上分别设置在显示区域540的两侧，可以满足特定显示基板(例如，集成栅极驱动器的显示基板)的布线要求(例如，布线空间小)，还可以增加测试设备选择范围(例如，对测试设备的测试信号通道数量的要求降低)。
然而，本公开的发明人在研究中注意到，对于同一测试线(例如，第一测试线511、第二测试线512或第三测试线513)，由于测试线存在例如电阻和寄生电容，在电流流经测试线之后，测试线的不同位置处的信号的相位延迟以及信号幅值(或者电压降)存在差异，由此导致在同一时刻显示区域540在不同位置存在亮度差异，也即，在显示基板的测试时，显示区域540存在亮度不均匀问题。例如，在测试垫上施加的测试数据信号发生改变时，测试线的不同位置处的信号的相位延迟不同使得显示区域540不同位置处的显示子像素的亮度变化不一致，例如，使得显示区域540部分位置处的显示子像素的亮度提前达到或延后达到最大亮度或最小亮度。例如，测试线的不同位置处的信号的电压降不同使得显示区域540不同位置处的显示子像素的亮度(处于亮度稳定状态下的亮度)不一致。
此外，对于图1示出的显示基板，在向多条测试线同时施加测试数据信号的情况下，由于不同测试线的电压降(IR drop)的梯度方向存在差异，例如，第一测试线511和第二测试线512上的电压降从左至右逐渐增加，而第三测试线513上的电压降从左至右逐渐降低。因此，显示基板500的同一显示像素的第一显示子像素、第二显示子像素和第三显示子像素的发光强度不匹配，例如，它们分别被施加值为255的数据信号(取值范围为0～255)时，所发出的红光、绿光和蓝光不能混合形成希望的白光，由此使得显示基板500的至少部分显示区域540存在色偏。
下面结合图1、图2A、图2B、图3以及图4进行示例性说明。
如图1所示，第一测试线511的第一部分包括在第一方向D1上顺次排布的第一测试线511的第一位置5111、第一测试线511的第二位置5112和第一测试线511的第三位置5113。第二测试线512的第二部分包括在第一方向D1上顺次排布的第二测试线512的第一位置5121、第二测试线512的第二位置5122和第二测试线512的第三位置5123。第三测试线513的第三部分包括在第一方向D1上顺次排布的第三测试线513的第一位置5131、第三测试线513的第二位置5132和第三测试线513的第三位置5133。
图2A示出了从第二测试线512的第一位置5121取出的电压信号551以及从第二测试线512的第三位置5123取出的电压信号552的时序图(图2A中横向方向为时间，纵向方向为电压)。图2B示出了图2A所示的局部区域 (图2A中的虚线框区域)的电压信号(也即，电压信号的上升沿)的放大图。
如图2A所示，从第二测试线512的第一位置5121取出的电压信号551的幅值略大于从第二测试线512的第三位置5123取出的电压信号552的幅值，这表明相比于第二测试线512的第一位置5121，第二测试线512的第三位置5123处的电压降较大；如图2B所示，从第二测试线512的第一位置5121取出的电压信号551的上升沿的陡峭程度大于从第二测试线512的第三位置5123取出的电压信号552的上升沿的陡峭程度，这表明相比于从第二测试线512的第一位置5121取出的电压信号，从第二测试线512的第三位置5123取出的电压信号的时间延迟较大。
为了更清楚地显示出第二测试线512的第一位置5121和第二测试线512的第三位置5123的电压降和时间延迟的区别，本公开的发明人对从第二测试线512的第一位置5121取出的电压信号以及从第二测试线512的第三位置5123取出的电压信号随时间的变化特性进行了仿真，仿真结果如图3所示。图3的横轴为时间，这里，u表示微秒，m表示毫秒。
如图3所示，在向第二测试垫532施加方波脉冲570的情况下，从第二测试线512的第一位置5121取出的电压信号571的上升沿的陡峭程度大于从第二测试线512的第三位置5123取出的电压信号572的上升沿的陡峭程度，并且从第二测试线512的第一位置5121取出的电压信号571的幅值大于从第二测试线512的第三位置5123取出的电压信号572的幅值，这表明相比于第二测试线512的第一位置5121，第二测试线512的第三位置5123处的电压降以及时间延迟均较大。例如，如图3所示，从第二测试线512的第一位置5121取出的电压信号的上升时间约为162微秒，从第二测试线512的第三位置5123取出的电压信号的上升时间约为224微秒，从第二测试线512的第一位置5121取出的电压信号571的幅值与从第二测试线512的第三位置5123取出的电压信号572的幅值之差约为213毫伏。例如，从第一测试线511取出的信号以及从第三测试线513取出的信号具有类似的电压降特性以及时间延迟特性，在此不再赘述。
类似地，由于测试线的电阻的影响，第一测试线511的第一位置5111、第一测试线511的第二位置5112和第一测试线511的第三位置5113的电压 降逐渐增加，因此从第一测试线511的第一位置5111取出的电压信号的幅值、从第一测试线511的第二位置5112取出的电压信号的幅值以及从第一测试线511的第三位置5113取出的电压信号的幅值逐渐降低。第三测试线513的第一位置5131、第三测试线513的第二位置5132和第三测试线513的第三位置5133的电压降逐渐降低，因此取出的电压逐渐增加。由于测试线的电容的影响，第一测试线511的第一位置5111、第一测试线511的第二位置5112和第一测试线511的第三位置5113处的电压信号的时间延迟逐渐增加；第三测试线513的第一位置5131、第三测试线513的第二位置5132和第三测试线513的第三位置5133处的电压信号的时间延迟逐渐降低。
例如，由于测试线上信号幅值的不均匀分布(例如，逐渐降低)，在显示基板500的测试中，显示子像素的发光亮度沿第一方向D1不均匀分布(例如，逐渐降低)。下面结合图4进行示例性说明。
图4示出了第一显示子像素在第一方向D1上的亮度分布图561、第二显示子像素在第一方向D1上的亮度分布图562以及第三显示子像素在第一方向D1上的亮度分布图563，这里，亮度分布图在纵向方向的尺寸表示该亮度分布图对应的显示子像素的亮度。
需要说明的是，图4示出的亮度分布图是基于以下理想情况获得的，也即，在多个显示子像素(例如，第一显示子像素)接收预定的数据信号(例如，接收的数据信号彼此相等)的情况下，在第一方向D1上分布的多个显示子像素(例如，第一显示子像素)具有相同的亮度。
如图4所示，被从第一测试线511的第一位置5111取出的测试数据信号驱动的第一显示子像素(也即，对应于第一位置的第一显示子像素)的亮度，被从第一测试线511的第二位置5112取出的测试数据信号驱动的第一显示子像素(也即，对应于第二位置的第一显示子像素)的亮度，以及被从第一测试线511的第三位置5113取出的测试数据信号驱动的第一显示子像素(也即，对应于第三位置的第一显示子像素)的亮度，逐渐降低。被从第二测试线512的第一位置5121取出的测试数据信号驱动的第二显示子像素的亮度，被从第二测试线512的第二位置5122取出的测试数据信号驱动的第二显示子像素的亮度，以及被从第二测试线512的第三位置5123取出的测试数据信号驱动的第二显示子像素的亮度，逐渐降低。被从第三测试线513的第一位置5131 取出的测试数据信号驱动的第三显示子像素的亮度，被从第三测试线513的第二位置5132取出的测试数据信号驱动的第三显示子像素的亮度，以及被从第三测试线513的第三位置5133取出的测试数据信号驱动的第三显示子像素的亮度，逐渐增加。
例如，在显示基板500的测试中，从显示区域540的左侧到显示区域540的右侧，第一显示子像素和第二显示子像素的亮度逐渐降低，第三显示子像素的亮度逐渐增加。因此，图1示出的显示基板500的测试线的设计导致了图1示出的显示基板500在测试中存在亮度不均匀问题。
图4还示出了显示基板500显示的颜色沿第一方向D1的分布图564，这里假设了第一显示子像素、第二显示子像素和第三显示子像素分别发射绿光、红光和蓝光。
如图4所示，由于显示基板500对应于第一位置的显示像素发射的红光和绿光的亮度大于蓝光的亮度，对应于第一位置的显示像素发射的光线(也即，混合后的光线)的颜色偏黄。如图4所示，由于显示基板500对应于第三位置的显示像素发射的红光和绿光的亮度小于蓝光的亮度，对应于第三位置的显示像素发射的光线的颜色偏蓝。因此，图1示出的显示基板500的测试线的设计导致了图1示出的显示基板500在测试中存在色偏问题。
例如，图1示出的显示基板500在测试中(例如，不良检测)由于测试走线设计而存在亮度不均匀问题和/或色偏问题，由此可能导致显示基板500中由于其他原因存在的与亮度相关的不良被显示基板500的测试走线设计导致的亮度差异和/或色偏所掩盖，或者使得检测人员和/或检测装置(例如，光学自动检测装置)倾向于忽略显示基板500存在的与亮度和/或色偏相关的不良。这降低了显示基板500的测试中的不良检出率(也即，增加了不良漏检率)，并增加了后续工序中的资源浪费，增加了该显示基板500以及包括该显示基板500的显示装置的制作成本。例如，在测试数据信号的幅值较弱时，显示基板500在测试中(例如，不良检测)存在的亮度不均匀问题和/或色偏问题将更为明显。
本公开的至少一个实施例提供了一种显示基板、显示装置和显示基板的测试方法。该显示基板包括显示区域以及设置在显示区域外的周边区域。周边区域中设置有沿第一方向延伸的第一引导走线，第一引导走线包括第一端 和第二端；周边区域中还设置有第一测试线，第一测试线在第一引导走线上的第一位置与第一引导走线电连接，第一位置位于第一端和第二端之间；显示区域包括沿不同于第一方向的第二方向延伸且平行设置的多条第一组第一信号线，多条第一组第一信号线中在第一方向上排在最外侧的两条第一信号线分别与第一端和第二端连接，多条第一组第一信号线中其余的第一信号线在第一端和第二端之间与第一引导走线连接。
在一些示例中，该显示基板可以降低显示基板在测试中的亮度差异，提升显示基板显示亮度的均匀性，由此可以降低由显示基板亮度不均匀导致的漏检，提升显示基板测试阶段的不良检出率。
在一些示例中，该显示基板还可以降低显示基板在测试中的色偏，因此可以降低由显示基板色偏导致的漏检，并可以进一步地提升显示基板测试阶段的不良检出率。
下面通过几个示例对根据本公开实施例提供的显示基板进行非限制性的说明，如下面所描述的，在不相互抵触的情况下这些具体示例中不同特征可以相互组合，从而得到新的示例，这些新的示例也都属于本公开保护的范围。
图5示出了本公开的至少一个实施例提供的显示基板100的平面示意图，该显示基板100可以为液晶显示基板(例如，液晶显示面板的阵列基板)或者自发光显示基板(例如，有机发光二级管(OLED)显示面板的阵列基板)。该显示基板通过半导体制备工艺形成，包括层叠结构。
如图5所示，该显示基板100包括显示区域140以及设置在显示区域140外的周边区域；周边区域中设置有沿第一方向D1延伸的第一引导走线121，第一引导走线121包括第一端1211和第二端1212；周边区域中还设置有第一测试线111，第一测试线111在第一引导走线121上的第一位置1213与第一引导走线121电连接，第一位置1213位于第一端1211和第二端1212之间。
在一些示例中，通过设置沿第一方向D1延伸的第一引导走线121，并使得第一测试线111连接至第一引导走线121的第一位置1213处，可以使得第一引导走线121上的电压信号的幅值沿第一方向D1先增加后降低，也即，第一引导走线121的第一位置1213处的电压信号的幅值最大，电压信号的幅值从第一位置1213向第一位置1213的两侧逐渐降低，使得第一引导走线121上的电压信号的相位延迟沿第一方向D1先降低后增加。因此，相比于图1 示出的显示基板500中测试线上的电压信号的幅值和信号延迟沿第一方向D1单调变化的方案，图5示出的显示基板100可以降低第一引导走线121上的电压信号幅值和相位延迟的差异，并因此可以降低显示基板100沿第一方向D1的亮度差异，提升显示基板100的亮度均匀性，由此可以降低由显示基板100亮度不均匀导致的漏检，提升显示基板测试阶段的不良检出率。下面结合图5示出的显示基板100做示例性说明。
如图5所示，周边区域中还设置有第二引导走线122，第二引导走线122沿第一方向D1延伸且包括第三端1221和第四端1222；周边区域中还设置有第二测试线112，第二测试线112在第二引导走线122上的第三位置1223与第二引导走线122电连接，第三位置1223位于第三端1221和第四端1222之间。
如图5所示，周边区域中还设置有第三引导走线123，第三引导走线123沿第一方向D1延伸且包括第五端1231和第六端1232；周边区域还设置有第三测试线113，第三测试线113在第三引导走线123上的第四位置1233与第三引导走线123电连接，第四位置1233位于第五端1231和第六端1232之间。
第一端1211和第二端1212可以是，也可以不是第一引导走线121的物理端部。对于后一种情形，虽然第一引导走线121在第一端1211和第二端1212之外还可以存在延伸部分，但是由于这一部分不参与传输信号，所以不影响上述布线的技术效果。
例如，为了清楚的表示显示区域140，图5夸大了相邻的信号线之间的间距，因此使得图5示出的第一端1211和第二端1212看起来不是第一引导走线121的物理端部。例如，在一些实际产品中，位于第一端1211的远离第二端1212的一侧的延伸部分(例如，几百微米)相比于第一引导走线121的长度(例如，几百毫米)可以忽略不计，因此，在一些实际产品中，第一端1211和第二端1212可以作为第一引导走线121的物理端部。例如，在一些实际产品中，第三端1221和第四端1222可以也作为第二引导走线122的物理端部，第五端1231和第六端1232也可以作为第三引导走线123的物理端部。
在另一些示例中，第一端1211和第二端1212还可以不是第一引导走线121的物理端部，第三端1221和第四端1222还可以不是第二引导走线122 的物理端部，第五端1231和第六端1232还可以不是第三引导走线123的物理端部，为清楚起见，该示例将在后面进行详细阐述，在此不再赘述。
例如，第一引导走线121、第二引导走线122和第三引导走线123同层设置，此种情况下，可以采用同一图案化工艺对同一膜层图案化获得第一引导走线121、第二引导走线122和第三引导走线123，由此可以简化显示基板100的制作工艺。例如，同层设置可以是位于同一水平面内，也可以是不位于同一水平面内。例如，第一引导走线121、第二引导走线122和第三引导走线123同层设置是指在垂直于显示基板的方向上，第一引导走线121与第二引导走线122之间不具有其他层，第一引导走线121和第三引导走线123之间不具有其他层，且在第二引导走线122和第三引导走线123之间不具有其他层。例如，本公开的一些实施例中的其它同层设置也可以具有类似的定义，之后不再赘述。
在一些示例中，第一引导走线121、第二引导走线122和第三引导走线123还可以分别位于至少两个结构层中。例如，第一引导走线121、第二引导走线122位于同一结构层中，第三引导走线123位于另一个结构层中。在一些示例中，，第一引导走线121、第二引导走线122和第三引导走线123还可以分别位于不同结构层中，此时，第一引导走线121位于第一结构层中，第二引导走线122位于第二结构层中，且第三引导走线123位于第三结构层中。
如图5所示，第一测试线111包括沿第二方向D2延伸的第一部分1111，以及包括从第一测试垫131延伸至第一部分1111的一端并与该第一部分1111的一端连接的第一延伸部分1112。第二测试线112包括沿第二方向D2延伸的第二部分1121，以及包括从第二测试垫132延伸至第二部分1121的一端并与该第二部分1121的一端连接的第二延伸部分1122。第三测试线113包括沿第二方向D2延伸的第三部分1131，以及包括从第三测试垫133延伸至第三部分1131的一端并与该第三部分1131的一端连接的第三延伸部分1132。
例如，如图5所示，第一部分1111、第二部分1121和第三部分1131同层且彼此平行设置，例如，第二部分1121和第三部分1131在第一方向D1上设置在第一部分1111两侧。需要说明的是，第二部分1121与第一部分1111 在第一方向D1上的间距以及第三部分1131与第一部分1111在第一方向D1上的间距(例如，约为几微米-几十微米)相比于引导走线(第一引导走线121、第二引导走线122和第三引导走线123)在第一方向D1上的长度(例如，约为几百毫米)可以忽略不计。例如，第二部分1121与第一部分1111在第一方向D1上的间距等于第三部分1131与第一部分1111在第一方向D1上的间距。
此种情况下，如果第一引导走线121、第二引导走线122以及第三引导走线123具有相同的长度、相同的宽度分布(例如，相同的宽度)以及相同的厚度分布(例如，相同的厚度)，可以认为第一引导走线121的第一端1211与第一位置1213之间的电阻值与第一引导走线121的第一位置1213与第二端1212之间的电阻值的比值(也即，第一电阻比值)，第二引导走线122的第三端1221与第三位置1223之间的电阻值与第二引导走线122的第三位置1223与第四端1222之间的电阻值的比值(也即，第二电阻比值)，以及第三引导走线123的第五端1231与第四位置1233之间的电阻值与第三引导走线123的第四位置1233与第六端1232之间的电阻值的比值(也即，第三电阻比值)彼此相等。
例如，如图5所示，第一测试线111的第一延伸部分1112包括彼此相接的第一横向延伸部分和第一纵向延伸部分，第二测试线112的第二延伸部分1122包括彼此相接的第二横向延伸部分和第二纵向延伸部分，第三测试线113第三延伸部分1132包括彼此相接的第三横向延伸部分和第三纵向延伸部分。例如，如图5所示，第一横向延伸部分、第二横向延伸部分和第三横向延伸部分分别沿第一方向D1延伸，第一纵向延伸部分、第二纵向延伸部分和第三纵向延伸部分分别沿第二方向D2延伸。需要说明的是，第一延伸部分1112、第二延伸部分1122和第三延伸部分1132的结构不限于图5示出的结构，在此不再赘述。例如，第一延伸部分1112、第二延伸部分1122和第三延伸部分1132同层设置。
例如，第一测试线111、第二测试线112和第三测试线113彼此电绝缘。例如，第一测试线111、第二测试线112和第三测试线113均使用金属(例如，铝或铝合金、铜或铜合金等)制成，以降低第一测试线111、第二测试线112和第三测试线113的电阻以及第一测试线111、第二测试线112和第 三测试线113引起的电压降。
如图5所示，周边区域包括邦定区130以及与该邦定区相对设置的邦定对置区120，邦定区130和邦定对置区120沿不同于第一方向D1的第二方向D2分别位于显示区域140相对的两侧，邦定区130以及邦定对置区120沿第一方向D1延伸。例如，第一方向D1和第二方向D2彼此垂直。
如图5所示，第一引导走线121、第二引导走线122和第三引导走线123设置在邦定对置区120中。以下以第一引导走线121、第二引导走线122和第三引导走线123设置在邦定对置区120为例对本公开的实施例进行示例性描述，但本公开的实施例不限于此。
如图5所示，显示区域140包括沿第二方向D2延伸且平行设置的多条第一组第一信号线141，沿第二方向D2延伸且平行设置的多条第二组第一信号线142以及沿第三方向延伸且平行设置的多条第三组第一信号线143。
如图5所示，多条第一组第一信号线141中沿第一方向D1排在最外侧的两条第一信号线分别与第一端1211和第二端1212连接，多条第一组第一信号线141中其余的第一信号线在第一端1211和第二端1212之间与第一引导走线121连接。此种情况下，第一端1211和第二端1212是指第一引导走线121的与多条第一组第一信号线141中沿第一方向D1排在最外侧的两条第一信号线连接的点，第一端1211和第二端1212可以是第一引导走线121的物理端部，也可以不是第一引导走线121的物理端部。
如图5所示，多条第二组第一信号线142中沿第一方向D1排在最外侧的两条第一信号线分别与第三端1221和第四端1222连接，多条第二组第一信号线142中其余的第一信号线在第三端1221和第四端1222之间与第二引导走线122连接。此种情况下，第三端1221和第四端1222是指第二引导走线122的与多条第二组第一信号线142中沿第一方向D1排在最外侧的两条第一信号线连接的点，第三端1221和第四端1222可以是第二引导走线122的物理端部，也可以不是第二引导走线122的物理端部。
如图5所示，多条第三组第一信号线143中沿第一方向D1排在最外侧的两条第一信号线分别与第五端1231和第六端1232连接，多条第三组第一信号线143中其余的第一信号线在第五端1231和第六端1232之间与第三引导走线123连接。此种情况下，第五端1231和第六端1232是指第三引导走 线123的与多条第三组第一信号线143中沿第一方向D1排在最外侧的两条第一信号线连接的点，第五端1231和第六端1232可以是第三引导走线123的物理端部，也可以不是第三引导走线123的物理端部。
例如，对于相邻的第一组第一信号线141、第二组第一信号线142以及第三组第一信号线143，第二组第一信号线142与第二引导走线122的连接点、第一组第一信号线141与第一引导走线121的连接点、以及第三组第一信号线143与第三引导走线123的连接点在第一方向D1上顺次排布且彼此紧邻，也即，上述三个连接点之间不存在引导走线与第一信号线之间的其他的连接点。例如，上述第一组第一信号线141与第一引导走线121的连接点与第二组第一信号线142与第二引导走线122的连接点之间的间距与引导走线121-123的长度相比可以忽略不计，上述第一组第一信号线141与第一引导走线121的连接点与第三组第一信号线143与第三引导走线123的连接点之间的间距与引导走线121-123的长度相比可以忽略不计，因此上述相邻的第一组第一信号线141、第二组第一信号线142以及第三组第一信号线143接收的数据信号可以彼此匹配。例如，上述第一组第一信号线141与第一引导走线121的连接点与第二组第一信号线142与第二引导走线122的连接点之间的间距等于上述第一组第一信号线141与第一引导走线121的连接点与第三组第一信号线143与第三引导走线123的连接点之间的间距。例如，上述相邻的第一组第一信号线141、第二组第一信号线142以及第三组第一信号线143接收的数据信号可以分别与同一显示像素中的第一显示子像素、第二显示子像素和第三显示子像素相连，由此第一显示子像素、第二显示子像素和第三显示子像素接收的数据信号可以彼此匹配，进而第一显示子像素、第二显示子像素和第三显示子像素发射的光线可以混合成为白光。例如，引导走线是以均一的厚度和均一的宽度延伸的导电结构。
例如，第一信号线为数据线；多条第一组第一信号线141、多条第二组第一信号线142和多条第三组第一信号线143分别用于传输显示不同颜色的光的子像素的数据信号。例如，多条第一组第一信号线141用于传输显示绿光的子像素的数据信号，多条第二组第一信号线142用于传输显示红光的子像素的数据信号，多条第三组第一信号线143用于传输显示蓝光的子像素的数据信号。
如图5所示，显示区域140还包括沿第一方向D1延伸且平行设置的多条第二信号线144，多条第二信号线144与多条第一信号线交叉且绝缘，该交叉界定了阵列排布的多个显示子像素。例如，第二信号线144为栅线；多条第二信号线144用于传输扫描信号。例如，多条第一信号线所在的结构层与多条第二信号线144所在的结构层之间设置有绝缘层。例如，每个显示子像素包括像素驱动电路，该像素驱动电路可以包括晶体管、电容等器件。对于显示基板为自发光显示基板的情形，每个显示子像素还可以包括发光器件。
例如，显示区域140包括阵列排布的多个显示像素(图5中未示出)，每个显示像素包括第一显示子像素1451、第二显示子像素1452和第三显示子像素1453，第一显示子像素1451、第二显示子像素1452和第三显示子像素1453分别与第一组第一信号线141、第二组第一信号线142和第三组第一信号线143电连接，以基于第一组第一信号线141、第二组第一信号线142和第三组第一信号线143提供的数据信号发光。例如，第一显示子像素1451、第二显示子像素1452和第三显示子像素1453分别用于发射绿光、红光和蓝光。
需要说明的是，第一显示子像素1451、第二显示子像素1452和第三显示子像素1453的排布方式可以根据实际应用需求进行设定。例如，第一显示子像素1451、第二显示子像素1452和第三显示子像素1453的排布方式可以采用岛状(Island Type)排布方式、条形(Stipe Type)排布方式、三角性(Delta形)排布方式、马赛克型(Mosaic Type)排布方式，信号线的排布方式可以在图5示出的信号线的排布方式的基础上根据第一显示子像素1451、第二显示子像素1452和第三显示子像素1453的排布方式做适应性调整，在此不再赘述。
例如，第一部分1111、第二部分1121和第三部分1131和第一信号线同层设置，第一测试线111的第一延伸部分1112、第二测试线112的第二延伸部分1122、第三测试线113的第三延伸部分1132、第一引导走线121、第二引导走线122和第三引导走线123与第二信号线144同层设置，由此可以进一步地简化显示基板100的制作工艺。此种情况下，第一测试线111的第一延伸部分1112、第二测试线112的第二延伸部分1122和第三测试线113的第三延伸部分1132分别经由过孔与第一部分1111、第二部分1121和第三部 分1131连接，第一部分1111、第二部分1121和第三部分1131分别经由过孔与第一引导走线121、第二引导走线122和第三引导走线123连接，并且第一信号线分别经由过孔与第一引导走线121、第二引导走线122和第三引导走线123连接。作为示例，图11示出了第一测试线111的第一延伸部分1112、第一测试线111的第一部分1111、第一引导走线121与第一组第一信号线141之间的连接方式。图11为沿着第一测试线111的第一延伸部分1112、第一测试线111的第一部分1111、第一引导走线121与第一组第一信号线141的布线路径截取的截面图。如图11所示，显示基板100包括衬底基板1001；在衬底基板1001上，第一测试线111的第一部分1111和第一组第一信号线141同层设置，第一测试线111的第一延伸部分1112和第一引导走线121同层设置，第一测试线111的第一部分1111和第一组第一信号线141通过绝缘层1003与第一测试线111的第一延伸部分1112和第一引导走线121绝缘；第一测试线111的第一延伸部分1112通过第一过孔10031与第一测试线111的第一部分1111连接，第一测试线111的第一部分1111通过第二过孔10032与第一引导走线121连接，第一引导走线121通过第三过孔10033与第一组第一信号线141；第一过孔10031、第二过孔10032和第三过孔10033均设置在绝缘层1003中且为导电过孔。例如，第一测试线111的第一部分1111和第一组第一信号线141通过绝缘层1002与衬底基板1001绝缘；然而，本公开实施例不局限于此，可以不设置绝缘层1002而将第一测试线111的第一部分1111和第一组第一信号线141直接形成在衬底基板1001上。在图11中，第一测试线111的第一延伸部分1112和第一引导走线121位于第一测试线111的第一部分1111和第一组第一信号线141的上方；然而，本公开实施例不局限于此，可以将第一测试线111的第一部分1111和第一组第一信号线141设置在第一测试线111的第一延伸部分1112和第一引导走线121的上方。例如，可以按照与图11相似的方式，对第二测试线112的第二延伸部分1122、第二测试线112的第二部分1121、第二引导走线122与第二组第一信号线142进行连接。例如，可以按照与图11相似的方式，对第三测试线113的第三延伸部分1132、第三测试线113的第三部分1131、第三引导走线123与第三组第一信号线143进行连接。
在一些示例中，第一测试线111的第一延伸部分1112、第二测试线112 的第二延伸部分1122和第三测试线113的第三延伸部分1132还可以与第一部分1111、第二部分1121和第三部分1131以及第一信号线同层设置。此种情况下，第一测试线111的第一延伸部分1112、第二测试线112的第二延伸部分1122和第三测试线113的第三延伸部分1132可以通过直接搭接分别与第一部分1111、第二部分1121和第三部分1131电连接而无需过孔，第一部分1111、第二部分1121和第三部分1131分别经由过孔与第一引导走线121、第二引导走线122和第三引导走线123连接，并且第一信号线分别经由过孔与第一引导走线121、第二引导走线122和第三引导走线123连接。图12为沿着第一测试线111的第一延伸部分1112、第一测试线111的第一部分1111、第一引导走线121与第一组第一信号线141的布线路径截取的另一截面图。如图12所示，第一测试线111的第一延伸部分1112与第一测试线111的第一部分1111直接搭接，从而不需要设置图11所示的第一过孔10031；除此之外，图12的其他结构与图11相同，在此不再赘述。例如，可以按照与图12相似的方式，第二测试线112的第二延伸部分1122与第二测试线112的第二部分1121直接搭接。例如，可以按照与图12相似的方式，第三测试线113的第三延伸部分1132与第三测试线113的第三部分1131直接搭接。
如图5所示，邦定区130还包括多个第一组第一信号垫135、多个第二组第一信号垫136以及多个第三组第一信号垫137；多条第一组第一信号线141与多个第一组第一信号垫135一一对应连接；多条第二组第一信号线142与多个第二组第一信号垫136一一对应连接；多条第三组第一信号线143与多个第三组第一信号垫137一一对应连接。例如，上述多个第一组第一信号垫135、多个第二组第一信号垫136以及多个第三组第一信号垫137用于在后续工序中通过例如柔性电路板与数据驱动器连接，以从数据驱动器接收多个数据信号，并将多个数据信号提供给对应的第一信号线。
如图5所示，邦定区130还包括多个第二信号垫138，多条第二信号线144与多个第二信号垫138一一对应连接。例如，上述多个第二信号垫138用于在后续工序中通过例如柔性电路板与栅极驱动器连接，以从栅极驱动器接收多个扫描信号，并将多个扫描信号提供给对应的第二信号线144。在其他实施例中，显示基板上集成有栅极驱动电路(即GOA)，相应地，邦定区130还包括用于为该栅极驱动电路提供扫描起始信号(STV)、时钟信号等 的信号垫。
例如，邦定区130还可以不设置第一信号垫135～137和第二信号垫138，此种情况下，可以使用多根走线与第一信号线和第二信号线连接，并在后续工序中，将上述多根走线与栅极驱动器和数据驱动器连接。
如图5所示，邦定区130还包括第一测试垫131、第二测试垫132、第三测试垫133，用于在测试中与测试探针接触以接收相应的测试数据信号。例如，邦定区130还可以包括扫描信号测试垫(图中未示出)。
如图5所示，第一测试线111的一端与第一测试垫131电连接且第一测试线111的另一端与第一位置1213电连接，由此施加在第一测试垫131上的第一测试数据信号可经由第一测试线111和第一引导走线121施加到多条第一组第一信号线141上。第二测试线112的一端与第二测试垫132电连接且第二测试线112的另一端与第三位置1223电连接，由此施加在第二测试垫132上的第二测试数据信号可经由第二测试线112和第二引导走线122施加到多条第二组第一信号线142上。第三测试线113的一端与第三测试垫133电连接且第三测试线113的另一端与第四位置1233电连接，由此施加在第三测试垫133上的第三测试数据信号可经由第三测试线113和第三引导走线123施加到多条第三组第一信号线143上。
例如，第一测试线111、第二测试线112和第三测试线113的整体电阻彼此相等，由此使得第一测试线111、第二测试线112和第三测试线113导致的电压降彼此相等。例如，在第一测试线111、第二测试线112和第三测试线113的宽度、厚度和制作材料均相同的情况下，第一测试线111、第二测试线112和第三测试线113的长度也相等。例如，在第一测试垫131上施加的第一测试数据信号的幅值，在第二测试垫132上施加的第二测试数据信号的幅值，以及在第三测试垫133上施加的第三测试数据信号的幅值彼此相等的情况下，由于第一测试线111、第二测试线112和第三测试线113导致的电压降彼此相等，因此第一位置1213处的数据信号的幅值、第三位置1223处的数据信号的幅值和第四位置1233处的数据信号的幅值彼此匹配(例如，相等)。
在另一些示例中，第一测试线111、第二测试线112和第三测试线113的整体电阻和长度还可以彼此不相等，此种情况下，可以基于第一测试线 111、第二测试线112和第三测试线113的电阻差异信息获取第一测试线111、第二测试线112和第三测试线113之间的电压降差异，并基于上述电压降差异获取校正后的第一测试数据信号、校正后第二测试数据信号以及校正后的第三测试数据信号，以使得在将校正后的第一测试数据信号、校正后第二测试数据信号以及校正后的第三测试数据信号分别施加在第一测试垫131、第二测试垫132和第三测试垫133之后，在第一位置1213处的数据信号的幅值、第三位置1223处的数据信号的幅值和第四位置1233处的数据信号的幅值彼此匹配(例如，相等)。因此，在本公开的一些示例中，可以在保证或提升显示基板在测试阶段的亮度均匀性的基础上，降低对第一测试线111、第二测试线112和第三测试线113要求(例如，电阻一致性或长度一致性要求)，由此可以提升测试线的设计灵活性以及布线难度。
如图5所示，邦定区130还包括控制信号垫134，周边区域还设置有测试控制线114，测试控制线114与控制信号垫134连接并包括在邦定对置区120沿第一方向D1延伸的横向部分1141。如图5所示，邦定对置区120还包括多个第一组控制开关124、多个第二组控制开关125以及多个第三组控制开关126。
如图5所示，多个第一组控制开关124的第一端与多条第一组第一信号线141一一对应电连接，多个第一组控制开关124的第二端与第一引导走线121电连接；多个第一组控制开关124的第三端(控制端)与测试控制线114的横向部分1141电连接，以基于施加在控制信号垫134的控制信号控制多个第一组控制开关124的开启和关闭，由此控制是否将施加在第一测试垫131上的第一测试数据信号经由第一测试线111和第一引导走线121施加到多条第一组第一信号线141上。
如图5所示，多个第二组控制开关125的第一端与多条第二组第一信号线142一一对应电连接，多个第二组控制开关125的第二端与第二引导走线122电连接；多个第二组控制开关125的第三端(控制端)与测试控制线114的横向部分1141电连接，以基于施加在控制信号垫134的控制信号控制多个第二组控制开关125的开启和关闭，由此控制是否将施加在第二测试垫132上的第二测试数据信号经由第二测试线112和第二引导走线122施加到多条第二组第一信号线142上。
如图5所示，多个第三组控制开关126的第一端与多条第三组第一信号线143一一对应电连接，多个第三组控制开关126的第二端与第三引导走线123电连接；多个第三组控制开关126的第三端(控制端)与测试控制线114的横向部分1141电连接，以基于施加在控制信号垫134的控制信号控制多个第三组控制开关126的开启和关闭，由此控制是否将施加在第三测试垫133上的第三测试数据信号经由第三测试线113和第三引导走线123施加到多条第三组第一信号线143上。
例如控制开关124～126可以为晶体管，例如N型晶体管或P型晶体管，其第一端和第二端之一可以为源极，而另一个为漏极，第三端为栅极。作为控制开关124～126的晶体管例如可以在制备显示基板的过程中，与显示区中的显示子像素中的晶体管一同形成，由此可以简化制备工艺。例如，在包括图5示出的显示基板100的显示装置进行正常显示时，可以向控制信号垫134施加无效信号(使得控制开关关闭的电平信号)，以使得控制开关关闭，由此可以避免第一测试线111、第二测试线112和第三测试线113对显示装置的正常显示产生不利影响。
需要说明的是，根据实际应用需求，本公开的一些实施例提供显示基板100还可以不设置控制开关、控制信号垫和控制线，此种情况下，可以在完成显示基板100的测试之后，通过切割将位于邦定对置区120中的第一引导走线121、第二引导走线122和第三引导走线123去除，在此不再赘述。
例如，在对显示基板100进行测试(例如，液晶盒测试)中，可以在第一测试垫131、第二测试垫132和第三测试垫133的至少一个上施加测试数据信号，在控制信号垫134上施加有效信号(使得控制开关开启的电平信号)，以使得控制开关开启，使得在第一测试垫131、第二测试垫132和第三测试垫133的至少一个上施加的测试数据信号能够传输到对应的第一信号线(数据线)上，并且在扫描信号垫施加栅极扫描信号，以使得传输到对应的第一信号线(数据线)上的测试数据信号能够驱动对应的显示子像素发光。
如图5所示，第一测试垫131和第二测试垫132在第一方向D1上位于显示区域140的一侧，第三测试垫133和控制信号垫134在第一方向D1上位于显示区域140的另一侧。例如，将第一测试垫131、第二测试垫132和第三测试垫133在第一方向D1上分别设置在显示区域140的两侧可以满足 特定显示基板100(例如，基于GOA的显示基板100)的布线要求(例如，布线空间小)和/或增加测试设备选择范围(例如，对测试设备的测试信号通道数量的要求降低)。
例如，第一测试线111和第二测试线112可以由邦定区130(例如，显示基板100的左下角)延伸至邦定对置区120的中间区域，第三测试线113可以由邦定区130(例如，显示基板100的右下角)延伸至邦定对置区120的中间区域，测试控制线114可以由邦定区130(例如，显示基板100的右下角)延伸至邦定对置区120的左侧(例如，显示基板100的左上角)。
在一些示例中，显示基板100还包括控制引导走线190，如图10所示，测试控制线114还可以由邦定区130(例如，显示基板100的右下角)延伸至邦定对置区120的中间区域，此种情况下，控制引导走线190包括第七端191和第八端192，并且测试控制线114经由控制引导走线190上位于第七端191和第八端192之间的连接点与控制引导走线190连接。此处，第七端191和第八端192是指控制引导走线190的与多个控制开关124-126中沿第一方向D1位于最外侧的两个控制开关连接的点，并且第七端191和第八端192可以是也可以不是控制引导走线190的物理端点。例如，通过设置控制引导走线190，可以使得不同控制开关接收的控制信号(有效信号或无效信号)的时间延迟降低，由此使得位于不同位置处的显示子像素的亮度变化更为一致，并提升显示基板的瞬时亮度均匀性。
例如，控制引导走线190的具体设计以及测试控制线114与控制引导走线190的连接关系可以参照第一引导走线121和第一测试线111进行设计，在此不再赘述。例如，控制引导走线190位于邦定对置区120，且与第一引导走线121、第二引导走线122和第三引导走线123平行设置。
例如，第一位置1213为第一引导走线121在第一端1211和第二端1212之间的“电阻中点”(下面称为第一引导走线121的电阻中点)。在本公开实施例中，“电阻中点”指的是走线上两点之间使得到该两点的电阻相等的点；相应地，下面描述中提及的“电阻1/3点”指的是走线上两点(起点和终点)之间使得到起点的电阻等于起点和终点之间电阻的1/3的点，“电阻2/3点”指的是走线上两点(起点和终点)之间使得到起点的电阻等于起点和终点之间电阻的2/3的点。
在第一位置1213为“电阻中点”情况下，第一端1211处的电压信号的幅值等于第二端1212处的电压信号的幅值，并且第一引导走线121上的最大的电压降为第一位置1213处的电压信号的幅值与第一端1211处(或第二端1212处)的电压信号的幅值的差值。因此，图5所示的显示基板100的第一引导走线121上的最大的电压降为图1示出的显示基板500的第一测试线511的第一部分上最大电压降的例如一半。并且，图5所示的显示基板100的第一引导走线121上的电压降关于第一位置1213例如对称分布。下面结合图6和图7进行示例性说明。
图6示出了图5示出的显示基板100的第一引导走线121上的第一端1211和第二端1212的电压信号随时间的变化的仿真曲线。图6的横轴为时间，这里，u表示微秒，m表示毫秒；图6的纵轴为电压信号的幅值。
图7示出了第一显示子像素在第一方向D1上的亮度分布图161、第二显示子像素在第一方向D1上的亮度分布图162以及第三显示子像素在第一方向D1上的亮度分布图163，这里，亮度分布图在纵向方向的尺寸表示该亮度分布图对应的显示子像素的亮度。
如图6所示，在向第一测试垫131施加方波脉冲170的情况下，第一引导走线121的第一端1211的电压信号171的上升沿的陡峭程度与第一引导走线121的第二端1212的电压信号172的上升沿的陡峭程度具有较好的匹配度(即，基本相同)，并且第一引导走线121的第一端1211的电压信号171的幅值与第一引导走线121的第二端1212的电压信号172的幅值具有较好的匹配度(即，基本相等)，这表明第一引导走线121的第一端1211和第一引导走线121的第二端1212具有类似的电压降和时间延迟，由此图5示出的显示基板100减小了第一引导走线121上的最大的电压降。例如，如图6所示，第一引导走线121的第一端1211的电压信号171的上升沿的上升时间约为199微秒，第一引导走线121的第二端1212的电压信号172的上升时间约为211微秒，两者之间仅相差12微秒；第一引导走线121的第一端1211的电压信号171的幅值与第一引导走线121的第二端1212的电压信号172的幅值之差仅约为53毫伏。例如，第二引导走线122的信号以及第三引导走线123的信号具有类似的电压降特性以及时间延迟特性，在此不再赘述。
例如，第一引导走线121上的电压信号的幅值沿第一方向D1先增加后 降低(也即，第一引导走线121的第一位置1213处的电压信号的幅值最大，电压信号的幅值从第一位置1213向第一位置1213的两侧逐渐降低)，第一引导走线121上的电压信号的相位延迟沿第一方向D1先降低后增加。对应地，在第一方向D1上，第一子像素的发光亮度先增加后降低(参见图7)。
例如，通过使得第一引导走线121上的电压信号的幅值沿第一方向D1先增加后降低，可以减小第一引导走线121上的最大的电压降，由此可以降低图5所示的显示基板100的第一显示子像素在第一方向D1上的亮度差异，也即，在同一时刻，具有最大发光亮度的第一显示子像素与具有最小发光亮度的第一显示子像素之间的发光亮度差值降低。这提升了显示基板100亮度均匀性，进而可以降低由显示基板100的测试线设计引起的亮度不均匀而导致的漏检，以及提升显示基板测试阶段的不良检出率。
例如，第三位置1223可以为第二引导走线122的第三端1221和第四端1222之间的电阻中点(下面称为第二引导走线122的电阻中点)，第四位置1233可以为第三引导走线123的第五端1231和第六端1232之间的电阻中点(下面称为第三引导走线123的电阻中点)。此种情况下，可以使得图5所示的显示基板100的第二引导走线122上的最大的电压降以及第三引导走线123上的最大的电压降分别为图1示出的显示基板500的第二测试线512的第二部分上最大电压降以及第三测试线513的第三部分上最大电压降的例如一半，并且，使得图5所示的显示基板100的第二引导走线122上的电压降关于第三位置1223例如对称分布，第三引导走线123上的电压降关于第四位置1233例如对称分布。
例如，第二引导走线122上的电压信号的幅值和第三引导走线123上的电压信号的幅值沿第一方向D1先增加后降低，第二引导走线122和第三引导走线123上的电压信号的相位延迟沿第一方向D1先降低后增加。对应地，在第一方向D1上，第二子像素的发光亮度和第三子像素的发光亮度先增加后降低(参见图7)。
例如，通过使得第二引导走线122和第三引导走线123上的电压信号的幅值沿第一方向D1先增加后降低，可以减小第二引导走线122和第三引导走线123上的最大的电压降，由此可以降低图5所示的显示基板100的第二显示子像素在第一方向D1上的亮度差异以及第三显示子像素在第一方向D1 上的亮度差异，提升显示基板100亮度均匀性，进而可以降低由显示基板100的测试线设计引起的亮度不均匀导致的漏检，以及提升显示基板测试阶段的不良检出率。
例如，在第一引导走线121、第二引导走线122和第三引导走线123分别具有均匀的厚度、宽度以及材料分布且第一电阻比值、第二电阻比值和第三电阻比值彼此相等的情况下，第一引导走线121、第二引导走线122和第三引导走线123上的电压降一致且彼此匹配，由此使得同一显示像素中第一显示子像素1451、第二显示子像素1452和第三显示子像素1453接收到的数据信号彼此匹配，并使得显示基板100的同一显示像素的第一显示子像素1451、第二显示子像素1452和第三显示子像素1453的发光强度匹配(例如，可以混合形成白光)，由此可以抑制显示基板100的色偏问题。
例如，在第一位置1213为第一引导走线121的第一端1211和第二端1212之间的电阻中点(下面称为第一引导走线121的电阻中点)，第三位置1223为第二引导走线122的第三端1221和第四端1222之间的电阻中点，第四位置1233为第三引导走线123的第五端1231和第六端1232之间的电阻中点的情况下，第一引导走线121的第一端1211和第二端1212之间的电阻中点(即第一位置1213)为第一端1211和第二端1212之间的中点，第二引导走线122的第三端1221和第四端1222之间的电阻中点(即第三位置1223)为第三端1221和第四端1222之间的中点，第三引导走线123的第五端1231和第六端1232之间的电阻中点(即第四位置1233)为第五端1231和第六端1232之间的中点，由此使得第一引导走线121的电阻中点对应的第一显示子像素1451、第二引导走线122的电阻中点对应的第二显示子像素1452以及第三引导走线123的电阻中点对应的第三显示子像素1453可以位于显示基板100的同一个显示像素中。
图7还示出了显示基板100显示的颜色沿第一方向D1的分布图160，这里假设了第一显示子像素1451、第二显示子像素1452和第三显示子像素1453分别发射绿光、红光和蓝光。
由于第一引导走线121、第二引导走线122和第三引导走线123的电压降一致且彼此匹配，显示基板100的同一显示像素的第一显示子像素1451、第二显示子像素1452和第三显示子像素1453的发光强度匹配。例如，它们 分别被施加值为255的数据信号(取值范围为0～255)时，所发出的红光、绿光和蓝光可以混合形成白光，如图7的分布图160所示。由此，可以抑制显示基板100的色偏问题。
例如，由于引导走线从电阻中点到引导走线两端的电压信号的幅值逐步降低，因此，在第一方向D1上显示基板100的显示像素的发光亮度(例如，白光亮度)从显示区域140中对应于电阻中点的位置向显示区域140的两侧(在第一方向D1上的两侧)逐渐降低。
例如，由于图5所示的显示基板100可以抑制显示基板100的色偏问题，因此，可以降低由显示基板100的测试线设计引起的色偏而导致的漏检，进一步地提升显示基板测试阶段的不良检出率。
需要说明的是，第一位置1213不限于第一引导走线121的第一端1211和第二端1212之间的电阻中点，第一位置1213还可以为第一引导走线121的第一端1211和第二端1212之间其它任意位置，此时，对应的显示基板100也具有一定的降低亮度差异的技术效果。类似地，第三位置1223还可以为第二引导走线122的第三端1221和第四端1222之间其它任意位置，第四位置1233还可以为第三引导走线123的第五端1231和第六端1232之间其它任意位置，对应的显示基板100也具有一定的降低亮度差异的技术效果。
需要说明的是，第一电阻比值、第二电阻比值和第三电阻比值不限于设置为彼此相等，根据实际应用需求，第一电阻比值、第二电阻比值和第三电阻比值还可以具有一定的差异，此种情况下，图5示出的显示基板100具有一定程度的色偏，但图5示出的显示基板100的色偏依然可以弱于图1示出的显示基板500的色偏。
需要说明的是，第一测试垫131、第二测试垫132和第三测试垫133不限于在第一方向D1上分别设置在显示区域140的两侧，根据实际应用需求，第一测试垫131、第二测试垫132和第三测试垫133在第一方向D1上可以设置在显示区域140的同一侧。此种情况下，通过设置第一引导走线121、第二引导走线122和第三引导走线123，也可以降低显示基板100在第一方向D1上亮度差异，提升显示基板100的亮度均匀性，由此可以降低由显示基板亮度不均匀导致的漏检，提升显示基板测试阶段的不良检出率。
例如，在显示基板100用于液晶显示面板的情况下，显示基板100可以 为阵列基板，在第二方向上，阵列基板的尺寸大于与其对盒的彩膜基板的尺寸，且邦定区130位于阵列基板不与彩膜基板交叠的区域(即阵列基板由彩膜基板暴露的区域)，由此可以在显示基板的测试中，向第一测试垫131、第二测试垫132、第三测试垫133施加测试数据信号，并且可以在后续工序中，将第一信号线和第二信号线分别与栅极驱动器和数据驱动器连接。
在另一些示例中，第一测试线111还在第一引导走线121上的第二位置1214与第一引导走线121电连接，第二位置1214位于第一端1211和第二端1212之间且与第一位置1213不同，由此可以进一步地降低第一显示子像素沿第一方向D1的亮度差异，提升显示基板100的亮度均匀性以及显示基板测试阶段的不良检出率。
例如，第一位置1213和第二位置1214分别位于第一引导走线121的第一端1211和第二端1212之间的电阻1/3点和电阻2/3点，由此可以进一步地降低第一显示子像素沿第一方向D1的亮度差异，提升显示基板100的亮度均匀性以及显示基板测试阶段的不良检出率。下面以图8示出的第一测试线111进行示例性的说明。
如图8所示，第一测试线111除了包括沿第二方向D2延伸的第一部分1111以及从第一测试垫131延伸至第一部分1111的一端并与该第一部分1111的一端连接的第一延伸部分1112之外，第一测试线111还包括第一子走线1113、第二子走线1114和第三子走线1115。在图8中，上虚线框包围的线段为第一子走线1113，左虚线框包围的线段为第二子走线1114，右虚线框包围的线段为第三子走线1115。
如图8所示，第一子走线1113沿第一方向D1延伸，且包括第一子走线1113的第一端11131、第一子走线1113的第二端11133以及第一子走线1113的第一位置11132。第一部分1111的另一端经由第一子走线1113的第一位置11132与第一子走线1113相连；第二子走线1114的一端与第一子走线1113的第一端11131相连，第二子走线1114的另一端与第一引导走线121的第一位置1213相连；第三子走线1115的一端与第一子走线1113的第二端11133相连，第三子走线1115的另一端与第一引导走线121的第二位置1214相连。
例如，第一子走线1113的第一位置11132为第一子走线1113在第一子走线1113的第一端11131和第一子走线1113的第二端11133之间的电阻中 点，由此第一子走线1113的第一端11131和第一子走线1113的第二端11133的电压信号的幅值相等；在第二子走线1114和第三子走线1115电阻值相等的情况下，第一引导走线121的第一位置1213的电压信号的幅值等于第一引导走线121的第二位置1214的电压信号的幅值，并且，图8示出的第一引导走线121上的最大的电压降为图1示出的显示基板500的第一测试线511的第一部分上最大电压降的例如三分之一。其他实施例中，第一子走线1113可以通过更多(大于等于3个)位置与第一引导走线121电连接，从而使得第一引导走线121上的压降差异更小。
例如，在将图8示出的第一测试线111和第一引导走线121应用于图5示出的显示基板100中，可以进一步地降低第一引导走线121上的电压信号幅值和相位延迟的差异，并因此可以进一步地降低显示基板100沿第一方向D1的亮度差异，提升显示基板100的亮度均匀性，由此可以进一步地降低由显示基板100亮度不均匀导致的漏检，提升显示基板测试阶段的不良检出率。
例如，根据实际应用需求，第一测试线111还可以在第一引导走线121上的更多位置处与第一引导走线121电连接，例如，与第一引导走线121的第一端1211和第二端1212之间的电阻1/5点、电阻2/5点、电阻3/5点和电阻4/5点电连接，由此可以进一步地提升显示基板100的亮度均匀性，以及显示基板测试阶段的不良检出率，在此不再赘述。
需要说明的是，图5示出的显示基板100中的第二测试线112和第二引导走线122以及第三测试线113和第三引导走线123也可以采用类似于图8示出的设计，由此可以进一步地降低第二引导走线122和第三引导走线123上的电压信号幅值和相位延迟的差异，并因此可以进一步地降低显示基板100沿第一方向D1的亮度差异，提升显示基板测试阶段的不良检出率。
需要说明的是，为清楚起见，以上的实施例主要说明了显示基板100的引导走线(例如，第一引导走线121)上的电压信号的幅值差异降低对提升显示基板100的亮度均匀性以及抑制色偏的作用，然而，引导走线上的电压信号的时间延迟差异的降低也会对提升显示基板100的亮度均匀性以及抑制色偏具有一定的作用，在此不再赘述。
本公开的至少一个实施例还提供了一种显示装置，其包括本公开的任一实施例提供的显示基板1。
图9示出了本公开的一些实施例提供的显示装置10。如图9所示，该显示装置10包括本公开的任一实施例提供的显示基板100以及主控电路200，显示基板100与主控电路200电连接。例如，在主控电路200的控制下，显示基板100实现显示功能。例如，在主控电路200的控制下，对显示基板100的性能进行测试。例如，主控电路200为中央处理器。
需要说明的是，对于主控电路的组成部分(例如，供电电路、图像数据编码/解码装置、栅极驱动器、数据驱动器、时钟电路等)可以采用适用的常规部件，在此不做赘述，也不应作为对本公开实施例的限制。例如，根据本公开实施例的显示装置10可以是手机、平板电脑、电视机、显示器、笔记本电脑、数码相机、导航仪等具有显示功能的产品或部件。
本公开的一些实施例又提供了一种上述的显示基板的测试方法，其包括：经由第一测试线和第一引导走线向多条第一组第一信号线施加第一信号，并基于显示基板的显示情况进行检测。
下面以图5示出的显示基板为例，对本公开的至少一个实施例提供的显示基板的测试方法做示例性说明。
例如，显示基板的测试方法包括步骤S101-步骤S103的至少一个步骤。
步骤S101：经由第一测试线和第一引导走线向多条第一组第一信号线施加第一信号，并基于显示基板的显示情况进行检测。
步骤S102：经由第二测试线和第二引导走线向多条第二组第一信号线施加第二信号，并基于显示基板的显示情况进行检测。
步骤S103：经由第三测试线和第三引导走线向多条第三组第一信号线施加第三信号，并基于显示基板的显示情况进行检测。
例如，在步骤S101中，可以在第一测试垫上施加第一信号(也即，测试数据信号)，在控制信号垫上施加有效信号(例如，使得控制开关开启的电平信号)，以使得在第一测试垫上施加的测试数据信号能够传输到多条第一组第一信号线上，并且在扫描信号垫施加栅极扫描信号，以使得传输到多条第一组第一信号线上的第一信号能够驱动对应的第一显示子像素发光。然后，可以基于第一显示子像素发光情况进行检测。例如，可以基于显示区域的多个第一显示子像素发光情况判定显示基板的显示区域本身是否存在不良，例如亮度不均匀问题(MURA)。又例如，可以基于全白测试时是否存 在亮度为零或者亮度偏低的第一显示子像素判定显示基板的显示区域本身是否存在亮点不良或者暗点不良。
例如，步骤S102和步骤S103的具体方法与步骤S101类似，在此不再赘述。例如，在显示基板的测试时，可以根据需求执行步骤S101-步骤S103中的至少一个步骤；在执行步骤S101-步骤S103中的多个步骤时，该多个步骤可以顺次执行，也可以同时执行，下面以同时执行步骤S101-步骤S103进行示例性说明。
例如，在同时执行步骤S101-步骤S103时，可以在第一测试垫、第二测试垫和第三测试垫的分别施加第一信号、第二信号和第三信号，在控制信号垫上施加有效信号(使得控制开关开启的电平信号)，以使得控制开关开启，并使得在第一测试垫、第二测试垫和第三测试垫上施加的第一信号、第二信号和第三信号能够传输到对应的信号线上，并且在扫描信号垫施加栅极扫描信号，以使得传输到对应的信号线上的信号能够驱动对应的显示子像素发光。此种情况下，可以检测显示基板是否存在例如色度偏差。
由于本公开的一些实施例提供的显示基板可以降低由显示基板的测试引线导致的亮度差异和/或色偏，因此可以降低由显示基板的测试引线导致的漏检，提升显示基板测试阶段的不良检出率。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (20)

  1. 一种显示基板，包括显示区域以及设置在所述显示区域外的周边区域，其中，
    所述周边区域中设置有沿第一方向延伸的第一引导走线，所述第一引导走线包括第一端和第二端；
    所述周边区域中还设置有第一测试线，所述第一测试线在所述第一引导走线上的第一位置与所述第一引导走线电连接，所述第一位置位于所述第一端和所述第二端之间；以及
    所述显示区域包括沿不同于所述第一方向的第二方向延伸且平行设置的多条第一组第一信号线，所述多条第一组第一信号线中沿所述第一方向排在最外侧的两条第一信号线分别与所述第一端和所述第二端连接，所述多条第一组第一信号线中其余的第一信号线在所述第一端和所述第二端之间与所述第一引导走线连接。
  2. 根据权利要求1所述的显示基板，其中，所述第一位置为所述第一引导走线的第一端和第二端之间的电阻中点。
  3. 根据权利要求1所述的显示基板，其中，所述第一测试线还在所述第一引导走线上的第二位置与所述第一引导走线电连接，所述第二位置位于所述第一端和所述第二端之间且与所述第一位置不同。
  4. 根据权利要求3所述的显示基板，其中，所述第一位置和所述第二位置分别位于所述第一引导走线的第一端和第二端之间的电阻1/3点和电阻2/3点。
  5. 根据权利要求1-4任一项所述的显示基板，其中，
    所述显示区域还包括沿所述第一方向延伸且平行设置的多条第二信号线；
    所述多条第二信号线与所述第一组第一信号线交叉且绝缘；并且
    所述第一引导走线和所述多条第二信号线同层设置。
  6. 根据权利要求5所述的显示基板，其中，
    所述第一测试线包括沿所述第二方向延伸的第一部分以及除所述第一部分之外的第一延伸部分，所述第一部分的一端与所述第一引导走线电连接， 且所述第一部分的另一端与所述第一延伸部分电连接；
    所述第一部分和所述多条第一组第一信号线同层设置；并且
    所述第一延伸部分、所述第一引导走线和所述多条第二信号线同层设置。
  7. 根据权利要求1至6任一项所述的显示基板，其中，
    所述周边区域包括邦定区和邦定对置区；
    所述邦定区和所述邦定对置区沿所述第二方向分别位于所述显示区域的两侧；并且
    所述第一引导走线设置在所述邦定对置区中。
  8. 根据权利要求7所述的显示基板，其中，所述邦定区包括第一测试垫，所述第一测试线的一端与所述第一测试垫电连接且所述第一测试线的另一端在所述第一位置处与所述第一引导走线电连接。
  9. 根据权利要求7所述的显示基板，其中，所述邦定区包括多个第一组第一信号垫，所述多条第一信号线与所述多个第一组第一信号垫一一对应连接。
  10. 根据权利要求7所述的显示基板，其中，
    所述周边区域还设置有测试控制线；
    所述邦定对置区还包括多个第一组控制开关，所述多个第一组控制开关的第一端与所述多条第一组第一信号线一一对应电连接，所述多个第一组控制开关的第二端与所述第一引导走线电连接，所述多个第一组控制开关的控制端与所述测试控制线电连接。
  11. 根据权利要求10所述的显示基板，其中，
    所述邦定对置区还设置有第二引导走线，所述第二引导走线沿所述第一方向延伸且包括第三端和第四端；
    所述周边区域中还设置有第二测试线，所述第二测试线在所述第二引导走线上的第三位置与所述第二引导走线电连接，所述第三位置位于所述第三端和所述第四端之间；以及
    所述显示区域还包括沿所述第二方向延伸且平行设置的多条第二组第一信号线，所述多条第二组第一信号线中沿所述第一方向排在最外侧的两条第一信号线分别与所述第三端和所述第四端连接，所述多条第二组第一信号线中其余的第一信号线在所述第三端和所述第四端之间与所述第二引导走线连 接；以及
    所述邦定区还包括第二测试垫，所述第二测试线的一端与所述第二测试垫电连接，且所述第二测试线的另一端在所述第三位置处与所述第二引导走线电连接。
  12. 根据权利要求11所述的显示基板，其中，
    所述邦定对置区还设置有第三引导走线，所述第三引导走线沿所述第一方向延伸且包括第五端和第六端；
    所述周边区域还设置有第三测试线，所述第三测试线在所述第三引导走线上的第四位置与所述第三引导走线电连接，所述第四位置位于所述第五端和所述第六端之间；
    所述显示区域还包括沿所述第二方向延伸且平行的多条第三组第一信号线，所述多条第三组第一信号线中沿所述第一方向排在最外侧的两条第一信号线分别与所述第五端和所述第六端连接，所述多条第三组第一信号线中其余的第一信号线在所述第五端和所述第六端之间与所述第三引导走线连接；以及
    所述邦定区还包括第三测试垫，所述第三测试线的一端与所述第三测试垫电连接，且所述第三测试线的另一端在所述第四位置与所述第三引导走线电连接。
  13. 根据权利要求10所述的显示基板，其中，
    所述邦定对置区中设置有沿所述第一方向延伸的控制引导走线，所述控制引导走线包括第七端和第八端；
    所述测试控制线在所述控制引导走线上位于所述第七端和所述第八端之间的连接点处与所述控制引导走线连接；
    所述多个第一组控制开关中沿所述第一方向排在最外侧的两个控制开关分别与所述第七端和所述第八端连接，所述多个第一组控制开关中其余的控制开关在所述第七端和所述第八端之间与所述控制引导走线连接。
  14. 根据权利要求12所述的显示基板，其中，
    所述邦定对置区还包括多个第二组控制开关，所述多个第二组控制开关的第一端与所述多条第二组第一信号线一一对应电连接，所述多个第二组控制开关的第二端与所述第二引导走线电连接，所述多个第二组控制开关的控 制端与所述测试控制线电连接；并且
    所述邦定对置区还包括多个第三组控制开关，所述多个第三组控制开关的第一端与所述多条第三组第一信号线一一对应电连接，所述多个第三组控制开关的第二端与所述第三引导走线电连接，所述多个第三组控制开关的控制端与所述测试控制线电连接。
  15. 根据权利要求12所述的显示基板，其中，
    所述邦定区还设置与所述测试控制线电连接的控制信号垫；
    所述第一测试垫和所述第二测试垫在所述第一方向上位于所述显示区域的一侧，所述第三测试垫和所述控制信号垫在所述第一方向上位于所述显示区域的另一侧。
  16. 根据权利要求12所述的显示基板，其中，
    第一电阻比值、第二电阻比值和第三电阻比值彼此相等；
    所述第一电阻比值为所述第一引导走线的所述第一端与所述第一位置之间的电阻值与所述第一引导走线的所述第一位置与所述第二端之间的电阻值的比值；
    所述第二电阻比值为所述第二引导走线的所述第三端与所述第三位置之间的电阻值与所述第二引导走线的所述第三位置与所述第四端之间的电阻值的比值；以及
    所述第三电阻比值为所述第三引导走线的所述第五端与所述第四位置之间的电阻值与所述第三引导走线的所述第四位置与所述第六端之间的电阻值的比值。
  17. 根据权利要求16所述的显示基板，其中，
    所述第一位置为所述第一引导走线的所述第一端和所述第二端之间的电阻中点；
    所述第三位置为所述第二引导走线的所述第三端和所述第四端之间的电阻中点；以及
    所述第四位置为所述第三引导走线的所述第五端和所述第六端之间的电阻中点。
  18. 根据权利要求12所述的显示基板，其中，所述多条第一组第一信号线、所述多条第二组第一信号线和所述多条第三组第一信号线分别用于传输 显示不同颜色的光的子像素的数据信号。
  19. 根据权利要求12所述的显示基板，其中，所述第一测试线、所述第二测试线和所述第三测试线的电阻彼此相等。
  20. 一种显示装置，包括如权利要求1-19任一所述的显示基板以及与所述显示基板电连接的主控电路。
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