WO2020130039A1 - Semiconductor device joining member - Google Patents

Semiconductor device joining member Download PDF

Info

Publication number
WO2020130039A1
WO2020130039A1 PCT/JP2019/049601 JP2019049601W WO2020130039A1 WO 2020130039 A1 WO2020130039 A1 WO 2020130039A1 JP 2019049601 W JP2019049601 W JP 2019049601W WO 2020130039 A1 WO2020130039 A1 WO 2020130039A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
voids
joining
metal
bonding
Prior art date
Application number
PCT/JP2019/049601
Other languages
French (fr)
Japanese (ja)
Inventor
福井　彰
としゑ 福井
Original Assignee
株式会社半導体熱研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社半導体熱研究所 filed Critical 株式会社半導体熱研究所
Publication of WO2020130039A1 publication Critical patent/WO2020130039A1/en

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/30—Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C5/00—Alloys based on noble metals
    • C22C5/02—Alloys based on gold
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C5/00—Alloys based on noble metals
    • C22C5/06—Alloys based on silver
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C9/00—Alloys based on copper
    • C22C9/02—Alloys based on copper with tin as the next major constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector

Definitions

  • the present invention relates to a semiconductor device joining member used for joining a semiconductor device and a substrate.
  • HV Hybrid Vehicle
  • EV Electric Vehicle
  • IGBT insulated gate bipolar transistor
  • the first-generation IGBT module For the first-generation IGBT module, initially a DBC (Direct Bonded Cupper; an insulating ceramic substrate joined with Cu with excellent conductivity as a circuit layer) was considered as the insulating circuit substrate, but it was more severe. DBA (Direct Bonded Aluminum, which has a highly conductive Al joined as a circuit layer to a ceramic substrate.) that can be used in the usage environment has come to be used. After that, by omitting the heat dissipation board and thermal grease, and adopting a structure in which the DBA and the cooler are joined with Al punching metal, the second-generation IGBT module reduces thermal resistance by 30% compared to the first-generation IGBT module. Was put to practical use.
  • DBC Direct Bonded Cupper; an insulating ceramic substrate joined with Cu with excellent conductivity as a circuit layer
  • heat path A structure in which a heat dissipation path (hereinafter, referred to as “heat path”) is provided on one surface of a semiconductor device, like the first-generation IGBT module and the second-generation IGBT module, is called a single-sided cooling structure.
  • the 3rd generation IGBT module has a double-sided cooling structure in which Cu thin plates are soldered on both sides of the semiconductor device, and the semiconductor device is insulated by Si 4 N 3 ceramic (hereinafter referred to as “SIN ceramic”). Then, it is joined to the cooler with an insulating resin adhesive (insulating grease).
  • SIN ceramic Si 4 N 3 ceramic
  • an insulating resin adhesive insulating grease
  • the heat radiation path from the semiconductor device used in the 3rd generation IGBT module has a simple structure in which the electrode substrate, the SIN ceramic plate material, and the radiator of the cooler are joined. Bonding of a semiconductor device and a substrate such as an electrode substrate is called die bonding (or die attachment or chip bonding). The material used for die bonding is called a die bond material.
  • the electrode substrate, the SIN ceramic plate material, and the radiator of the cooler are joined with an insulating resin adhesive (insulating grease). Since the heat path composed of these members can be used for both double-sided cooling structure and single-sided cooling structure, it is considered to be widely used in the future as a heat path for IGBT modules.
  • the present inventor has proposed a heat dissipation electrode substrate containing a metal and diamond as main components, in which the thermal resistance of the Cu electrode is reduced (the thermal conductivity is higher than Cu) in order to improve the heat dissipation efficiency in the IGBT module ( Patent Document 1). Further, a high thermal conductive insulating resin composite member used for joining a heat dissipation substrate or an electrode to a cooler is also proposed (Patent Document 2). This high thermal conductive insulating resin composite member has a main layer in which diamond or ceramic is placed in an insulating resin material, and protective bonding layers placed on the front and back surfaces of the main layer. By using this high heat conductive insulating resin composite member in place of the conventional insulating member made of a resin adhesive and ceramic, the thermal resistance can be significantly reduced.
  • the thermal resistance of the heat path in the IGBT module is reduced by using the heat dissipation substrate and the high thermal conductive insulating resin composite member proposed by the present inventors in Patent Documents 1 and 2.
  • the main heat path also includes a die bond for joining a semiconductor device and a substrate (for example, an electrode substrate).
  • the thermal resistance of the die bond material must be reduced in order to further reduce the size and improve the performance of the IGBT module by mounting the semiconductor device whose maximum operating temperature reaches 300°C. Further, reliability during operation of the semiconductor device is also required.
  • the DBA is equipped with a Si semiconductor device with a maximum operating temperature of about 150°C.
  • the coefficient of linear expansion of Si which is the material for semiconductor devices, is 4.5 ppm/K.
  • the linear expansion coefficient of DBA is 7 ppm/K.
  • the reliability of the die bond of the solder thus formed can be ensured by confirming the meniscus state of the solder on the outer periphery and confirming defects such as voids by measuring the inside of the solder with X-rays or ultrasonic waves. , Has been used for a long time.
  • the meniscus state of the solder means a state in which the solder flows to the outer periphery of the joint.
  • the linear expansion coefficient of Cu is 17 ppm/K.
  • the difference in the linear expansion coefficient of the electrodes increases to 12.5 ppm/K, and the die bond breaks.
  • DBC diamond-diene styrene
  • peeling of the Cu electrode and destruction of the ceramic occur at the portion where the thermal stress is concentrated. Therefore, when the maximum operating temperature becomes high, it becomes difficult for the die bond material such as solder to relax the thermal stress generated between them.
  • Sn solder In-vehicle IGBT modules are Pb-free, Sn-based solder (Sn-based solder) such as SnCu (melting point 228°C), SnAg-based (melting point 221°C), SnAgCu-based (melting point 219°C). , SnSb-based (melting point 240 °C) solder is used. Further, those Sn-based solders filled with Ni balls to adjust the thickness of the die bond are also used. However, all of these have melting points below 300°C. Moreover, the thermal conductivity is as low as 60 W/mK or less. Furthermore, the electric conductivity is also extremely low at 25% IACS or less.
  • IACS International Annealed Copper Standard
  • Sn has a melting point of 234° C., a thermal conductivity of 66 ppm/m ⁇ K, and an electrical conductivity of 15% IACS. Therefore, it is difficult to use the Sn-based solder containing Sn as a main component to release heat emitted from a semiconductor device having a maximum operating temperature of 300° C. or to use for joining such a semiconductor device and an electrode.
  • Au solder A solder that uses a eutectic of Au and an additive material, which has higher heat resistance than Sn-based solder, is also used.
  • AuSi solder containing Si as an additive has a melting point of 370° C., but is brittle, and has a low thermal conductivity of 53 W/m ⁇ K and a low electrical conductivity of 22% IACS.
  • the AuGe solder containing Ge as an additive also has a melting point of 356° C., but is brittle, and has a low thermal conductivity of 44 W/m ⁇ K and a low electrical conductivity of 17% IACS.
  • these Au-based solders are expensive and unsuitable for use as a material for joining semiconductor devices having particularly large dimensions.
  • Ag wax material In addition to the above, there is also a method of joining the semiconductor device and the electrode with Ag wax material having high heat resistance.
  • Ag wax has good properties in that it has high thermal conductivity and high electrical conductivity.
  • the melting point of Ag wax material is generally 600° C. or higher, and there is a problem in that when a semiconductor device and an electrode are fusion-bonded using Ag wax material, the semiconductor device is damaged by heat.
  • Non-Patent Document 1 Nano-sized Ag particles (including those generated by reduction of silver oxide) and flake-shaped Ag particles are sintered at a temperature lower than the melting point of the bulk material due to their surface activity. It has been proposed to utilize the low temperature fusion phenomenon of being (low temperature sintered). The sintered body that is sintered by utilizing the low temperature fusion phenomenon of nano Ag does not melt up to the melting point of the bulk material.
  • Non-Patent Document 1 a power semiconductor module using nano Ag as a die bond material is the same as the case of using solder as a die bond material based on the result of a heat cycle test in which cooling to -40°C and heating to 125°C are repeated. It is said that some degree of reliability can be obtained.
  • the secondary particles grown from the nano Ag particles are not sintered, and there are clear grain boundaries and voids of the nanoparticles inside. Therefore, sufficient strength cannot be obtained, and a heat cycle test reaching 300° C. tends to cause deterioration starting from a grain boundary. Therefore, it is difficult to use as a die-bonding material for joining semiconductor devices whose maximum operating temperature reaches 300°C.
  • Non-Patent Document 2 there are problems that it is difficult to thicken the die bond and the bonding strength is unstable.
  • the price of nano Ag powder is 100 times or more that of ordinary powder. This is several times more expensive than Au solder and extremely expensive.
  • Non-Patent Document 2 proposes that an AgSn alloy produced by sintering a mixture of Ag and Sn powders at a load of 5 MPa by utilizing a low temperature fusion phenomenon is used as a die bond.
  • This sintered body contains a large amount of Ag 3 Sn, and voids are reduced.
  • this AgSn alloy has a low thermal conductivity of about 70 W/mK. This is slightly higher than the thermal conductivity of Sn solder (about 60 W/mK).
  • Ag 3 Sn aggregates at the grain boundaries. It is said that this AgSn alloy has a high die shear strength (bonding strength between a semiconductor device and an electrode substrate), but when a heat cycle test is performed, Ag 3 Sn aggregated at grain boundaries causes die bond deterioration.
  • the problem to be solved by the present invention is to provide a semiconductor device bonding member that can be used for bonding a semiconductor device including a semiconductor element whose maximum operating temperature reaches 300° C. and a substrate such as an electrode substrate.
  • the thermal conductivity of the die bond of the semiconductor device whose maximum operating temperature is 150°C (the thermal conductivity of solder is 60 W/mK It is required to have a thermal conductivity more than twice that of the following), that is, a thermal conductivity of 120 W/m ⁇ K or more.
  • the heat resistance temperature of the die bond is preferably 500° C. or higher in order to ensure reliability during operation.
  • the electric conductivity is preferably 50% IACS or more.
  • the linear expansion coefficients of the main materials constituting semiconductor devices are 4.1 ppm/K for Si, 4.5 ppm/K for SiC, and 3.2-5.6 ppm/K for GaN, which are all small.
  • Cu which is a typical electrode material, has a high thermal conductivity of 17 ppm/K. Therefore, the die bond for joining the semiconductor device and the electrode substrate must be capable of relieving a large thermal stress generated during the operation of the semiconductor device due to the difference in linear expansion coefficient between the two.
  • the thickness of the die bond is preferably 0.01 mm or more and 0.3 mm or less.
  • the joining of the semiconductor devices must be performed at a temperature and a load that do not damage the semiconductor devices.
  • Some of the conventional joining examples have been reported to reach a peak temperature of about 450°C during joining.
  • the maximum temperature at the time of bonding is preferably 350°C or lower.
  • the limit value of the pressure applied to the semiconductor device mounted on the IGBT module the maximum value of the pressure that does not cause the destruction of the semiconductor device
  • no specific value has been reported, but it is applied when the semiconductor device is bonded.
  • the pressure applied is preferably less than 5 MPa.
  • low temperature and low load are not always preferable, and it is necessary to determine the temperature and load so that the semiconductor device and the electrode substrate are bonded with sufficient strength.
  • These conditions differ depending on the material to be joined, the joining method, and the joining apparatus, and there are optimum conditions for each, but most of them are know-how, and manufacturers rarely present detailed joining conditions.
  • the low-temperature fusion phenomenon referred to here is that Sn is melted and reacted with Ag at a temperature lower than Ag of the bulk material.
  • a method utilizing this low temperature fusion phenomenon is hereinafter referred to as "low temperature low pressure fusion reaction joining method".
  • the low-temperature low-pressure fusion reaction joining method referred to here is different from the low-temperature fusion phenomenon caused by the surface activity of particles as seen in nano Ag.
  • the melting point of Ag is 961°C
  • the melting point of Sn is 232°C
  • the melting point of Cu is 1083°C. Therefore, the bonding temperature can be lowered by appropriately changing the content ratio of these.
  • the thermal conductivity greatly decreases.
  • heat of Ag 3 Sn alloy of 60Ag40Sn (Ag content: 60 weight percent, Sn content: 40 weight percent) produced by a pressure sintering method. It has a low conductivity of 70 W/mK, which is far from the thermal conductivity of BAg-18 (215 W/mK).
  • the thermal conductivity of 60Ag40Sn produced by the melting method is as low as 83 W/mK.
  • the thermal conductivity of 90Ag10Sn was 310 W/mK, which was extremely high.
  • Samples 1 to 10 in which a die bond having a thickness of 0.2 mm was formed between the SiC semiconductor device and the electrode were prepared by placing the SiC semiconductor device and the electrode under a pressure of 1 MPa or 5 MPa at 300° C. for 10 minutes in a vacuum atmosphere. Then, in order to confirm the suitability of use in the mounted state, each remelting temperature was measured, and subsequently, a heat cycle test was performed to judge the pass/fail. Then, the reliability of Samples 1 to 10 was confirmed from the results of the remelting temperature and the heat cycle test. Table 1 shows the compositions of Samples 1 to 10, the pressurization conditions, the remelting temperature, and the results of the heat cycle test.
  • the present invention obtained from the above study is a semiconductor device joining member for joining a joined surface of a semiconductor device and a joined surface of a substrate on which the semiconductor device is mounted, Ag, Cu, and at least one of Au and Sn as a main component, including a layer made of an alloy having a melting point of 500 °C or more, Inside, having a plurality of voids having a total volume of 5% or more and 40% or less, Characterized by having a thermal conductivity of 120 W/mK or more and an electrical conductivity of 50% IACS or more after 300 heat cycle tests in which cooling to -40°C and heating to 300°C are repeated. ..
  • the semiconductor device joining member according to the present invention is a member arranged between the joining surfaces of the semiconductor device and the substrate in order to join the joining surfaces.
  • the semiconductor device bonding member according to the present invention contains at least one kind of Ag, Cu, and Au and Sn as a main component, and includes a layer made of an alloy having a melting point of 500° C. or higher, and therefore, the It has sufficient heat resistance as a material for bonding semiconductor devices whose temperature is 300°C or higher.
  • the semiconductor device bonding member according to the present invention has a plurality of voids having a total volume of 5% or more and 40% or less of the whole inside thereof, and these voids allow deformation of the semiconductor device bonding member.
  • the thermal stress caused by the difference in linear expansion coefficient between the semiconductor device and the substrate such as the electrode substrate is relaxed.
  • the effect of relieving the thermal stress largely depends on the amount of voids. If the proportion of voids is less than 5 volume percent, the effect of relaxing the thermal stress is not sufficient, and if it exceeds 40 volume percent, the material itself tends to break.
  • the shape and number of voids may be appropriately determined according to the use environment and manufacturing process of the object to be joined, but the guideline for the size of one void is, for example, when the voids are approximated to spheres of the same volume.
  • the diameter is 0.005 mm or more and 3 mm or less. If it is smaller than 0.005 mm, it is difficult to obtain the effect of relieving stress. If it is larger than 3 mm, the thermal resistance tends to increase at the position of the void.
  • the size of one void is more preferably 0.2 mm or more and 2 mm or less.
  • the size and distribution of the voids only need to satisfy the above requirement that the total volume of the plurality of voids be 5% or more and 40% or less of the whole, and need not necessarily be uniform over the entire semiconductor device bonding member. Absent. For example, it may have a layer having a high porosity at the center of the member and a layer having a low porosity (or almost no voids) on its front and back surfaces. Conversely, it may have a layer having a low porosity (or almost no voids) in the center of the member and a layer having a high porosity on the front and back surfaces thereof. Alternatively, the front and back surfaces may have different porosities.
  • the thermal conductivity is 120 W/mK or more, and the electrical conductivity is 50% IACS or more, The heat generated during the operation of the semiconductor device can be efficiently released, and excessive Joule heat is not generated in the semiconductor device joining member. Since the semiconductor device bonding member according to the present invention has these characteristics, it can be used for bonding a semiconductor device whose maximum temperature during operation reaches 300° C. and a substrate on which the semiconductor device is mounted.
  • the content of Sn in the layer made of the above alloy is 2% by weight or more and 20% by weight or less.
  • Non-Patent Document 2 an AgSn alloy containing a large amount of Ag 3 Sn (for example, occupying 50% by volume of the whole) is produced, whereas in the semiconductor device bonding member according to the present invention, Ag contained in the layer made of the alloy is Ag.
  • the ratio of 3 Sn is 10 volume% or less. More preferably, the proportion of Ag 3 Sn is 5 volume% or less, and even more preferably 3 volume% or less.
  • the presence of eutectic at grain boundaries is likely to be the origin of cracks. By setting the Sn content in the above range, it becomes difficult for eutectic to exist at the grain boundaries. Thereby, generation of cracks can be suppressed and durability can be improved.
  • the semiconductor device bonding member according to the present invention it is possible to bond a semiconductor device having a maximum operating temperature of 300° C. and an electrode substrate or the like on which the semiconductor device is mounted. Moreover, in the semiconductor device bonding member according to the present invention, expensive nano Ag is not necessarily used. Furthermore, the technology and equipment cultivated up to now for soldering can be used.
  • voids In solder, when 5% or more of voids (voids) are present, the voids become the starting point in the heat cycle test, and cracks are chained and broken in the low-strength, brittle eutectic alloy existing in the grain boundaries. .. Further, in the AgSn alloy containing a large amount of Ag 3 Sn as described in Non-Patent Document 2, the void ratio is small, but in the heat cycle test, the void is the starting point, and Ag 3 Sn with low strength existing at the grain boundary is present. Cracks are chained to break the part of the eutectic alloy.
  • the primary particles are sintered at a temperature lower than the melting point of Ag of the bulk material, but the secondary particles formed by sintering do not sinter unless the temperature is 400° C. or higher, so a grain boundary is formed, A void occurs there.
  • the voids become the starting points in the heat cycle test, and the cracks of the secondary particles having low strength are chained and destroyed.
  • fracture due to cracking of Ag 3 Sn eutectic alloy and secondary particles occurs even in the absence of voids.
  • a semiconductor device or an electrode substrate is joined by a low-temperature low-pressure melting reaction joining method using Ag and Sn, and high heat conductivity and heat resistance are secured by Ag, AgSn alloy, etc. Then, the thermal stress is relaxed by the voids, and the spread of cracks originating from the voids is suppressed by using Ag, AgSn alloy or the like.
  • the present invention is based on the idea opposite to the conventional material development of eliminating defects such as voids, so that the voids do not become the origin of defects by surrounding the voids with a highly heat-resistant and strong material. By doing so, the voids are used for relaxing the thermal stress.
  • the semiconductor device joining member according to the present invention is as described above, but its technical idea can be generalized. Specifically, the technical idea of the present invention is to provide a semiconductor device joining member for joining a joined surface of a semiconductor device and a joined surface of a substrate on which the semiconductor device is mounted, An alloy containing a first metal and a second metal having a melting point lower than that of the first metal as main components, a content of the second metal of 2% by weight or more and 20% by weight or less, and a melting point of 500° C. or more.
  • the thermal conductivity is 120W/mK or more and the electrical conductivity is 50%IACS or more after the heat cycle test in which cooling to -40°C and heating to 300°C are repeated 300 times.
  • the semiconductor device bonding member 10 of this embodiment is a so-called die bond, and is used for bonding the semiconductor device 11 to a substrate such as the electrode substrate 12 as schematically shown in FIG.
  • the semiconductor device bonding member 10 of the present embodiment is one in which voids (voids) 102 are provided at a predetermined ratio inside a skeleton 101 made of an alloy or the like. Note that, in FIG. 1, the structure of the semiconductor device bonding member 10 in the case of being manufactured by introducing the second metal into the through hole provided in the plate material of the first metal, that is, an example in which the voids 102 are arranged in the vertical direction of the drawing.
  • the voids 102 may be randomly located inside the skeleton 101.
  • the size and shape of the voids need not be constant.
  • the voids (voids) 102 do not necessarily have to be evenly distributed over the entire semiconductor device bonding member 10. For example, if there is a place where stress tends to increase during operation, many voids are concentrated in that place. It may be arranged in a desired manner. Further, it may be a stack of a layer containing many voids and a layer containing few voids (or few voids).
  • the above-mentioned low-temperature low-pressure melting reaction joining method can be preferably used for producing the alloy forming the skeleton 101 of the semiconductor device joining member 10.
  • a powder method or a skeleton method can be used.
  • an appropriate method can be used as long as a semiconductor device bonding member satisfying the requirements of the claims can be manufactured.
  • the first metal is, for example, one or more of Ag, Cu, Au, and alloys thereof.
  • a metal having a high melting point, a high thermal conductivity, and a high electrical conductivity is used as the first metal.
  • a metal in which an intermetallic compound is less likely to be formed by a reaction with a second metal (Sn or the like) is used.
  • Ag can be preferably used as the first metal.
  • Cu the amount of Ag used can be reduced and a semiconductor device bonding member can be manufactured at low cost. It is also possible to use Au, or an alloy of Ag, Cu, and Au.
  • the second metal melts and reacts with the first metal to alloy at low temperatures. Sn can be preferably used for the second metal.
  • the ratio of the second metal is preferably in the range of 2% by weight or more and 20% by weight or less of the semiconductor device joining member to be obtained, although it varies depending on the temperature and pressure applied during the production of the semiconductor device joining member. As a result, no problem occurs in the heat cycle test, and the required characteristics can be obtained.
  • the first metal is Ag and the second metal is Sn
  • the Sn content reacted with Ag is reduced to 20% by weight or less
  • the formation of a eutectic substance composed of Ag 3 Sn is suppressed.
  • the presence of eutectic at grain boundaries is likely to cause cracking.
  • the Sn content is less than 2% by weight, it is difficult to disperse the Sn uniformly, so that the temperature at the time of joining with a semiconductor device or the like tends to vary.
  • the junction temperature may exceed 450° C. (the temperature at which the semiconductor device may be destroyed) at the position where Sn does not exist.
  • one or more of Cu, Ag, Pb, Cd, Zn, Sb, Ni, Mn, Ti, In, Mo, Si, V, Ge and Li are added metals. May be further included.
  • One of the members to be joined is a semiconductor device, and the other is a substrate (for example, an electrode substrate) on which the semiconductor device is mounted.
  • a metal layer made of Ni, Pt, Co or the like is provided on the joint surface.
  • An IGBT module often has a Ni layer with a thickness of about 2 ⁇ m.
  • a metal layer made of Ti, W, Co or the like may be provided on the bonding surface of the electrode substrate or the heat dissipation substrate.
  • a metal layer made of Ni, Pt, Co or the like may be provided in order to prevent reaction with the Ag brazing material.
  • electrolytic Ni plating which is a Ni-based plating, electroless Ni-P, Ni-B, or the like is used.
  • one or more plating layers of Ag, Au, Cu, Zn, etc. may be provided on each of the above layers.
  • electrodes made of thin Ni-based metal may be placed on the front and back surfaces of the semiconductor device, and in that case, such electrodes are called a semiconductor device.
  • a layer made of Au, Ag, Cu, a metal such as Sn, or an alloy thereof may be provided, and in that case, a semiconductor device including this layer is also included. be called. That is, it can be construed as a semiconductor device in a broad sense, including a layer integrally formed with the semiconductor device before being bonded to the electrode substrate.
  • a protruding auxiliary electrode may be provided on the surface to be joined of the electrode substrate.
  • Such an auxiliary electrode is attached to a flat plate such as Cu by a brazing material or a die bonding material.
  • Such an auxiliary electrode may also be provided with a Ni-based plating layer for improving the bondability with a semiconductor device, or a layer made of a metal such as Au, Ag, Cu, Sn, or an alloy thereof. In that case, including these layers, it is called an electrode substrate. That is, it can be interpreted as an electrode substrate in a broad sense, including a layer integrally formed with the electrode substrate before being bonded to the semiconductor device.
  • the Ag layer formed on the surface to be joined of the semiconductor device to enhance the joining property is a part of the semiconductor device, and the layer formed by alloying Ag and Sn contained in the Ag layer is the semiconductor device joining. It can be interpreted as being part of a member.
  • the metal disposed on the surface layer of DBC or DBA is a part of the electrode substrate, and the layer formed by alloying the metal and Sn can be interpreted as a part of the semiconductor device bonding member. it can.
  • One of the methods for producing the semiconductor device joining member 10 is a powder method. This is a method in which a mixture of Ag and Sn powders or a powder obtained by Sn-plating Ag particles is sintered and bonded to a member to be bonded (semiconductor device or electrode substrate).
  • the other is the skeleton method. This has a void by making a plate material made of AgSn alloy with less Ag or Ag 3 Sn in a sintered body, or by subjecting the plate material to laser processing, drill processing, etching processing, punching processing, reticulation processing, etc.
  • the skeleton is made in advance, and the skeleton is made to react with Ag by impregnating the skeleton with molten Sn or the like, and is joined to a member to be joined (semiconductor device or electrode substrate). Further, the powder method and the skeleton method may be appropriately combined. In addition, for the reaction between the first metal and the second metal, a suitable method such as a sintering method, an impregnation method, or a partial reaction joining method may be used.
  • the powder method it is possible to use, for example, particles with a particle size in the range of 10 nm to 0.3 mm.
  • the powder used may have a uniform size, or may be a mixed powder having different particle sizes.
  • the skeleton may be produced by an appropriate method such as a sintering method. Although details of the manufacturing method will be described later, for example, a skeleton containing voids can be manufactured by heating and sintering at 750° C. or higher in vacuum, hydrogen+nitrogen, and hydrogen atmosphere.
  • a plate-shaped product When using a plate-shaped product, it is possible to use, for example, a product having a thickness of 0.02 to 0.3 mm.
  • a plate-shaped member When a plate-shaped member is used, holes having a size and number corresponding to the void ratio to be formed inside the semiconductor device bonding member to be obtained are formed.
  • the low temperature and low pressure conditions are not always optimal for joining semiconductor devices and the like by die bonding. It is necessary to secure the performance and quality suitable for the composition of the die bond and the target semiconductor module.
  • the pressure sintering infiltration method uses a mixed powder of Ag, Sn, etc., or an Ag plate with holes formed in advance, and melts Sn and alloys while pressurizing, while joining the semiconductor device and the cooler. is there.
  • the melting reaction method the semiconductor devices and electrode substrates are joined while melting and alloying Sn arranged above and below the skeleton of Ag, and the target can be achieved with a low pressure.
  • the Ag plate Sn reaction method is a semiconductor device in which one or more Ag plates or Ag nets having holes are arranged on top and bottom of a layered one, and the Sn is melted and reacted with Ag to form an alloy. And an electrode substrate. This gives the highest strength AgSn alloy. Further, the target can be achieved with a low pressure.
  • one or more plating layers made of Ag or/and Sn may be provided on the surface of the prepared alloy.
  • a layer made of an alloy is formed on the front surface and the back surface of the semiconductor device bonding member, and a layer having a high porosity made of only Ag can be formed in the central portion sandwiched between them.
  • Each of the above methods can be used as the above-mentioned low temperature low pressure fusion reaction joining method.
  • a plate material of the second metal is arranged above and below the skeleton, or the surface of the skeleton is plated with a second metal.
  • the second metal can be arranged.
  • the powdery first metal is used, the powder of the first metal and the powder of the second metal may be mixed and sintered to produce a skeleton of the mixed powder.
  • the second metal and the first metal can be effectively impregnated with Sn. In this case, the entire semiconductor device bonding member is likely to be alloyed.
  • the second metal may be plated on the bonding surface of the semiconductor device and/or the bonding surface of the substrate (electrode substrate or the like), and they may be arranged above and below the skeleton. Even if one or a plurality of plating layers made of Ni, Ag, Ti or the like are formed on the bonding surface of the semiconductor device and/or the bonding surface of the substrate before the second metal is plated on the bonding surface. Good. In particular, by forming the Ni plating layer, the bondability with the AgSn alloy can be improved.
  • the first metal When the dissolved second metal enters the hole of the first metal, the first metal gradually dissolves from the surface of the hole, and the second metal is impregnated inside the skeleton of the first metal. Similarly, on the surface of the skeleton, the first metal gradually dissolves and is impregnated with the second metal.
  • pressure may be applied. On the other hand, if excessive pressure is applied, the semiconductor element may be damaged, so the applied pressure is preferably less than 5 MPa, more preferably 0.5 to 4.0 MPa.
  • the second metal melted by the impregnation reacts with the first metal forming the skeleton to be alloyed, whereby the semiconductor device and the electrode substrate are die-bonded with high strength. Also, when the mixed powder of the first metal and the second metal is used, the second metal is melted to be alloyed, whereby the semiconductor device and the electrode substrate are die-bonded with high strength.
  • the melting point of the alloy layer included in the semiconductor device joining member is 500° C. or higher because heat may be locally generated during the operation of the semiconductor device. Also, in the case of AgSn alloy, brittle Ag 3 Sn particles agglomerate at grain boundaries in alloys with a melting point of 500°C or lower, causing damage such as cracks and chips in the heat cycle test, and lowering properties such as thermal conductivity.
  • Die bonding can be performed in a vacuum atmosphere, non-oxidizing atmosphere, nitrogen atmosphere, hydrogen atmosphere, hydrogen nitrogen atmosphere.
  • the melting point of Sn is 235° C.
  • the re-melting point of AgSn alloy becomes 500° C. or higher by reacting with Ag to form an alloy.
  • the thermal conductivity of the semiconductor device bonding member (die bond) included in the test piece was obtained by comparing the thermal conductivity of the test piece with the thermal conductivity of the SiC comparative piece and the Cu comparative piece.
  • a thermal conductivity of 120 W/m ⁇ K was used as a standard, and one having a thermal conductivity of more than this was regarded as a pass.
  • a laser processing machine is used to cut out a test piece with a diameter of 10 mm and a thickness of 2.0 mm, and the electrical conductivity is measured by the four-terminal method using an electrical conductivity measuring device (RT70V manufactured by Napson Corporation). did. Separately from this test piece, a W comparison piece (having a Ni plating layer on one side) and a Cu comparison piece (having a Ni plating layer on one side) having a diameter of 10 mm and a thickness of 2.0 mm were prepared. The electrical conductivity was measured in the same manner as above. Then, the electrical conductivity of the test piece was determined by comparing the electrical conductivity of the test piece with the electrical conductivity of the W comparative piece and the Cu comparative piece.
  • Example 1 The value of each parameter is the value related to Example 2.
  • Examples 1 and 3 to 15 were produced by appropriately changing the parameter values as shown in Table 2 below.
  • Step 1 A 12 mm square Ag plate material having a thickness of 0.2 mm and one through hole having a diameter of 0.36 mm per 1 mm square was formed by laser processing (hereinafter referred to as a skeleton).
  • Process 2 A 30 ⁇ m square, 1.5 mm thick Cu plate material was provided with a 2 ⁇ m thick Ni plating layer on one surface (joint surface), and a 12 mm square, 0.009 mm thick Sn plating layer was provided in the center thereof. The thing (henceforth this is called an electrode substrate) was produced.
  • Process 3 12 mm square, a 2 ⁇ m-thick Ni plating layer is provided on one surface (bonding surface) of the SiC plate material, and a 0.009 mm-thick Sn plating layer is further provided thereon (hereinafter referred to as a semiconductor device. Called a plate).
  • Step 4 A laminated body was produced in which the electrode substrate, the skeleton, and the semiconductor device plate were sequentially stacked.
  • Step 5 The laminate was heated to 300° C. in a vacuum atmosphere, kept at 300° C., a pressure of 1 MPa was applied, kept for 5 minutes and gradually cooled.
  • Step 6 A heat resistance test, a heat cycle test, a measurement of thermal conductivity, and a measurement of electrical conductivity were performed on the semiconductor device plate and the electrode substrate joined by the above treatment.
  • Example 1 the void ratio is 5 vol% and the Sn content is 3.7 wt% (5 vol%).
  • the weight is 1.888 ⁇ g (Ag density: 10.49g/cm -3 ).
  • the total volume of Ag and Sn is 0.19 mm 3 , and the total weight is 1.961 ⁇ g.
  • a 10% void is formed on a plate material with a 1 mm square and a thickness of 0.2 mm. It can be seen that it is sufficient to form a 0.005 mm thick Sn layer. If the voids formed in the plate material are approximated to cylindrical through holes, it is understood that one through hole having a diameter of 0.36 mm should be provided for each 1 mm square.
  • the skeleton of Example 9 (AgCu described in Table 2) is an alloy containing 30% by weight of Ag and 70% of Cu.
  • the ratio of the voids is determined in advance, and the size of the material to be used and the size of the through-hole to be formed in advance are determined.
  • the voids (voids) of the semiconductor device bonding member after creation are determined. The ratio of can be evaluated by various measurements.
  • the cross section of the semiconductor device bonding member is photographed by an electron microscope or the like, and the ratio of the voids included in the semiconductor device bonding member is evaluated by using the ratio of the voids appearing in the cross section as a representative value.
  • the ratio of voids included in the semiconductor device bonding member can be evaluated from the theoretical density of the non-alloy and the density of the manufactured semiconductor device bonding member.
  • Table 2 shows the produced Examples 1 to 15 and their evaluation results, and the Comparative Examples 1 to 9 produced for comparison and their evaluation results.
  • Comparative Example 1 the semiconductor device and the electrode substrate could not be joined, and in Comparative Example 6, the powder was not sintered, so that neither test piece could be produced.
  • Comparative Examples 2 to 5 and 7 to 9 test pieces could be produced, but when the temperature was raised to 500° C., melting was observed in the joint portion, and therefore the heat cycle test was not performed.
  • the thermal conductivity after the heat cycle test was 120 W/m ⁇ K or more, and the electrical conductivity was 50%. More than IACS.
  • the semiconductor device bonding member of each of the above-described embodiments satisfies the requirements required when bonding a semiconductor device having a maximum operating temperature of 300° C. to a substrate.
  • voids inside semiconductor device bonding members have been considered to be defects, and void-free materials have been developed, but the present invention has found that voids are effective in alleviating thermal stress. ..
  • this semiconductor device joining member can be suitably used when a semiconductor device is joined to an electrode substrate to conduct electricity in a vertical conduction type IGBT which is a power semiconductor module. Further, it can be suitably used also for bonding a semiconductor device to a heat dissipation board (non-energized) in a module in the other plane conduction type semiconductor fields (communication, arithmetic, memory, laser, LED, sensor, etc.). .. Further, not only the SiC semiconductor device but also the IGBT module having a semiconductor device such as Si, GaN or GaAs mounted thereon can be suitably used.
  • the semiconductor device bonding member according to the present invention can be preferably used.
  • INDUSTRIAL APPLICABILITY The semiconductor device joining member according to the present invention can greatly contribute to future miniaturization and high performance of semiconductor modules and cost reduction. Further, energy saving can be realized by using the above semiconductor module in an electric vehicle or an industrial machine. In the specification of the present application, the semiconductor module has been mainly described.
  • a semiconductor package (a terminal that serves as a contact for wrapping a semiconductor element or an integrated circuit with resin or the like to protect it from the surroundings and inputting and outputting electric power and electric signals)
  • the semiconductor device joining member according to the present invention can be preferably used for a packaging member provided with or wiring.

Abstract

This semiconductor device joining member 10 is used to join a to-be-joined surface of a semiconductor device 11 and a to-be-joined surface of a substrate 12 on which said semiconductor device 11 is to be placed, includes a layer comprising an alloy 102 that contains, as main components, Sn and at least one selected from among Ag, Cu, and Au, and has a melting point of at least 500°C. The inside of said joining member has a plurality of voids 101, the volume of which accounts for 5-40% of the total volume of the joining member. The joining member is configured to have a thermal conductivity of at least 120 W/m·K and an electrical conductivity of at least 50% IACS after having undergone a heat cycle test in which a cycle of cooling to -40°C and heating to 300°C is repeated 300 times.

Description

半導体デバイス接合部材Semiconductor device bonding material
　本発明は、半導体デバイスと基板とを接合するために用いられる半導体デバイス接合部材に関する。 The present invention relates to a semiconductor device joining member used for joining a semiconductor device and a substrate.
　近年、HV（Hybrid Vehicle）車に続き、世界各国で電気自動車（EV: Electric Vehicle）が普及しつつある。こうしたなか、SiC半導体デバイスを使用した小型、高性能、かつ安価な絶縁ゲートバイポーラトランジスタ（IGBT: Insulated Gate Bipolar Transistor）モジュールの研究開発が進められている。 In recent years, following the HV (Hybrid Vehicle) vehicle, electric vehicles (EV: Electric Vehicle) are becoming popular in countries around the world. Under these circumstances, research and development of small, high-performance, and inexpensive insulated gate bipolar transistor (IGBT) modules using SiC semiconductor devices are underway.
　第1世代のIGBTモジュールでは、当初、絶縁回路基板としてDBC（Direct Bonded Cupper。絶縁性のセラミック基板に、導電性の優れたCuを回路層として接合したもの。）が検討されたが、より厳しい使用環境で使用することが可能なDBA（Direct Bonded Aluminum。セラミック基板に、導電性の優れたAlを回路層として接合したもの。）が用いられるようになった。その後、放熱基板とサーマルグリスを省略し、DBAと冷却器をAlパンチングメタルで接合した構造を採ることで、第1世代のIGBTモジュールに比べて熱抵抗を30％低減した第2世代のIGBTモジュールが実用化された。第1世代のIGBTモジュール及び第2世代のIGBTモジュールのように、半導体デバイスの片面に放熱経路（以下、「熱路」という。）を設ける構造は、片面冷却構造と呼ばれる。 For the first-generation IGBT module, initially a DBC (Direct Bonded Cupper; an insulating ceramic substrate joined with Cu with excellent conductivity as a circuit layer) was considered as the insulating circuit substrate, but it was more severe. DBA (Direct Bonded Aluminum, which has a highly conductive Al joined as a circuit layer to a ceramic substrate.) that can be used in the usage environment has come to be used. After that, by omitting the heat dissipation board and thermal grease, and adopting a structure in which the DBA and the cooler are joined with Al punching metal, the second-generation IGBT module reduces thermal resistance by 30% compared to the first-generation IGBT module. Was put to practical use. A structure in which a heat dissipation path (hereinafter, referred to as “heat path”) is provided on one surface of a semiconductor device, like the first-generation IGBT module and the second-generation IGBT module, is called a single-sided cooling structure.
　第3世代のIGBTモジュールは、半導体デバイスの両面にCu薄板をハンダ付けした両面冷却構造を有しており、Si4N3セラミック（以下、「SINセラミック」と記載する。）により半導体デバイスが絶縁され、絶縁樹脂接着剤（絶縁グリス）により冷却器と接合される。こうした新しい構造を採ることにより、第1世代のIGBTモジュールに比べて熱抵抗を65％低減し、第2世代のIGBTモジュールに比べて熱抵抗を50％低減した、優れた冷却性を有するIGBTモジュールが実用化された。 The 3rd generation IGBT module has a double-sided cooling structure in which Cu thin plates are soldered on both sides of the semiconductor device, and the semiconductor device is insulated by Si 4 N 3 ceramic (hereinafter referred to as “SIN ceramic”). Then, it is joined to the cooler with an insulating resin adhesive (insulating grease). By adopting such a new structure, the thermal resistance of the IGBT module is reduced by 65% compared to the 1st generation IGBT module, and the thermal resistance is reduced by 50% compared to the 2nd generation IGBT module. Was put to practical use.
　第3世代のIGBTモジュールで用いられる、半導体デバイスからの放熱経路は、電極基板、SINセラミックの板材、及び冷却器のラジエータを接合した簡素な構成のものである。半導体デバイスと電極基板等の基板の接合は、ダイボンディング（あるいはダイアタッチ、チップボンディング）と呼ばれる。また、ダイボンディングに用いられる材料はダイボンド材料と呼ばれる。電極基板、SINセラミックの板材、及び冷却器のラジエータは絶縁樹脂接着剤（絶縁グリス）で接合される。これらの部材で構成される熱路は両面冷却構造と片面冷却構造を問わず使用可能であることから、IGBTモジュールの熱路として将来にわたって広く用いられるものと考えられる。 The heat radiation path from the semiconductor device used in the 3rd generation IGBT module has a simple structure in which the electrode substrate, the SIN ceramic plate material, and the radiator of the cooler are joined. Bonding of a semiconductor device and a substrate such as an electrode substrate is called die bonding (or die attachment or chip bonding). The material used for die bonding is called a die bond material. The electrode substrate, the SIN ceramic plate material, and the radiator of the cooler are joined with an insulating resin adhesive (insulating grease). Since the heat path composed of these members can be used for both double-sided cooling structure and single-sided cooling structure, it is considered to be widely used in the future as a heat path for IGBT modules.
　本発明者は、IGBTモジュールにおける放熱効率を高めるべく、Cu電極の熱抵抗を低減した（Cuよりも熱伝導率が高い）、金属とダイヤモンドを主成分とする放熱電極基板を提案している（特許文献１）。また、放熱基板や電極と冷却器を接合するために用いられる高熱伝導性絶縁樹脂複合部材も提案している（特許文献２）。この高熱伝導性絶縁樹脂複合部材は、ダイヤモンドやセラミックを絶縁樹脂材料中に配置してなる主層と、該主層の表裏面に配置した保護接合層を有している。従来の樹脂接着剤とセラミックからなる絶縁部材に代えて、この高熱伝導性絶縁樹脂複合部材を用いることにより、熱抵抗を大幅に低減することができる。 The present inventor has proposed a heat dissipation electrode substrate containing a metal and diamond as main components, in which the thermal resistance of the Cu electrode is reduced (the thermal conductivity is higher than Cu) in order to improve the heat dissipation efficiency in the IGBT module ( Patent Document 1). Further, a high thermal conductive insulating resin composite member used for joining a heat dissipation substrate or an electrode to a cooler is also proposed (Patent Document 2). This high thermal conductive insulating resin composite member has a main layer in which diamond or ceramic is placed in an insulating resin material, and protective bonding layers placed on the front and back surfaces of the main layer. By using this high heat conductive insulating resin composite member in place of the conventional insulating member made of a resin adhesive and ceramic, the thermal resistance can be significantly reduced.
国際公開第２０１８／１９００２３号International Publication No. 2018/190023 特許第６３８４９７９号公報Japanese Patent No. 6384979
　特許文献１及び２において本発明者が提案した放熱基板及び高熱伝導性絶縁樹脂複合部材を用いることによりIGBTモジュールにおける熱路の熱抵抗が低減される。しかし、主要な熱路には、これらのほか、半導体デバイスと基板（例えば電極基板）を接合するダイボンドも含まれる。最高動作温度が300℃に達する半導体デバイスを搭載してIGBTモジュールを更に小型化及び高性能化するには、ダイボンド材料の熱抵抗を低減する必要がある。また、半導体デバイスの動作時の信頼性も求められる。 The thermal resistance of the heat path in the IGBT module is reduced by using the heat dissipation substrate and the high thermal conductive insulating resin composite member proposed by the present inventors in Patent Documents 1 and 2. However, in addition to these, the main heat path also includes a die bond for joining a semiconductor device and a substrate (for example, an electrode substrate). The thermal resistance of the die bond material must be reduced in order to further reduce the size and improve the performance of the IGBT module by mounting the semiconductor device whose maximum operating temperature reaches 300°C. Further, reliability during operation of the semiconductor device is also required.
　従来のIGBTモジュールでは、最高動作温度が150℃程度であるSi半導体デバイスがDBAに搭載されている。半導体デバイスの材料であるSiの線膨張係数は4.5ppm/Kである。また、DBAの線膨張係数は7ppm/Kである。従来、半導体デバイスと絶縁回路基板を接合するダイボンドの材料として柔らかいハンダを用いることによって、半導体デバイスの動作時に生じる、半導体デバイスと絶縁回路基板の線膨張係数の差に起因する熱応力を緩和している。 In the conventional IGBT module, the DBA is equipped with a Si semiconductor device with a maximum operating temperature of about 150°C. The coefficient of linear expansion of Si, which is the material for semiconductor devices, is 4.5 ppm/K. The linear expansion coefficient of DBA is 7 ppm/K. Conventionally, by using a soft solder as a material of a die bond that joins a semiconductor device and an insulating circuit board, thermal stress caused by a difference in linear expansion coefficient between the semiconductor device and the insulating circuit board, which occurs during operation of the semiconductor device, is relaxed. There is.
　このように、従来、半導体デバイスと電極基板は、溶融させたハンダで接合（溶融接合）されている。こうして形成したハンダのダイボンドは、外周のハンダのメニスカス状態を確認したり、ハンダの内部をX線や超音波により測定することによってボイド等の欠陥を確認したりすることで信頼性が確保できることから、長く用いられてきた。ハンダのメニスカス状態とは、ハンダが接合部の外周に流れ出た状態をいう。 In this way, conventionally, semiconductor devices and electrode substrates have been joined (melted) with molten solder. The reliability of the die bond of the solder thus formed can be ensured by confirming the meniscus state of the solder on the outer periphery and confirming defects such as voids by measuring the inside of the solder with X-rays or ultrasonic waves. , Has been used for a long time. The meniscus state of the solder means a state in which the solder flows to the outer periphery of the joint.
　電極での冷却性を向上するために、熱伝導率が高いCuの大型の電極基板を半導体デバイスに接合した場合、Cuの線膨張係数は17ppm/Kであることから、Siの半導体デバイスとCu電極の線膨張係数差が12.5ppm/Kと大きくなり、ダイボンドが破壊する。また、一方、DBCを使用しても熱応力が集中する部分でCu電極の剥離やセラミックの破壊が起こる。そのため、最高動作温度が高くなるとハンダ等のダイボンド材料では両者の間に生じる熱応力を緩和することが難しくなる。 When a large Cu electrode substrate with high thermal conductivity is bonded to a semiconductor device in order to improve the cooling performance at the electrode, the linear expansion coefficient of Cu is 17 ppm/K. The difference in the linear expansion coefficient of the electrodes increases to 12.5 ppm/K, and the die bond breaks. On the other hand, even if DBC is used, peeling of the Cu electrode and destruction of the ceramic occur at the portion where the thermal stress is concentrated. Therefore, when the maximum operating temperature becomes high, it becomes difficult for the die bond material such as solder to relax the thermal stress generated between them.
　ここで、従来用いられている代表的なハンダや他の接合材のいくつかを概説する。 Here, we will outline some of the typical solders and other jointing materials that have been conventionally used.
（Sn系ハンダ）
　車載用のIGBTモジュールでは、Pbフリーである、Sn系のハンダ（Snを主成分とするハンダ）、例えばSnCu系（融点228℃）、SnAg系（融点221℃）、SnAgCu系（融点219℃）、SnSb系（融点240℃）のハンダが用いられている。また、これらのSn系のハンダにNiボールを充填してダイボンドの厚さを調整したものも用いられている。しかし、これらのいずれも、融点が300℃未満である。また、熱伝導率が60W/m・K以下と低い。さらに、電気伝導率も25%IACS以下と極めて低い。この値は、電気炉で発熱材として用いられるWの電気伝導率30%IACSより低い。なお、IACS（International Annealed Copper Standard）とは、焼鈍標準軟銅(体積抵抗率: 1.7241×10-2μΩm)の電気伝導率を100%IACSとして、各種材料の電気伝導率を表したものである。Snの融点は234℃、熱伝導率は66ppm/m・K、電気伝導率15%IACSである。そのため、Snを主成分として含む上記Sn系のハンダでは最高動作温度が300℃に達する半導体デバイスから放出される熱を放出したり、そうした半導体デバイスと電極の接合に用いたりすることは難しい。 (Sn solder)
In-vehicle IGBT modules are Pb-free, Sn-based solder (Sn-based solder) such as SnCu (melting point 228°C), SnAg-based (melting point 221°C), SnAgCu-based (melting point 219°C). , SnSb-based (melting point 240 ℃) solder is used. Further, those Sn-based solders filled with Ni balls to adjust the thickness of the die bond are also used. However, all of these have melting points below 300°C. Moreover, the thermal conductivity is as low as 60 W/mK or less. Furthermore, the electric conductivity is also extremely low at 25% IACS or less. This value is lower than the electrical conductivity of 30% IACS of W used as a heating material in an electric furnace. In addition, IACS (International Annealed Copper Standard) represents the electrical conductivity of various materials with the electrical conductivity of annealed standard annealed copper (volume resistivity: 1.7241×10 −2 μΩm) being 100% IACS. Sn has a melting point of 234° C., a thermal conductivity of 66 ppm/m·K, and an electrical conductivity of 15% IACS. Therefore, it is difficult to use the Sn-based solder containing Sn as a main component to release heat emitted from a semiconductor device having a maximum operating temperature of 300° C. or to use for joining such a semiconductor device and an electrode.
（Au系ハンダ）
　Sn系ハンダよりも耐熱性が高い、Auと添加材の共晶を利用したハンダも用いられている。しかし、添加剤としてSiを含むAuSiのハンダは、融点が370℃であるものの脆く、また、熱伝導率が53W/m・K、電気伝導率が22%IACS、といずれも低い。添加剤としてGeを含むAuGeのハンダも、融点が356℃であるものの脆く、熱伝導率が44W/m・K、電気伝導率が17%IACS、といずれも低い。加えて、これらのAu系ハンダは高価であり、特に寸法が大きい半導体デバイスを接合する材料として使用するには不向きである。 (Au solder)
A solder that uses a eutectic of Au and an additive material, which has higher heat resistance than Sn-based solder, is also used. However, AuSi solder containing Si as an additive has a melting point of 370° C., but is brittle, and has a low thermal conductivity of 53 W/m·K and a low electrical conductivity of 22% IACS. The AuGe solder containing Ge as an additive also has a melting point of 356° C., but is brittle, and has a low thermal conductivity of 44 W/m·K and a low electrical conductivity of 17% IACS. In addition, these Au-based solders are expensive and unsuitable for use as a material for joining semiconductor devices having particularly large dimensions.
（Ag蝋材）
　上記の他に、耐熱性が高いAg蝋材で半導体デバイスと電極を接合するという方法もある。Ag蝋材は熱伝導率と電気伝導率が高いという点で良好な特性を有する。しかし、Ag蝋材の融点は一般に600℃以上であり、Ag蝋材を用いて半導体デバイスと電極を溶融接合しようとすると、半導体デバイスが熱により破損するという問題がある。 (Ag wax material)
In addition to the above, there is also a method of joining the semiconductor device and the electrode with Ag wax material having high heat resistance. Ag wax has good properties in that it has high thermal conductivity and high electrical conductivity. However, the melting point of Ag wax material is generally 600° C. or higher, and there is a problem in that when a semiconductor device and an electrode are fusion-bonded using Ag wax material, the semiconductor device is damaged by heat.
（ナノAg）
　大学、研究機関、企業等では、上記のSn系ハンダ、Au系ハンダ、及びAg蝋材に代わる新たな材料を、パワー半導体のIGBTモジュールやLEDのダイボンディングに用いる試みがなされている。例えば非特許文献１では、ナノサイズのAg粒子（酸化銀の還元等により生成されるものを含む）やフレーク状のAg粒子等が、その表面活性によりバルク材料の融点よりも低い温度で焼結（低温焼結）されるという、低温融合現象を利用することが提案されている。ナノAgの低温融合現象を利用して焼結した焼結体はバルク材料の融点まで溶融しない。この方法では、300℃程度の低温で、ナノAgの一次粒子同士が結合して二次粒子が形成されていく。こうして形成される二次粒子の焼結温度は400℃以上と高温であり、300℃程度の低温のままでは二次粒子の焼結が進まない。ナノAgの低温融合現象を利用して焼結した焼結体の顕微鏡像には二次粒子間の粒界が明確に現れる。 (Nano Ag)
Universities, research institutes, companies, and the like have attempted to use new materials in place of the above Sn-based solder, Au-based solder, and Ag solder for die bonding of power semiconductor IGBT modules and LEDs. For example, in Non-Patent Document 1, nano-sized Ag particles (including those generated by reduction of silver oxide) and flake-shaped Ag particles are sintered at a temperature lower than the melting point of the bulk material due to their surface activity. It has been proposed to utilize the low temperature fusion phenomenon of being (low temperature sintered). The sintered body that is sintered by utilizing the low temperature fusion phenomenon of nano Ag does not melt up to the melting point of the bulk material. In this method, at a low temperature of about 300° C., primary particles of nano-Ag are bound to each other to form secondary particles. The sintering temperature of the secondary particles thus formed is as high as 400° C. or higher, and the sintering of the secondary particles does not proceed at a low temperature of about 300° C. Grain boundaries between secondary particles clearly appear in the microscopic image of the sintered body that was sintered by utilizing the low temperature fusion phenomenon of nano Ag.
　非特許文献１では、ナノAgをダイボンド材料として用いたパワー半導体モジュールについて、-40℃への冷却と125℃への加熱を繰り返したヒートサイクルテストの結果から、ダイボンド材料としてハンダを用いる場合と同程度の信頼性が得られるとされている。しかし、非特許文献１に記載されているような低温下では、ナノAg粒子から成長した二次粒子が焼結されず、内部に明確なナノ粒子の粒界やボイドが存在する。そのため、十分な強度を得ることができず、300℃に達するヒートサイクルテストを行うと粒界を起点とする劣化が生じやすい。従って、最高動作温度が300℃に達する半導体デバイスを接合するダイボンド材料として用いることは難しい。また、非特許文献２に記載されているように、ダイボンドを厚くすることが難しい、接合強度が不安定であるといった問題もある。なお、ナノAg粉末の価格は通常粉末の100倍以上である。これはAuはんだの数倍であり極めて高価である。 In Non-Patent Document 1, a power semiconductor module using nano Ag as a die bond material is the same as the case of using solder as a die bond material based on the result of a heat cycle test in which cooling to -40°C and heating to 125°C are repeated. It is said that some degree of reliability can be obtained. However, at a low temperature as described in Non-Patent Document 1, the secondary particles grown from the nano Ag particles are not sintered, and there are clear grain boundaries and voids of the nanoparticles inside. Therefore, sufficient strength cannot be obtained, and a heat cycle test reaching 300° C. tends to cause deterioration starting from a grain boundary. Therefore, it is difficult to use as a die-bonding material for joining semiconductor devices whose maximum operating temperature reaches 300°C. Further, as described in Non-Patent Document 2, there are problems that it is difficult to thicken the die bond and the bonding strength is unstable. The price of nano Ag powder is 100 times or more that of ordinary powder. This is several times more expensive than Au solder and extremely expensive.
（Ag及びSnから構成されAg3Snを多く含む合金）
　非特許文献２では、AgとSnの粉末の混合物について、低温融合現象を利用し、5MPaの荷重で焼結して作製したAgSn合金をダイボンドとして用いることが提案されている。この焼結隊にAg3Snが多く含まれており、ボイドは少なくなる。しかし、このAgSn合金は熱伝導率が約70W/m・Kと低い。これはSnハンダの熱伝導率（約60W/m・K）よりも若干高い程度である。また、粒界にAg3Snが凝集している。このAgSn合金は高いダイシェア強度（半導体デバイスと電極基板の接合強度）を有するとされているが、ヒートサイクルテストを行うと、粒界に凝集しているAg3Snによってダイボンドの劣化が生じる。 (Alloy composed of Ag and Sn and containing much Ag 3 Sn)
Non-Patent Document 2 proposes that an AgSn alloy produced by sintering a mixture of Ag and Sn powders at a load of 5 MPa by utilizing a low temperature fusion phenomenon is used as a die bond. This sintered body contains a large amount of Ag 3 Sn, and voids are reduced. However, this AgSn alloy has a low thermal conductivity of about 70 W/mK. This is slightly higher than the thermal conductivity of Sn solder (about 60 W/mK). In addition, Ag 3 Sn aggregates at the grain boundaries. It is said that this AgSn alloy has a high die shear strength (bonding strength between a semiconductor device and an electrode substrate), but when a heat cycle test is performed, Ag 3 Sn aggregated at grain boundaries causes die bond deterioration.
　このように、さまざまなダイボンド材料の開発が進められているが、現状では最高動作温度が300℃に達する半導体デバイスを接合するダイボンド材料やダイボンディング技術は未だ確立されていない。また、従来のダイボンド材料の特性評価の多くは材料単体を評価したものであり、必ずしも半導体デバイスを電極基板等に接合された実装時の状態を考慮したものではない。 In this way, various die-bond materials are being developed, but at present, the die-bond material and the die-bonding technology for joining semiconductor devices whose maximum operating temperature reaches 300°C have not been established yet. Further, most of the characteristic evaluations of conventional die bond materials are evaluations of the material alone, and do not necessarily consider the state of mounting the semiconductor device bonded to an electrode substrate or the like.
　本発明が解決しようとする課題は、最高動作温度が300℃に達する半導体素子を含む半導体デバイスと電極基板等の基板を接合するために用いることができる半導体デバイス接合部材を提供することである。 The problem to be solved by the present invention is to provide a semiconductor device bonding member that can be used for bonding a semiconductor device including a semiconductor element whose maximum operating temperature reaches 300° C. and a substrate such as an electrode substrate.
（目標特性）
　最高動作温度が300℃に達する半導体デバイスから発せられる熱を十分に放出するには、最高動作温度が150℃である半導体デバイスのダイボンドの熱伝導率（ハンダの熱伝導率は60W/m・K以下）の2倍以上の熱伝導率、即ち120W/m・K以上の熱伝導率を有することが求められる。また、半導体デバイスは動作時に局所的に熱が発生する場合があることから、動作時の信頼性を確保するために、ダイボンドの耐熱温度は500℃以上であることが好ましい。従来のIGBTモジュールにおいて、電気伝導率に起因する問題は未だ顕在化していないが、半導体デバイス（チップ）に流れる電流が100A、200A、300Aと大きくなるにつれて、半導体デバイスとの接合部で発生するジュール熱が電流値の二乗及び電気抵抗値に比例して大きくなっていくことを考慮すると、電気伝導率が50%IACS以上であることが好ましい。 (Target characteristic)
In order to sufficiently dissipate the heat generated by a semiconductor device whose maximum operating temperature reaches 300°C, the thermal conductivity of the die bond of the semiconductor device whose maximum operating temperature is 150°C (the thermal conductivity of solder is 60 W/mK It is required to have a thermal conductivity more than twice that of the following), that is, a thermal conductivity of 120 W/m·K or more. In addition, since the semiconductor device may locally generate heat during operation, the heat resistance temperature of the die bond is preferably 500° C. or higher in order to ensure reliability during operation. In the conventional IGBT module, the problem caused by electric conductivity has not yet become apparent, but as the current flowing through the semiconductor device (chip) increases to 100A, 200A, 300A, the module generated at the junction with the semiconductor device Considering that the heat increases in proportion to the square of the current value and the electric resistance value, the electric conductivity is preferably 50% IACS or more.
（評価）
　半導体デバイスを構成する主な材料の線膨張係数は、Siが4.1ppm/K、SiCが4.5ppm/K、GaNが3.2-5.6ppm/K、といずれも小さい。一方、代表的な電極材料であるCuの熱伝導率は17ppm/Kと大きい。従って、半導体デバイスと電極基板を接合するダイボンドは、両者の線膨張係数の差に起因して半導体デバイスの動作時に生じる大きな熱応力を緩和可能なものでなければならない。従来、ダイボンドの開発では、耐熱性や融点の特性以外に、300℃で所定時間保持して劣化が生じないかのテスト、あるいは常温でのダイシェア試験（せん断強度測定）を行うことで、実装時の特性評価に代えていた。一部では、これらと併せ、-40℃への冷却と250℃への加熱を繰り返し行い、劣化が生じないかを確認する試験（ヒートサイクルテスト）も行われてきた。本発明では、後述するようにSiC半導体デバイスと電極の接合面にそれぞれ1乃至複数のNi系めっき層などを設けてダイボンディングすることを想定している。従って、IGBTモジュールへの実装を想定したテストを行うには、上記めっき層を設けてダイボンディングした状態で-40℃への冷却と300℃への加熱を繰り返すヒートサイクルテストを行うことにより実装時の特性を判断する必要がある。また、このヒートサイクルテストを行った後でも、上述の熱伝導率及び電気伝導率を有することが求められる。 (Evaluation)
The linear expansion coefficients of the main materials constituting semiconductor devices are 4.1 ppm/K for Si, 4.5 ppm/K for SiC, and 3.2-5.6 ppm/K for GaN, which are all small. On the other hand, Cu, which is a typical electrode material, has a high thermal conductivity of 17 ppm/K. Therefore, the die bond for joining the semiconductor device and the electrode substrate must be capable of relieving a large thermal stress generated during the operation of the semiconductor device due to the difference in linear expansion coefficient between the two. In the past, in the development of die bonds, in addition to the heat resistance and melting point characteristics, a test was carried out at 300°C for a predetermined time to see if deterioration did not occur, or a die shear test (shear strength measurement) at room temperature was carried out. Instead of the characteristic evaluation. In some cases, in addition to these, a test (heat cycle test) has been performed in which cooling to -40°C and heating to 250°C are repeated to confirm whether or not deterioration occurs. In the present invention, it is assumed that one to a plurality of Ni-based plating layers or the like are provided on the bonding surfaces of the SiC semiconductor device and the electrodes and die bonding is performed, as described later. Therefore, to perform a test assuming mounting on an IGBT module, perform a heat cycle test that repeats cooling to -40°C and heating to 300°C with the above-mentioned plating layer provided and die-bonding. It is necessary to judge the characteristics of. Further, it is required to have the above-mentioned thermal conductivity and electrical conductivity even after the heat cycle test.
（製品形態）
　半導体デバイスの大きさや性能に応じてダイボンド材料に求められる特性は異なるが、ダイボンドが薄すぎると半導体デバイスと電極の間に生じる熱応力を十分に緩和することができない場合がある。一方、ダイボンドが厚すぎると平行度や寸法精度を高めることが難しくなり、特性にばらつきが生じやすくなる。これらの点を考慮すると、ダイボンドの厚さは0.01mm以上0.3mm以下とすることが好ましい。 (Product form)
The characteristics required of the die bond material differ depending on the size and performance of the semiconductor device, but if the die bond is too thin, the thermal stress generated between the semiconductor device and the electrode may not be sufficiently relaxed. On the other hand, if the die bond is too thick, it becomes difficult to improve the parallelism and the dimensional accuracy, and the characteristics tend to vary. Considering these points, the thickness of the die bond is preferably 0.01 mm or more and 0.3 mm or less.
（製造履歴）
　半導体デバイスの接合は、当然のことながら半導体デバイスが破損しない温度及び荷重で行わなければならない。従来の接合例には接合時のピーク温度が450℃程度に達すると報告されたものも存在する。しかし、半導体デバイスの破損を確実に防止するには接合時の最高温度が350℃以下であることが好ましい。IGBTモジュールに実装される半導体デバイスにかかる圧力の限界値（半導体デバイスの破壊が生じない圧力の最大値）については、特に具体的な値が報告されたものはないが、半導体デバイスの接合時に印加する圧力は5MPa未満とすることが好ましい。但し、必ずしも低温、低荷重が好ましいとは言えず、半導体デバイスや電極基板が十分な強度で接合されるように温度や荷重を定める必要がある。被接合物の素材、接合方法、接合装置によってこれらの条件は異なり、それぞれに最適条件が存在するが、その多くはノウハウ化されておりメーカーから詳細な接合条件が提示されることは少ない。 (Manufacturing history)
As a matter of course, the joining of the semiconductor devices must be performed at a temperature and a load that do not damage the semiconductor devices. Some of the conventional joining examples have been reported to reach a peak temperature of about 450°C during joining. However, in order to reliably prevent damage to the semiconductor device, the maximum temperature at the time of bonding is preferably 350°C or lower. Regarding the limit value of the pressure applied to the semiconductor device mounted on the IGBT module (the maximum value of the pressure that does not cause the destruction of the semiconductor device), no specific value has been reported, but it is applied when the semiconductor device is bonded. The pressure applied is preferably less than 5 MPa. However, low temperature and low load are not always preferable, and it is necessary to determine the temperature and load so that the semiconductor device and the electrode substrate are bonded with sufficient strength. These conditions differ depending on the material to be joined, the joining method, and the joining apparatus, and there are optimum conditions for each, but most of them are know-how, and manufacturers rarely present detailed joining conditions.
（材質の決定）
　半導体デバイスは450℃に達すると破壊する可能性がある。そこで、本発明者は、ダイボンドの検討にあたり、まず、半導体デバイスの破壊温度以下（450℃）で接合可能であり、また-40～300℃でのヒートサイクルテスト後にも十分な熱伝導率と電気伝導率を有することが期待される材料である、Ag（融点961℃、熱伝導率105ppm/m・K、電気伝導率110%IACS）系の材料を調査した。溶解法で製造されるAg蝋の1つであるBAg-18（JIS規格。Agの含有率：60質量パーセント、Cuの含有率：30質量パーセント、Snの含有率：10質量パーセント）の融点（固相線温度）は約671℃である。その熱伝導率を測定したところ、215W/m・K、電気伝導率は57%IACSであった。これらはいずれも目標値を超えている。バルク材料の溶融温度（融点）は671℃と高いものの、非特許文献２に記載されているような低温融合現象を利用すれば解決できると考えた。ここでいう低温融合現象は、Snを溶かし、バルク材のAgよりも低い温度でAgと反応させることを言う。この低温融合現象を利用した方法を、本願明細書では、以降、「低温低圧溶融反応接合法」と呼ぶ。ここでいう低温低圧溶融反応接合法は、ナノAgにおいて見られるような、粒子の表面活性に起因する低温融合現象とは異なる。 (Determination of material)
Semiconductor devices can be destroyed when they reach 450°C. Therefore, the present inventor, when studying the die bond, can first bond the semiconductor device at a temperature below the breakdown temperature of the semiconductor device (450° C.), and has sufficient thermal conductivity and electrical conductivity even after a heat cycle test at -40 to 300° C. Materials of Ag (melting point 961°C, thermal conductivity 105ppm/mK, electrical conductivity 110%IACS) based materials, which are expected to have conductivity, were investigated. A melting point of BAg-18 (JIS standard. Ag content: 60 mass%, Cu content: 30 mass%, Sn content: 10 mass%), which is one of Ag waxes manufactured by the melting method. Solidus temperature) is about 671°C. When its thermal conductivity was measured, it was 215 W/m·K and its electrical conductivity was 57% IACS. Each of these exceeds the target value. Although the melting temperature (melting point) of the bulk material is as high as 671° C., it was thought that this could be solved by using the low temperature fusion phenomenon as described in Non-Patent Document 2. The low-temperature fusion phenomenon referred to here is that Sn is melted and reacted with Ag at a temperature lower than Ag of the bulk material. In the present specification, a method utilizing this low temperature fusion phenomenon is hereinafter referred to as "low temperature low pressure fusion reaction joining method". The low-temperature low-pressure fusion reaction joining method referred to here is different from the low-temperature fusion phenomenon caused by the surface activity of particles as seen in nano Ag.
　Agの融点は961℃、Snの融点は232℃、Cuの融点は1083℃である。従って、これらの含有比を適宜に変更することにより接合温度を下げることができる。しかし、AgにSnを混合すると大きく熱伝導率が低下することが知られている。また、非特許文献２に記載されているように、加圧焼結法で作製された60Ag40Sn（Agの含有率：60重量パーセント、Snの含有率：40重量パーセント）のAg3Sn合金の熱伝導率は70W/m・Kと低く、BAg-18の熱伝導率（215W/m・K）とは大きく隔たりがある。さらに、溶解法で作製された60Ag40Snの熱伝導率は83W/m・Kと低い。一方、90Ag10Sn（Agの含有率：90重量パーセント、Snの含有率：10重量パーセント）の熱伝導率は310W/m・Kと非常に高かった。 The melting point of Ag is 961°C, the melting point of Sn is 232°C, and the melting point of Cu is 1083°C. Therefore, the bonding temperature can be lowered by appropriately changing the content ratio of these. However, it is known that when Sn is mixed with Ag, the thermal conductivity greatly decreases. Further, as described in Non-Patent Document 2, heat of Ag 3 Sn alloy of 60Ag40Sn (Ag content: 60 weight percent, Sn content: 40 weight percent) produced by a pressure sintering method. It has a low conductivity of 70 W/mK, which is far from the thermal conductivity of BAg-18 (215 W/mK). Furthermore, the thermal conductivity of 60Ag40Sn produced by the melting method is as low as 83 W/mK. On the other hand, the thermal conductivity of 90Ag10Sn (Ag content: 90% by weight, Sn content: 10% by weight) was 310 W/mK, which was extremely high.
　こうしたことを踏まえて10種類の混合粉末材料（いずれも平均粒径2μm）を、SiC半導体デバイス（片面にNiめっき層を設けたもの）と電極（片面にNiめっき層を設けたもの）の間に配置し、真空雰囲気において300℃で1MPa又は5MPaの加圧下で10分間保持することにより、SiC半導体デバイスと電極の間に厚さ0.2mmのダイボンドを形成した試料１～１０を作製した。そして、実装状態での使用の適否を確認するために、それぞれの再溶解温度を測定し、続いてヒートサイクルテストを行って合否を判定した。そして、再溶解温度とヒートサイクルテストの結果から試料１～１０の信頼性を確認した。表1に試料１～１０の組成、加圧条件、再溶解温度、及びヒートサイクルテストの結果を示す。
Figure JPOXMLDOC01-appb-T000001
 Based on this, 10 types of mixed powder materials (all having an average particle size of 2 μm) were used between the SiC semiconductor device (having a Ni plating layer on one side) and the electrode (having a Ni plating layer on one side). Samples 1 to 10 in which a die bond having a thickness of 0.2 mm was formed between the SiC semiconductor device and the electrode were prepared by placing the SiC semiconductor device and the electrode under a pressure of 1 MPa or 5 MPa at 300° C. for 10 minutes in a vacuum atmosphere. Then, in order to confirm the suitability of use in the mounted state, each remelting temperature was measured, and subsequently, a heat cycle test was performed to judge the pass/fail. Then, the reliability of Samples 1 to 10 was confirmed from the results of the remelting temperature and the heat cycle test. Table 1 shows the compositions of Samples 1 to 10, the pressurization conditions, the remelting temperature, and the results of the heat cycle test.
Figure JPOXMLDOC01-appb-T000001
　試料１－３では内部に多数のボイド（空隙）が存在していたにもかかわらず、ヒートサイクルテストにおいて劣化が生じなかった。本発明者は、この結果は、車載用の第2世代のIGBTモジュールにおいて放熱基板を省略する際にDBA（線膨張係数が7ppm/K）と、Al合金（線膨張係数が21ppm/K）からなる冷却器（ラジエータ）とをAlハンダにより接合するとAl板では接合面が剥離した一方、Alパンチング板（Al板材に多数の貫通孔を形成したもの）では接合面の剥離が生じなかったという事実、つまり、Alパンチング板に形成されている貫通孔（空隙）が応力を緩和した、という事実と共通していると考えた。また、従来、ハンダや、Ag3Snを多く含むAgSn合金では問題とされてきたボイドやパンチングメタルの貫通孔等の空隙が、接合部材間の線膨張係数差から生じる熱応力を緩和する効果があることに気づいた。そして、条件を種々に変更しつつ半導体デバイス接合部材を作製及び評価した結果を検討し、本発明に想到した。 In Sample 1-3, although there were many voids (voids) inside, deterioration did not occur in the heat cycle test. The present inventors have found that this result is obtained from DBA (coefficient of linear expansion of 7 ppm/K) and Al alloy (coefficient of linear expansion of 21 ppm/K) when omitting the heat dissipation board in the second-generation IGBT module for vehicle installation. The fact that when joining a cooling device (radiator) with Al solder, the joining surface peeled off on the Al plate, but on the Al punching plate (where many through holes were formed in the Al plate material), the joining surface did not peel off. In other words, it was thought to be common with the fact that the through holes (voids) formed in the Al punching plate relieved the stress. Further, conventionally, solder and voids such as voids and through holes of punching metal, which have been problematic in AgSn alloys containing a large amount of Ag 3 Sn, have the effect of relaxing the thermal stress caused by the difference in linear expansion coefficient between joining members. I realized that there is. Then, the present invention was devised by studying the results of producing and evaluating the semiconductor device bonding member while changing the conditions variously.
　上記検討から得られた本発明は、半導体デバイスの被接合面と該半導体デバイスが載置される基板の被接合面とを接合する半導体デバイス接合部材であって、
　Ag、Cu、及びAuのうちの少なくとも1種類とSnとを主成分とし、融点が500℃以上である合金からなる層を含み、
　内部に、総体積が全体の5パーセント以上40パーセント以下である複数の空隙を有し、
　-40℃への冷却と300℃への加熱を繰り返すヒートサイクルテストを300回行った後の熱伝導率が120W/m・K以上、電気伝導率が50%IACS以上である
　ことを特徴とする。 The present invention obtained from the above study is a semiconductor device joining member for joining a joined surface of a semiconductor device and a joined surface of a substrate on which the semiconductor device is mounted,
Ag, Cu, and at least one of Au and Sn as a main component, including a layer made of an alloy having a melting point of 500 ℃ or more,
Inside, having a plurality of voids having a total volume of 5% or more and 40% or less,
Characterized by having a thermal conductivity of 120 W/mK or more and an electrical conductivity of 50% IACS or more after 300 heat cycle tests in which cooling to -40°C and heating to 300°C are repeated. ..
　本発明に係る半導体デバイス接合部材は、半導体デバイスの被接合面と基板の被接合面とを接合するために両接合面の間に配される部材である。本発明に係る半導体デバイス接合部材は、Ag、Cu、及びAuのうちの少なくとも1種類とSnとを主成分とする、融点が500℃以上である合金からなる層を含むことから、動作時の温度が300℃あるいはそれ以上となる半導体デバイスを接合する材料として十分な耐熱性を有している。 The semiconductor device joining member according to the present invention is a member arranged between the joining surfaces of the semiconductor device and the substrate in order to join the joining surfaces. The semiconductor device bonding member according to the present invention contains at least one kind of Ag, Cu, and Au and Sn as a main component, and includes a layer made of an alloy having a melting point of 500° C. or higher, and therefore, the It has sufficient heat resistance as a material for bonding semiconductor devices whose temperature is 300°C or higher.
　また、本発明に係る半導体デバイス接合部材は、その内部に総体積が全体の5パーセント以上、40パーセント以下の複数の空隙を有しており、これらの空隙によって半導体デバイス接合部材の変形が許容され、半導体デバイスと電極基板等の基板の線膨張係数の差により生じる熱応力が緩和される。熱応力を緩和する効果は、空隙の量に大きく依存する。空隙の割合が5体積パーセント未満であると熱応力を緩和する効果が十分でなく、40体積パーセントを超えると材料そのものが破断しやすくなる。また空隙の形状や数は被接合物の使用環境や製造工程などに応じて適宜に決めればよいが、1個の空隙の大きさの目安は、例えば該空隙を同体積の球に近似したときにその直径が0.005mm以上3mm以下の範囲である。0.005mmよりも小さいと、応力を緩和する効果が得られにくい。また3mmよりも大きいと空隙の位置で熱抵抗が増大しやすくなる。1個の空隙の大きさは、より好ましくは0.2mm以上2mm以下である。上記空隙の大きさや分布は、複数の空隙の総体積が全体の5パーセント以上40パーセント以下であるという上記の要件を満たしていればよく、必ずしも半導体デバイス接合部材の全体にわたって一様である必要はない。例えば、部材の中心部に空隙率が高い層を有し、その表裏面に空隙率が低い（あるいは空隙がほとんどない）層を有するものであってもよい。逆に、部材の中心部に空隙率が低い（あるいは空隙がほとんどない）層を有し、その表裏面に空隙率が高い層を有するものであってもよい。あるいは、表裏面で空隙率が異なっていてもよい。 Further, the semiconductor device bonding member according to the present invention has a plurality of voids having a total volume of 5% or more and 40% or less of the whole inside thereof, and these voids allow deformation of the semiconductor device bonding member. The thermal stress caused by the difference in linear expansion coefficient between the semiconductor device and the substrate such as the electrode substrate is relaxed. The effect of relieving the thermal stress largely depends on the amount of voids. If the proportion of voids is less than 5 volume percent, the effect of relaxing the thermal stress is not sufficient, and if it exceeds 40 volume percent, the material itself tends to break. Also, the shape and number of voids may be appropriately determined according to the use environment and manufacturing process of the object to be joined, but the guideline for the size of one void is, for example, when the voids are approximated to spheres of the same volume. The diameter is 0.005 mm or more and 3 mm or less. If it is smaller than 0.005 mm, it is difficult to obtain the effect of relieving stress. If it is larger than 3 mm, the thermal resistance tends to increase at the position of the void. The size of one void is more preferably 0.2 mm or more and 2 mm or less. The size and distribution of the voids only need to satisfy the above requirement that the total volume of the plurality of voids be 5% or more and 40% or less of the whole, and need not necessarily be uniform over the entire semiconductor device bonding member. Absent. For example, it may have a layer having a high porosity at the center of the member and a layer having a low porosity (or almost no voids) on its front and back surfaces. Conversely, it may have a layer having a low porosity (or almost no voids) in the center of the member and a layer having a high porosity on the front and back surfaces thereof. Alternatively, the front and back surfaces may have different porosities.
　さらに、-40℃への冷却と300℃への加熱を300回繰り返すヒートサイクルテストを行った後の熱伝導率が120W/m・K以上、電気伝導率が50%IACS以上であることから、半導体デバイスの動作時に発生する熱を効率よく放出することができ、また、半導体デバイス接合部材に過剰なジュール熱が発生することもない。本発明に係る半導体デバイス接合部材は、これらの特徴を有するため、動作時の最高温度が300℃に達する半導体デバイスと、該半導体デバイスが載置される基板の接合に用いることができる。 Furthermore, after conducting a heat cycle test in which cooling to -40°C and heating to 300°C are repeated 300 times, the thermal conductivity is 120 W/mK or more, and the electrical conductivity is 50% IACS or more, The heat generated during the operation of the semiconductor device can be efficiently released, and excessive Joule heat is not generated in the semiconductor device joining member. Since the semiconductor device bonding member according to the present invention has these characteristics, it can be used for bonding a semiconductor device whose maximum temperature during operation reaches 300° C. and a substrate on which the semiconductor device is mounted.
　本発明に係る半導体デバイス接合部材では、上記合金からなる層におけるSnの含有率が2重量パーセント以上20重量パーセント以下であることが好ましい。本発明者がSnの含有率を種々に設定して行った試験の結果によれば、貫通孔を複数設けたAg板材に、Snの含有率が全体の2重量パーセントから20重量パーセントの範囲となるように調整した大きさのSnの板材を重ね、Snの融点以上である300℃に加熱したあと0.5MPaの圧力を印加することにより、Ag板材の表面で溶融したSnをAgと合金化したところ、いずれも融点が500℃以上である等の上記の要件を満たす半導体デバイス接合部材を得ることができた。また、Snの含有率が全体の2重量パーセントから20重量パーセントの範囲となるように調整したAg粉末とSn粉末についても上記の要件を満たす半導体デバイス接合部材を得ることができた。本願明細書ではこれらの方法を「低温低圧溶融反応接合法」と呼ぶ。Agに溶融させるSnの含有率を20重量パーセント以下と低くするとAg3Snからなる共晶物の生成が抑制される。非特許文献２ではAg3Snを多く含む（例えば全体の50体積パーセントを占める）AgSn合金が作製されるのに対し、本発明に係る半導体デバイス接合部材では、上記合金からなる層に含まれるAg3Snの割合が10体積パーセント以下である。より好ましくは、Ag3Snの割合は5体積パーセント以下であり、さらに好ましくは3体積パーセント以下である。粒界に共晶物が存在していると亀裂の起点になりやすい。Snの含有率を上記範囲内とすることにより、粒界に共晶物が存在しにくくなる。これにより、亀裂の発生を抑え、耐久性を高くすることができる。 In the semiconductor device bonding member according to the present invention, it is preferable that the content of Sn in the layer made of the above alloy is 2% by weight or more and 20% by weight or less. According to the results of the test conducted by the present inventor variously set the content of Sn, the Ag plate material provided with a plurality of through holes, the content of Sn is in the range of 2% by weight to 20% by weight of the whole. By stacking Sn plates with sizes adjusted so that Sn was melted on the surface of the Ag plate and alloyed with Ag by applying a pressure of 0.5 MPa after heating to 300°C, which is the melting point of Sn or higher. However, in all cases, a semiconductor device bonding member satisfying the above requirements such as a melting point of 500° C. or higher could be obtained. Further, it was possible to obtain a semiconductor device bonding member satisfying the above requirements also for Ag powder and Sn powder adjusted so that the Sn content was in the range of 2% by weight to 20% by weight. In the present specification, these methods are referred to as "low temperature low pressure fusion reaction bonding method". When the content of Sn to be melted in Ag is reduced to 20% by weight or less, the formation of a eutectic substance composed of Ag 3 Sn is suppressed. In Non-Patent Document 2, an AgSn alloy containing a large amount of Ag 3 Sn (for example, occupying 50% by volume of the whole) is produced, whereas in the semiconductor device bonding member according to the present invention, Ag contained in the layer made of the alloy is Ag. The ratio of 3 Sn is 10 volume% or less. More preferably, the proportion of Ag 3 Sn is 5 volume% or less, and even more preferably 3 volume% or less. The presence of eutectic at grain boundaries is likely to be the origin of cracks. By setting the Sn content in the above range, it becomes difficult for eutectic to exist at the grain boundaries. Thereby, generation of cracks can be suppressed and durability can be improved.
　本発明に係る半導体デバイス接合部材を用いることにより、最高動作温度が300℃に達する半導体デバイスと、該半導体デバイスが載置される電極基板等とを接合することができる。また、本発明に係る半導体デバイス接合部材では、必ずしも高価なナノAgを使用しなくても良い。更に、これまでハンダ接合で培った技術や設備が使用できる。 By using the semiconductor device bonding member according to the present invention, it is possible to bond a semiconductor device having a maximum operating temperature of 300° C. and an electrode substrate or the like on which the semiconductor device is mounted. Moreover, in the semiconductor device bonding member according to the present invention, expensive nano Ag is not necessarily used. Furthermore, the technology and equipment cultivated up to now for soldering can be used.
　ハンダでは、一般に、5%以上の空隙（ボイド）が存在すると、ヒートサイクルテストにおいてボイドが起点となり、粒界に存在する、強度が低く脆い共晶合金の部分を亀裂が連鎖して破壊される。また、非特許文献２に記載のようなAg3Snを多く含んだAgSn合金ではボイドの割合が少ないが、ヒートサイクルテストにおいてそのボイドが起点となり、粒界に存在する、強度が低いAg3Sn共晶合金の部分を亀裂が連鎖して破壊される。ナノAgの場合、一次粒子はバルク材のAgの融点よりも低温で焼結されるが、焼結により形成された二次粒子は400℃以上でないと焼結しないため、粒界が形成され、そこにボイドが発生する。このようなボイドが存在すると、ヒートサイクルテストにおいてボイドが起点となり、強度が低い二次粒子の亀裂が連鎖して破壊される。上記の他に、ボイドのないところでもAg3Sn共晶合金や二次粒子の亀裂による破壊が起こる。 In solder, when 5% or more of voids (voids) are present, the voids become the starting point in the heat cycle test, and cracks are chained and broken in the low-strength, brittle eutectic alloy existing in the grain boundaries. .. Further, in the AgSn alloy containing a large amount of Ag 3 Sn as described in Non-Patent Document 2, the void ratio is small, but in the heat cycle test, the void is the starting point, and Ag 3 Sn with low strength existing at the grain boundary is present. Cracks are chained to break the part of the eutectic alloy. In the case of nano Ag, the primary particles are sintered at a temperature lower than the melting point of Ag of the bulk material, but the secondary particles formed by sintering do not sinter unless the temperature is 400° C. or higher, so a grain boundary is formed, A void occurs there. When such voids are present, the voids become the starting points in the heat cycle test, and the cracks of the secondary particles having low strength are chained and destroyed. In addition to the above, fracture due to cracking of Ag 3 Sn eutectic alloy and secondary particles occurs even in the absence of voids.
　従来のダイボンドでは、ボイド等の空隙があると、そこが起点となり亀裂が連鎖して破壊され、ヒートサイクルテストに合格できないという問題があったため、ボイド等の空隙を極力減らすことを目的として研究開発が行われてきた。しかし、本発明者が見出した知見によれば、ボイド等の空隙があっても、共晶物や二次粒界が少なく、半導体デバイス接合部材全体としての強度が十分に高ければヒートサイクルテストに合格し、また、ヒートサイクルテスト後にも熱伝導率や電気伝導率に関する所要の特性を有する。 In the conventional die bond, if there were voids and other voids, there was the problem that cracks would chain and break, starting from that point, and the heat cycle test could not be passed. Has been done. However, according to the findings found by the present inventor, even if there are voids and the like, if there are few eutectic substances and secondary grain boundaries and the strength of the entire semiconductor device bonding member is sufficiently high, a heat cycle test It also passed the test and had the required properties regarding thermal conductivity and electrical conductivity after the heat cycle test.
　本発明では、Ag等とSnを用いた低温低圧溶融反応接合法によって半導体デバイスや電極基板を接合し、Ag、AgSn合金等により高い熱伝導率と耐熱性を確保する。そして、ボイドにより熱応力の緩和を行い、また、Ag、AgSn合金等を用いることで、ボイドを起点とする亀裂の広がりを抑制する。本発明は、これまでボイド等の欠陥をなくすという従来の材料開発とは逆の発想に基づくものであり、ボイドを耐熱性が高く強固な材料で取り囲むことによってボイドが欠陥の起点とならないようにすることで、ボイドを熱応力の緩和に利用したものである。 In the present invention, a semiconductor device or an electrode substrate is joined by a low-temperature low-pressure melting reaction joining method using Ag and Sn, and high heat conductivity and heat resistance are secured by Ag, AgSn alloy, etc. Then, the thermal stress is relaxed by the voids, and the spread of cracks originating from the voids is suppressed by using Ag, AgSn alloy or the like. The present invention is based on the idea opposite to the conventional material development of eliminating defects such as voids, so that the voids do not become the origin of defects by surrounding the voids with a highly heat-resistant and strong material. By doing so, the voids are used for relaxing the thermal stress.
本発明に係る半導体デバイス接合部材の一実施例により半導体デバイスと電極部材を接合した状態の模式図。The schematic diagram of the state which joined the semiconductor device and the electrode member by one Example of the semiconductor device joining member concerning the present invention.
　本発明に係る半導体デバイス接合部材は上記の通りであるが、その技術的思想はより一般化することができる。具体的には、本発明の技術的思想は、半導体デバイスの被接合面と該半導体デバイスが載置される基板の被接合面とを接合する半導体デバイス接合部材を、
　第１金属と、該第１金属よりも融点が低い第２金属を主成分とし、該第２金属の含有率が2重量パーセント以上、20重量パーセント以下である、融点が500℃以上である合金からなる層を含み、
　内部に、総体積が全体の5パーセント以上40パーセント以下である複数の空隙を有し、
　-40℃への冷却と300℃への加熱を300回繰り返すヒートサイクルテストを行った後の熱伝導率が120W/m・K以上、電気伝導率が50%IACS以上である
　という要件を満たすものとすること、と表現することができる。 The semiconductor device joining member according to the present invention is as described above, but its technical idea can be generalized. Specifically, the technical idea of the present invention is to provide a semiconductor device joining member for joining a joined surface of a semiconductor device and a joined surface of a substrate on which the semiconductor device is mounted,
An alloy containing a first metal and a second metal having a melting point lower than that of the first metal as main components, a content of the second metal of 2% by weight or more and 20% by weight or less, and a melting point of 500° C. or more. Including a layer consisting of
Inside, having a plurality of voids having a total volume of 5% or more and 40% or less,
Satisfies the requirement that the thermal conductivity is 120W/mK or more and the electrical conductivity is 50%IACS or more after the heat cycle test in which cooling to -40℃ and heating to 300℃ are repeated 300 times. Can be expressed as
　本発明に係る半導体デバイス接合部材の実施例を説明する。本実施例の半導体デバイス接合部材１０は、いわゆるダイボンドであって、図１に模式的に示すように、半導体デバイス１１を電極基板１２等の基板と接合するために用いられる。本実施例の半導体デバイス接合部材１０は、合金等からなる骨格１０１の内部に空隙（ボイド）１０２を所定の割合で設けたものである。なお、図１では、第１金属の板材に設けた貫通孔に第２金属を導入することにより作製した場合の半導体デバイス接合部材１０の構造、即ち、ボイド１０２が図の上下方向に並ぶ例を記載したが、ボイド１０２は骨格１０１の内部にランダムに位置してもよい。また、空隙（ボイド）の大きさや形状が一定である必要はない。さらに、必ずしも半導体デバイス接合部材１０の全体にわたって空隙（ボイド）１０２が均一に分布している必要はなく、例えば動作時に応力が大きくなりやすい場所がある場合には、その場所に多くの空隙を集中的に配置してもよい。さらに、ボイドを多く含む層と、ボイドが少ない（あるいはほとんどない）層とを積層したものであってもよい。半導体デバイス接合部材１０の骨格１０１を構成する合金の作製には、上記の低温低圧溶融反応接合法を好適に用いることができる。半導体デバイス接合部材１０の骨格１０１を構成するにはいくつもの方法があるが、例えば粉末法や骨格法を用いることができる。その他、請求項に記載の要件を満たす半導体デバイス接合部材を作製可能である限りにおいて、適宜の方法を用いることができる。 An example of a semiconductor device joining member according to the present invention will be described. The semiconductor device bonding member 10 of this embodiment is a so-called die bond, and is used for bonding the semiconductor device 11 to a substrate such as the electrode substrate 12 as schematically shown in FIG. The semiconductor device bonding member 10 of the present embodiment is one in which voids (voids) 102 are provided at a predetermined ratio inside a skeleton 101 made of an alloy or the like. Note that, in FIG. 1, the structure of the semiconductor device bonding member 10 in the case of being manufactured by introducing the second metal into the through hole provided in the plate material of the first metal, that is, an example in which the voids 102 are arranged in the vertical direction of the drawing. Although described, the voids 102 may be randomly located inside the skeleton 101. In addition, the size and shape of the voids need not be constant. Further, the voids (voids) 102 do not necessarily have to be evenly distributed over the entire semiconductor device bonding member 10. For example, if there is a place where stress tends to increase during operation, many voids are concentrated in that place. It may be arranged in a desired manner. Further, it may be a stack of a layer containing many voids and a layer containing few voids (or few voids). The above-mentioned low-temperature low-pressure melting reaction joining method can be preferably used for producing the alloy forming the skeleton 101 of the semiconductor device joining member 10. There are various methods for forming the skeleton 101 of the semiconductor device bonding member 10, and for example, a powder method or a skeleton method can be used. In addition, an appropriate method can be used as long as a semiconductor device bonding member satisfying the requirements of the claims can be manufactured.
（第１金属）
　上記第１金属は、例えばAg、Cu、Au、及びそれらの合金のうちの1乃至複数からなる。第１金属には融点、熱伝導率、電気伝導率が高い金属を用いる。また、第２金属（Sn等）との反応によって金属間化合物が形成されにくい金属を用いる。第１金属には、特にAgを好適に用いることができる。一方、Cuを用いることによりAgの使用量を減らして安価に半導体デバイス接合部材を作製することができる。またAu、あるいはAg、Cu、及びAuの合金を用いることもできる。 (First metal)
The first metal is, for example, one or more of Ag, Cu, Au, and alloys thereof. A metal having a high melting point, a high thermal conductivity, and a high electrical conductivity is used as the first metal. In addition, a metal in which an intermetallic compound is less likely to be formed by a reaction with a second metal (Sn or the like) is used. Particularly, Ag can be preferably used as the first metal. On the other hand, by using Cu, the amount of Ag used can be reduced and a semiconductor device bonding member can be manufactured at low cost. It is also possible to use Au, or an alloy of Ag, Cu, and Au.
（第２金属）
　第２金属は溶融させ、第１金属と反応させて低温で合金化する。第２金属にはSnを好適に用いることができる。半導体デバイス接合部材の作製時に印加する温度や圧力によって異なるが、第２金属の割合は、得ようとする半導体デバイス接合部材の2重量パーセント以上、20重量パーセント以下の範囲内とするとよい。これにより、ヒートサイクルテストにおいて問題が生じず、また所要の特性を得ることができる。 (Second metal)
The second metal melts and reacts with the first metal to alloy at low temperatures. Sn can be preferably used for the second metal. The ratio of the second metal is preferably in the range of 2% by weight or more and 20% by weight or less of the semiconductor device joining member to be obtained, although it varies depending on the temperature and pressure applied during the production of the semiconductor device joining member. As a result, no problem occurs in the heat cycle test, and the required characteristics can be obtained.
　第１金属がAg、第２金属がSnである場合、状態図から分かるように、Agと反応させるSnの含有率を20重量パーセント以下と低くするとAg3Snからなる共晶物の生成が抑制される。粒界に共晶物が存在していると亀裂の原因になりやすい。Snの含有率を上記範囲内とすることにより、粒界に共晶物が存在しにくくなる。これにより、亀裂の発生を抑え、耐久性を高くすることができる。一方、Snの含有率が2重量パーセント未満であると、Snを均一に配置することが難しいため半導体デバイス等との接合時の温度にバラつきが生じやすい。その結果、Snが存在しない位置において、接合温度が450℃（半導体デバイスが破壊する可能性のある温度）を超える可能性がある。なお、第１金属と第２金属以外に、添加金属としてCu、Ag、Pb、Cd、Zn、Sb、Ni、Mn、Ti、In、Mo、Si、V、Ge及びLiのうちの１乃至複数を更に含んでいてもよい。また、半導体デバイス等との接合部以外には、Agのみから構成される部分や、AgとAgSnが混在する部分があってもよい。 When the first metal is Ag and the second metal is Sn, as can be seen from the state diagram, when the Sn content reacted with Ag is reduced to 20% by weight or less, the formation of a eutectic substance composed of Ag 3 Sn is suppressed. To be done. The presence of eutectic at grain boundaries is likely to cause cracking. By setting the Sn content in the above range, it becomes difficult for eutectic to exist at the grain boundaries. Thereby, generation of cracks can be suppressed and durability can be improved. On the other hand, if the Sn content is less than 2% by weight, it is difficult to disperse the Sn uniformly, so that the temperature at the time of joining with a semiconductor device or the like tends to vary. As a result, the junction temperature may exceed 450° C. (the temperature at which the semiconductor device may be destroyed) at the position where Sn does not exist. In addition to the first metal and the second metal, one or more of Cu, Ag, Pb, Cd, Zn, Sb, Ni, Mn, Ti, In, Mo, Si, V, Ge and Li are added metals. May be further included. In addition to the junction with a semiconductor device or the like, there may be a portion composed only of Ag or a portion in which Ag and AgSn are mixed.
（被接合部材）
　被接合部材の一方は半導体デバイスであり、他方は該半導体デバイスを載置する基板（例えば電極基板）である。従来、これらをハンダにより接合する際には、接合面にNi、Pt、Co等からなる金属層を設けている。IGBTモジュールでは厚さ2μm程度のNi層を設けることが多い。また、電極基板や放熱基板の接合面には、Niのほか、Ti、W、Co等からなる金属層を設けることもある。さらに、Ag蝋材により接合する場合には、Ag蝋材との反応を防止するためにNi、Pt、Co等からなる金属層が設けられることがある。多くの場合、Ni系のめっきである電解Niめっき、無電解のNi-P、Ni-Bなどが用いられる。その他、上記各層の上に、Ag、Au、Cu、Zn等の、1乃至複数のめっき層が設けられることもある。本発明に係る半導体デバイス接合部材により半導体デバイスと基材を接合する際にも、上記同様に各層を適宜に用いることができる。 (Parts to be joined)
One of the members to be joined is a semiconductor device, and the other is a substrate (for example, an electrode substrate) on which the semiconductor device is mounted. Conventionally, when these are joined by solder, a metal layer made of Ni, Pt, Co or the like is provided on the joint surface. An IGBT module often has a Ni layer with a thickness of about 2 μm. In addition to Ni, a metal layer made of Ti, W, Co or the like may be provided on the bonding surface of the electrode substrate or the heat dissipation substrate. Furthermore, when joining with an Ag brazing material, a metal layer made of Ni, Pt, Co or the like may be provided in order to prevent reaction with the Ag brazing material. In many cases, electrolytic Ni plating, which is a Ni-based plating, electroless Ni-P, Ni-B, or the like is used. In addition, one or more plating layers of Ag, Au, Cu, Zn, etc. may be provided on each of the above layers. When the semiconductor device and the base material are bonded by the semiconductor device bonding member according to the present invention, each layer can be appropriately used as described above.
　例えば、パワー半導体である半導体デバイスを搭載したIGBTでは、半導体デバイスの表裏面に薄いNi系金属からなる電極を配置することがあり、その場合、こうした電極を含めて半導体デバイスと呼ばれる。また、電極基板との接合性を向上するためにAu、Ag、Cu、Sn等の金属、あるいはそれらの合金などからなる層が設けられることもあり、その場合はこの層も含めて半導体デバイスと呼ばれる。つまり、電極基板と接合する前の半導体デバイスと一体的に構成されている層を含めて、広義の半導体デバイスと解釈することができる。 For example, in an IGBT equipped with a semiconductor device that is a power semiconductor, electrodes made of thin Ni-based metal may be placed on the front and back surfaces of the semiconductor device, and in that case, such electrodes are called a semiconductor device. Further, in order to improve the bondability with the electrode substrate, a layer made of Au, Ag, Cu, a metal such as Sn, or an alloy thereof may be provided, and in that case, a semiconductor device including this layer is also included. be called. That is, it can be construed as a semiconductor device in a broad sense, including a layer integrally formed with the semiconductor device before being bonded to the electrode substrate.
　さらに、電極基板の被接合面に突出した凸状の補助電極が設けられることもある。こうした補助電極は、ろう材やダイボンド材料によってCu等の平板に取り付けられている。こうした補助電極にも、半導体デバイスとの接合性を向上するためのNi系めっき層が設けられたり、Au、Ag、Cu、Sn等の金属、あるいはそれらの合金からなる層が設けられたりすることがあり、その場合には、これらの層を含めて電極基板と呼ばれる。つまり、半導体デバイスと接合する前の電極基板と一体的に構成された層を含めて、広義の電極基板と解釈することができる。例えば、接合性を高めるために半導体デバイスの被接合面に形成されたAg層は半導体デバイスの一部であり、該Ag層に含まれるAgとSnが合金化して形成される層は半導体デバイス接合部材の一部であると解釈することができる。その他、DBCやDBAの表層に配される金属についても、電極基板の一部であり、該金属とSnが合金化して形成される層は半導体デバイス接合部材の一部であると解釈することができる。 Furthermore, a protruding auxiliary electrode may be provided on the surface to be joined of the electrode substrate. Such an auxiliary electrode is attached to a flat plate such as Cu by a brazing material or a die bonding material. Such an auxiliary electrode may also be provided with a Ni-based plating layer for improving the bondability with a semiconductor device, or a layer made of a metal such as Au, Ag, Cu, Sn, or an alloy thereof. In that case, including these layers, it is called an electrode substrate. That is, it can be interpreted as an electrode substrate in a broad sense, including a layer integrally formed with the electrode substrate before being bonded to the semiconductor device. For example, the Ag layer formed on the surface to be joined of the semiconductor device to enhance the joining property is a part of the semiconductor device, and the layer formed by alloying Ag and Sn contained in the Ag layer is the semiconductor device joining. It can be interpreted as being part of a member. In addition, the metal disposed on the surface layer of DBC or DBA is a part of the electrode substrate, and the layer formed by alloying the metal and Sn can be interpreted as a part of the semiconductor device bonding member. it can.
（合金化と接合の工程）
　半導体デバイス接合部材１０の作製方法の一つは粉末法である。これは、AgとSnの粉末の混合物や、Ag粒子にSnメッキを施した粉末を焼結し、被接合部材（半導体デバイスや電極基板）と接合する方法である。他の一つは骨格法である。これは、AgやAg3Snの少ないAgSn合金からなる板材を焼結体で作製しておく、あるいは板材にレーザ加工、ドリル加工、エッチング加工、パンチング加工、網状加工等を施すことによりボイドを有する骨格を作っておくというものであり、その骨格に溶融したSnを含浸させる等によりAgと反応させ、被接合部材（半導体デバイスや電極基板）と接合する方法である。また、粉末法と骨格法を適宜に組み合わせてもよい。その他、第１金属と第２金属の反応には、焼結法、含浸法、部分反応接合法等、適宜のものを用いればよい。 (Process of alloying and joining)
One of the methods for producing the semiconductor device joining member 10 is a powder method. This is a method in which a mixture of Ag and Sn powders or a powder obtained by Sn-plating Ag particles is sintered and bonded to a member to be bonded (semiconductor device or electrode substrate). The other is the skeleton method. This has a void by making a plate material made of AgSn alloy with less Ag or Ag 3 Sn in a sintered body, or by subjecting the plate material to laser processing, drill processing, etching processing, punching processing, reticulation processing, etc. The skeleton is made in advance, and the skeleton is made to react with Ag by impregnating the skeleton with molten Sn or the like, and is joined to a member to be joined (semiconductor device or electrode substrate). Further, the powder method and the skeleton method may be appropriately combined. In addition, for the reaction between the first metal and the second metal, a suitable method such as a sintering method, an impregnation method, or a partial reaction joining method may be used.
　粉末法を用いる場合、例えば粒径が10nm～0.3mmの範囲のものを用いることができる。使用する粉末の大きさは均一であってもよく、あるいは異なる粒径の混合粉末であってもよい。骨格その作製方法には焼結法等、適宜のものを用いればよい。作製方法の詳細は後述するが、例えば、真空、水素+窒素、水素雰囲気において750℃以上で加熱焼結することによりボイドを含んだもの骨格を作製することができる。 When using the powder method, it is possible to use, for example, particles with a particle size in the range of 10 nm to 0.3 mm. The powder used may have a uniform size, or may be a mixed powder having different particle sizes. The skeleton may be produced by an appropriate method such as a sintering method. Although details of the manufacturing method will be described later, for example, a skeleton containing voids can be manufactured by heating and sintering at 750° C. or higher in vacuum, hydrogen+nitrogen, and hydrogen atmosphere.
　板状のものを用いる場合、例えば厚さ0.02～0.3mmのものを用いることができる。また、板状のものを用いる場合には、得ようとする半導体デバイス接合部材の内部に形成する空隙（ボイド）率に応じた大きさ及び数の孔を作っておく。 When using a plate-shaped product, it is possible to use, for example, a product having a thickness of 0.02 to 0.3 mm. When a plate-shaped member is used, holes having a size and number corresponding to the void ratio to be formed inside the semiconductor device bonding member to be obtained are formed.
　ダイボンドによる半導体デバイス等の接合には必ずしも低温低圧という条件が最適であるとは限らない。ダイボンドの組成、対象とする半導体モジュールに適した性能や品質を確保することが必要である。 The low temperature and low pressure conditions are not always optimal for joining semiconductor devices and the like by die bonding. It is necessary to secure the performance and quality suitable for the composition of the die bond and the target semiconductor module.
　加圧焼結溶浸法は、Ag、Sn等の混合粉末、あるいは予め孔を形成したAg板を使用し、Snを溶かして加圧しながら合金化しつつ、半導体デバイスと冷却器を接合するものである。また、溶融反応法は、Agのスケルトンの上下に配置したSnを溶かして合金化しながら半導体デバイスや電極基板を接合するものであり、低い加圧力で目標を達成することができる。さらに、Ag板Sn反応法は、孔を形成したAg板やAg網を1乃至複数、層状に配置したものの上下にSnを配置し、そのSnを溶かしAgと反応させて合金化しつつ、半導体デバイスや電極基板を接合するものである。これにより、最も高い強度のAgSn合金が得られる。また、低い加圧力で目標を達成することができる。また、合金の表面を平滑化したり被接合物との接合性を向上したりするために、作成した合金の表面に1乃至複数の、Ag又は／及びSnからなるメッキ層を設けてもよい。Ag板Sn反応法では、半導体デバイス接合部材の表面及び裏面に合金からなる層が形成され、それらに挟まれた中央部にはAgのみからなり空隙率が高い層が形成されうる。なお、上記各方法はいずれも、上述した低温低圧溶融反応接合法として用いることができる。 The pressure sintering infiltration method uses a mixed powder of Ag, Sn, etc., or an Ag plate with holes formed in advance, and melts Sn and alloys while pressurizing, while joining the semiconductor device and the cooler. is there. In the melting reaction method, the semiconductor devices and electrode substrates are joined while melting and alloying Sn arranged above and below the skeleton of Ag, and the target can be achieved with a low pressure. Further, the Ag plate Sn reaction method is a semiconductor device in which one or more Ag plates or Ag nets having holes are arranged on top and bottom of a layered one, and the Sn is melted and reacted with Ag to form an alloy. And an electrode substrate. This gives the highest strength AgSn alloy. Further, the target can be achieved with a low pressure. In addition, in order to smooth the surface of the alloy and improve the bondability with the object to be bonded, one or more plating layers made of Ag or/and Sn may be provided on the surface of the prepared alloy. In the Ag plate Sn reaction method, a layer made of an alloy is formed on the front surface and the back surface of the semiconductor device bonding member, and a layer having a high porosity made of only Ag can be formed in the central portion sandwiched between them. Each of the above methods can be used as the above-mentioned low temperature low pressure fusion reaction joining method.
　孔を形成した板状物や網状物の第１金属からなる骨格を用いる場合には、例えば骨格の上下に第２金属の板材を配置したり、骨格の表面に第２金属をめっき処理したりすることにより第２金属を配することもできる。また、粉末状の第１金属を用いる場合には、第１金属の粉末と第２金属の粉末を混合して焼結し、混合粉末のスケルトンを作製してもよい。これにより効果的に第２金属を第１金属にSnを含浸させることができる。この場合には、半導体デバイス接合部材が全体にわたって合金化しやすくなる。また、半導体デバイスの接合面及び／又は基板（電極基板等）の接合面に第２金属をめっきし、上記骨格の上下にそれらを配置してもよい。なお、半導体デバイスの接合面及び／又は基板の接合面に第２金属をめっきする前の段階で、該接合面にNi、Ag、Ti等からなる１乃至複数のめっき層が形成されていてもよい。特に、Niめっき層を形成しておくことによりAgSn合金との接合性を高めることができる。 When using a skeleton made of a plate-like or net-like first metal having holes, for example, a plate material of the second metal is arranged above and below the skeleton, or the surface of the skeleton is plated with a second metal. By doing so, the second metal can be arranged. When the powdery first metal is used, the powder of the first metal and the powder of the second metal may be mixed and sintered to produce a skeleton of the mixed powder. As a result, the second metal and the first metal can be effectively impregnated with Sn. In this case, the entire semiconductor device bonding member is likely to be alloyed. Further, the second metal may be plated on the bonding surface of the semiconductor device and/or the bonding surface of the substrate (electrode substrate or the like), and they may be arranged above and below the skeleton. Even if one or a plurality of plating layers made of Ni, Ag, Ti or the like are formed on the bonding surface of the semiconductor device and/or the bonding surface of the substrate before the second metal is plated on the bonding surface. Good. In particular, by forming the Ni plating layer, the bondability with the AgSn alloy can be improved.
　金属の接合、反応、焼結、含浸等を行う際には、温度、圧力、保持時間等の条件を最適化し、接合状態が良好な合金を作製することが基本であり、これは、本実施例のように意図的にボイドを形成させる場合においても同様である。含浸法により第１金属と第２金属を主成分とする合金からなる層を含む半導体デバイス接合部材を作製する場合、溶融して第２金属が毛細管現象によって第１金属からなるスケルトンの孔に流入するため、含浸時の荷重は半導体デバイスの自重程度で十分である。溶解した第２金属が第１金属の孔に入り込むとその孔の表面から第１金属が徐々に溶解し、第１金属の骨格の内部に第２金属が含浸する。骨格の表面でも同様に、第１金属が徐々に溶解して第２金属が含浸していく。また、高い精度で厚さを制御する場合には圧力を印加すればよい。一方、過剰な圧力を印加すると半導体素子が損傷する等の心配があることから、印加する圧力は5MPa未満であることが好ましく、0.5～4.0Mpa範囲であることがより好ましい。含浸により溶融した第２金属が骨格を構成する第１金属と反応して合金化し、これによって半導体デバイスと電極基板が高強度でダイボンディングされる。また、第１金属と第２金属の混合粉末を用いた場合にも第２金属の溶融により合金化し、これによって半導体デバイスと電極基板が高強度でダイボンディングされる。 When performing metal joining, reaction, sintering, impregnation, etc., it is fundamental to optimize the conditions such as temperature, pressure, holding time, etc. to produce an alloy with a good joining state. The same applies to the case where a void is intentionally formed as in the example. When a semiconductor device bonding member including a layer made of an alloy containing a first metal and a second metal as a main component is produced by an impregnation method, the second metal is melted and flows into a skeleton hole made of the first metal by a capillary phenomenon. Therefore, it is sufficient that the load during impregnation is about the weight of the semiconductor device. When the dissolved second metal enters the hole of the first metal, the first metal gradually dissolves from the surface of the hole, and the second metal is impregnated inside the skeleton of the first metal. Similarly, on the surface of the skeleton, the first metal gradually dissolves and is impregnated with the second metal. Further, when the thickness is controlled with high accuracy, pressure may be applied. On the other hand, if excessive pressure is applied, the semiconductor element may be damaged, so the applied pressure is preferably less than 5 MPa, more preferably 0.5 to 4.0 MPa. The second metal melted by the impregnation reacts with the first metal forming the skeleton to be alloyed, whereby the semiconductor device and the electrode substrate are die-bonded with high strength. Also, when the mixed powder of the first metal and the second metal is used, the second metal is melted to be alloyed, whereby the semiconductor device and the electrode substrate are die-bonded with high strength.
　本発明において半導体デバイス接合部材に含まれる、合金からなる層融点を500℃以上としているのは、半導体デバイスの動作時に局所的に熱が発生する場合があるためである。また、AgSn合金の場合、融点が500℃以下である合金では粒界に脆いAg3Sn粒子が凝集し、ヒートサイクルテストにおいて割れや欠け等の損傷が生じたり、熱伝導率等の特性が低下したりするという問題も生じる。AgとSnの状態図から分かるように、また後述する実施例と比較例に示すとおり、AgSn合金の場合、Snの含有率が2wt%以上20wt%以下であれば、低温融合現象を利用して上述した所要の特性を有する半導体デバイス接合部材が得られる。 In the present invention, the melting point of the alloy layer included in the semiconductor device joining member is 500° C. or higher because heat may be locally generated during the operation of the semiconductor device. Also, in the case of AgSn alloy, brittle Ag 3 Sn particles agglomerate at grain boundaries in alloys with a melting point of 500°C or lower, causing damage such as cracks and chips in the heat cycle test, and lowering properties such as thermal conductivity. There is also the problem of As can be seen from the phase diagram of Ag and Sn, and as shown in Examples and Comparative Examples described later, in the case of AgSn alloy, if the Sn content is 2 wt% or more and 20 wt% or less, by utilizing the low temperature fusion phenomenon A semiconductor device bonding member having the above-mentioned required characteristics can be obtained.
　ダイボンディングは、真空雰囲気、非酸化雰囲気、窒素雰囲気、水素雰囲気、水素窒素雰囲気で行うことができる。Snの融点は235℃であるが、Agと反応させて合金化することによって、AgSn合金の再融点は500℃以上になる。 Die bonding can be performed in a vacuum atmosphere, non-oxidizing atmosphere, nitrogen atmosphere, hydrogen atmosphere, hydrogen nitrogen atmosphere. Although the melting point of Sn is 235° C., the re-melting point of AgSn alloy becomes 500° C. or higher by reacting with Ag to form an alloy.
（評価１：信頼性）
　本実施例では、半導体デバイスの自重を加えつつSnを溶融させて合金からなる層を形成した。その過程で、Snの一部が外周に出てくるため、その状態を管理することで接合の信頼性を確保した。 (Evaluation 1: Reliability)
In this example, Sn was melted while applying the own weight of the semiconductor device to form a layer made of an alloy. In the process, a part of Sn comes out to the outer circumference, so the reliability of the joining was secured by managing the state.
（評価２：耐熱評価）
　試験片を500℃に加熱し、接合部の溶解の有無を確認した。接合部に溶解が見られないものを合格とした。また、接合部に溶解が見られなかったものについて、ヒートサイクルテストを行った。 (Evaluation 2: Heat resistance evaluation)
The test piece was heated to 500° C., and it was confirmed whether or not the joint was melted. The one in which no dissolution was observed at the joint was regarded as acceptable. In addition, a heat cycle test was performed on a material in which dissolution was not observed in the bonded portion.
（評価３：ヒートサイクルテスト）
　後述の各実施例では、最高動作温度300℃の半導体デバイスの接合を想定したヒートサイクルテストを行った。ヒートサイクルテストでは、12mm四方、厚さ0.3mmのSiC半導体デバイスの接合面にNiとSnのめっき処理を施したものと、30mm四方、厚さ1.5mmのCu電極基板の接合面にNiとSnのめっき処理を施したものとを両面に配し、それぞれの接合面を厚さ0.2mmのダイボンドで接合したものを使用した。そして、-40℃への冷却と300℃への加熱を100回繰り返す毎に、接合部の状態を確認するというテストを、計3回（即ち、冷却と加熱を合計300回）行った。ヒートサイクルテストにおいて割れや欠けなどの問題が生じなかったものを合格、割れや欠けが生じたものを不合格とした。 (Evaluation 3: heat cycle test)
In each of the examples described below, a heat cycle test was performed assuming bonding of semiconductor devices with a maximum operating temperature of 300°C. In the heat cycle test, the bonding surface of the 12 mm square, 0.3 mm thick SiC semiconductor device was plated with Ni and Sn, and the bonding surface of the 30 mm square, 1.5 mm thick Cu electrode substrate was bonded with Ni and Sn. The one subjected to the plating treatment was placed on both sides, and each joining surface was joined with a die bond having a thickness of 0.2 mm. Then, every time the cooling to -40°C and the heating to 300°C were repeated 100 times, the test of confirming the state of the joint was performed a total of 3 times (that is, cooling and heating were performed 300 times in total). Those that did not cause problems such as cracks and chips in the heat cycle test were accepted, and those that had cracks and chips were rejected.
（評価４：熱伝導率）
　ヒートサイクルテストに合格したもの（以下、「合格品」と呼ぶ。）からレーザ加工機により直径10mm、厚さ2.0mmの試験片を切り出し、熱伝導測定器（アドバンス理工社製　FTC-RT）を用いたレーザーフラッシュ法により熱伝導率を測定した。また、この試験片とは別に、直径10mm、厚さ2.0mmのSiC比較片（片面にNiめっき層を設けたもの）及びCu比較片（片面にNiめっき層を設けたもの）を作製して上記同様に熱伝導率を測定した。そして、試験片の熱伝導率をSiC比較片及びCu比較片の熱伝導率と比較することにより試験片に含まれる半導体デバイス接合部材（ダイボンド）の熱伝導率を求めた。この評価では、熱伝導率120W/m・Kを基準とし、これ以上の熱伝導率を有するものを合格とした。 (Evaluation 4: thermal conductivity)
A test piece with a diameter of 10 mm and a thickness of 2.0 mm was cut out from the one that passed the heat cycle test (hereinafter referred to as "passed product") with a laser processing machine, and a heat conduction measuring instrument (Advance Riko FTC-RT) was used. The thermal conductivity was measured by the laser flash method used. Separately from this test piece, a SiC comparison piece (having a Ni plating layer on one side) and a Cu comparison piece (having a Ni plating layer on one side) having a diameter of 10 mm and a thickness of 2.0 mm were prepared. The thermal conductivity was measured in the same manner as above. Then, the thermal conductivity of the semiconductor device bonding member (die bond) included in the test piece was obtained by comparing the thermal conductivity of the test piece with the thermal conductivity of the SiC comparative piece and the Cu comparative piece. In this evaluation, a thermal conductivity of 120 W/m·K was used as a standard, and one having a thermal conductivity of more than this was regarded as a pass.
（評価５：電気伝導率）
　SiCは半導体であり、ヒートサイクルテストに使用した試験片（SiC半導体デバイスとCu電極基板を接合したもの）のままでは電気伝導率を測定することが難しい。そこで、熱伝導率が120W/m・K以上であった試験片について、SiC半導体デバイスと同程度の線膨張係数（4.5ppm/K）を有するWの板材をSiC半導体デバイスに代えて使用した、電気伝導率測定用の試験片を作製した。そして、上記同様のヒートサイクルテストを行ったあと、電気伝導率を測定した。なお、SiC半導体デバイスを用いた試験片における合格品に対応する電気伝導率測定用の試験片は、いずれもヒートサイクルテストに合格した。 (Evaluation 5: electric conductivity)
Since SiC is a semiconductor, it is difficult to measure the electrical conductivity of the test piece used for the heat cycle test (a SiC semiconductor device and a Cu electrode substrate bonded together). Therefore, for the test piece having a thermal conductivity of 120 W/mK or more, a W plate material having a linear expansion coefficient (4.5 ppm/K) similar to that of the SiC semiconductor device was used instead of the SiC semiconductor device, A test piece for measuring electric conductivity was prepared. Then, after conducting a heat cycle test similar to the above, the electrical conductivity was measured. All the test pieces for electrical conductivity measurement corresponding to the passed products in the test pieces using the SiC semiconductor device passed the heat cycle test.
　電気伝導率の測定時には、レーザ加工機により直径10mm、厚さ2.0mmの試験片を切り出し、電気伝導率測定装置（(株)ナプソン社製　RT70V）を用いた四端子法により電気伝導率を測定した。また、この試験片とは別に、直径10mm、厚さ2.0mmのW比較片（片面にNiめっき層を設けたもの）及びCu比較片（片面にNiめっき層を設けたもの）を作製して上記同様に電気伝導率を測定した。そして、試験片の電気伝導率をW比較片及びCu比較片の電気伝導率と比較することにより、試験片の電気伝導率を求めた。この評価では、電気伝導率50%IACSを基準とし、これを以上の電気伝導率を有するものを合格とした。なお、電気伝導率の測定において広く用いられている、渦電流をシグマテスターで測定する方法も検討したが、本実施例の試験片のように、内部が複数の異なる構造体である場合の電気伝導率の測定には適さないと判断して四端子法により電気伝導率を測定した。 When measuring the electrical conductivity, a laser processing machine is used to cut out a test piece with a diameter of 10 mm and a thickness of 2.0 mm, and the electrical conductivity is measured by the four-terminal method using an electrical conductivity measuring device (RT70V manufactured by Napson Corporation). did. Separately from this test piece, a W comparison piece (having a Ni plating layer on one side) and a Cu comparison piece (having a Ni plating layer on one side) having a diameter of 10 mm and a thickness of 2.0 mm were prepared. The electrical conductivity was measured in the same manner as above. Then, the electrical conductivity of the test piece was determined by comparing the electrical conductivity of the test piece with the electrical conductivity of the W comparative piece and the Cu comparative piece. In this evaluation, an electric conductivity of 50% IACS was used as a standard, and a material having an electric conductivity of the above was regarded as acceptable. A method of measuring eddy currents with a sigma tester, which is widely used in the measurement of electrical conductivity, was also examined. The electrical conductivity was measured by the four-terminal method because it was judged that it was not suitable for the measurement of conductivity.
　次に、実施例１～１５の作製手順を説明する。各パラメータの値は実施例２に関する値を記載している。実施例１及び３～１５は、後掲の表２に示すように、適宜パラメータの値を変更して作製した。 Next, the manufacturing procedure of Examples 1 to 15 will be described. The value of each parameter is the value related to Example 2. Examples 1 and 3 to 15 were produced by appropriately changing the parameter values as shown in Table 2 below.
（実施例１～１５の作製手順）
　工程１：12mm四方、厚さ0.2mmのAg板材に、レーザ加工により、直径0.36mmの貫通孔を1mm四方につき1個開けたもの（以下、骨格と呼ぶ。）を作製した。
　工程２：30mm四方、厚さ1.5mmのCu板材の一方の表面（接合面）に厚さ2μmのNiめっき層を設け、その中央に、12mm四方、厚さ0.009mmのSnめっき層を設けたもの（以下、これを電極基板と呼ぶ）を作製した。
　工程３：12mm四方、SiC板材の一方の表面（接合面）に厚さ2μmのNiめっき層を設け、さらにその上に厚さ0.009mmのSnめっき層を設けたもの（以下、これを半導体デバイス板と呼ぶ）を作製した。
　工程４：電極基板、骨格、及び半導体デバイス板を順に重ねた積層体を作製した。
　工程５：積層体を真空雰囲気で300℃に加熱した後、300℃に保持し1MPaの圧力を印加し、5分間保持し徐冷した。
　工程６：上記処理により半導体デバイス板と電極基板を接合したものについて、耐熱試験、ヒートサイクルテスト、熱伝導率の測定、及び電気伝導率の測定を行った。 (Procedure of Examples 1 to 15)
Step 1: A 12 mm square Ag plate material having a thickness of 0.2 mm and one through hole having a diameter of 0.36 mm per 1 mm square was formed by laser processing (hereinafter referred to as a skeleton).
Process 2: A 30 μm square, 1.5 mm thick Cu plate material was provided with a 2 μm thick Ni plating layer on one surface (joint surface), and a 12 mm square, 0.009 mm thick Sn plating layer was provided in the center thereof. The thing (henceforth this is called an electrode substrate) was produced.
Process 3: 12 mm square, a 2 μm-thick Ni plating layer is provided on one surface (bonding surface) of the SiC plate material, and a 0.009 mm-thick Sn plating layer is further provided thereon (hereinafter referred to as a semiconductor device. Called a plate).
Step 4: A laminated body was produced in which the electrode substrate, the skeleton, and the semiconductor device plate were sequentially stacked.
Step 5: The laminate was heated to 300° C. in a vacuum atmosphere, kept at 300° C., a pressure of 1 MPa was applied, kept for 5 minutes and gradually cooled.
Step 6: A heat resistance test, a heat cycle test, a measurement of thermal conductivity, and a measurement of electrical conductivity were performed on the semiconductor device plate and the electrode substrate joined by the above treatment.
　下記の表２に記載のボイド率について、以下、説明する。なお、分かりやすくするために、ここでは、骨格の大きさを1mm四方として説明する。 The void ratios listed in Table 2 below are explained below. For the sake of clarity, the size of the skeleton will be described here as 1 mm square.
　実施例１ではボイド率が5vol%、Snの含有率が3.7wt%（5vol%）である。
　1mm四方、厚さ0.2mmの板材に10vol%のボイドを形成すると、Agの体積は1mm×1mm×0.2mm×0.9=0.18mm3、重量は1.888μg（Agの密度：10.49g/cm-3）となる。実施例１では、電極基板と半導体デバイス板のそれぞれの接合面に0.005mm厚さのSn層を形成し、Snの体積を1mm×1mm×0.005mm×2=0.01mm3、重量を0.073μg（Snの密度：7.31g/cm-3）とする。AgとSnの体積の合計は0.19mm3、重量の合計は1.961μgとなる。ここで、Snの含有率は0.01/0.19=0.052（5.2vol%）、0.073/1.961=0.037（3.7wt%）となる。 In Example 1, the void ratio is 5 vol% and the Sn content is 3.7 wt% (5 vol%).
When 10vol% voids are formed on a 1mm square, 0.2mm thick plate, the Ag volume is 1mm × 1mm × 0.2mm × 0.9=0.18mm 3 , and the weight is 1.888μg (Ag density: 10.49g/cm -3 ). In Example 1, a 0.005 mm-thick Sn layer was formed on each bonding surface of the electrode substrate and the semiconductor device plate, the volume of Sn was 1 mm×1 mm×0.005 mm×2=0.01 mm 3 , and the weight was 0.073 μg ( Sn density: 7.31 g/cm -3 ). The total volume of Ag and Sn is 0.19 mm 3 , and the total weight is 1.961 μg. Here, the Sn content is 0.01/0.19=0.052 (5.2 vol%) and 0.073/1.961=0.037 (3.7 wt%).
　骨格に形成されているボイドの体積は1mm×1mm×0.2mm×0.1=0.02mm3である。これに、体積0.01mm3のSnが導入されてAgSn合金が形成されることから、最終的に残存するボイドは0.01mm3となる。従って、ボイドを含む体積が0.2mm3である半導体デバイス接合部材の内部のボイド率は5vol%となる。 The volume of voids formed in the skeleton is 1 mm × 1 mm × 0.2 mm × 0.1 = 0.02 mm 3 . Since a volume of 0.01 mm 3 of Sn is introduced into this to form an AgSn alloy, the finally remaining void becomes 0.01 mm 3 . Therefore, the void ratio inside the semiconductor device bonding member having a volume including voids of 0.2 mm 3 is 5 vol %.
　以上のとおり、Snの含有率が3.7wt%（5vol%）、ボイド率が5vol%の半導体デバイス接合部材を作製するには、1mm四方、厚さ0.2mmの板材に10%のボイドを形成し、厚さ0.005mmのSn層を形成すれば良いことが分かる。板材に形成するボイドを円柱形の貫通孔と近似すると、径が0.36mmである貫通孔を1mm四方につき1個、設ければよいことが分かる。 As described above, in order to manufacture a semiconductor device bonding member with a Sn content of 3.7 wt% (5 vol%) and a void ratio of 5 vol%, a 10% void is formed on a plate material with a 1 mm square and a thickness of 0.2 mm. It can be seen that it is sufficient to form a 0.005 mm thick Sn layer. If the voids formed in the plate material are approximated to cylindrical through holes, it is understood that one through hole having a diameter of 0.36 mm should be provided for each 1 mm square.
　実施例２ではボイド率が10vol%、Snの含有率が7.2wt%（10vol%）である。
　1mm四方、厚さ0.2mmの板材に19vol%のボイドを形成すると、Agの体積は1mm×1mm×0.2mm×0.81=0.162mm3、重量は1.699μg（Agの密度：10.49g/cm-3）となる。実施例２では、電極基板と半導体デバイス板のそれぞれの接合面に0.009mm厚さのSn層を形成し、Snの体積を1mm×1mm×0.009mm×2=0.018mm3、重量を0.132μg（Snの密度：7.31g/cm-3）とする。AgとSnの体積の合計は0.18mm3、重量の合計は1.831μgとなる。ここで、Snの含有率は0.018/0.18=0.1（10.0vol%）、0.132/1.831=0.072（7.2wt%）となる。 In Example 2, the void ratio is 10 vol% and the Sn content is 7.2 wt% (10 vol%).
If a 19 vol% void is formed on a 1 mm square, 0.2 mm thick plate material, the Ag volume will be 1 mm × 1 mm × 0.2 mm × 0.81 = 0.162 mm 3 , and the weight will be 1.699 μg (Ag density: 10.49 g/cm -3 ). In Example 2, a 0.009 mm-thick Sn layer was formed on each bonding surface of the electrode substrate and the semiconductor device plate, the volume of Sn was 1 mm×1 mm×0.009 mm×2=0.018 mm 3 , and the weight was 0.132 μg ( Sn density: 7.31 g/cm -3 ). The total volume of Ag and Sn is 0.18 mm 3 , and the total weight is 1.831 μg. Here, the Sn content is 0.018/0.18=0.1 (10.0 vol%) and 0.132/1.831=0.072 (7.2 wt%).
　骨格に形成されているボイドの体積は1mm×1mm×0.2mm×0.19=0.038mm3である。これに、体積0.018mm3のSnが導入されAgSn合金が形成されることから、最終的に残存するボイドは0.02mm3となる。従って、ボイドを含む体積が0.2mm3である半導体デバイス接合部材の内部のボイド率は10vol%となる。 The volume of voids formed in the skeleton is 1 mm × 1 mm × 0.2 mm × 0.19 = 0.038 mm 3 . This, because the Sn volume 0.018 mm 3 is AgSn alloy is introduced is formed, voids which finally remains is the 0.02 mm 3. Therefore, the void ratio inside the semiconductor device bonding member having a volume including voids of 0.2 mm 3 is 10 vol %.
　以上のとおり、Snの含有率が7.21wt%（10vol%）、ボイド率が10vol%の半導体デバイス接合部材を作製するには、1mm四方、厚さ0.2mmの板材に19vol%のボイドを形成し、厚さ0.009mmのSn層を形成すれば良いことが分かる。このボイドを円柱形の貫通孔と近似すると、径が0.35mmである貫通孔を1mm四方につき1個、設ければよいことが分かる。 As described above, in order to fabricate a semiconductor device bonding member with a Sn content of 7.21 wt% (10 vol%) and a void ratio of 10 vol%, 19 vol% voids were formed on a 1 mm square, 0.2 mm thick plate material. It can be seen that it is only necessary to form a 0.009 mm thick Sn layer. If this void is approximated to a cylindrical through hole, it will be understood that one through hole having a diameter of 0.35 mm should be provided for each 1 mm square.
　ここでは、実施例１及び２についてのみ詳述したが、他の実施例（及び比較例）についても上記同様の方法で貫通孔の径を決めればよい。なお、実施例９の骨格（表２に記載のAgCu）は、Agを30重量パーセント、Cuを70パーセント含んだ合金である。また、本実施例では、空隙の割合を先に決めておき、使用する材料の大きさや、予め形成する貫通孔の大きさを決定したが、作成後の半導体デバイス接合部材が有する空隙（ボイド）の割合は、種々の計測によって評価することができる。例えば、半導体デバイス接合部材の断面を電子顕微鏡等により撮影し、その断面に現れている空隙の割合を代表値として半導体デバイス接合部材が有する空隙の割合を評価したり、あるいは合金完成度（空隙がない合金の理論密度と作製した半導体デバイス接合部材の密度の比）から半導体デバイス接合部材が有する空隙の割合を評価したりすることができる。 Here, only the first and second embodiments are described in detail, but the diameters of the through holes may be determined in the same manner as above for the other embodiments (and comparative examples). The skeleton of Example 9 (AgCu described in Table 2) is an alloy containing 30% by weight of Ag and 70% of Cu. In addition, in this embodiment, the ratio of the voids is determined in advance, and the size of the material to be used and the size of the through-hole to be formed in advance are determined. However, the voids (voids) of the semiconductor device bonding member after creation are determined. The ratio of can be evaluated by various measurements. For example, the cross section of the semiconductor device bonding member is photographed by an electron microscope or the like, and the ratio of the voids included in the semiconductor device bonding member is evaluated by using the ratio of the voids appearing in the cross section as a representative value. The ratio of voids included in the semiconductor device bonding member can be evaluated from the theoretical density of the non-alloy and the density of the manufactured semiconductor device bonding member.
　作製した実施例１～１５とそれらの評価結果、及び比較のために作製した比較例１～９とそれらの評価結果を表２に示す。比較例１では半導体デバイス及び電極基板と接合することができず、また、比較例６では粉末が焼結されなかったため、いずれも試験片を作製することができなかった。また、比較例２～５、７～９では試験片を作製することはできたが、500℃に加熱すると接合部に溶解が見られたため、ヒートサイクルテストを行わなかった。一方、実施例１～１５ではいずれも、500℃に加熱しても接合部に溶融は見られず、またヒートサイクルテスト後の熱伝導率が120W/m・K以上、電気伝導率が50%IACS以上となった。
Figure JPOXMLDOC01-appb-T000002
 Table 2 shows the produced Examples 1 to 15 and their evaluation results, and the Comparative Examples 1 to 9 produced for comparison and their evaluation results. In Comparative Example 1, the semiconductor device and the electrode substrate could not be joined, and in Comparative Example 6, the powder was not sintered, so that neither test piece could be produced. Further, in Comparative Examples 2 to 5 and 7 to 9, test pieces could be produced, but when the temperature was raised to 500° C., melting was observed in the joint portion, and therefore the heat cycle test was not performed. On the other hand, in each of Examples 1 to 15, no melting was observed in the joint even when heated to 500° C., the thermal conductivity after the heat cycle test was 120 W/m·K or more, and the electrical conductivity was 50%. More than IACS.
Figure JPOXMLDOC01-appb-T000002
　以上、説明したように、上記各実施例の半導体デバイス接合部材は、最高動作温度が300℃に達する半導体デバイスを基板に接合する際に求められる要件を満たしている。従来、半導体デバイス接合部材の内部のボイドは欠陥であるとみなされ、ボイドのない材料開発が進められてきたが、本発明によって、ボイドが熱応力の緩和に有効であることが見出された。 As described above, the semiconductor device bonding member of each of the above-described embodiments satisfies the requirements required when bonding a semiconductor device having a maximum operating temperature of 300° C. to a substrate. Conventionally, voids inside semiconductor device bonding members have been considered to be defects, and void-free materials have been developed, but the present invention has found that voids are effective in alleviating thermal stress. ..
　上記実施例はいずれも具体的な実施形態の例示であって、本発明の趣旨に沿って適宜に変更することができる。例えば、作製時に印加する温度、圧力等の条件によって、作製後の半導体デバイス接合部材の特性が異なることから、上記の各実施例におけるSnの含有率の範囲及び作製時の温度圧力条件は、半導体デバイス接合部材に求められる所要の特性を満たす限りにおいて適宜に変更することができる。 All of the above examples are exemplifications of specific embodiments, and can be appropriately modified in accordance with the spirit of the present invention. For example, since the characteristics of the semiconductor device bonding member after fabrication differ depending on conditions such as temperature and pressure applied during fabrication, the range of the Sn content in each of the above examples and the temperature and pressure conditions during fabrication are semiconductors. It can be appropriately changed as long as the required characteristics required for the device joining member are satisfied.
　また、この半導体デバイス接合部材はパワー半導体モジュールである垂直通電型のIGBTにおいて半導体デバイスを電極基板と接合して通電する際に好適に用いることができる。また、それ以外の平面通電型の半導体分野（通信、演算、メモリ、レーザ、LED、センサー等）のモジュールにおいて半導体デバイスを放熱基板（無通電）と接合する際にも好適に使用することができる。さらに、SiC半導体デバイスに限らず、Si、GaN、GaAs等の半導体デバイスを搭載したIGBTモジュールにおいても好適に用いることができる。特に、上記のような接合の対象物の線膨張係数の差が大きい場合に、本発明に係る半導体デバイス接合部材を好適に用いることができる。本発明に係る半導体デバイス接合部材は、今後の半導体モジュールの小型高性能化やコストダウンに大きく貢献できるものである。さらに、上記の半導体モジュールを電動車や産業用機械に用いることで省エネを実現することもできる。なお、本願明細書では半導体モジュールを中心に説明したが、半導体パッケージ（半導体素子や集積回路を樹脂等で包み込んで周囲から防護するとともに、電力や電気信号の入出力を行うための接点となる端子や配線を設けた包装部材）についても同様に本発明に係る半導体デバイス接合部材を好適に用いることができる。 Moreover, this semiconductor device joining member can be suitably used when a semiconductor device is joined to an electrode substrate to conduct electricity in a vertical conduction type IGBT which is a power semiconductor module. Further, it can be suitably used also for bonding a semiconductor device to a heat dissipation board (non-energized) in a module in the other plane conduction type semiconductor fields (communication, arithmetic, memory, laser, LED, sensor, etc.). .. Further, not only the SiC semiconductor device but also the IGBT module having a semiconductor device such as Si, GaN or GaAs mounted thereon can be suitably used. In particular, when the difference between the linear expansion coefficients of the objects to be bonded as described above is large, the semiconductor device bonding member according to the present invention can be preferably used. INDUSTRIAL APPLICABILITY The semiconductor device joining member according to the present invention can greatly contribute to future miniaturization and high performance of semiconductor modules and cost reduction. Further, energy saving can be realized by using the above semiconductor module in an electric vehicle or an industrial machine. In the specification of the present application, the semiconductor module has been mainly described. However, a semiconductor package (a terminal that serves as a contact for wrapping a semiconductor element or an integrated circuit with resin or the like to protect it from the surroundings and inputting and outputting electric power and electric signals) Similarly, the semiconductor device joining member according to the present invention can be preferably used for a packaging member provided with or wiring.
１０…半導体デバイス接合部材
　１０１…骨格
　１０２…ボイド
１１…半導体デバイス
１２…電極基板 10... Semiconductor device joining member 101... Skeleton 102... Void 11... Semiconductor device 12... Electrode substrate

Claims (4)

  1. 　半導体デバイスの被接合面と該半導体デバイスが載置される基板の被接合面とを接合する半導体デバイス接合部材であって、
    　Ag、Cu、及びAuのうちの少なくとも1種類とSnとを主成分とし、融点が500℃以上である合金からなる層を含み、
    　内部に、総体積が全体の5パーセント以上40パーセント以下である複数の空隙を有し、
    　-40℃への冷却と300℃への加熱を300回繰り返すヒートサイクルテストを行った後の熱伝導率が120W/m・K以上、電気伝導率が50%IACS以上である
    　ことを特徴とする半導体デバイス接合部材。     A semiconductor device joining member for joining a joined surface of a semiconductor device and a joined surface of a substrate on which the semiconductor device is mounted,
    Ag, Cu, and at least one of Au and Sn as a main component, including a layer made of an alloy having a melting point of 500 ℃ or more,
    Inside, having a plurality of voids having a total volume of 5% or more and 40% or less,
    It is characterized by having a thermal conductivity of 120 W/mK or more and an electrical conductivity of 50% IACS or more after conducting a heat cycle test in which cooling to -40°C and heating to 300°C are repeated 300 times. Semiconductor device joining member.
  2. 　Snの含有率が、全体の2重量パーセント以上20重量パーセント以下であることを特徴とする請求項１に記載の半導体デバイス接合部材。 The semiconductor device joining member according to claim 1, wherein the Sn content is 2% by weight or more and 20% by weight or less of the whole.
  3. 　請求項１又は２に記載の半導体デバイス接合部材を含む半導体モジュール。 A semiconductor module including the semiconductor device bonding member according to claim 1.
  4. 　請求項１又は２に記載の半導体デバイス接合部材を含む半導体パッケージ。 A semiconductor package including the semiconductor device bonding member according to claim 1.
PCT/JP2019/049601 2018-12-18 2019-12-18 Semiconductor device joining member WO2020130039A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018236065A JP6516277B1 (en) 2018-12-18 2018-12-18 Semiconductor element bonding member
JP2018-236065 2018-12-18

Publications (1)

Publication Number Publication Date
WO2020130039A1 true WO2020130039A1 (en) 2020-06-25

Family

ID=66625606

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2019/049601 WO2020130039A1 (en) 2018-12-18 2019-12-18 Semiconductor device joining member

Country Status (2)

Country Link
JP (1) JP6516277B1 (en)
WO (1) WO2020130039A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6803106B1 (en) * 2020-09-18 2020-12-23 株式会社半導体熱研究所 Joining member of semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011114751A1 (en) * 2010-03-19 2011-09-22 古河電気工業株式会社 Conductive connecting member and manufacturing method of same
WO2012077228A1 (en) * 2010-12-10 2012-06-14 三菱電機株式会社 Lead-free solder alloy, semiconductor device, and method for manufacturing semiconductor device
JP2017157582A (en) * 2016-02-29 2017-09-07 株式会社東芝 Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011114751A1 (en) * 2010-03-19 2011-09-22 古河電気工業株式会社 Conductive connecting member and manufacturing method of same
WO2012077228A1 (en) * 2010-12-10 2012-06-14 三菱電機株式会社 Lead-free solder alloy, semiconductor device, and method for manufacturing semiconductor device
JP2017157582A (en) * 2016-02-29 2017-09-07 株式会社東芝 Semiconductor device

Also Published As

Publication number Publication date
JP6516277B1 (en) 2019-05-22
JP2020098848A (en) 2020-06-25

Similar Documents

Publication Publication Date Title
US10818585B2 (en) Copper/ceramic joined body, insulated circuit board, method for producing copper/ceramic joined body, and method for producing insulated circuit board
JP7115591B2 (en) Solder material for semiconductor devices
CN108290250B (en) Soldered joint
WO2017213207A1 (en) Ceramic circuit board and method for manufacturing ceramic circuit board
JP4964009B2 (en) Power semiconductor module
TWI581342B (en) Power module
CN107534034A (en) Conjugant, the power module substrate for carrying radiator, radiator and conjugant manufacture method, carry radiator power module substrate manufacture method, the manufacture method of radiator
JP6810915B2 (en) Solder material
WO2016088687A1 (en) Heat-dissipating substrate and method for manufacturing same
WO2020130039A1 (en) Semiconductor device joining member
CN106132909B (en) Ceramics-the manufacturing method of aluminium conjugant, the manufacturing method of power module substrate and ceramics-aluminium conjugant, power module substrate
WO2022059286A1 (en) Bonding member for semiconductor devices
WO2023276323A1 (en) Joining member
JP2016111328A (en) Heat-dissipating substrate, and semiconductor package and semiconductor module using the same
CN111822698A (en) Bonded structure and bonding material
Park High-power semiconductor die-attachment: Application of Zn with minor metal additions
JP2001267468A (en) Ceramic circuit board compound
JP2017098574A (en) Heat dissipating substrate and method of manufacturing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19898930

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 03/09/2021)

NENP Non-entry into the national phase

Ref country code: JP

122 Ep: pct application non-entry in european phase

Ref document number: 19898930

Country of ref document: EP

Kind code of ref document: A1