WO2020113440A1 - Procédé de stockage de données, dispositif flash, batterie intelligente et plateforme mobile - Google Patents

Procédé de stockage de données, dispositif flash, batterie intelligente et plateforme mobile Download PDF

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Publication number
WO2020113440A1
WO2020113440A1 PCT/CN2018/119230 CN2018119230W WO2020113440A1 WO 2020113440 A1 WO2020113440 A1 WO 2020113440A1 CN 2018119230 W CN2018119230 W CN 2018119230W WO 2020113440 A1 WO2020113440 A1 WO 2020113440A1
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Prior art keywords
storage unit
data
reserved
flash memory
memory device
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PCT/CN2018/119230
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English (en)
Chinese (zh)
Inventor
张华森
江帆
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深圳市大疆创新科技有限公司
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Priority to PCT/CN2018/119230 priority Critical patent/WO2020113440A1/fr
Priority to CN201880041365.5A priority patent/CN110799935A/zh
Publication of WO2020113440A1 publication Critical patent/WO2020113440A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Definitions

  • the embodiments of the present invention relate to the field of storage technologies, and in particular, to data storage methods, flash memory devices, smart batteries, and removable platforms.
  • the flash memory flash memory device has been widely used in the embedded field because it has the characteristics of erasable, programmable, no loss of power-off data and support for fast read access.
  • the flash memory device must first perform an erase operation when writing data, and the erase operation is based on the smallest erase unit (sector) as a unit. Since the number of erasures of each minimum erasing unit is limited, usually only 100,000 times, it is necessary to manage the erasure times of each minimum erasing unit, so as to ensure that the erasure times are balanced.
  • Flash, Transform, Layer, FTL Flash memory
  • the current Flash conversion layer needs to track and manage the number of erasures for each minimum erase unit, and requires more storage space and computing resources.
  • the Flash conversion layer For electronic devices using a single-chip MCU as a microprocessor, it is more difficult to implement the Flash conversion layer due to limited storage space and computing resources.
  • the embodiments of the present invention provide a data storage method, a flash memory device, a smart battery, and a removable platform.
  • an embodiment of the present invention provides a data storage method, including:
  • an embodiment of the present invention provides a flash memory device, including a processor, a memory, and a flash memory device.
  • the flash memory device is provided with a plurality of minimum storage units, and the processor implements after reading executable instructions from the memory:
  • an embodiment of the present invention provides a smart battery, including a processor, a memory, and a flash memory device.
  • the flash memory device is provided with a plurality of minimum storage units, and the processor implements after reading executable instructions from the memory:
  • an embodiment of the present invention provides a movable platform, including the smart battery described in the third aspect.
  • an embodiment of the present invention provides a readable storage medium that stores a number of computer instructions, and when the computer instructions are executed, the steps of the method of the first aspect are implemented.
  • the storage times of the flash memory device can be determined. Then, it is compared whether the storage times and the times threshold are equal, and then, it is determined whether to perform address conversion on the reserved storage unit in the flash memory device according to the comparison result.
  • FIG. 1 is a schematic flowchart of a data storage method according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a process for obtaining storage times provided by an embodiment of the present invention
  • FIG. 3 is another schematic flowchart of acquiring storage times provided by an embodiment of the present invention.
  • FIG. 4 is a schematic flowchart of writing data according to a storage state of a first storage unit according to an embodiment of the present invention
  • FIG. 5(a) to FIG. 5(b) are schematic diagrams of the results of writing data when the first storage unit provided by the embodiment of the present invention is not full of data;
  • 6(a) to 6(c) are schematic diagrams of a process of writing data when the first storage unit provided by the embodiment of the present invention has filled with data;
  • FIG. 7 is a schematic diagram of a process of writing data before address conversion provided by an embodiment of the present invention.
  • 8(a) to 8(f) are schematic diagrams of a process of writing data first and then address conversion provided by an embodiment of the present invention.
  • FIG. 9 is a schematic flowchart of address conversion before writing data according to an embodiment of the present invention.
  • FIG. 10(a) to FIG. 10(d) are schematic diagrams of a process of address conversion before writing data when the first storage unit is full of data provided by an embodiment of the present invention
  • 11(a) to 11(c) are schematic diagrams of a process of address conversion before writing data when the first storage unit is not full of data according to an embodiment of the present invention
  • FIGS. 13(a) to 13(d) are schematic diagrams of a process of simultaneously performing address conversion and writing data when the first storage unit is full of data according to an embodiment of the present invention
  • FIG. 14 is a schematic flowchart of a data storage method according to an embodiment of the present invention.
  • 15(a) to 15(b) are schematic diagrams of a process for excluding bad blocks from being a first storage unit according to an embodiment of the present invention
  • 16(a)-FIG. 16(b) are schematic diagrams of a process of removing bad blocks to reserve storage units provided by an embodiment of the present invention.
  • 17(a) to 17(b) are schematic diagrams of a process for excluding bad blocks from being a second storage unit according to an embodiment of the present invention
  • 18(a) to 18(h) are schematic process diagrams of a data storage method provided by an embodiment of the present invention.
  • FIG. 19 is a block diagram of a flash memory device provided by an embodiment of the present invention.
  • 20 is a block diagram of a smart battery provided by an embodiment of the present invention.
  • the conversion layer FTL needs to manage the erasure times of each minimum erasure unit to avoid some minimum erasure units reaching the erasure times soon The upper limit and part of the smallest erasing unit has not been erased or rarely erased.
  • the embodiments of the present invention provide a data storage method, which can use FTL software to perform equalization processing on the number of erasures of each minimum erasing unit in the flash memory device.
  • the inventive concept is to set a reserved storage unit and then store it in the flash memory. When the storage frequency of the device reaches the threshold of the number of times, address conversion is performed on the reserved storage unit. The address conversion avoids writing data to the same minimum storage unit multiple times, so that the probability of data storage in each minimum storage unit tends to be consistent, even if each minimum storage unit The number of erasures tends to be consistent to achieve a balanced effect.
  • mapping relationship between the logical address (LA) and the physical address (PA) may be stored in the flash memory device in advance.
  • the physical address refers to the first address of the smallest storage unit
  • the logical address refers to the first address of the logical block that has a mapping relationship with the smallest storage unit.
  • mapping relationship including the logical address and the physical address may be stored in any minimum storage unit in the flash memory device.
  • the mapping relationship is stored in the last smallest storage unit of the flash memory device.
  • the technician can also store the mapping relationship in an external storage, cloud, etc., and in the case where the solution of this embodiment can be implemented, the corresponding solution falls within the protection scope of the present application.
  • the minimum storage unit refers to the smallest physical area (ie, the minimum erase unit) that can be operated each time the flash memory device is erased, for example, 4K bits.
  • the technician can also adjust the size of the minimum storage unit according to the specific scenario, and the corresponding solution falls within the protection scope of the present application.
  • FIG. 1 is a schematic flowchart of a data storage method according to an embodiment of the present invention.
  • a data storage method includes steps 101 to 103, where:
  • step 101 if a data storage request is received, the number of storage times of the flash memory device is determined.
  • the FTL software in the flash memory device can interact with the application software.
  • the user can select a location to store data through the application software, and the location may include one logical address or multiple logical addresses.
  • the process of writing data to each logical address still starts from the first logical address, which is similar to the writing scheme of one logical address, so the subsequent embodiment chooses a scenario description scheme of logical addresses .
  • the flash memory device may receive the data storage request of the application software.
  • the data storage request includes a first logical address, and the first logical address may be mapped to a physical address, and the physical address represents a head address of a minimum storage unit, and may also indicate head addresses of a plurality of minimum storage units.
  • the FTL software each time a data storage request is received, the FTL software records the data storage request or modifies the number of times the flash memory device has stored data, so that the number of times the flash memory device is stored can be determined. It should be noted that when determining the storage times, the records can be obtained first, and then the storage times can be determined in conjunction with the data storage request; the data storage requests can also be recorded first, and then the storage times of the flash memory device can be determined. Technicians can make settings according to specific scenarios, which are not limited here.
  • the storage times may include: the number of times data has been written to the flash memory device from the perspective of the storage device.
  • determining the storage times of the flash memory device may include:
  • the FTL software adjusts the recorded storage times (corresponding to step 201).
  • the adjustment method can be to record the data storage request, and then count the data storage request that has been recorded, so as to obtain the storage times; or add 1 to the previous storage times, and use the adjusted times as the determined storage times. Then, the recorded storage times are read to obtain the storage times of the flash memory device (corresponding to step 202).
  • the storage times may further include: from the perspective of the smallest storage unit, the number of times data has been written to the first storage unit.
  • determining the storage times of the flash memory device may include:
  • the first logical address is obtained in the data storage request, and the first logical address refers to a logical address that the user desires to write data.
  • the FTL software adjusts the storage times of the first logical address in the data storage request, and the storage times of the first logical address refers to the number of times the data has been written in the first logical address (corresponding to step 301). Then, the FTL software reads the storage times of the first logical address in the data storage request to obtain the storage times of the flash memory device (corresponding to step 302).
  • step 102 the stored number of times is compared with a preset number of times threshold to obtain a comparison result.
  • the threshold of times can be set in advance, and the threshold of times can be adjusted according to the specifics, for example, according to empirical values, for example, according to the statistics of big data, the longest life of the flash memory device or the minimum storage unit
  • the threshold value of the number of times corresponding to the same erasure times, the similarity, or the smallest difference corresponds to the threshold number of times in this embodiment.
  • the technician can also set the threshold of the number of times according to other methods. In the case where the scheme of the present application can be realized, the corresponding scheme falls within the protection scope of the present application.
  • the threshold of the number of times may be stored in any minimum storage unit in the flash memory device.
  • the number of times threshold is stored in the last smallest storage unit of the flash memory device.
  • the FTL software can compare the storage times and the threshold of the times to obtain a comparison result.
  • the comparison result may include that the storage times and the threshold are equal, or the storage times and the thresholds are not equal.
  • the FTL software when the number of storage times is equal to the threshold of the number of times, in this embodiment, the FTL software also clears the number of storage times.
  • the method of clearing may include deleting the recorded storage data storage request, marking the recorded storage data storage request, and resetting the storage frequency variable to zero.
  • step 103 it is determined according to the comparison result whether to perform address conversion on the reserved storage unit in the flash memory device.
  • the FTL software may determine whether to perform address conversion on the reserved storage unit in the flash memory device according to the comparison result, which may include:
  • the comparison result is that the number of storage times is not equal to the number of times threshold, it is determined to maintain the current mapping relationship of the storage unit and store the data to the first storage unit mapped to the first logical address in the data storage request.
  • maintaining the current mapping relationship of the reserved storage unit means that no address conversion is performed on the mapping relationship between the reserved address and the reserved storage unit.
  • the FTL software stores the data to the first storage unit mapped to the first logical address in the data storage request, referring to FIG. 4, may include:
  • the FTL software may determine the storage state of the first storage unit, where the storage state may include data indicating that the first storage unit is not full and data indicating that the first storage unit is full (corresponding to step 401).
  • the FTL software determines whether the storage status indicates that the first storage unit is not full of data or that the first storage unit is full of data (corresponding to step 402).
  • the FTL software After that, if the storage status indicates that the first storage unit is not full of data, the FTL software writes the data to the tail of the stored data (corresponding to step 403), that is, directly writes data to the first storage unit, without the need for the first storage
  • the cell is erased. 5(a) to 5(b), taking the first logical address as the first logical address LA0 in the logical address space as an example, the FTL software determines that the data XX0 already stored in the first storage unit PA1 and the data XX0 The size of is smaller than the size of the first storage unit PA1, that is, the first storage unit PA1 is not full of data, the FTL software writes data from the end of the data XX0, and obtains the result shown in FIG. 5(b).
  • the FTL software erases the first storage unit, and then writes data to the first storage unit (corresponding to step 404). 6(a) to 6(c), continue to take the first logical address as the first logical address LA0 of the logical address space as an example, the FTL software determines the data XX1 already stored in the first storage unit PA1, and the data The size of XX1 is equal to the size of the first storage unit PA1, that is, the first storage unit PA1 has been filled with data, FTL software erases the data XX1 in the first storage unit PA1, using FF to indicate that no data is stored, the result is shown in Figure 6(b ) As shown. Then, the FTL software writes data to the first storage unit PA1, and the result is shown in FIG. 6(c).
  • FIG. 5(a) to FIG. 5(b) and FIG. 6(a) to FIG. 6(c) are shown by adding groups and underlining.
  • Scenario 1 If the result of the comparison is that the number of storage times is equal to the threshold of number of times, then it is determined to perform address conversion on the reserved storage unit. Address translation can include the following methods:
  • the FTL software writes data to the first storage unit (corresponding to step 701).
  • the scenario of writing data may consider that the first storage unit has full data or not full data, see FIG. 5(a ) To FIG. 5(b) and FIG. 6(a) to FIG. 6(c), which will not be repeated here.
  • the FTL software erases the reserved storage unit and copies the data in the first storage unit to the reserved storage unit (corresponding to step 702).
  • the FTL software maps the first logical address to the reserved storage unit and the reserved address to the first storage unit to complete the address conversion (corresponding to step 703).
  • FTL software erases the first memory cell PA1.
  • Data XX1 becomes data FF, and the result is shown in Figure 8(b).
  • the FTL software writes data into the first storage unit PA1, and the result is shown in FIG. 8(c).
  • the FTL software erases the reserved memory cell PA0, and the data in the reserved memory cell PA0 changes from XX2 to FF.
  • FIG. 8(d) The result is shown in FIG. 8(d).
  • the FTL software to copy the data in the first storage unit PA1 PA0 to retain the storage unit, the reservation data storage unit PA0 from FF to the data, the results shown in FIG 8 (e) in FIG.
  • the FTL software maps the first logical address LA0 to the reserved storage unit PA0 and the reserved address RS to the first storage unit PA1 to complete the address conversion. The result is shown in FIG. 8(f).
  • FIG. 8(a) to FIG. 8(f) are shown by adding groups and underlining.
  • the FTL software maps the first logical address to the reserved storage unit and the reserved address to the first storage unit to complete address conversion (corresponding to step 901). Then, the FTL software stores the data in the reserved storage unit mapped to the first logical address (corresponding to step 902).
  • step 902 it may include a case: Case 1, if the reserved storage unit is not full of data, data is written from the end of the stored data. Case 2: If the reserved storage unit is full of data, the reserved storage unit is erased and data is written.
  • FIG. 10(a) In the case where the reserved storage unit is full of data, refer to FIG. 10(a), continue to map the reserved address RS to the reserved storage unit PA0, and the first logical address LA0, and take the data XX1 stored in the first storage unit PA1 as an example .
  • the FTL software maps the first logical address LA0 to the reserved storage unit PA0 and the reserved address RS to the first storage unit PA1 to complete the address conversion.
  • the result is shown in FIG. 10(b).
  • the FTL software erases the data XX2 in the reserved memory cell PA0 into data FF, and the result is shown in FIG. 10(c).
  • the FTL software to write data to the reserved memory unit PA0, the results shown in FIG 10 (d) shown in FIG.
  • FIG. 11(a) In the case where the reserved storage unit is not full of data, refer to FIG. 11(a), continue to map the reserved address RS to the reserved storage unit PA0, and the first logical address LA0, and use the stored data XX1 in the first storage unit PA1 as example.
  • the FTL software maps the first logical address LA0 to the reserved storage unit PA0 and the reserved address RS to the first storage unit PA1 to complete the address conversion. The result is shown in FIG. 11(b). Then, FTL software writes data retained in the storage unit after the data PA0 XX2, the results shown in FIG 11 (c) shown in FIG.
  • FIG. 10(a) to FIG. 10(d) and FIG. 11(a) to FIG. 11(c) are shown by adding groups and underlining.
  • address translation may include:
  • the FTL software writes data to the first storage unit (corresponding to step 1201).
  • step 1201 For the manner of writing data to the first storage unit, reference may be made to the contents of FIG. 5(a) to FIG. 5(b) and FIG. 6(a) to FIG. 6(c), which will not be repeated here.
  • the FTL software erases the reserved memory cells to erase the reserved memory cells (corresponding to step 1202). Then, the FTL software copies the data in the second storage unit to the reserved storage unit (corresponding to step 1203). Finally, the FTL software maps the reserved address to the second storage unit and the second logical address to the reserved storage unit to complete the address conversion (corresponding to step 1204).
  • step 1201 can precede step 1202 to step 1204, step 1201 can follow step 1202 to step 1204, and step 1201 can be simultaneously with step 1202 to step 1204 carried out.
  • step 1201 is executed simultaneously with steps 1202 to 1204 as an example for description.
  • the reserved address RS is mapped to the reserved memory unit PA0, and the second logical address LA0 is mapped to the second memory unit PA1, the first logical address LA5 is mapped to the first memory unit PA5, and the reserved memory unit PA0
  • the data XX2 is stored, the second storage unit PA1 stores data XX3, and the first storage unit PA5 stores data XX1.
  • the FTL software erases the data XX1 in the first memory cell PA5 into data FF, and erases the data XX2 in the reserved memory cell PA0 into data FF, and the result is shown in FIG. 13(b).
  • the FTL software writes the data in the first storage unit PA5, and copies the data XX3 in the second storage unit PA1 to the reserved storage unit PA0, that is, the data FF in the reserved storage unit PA0 becomes XX3, and the result is shown in FIG. 13 (c) shown.
  • the FTL software reserved address RS is mapped to the second storage unit PA1 and the second logical address LA0 is mapped to the reserved storage unit PA0 to complete the address conversion. The result is shown in FIG. 13(d).
  • the storage times of the flash memory device can be determined. Then, it is compared whether the storage times and the times threshold are equal, and then, it is determined whether to perform address conversion on the reserved storage unit in the flash memory device according to the comparison result. It can be seen that in this embodiment, by setting the threshold of the number of times of storage, when the threshold of the number of times is reached, the address conversion is performed on the reserved storage unit in the flash memory device, thereby avoiding writing data to the same minimum storage unit multiple times, so that each minimum storage unit in the flash memory device The probability of being erased tends to be consistent, so as to achieve the effect of balancing the number of erases, which is beneficial to prolong the service life of flash memory devices. In addition, in this embodiment, only part of the data of the smallest storage unit is processed, and the requirements on storage space and computing resources are relatively low, which is suitable for a flash memory device using a single-chip MCU as a processor.
  • state information may be set for each smallest storage unit, and the state information may be used to record the health status and status information of each smallest storage unit. At least include the health state and other states. Other states include at least one of the following: read failure, write failure, and erase failure.
  • a data storage method may further include:
  • the FTL software obtains the status information of each minimum storage unit of the flash memory device (corresponding to step 1401).
  • the FTL software can obtain the status information of all the smallest storage units in the flash memory device, so that the status information of any one of the smallest storage units can be quickly queried.
  • the FTL software can also obtain the minimum storage unit related to the data storage and address conversion, so that the amount of data obtained is small and the query speed is fast.
  • the FTL software determines that the status information of each minimum storage unit is healthy, it performs a step of determining whether to perform address conversion on the reserved storage unit in the flash memory device according to the comparison result (corresponding to step 1402).
  • the comparison result For the content of the comparison result to determine whether to perform address conversion on the reserved storage unit in the flash memory device, reference may be made to FIG. 1 and related content, which will not be repeated here.
  • the FTL software determines that the state information of the first storage unit mapped by the first logical address is other than the healthy state
  • the first storage unit is replaced and the determination according to the comparison result is performed.
  • the step of performing address conversion on the storage unit reserved in the flash memory device For the content of determining whether to perform address conversion on the reserved storage unit in the flash memory device according to the comparison result, refer to FIG. 1 and related content, and details are not described herein again.
  • replacing the first storage unit may include: referring to FIG. 15(a), because the status information of the first storage unit PA1 is other states, the FTL software will replace the third storage unit PA2 adjacent to the first storage unit PA1 As the first storage unit after replacement, a mapping relationship between the first logical address LA0 and the first storage unit after replacement (ie, the third storage unit PA2) is then established, and the result is shown in FIG. 15(b).
  • the first storage unit PA in FIG. 15(a) is a bad block, which is shown on a gray background, and the third logical address in FIG. 15(b) does not have a mapping relationship, and is also shown on a gray background.
  • bad blocks i.e., the first storage unit PA1
  • the third logical address LA1 is removed from the mapping relationship, so as to ensure the relationship between the logical address and each minimum storage unit in the mapping relationship.
  • the minimum storage unit in which the FTL software obtains status information further includes a reserved storage unit. If the status information of the reserved storage unit is other states, the FTL software uses the smallest storage unit closest to the reserved storage unit as the reserved storage unit after replacement, and establishes the mapping relationship between the reserved address and the reserved storage unit after replacement. Referring to FIG. 16(a), when the state information of the reserved storage unit PA0 is detected to be other states, the FTL software detects that the nearest smallest storage unit of the reserved storage unit PA0 is the second storage unit PA1, so the FTL software stores the second storage unit The unit PA1 serves as a reserved storage unit after replacement and establishes a mapping relationship between the reserved address RS and the second storage unit PA1. The result is shown in FIG. 16(b).
  • the reserved storage unit PA0 before replacement is a bad block and is eliminated from the mapping relationship; the second logical address LA0 has no minimum storage unit mapped to it, and the deleted content is shown on a gray background.
  • the minimum storage unit for obtaining status information by the FTL software further includes a second storage unit. If the status information of the second storage unit is other states, the FTL software uses the smallest storage unit closest to the second storage unit as the reserved storage unit after replacement, and establishes the mapping relationship between the reserved address and the replaced storage unit after replacement. Referring to FIG.
  • the FTL software detects that the nearest smallest storage unit of the second storage unit PA1 is the fourth storage unit PA2, so the FTL software will
  • the four storage units PA2 are used as reserved storage units after replacement, and the mapping relationship between the reserved address RS and the fourth storage unit PA2 is established, and the second storage unit PA1 and the fourth logical address LA1 indicated by the gray background are removed, and the result is as shown in the figure 17(b).
  • the last smallest storage unit of the reserved storage unit RS after replacement is changed from the second storage unit PA1 to the fourth storage unit PA2. If the reserved storage unit RS needs address conversion, it can be converted according to the address conversion method shown in FIG. 4 or FIG. 7, which will not be repeated here.
  • the data storage method provided by the embodiments of the present invention will be described below with reference to the embodiments and the accompanying drawings.
  • the threshold value of the number of times is 1, that is, each time the user writes data to the flash memory device, the address RS is reserved for address conversion.
  • the FTL software can display the logical address to the user, and the user selects the logical address into which the data is stored. For convenience of description, in this embodiment, the solution of this embodiment is described in a manner that a user sequentially selects logical addresses.
  • the reserved address RS is mapped to the reserved memory unit PA0, and the logical addresses LA to N-1 are sequentially mapped to the smallest memory units PA to 1 to PA, in which the smallest memory unit SA stores all the information required by the FTL software.
  • the smallest storage unit SA is not visible (shown by a slanted background).
  • the FTL software when storing data for the first time, the FTL software detects that the user chooses to write data to the first logical address LA0, and at this time the first logical address is mapped to PA1. Since the storage number of the flash memory device reaches 1 and the status information of each minimum storage unit is healthy, the FTL software performs address conversion on the reserved storage unit and writes data XX0. The result is shown in FIG. 18(c).
  • the logical address LA0 is mapped to the smallest storage unit PA0, and the save address is mapped to the smallest storage unit PA1, that is, the smallest storage unit PA1 becomes a reserved storage unit.
  • the FTL software when storing data for the second time, the FTL software detects that the user selects to write data to the first logical address LA1, and at this time the first logical address is mapped to PA2. Since the storage number of the flash memory device reaches 1, the FTL software detects that the first storage unit PA2 is a bad block (the status information is other status), as shown in FIG. 18(d). The FTL software first replaces the first storage unit. Since the closest storage unit of the minimum storage unit PA2 is the minimum storage unit PA3, the minimum storage unit PA3 is used as the first storage unit after replacement. The result is shown in FIG. 18(e). Then, the FTL software performs address conversion on the reserved storage unit PA1 and writes data XX1. The result is shown in FIG. 18(f). At this time, the logical address LA1 is mapped to the smallest storage unit PA1, and the stored address RS is mapped to the smallest storage unit. PA3, the smallest storage unit PA3, becomes a reserved storage unit.
  • FIGS. 18(a) to 18(h) show the cyclic process in which the reserved memory cells pass through the smallest memory cells PA0, PA1, PA3, ..., PA-1, and then return to the smallest memory cell PA0.
  • the data written by the user can be guaranteed to be stored in different minimum storage units, which can prevent the user from writing the data to the same logical address multiple times, the same minimum storage unit erasure times increase too fast The situation achieves the effect of balancing the number of erasures of each memory cell.
  • the FTL software in the scenario where data is written without address conversion, the FTL software only manages the first storage unit mapped by the first logical address; in the scenario where data is written and address conversion is required, the FTL software Only the first storage unit and the reserved storage unit (the two are adjacent) are managed; in the scenario where data is written, address conversion is required, and the first storage unit and the reserved storage unit are not adjacent, the FTL software only stores the first storage unit Units, reserved storage units and second storage units are managed, that is, the number of storage units managed by the FTL software each time is greatly reduced, and the demand for storage resources and computing resources is low, which is suitable for the scenario where a single-chip microcomputer is used as a processor.
  • FIG. 19 is a block diagram of a flash memory device according to an embodiment of the present invention.
  • a flash memory device 1900 includes a processor 1901, a memory 1902, and a flash memory device 1904.
  • the flash memory device is provided with a plurality of minimum storage units, and each storage unit can be used for data.
  • the processor 1901 passes a communication bus 1903. Communicating with the memory 1902, the processor 1901 realizes after reading the executable instructions from the memory 1902:
  • the processor 1901 is configured to determine the storage times of the flash memory device includes:
  • the processor 1901 is configured to determine the storage times of the flash memory device includes:
  • the number of times of storing the first logical address refers to the number of times data has been written in the first logical address
  • the processor 1901 is configured to determine whether to perform address translation on the reserved storage unit in the flash memory device according to the comparison result includes:
  • the comparison result is that the storage times are not equal to the times threshold, it is determined to maintain the current mapping relationship of the reserved storage unit and store the data to the first storage mapped to the first logical address in the data storage request unit.
  • the first storage unit of the first logical address mapping used by the processor 1901 to store data in the data storage request includes:
  • the storage state indicates that the first storage unit is full of data, the first storage unit is erased and data is written.
  • the processor 1901 is configured to determine whether to perform address translation on the reserved storage unit in the flash memory device according to the comparison result includes:
  • the processor 1901 is configured to perform address conversion on the reserved storage unit including:
  • the first logical address is mapped to the reserved storage unit and the reserved address is mapped to the first storage unit to complete address conversion.
  • the flash memory device includes a reserved storage unit mapped to a reserved address; if the reserved storage unit is adjacent to the first storage unit mapped to the first logical address in the data storage request, the processor 1901 is used to perform address conversion on the reserved storage unit including:
  • the reserved storage unit used by the processor 1901 to store data to the first logical address map includes:
  • the reserved storage unit is full of data, the reserved storage unit is erased and data is written.
  • the flash memory device includes a reserved storage unit mapped to a reserved address and a second storage unit mapped to a second logical address, the reserved storage unit is adjacent to the second storage unit and is The first storage units are not adjacent, and the processor 1901 for performing address conversion on the reserved storage unit includes:
  • the reserved address is mapped to the second storage unit and the second logical address is mapped to the reserved storage unit to complete address conversion.
  • the processor 1901 is further configured to:
  • the state information is used to record the health state of each minimum storage unit; the state information includes at least a health state;
  • a step of determining whether to perform address conversion on the storage unit reserved in the flash memory device is performed according to the comparison result.
  • each of the minimum storage units includes a first storage unit.
  • the processor 1901 is used to obtain status information of each minimum storage unit in the flash memory device, it is also used to:
  • the processor 1901 for replacing the first storage unit includes:
  • a third storage unit adjacent to the first storage unit is used as the replaced first storage unit, and a mapping relationship between the first logical address and the replaced first storage unit is established.
  • each of the minimum storage units includes a reserved storage unit
  • the processor 1901 is used to obtain status information of each minimum storage unit in the flash memory device, and is also used to:
  • the smallest storage unit closest to the reserved storage unit is used as the reserved storage unit after replacement, and the mapping relationship between the reserved address and the replaced reserved storage unit is established.
  • each of the minimum storage units includes a second storage unit adjacent to the reserved storage unit, and the processor 1901 is used to obtain status information of each minimum storage unit in the flash memory device and then use to:
  • the fourth storage unit adjacent to the second storage unit is used as the replaced second storage unit, and the second logical address and the replaced The mapping relationship of the second storage unit.
  • the other states include at least one of the following: read failure, write failure, and erase failure.
  • any storage unit in the flash memory device stores a mapping relationship between the first logical address and the first storage unit and a mapping relationship between the reserved address and the reserved storage unit.
  • the any storage unit is the last storage unit in the flash memory device.
  • FIG. 19 is a block diagram of a smart battery according to an embodiment of the present invention.
  • a smart battery 2000 is characterized by including a processor 2001, a memory 2002, and a flash memory device 2004.
  • the flash memory device 2004 is provided with a plurality of minimum storage units.
  • the processor 2001 reads from the memory 2002 After the executable instruction is realized:
  • the processor 2001 is used to determine the storage times of the flash memory device includes:
  • the processor 2001 is used to determine the storage times of the flash memory device includes:
  • the number of times of storing the first logical address refers to the number of times data has been written in the first logical address
  • the processor 2001 is configured to determine whether to perform address conversion on the reserved storage unit in the flash memory device according to the comparison result includes:
  • the comparison result is that the storage times are not equal to the times threshold, it is determined to maintain the current mapping relationship of the reserved storage unit and store the data to the first storage mapped to the first logical address in the data storage request unit.
  • the first storage unit of the first logical address mapping used by the processor 2001 to store data in the data storage request includes:
  • the storage state indicates that the first storage unit is full of data, the first storage unit is erased and data is written.
  • the processor 2001 is configured to determine whether to perform address conversion on the reserved storage unit in the flash memory device according to the comparison result includes:
  • the processor 2001 is configured to perform address conversion on the reserved storage unit including:
  • the first logical address is mapped to the reserved storage unit and the reserved address is mapped to the first storage unit to complete address conversion.
  • the flash memory device includes a reserved storage unit mapped to a reserved address; if the reserved storage unit is adjacent to the first storage unit mapped to the first logical address in the data storage request, the processor 2001 is used to perform address conversion on the reserved storage unit including:
  • the reserved storage unit used by the processor 2001 to store data to the first logical address map includes:
  • the reserved storage unit is full of data, the reserved storage unit is erased and data is written.
  • the flash memory device includes a reserved storage unit mapped to a reserved address and a second storage unit mapped to a second logical address, the reserved storage unit is adjacent to the second storage unit and is The first storage unit is not adjacent, and the processor 2001 is used to perform address conversion on the reserved storage unit including:
  • the reserved address is mapped to the second storage unit and the second logical address is mapped to the reserved storage unit to complete address conversion.
  • the processor 2001 is further used to:
  • the state information is used to record the health state of each minimum storage unit; the state information includes at least a health state;
  • a step of determining whether to perform address conversion on the storage unit reserved in the flash memory device is performed according to the comparison result.
  • each of the minimum storage units includes a first storage unit. After the processor 2001 is used to obtain status information of each minimum storage unit in the flash memory device, it is also used to:
  • the processor 2001 for replacing the first storage unit includes:
  • a third storage unit adjacent to the first storage unit is used as the replaced first storage unit, and a mapping relationship between the first logical address and the replaced first storage unit is established.
  • the minimum storage units include reserved storage units. After the processor 2001 is used to obtain status information of the minimum storage units in the flash memory device, it is also used to:
  • the smallest storage unit closest to the reserved storage unit is used as the reserved storage unit after replacement, and the mapping relationship between the reserved address and the replaced reserved storage unit is established.
  • each of the minimum storage units includes a second storage unit adjacent to the reserved storage unit, and the processor 2001 is used to obtain status information of each minimum storage unit in the flash memory device and then use to:
  • the fourth storage unit adjacent to the second storage unit is used as the replaced second storage unit, and the second logical address and the replaced The mapping relationship of the second storage unit.
  • the other states include at least one of the following: read failure, write failure, and erase failure.
  • any storage unit in the flash memory device stores a mapping relationship between the first logical address and the first storage unit and a mapping relationship between the reserved address and the reserved storage unit.
  • the any storage unit is the last storage unit in the flash memory device.
  • An embodiment of the present invention also provides a movable platform, which may include the above-mentioned smart battery.
  • the mobile platform can be drones, smart phones, tablet computers, handheld camera equipment and other devices.
  • An embodiment of the present invention also provides a readable storage medium, which stores a number of computer instructions.
  • the steps of the data storage method shown in the foregoing embodiments are implemented. Specific content may be Reference is made to the embodiments of the data storage method, which will not be repeated here.

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

L'invention concerne un procédé de stockage de données, un dispositif flash, une batterie intelligente et une plateforme mobile. Le procédé de stockage de données comprend les étapes consistant à : si une demande de stockage de données est reçue, déterminer le nombre d'opérations de stockage d'un dispositif flash ; comparer le nombre d'opérations de stockage à un seuil du nombre d'opérations pour obtenir un résultat de comparaison ; et déterminer, selon le résultat de comparaison, s'il faut effectuer une conversion d'adresse sur une unité de stockage réservée dans le dispositif flash. Selon le présent mode de réalisation, par configuration du seuil du nombre d'opérations, lorsque le seuil est atteint, l'unité de stockage réservée dans le dispositif flash est soumise à une conversion d'adresse, de manière à éviter une situation dans laquelle des données sont écrites de multiples fois dans la même unité de stockage minimale, à faire tendre vers une valeur uniforme les probabilités que les unités de stockage minimales dans le dispositif flash soient effacées, à obtenir un effet de rendre équilibré le nombre d'opérations d'effacement, et à prolonger la durée de vie du dispositif flash. De plus, dans le présent mode de réalisation, seules des données présentes dans certaines des unités de stockage minimales sont traitées, les exigences sur l'espace de stockage et les ressources informatiques sont faibles, et le mode de réalisation est applicable à des dispositifs flash utilisant un micro-ordinateur monopuce (MCU) comme processeur.
PCT/CN2018/119230 2018-12-04 2018-12-04 Procédé de stockage de données, dispositif flash, batterie intelligente et plateforme mobile WO2020113440A1 (fr)

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CN101740110B (zh) * 2009-12-17 2013-06-12 中兴通讯股份有限公司 一种Nand Flash擦除均衡的方法及装置
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