WO2020108526A1 - 移位寄存器、栅极驱动电路、显示装置及驱动方法 - Google Patents
移位寄存器、栅极驱动电路、显示装置及驱动方法 Download PDFInfo
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- WO2020108526A1 WO2020108526A1 PCT/CN2019/121250 CN2019121250W WO2020108526A1 WO 2020108526 A1 WO2020108526 A1 WO 2020108526A1 CN 2019121250 W CN2019121250 W CN 2019121250W WO 2020108526 A1 WO2020108526 A1 WO 2020108526A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
Definitions
- the present disclosure relates to the field of display technology, and in particular, to a shift register, a gate driving circuit including the shift register, a display device including the gate driving circuit, and a driving method of the display device.
- the pixel circuit includes a driving transistor that drives the organic light emitting diode to emit light. Due to the uneven manufacturing process, the threshold voltages of the driving transistors in different pixel devices are inconsistent. Therefore, the brightness of the light emitting diodes in different pixel devices in the same display panel is not uniform. In view of this, a compensation circuit needs to be provided.
- the display device with a narrow bezel is a market trend. If the structure of the shift register is too complicated, it is not conducive to realizing a display device with a narrow bezel.
- a shift register including: a plurality of signal input circuits connected to a plurality of signal input terminals, a plurality of input control terminals, and a pull-up control terminal; a plurality of reset circuits connected to a plurality of reset controls Terminal, the first power terminal and the pull-up control terminal; a control and output circuit connected to the pull-up control terminal, pull-down control terminal, output power terminal, output clock signal terminal and output signal terminal, and configured as: The voltage of the pull-down control terminal is determined according to the voltage at the pull-up control terminal, a signal provided by the output clock signal terminal is output through the signal output terminal in response to the voltage of the pull-up control terminal, and in response to the The signal provided by the output power terminal is output through the signal output terminal by pulling down the voltage of the control terminal.
- the working period of the shift register is divided into multiple stages, the multiple stages do not overlap in time, and each of the stages includes at least a first sub-stage and a second sub-stage.
- Each of the plurality of signal input circuits is configured to respond to a signal of a corresponding one of the plurality of input control terminals, and apply to the pull-up control terminal in a first sub-stage of different stages of the plurality of stages A signal provided by a corresponding one of the plurality of signal input terminals.
- Each of the plurality of reset circuits is configured to apply a signal to the pull-up control terminal in a second sub-stage of a different one of the plurality of stages in response to a signal of a corresponding one of the plurality of reset control terminals The first power signal provided by the first power terminal.
- control and output circuit includes: a pull-down control circuit connected to the pull-up control terminal, the pull-down control terminal, the first power supply terminal, and the pull-down control clock terminal, and configured to The voltage at the pull-up control terminal applies a signal provided by one of the first power terminal and the pull-down control clock terminal to the pull-down control terminal; and an output circuit connected to the signal output terminal, the output power terminal, and the Output a clock signal terminal, the pull-up control terminal and the pull-down control terminal, and are configured to output a signal provided by the output clock signal terminal through the signal output terminal in response to the voltage of the pull-up control terminal, and in response to the voltage of the pull-down control terminal, The signal provided by the output power supply terminal is output through the signal output terminal.
- the duty cycle of the shift register is divided into a detection stage and a display stage
- the multiple signal input circuits include a first input circuit and a second input circuit
- the multiple signal input terminals include a first The input terminal and the second input terminal.
- the signal output terminal includes a cascade output terminal and a scan signal output terminal.
- the first input circuit is connected to the cascade output terminal, the detection trigger terminal, the first input terminal and the pull-up control terminal, and is configured to respond to the cascade output terminal and the detection trigger terminal Both receive an effective level, and apply the signal provided by the first input terminal to the pull-up control terminal in the first sub-stage of the detection stage.
- the second input circuit is connected to a display trigger terminal, the second input terminal, and the pull-up control terminal, and is configured to respond to the display trigger terminal receiving an effective level at the first stage of the display stage
- the sub-stage applies the signal provided by the second input terminal to the pull-up control terminal.
- the plurality of reset circuits include a first reset circuit and a second reset circuit
- the plurality of reset control terminals include a first reset control terminal and a second reset control terminal.
- the first reset circuit is connected to the first reset control terminal, the first power supply terminal, and the pull-up control terminal, and is configured to respond to the voltage of the first reset control terminal during the detection phase.
- the two sub-phases provide the first power signal to the pull-up control terminal.
- the second reset circuit is connected to the second reset control terminal, the first power supply terminal, and the pull-up control terminal, and is configured to respond to the voltage of the second reset control terminal during the first
- the two sub-phases provide the first power signal to the pull-up control terminal.
- the first input circuit includes a detection control subcircuit connected to the cascade output terminal, the detection trigger terminal, and a detection control node, and configured to respond to the cascade output terminal And one of the detection trigger terminals receives an effective level, and applies a signal provided by the other of the cascade output terminal and the detection trigger terminal to the detection control node; a detection input sub-circuit, It is connected to the detection control node, the first input terminal, and the pull-up control terminal, and is configured to apply to the pull-up control terminal by the first A signal provided by an input terminal; and a detection storage sub-circuit, connected to the detection control node and the first power supply terminal, configured to store the voltage at the detection control node.
- the first input circuit further includes: a detection reset sub-circuit connected to the detection control node, a detection reset terminal, and the first power supply terminal, configured to respond to the voltage of the detection reset terminal The first power signal is provided to the detection control node.
- the detection control sub-circuit includes a detection control transistor, a control electrode of the detection control transistor is connected to the detection trigger terminal, and a first electrode of the detection control transistor is connected to the cascade output terminal The second electrode of the detection control transistor is connected to the detection control node.
- the detection control sub-circuit includes a detection control transistor, a control electrode of the detection control transistor is connected to the cascade output terminal, and a first electrode of the detection control transistor is connected to the detection trigger terminal The second electrode of the detection control transistor is connected to the detection control node.
- the detection input sub-circuit includes a detection input transistor and a switching transistor.
- the control electrode of the detection input transistor is connected to the detection control node, the first electrode of the detection input transistor is connected to the first input terminal, and the second electrode of the detection input transistor is connected to the The first pole.
- the control electrode of the switching transistor is connected to the first input terminal, and the second electrode is connected to the pull-up control terminal.
- the detection input sub-circuit includes a detection input transistor, a switching transistor, and a detection leakage prevention transistor.
- the control electrode of the detection input transistor is connected to the detection control node, the first electrode of the detection input transistor is connected to the first input terminal, and the second electrode of the detection input transistor is connected to the The first pole.
- the control electrode of the switching transistor is connected to the detection clock terminal, and the second electrode is connected to the first electrode of the detection anti-leakage transistor.
- the control electrode of the detection leakage prevention transistor is connected to the detection clock terminal, the first electrode is connected to an intermediate leakage prevention node, and the second electrode is connected to the pull-up control terminal.
- the detection reset sub-circuit includes a detection reset transistor, a control electrode of the detection reset transistor is connected to the detection reset terminal, a first electrode is connected to the detection control node, and a second electrode is connected to all Describe the first power terminal.
- the pull-down control circuit includes: at least one pull-down control input sub-circuit connected to the pull-down control clock terminal and the pull-down control terminal, configured to apply the pull-down control to the pull-up control terminal A signal provided by the clock terminal; and a control sub-circuit, which is connected to the pull-up control terminal, the pull-down control terminal and the first power supply terminal, and is configured to divide all the signals according to the voltage at the pull-up control terminal The voltage of the pull-down control terminal is determined to be the voltage provided by one of the first power supply terminal and the pull-down control clock terminal.
- the control sub-circuit includes a first pull-down control transistor and a second pull-down control transistor.
- the control electrode of the first pull-down control transistor is connected to the pull-up control terminal, the first electrode is connected to the pull-down control terminal, and the second electrode is connected to the first power supply terminal.
- the control electrode of the second pull-down control transistor is connected to the pull-down control terminal, the first electrode is connected to the pull-up control terminal, and the second electrode is connected to the first power supply terminal.
- the control sub-circuit includes a first pull-down control transistor, a second pull-down control transistor, and a pull-down control anti-leakage transistor.
- the control electrode of the first pull-down control transistor is connected to the pull-up control terminal, the first electrode is connected to the pull-down control terminal, and the second electrode is connected to the first power supply terminal.
- the control electrode of the second pull-down control transistor is connected to the pull-down control terminal, the first electrode is connected to the pull-up control terminal, and the second electrode is connected to the first electrode of the pull-down control anti-leakage transistor.
- the control electrode of the pull-down control anti-leakage transistor is connected to the pull-down control terminal, and the second electrode of the pull-down control anti-leakage transistor is connected to the first power terminal.
- the pull-down control clock terminal includes multiple pull-down control clock terminals, and the multiple pull-down control clock terminals provide valid signals in different time periods.
- the pull-down control circuit includes a plurality of the pull-down control input sub-circuits, each of the pull-down control input sub-circuits is connected to one of the plurality of pull-down control clock terminals and the pull-down control terminal, configured to respond to the pull-down
- the control clock terminal receives the valid signal, and applies the signal provided by the pull-down control clock terminal to the pull-down control terminal.
- each of the pull-down control input sub-circuits includes a pull-down control input transistor.
- the control electrode and the first electrode of the pull-down control input transistor are connected to one of the plurality of pull-down control clock terminals, and the second electrode is connected to the pull-down control terminal.
- the output power terminal includes a second power terminal and the first power terminal.
- the output circuit includes a cascade output sub-circuit connected to the cascade output terminal, the output clock signal terminal, the pull-up control terminal, the pull-down control terminal, and the first power supply terminal, and It is configured to output the signal provided by the output clock signal terminal through the cascade output terminal in response to the voltage of the pull-up control terminal, and output the output through the cascade output terminal in response to the voltage of the pull-down control terminal A signal provided by the first power supply terminal, and at least one scan signal output sub-circuit connected to the scan signal output terminal, the output clock signal terminal, the pull-up control terminal, the pull-down control terminal and the first Two power terminals, and configured to output the signal provided by the output clock signal terminal through the scan signal output terminal in response to the voltage of the pull-up control terminal, and pass the scan signal in response to the voltage of the pull-down control terminal
- the output end outputs the signal provided by the second power supply end.
- the cascade output sub-circuit includes: a cascade output pull-up transistor, a cascade output pull-down transistor, and a pull-up control capacitor.
- the control electrode of the cascade output pull-up transistor is connected to the pull-up control terminal, the first electrode is connected to the output clock signal terminal, and the second electrode is connected to the cascade output terminal.
- the control electrode of the cascade output pull-down transistor is connected to the pull-down control terminal, the first electrode is connected to the first power supply terminal, and the second electrode is connected to the cascade output terminal.
- the first pole of the pull-up control capacitor is connected to the pull-up control terminal, and the second pole is connected to the cascade output terminal.
- the scan signal output sub-circuit includes a scan output pull-up transistor and a scan output pull-down transistor.
- the control electrode of the scan output pull-up transistor is connected to the pull-up control terminal, the first electrode is connected to the output clock signal terminal, and the second electrode is connected to the scan signal output terminal.
- the control electrode of the scan output pull-down transistor is connected to the pull-down control terminal, the first electrode is connected to the second power terminal, and the second electrode is connected to the scan signal output terminal.
- the first reset circuit includes: a first reset transistor whose control electrode is connected to the first reset control terminal, the first electrode is connected to the pull-up control terminal, and the second electrode is connected to the first power supply terminal.
- the second reset circuit includes a second reset transistor whose control pole is connected to the second reset control end, the first pole is connected to the pull-up control end, and the second pole is connected to the first power supply end.
- the first reset circuit includes: a first reset transistor whose control electrode is connected to the first reset control terminal, the first electrode is connected to the pull-up control terminal, and the second electrode is connected to the first power supply terminal.
- the second reset circuit includes: a second reset transistor and a reset leakage prevention transistor, the control electrode of the second reset transistor is connected to the second reset control terminal, the first electrode is connected to the pull-up control terminal, and the second electrode is connected to all The first pole of the reset leakage prevention transistor, the control pole of the reset leakage prevention transistor is connected to the second reset control terminal, the first pole is connected to the middle leakage prevention node, and the second pole is connected to the first power supply terminal.
- the shift register further includes: an intermediate leakage prevention transistor, a control electrode of the intermediate leakage prevention transistor is connected to the pull-up control terminal, a first pole and a third power supply terminal or the pull-up control terminal Electrically connected, the second pole is connected to the intermediate leakproof node.
- a gate drive circuit in a second aspect, includes a cascaded multi-stage shift register, and the shift register is the aforementioned shift register.
- the cascade output terminal of the 4n+1 stage shift register is connected to the display trigger terminal of the 4n+3 stage shift register, and the output clock signal terminal of the 4n+1 stage shift register is connected to provide the first output clock
- the first output clock signal line of the signal, the second reset control terminal of the 4n+1th stage shift register is connected to the cascade output terminal of the 4n+4th stage shift register.
- the cascade output terminal of the 4n+2 stage shift register is connected to the display trigger terminal of the 4n+4 stage shift register, and the output clock signal terminal of the 4n+2 stage shift register is connected to provide the second output clock
- the second output clock signal line of the signal, the second reset control terminal of the 4n+2 stage shift register is connected to the cascade output terminal of the 4n+5 stage shift register.
- the cascade output terminal of the 4n+3 stage shift register is connected to the display trigger terminal of the 4n+5 stage shift register, and the output clock signal terminal of the 4n+3 stage shift register is connected to provide the third output clock
- the third output clock signal line of the signal, the second reset control terminal of the 4n+3 stage shift register is connected to the cascade output terminal of the 4n+6 stage shift register.
- the cascade output terminal of the 4n+4th stage shift register is connected to the display trigger terminal of the 4n+6th stage shift register, and the output clock signal terminal of the 4n+4th stage shift register is connected to provide a fourth output clock
- the fourth output clock signal line of the signal, the second reset control terminal of the 4n+4th stage shift register is connected to the cascade output terminal of the 4n+7th stage shift register.
- a display device including the above-mentioned gate drive circuit.
- a method for driving a shift register is provided.
- the shift register is the above shift register.
- the duty cycle of the shift register is divided into a display phase and a detection phase that do not overlap in time, and each of the display phase and the detection phase includes a first sub-phase, a second sub-phase, and a third sub-phase.
- the driving method includes: in a first sub-stage of the display stage, the second input circuit applies the effective signal provided by the second input terminal to the pull-up control terminal in response to the signal of the display trigger terminal; In the second sub-stage of the display phase, the control and output circuit determines the voltage of the pull-down control terminal as an invalid voltage in response to the signal of the pull-up control terminal, and passes the signal in response to the signal of the pull-up control terminal The signal output terminal outputs the signal provided by the output clock signal terminal; in the third sub-stage of the display phase, the second reset circuit provides the invalid signal of the first power supply terminal to the signal of the second reset control terminal in response to the signal of the second reset control terminal The pull-up control terminal; in the first sub-stage of the detection phase, the first input circuit applies the first input to the pull-up control terminal in response to the signals of the detection trigger terminal and the signal output terminal Valid signal provided by the terminal; in the second sub-stage of the detection phase, the control and output circuit determines the voltage of the pull-down control terminal as an
- FIG. 1 is a block diagram of a shift register provided by the present disclosure
- FIG. 2 is a circuit diagram of a shift register provided by the present disclosure
- FIG. 3 is a circuit diagram of a shift register provided by the present disclosure.
- FIG. 5 is a circuit diagram of a shift register provided by the present disclosure.
- FIG. 7 is a block diagram of a gate driving circuit provided by the present disclosure.
- FIG. 8 is a schematic diagram of a pixel circuit in a pixel unit in a display panel provided by the present disclosure
- FIG. 10 is a block diagram of the shift register provided by the present disclosure.
- a signal or level is called “valid”, which means that the signal or level can drive the corresponding transistor to turn on and/or turn on the corresponding circuit
- a signal or level is called “invalid”
- Valid Means that the signal or level can drive the corresponding transistor to be turned off and/or the corresponding circuit to be closed.
- the effective level is low and the invalid level is high; for N-type transistors, the effective level is high and the invalid level is low.
- the case where all transistors are N-type transistors, the effective level is high level, and the invalid level is low level is taken as an example for description, but the present disclosure is not limited thereto.
- inventions of the present disclosure provide a shift register.
- the shift register includes: multiple signal input circuits, multiple reset circuits, control and output circuits.
- the control and output circuit may include a pull-down control circuit 140 and an output circuit 130.
- the pull-down control circuit 140 is connected to the pull-up control terminal Q, the pull-down control terminal QB, the first power supply terminal VGL1 and the pull-down control clock terminal, and is configured to be controlled by the first power supply terminal VGL1 and pull-down according to the voltage at the pull-up control terminal Q
- the signal provided by one of the clock terminals is applied to the pull-down control terminal QB.
- the first power terminal VGL1 is used to provide a first power signal, which has a constant invalid level.
- the output circuit 130 is connected to the signal output terminal, the output power terminal, the output clock signal terminal, the pull-up control terminal Q and the pull-down control terminal QB, and is configured to output the output clock through the signal output terminal in response to the voltage of the pull-up control terminal Q
- the signal provided by the signal terminal, and in response to the voltage of the pull-down control terminal QB, the signal provided by the power supply terminal is output through the signal output terminal.
- the output power terminal is used to provide a constant invalid level voltage.
- the multiple signal input circuits are connected to the multiple signal input terminals, the multiple input control terminals, and the pull-up control terminal Q.
- the multiple reset circuits are connected to multiple reset control terminals, the first power supply terminal VGL1 and the pull-up control terminal Q.
- the working cycle of the shift register according to the present disclosure is divided into multiple stages, the multiple stages do not overlap in time, and each stage includes at least a first sub-stage and a second sub-stage.
- the plurality of signal input circuits are each configured to respond to the signal of a corresponding one of the plurality of input control terminals, and the control terminal Q is pulled up by the corresponding one of the plurality of signal input terminals in the first sub-stage of different stages among the plurality of stages. A signal provided.
- the plurality of reset circuits are each configured to, in response to a signal of a corresponding one of the plurality of reset control terminals, pull up the control terminal Q at a second sub-stage of different stages among the plurality of stages to apply the first provided by the first power supply terminal VGL1 Power signal.
- FIG. 1 shows an example of a shift register.
- the shift register shown in FIG. 1 includes a plurality of signal input circuits 110 and 120, a plurality of reset circuits 150 and 160, an output circuit 130, and a pull-down control circuit 140.
- the multiple signal input terminals include a first input terminal CLKE and a second input terminal VDD
- the multiple input control terminals include a detection trigger terminal OE and a cascade output terminal CR as the first input control terminal.
- the multiple reset control terminals include the first reset control terminal TRST and the second reset control terminal DRST, and the duty cycle of the shift register is divided into two that do not overlap in time Stage: display stage T1 and detection stage T2 (see Figure 6).
- the present disclosure is not limited to this.
- the first input circuit 110 as the detection input circuit is connected to the cascade output terminal CR, the detection trigger terminal OE, the first input terminal CLKE, and the pull-up control terminal Q, and is configured to respond to the cascade output terminal CR and the detection trigger terminal OE Both receive the active level, and in the first sub-stage of the detection stage T2, the control terminal Q is pulled up to apply the signal provided by the first input terminal CLKE.
- the second input circuit 120 as the display input circuit is connected to the display trigger terminal DTR, the third power supply terminal VDD as the second input terminal and the pull-up control terminal Q, and is configured to respond to the display trigger terminal DTR receiving an effective level at The first sub-phase of the display phase T1 pulls up the control terminal Q to apply the signal provided by the third power terminal VDD.
- the third power terminal VDD is used to provide a third power signal, which has a constant effective level.
- the first reset circuit 160 is connected to the first reset control terminal TRST, the first power supply terminal VGL1, and the pull-up control terminal Q, and is configured to respond to the voltage of the first reset control terminal TRST in the second sub-stage of the detection stage T2.
- a power signal is provided to the pull-up control terminal Q.
- the second reset circuit 150 is connected to the second reset control terminal DRST, the first power supply terminal VGL1, and the pull-up control terminal Q, and is configured to respond to the voltage of the second reset control terminal DRST and change the A power signal is provided to the pull-up control terminal Q.
- multiple signal input circuits 110 and 120 alternately pull up the control terminal Q to provide signals at different time periods of a working cycle, and accordingly, multiple reset circuits 150 and 160 alternately at different time periods Pulling up the control terminal provides an invalid level (ie, resetting the pull-up control terminal Q).
- the signals output by the signal output terminal are multiple signals having only one signal The superposition of the signals output by the shift register of the input circuit.
- multiple signal input circuits and multiple reset circuits share the output circuit and the pull-down control circuit, and there is no need to provide a connector, thereby simplifying the structure of the shift register and facilitating the realization of a narrow border.
- the display scan signal and the detection scan signal can be simultaneously output through a signal output terminal (for example, a scan signal output terminal) of a shift register.
- a signal output terminal for example, a scan signal output terminal
- the first input circuit 110 for providing the detection input signal is controlled by both the cascade output terminal CR and the detection trigger terminal OE, a random detection function can be realized, which will be described later.
- the signal output terminal includes a scan signal output terminal OUT and a cascade output terminal CR.
- the output circuit 130 includes a cascade output sub-circuit 131 and at least one scan signal output sub-circuit (for example, 132 in FIGS. 1-4, or 132 and 133 in FIG. 5).
- the cascade output sub-circuit 131 is connected to the cascade output terminal CR, the output clock signal terminal CLKD, the pull-up control terminal Q, the pull-down control terminal QB, and the first power supply terminal VGL1, and is configured to respond to the voltage of the pull-up control terminal Q,
- the signal provided by the output clock signal terminal CLKD is output through the cascade output terminal CR, and in response to the voltage of the pull-down control terminal QB, the signal provided by the first power supply terminal VGL1 is output through the cascade output terminal CR.
- the scan signal output sub-circuit is connected to the scan signal output terminal OUT, the output clock signal terminal CLKD, the pull-up control terminal Q, the pull-down control terminal QB, and the second power supply terminal VGL2, and is configured to respond to the voltage of the pull-up control terminal Q through
- the scan signal output terminal OUT outputs the signal provided by the output clock signal terminal CLKD, and in response to the voltage of the pull-down control terminal QB, outputs the signal provided by the second power supply terminal VGL2 through the scan signal output terminal OUT.
- the first power supply terminal VGL1 and the second power supply terminal VGL2 are used as the output power supply terminal, but the present disclosure is not limited thereto, as long as the output power supply terminal can provide a constant invalid level.
- this stage may include as a first sub-stage The charging sub-stage t1, the output sub-stage t2, and the pull-down sub-stage t3 as the second sub-stage (see FIG. 6).
- one of the plurality of signal input circuits provides a signal to the pull-up control terminal Q to charge the pull-up control terminal Q.
- the second input The circuit 120 provides a high-level signal to the Q point
- the first input circuit 110 provides a high-level signal to the Q point.
- the invalid first clock signal is provided to the output clock signal terminal CLKD, and the output circuit 130 outputs the invalid first clock signal through the signal output terminals (for example, CR and OUT).
- the signal input circuit no longer pulls up the control terminal Q to provide a signal, so that the pull-up control terminal Q floats, and the potential of the pull-up control terminal Q is still high, so that the output circuit 130 maintains the slave signal output terminal (e.g. CR and OUT) output the first clock signal.
- the first clock signal is an effective signal, so that the signal output terminal can output an effective signal, and in the output sub-phase t2, the pull-down control circuit 140 pulls the pull-down control terminal QB according to the potential of the pull-up control terminal Q 'S potential is pulled low.
- the first clock signal is a low-level signal, and the potential of the pull-up control terminal Q is initially high. Then, one of the plurality of reset circuits pulls up the control terminal Q to provide the first power signal, for example, in the pull-down sub-phase t3 of the display phase T1, the second reset circuit 150 responds to the high level of the second reset control terminal DRST The level of the pull-up control terminal Q is lowered. In the pull-down sub-phase t3 of the detection phase T2, the first reset circuit 160 pulls the level of the pull-up control terminal Q low in response to the high level of the first reset control terminal TRST .
- the pull-down control circuit 140 applies the signal of the pull-down control clock terminal to the pull-down control terminal QB so that the potential of the pull-down control terminal QB is an effective level.
- the output circuit 130 outputs the invalid level provided by the output power supply terminal to the signal output terminal under the control of the effective level of the pull-down control terminal QB.
- the shift register When each signal input circuit pulls up the control terminal Q to provide a signal, the shift register enters the charging sub-phase t1 and undergoes the output sub-phase t2 and the pull-down sub-phase t3. In other words, in a working cycle of the entire shift register, the operation sequence of the charging sub-stage, the output sub-stage, and the pull-down sub-stage are repeated multiple times, so that the shift register can output a superposition of multiple scanning signals.
- the pull-down control circuit 140 may include a control sub-circuit 143 and at least one input sub-circuit.
- the input sub-circuit is connected to the pull-down control clock terminal and the pull-down control terminal Q, and is configured to apply the signal provided by the pull-down control clock terminal to the pull-up control terminal Q.
- the control sub-circuit 143 is connected to the pull-up control terminal Q, the pull-down control terminal QB and the first power supply terminal VGL1, and is configured to determine the voltage of the pull-down control terminal QB as the first power supply terminal according to the voltage at the pull-up control terminal Q The voltage provided by one of VGL1 and the pull-down control clock terminal.
- the pull-down control circuit 140 includes a control sub-circuit 143 and a plurality of input sub-circuits (for example, in the example of FIG. 1, two input sub-circuits 141 And 142), and the shift register includes a plurality of pull-down control clock terminals (for example, in the example of FIG. 1, the shift register includes a first pull-down control clock terminal CLKM and a second pull-down control clock terminal CLKN).
- a plurality of the input sub-circuits are respectively used to provide an effective pull-down control signal to the pull-down control terminal at different time periods.
- one of the multiple input sub-circuits and the control sub-circuit 143 form a functionally complete pull-down control circuit 140, and the remaining input sub-circuits are in an idle state.
- Multiple input sub-circuits are alternately energized, so that the service life of a single input sub-circuit can be extended.
- Each input subcircuit is electrically connected to a corresponding one of the plurality of pull-down control clock terminals and the pull-down control terminal QB, and is configured to apply to the pull-down control terminal QB in response to the pull-down control clock terminal receiving a valid signal provided by the pull-down control clock terminal signal of. It should be explained that when the shift register is running, one of the pull-down control clock terminals in the shift register receives a valid pull-down control clock signal, and the remaining pull-down control clock terminals receive an invalid pull-down control clock signal. .
- an effective pull-down control clock signal can be provided to the pull-down control terminal QB through the input sub-circuit.
- the pull-down control sub-circuit 140 includes two pull-down control clock terminals, which are the first pull-down control clock terminal CLKM and the second pull-down control clock terminal, respectively. CLKN, and the pull-down control sub-circuit 140 includes an input sub-circuit 141 electrically connected to the first pull-down control clock terminal CLKM and an input sub-circuit 142 electrically connected to the second pull-down control clock terminal CLKN.
- the specific structure of the input sub-circuit is not particularly limited.
- the input sub-circuit includes a pull-down control input transistor, the gate of the pull-down control input transistor and the first The pole is electrically connected to the corresponding pull-down control clock terminal, and the second pole is electrically connected to the pull-down control terminal Q.
- the control sub-circuit 143 may include a first pull-down control transistor M8 and a second pull-down control transistor M9.
- the control electrode of the first pull-down control transistor M8 is connected to the pull-up control terminal Q, the first electrode is connected to the pull-down control terminal QB, and the second electrode is connected to the first power supply terminal VGL1.
- the control electrode of the second pull-down control transistor M9 is connected to the pull-down control terminal QB, the first electrode is connected to the pull-up control terminal Q, and the second electrode is connected to the first power supply terminal VGL1.
- the input sub-circuit 141 includes a control signal input transistor M7
- the input sub-circuit 142 includes a control signal input transistor M10.
- the control electrode and the first electrode of the control signal input transistor M7 are connected to the first pull-down control clock terminal CLKM
- the second electrode of the control signal input transistor M7 is electrically connected to the pull-down control terminal QB
- the control electrode and the first electrode of the control signal input transistor M10 are connected to the second pull-down control clock terminal CLKN, and the second electrode of the control signal input transistor M10 is electrically connected to the pull-down control terminal QB.
- the size of the control signal input transistor M7 is the same as the size of the control signal input transistor M10, but the width-to-length ratio of the control signal input transistor M7 is smaller than the size of the first pull-down control transistor M8, so that The pull-up control transistor M8 controls the voltage of the pull-down control terminal QB.
- the pull-up control terminal Q is a high-level signal
- the first pull-down control transistor M8 is turned on
- the control signal input transistors M7 and M10 whose control poles are applied with one of the effective levels Turn on, under the control signal input transistors M7/M10 and the first pull-down control transistor M8 voltage division, the low-level signal provided by the first power supply terminal VGL1 is provided to the pull-down control terminal QB, so that the first power can be ensured
- the flat signal terminal VGL2 is disconnected from the signal output terminal OUT.
- the pull-up control terminal Q voltage is pulled down by the reset circuit 150 or 160.
- the effective pull-down control clock signal supplied to the pull-down control terminal QB through the input sub-circuit causes the output circuit 130 to provide a low-level signal to signal output terminals such as the cascade output terminal CR and the scan signal output terminal OUT.
- the gate of the second pull-down control transistor M9 is an effective pull-down control clock signal, the second pull-down control transistor M9 is turned on, and the pull-up control terminal Q is further processed by the signal provided by the first power supply terminal VGL1 Lowers noise.
- the pull-down control sub-circuit 143 further includes a first anti-leakage The transistor M18, and the second electrode of the second pull-down control transistor M9 is connected to the first electrode of the pull-down control leakage prevention transistor M18 instead of the first power supply terminal VGL1.
- the control electrode of the pull-down control anti-leakage transistor M18 is connected to the pull-down control terminal QB, and the second electrode of the pull-down control anti-leakage transistor is connected to the first power terminal VGL1.
- both the second pull-down control transistor M9 and the first leakage prevention transistor M18 are turned off to ensure that the first power supply terminal VGL1 does not affect the potential of the pull-up control terminal Q.
- the second reset circuit 150 includes a second reset transistor M6 whose control pole is connected to the second reset control terminal DRST and the first pole is connected to the pull-up control Terminal Q, the second pole is connected to the first power terminal VGL1.
- the second reset transistor M6 By supplying an effective reset signal to the control electrode of the second reset transistor M6 in the pull-down sub-phase t3, the second reset transistor M6 can be turned on, thereby providing the signal of the first power supply terminal VGL1 to the pull-up control terminal Q to Pulling the control terminal Q potential low, the output circuit 130 will not provide an invalid signal to the signal output terminal.
- the second reset sub-circuit 150 further includes a reset leakage prevention transistor M17, and the second reset transistor M6 Is connected to the first electrode of the reset leakage prevention transistor M17, the control electrode of the reset leakage prevention transistor M17 is connected to the second reset control terminal DRST, and the second electrode is connected to the first power supply terminal VGL1.
- the reset leakage prevention transistor M17 when the control electrode of the reset leakage prevention transistor M17 receives the reset control signal, the reset leakage prevention transistor M17 is turned on, and the second reset transistor M6 is turned on, so that the first power supply terminal VGL1 and the pull-up control The terminal Q is turned on.
- the control electrode of the second reset transistor M6 and the control electrode of the reset leakage prevention transistor M17 receive an invalid reset signal, therefore, the second reset transistor M6 and the reset leakage prevention transistor M17 are turned off to ensure pull-up control Terminal Q will not be pulled low.
- the first reset circuit 160 includes: a first reset transistor M15, whose control electrode is connected to the first reset control terminal TRST, and the first electrode is connected to the pull-up control terminal Q, The two poles are connected to the first power terminal VGL1.
- the first reset transistor M15 When the control electrode of the first reset transistor M15 receives an effective control signal, the first reset transistor M15 is turned on, and then the first power supply terminal VLG1 and the pull-up control terminal Q are turned on, and the pull-up control terminal Q is reset.
- the first input circuit 110 may be used as a detection signal input circuit
- the second input circuit 10 may be used as a display signal input circuit
- the shift register may be used in a display panel including an external detection circuit.
- the first input circuit 110 is used to pull up the control terminal Q to provide a detection trigger signal
- the second input circuit 120 is used to pull up the control terminal Q to provide a display trigger signal.
- the detection scan signal here is a signal used to control the external compensation circuit of the organic light emitting diode display panel to detect each pixel unit.
- the first input circuit 110 and the second input circuit 120 take turns (for example, in the sub-phase t1 of the detection phase T2 and the sub-phase t1 of the display phase T1) to pull up the control terminal Q to provide a trigger signal.
- the first input circuit 110 includes a detection control sub-circuit 111, a detection input sub-circuit 112, and a detection storage sub-circuit 113.
- the detection control sub-circuit 111 is connected to the cascade output terminal CR, the detection trigger terminal OE, and the detection control node H, and is configured to respond to one of the cascade output terminal CR and the detection trigger terminal OE to receive an effective level
- the control node H applies a signal provided by the other of the cascade output terminal CR and the detection trigger terminal OE.
- the detection input sub-circuit 112 is connected to the detection control node H, the first input terminal CLKE and the pull-up control terminal Q, and is configured to apply the pull-up control terminal Q in response to the effective level of the detection control node H by the first input terminal CLKE The signal provided.
- the detection storage sub-circuit 113 is connected to the detection control node H and the first power terminal VGL1 and is configured to store the voltage at the detection control node H.
- the timing of the detection input sub-circuit 112 to provide a signal to the pull-up control terminal can be controlled.
- the first input circuit 110 further includes a detection reset sub-circuit 114 connected to the detection control node H, the detection reset terminal CLKB and the first power supply terminal VGL1, configured to respond to the voltage of the detection reset terminal CLKB to The first power signal is provided to the detection control node H.
- the pull-down sub-phase t3 of the detection phase T2 provides an effective signal to the detection reset terminal CLKB.
- the first power signal can be applied to the detection control node H in the pull-down sub-stage of the detection stage, so that the discharge of the detection control node H is more sufficient.
- the signal output from the signal output terminal includes the display scan signal and the detection scan signal.
- the signal input to the first input circuit 110 is a signal output through the cascade output terminal CR, which is the same in waveform as the signal including the display scan signal output from the scan signal output terminal. Using the display scan signal to control the output of the first input circuit 110 can reduce energy consumption and simplify the circuit structure.
- the detection trigger terminal OE inputs a high-level detection trigger signal during a certain time period in the display phase T1.
- the detection trigger terminal OE when the detection trigger terminal OE inputs a high-level signal and the display scan signal output by the shift register at this stage is high at the same time, the corresponding The detection stage of the current stage performs detection and compensation operations on the shift register of the current stage, that is, selects the shift register of the current stage in the multi-stage shift register for detection and compensation.
- the detection trigger signal for example, non-progressive scanning
- the detection trigger terminal OE can be set to randomly perform detection and compensation while displaying the progressive display scan, thereby avoiding the problems caused by the progressive detection and compensation .
- the detection control sub-circuit 111 includes a detection control transistor M1.
- the control electrode of the detection control transistor M1 is connected to the detection trigger terminal OE, the first electrode of the detection control transistor is connected to the cascade output terminal CR, and the second electrode of the detection control transistor is connected to the detection control node H.
- the detection control sub-circuit 111 includes a detection control transistor M1.
- the control electrode of the detection control transistor M1 is connected to the cascade output terminal CR, the first electrode of the detection control transistor is connected to the detection trigger terminal OE, and the second electrode of the detection control transistor is connected to the detection control node H.
- the detection input sub-circuit 112 includes a detection input transistor M3 and a switching transistor M4.
- the control electrode of the detection input transistor M3 is connected to the detection control node H
- the first electrode of the detection input transistor M3 is connected to the first input terminal CLKE
- the second electrode of the detection input transistor M3 is connected to the first electrode of the switching transistor M4.
- the control electrode of the switching transistor M4 is connected to the first input terminal CLKE, and the second electrode is connected to the pull-up control terminal Q.
- the detection input sub-circuit 112 is connected to the first input terminal CLKE for providing a clock signal instead of a signal terminal (for example, VDD) for providing a constant high level, under the influence of the gate-source capacitance such as the transistor M3
- the level of the second pole of the transistor M3 can be higher, so that the level of the pull-up control terminal Q is higher, which can improve the stability of the shift register operation.
- the detection input sub-circuit 112 includes a detection input transistor M3, a switching transistor M4, and a detection leakage prevention transistor M4'.
- the control electrode of the detection input transistor M3 is connected to the detection control node H, the first electrode of the detection input transistor M3 is connected to the first input terminal CLKE, and the second electrode of the detection input transistor M3 is connected to the first electrode of the switching transistor M4.
- the control electrode of the switching transistor M4 is connected to the detection clock terminal CLKC, and the second electrode is connected to the first electrode of the detection leakage prevention transistor M4'.
- the control electrode of the detection leakage prevention transistor M4' is connected to the detection clock terminal CLKC, and the second electrode is connected to the pull-up control terminal Q.
- the detection clock terminal CLKC needs to provide an effective level in the charging sub-phase t1 of the detection phase T2.
- the levels of the detection clock terminal CLKC at other times may be as shown in FIGS. 6 and 9.
- the detection control node H is detected at a high level, and the control electrode of the switching transistor M4 is applied with a high level by detecting the clock terminal CLKC or the first input terminal CLKE.
- the detection input transistor M3 and the switching transistor M4 are turned on, so that the effective signal provided by the first input terminal CLKE can be output to the pull-up control terminal Q.
- the switching transistor M4 and the detection leakage prevention transistor M4' can be synchronously controlled.
- the control electrode of the switching transistor M4 and the detection leakage prevention transistor M4' receive an effective control signal, both are turned on at the same time, thereby allowing the detection input
- the sub-circuit 112 provides the signal of the first input terminal CLKE to the pull-up control terminal Q.
- the detection reset sub-circuit 114 includes a detection reset transistor M2, the control electrode of the detection reset transistor M2 is connected to the detection reset terminal CLKB, the first electrode is connected to the detection control node H, and the second electrode is connected to the first power supply terminal VGL1.
- the detection reset transistor M2 When the control electrode of the detection reset transistor M2 receives a valid reset signal, the detection reset transistor M2 is turned on, so that the detection control node H can be discharged.
- the second input circuit 120 includes a fifth transistor M5 whose control terminal is connected to the display trigger terminal DTR, the first electrode is connected to the third power supply terminal VDD, and the second electrode is connected to the pull-up control terminal Q.
- the shift register includes at least one of the detection leakage prevention transistor M4', the reset leakage prevention transistor M17, and the pull-down control leakage prevention transistor M18, in order to prevent the first such as the detection leakage prevention transistor M4' Leakage occurs at the node of the first pole of the reset leakage prevention transistor M17 and/or the first pole of the pull-down control leakage prevention transistor M18 (for example, the middle leakage prevention node OFF in FIGS.
- the shift register It also includes an intermediate leakage prevention transistor M16, the control electrode of the intermediate leakage prevention transistor M16 is electrically connected to the pull-up control terminal Q, the first pole is electrically connected to the third power supply terminal VDD, and the second pole is connected to the first One pole, the first pole of the reset leakage prevention transistor M17 and/or the first pole of the pull-down control leakage prevention transistor M18 (for example, the middle leakage prevention node OFF of FIGS. 4 and 5) are electrically connected.
- the first electrode of the middle leakage prevention transistor M16 may be connected to the pull-up control terminal Q instead of the third power supply terminal VDD.
- the specific structure of the output circuit 130 is not particularly limited.
- the output circuit 130 includes a cascade output sub-circuit and at least one scan signal output sub-circuit. Different output sub-circuits respectively provide two output signals with the same waveform, so as to avoid the influence of other signals on the scan signal output by the scan signal output terminal OUT.
- the output circuit 130 includes a cascade output sub-circuit 131 and a scan signal output sub-circuit 132.
- the output sub-circuit 130 includes a cascade output sub-circuit 131 and two scan signal output sub-circuits 132.
- the cascade output sub-circuit 131 includes a cascade output pull-up transistor M11, a cascade output pull-down transistor M12, and a pull-up control capacitor C2.
- the control pole of the cascade output pull-up transistor M11 is connected to the pull-up control terminal Q, the first pole is connected to the output clock signal terminal CLKD, and the second pole is connected to the cascade output terminal CR.
- the control electrode of the cascode output pull-down transistor M12 is connected to the pull-down control terminal QB, the first electrode is connected to the first power supply terminal VGL1, and the second electrode is connected to the cascade output terminal CR.
- the first pole of the pull-up control capacitor C2 is connected to the pull-up control terminal Q, and the second pole is connected to the cascade output terminal CR.
- the potential of the pull-up control point Q can be increased.
- the pull-up control point Q floats and the transistor M11 is turned on. Due to the bootstrap effect of the pull-up control capacitor C2, the potential of the pull-up control point Q can be coupled to Potential.
- each scan signal output sub-circuit 132 includes a scan output pull-up transistor and a scan output pull-down transistor.
- the control electrode of the scan output pull-up transistor is connected to the pull-up control terminal Q, the first electrode is connected to the output clock signal terminal, and the second electrode is connected to the scan signal output terminal.
- the control electrode of the scan output pull-down transistor is connected to the pull-down control terminal QB, the first electrode is connected to the second power terminal VGL2, and the second electrode is connected to the scan signal output terminal.
- the cascade output sub-circuit 131 and the scan signal output sub-circuit 132 are connected to a single output clock signal terminal CLKD.
- FIG. 5 there are multiple output clock signal terminals (eg, CLKD, CLKF, CLKG, etc. shown in FIG. 5 ), a cascade output sub-circuit 131 and multiple scan signal output sub-circuits 132 Connect to different output clock signal terminals.
- multiple output clock signal terminals eg, CLKD, CLKF, CLKG, etc. shown in FIG. 5
- a cascade output sub-circuit 131 and multiple scan signal output sub-circuits 132 Connect to different output clock signal terminals.
- the output circuit 130 has a scan signal output sub-circuit 132, the control electrode of the scan output pull-up transistor M13 is connected to the pull-up control terminal Q, and the first electrode is connected to the output clock signal terminal , The second pole is connected to the scan signal output terminal OUT.
- the control electrode of the scan output pull-down transistor M14 is connected to the pull-down control terminal QB, the first electrode is connected to the second power supply terminal VGL2, and the second electrode is connected to the scan signal output terminal OUT.
- the output circuit 130 has two scan signal output sub-circuits 132, and has two scan signal output terminals OUT1 and OUT2.
- the control electrode of the scan output pull-up transistor M13 is connected to the pull-up control terminal Q, the first electrode is connected to the output clock signal terminal CLKF, and the second electrode is connected to the scan signal output terminal OUT1.
- the control electrode of the scan output pull-down transistor M14 is connected to the pull-down control terminal QB, the first electrode is connected to the second power supply terminal VGL2, and the second electrode is connected to the scan signal output terminal OUT1.
- the control electrode of the scan output pull-up transistor M19 is connected to the pull-up control terminal Q, the first electrode is connected to the output clock signal terminal CLKG, and the second electrode is connected to the scan signal output terminal OUT2.
- the control electrode of the scan output pull-down transistor M20 is connected to the pull-down control terminal QB, the first electrode is connected to the second power terminal VGL2, and the second electrode is connected to the scan signal output terminal OUT2.
- the level of the low-level signal provided by the second power terminal VGL2 is generally higher than the level of the low-level signal provided by the first power terminal VGL1, so that the signal output from the signal output terminal can be lossless.
- a gate drive circuit in a second aspect, includes a cascaded multi-stage shift register, where the shift register is the above-mentioned shift register provided by the present disclosure.
- the so-called “cascade” refers to the output terminal (for example, the cascade output terminal) of the shift register of the current stage (for example, the Nth stage) and the second-stage (for example, N+2th stage) shift register
- the display trigger terminal (for example, the display trigger terminal DTR in the above embodiment) is electrically connected.
- the signal output from the output terminal of the shift register can be used to drive the thin film transistor connected to the gate line to turn on or off, and can be used to drive an external circuit for detection and compensation.
- the cascade output terminal CR of the 4n+1th stage shift register (for example, the first stage shift register A1 in FIG. 7) is connected to the 4n+3th stage shift register (for example, FIG. 7
- the display trigger terminal DTR of the third-stage shift register A3) the output clock signal terminal CLKD of the 4n+1th-stage shift register is connected to the first output clock signal line CLKD_1 for providing the first output clock signal
- the first The second reset control terminal DRST of the 4n+1-stage shift register is connected to the cascade output terminal CR of the 4n+4th stage shift register (for example, the fourth-stage shift register A4 in FIG. 7).
- the cascade output terminal CR of the 4n+2 stage shift register (for example, the second stage shift register A2 in FIG. 7) is connected to the 4n+4 stage shift register (for example, the fourth stage shift in FIG. 7
- the display trigger terminal DTR of the bit register A4), the output clock signal terminal CLKD of the 4n+2 stage shift register is connected to the second output clock signal line CLKD_2 for providing the second output clock signal, and the 4n+2 stage shift
- the second reset control terminal DRST of the register is connected to the cascade output terminal CR of the 4n+5th stage shift register (for example, the 5th stage shift register, not shown in the figure).
- the cascade output terminal CR of the 4n+3 stage shift register (for example, the third stage shift register A3 in FIG. 7) is connected to the 4n+5 stage shift register (for example, the 5th stage shift register, figure (Not shown in ), the output clock signal terminal CLKD of the 4n+3 stage shift register is connected to the third output clock signal line CLKD_3 for providing the third output clock signal, and the 4n+3 stage shift
- the second reset control terminal DRST of the register is connected to the cascade output terminal CR of the 4n+6th stage shift register (for example, the 6th stage shift register, not shown in the figure).
- the cascade output terminal CR of the 4n+4th stage shift register (for example, the fourth stage shift register A4 in FIG. 7) is connected to the 4n+6th stage shift register (for example, the 6th stage shift register, figure Display trigger terminal DTR, the output clock signal terminal of the 4n+4th stage shift register is connected to the fourth output clock signal line CLKD_4 for providing the fourth output clock signal, and the 4n+4th stage shift
- the second reset control terminal DRST of the register is connected to the cascade output terminal CR of the 4n+7th stage shift register (for example, the 7th stage shift register, not shown in the figure).
- n is an integer.
- the detection reset terminal CLKB of the odd-numbered shift register is connected to the first detection reset clock line CKB
- the detection reset terminal CLKB of the even-numbered shift register is connected to the second detection reset clock Line CKC.
- the shift register is a shift register as shown in FIGS. 4 and 5
- the detection clock terminal CLKC of the odd-numbered shift register is connected to the second detection reset clock line CKC
- the detection clock terminal of the even-numbered shift register CLKC is connected to the second detection reset clock line CKB.
- a display device including a gate driving circuit, wherein the gate driving circuit is the above-mentioned gate driving circuit provided by the present disclosure.
- the display panel includes multiple data lines, multiple gate lines, and multiple detection lines, and the multiple gate lines and multiple data lines divide the display panel into multiple pixel units.
- each pixel unit corresponds to a pixel circuit and a detection switch transistor T3, and each pixel unit includes a data writing transistor T2.
- the gate of the data writing transistor T2 and the gate of the detection switching transistor T3 are all connected to the corresponding gate lines (for example, in the embodiment shown in FIG. 8, the gate of the data writing transistor T1
- the electrode and the gate of the detection switch transistor T3 are electrically connected to the gate line GL1).
- the data writing transistor T2 When the gate line receives the display scan signal, the data writing transistor T2 is turned on, and the data input through the corresponding data line DL can be written into the pixel circuit to drive the pixel unit to emit light.
- the detection switch transistor T3 When the gate line receives the detection scan signal, the detection switch transistor T3 is turned on, so that the detection signal can be collected through the detection signal line SL.
- the pixel circuit includes a driving transistor T1, a data writing transistor T2, and an organic light emitting diode OLED.
- the first electrode of the data writing transistor T2 is electrically connected to the corresponding data line DL, and the second electrode of the data writing transistor T2 is electrically connected to the gate of the driving transistor T1.
- the first electrode of the driving transistor T1 is electrically connected to the high-level signal terminal ELVDD, the second electrode of the driving transistor T2 is electrically connected to the anode of the organic light emitting diode OLED, and the cathode of the organic light emitting diode OLED is grounded.
- the gate of the detection switch transistor T3 is electrically connected to the gate line GL1
- the first electrode of the detection switch transistor T3 is electrically connected to the anode of the organic light emitting diode OLED
- the second electrode of the detection switch transistor T3 is electrically connected to the detection signal line SL.
- a method for driving a shift register wherein the shift register is the above-mentioned shift register provided by the present disclosure.
- the duty cycle of the shift register is divided into a display phase T1 and a detection phase T2 that do not overlap in time, and each of the display phase and the detection phase includes a first sub-phase t1, a second sub-phase t2, and a third sub-phase Phase t3.
- the driving method includes: in the first sub-stage t1 of the display stage T1, the second input circuit 120 applies the signal provided by the second input terminal VDD to the pull-up control terminal Q in response to the signal of the display trigger terminal DTR Valid signal; in the second sub-phase t2 of the display phase T1, the voltage of the pull-down control terminal QB is determined as an invalid voltage by the control and output circuit in response to the signal of the pull-up control terminal Q, and in response to The signal of the pull-up control terminal Q outputs the signal provided by the output clock signal terminal CLKD through the signal output terminals OUT and CR; in the third sub-phase t3 of the display phase T1, the second reset circuit 150 responds The signal of the second reset control terminal DRST provides the invalid signal of the first power supply terminal VGL1 to the pull-up control terminal Q; in the first sub-stage t1 of the detection stage T2, the first input circuit 110 responds At the signals of the detection trigger terminal OE and the signal output terminal CR, an effective signal provided by the first input
- the driving process of the display device including the above shift register can be seen in FIG. 9, wherein the display device includes a gate drive circuit, and the gate drive circuit includes a plurality of cascaded shift registers described above, and these shift registers Cascade as shown in Figure 7.
- the driving process includes multiple frame periods (only the first two frame periods are shown in FIG. 9, the first frame period is 1F and the second frame period is 2F), and each frame period includes the display phase T1 and detection Phase T2.
- the signals on the first detection reset clock line CKB connected to the detection reset terminal CLKB of the odd-numbered shift register and the second detection reset clock line CKC connected to the detection reset terminal CLKB of the even-numbered shift register are complementary, that is, the first The detection reset clock line CKB provides a signal during an odd frame period and is always low during an even frame period, and the second detection reset clock line CKC provides a signal during an even frame period and is always low during an odd frame period.
- the signals provided by the first to fourth output clock signal lines CLKD_1, CLKD_2, CLKD_3, and CLKD_4 are sequentially delayed by a certain time, so that multiple shift registers sequentially output display scan signals in a frame period, thereby implementing progressive display scan.
- the signals of the detection trigger terminals of the shift registers of different stages are controlled separately, so that within a predetermined number of frame periods, all the detection input circuits of the shift register pull the control terminal to the pull-up control terminal during the detection phase A valid signal was output.
- the detection stage T2 is entered after the last stage of the shift register completes the output of the display scan signal.
- the display trigger signal DTR is provided to the display input circuit 110 of the corresponding shift register, the first clock signal is provided to the output clock signal terminal CLKD of the shift register, and the signal in the shift register The output terminal displays the scan signal.
- a valid third clock signal is provided to the first input terminal CLKE of the corresponding shift register, and then, a detection scan signal is output at the signal output terminal of the shift register.
- the first input circuit is controlled to store the initial trigger signal during the display phase T1.
- the first input terminal CLKE provides invalid signals. Therefore, the detection input sub-circuit of the first input circuit is disconnected from the pull-up control terminal, thereby ensuring that the first input The signal stored in the circuit will not affect the output of the display scan signal.
- the gate driving circuit includes two shift register groups, the odd-numbered shift register is a shift register group, and the even-numbered shift register is a shift register group.
- the gate driving circuit includes four first clock signal lines, which are respectively a first output clock signal line CLKD_1 and a third output clock signal line CLKD_3 that provide an output clock signal to the odd-numbered shift register, and
- the even-numbered shift register provides a second output clock signal line CLKD_2 and a fourth output clock signal line CLKD_4 that output clock signals.
- H ⁇ 1> represents the potential of the detection control node of the detection input circuit of the first-stage shift register
- H ⁇ 2> represents the detection control node of the detection input circuit of the second-stage shift register The potential.
- Each frame period of the driving method includes a display phase T1 and a detection phase T2.
- the operation in the display stage T1 may include a charging sub-stage t1, an output sub-stage t2, and a pull-down sub-stage t3.
- the high-level signal provided by the high-level signal terminal VDD is written to the pull-up control terminal Q, so that both the cascade output pull-up transistor M11 and the scan output pull-up transistor M13 are turned on.
- the output clock signal terminal CLKD receives an invalid clock signal, so an invalid signal can be output through the output terminal OUT ⁇ 1>. Since the control signal input transistor M7 is turned on, the voltage dividing effect of the control signal input transistor M7 and the first pull-down control transistor M8 makes the pull-down control terminal QB low, ensuring that the second pull-down control transistor M9 is turned off, and the cascade output pull-down The transistor M12 and the scan output pull-down transistor M14 are all turned off.
- the trigger signal DTR is displayed as low level. Therefore, the fifth transistor M5 is turned off, so that the pull-up control terminal Q is floating, and the bootstrap effect of the storage capacitor C2 couples the pull-up control terminal Q. To a higher potential, thereby maintaining the cascade output pull-up transistor M11 and the scan output pull-up transistor M13 on. At this time, a valid clock signal is input to the output clock signal terminal CLKD, thereby ensuring that the signal output terminal (including the cascade output terminal CR and the scan signal output terminal OUT) outputs a valid signal during the output sub-phase t2.
- the pull-down control terminal QB is a low-level signal, thereby ensuring the cascade output pull-down transistor M12 and the scan output pull-down transistor M14 disconnect. Also, it is ensured that the second pull-down control transistor M9 is turned off, thereby preventing the pull-up control terminal Q from being pulled low.
- the gate of the second reset transistor M6 receives a valid reset signal, thereby turning on the second reset transistor M6, pulling the pull-up control terminal Q potential low, and causing the first pull-down control transistor M8
- the second pull-down control transistor M9 is turned off.
- the effective signal input through the control signal input transistor M7 causes the cascade output pull-down transistor M12 to turn on, the scan signal output pull-down transistor M14 to turn on, and pulls down the potential of the cascade signal output terminal and the scan signal output terminal OUT ⁇ 1> .
- the detection stage T2 is entered.
- an effective first clock signal is provided to the first-stage shift register A1 through the clock signal terminal CLKD, and an effective clock signal is provided to the gate of the switching transistor M4 through the first input terminal CLKE, so that the switching transistor M4 is turned on, and the signal stored in the first storage sub-circuit 113 (for example, the storage capacitor C1 shown in FIG. 2) makes the detection input transistor M3 turned on to write the effective signal provided by the first input terminal CLKE to the upper
- the control terminal Q is pulled to turn on the cascade output pull-up transistor M11 and the scan output pull-up transistor M13.
- the signal output terminal outputs the first clock signal provided by the output clock signal terminal CLKD.
- an effective reset signal is provided to the gate of the first reset transistor M15 through the reset control terminal TRST, thereby turning on the first reset transistor M15, pulling the potential of the pull-up control terminal Q low, and causing the first pull-down control The transistor M8 is turned off.
- the potential of the pull-down control terminal QB is high, and the low potential of the pull-up control terminal Q is further maintained.
- the high potential of the pull-down control terminal QB turns on the cascade output pull-down transistor M12 and the scan output pull-down transistor M14, and pulls down the potentials of the cascade signal output terminal and the scan signal output terminal OUT ⁇ 1>.
- the ratio of the output waveform superimposition can be completed by adjusting the pulse width of the first clock signal and the pulse width of the input signal.
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Abstract
本公开提供一种移位寄存器,所述移位寄存器包括多个信号输入电路、多个复位电路、以及控制和输出电路。其中,所述移位寄存器的工作周期分为多个阶段,所述多个阶段在时间上不重叠,并且每个所述阶段至少包括第一子阶段和第二子阶段。所述多个信号输入电路各自配置为响应于所述多个输入控制端中的相应一个的信号,在所述多个阶段中的不同阶段的第一子阶段向所述上拉控制端施加由所述多个信号输入端中的相应一个提供的信号。所述多个复位电路各自配置为响应于所述多个复位控制端中的相应一个的信号,在所述多个阶段中的不同阶段的第二子阶段向所述上拉控制端施加由所述第一电源端提供的第一电源信号。所述多个输入电路和多个复位电路共用所述控制和输出电路,所述控制和输出电路基于所述上拉控制端的信号输出信号,该信号的波形可以是与多个信号输入电路所提供的信号相对应的多个波形的叠加。
Description
相关申请的交叉引用
本申请要求于2018年11月29日提交至中国知识产权局的中国专利申请No.201811442460.4的优先权,其全部内容以引用的方式合并于此。
本公开涉及显示技术领域,具体地,涉及一种移位寄存器、包括该移位寄存器的栅极驱动电路、包括该栅极驱动电路的显示装置和该显示装置的驱动方法。
对于有机发光二极管显示面板而言,像素电路包括驱动有机发光二极管发光的驱动晶体管。由于制造工艺不均匀,导致不同像素器中的驱动晶体管的阈值电压不一致,因此,同一个显示面板中不同的像素器中的发光二极管亮度不均匀。有鉴于此,需要设置补偿电路。
窄边框的显示装置是一种市场趋势,移位寄存器结构过于复杂则不利于实现窄边框的显示装置。
因此,需要简化移位寄存器的结构,特别是具有补偿功能的移位寄存器的结构。
发明内容
在一方面,提供一种移位寄存器,包括:多个信号输入电路,其连接至多个信号输入端、多个输入控制端、以及上拉控制端;多个复位电路,其连接至多个复位控制端、第一电源端和所述上拉控制端;控制和输出电路,其连接至所述上拉控制端、下拉控制端、输出电源端、输出时钟信号端和输出信号端,并且配置为:根据所述上拉控制端处的电压确定所述下拉控制端的电压,响应于所述上拉控制端的电压而通过所述信号输出端输出所述输出时钟信号端提供的信号,并且 响应于所述下拉控制端的电压而通过所述信号输出端输出所述输出电源端提供的信号。所述移位寄存器的工作周期分为多个阶段,所述多个阶段在时间上不重叠,并且每个所述阶段至少包括第一子阶段和第二子阶段。所述多个信号输入电路各自配置为响应于所述多个输入控制端中的相应一个的信号,在所述多个阶段中的不同阶段的第一子阶段向所述上拉控制端施加由所述多个信号输入端中的相应一个提供的信号。所述多个复位电路各自配置为响应于所述多个复位控制端中的相应一个的信号,在所述多个阶段中的不同阶段的第二子阶段向所述上拉控制端施加由所述第一电源端提供的第一电源信号。
在一些实施例中,所述控制和输出电路包括:下拉控制电路,连接至所述上拉控制端、所述下拉控制端、所述第一电源端和下拉控制时钟端,并且配置为根据上拉控制端处的电压,将由第一电源端和下拉控制时钟端中的一者提供的信号施加至下拉控制端;以及输出电路,连接至所述信号输出端、所述输出电源端、所述输出时钟信号端、所述上拉控制端和所述下拉控制端,并且配置为响应于上拉控制端的电压,通过信号输出端输出输出时钟信号端提供的信号,并且响应于下拉控制端的电压,通过所述信号输出端输出所述输出电源端提供的信号。
在一些实施例中,所述移位寄存器的工作周期分为检测阶段和显示阶段,所述多个信号输入电路包括第一输入电路和第二输入电路,所述多个信号输入端包括第一输入端和第二输入端,所述信号输出端包括级联输出端和扫描信号输出端。所述第一输入电路连接至所述级联输出端、检测触发端、所述第一输入端和所述上拉控制端,并且配置为响应于所述级联输出端和所述检测触发端均接收到有效电平,在所述检测阶段的第一子阶段向所述上拉控制端施加由所述第一输入端提供的信号。所述第二输入电路连接至显示触发端、所述第二输入端和所述上拉控制端,并且配置为响应于所述显示触发端接收到有效电平,在所述显示阶段的第一子阶段向所述上拉控制端施加由所述第二输入端提供的信号。
在一些实施例中,所述多个复位电路包括第一复位电路和第二 复位电路,所述多个复位控制端包括第一复位控制端和第二复位控制端。所述第一复位电路连接至所述第一复位控制端、所述第一电源端和所述上拉控制端,配置为响应于所述第一复位控制端的电压,在所述检测阶段的第二子阶段将所述第一电源信号提供给所述上拉控制端。所述第二复位电路连接至所述第二复位控制端、所述第一电源端和所述上拉控制端,配置为响应于所述第二复位控制端的电压,在所述显示阶段的第二子阶段将所述第一电源信号提供给所述上拉控制端。
在一些实施例中,所述第一输入电路包括:检测控制子电路,其连接至所述级联输出端、所述检测触发端和检测控制节点,并且配置为响应于所述级联输出端和所述检测触发端中的一者接收到有效电平,向所述检测控制节点施加由所述级联输出端和所述检测触发端中的另一者提供的信号;检测输入子电路,其连接至所述检测控制节点、所述第一输入端和所述上拉控制端,并且配置为响应于所述检测控制节点的有效电平,向所述上拉控制端施加由所述第一输入端提供的信号;以及检测存储子电路,其连接至所述检测控制节点和所述第一电源端,配置为存储所述检测控制节点处的电压。
在一些实施例中,所述第一输入电路还包括:检测复位子电路,其连接至所述检测控制节点、检测复位端和所述第一电源端,配置为响应于所述检测复位端的电压将所述第一电源信号提供给所述检测控制节点。
在一些实施例中,所述检测控制子电路包括检测控制晶体管,所述检测控制晶体管的控制极连接至所述检测触发端,所述检测控制晶体管的第一极连接至所述级联输出端,所述检测控制晶体管的第二极连接至所述检测控制节点。
在一些实施例中,所述检测控制子电路包括检测控制晶体管,所述检测控制晶体管的控制极连接至所述级联输出端,所述检测控制晶体管的第一极连接至所述检测触发端,所述检测控制晶体管的第二极连接至所述检测控制节点。
在一些实施例中,所述检测输入子电路包括:检测输入晶体管 和开关晶体管。所述检测输入晶体管的控制极连接至所述检测控制节点,所述检测输入晶体管的第一极连接至所述第一输入端,所述检测输入晶体管的第二极连接至所述开关晶体管的第一极。所述开关晶体管的控制极连接所述第一输入端,第二极连接至所述上拉控制端。
在一些实施例中,所述检测输入子电路包括:检测输入晶体管、开关晶体管和检测防漏电晶体管。所述检测输入晶体管的控制极连接至所述检测控制节点,所述检测输入晶体管的第一极连接至所述第一输入端,所述检测输入晶体管的第二极连接至所述开关晶体管的第一极。所述开关晶体管的控制极连接至检测时钟端,第二极连接至所述检测防漏电晶体管的第一极。所述检测防漏电晶体管的控制极连接至所述检测时钟端,所述第一极连接至中间防漏节点,第二极连接至所述上拉控制端。
在一些实施例中,所述检测复位子电路包括检测复位晶体管,所述检测复位晶体管的控制极连接至所述检测复位端,第一极连接至所述检测控制节点,第二极连接至所述第一电源端。
在一些实施例中,所述下拉控制电路包括:至少一个下拉控制输入子电路,其连接至所述下拉控制时钟端和下拉控制端,配置为向所述上拉控制端施加由所述下拉控制时钟端提供的信号;以及控制子电路,其连接至所述上拉控制端、所述下拉控制端和所述第一电源端,并且配置为根据所述上拉控制端处的电压,将所述下拉控制端的电压确定为由所述第一电源端和所述下拉控制时钟端中的一者提供的电压。
在一些实施例中,所述控制子电路包括第一下拉控制晶体管和第二下拉控制晶体管。所述第一下拉控制晶体管的控制极连接至所述上拉控制端,第一极连接至所述下拉控制端,第二极连接至所述第一电源端。所述第二下拉控制晶体管的控制极连接至所述下拉控制端,第一极连接至所述上拉控制端,第二极连接至所述第一电源端。
在一些实施例中,所述控制子电路包括第一下拉控制晶体管、第二下拉控制晶体管和下拉控制防漏电晶体管。所述第一下拉控制晶体管的控制极连接至所述上拉控制端,第一极连接至所述下拉控制 端,第二极连接至所述第一电源端。所述第二下拉控制晶体管的控制极连接至所述下拉控制端,第一极连接至所述上拉控制端,第二极连接至所述下拉控制防漏电晶体管的第一极。所述下拉控制防漏电晶体管的控制极连接至所述下拉控制端,所述下拉控制防漏电晶体管的第二极连接至所述第一电源端。
在一些实施例中,所述下拉控制时钟端包括多个下拉控制时钟端,通过所述多个下拉控制时钟端在不同的时段提供有效信号。所述下拉控制电路包括多个所述下拉控制输入子电路,每个所述下拉控制输入子电路连接至所述多个下拉控制时钟端之一和所述下拉控制端,配置为响应于该下拉控制时钟端接收到有效信号,向所述下拉控制端施加由该下拉控制时钟端提供的信号。
在一些实施例中,每个所述下拉控制输入子电路包括下拉控制输入晶体管。所述下拉控制输入晶体管的控制极和第一极连接至所述多个下拉控制时钟端之一,第二极连接至所述下拉控制端。
在一些实施例中,所述输出电源端包括第二电源端和所述第一电源端。所述输出电路包括:级联输出子电路,其连接至所述级联输出端、所述输出时钟信号端、所述上拉控制端、所述下拉控制端和所述第一电源端,并且配置为响应于所述上拉控制端的电压,通过所述级联输出端输出所述输出时钟信号端提供的信号,并且响应于所述下拉控制端的电压,通过所述级联输出端输出所述第一电源端提供的信号,和至少一个扫描信号输出子电路,其连接至所述扫描信号输出端、所述输出时钟信号端、所述上拉控制端、所述下拉控制端和所述第二电源端,并且配置为响应于所述上拉控制端的电压,通过所述扫描信号输出端输出所述输出时钟信号端提供的信号,并且响应于所述下拉控制端的电压,通过所述扫描信号输出端输出所述第二电源端提供的信号。
在一些实施例中,所述级联输出子电路包括:级联输出上拉晶体管、级联输出下拉晶体管和上拉控制电容器。所述级联输出上拉晶体管的控制极连接至上拉控制端,第一极连接至所述输出时钟信号端,第二极连接至所述级联输出端。所述级联输出下拉晶体管的控制 极连接至下拉控制端,第一极连接至所述第一电源端,第二极连接至所述级联输出端。所述上拉控制电容器的第一极连接至所述上拉控制端,第二极连接至所述级联输出端。
在一些实施例中,所述扫描信号输出子电路包括:扫描输出上拉晶体管和扫描输出下拉晶体管。所述扫描输出上拉晶体管的控制极连接至上拉控制端,第一极连接至所述输出时钟信号端,第二极连接至所述扫描信号输出端。所述扫描输出下拉晶体管的控制极连接至下拉控制端,第一极连接至所述第二电源端,第二极连接至所述扫描信号输出端。
在一些实施例中,所述第一复位电路包括:第一复位晶体管,其控制极连接至第一复位控制端,第一极连接至上拉控制端,第二极连接至第一电源端。所述第二复位电路包括:第二复位晶体管,其控制极连接至第二复位控制端,第一极连接至上拉控制端,第二极连接至第一电源端。
在一些实施例中,所述第一复位电路包括:第一复位晶体管,其控制极连接至第一复位控制端,第一极连接至上拉控制端,第二极连接至第一电源端。所述第二复位电路包括:第二复位晶体管和复位防漏电晶体管,所述第二复位晶体管的控制极连接至第二复位控制端,第一极连接至上拉控制端,第二极连接至所述复位防漏电晶体管的第一极,所述复位防漏电晶体管的控制极连接至所述第二复位控制端,第一极连接至中间防漏节点,第二极连接至第一电源端。
在一些实施例中,移位寄存器还包括:中间防漏电晶体管,所述中间防漏电晶体管的控制极连接至所述上拉控制端,第一极与第三电源端或所述上拉控制端电连接,第二极连接至所述中间防漏节点。
在第二方面,提供了一种栅极驱动电路。所述栅极驱动电路包括级联的多级移位寄存器,所述移位寄存器为上述移位寄存器。第4n+1级移位寄存器的级联输出端连接至第4n+3级移位寄存器的显示触发端,第4n+1级移位寄存器的输出时钟信号端连接至用于提供第一输出时钟信号的第一输出时钟信号线,第4n+1级移位寄存器的第二复位控制端连接至第4n+4级移位寄存器的级联输出端。第4n+2 级移位寄存器的级联输出端连接至第4n+4级移位寄存器的显示触发端,第4n+2级移位寄存器的输出时钟信号端连接至用于提供第二输出时钟信号的第二输出时钟信号线,第4n+2级移位寄存器的第二复位控制端连接至第4n+5级移位寄存器的级联输出端。第4n+3级移位寄存器的级联输出端连接至第4n+5级移位寄存器的显示触发端,第4n+3级移位寄存器的输出时钟信号端连接至用于提供第三输出时钟信号的第三输出时钟信号线,第4n+3级移位寄存器的第二复位控制端连接至第4n+6级移位寄存器的级联输出端。第4n+4级移位寄存器的级联输出端连接至第4n+6级移位寄存器的显示触发端,第4n+4级移位寄存器的输出时钟信号端连接至用于提供第四输出时钟信号的第四输出时钟信号线,第4n+4级移位寄存器的第二复位控制端连接至第4n+7级移位寄存器的级联输出端。
在第三方面,提供了一种显示装置,所述显示装置包括上述栅极驱动电路。
在第四方面,提供了一种移位寄存器的驱动方法,所述移位寄存器是上述移位寄存器。所述移位寄存器的工作周期分为在时间上不重叠的显示阶段和检测阶段,并且显示阶段和检测阶段中的每一个包括第一子阶段、第二子阶段和第三子阶段。所述驱动方法包括:在显示阶段的第一子阶段,由第二输入电路响应于所述显示触发端的信号,向所述上拉控制端施加由所述第二输入端提供的有效信号;在显示阶段的第二子阶段,由所述控制和输出电路响应于所述上拉控制端的信号将所述下拉控制端的电压确定为无效电压,并且响应于所述上拉控制端的信号而通过所述信号输出端输出所述输出时钟信号端提供的信号;在显示阶段的第三子阶段,由第二复位电路响应于所述第二复位控制端的信号,将所述第一电源端的无效信号提供给所述上拉控制端;在检测阶段的第一子阶段,由第一输入电路响应于所述检测触发端和所述信号输出端的信号,向所述上拉控制端施加由所述第一输入端提供的有效信号;在检测阶段的第二子阶段,由所述控制和输出电路响应于所述上拉控制端的信号将所述下拉控制端的电压确定为无效电压,并且响应于所述上拉控制端的信号而通过所述信号输出 端输出所述输出时钟信号端提供的信号;在检测阶段的第三子阶段,由第一复位电路响应于所述第一复位控制端的信号,将所述第一电源端的无效信号提供给所述上拉控制端。
附图是用来提供对本公开的进一步理解,并且构成说明书的一部分,与下面的具体实施方式一起用于解释本公开,但并不构成对本公开的限制。在附图中:
图1是本公开所提供的移位寄存器的框图;
图2是本公开所提供的移位寄存器的电路图;
图3是本公开所提供的移位寄存器的电路图;
图4是本公开所提供的移位寄存器的电路图;
图5是本公开所提供的移位寄存器的电路图;
图6是本公开所提供的移位寄存器的工作时序图;
图7是本公开所提供的栅极驱动电路的框图;
图8是本公开所提供的显示面板中像素单元中像素电路的示意图;
图9是驱动所述栅极驱动电路的信号时序图;
图10是本公开所提供的移位寄存器的框图。
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是,此处所描述的具体实施方式仅用于说明和解释本公开,并不用于限制本公开。
在本文中,一个信号或电平被称为“有效”,是指该信号或电平能够驱动相应的晶体管导通和/或使相应的电路开启,一个信号或电平被称为“无效”,是指该信号或电平能够驱动相应的晶体管关断和/或使相应的电路关闭。例如,对于P型晶体管,有效电平为低电平,无效电平为高电平;对于N型晶体管,有效电平为高电平,无效电平为低电平。在以下示例性描述中,以所有晶体管为N型晶体 管、有效电平为高电平、无效电平为低电平的情况为例进行描述,但是本公开不限于此。
在一个方面,本公开实施例提供一种移位寄存器。该移位寄存器包括:多个信号输入电路、多个复位电路、控制和输出电路。在一些实施例中,参照图10,控制和输出电路可包括下拉控制电路140和输出电路130。
下拉控制电路140,连接至上拉控制端Q、下拉控制端QB、第一电源端VGL1和下拉控制时钟端,并且配置为根据上拉控制端Q处的电压,将由第一电源端VGL1和下拉控制时钟端中的一者提供的信号施加至下拉控制端QB。其中,第一电源端VGL1用于提供第一电源信号,其具有恒定的无效电平。
输出电路130,连接至信号输出端、输出电源端、输出时钟信号端、上拉控制端Q和下拉控制端QB,并且配置为响应于上拉控制端Q的电压,通过信号输出端输出输出时钟信号端提供的信号,并且响应于下拉控制端QB的电压,通过信号输出端输出输出电源端提供的信号。其中,输出电源端用于提供恒定的无效电平电压。
多个信号输入电路,连接至多个信号输入端、多个输入控制端、以及上拉控制端Q。
多个复位电路,连接至多个复位控制端、第一电源端VGL1和上拉控制端Q。
根据本公开的移位寄存器的工作周期分为多个阶段,多个阶段在时间上不重叠,并且每个阶段至少包括第一子阶段和第二子阶段。多个信号输入电路各自配置为响应于多个输入控制端中的相应一个的信号,在多个阶段中的不同阶段的第一子阶段向上拉控制端Q施加由多个信号输入端中的相应一个提供的信号。多个复位电路各自配置为响应于多个复位控制端中的相应一个的信号,在多个阶段中的不同阶段的第二子阶段向上拉控制端Q施加由第一电源端VGL1提供的第一电源信号。
图1示出了移位寄存器的一个示例。图1所示的移位寄存器包括多个信号输入电路110和120、多个复位电路150和160、输出电 路130和下拉控制电路140。
在图1所示的示例中,多个信号输入端包括第一输入端CLKE和第二输入端VDD,多个输入控制端包括作为第一输入控制端的检测触发端OE和级联输出端CR、以及作为第二输入控制端的显示触发端DTR,多个复位控制端包括第一复位控制端TRST和第二复位控制端DRST,并且移位寄存器的工作周期被分为在时间上不重叠的两个阶段:显示阶段T1和检测阶段T2(见图6)。但是,本公开不限于此。
作为检测输入电路的第一输入电路110连接至级联输出端CR、检测触发端OE、第一输入端CLKE和上拉控制端Q,并且配置为响应于级联输出端CR和检测触发端OE均接收到有效电平,在检测阶段T2的第一子阶段向上拉控制端Q施加由第一输入端CLKE提供的信号。
作为显示输入电路的第二输入电路120连接至显示触发端DTR、作为第二输入端的第三电源端VDD和上拉控制端Q,并且配置为响应于显示触发端DTR接收到有效电平,在显示阶段T1的第一子阶段向上拉控制端Q施加由第三电源端VDD提供的信号。其中,第三电源端VDD用于提供第三电源信号,其具有恒定的有效电平。
第一复位电路160连接至第一复位控制端TRST、第一电源端VGL1和上拉控制端Q,配置为响应于第一复位控制端TRST的电压,在检测阶段T2的第二子阶段将第一电源信号提供给上拉控制端Q。
第二复位电路150连接至第二复位控制端DRST、第一电源端VGL1和上拉控制端Q,配置为响应于第二复位控制端DRST的电压,在显示阶段T1的第二子阶段将第一电源信号提供给上拉控制端Q。
在图1所示的示例中,多个信号输入电路110和120在一个工作周期的不同时间段轮流向上拉控制端Q提供信号,并且相应地,多个复位电路150和160在不同时间段轮流向上拉控制端提供无效电平(即,将上拉控制端Q复位)。
也就是说,在本公开所提供的移位寄存器中,多个信号输入电路和多个复位电路共用输出电路和下拉控制电路,因此,所述信号输 出端输出的信号是多个仅具有一个信号输入电路的移位寄存器输出的信号的叠加。
并且,多个信号输入电路和多个复位电路共用输出电路和下拉控制电路,无需设置连接器,从而可以简化移位寄存器的结构,有利于实现窄边框。
例如,在图1所示的示例中,可以通过一个移位寄存器的一个信号输出端(例如,扫描信号输出端)同时输出显示扫描信号和检测扫描信号。此外,由于用于提供检测输入信号的第一输入电路110由级联输出端CR和检测触发端OE两者控制,因此,可以实现随机检测功能,稍后将对此进行描述。
在一些实施例中,信号输出端包括扫描信号输出端OUT和级联输出端CR。输出电路130包括级联输出子电路131和至少一个扫描信号输出子电路(例如,图1-4中的132,或图5中的132和133)。
级联输出子电路131连接至级联输出端CR、输出时钟信号端CLKD、上拉控制端Q、下拉控制端QB和第一电源端VGL1,并且配置为响应于上拉控制端Q的电压,通过级联输出端CR输出所述输出时钟信号端CLKD提供的信号,并且响应于下拉控制端QB的电压,通过级联输出端CR输出第一电源端VGL1提供的信号。
扫描信号输出子电路连接至扫描信号输出端OUT、输出时钟信号端CLKD、上拉控制端Q、下拉控制端QB和第二电源端VGL2,并且配置为响应于上拉控制端Q的电压,通过扫描信号输出端OUT输出所述输出时钟信号端CLKD提供的信号,并且响应于下拉控制端QB的电压,通过扫描信号输出端OUT输出第二电源端VGL2提供的信号。
在上述示例中,将第一电源端VGL1和第二电源端VGL2作为输出电源端,但是本公开不限于此,只要输出电源端能够提供恒定无效电平即可。
对于移位寄存器的一个工作周期的所述多个阶段中的每一个,所述多个信号输入电路之一和所述多个复位电路之一工作,并且该阶段可以包括作为第一子阶段的充电子阶段t1、输出子阶段t2和作为 第二子阶段的下拉子阶段t3(见图6)。
在充电子阶段t1,由所述多个信号输入电路之一向上拉控制端Q提供信号,以对上拉控制端Q进行充电,例如,在显示阶段T1的充电子阶段t1,由第二输入电路120向Q点提供高电平信号,在检测阶段T2的充电子阶段t1,由第一输入电路110向Q点提供高电平信号。向输出时钟信号端CLKD提供无效的第一时钟信号,输出电路130通过信号输出端(例如CR和OUT)输出无效的第一时钟信号。
在输出子阶段t2,信号输入电路不再向上拉控制端Q提供信号,使得上拉控制端Q浮置,上拉控制端Q的电位仍为高,从而输出电路130维持从信号输出端(例如CR和OUT)输出第一时钟信号。在输出子阶段t2,第一时钟信号为有效信号,从而可以使得信号输出端输出有效信号,并且,在输出子阶段t2,下拉控制电路140根据上拉控制端Q的电位而将下拉控制端QB的电位拉低。
在下拉子阶段t3,第一时钟信号为低电平信号,上拉控制端Q的电位初始为高。然后,多个复位电路之一向上拉控制端Q提供第一电源信号,例如,在显示阶段T1的下拉子阶段t3,第二复位电路150响应于第二复位控制端DRST的高电平而将上拉控制端Q的电平拉低,在检测阶段T2的下拉子阶段t3,第一复位电路160响应于第一复位控制端TRST的高电平而将上拉控制端Q的电平拉低。此时,由于上拉控制端Q的电位为无效电平,因此,下拉控制电路140将下拉控制时钟端的信号施加至下拉控制端QB,以使下拉控制端QB的电位为有效电平。输出电路130在下拉控制端QB的有效电平的控制下,将输出电源端提供的无效电平输出至信号输出端。
每个信号输入电路向上拉控制端Q提供信号时,移位寄存器均进入充电子阶段t1,并且经历输出子阶段t2和下拉子阶段t3。换言之,在整个移位寄存器的一个工作循环中,充电子阶段、输出子阶段和下拉子阶段这一操作序列会重复多次,从而使移位寄存器可以输出多个扫描信号的叠加。
在一些实施例中,下拉控制电路140可包括控制子电路143和 至少一个输入子电路。所述输入子电路连接至下拉控制时钟端和下拉控制端Q,配置为向上拉控制端Q施加由下拉控制时钟端提供的信号。控制子电路143,连接至上拉控制端Q、下拉控制端QB和第一电源端VGL1,并且配置为根据上拉控制端Q处的电压,将下拉控制端QB的电压确定为由第一电源端VGL1和下拉控制时钟端中的一者提供的电压。
为了延长下拉控制子电路140的使用寿命,优选地在一些实施例中,下拉控制电路140包括控制子电路143和多个输入子电路(例如,在图1的示例中,两个输入子电路141和142),并且所述移位寄存器包括多个下拉控制时钟端(例如,在图1的示例中,移位寄存器包括第一下拉控制时钟端CLKM和第二下拉控制时钟端CLKN)。
多个所述输入子电路分别用于在不同的时段向所述下拉控制端提供有效的下拉控制信号。在所述移位寄存器的任何工作时间,多个输入子电路中的一个与控制子电路143组成一个功能上完整的下拉控制电路140,其余输入子电路处于闲置的状态。多个输入子电路交替地通电,从而可以延长单个输入子电路的使用寿命。
每个输入子电路电连接至多个下拉控制时钟端中的相应一个以及下拉控制端QB,配置为响应于该下拉控制时钟端接收到有效信号,向下拉控制端QB施加由该下拉控制时钟端提供的信号。需要解释的是,当移位寄存器运行时,该移位寄存器中的多个下拉控制时钟端中的一个接收到有效的下拉控制时钟信号,其余下拉控制时钟端均接收到无效的下拉控制时钟信号。
在下拉子阶段t3,可以通过输入子电路将有效的下拉控制时钟信号提供至下拉控制端QB。
当移位寄存器运行了一段时间后,可以停止向当前正在接收有效的下拉控制时钟信号的输入子电路输入有效的下拉控制时钟信号,而向其中一个没有接收到有效的下拉控制时钟信号的输入子电路提供有效的下拉控制时钟信号。
例如,在图1中所示的实施方式中,下拉控制子电路140包括两个下拉控制时钟端,该两个下拉控制时钟端分别为第一下拉控制时 钟端CLKM和第二下拉控制时钟端CLKN,并且,下拉控制子电路140包括与第一下拉控制时钟端CLKM电连接的输入子电路141和与第二下拉控制时钟端CLKN电连接的输入子电路142。
在本公开中,对何时向第一下拉控制时钟端CLKM提供有效的下拉控制时钟信号、何时向第二下拉控制时钟端CLKN提供有效的时钟信号并不做特殊要求。例如,每100帧更换一次,在显示前100帧画面时,向第一下拉控制时钟端CLKM提供有效的下拉控制时钟信号,在显示第200帧至第300帧画面时,向第二下拉控制时钟端CLKN提供有效的下拉控制时钟信号,依次类推。
在本公开中,对所述输入子电路的具体结构不做特殊的限定,在一些实施例中,所述输入子电路包括可以下拉控制输入晶体管,所述下拉控制输入晶体管的栅极和第一极与相应的下拉控制时钟端电连接,第二极与所述下拉控制端Q电连接。
在一些实施例中,例如,参照图2和图3,控制子电路143可以包括第一下拉控制晶体管M8和第二下拉控制晶体管M9。第一下拉控制晶体管M8的控制极连接至上拉控制端Q,第一极连接至下拉控制端QB,第二极连接至第一电源端VGL1。第二下拉控制晶体管M9的控制极连接至下拉控制端QB,第一极连接至上拉控制端Q,第二极连接至第一电源端VGL1。
在图2中所示的实施方式中,输入子电路141包括控制信号输入晶体管M7,输入子电路142包括控制信号输入晶体管M10。如图2中所示,控制信号输入晶体管M7的控制极和第一极连接至第一下拉控制时钟端CLKM,控制信号输入晶体管M7的第二极与下拉控制端QB电连接。控制信号输入晶体管M10的控制极和第一极连接至第二下拉控制时钟端CLKN,控制信号输入晶体管M10的第二极与下拉控制端QB电连接。
在本公开中,控制信号输入晶体管M7的尺寸与控制信号输入晶体管M10的尺寸相同,但是,控制信号输入晶体管M7的宽长比小于第一下拉控制晶体管M8的尺寸,从而可以由第一下拉控制晶体管M8主导对下拉控制端QB的电压的控制。
具体地,在输出子阶段t2,上拉控制端Q为高电平信号,第一下拉控制晶体管M8导通,并且控制信号输入晶体管M7和M10中的其控制极被施加有效电平的一个导通,在控制信号输入晶体管M7/M10和第一下拉控制晶体管M8的分压作用下,第一电源端VGL1提供的低电平信号被提供至下拉控制端QB,从而可以确保第一电平信号端VGL2与信号输出端OUT之间断开。
在下拉子阶段t3,通过复位电路150或160将上拉控制端Q电压下拉。进一步地,通过输入子电路提供至下拉控制端QB的有效的下拉控制时钟信号,使得输出电路130将低电平信号提供至诸如级联输出端CR和扫描信号输出端OUT的信号输出端。除此之外,由于第二下拉控制晶体管M9的栅极为有效的下拉控制时钟信号,因此,第二下拉控制晶体管M9导通,利用第一电源端VGL1提供的信号对上拉控制端Q进行进一步的拉低降噪。
为了防止在输出子阶段t2中下拉控电路140对上拉控制端Q进行不必要的放电,在一些实施例中,如图4和图5所示,下拉控制子电路143还包括第一防漏电晶体管M18,并且第二下拉控制晶体管M9的第二极连接至下拉控制防漏晶体管M18的第一极而不是第一电源端VGL1。下拉控制防漏电晶体管M18的控制极连接至下拉控制端QB,下拉控制防漏电晶体管的第二极连接至第一电源端VGL1。
当第二下拉控制晶体管M9的栅极为无效信号时,第二下拉控制晶体管M9以及第一防漏电晶体管M18均关断,确保第一电源端VGL1不会影响上拉控制端Q的电位。
在一些实施例中,参照图2和图3,第二复位电路150包括第二复位晶体管M6,该第二复位晶体管M6的控制极连接至第二复位控制端DRST,第一极连接至上拉控制端Q,第二极连接至第一电源端VGL1。
通过在下拉子阶段t3向第二复位晶体管M6的控制极提供有效的复位信号,可以使得第二复位晶体管M6导通,进而将第一电源端VGL1的信号提供至上拉控制端Q,以将上拉控制端Q电位拉低,使得输出电路130不会将无效信号提供至信号输出端。
为了防止在输出子阶段t2将上拉控制端Q电位拉低,在一些实施例中,参照图4和图5,第二复位子电路150还包括复位防漏电晶体管M17,并且第二复位晶体管M6的第二极连接至复位防漏电晶体管M17的第一极,复位防漏电晶体管M17的控制极连接至第二复位控制端DRST,第二极连接至第一电源端VGL1。
在本公开中,复位防漏电晶体管M17的控制极接收到复位控制信号时,该复位防漏电晶体管M17导通,并且第二复位晶体管M6导通,从而可以将第一电源端VGL1与上拉控制端Q导通。
在输出子阶段t2,第二复位晶体管M6的控制极以及复位防漏电晶体管M17的控制极接收到无效的复位信号,因此,第二复位晶体管M6和复位防漏电晶体管M17关断,确保上拉控制端Q不会被拉低。
在一些实施例中,如图2-5所示,第一复位电路160包括:第一复位晶体管M15,其控制极连接至第一复位控制端TRST,第一极连接至上拉控制端Q,第二极连接至第一电源端VGL1。
当第一复位晶体管M15的控制极接收到有效的控制信号时,该第一复位晶体管M15导通,进而将第一电源端VLG1与上拉控制端Q导通,将上拉控制端Q复位。
第一输入电路110可以用作检测信号输入电路,第二输入电路10可以用作显示信号输入电路,并且移位寄存器可以用于包括外部检测电路的显示面板中。第一输入电路110用于向上拉控制端Q提供检测触发信号,第二输入电路120用于向上拉控制端Q提供显示触发信号。通过本公开所提供的移位寄存器,可以实现检测扫描信号与显示扫描信号的叠加。
需要指出的是,此处的检测扫描信号是用于控制有机发光二极管显示面板的外部补偿电路对各个像素单元进行检测的信号。
第一输入电路110和第二输入电路120轮流(例如,在检测阶段T2的子阶段t1以及显示阶段T1的子阶段t1)向上拉控制端Q提供触发信号。
在一些实施例中,第一输入电路110包括检测控制子电路111、 检测输入子电路112和检测存储子电路113。
检测控制子电路111连接至级联输出端CR、检测触发端OE和检测控制节点H,并且配置为响应于级联输出端CR和检测触发端OE中的一者接收到有效电平,向检测控制节点H施加由级联输出端CR和检测触发端OE中的另一者提供的信号。
检测输入子电路112连接至检测控制节点H、第一输入端CLKE和上拉控制端Q,并且配置为响应于检测控制节点H的有效电平,向上拉控制端Q施加由第一输入端CLKE提供的信号。
检测存储子电路113连接至检测控制节点H和第一电源端VGL1,配置为存储检测控制节点H处的电压。
通过由检测控制子电路111控制检测控制节点H的电平,可以控制检测输入子电路112向上拉控制端提供信号的时机。
在一些实施例中,第一输入电路110还包括:检测复位子电路114,其连接至检测控制节点H、检测复位端CLKB和第一电源端VGL1,配置为响应于检测复位端CLKB的电压将第一电源信号提供给检测控制节点H。
在本公开所提供的实施方式中,在检测阶段T2的下拉子阶段t3向检测复位端CLKB提供有效信号。
通过检测复位子电路114,能够在检测阶段的下拉子阶段向检测控制节点H施加第一电源信号,从而使得检测控制节点H的放电更加充分。
如上文中所述,信号输出端输出的信号包括显示扫描信号和检测扫描信号。输入至第一输入电路110的信号为通过级联输出端CR输出的信号,其在波形上与由扫描信号输出端输出的包括显示扫描信号的信号相同。利用显示扫描信号控制第一输入电路110的输出,可以降低能耗、简化电路结构。
在一些实施例中,参照图6和图9,检测触发端OE在显示阶段T1中的某一时间段输入高电平的检测触发信号。根据本公开实施例,在由多个级联的移位寄存器组成的GOA电路中,当检测触发端OE输入高电平信号并且本级移位寄存器输出的显示扫描信号同时为高 时,在相应的检测阶段对本级移位寄存器进行检测和补偿操作,即,在多级移位寄存器中选择本级移位寄存器进行检测和补偿。这样,可以通过设置检测触发端OE输入的检测触发信号(例如,非逐行地扫描),来在逐行显示扫描的同时随机进行检测和补偿,从而避免逐行检测和补偿所带来的问题。
在一些实施例中,参照图2,检测控制子电路111包括检测控制晶体管M1。检测控制晶体管M1的控制极连接至检测触发端OE,检测控制晶体管的第一极连接至级联输出端CR,检测控制晶体管的第二极连接至检测控制节点H。
在一些实施例中,参照图3-5,检测控制子电路111包括检测控制晶体管M1。检测控制晶体管M1的控制极连接至级联输出端CR,检测控制晶体管的第一极连接至检测触发端OE,检测控制晶体管的第二极连接至检测控制节点H。
在一些实施例中,参照图2和图3,检测输入子电路112包括检测输入晶体管M3和开关晶体管M4。检测输入晶体管M3的控制极连接至检测控制节点H,检测输入晶体管M3的第一极连接至第一输入端CLKE,检测输入晶体管M3的第二极连接至开关晶体管M4的第一极。开关晶体管M4的控制极连接第一输入端CLKE,第二极连接至上拉控制端Q。
通过设置开关晶体管M4、并且使开关晶体管M4在输出显示扫描信号的时间段不导通,可以避免存储在检测存储子电路113中的信号对上拉控制端Q的电位造成影响。
由于检测输入子电路112连接至用于提供时钟信号的第一输入端CLKE而不是用于提供恒定高电平的信号端(例如,VDD),因此,在诸如晶体管M3的栅源电容的影响下,晶体管M3的第二极的电平可以更高,从而使得上拉控制端Q的电平更高,这可以提高移位寄存器工作的稳定性。
在一些实施例中,参照图4和图5,检测输入子电路112包括检测输入晶体管M3、开关晶体管M4和检测防漏电晶体管M4’。检测输入晶体管M3的控制极连接至检测控制节点H,检测输入晶体管 M3的第一极连接至第一输入端CLKE,检测输入晶体管M3的第二极连接至开关晶体管M4的第一极。开关晶体管M4的控制极连接至检测时钟端CLKC,第二极连接至检测防漏电晶体管M4’的第一极。检测防漏电晶体管M4’的控制极连接至检测时钟端CLKC,第二极连接至上拉控制端Q。在这种情况下,检测时钟端CLKC需要在检测阶段T2的充电子阶段t1提供有效电平。检测时钟端CLKC在其他时间的电平可参照图6和图9示出的那样。
在本公开中,在检测阶段T2的充电子阶段t1,检测控制节点H为高电平,开关晶体管M4的控制极通过检测时钟端CLKC或第一输入端CLKE被施加高电平。此时,检测输入晶体管M3和开关晶体管M4(以及,在图4-5的示例中,检测防漏电晶体管M4’)导通,从而可以将第一输入端CLKE提供的有效信号输出至上拉控制端Q。
可以同步地控制开关晶体管M4和检测防漏电晶体管M4’,当开关晶体管M4的控制极和检测防漏电晶体管M4’的控制极接收到有效的控制信号时,二者同时导通,从而允许检测输入子电路112将第一输入端CLKE的信号提供至上拉控制端Q。
当开关晶体管M4和检测防漏电晶体管M4’的控制端接收到无效的控制信号时,二者同时截止,从而避免对上拉控制端Q的电位造成影响。
在一些实施例中,检测复位子电路114包括检测复位晶体管M2,检测复位晶体管M2的控制极连接至检测复位端CLKB,第一极连接至检测控制节点H,第二极连接至第一电源端VGL1。
当检测复位晶体管M2的控制极接收到有效的复位信号时,检测复位晶体管M2导通,从而可以对检测控制节点H进行放电。
在一些实施例中,第二输入电路120包括第五晶体管M5,其控制端连接至显示触发端DTR,第一极连接至第三电源端VDD,第二极连接到上拉控制端Q。
在一些实施例中,当移位寄存器包括检测防漏电晶体管M4’、复位防漏电晶体管M17和下拉控制防漏晶体管M18中的至少一者时,为了防止在诸如检测防漏电晶体管M4’的第一极、复位防漏电 晶体管M17的第一极和/或下拉控制防漏晶体管M18的第一极(例如,图4和图5的中间防漏节点OFF)的节点处发生漏电,所述移位寄存器还包括中间防漏电晶体管M16,该中间防漏电晶体管M16的控制极与上拉控制端Q电连接,第一极与第三电源端VDD电连接,第二极与检测防漏电晶体管M4’的第一极、复位防漏电晶体管M17的第一极和/或下拉控制防漏晶体管M18的第一极(例如,图4和图5的中间防漏节点OFF)电连接。可替换地(图中未示出),中间防漏电晶体管M16的第一极可以连接至上拉控制端Q而不是第三电源端VDD。
在本公开中,对输出电路130的具体结构并不做特殊的限制,为了确保信号的稳定性,在一些实施例中,输出电路130包括级联输出子电路和至少一个扫描信号输出子电路,由不同的输出子电路分别提供两路具有相同波形的输出信号,从而避免其他信号对由扫描信号输出端OUT输出的扫描信号的影响。
在图2至图4所示的实施方式中,输出电路130包括一个级联输出子电路131和一个扫描信号输出子电路132。在图5所示的具体实施方式中,输出子电路130包括一个级联输出子电路131和两个扫描信号输出子电路132。
在一些实施例中,级联输出子电路131包括:级联输出上拉晶体管M11、级联输出下拉晶体管M12和上拉控制电容器C2。级联输出上拉晶体管M11的控制极连接至上拉控制端Q,第一极连接至输出时钟信号端CLKD,第二极连接至级联输出端CR。级联输出下拉晶体管M12的控制极连接至下拉控制端QB,第一极连接至第一电源端VGL1,第二极连接至级联输出端CR。上拉控制电容器C2的第一极连接至上拉控制端Q,第二极连接至级联输出端CR。
由于上拉控制电容器C2的自举效应,可以提高上拉控制点Q的电位。例如,参照图6,在输出子阶段t2,上拉控制点Q浮置,晶体管M11导通,由于上拉控制电容器C2的自举效应,上拉控制点Q的电位可被耦合至更高的电位。
在一些实施例中,每个扫描信号输出子电路132包括:扫描输 出上拉晶体管和扫描输出下拉晶体管。所述扫描输出上拉晶体管的控制极连接至上拉控制端Q,第一极连接至所述输出时钟信号端,第二极连接至所述扫描信号输出端。所述扫描输出下拉晶体管的控制极连接至下拉控制端QB,第一极连接至所述第二电源端VGL2,第二极连接至所述扫描信号输出端。
在一些实施例中,例如,参照图2-4,级联输出子电路131和扫描信号输出子电路132连接至单个输出时钟信号端CLKD。
在一些实施例中,例如,参照图5,存在多个输出时钟信号端(例如,图5所示的CLKD、CLKF、CLKG等),级联输出子电路131和多个扫描信号输出子电路132连接至不同的输出时钟信号端。
在图2至图4所示的实施例中,输出电路130具有一个扫描信号输出子电路132,扫描输出上拉晶体管M13的控制极连接至上拉控制端Q,第一极连接至输出时钟信号端,第二极连接至所述扫描信号输出端OUT。扫描输出下拉晶体管M14的控制极连接至下拉控制端QB,第一极连接至所述第二电源端VGL2,第二极连接至所述扫描信号输出端OUT。
在图5所示的实施例中,输出电路130具有两个扫描信号输出子电路132,并且具有两个扫描信号输出端OUT1和OUT2。扫描输出上拉晶体管M13的控制极连接至上拉控制端Q,第一极连接至输出时钟信号端CLKF,第二极连接至所述扫描信号输出端OUT1。扫描输出下拉晶体管M14的控制极连接至下拉控制端QB,第一极连接至所述第二电源端VGL2,第二极连接至所述扫描信号输出端OUT1。扫描输出上拉晶体管M19的控制极连接至上拉控制端Q,第一极连接至输出时钟信号端CLKG,第二极连接至所述扫描信号输出端OUT2。扫描输出下拉晶体管M20的控制极连接至下拉控制端QB,第一极连接至所述第二电源端VGL2,第二极连接至所述扫描信号输出端OUT2。
在本公开中,第二电源端VGL2提供的低电平信号的电平通常高于第一电源端VGL1提供的低电平信号的电平,以使得信号输出端输出的信号能够无损失。
在第二个方面,提供一种栅极驱动电路,所述栅极驱动电路包括级联的多级移位寄存器,其中,所述移位寄存器为本公开所提供的上述移位寄存器。
所谓“级联”是指,本级(例如,第N级)移位寄存器的输出端(例如,级联输出端)与往后数第二级(例如,第N+2级)移位寄存器的显示触发端(例如,上述实施例中的显示触发端DTR)电连接。根据本公开实施例,由移位寄存器的输出端输出的信号可以用于驱动与栅线相连的薄膜晶体管打开或关闭,并且可以用于驱动外部电路进行检测和补偿。
在一些实施例中,第4n+1级移位寄存器(例如,图7中的第1级移位寄存器A1)的级联输出端CR连接至第4n+3级移位寄存器(例如,图7中的第3级移位寄存器A3)的显示触发端DTR,第4n+1级移位寄存器的输出时钟信号端CLKD连接至用于提供第一输出时钟信号的第一输出时钟信号线CLKD_1,第4n+1级移位寄存器的第二复位控制端DRST连接至第4n+4级移位寄存器(例如,图7中的第4级移位寄存器A4)的级联输出端CR。
第4n+2级移位寄存器(例如,图7中的第2级移位寄存器A2)的级联输出端CR连接至第4n+4级移位寄存器(例如,图7中的第4级移位寄存器A4)的显示触发端DTR,第4n+2级移位寄存器的输出时钟信号端CLKD连接至用于提供第二输出时钟信号的第二输出时钟信号线CLKD_2,第4n+2级移位寄存器的第二复位控制端DRST连接至第4n+5级移位寄存器(例如,第5级移位寄存器,图中未示出)的级联输出端CR。
第4n+3级移位寄存器(例如,图7中的第3级移位寄存器A3)的级联输出端CR连接至第4n+5级移位寄存器(例如,第5级移位寄存器,图中未示出)的显示触发端,第4n+3级移位寄存器的输出时钟信号端CLKD连接至用于提供第三输出时钟信号的第三输出时钟信号线CLKD_3,第4n+3级移位寄存器的第二复位控制端DRST连接至第4n+6级移位寄存器(例如,第6级移位寄存器,图中未示出)的级联输出端CR。
第4n+4级移位寄存器(例如,图7中的第4级移位寄存器A4)的级联输出端CR连接至第4n+6级移位寄存器(例如,第6级移位寄存器,图中未示出)的显示触发端DTR,第4n+4级移位寄存器的输出时钟信号端连接至用于提供第四输出时钟信号的第四输出时钟信号线CLKD_4,第4n+4级移位寄存器的第二复位控制端DRST连接至第4n+7级移位寄存器(例如,第7级移位寄存器,图中未示出)的级联输出端CR。
其中,n为整数。
也就是说,对于第N级移位寄存器来说,其级联输出端为CR<N>,其显示触发端DTR连接至第N-2级移位寄存器的级联输出端CR<N-2>,其第二复位控制端DRST连接至第N+3级移位寄存器的级联输出端CR<N+2>。
在一些实施例中,参照图7和图9,奇数级移位寄存器的检测复位端CLKB连接至第一检测复位时钟线CKB,偶数级移位寄存器的检测复位端CLKB连接至第二检测复位时钟线CKC。此外,当移位寄存器是如图4和图5所示的移位寄存器时,奇数级移位寄存器的检测时钟端CLKC连接至第二检测复位时钟线CKC,偶数级移位寄存器的检测时钟端CLKC连接至第二检测复位时钟线CKB。
作为本公开的第三个方面,提供一种显示装置,所述显示装置包括栅极驱动电路,其中,所述栅极驱动电路为本公开所提供的上述栅极驱动电路。
所述显示面板包括多条数据线、多条栅线和多条检测线,多条栅线和多条数据线将所述显示面板划分为多个像素单元。如图8所示,每个像素单元都对应有像素电路和检测开关晶体管T3,每个像素单元都包括数据写入晶体管T2。在同一行像素单元中,数据写入晶体管T2的栅极以及检测开关晶体管T3的栅极均与相应的栅线(例如,在图8中所示的实施方式中,数据写入晶体管T1的栅极以及检测开关晶体管T3的栅极均与栅线GL1)电连接。当栅线接收到显示扫描信号时,数据写入晶体管T2导通,通过相应的数据线DL输入的数据可以写入像素电路中,驱动像素单元发光。当栅线接收到检测 扫描信号时,检测开关晶体管T3导通,从而可以通过检测信号线SL收集检测信号。
在本公开中,对像素电路的具体结构也没有特殊的限制。例如,在图8中所示的具体实施方式中,像素电路包括驱动晶体管T1、数据写入晶体管T2和有机发光二极管OLED。其中,数据写入晶体管T2的第一极与相应的数据线DL电连接,数据写入晶体管T2的第二极与驱动晶体管T1的栅极电连接。驱动晶体管T1的第一极与高电平信号端ELVDD电连接,驱动晶体管T2的第二极与有机发光二极管OLED的阳极电连接,有机发光二极管OLED的阴极接地。
检测开关晶体管T3的栅极与栅线GL1电连接,检测开关晶体管T3的第一极与有机发光二极管OLED的阳极电连接,检测开关晶体管T3的第二极与检测信号线SL电连接。
在第四个方面,提供一种移位寄存器的驱动方法,其中,所述移位寄存器为本公开所提供的上述移位寄存器。所述移位寄存器的工作周期分为在时间上不重叠的显示阶段T1和检测阶段T2,并且显示阶段和检测阶段中的每一个包括第一子阶段t1、第二子阶段t2和第三子阶段t3。
所述驱动方法包括:在显示阶段T1的第一子阶段t1,由第二输入电路120响应于显示触发端DTR的信号,向所述上拉控制端Q施加由所述第二输入端VDD提供的有效信号;在显示阶段T1的第二子阶段t2,由所述控制和输出电路响应于所述上拉控制端Q的信号将所述下拉控制端QB的电压确定为无效电压,并且响应于所述上拉控制端Q的信号而通过所述信号输出端OUT和CR输出所述输出时钟信号端CLKD提供的信号;在显示阶段T1的第三子阶段t3,由第二复位电路150响应于所述第二复位控制端DRST的信号,将所述第一电源端VGL1的无效信号提供给所述上拉控制端Q;在检测阶段T2的第一子阶段t1,由第一输入电路110响应于所述检测触发端OE和所述信号输出端CR的信号,向所述上拉控制端Q施加由所述第一输入端CLKE提供的有效信号;在检测阶段T2的第二子阶段t2,由所述控制和输出电路响应于所述上拉控制端Q的信号将所述下拉控 制端QB的电压确定为无效电压,并且响应于所述上拉控制端Q的信号而通过所述信号输出端OUT和CR输出所述输出时钟信号端CLKD提供的信号;在检测阶段T2的第三子阶段t3,由第一复位电路160响应于所述第一复位控制端TRST的信号,将所述第一电源端VGL1的无效信号提供给所述上拉控制端Q。
对包括上述移位寄存器的显示装置的驱动过程可参见图9,其中,所述显示装置包括栅极驱动电路,所述栅极驱动电路包括多个级联的上述移位寄存器,这些移位寄存器按照图7所示方式级联。所述驱动过程包括多个帧周期(在图9中仅示出了前两个帧周期,第一个帧周期1F和第二个帧周期2F),每个帧周期都包括显示阶段T1和检测阶段T2。
奇数级移位寄存器的检测复位端CLKB所连接的第一检测复位时钟线CKB和偶数级移位寄存器的检测复位端CLKB所连接的第二检测复位时钟线CKC上的信号互补,即,第一检测复位时钟线CKB在奇数帧周期内提供信号,在偶数帧周期内始终为低,第二检测复位时钟线CKC在偶数帧周期内提供信号,在奇数帧周期内始终为低。第一至第四输出时钟信号线CLKD_1、CLKD_2、CLKD_3、CLKD_4提供的信号依次延后一定时间,以使得多个移位寄存器在一帧周期中依次输出显示扫描信号,从而实现逐行显示扫描。
在不同的帧周期,分别控制不同级的移位寄存器的检测触发端的信号,以使得在预定个数的帧周期内,所有移位寄存器的检测输入电路均在检测阶段向所述上拉控制端输出过有效的信号。
需要解释的是,在本公开所提供的驱动方法中,当最后一级移位寄存器完成显示扫描信号的输出后,方进入检测阶段T2。
在每一个帧周期的显示阶段T1,向相应移位寄存器的显示输入电路110提供显示触发信号DTR,向该移位寄存器的输出时钟信号端CLKD提供第一时钟信号,在该移位寄存器的信号输出端输出显示扫描信号。
在每一个帧周期的检测阶段T2,向相应移位寄存器的第一输入端CLKE提供有效的第三时钟信号,然后,在该移位寄存器的信号 输出端输出检测扫描信号。
在不同的帧周期,分别向不同级的移位寄存器的第一时钟信号端CLKD提供有效的第一时钟信号,以使得在预定个数的帧周期内,所有移位寄存器均在检测阶段接收到过有效的第一时钟信号。
在本公开所提供的方法中,在显示阶段T1控制第一输入电路存储初始触发信号。但是,在显示阶段,第一输入端CLKE提供的均为无效信号,因此,第一输入电路的检测输入子电路与上拉控制端之间断开,从而可以确保在整个显示阶段T1,第一输入电路中存储的信号不会影响显示扫描信号的输出。
下面结合图2、图7和图9介绍本公开所提供的驱动方法。
如图9中所示,所述驱动方法的一个周期为显示装置的一帧,在图9中示出了第一个帧周期1F、第二个帧周期2F。在图7所示,栅极驱动电路包括两个移位寄存器组,奇数级的移位寄存器为一个移位寄存器组,偶数级的移位寄存器为一个移位寄存器组,相应地,对应于图7中的实施方式,所述栅极驱动电路包括四条第一时钟信号线,分别为向奇数级移位寄存器提供输出时钟信号的第一输出时钟信号线CLKD_1和第三输出时钟信号线CLKD_3、向偶数级移位寄存器提供输出时钟信号的第二输出时钟信号线CLKD_2、和第四输出时钟信号线CLKD_4。
在图9中,H<1>表示的是第一级移位寄存器的检测输入电路的检测控制节点的电位,H<2>表示的是第2级移位寄存器的检测输入电路的检测控制节点的电位。
所述驱动方法的每一个帧周期都包括显示阶段T1和检测阶段T2。
在第一个帧周期1F的显示阶段T1,在充电子阶段t1,向第一级移位寄存器的显示触发端以及第二级移位寄存器的显示触发端均输入有效的显示触发信号DTR(图7中为高电平信号)。
对于第一级移位寄存器A1而言,在显示阶段T1的工作可以包括充电子阶段t1、输出子阶段t2和下拉子阶段t3。
在充电子阶段t1,高电平信号端VDD提供的高电平信号被写入 上拉控制端Q,使得级联输出上拉晶体管M11和扫描输出上拉晶体管M13均导通。此时,输出时钟信号端CLKD接收到无效的时钟信号,因此可以通过输出端OUT<1>输出无效信号。由于控制信号输入晶体管M7导通,控制信号输入晶体管M7和第一下拉控制晶体管M8的分压作用使得下拉控制端QB为低电平,确保第二下拉控制晶体管M9截止,并且级联输出下拉晶体管M12、扫描输出下拉晶体管M14均截止。
在输出子阶段t2,显示触发信号DTR为低电平,因此,第五晶体管M5断开,使得上拉控制端Q浮置(floating),存储电容C2的自举作用将上拉控制端Q耦合至更高电位,从而维持级联输出上拉晶体管M11和扫描输出上拉晶体管M13导通。此时输出时钟信号端CLKD输入有效的时钟信号,从而可以确保在输出子阶段t2,信号输出端(包括级联输出端CR和扫描信号输出端OUT)输出有效的信号。在此子阶段,由于控制信号输入晶体管M7和第一下拉控制晶体管M8的分压作用,在下拉控制端QB为低电平信号,从而可以确保级联输出下拉晶体管M12和扫描输出下拉晶体管M14断开。并且,确保第二下拉控制晶体管M9断开,从而防止上拉控制端Q被拉低。
在下拉子阶段t3,第二复位晶体管M6的栅极接收到有效的复位信号,从而将第二复位晶体管M6导通,将上拉控制端Q电位拉低,并使得第一下拉控制晶体管M8和第二下拉控制晶体管M9均截止。通过控制信号输入晶体管M7输入的有效的信号使得级联输出下拉晶体管M12导通、扫描信号输出下拉晶体管M14导通,并将级联信号输出端、以及扫描信号输出端OUT<1>电位均下拉。
最后一级移位寄存器(例如,在图7的示例中,第四级移位寄存器A4)输出完毕后,进入检测阶段T2。如图9所示,通过时钟信号端CLKD向第一级移位寄存器A1提供有效的第一时钟信号,并且通过第一输入端CLKE向开关晶体管M4的栅极提供有效的时钟信号,使得开关晶体管M4导通,并且,第一存储子电路113(例如,图2所示的存储电容C1)中存储的信号使得检测输入晶体管M3导通,以将第一输入端CLKE提供的有效信号写入至上拉控制端Q,使 得级联输出上拉晶体管M11和扫描输出上拉晶体管M13导通,因此,信号输出端输出由输出时钟信号端CLKD提供的第一时钟信号。输出结束后,通过复位控制端TRST向第一复位晶体管M15的栅极提供有效复位信号,从而将第一复位晶体管M15导通,将上拉控制端Q电位拉低,并使得第一下拉控制晶体管M8截止,此时,下拉控制端QB电位为高,进一步维持上拉控制端Q的低电位。通过下拉控制端QB的高电位使得级联输出下拉晶体管M12导通、扫描输出下拉晶体管M14导通,并将级联信号输出端、以及扫描信号输出端OUT<1>电位均下拉。
在本公开中,可以通过调整了第一时钟信号的脉冲宽度以及输入信号的脉冲宽度来完成输出波形叠加的比例。
可以理解的是,以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式,然而本公开并不局限于此。对于本领域内的普通技术人员而言,在不脱离本公开的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本公开的保护范围。
Claims (26)
- 一种移位寄存器,包括:多个信号输入电路,其连接至多个信号输入端、多个输入控制端、以及上拉控制端;多个复位电路,其连接至多个复位控制端、第一电源端和所述上拉控制端;控制和输出电路,其连接至所述上拉控制端、下拉控制端、输出电源端、输出时钟信号端和输出信号端,并且配置为:根据所述上拉控制端处的电压确定所述下拉控制端的电压,响应于所述上拉控制端的电压而通过所述信号输出端输出所述输出时钟信号端提供的信号,并且响应于所述下拉控制端的电压而通过所述信号输出端输出所述输出电源端提供的信号,其中,所述移位寄存器的工作周期分为多个阶段,所述多个阶段在时间上不重叠,并且每个所述阶段至少包括第一子阶段和第二子阶段,所述多个信号输入电路各自配置为响应于所述多个输入控制端中的相应一个的信号,在所述多个阶段中的不同阶段的第一子阶段向所述上拉控制端施加由所述多个信号输入端中的相应一个提供的信号,所述多个复位电路各自配置为响应于所述多个复位控制端中的相应一个的信号,在所述多个阶段中的不同阶段的第二子阶段向所述上拉控制端施加由所述第一电源端提供的第一电源信号。
- 根据权利要求1所述的移位寄存器,其中,所述控制和输出电路包括:下拉控制电路,连接至所述上拉控制端、所述下拉控制端、所述第一电源端和下拉控制时钟端,并且配置为根据上拉控制端处的电压,将由第一电源端和下拉控制时钟端中的一者提供的信号施加至下拉控制端;以及输出电路,连接至所述信号输出端、所述输出电源端、所述输出时钟信号端、所述上拉控制端和所述下拉控制端,并且配置为响应于上拉控制端的电压,通过信号输出端输出输出时钟信号端提供的信号,并且响应于下拉控制端的电压,通过所述信号输出端输出所述输出电源端提供的信号。
- 根据权利要求2所述的移位寄存器,其中,所述移位寄存器的工作周期分为检测阶段和显示阶段,所述多个信号输入电路包括第一输入电路和第二输入电路,所述多个信号输入端包括第一输入端和第二输入端,所述信号输出端包括级联输出端和扫描信号输出端,所述第一输入电路连接至所述级联输出端、检测触发端、所述第一输入端和所述上拉控制端,并且配置为响应于所述级联输出端和所述检测触发端均接收到有效电平,在所述检测阶段的第一子阶段向所述上拉控制端施加由所述第一输入端提供的信号,所述第二输入电路连接至显示触发端、所述第二输入端和所述上拉控制端,并且配置为响应于所述显示触发端接收到有效电平,在所述显示阶段的第一子阶段向所述上拉控制端施加由所述第二输入端提供的信号。
- 根据权利要求3所述的移位寄存器,其中,所述多个复位电路包括第一复位电路和第二复位电路,所述多个复位控制端包括第一复位控制端和第二复位控制端,所述第一复位电路连接至所述第一复位控制端、所述第一电源端和所述上拉控制端,配置为响应于所述第一复位控制端的电压,在所述检测阶段的第二子阶段将所述第一电源信号提供给所述上拉控制端,所述第二复位电路连接至所述第二复位控制端、所述第一电源端和所述上拉控制端,配置为响应于所述第二复位控制端的电压,在所述显示阶段的第二子阶段将所述第一电源信号提供给所述上拉控制端。
- 根据权利要求4所述的移位寄存器,其中,所述第一输入电路包括:检测控制子电路,其连接至所述级联输出端、所述检测触发端和检测控制节点,并且配置为响应于所述级联输出端和所述检测触发端中的一者接收到有效电平,向所述检测控制节点施加由所述级联输出端和所述检测触发端中的另一者提供的信号;检测输入子电路,其连接至所述检测控制节点、所述第一输入端和所述上拉控制端,并且配置为响应于所述检测控制节点的有效电平,向所述上拉控制端施加由所述第一输入端提供的信号;以及检测存储子电路,其连接至所述检测控制节点和所述第一电源端,配置为存储所述检测控制节点处的电压。
- 根据权利要求5所述的移位寄存器,其中,所述第一输入电路还包括:检测复位子电路,其连接至所述检测控制节点、检测复位端和所述第一电源端,配置为响应于所述检测复位端的电压将所述第一电源信号提供给所述检测控制节点。
- 根据权利要求5或6所述的移位寄存器,其中,所述检测控制子电路包括检测控制晶体管,所述检测控制晶体管的控制极连接至所述检测触发端,所述检测控制晶体管的第一极连接至所述级联输出端,所述检测控制晶体管的第二极连接至所述检测控制节点。
- 根据权利要求5或6所述的移位寄存器,其中,所述检测控制子电路包括检测控制晶体管,所述检测控制晶体管的控制极连接至所述级联输出端,所述检测控制晶体管的第一极连接至所述检测触发端,所述检测控制晶体管的第二极连接至所述检测控制节点。
- 根据权利要求5至8中任一所述的移位寄存器,其中,所述 检测输入子电路包括:检测输入晶体管和开关晶体管,所述检测输入晶体管的控制极连接至所述检测控制节点,所述检测输入晶体管的第一极连接至所述第一输入端,所述检测输入晶体管的第二极连接至所述开关晶体管的第一极,并且所述开关晶体管的控制极连接所述第一输入端,第二极连接至所述上拉控制端。
- 根据权利要求5至8中任一所述的移位寄存器,其中,所述检测输入子电路包括:检测输入晶体管、开关晶体管和检测防漏电晶体管,所述检测输入晶体管的控制极连接至所述检测控制节点,所述检测输入晶体管的第一极连接至所述第一输入端,所述检测输入晶体管的第二极连接至所述开关晶体管的第一极,所述开关晶体管的控制极连接至检测时钟端,第二极连接至所述检测防漏电晶体管的第一极,并且所述检测防漏电晶体管的控制极连接至所述检测时钟端,所述第一极连接至中间防漏节点,第二极连接至所述上拉控制端。
- 根据权利要求6所述的移位寄存器,其中,所述检测复位子电路包括检测复位晶体管,所述检测复位晶体管的控制极连接至所述检测复位端,第一极连接至所述检测控制节点,第二极连接至所述第一电源端。
- 根据权利要求4-11中任一所述的移位寄存器,其中,所述下拉控制电路包括:至少一个下拉控制输入子电路,其连接至所述下拉控制时钟端和下拉控制端,配置为向所述上拉控制端施加由所述下拉控制时钟端提供的信号;以及控制子电路,其连接至所述上拉控制端、所述下拉控制端和所述第一电源端,并且配置为根据所述上拉控制端处的电压,将所述下 拉控制端的电压确定为由所述第一电源端和所述下拉控制时钟端中的一者提供的电压。
- 根据权利要求12所述的移位寄存器,其中,所述控制子电路包括第一下拉控制晶体管和第二下拉控制晶体管,所述第一下拉控制晶体管的控制极连接至所述上拉控制端,第一极连接至所述下拉控制端,第二极连接至所述第一电源端,所述第二下拉控制晶体管的控制极连接至所述下拉控制端,第一极连接至所述上拉控制端,第二极连接至所述第一电源端。
- 根据权利要求12所述的移位寄存器,其中,所述控制子电路包括第一下拉控制晶体管、第二下拉控制晶体管和下拉控制防漏电晶体管,所述第一下拉控制晶体管的控制极连接至所述上拉控制端,第一极连接至所述下拉控制端,第二极连接至所述第一电源端,所述第二下拉控制晶体管的控制极连接至所述下拉控制端,第一极连接至所述上拉控制端,第二极连接至所述下拉控制防漏电晶体管的第一极,所述下拉控制防漏电晶体管的控制极连接至所述下拉控制端,所述下拉控制防漏电晶体管的第二极连接至所述第一电源端。
- 根据权利要求12-14中任一所述的移位寄存器,其中,所述下拉控制时钟端包括多个下拉控制时钟端,通过所述多个下拉控制时钟端在不同的时段提供有效信号,所述下拉控制电路包括多个所述下拉控制输入子电路,每个所述下拉控制输入子电路连接至所述多个下拉控制时钟端之一和所述下拉控制端,配置为响应于该下拉控制时钟端接收到有效信号,向所述下拉控制端施加由该下拉控制时钟端提供的信号。
- 根据权利要求15所述的移位寄存器,其中,每个所述下拉 控制输入子电路包括下拉控制输入晶体管,所述下拉控制输入晶体管的控制极和第一极连接至所述多个下拉控制时钟端之一,第二极连接至所述下拉控制端。
- 根据权利要求4-16中任一所述的移位寄存器,其中,所述输出电源端包括第二电源端和所述第一电源端,所述输出电路包括:级联输出子电路,其连接至所述级联输出端、所述输出时钟信号端、所述上拉控制端、所述下拉控制端和所述第一电源端,并且配置为响应于所述上拉控制端的电压,通过所述级联输出端输出所述输出时钟信号端提供的信号,并且响应于所述下拉控制端的电压,通过所述级联输出端输出所述第一电源端提供的信号,和至少一个扫描信号输出子电路,其连接至所述扫描信号输出端、所述输出时钟信号端、所述上拉控制端、所述下拉控制端和所述第二电源端,并且配置为响应于所述上拉控制端的电压,通过所述扫描信号输出端输出所述输出时钟信号端提供的信号,并且响应于所述下拉控制端的电压,通过所述扫描信号输出端输出所述第二电源端提供的信号。
- 根据权利要求17所述的移位寄存器,其中,所述级联输出子电路包括:级联输出上拉晶体管、级联输出下拉晶体管和上拉控制电容器,所述级联输出上拉晶体管的控制极连接至上拉控制端,第一极连接至所述输出时钟信号端,第二极连接至所述级联输出端,所述级联输出下拉晶体管的控制极连接至下拉控制端,第一极连接至所述第一电源端,第二极连接至所述级联输出端,所述上拉控制电容器的第一极连接至所述上拉控制端,第二极连接至所述级联输出端。
- 根据权利要求17或18所述的移位寄存器,其中,所述扫 描信号输出子电路包括:扫描输出上拉晶体管和扫描输出下拉晶体管,所述扫描输出上拉晶体管的控制极连接至上拉控制端,第一极连接至所述输出时钟信号端,第二极连接至所述扫描信号输出端,所述扫描输出下拉晶体管的控制极连接至下拉控制端,第一极连接至所述第二电源端,第二极连接至所述扫描信号输出端。
- 根据权利要求4所述的移位寄存器,其中,所述第一复位电路包括:第一复位晶体管,其控制极连接至第一复位控制端,第一极连接至上拉控制端,第二极连接至第一电源端,所述第二复位电路包括:第二复位晶体管,其控制极连接至第二复位控制端,第一极连接至上拉控制端,第二极连接至第一电源端。
- 根据权利要求4所述的移位寄存器,其中,所述第一复位电路包括:第一复位晶体管,其控制极连接至第一复位控制端,第一极连接至上拉控制端,第二极连接至第一电源端,所述第二复位电路包括:第二复位晶体管和复位防漏电晶体管,所述第二复位晶体管的控制极连接至第二复位控制端,第一极连接至上拉控制端,第二极连接至所述复位防漏电晶体管的第一极,所述复位防漏电晶体管的控制极连接至所述第二复位控制端,第一极连接至中间防漏节点,第二极连接至第一电源端。
- 根据权利要求10或21所述的移位寄存器,还包括:中间防漏电晶体管,所述中间防漏电晶体管的控制极连接至所述上拉控制端,第一极与第三电源端或所述上拉控制端电连接,第二极连接至所述中间防漏节点。
- 一种栅极驱动电路,所述栅极驱动电路包括级联的多级移位寄存器,所述移位寄存器为权利要求1至22中任意一项所述的移位寄存器。
- 一种栅极驱动电路,所述栅极驱动电路包括级联的多级移位寄存器,所述移位寄存器为权利要求4至21中任意一项所述的移位寄存器,其中,在所述多级移位寄存器中,第4n+1级移位寄存器的级联输出端连接至第4n+3级移位寄存器的显示触发端,第4n+1级移位寄存器的输出时钟信号端连接至用于提供第一输出时钟信号的第一输出时钟信号线,第4n+1级移位寄存器的第二复位控制端连接至第4n+4级移位寄存器的级联输出端,第4n+2级移位寄存器的级联输出端连接至第4n+4级移位寄存器的显示触发端,第4n+2级移位寄存器的输出时钟信号端连接至用于提供第二输出时钟信号的第二输出时钟信号线,第4n+2级移位寄存器的第二复位控制端连接至第4n+5级移位寄存器的级联输出端,第4n+3级移位寄存器的级联输出端连接至第4n+5级移位寄存器的显示触发端,第4n+3级移位寄存器的输出时钟信号端连接至用于提供第三输出时钟信号的第三输出时钟信号线,第4n+3级移位寄存器的第二复位控制端连接至第4n+6级移位寄存器的级联输出端,第4n+4级移位寄存器的级联输出端连接至第4n+6级移位寄存器的显示触发端,第4n+4级移位寄存器的输出时钟信号端连接至用于提供第四输出时钟信号的第四输出时钟信号线,第4n+4级移位寄存器的第二复位控制端连接至第4n+7级移位寄存器的级联输出端。
- 一种显示装置,所述显示装置包括栅极驱动电路,所述栅极驱动电路为权利要求23或24所述的栅极驱动电路。
- 一种移位寄存器的驱动方法,所述移位寄存器包括:第一输入电路,连接至信号输出端、检测触发端、第一输入端和上拉控制端,第二输入电路,连接至显示触发端、第二输入端和所述上 拉控制端,第一复位电路和第二复位电路,第一复位电路连接至第一复位控制端、第一电源端和所述上拉控制端,第二复位电路连接至第二复位控制端、所述第一电源端和所述上拉控制端,控制和输出电路,其连接至所述上拉控制端、下拉控制端、输出电源端、输出时钟信号端和信号输出端,其中,所述移位寄存器的工作周期分为在时间上不重叠的显示阶段和检测阶段,并且显示阶段和检测阶段中的每一个包括第一子阶段、第二子阶段和第三子阶段,所述驱动方法包括:在显示阶段的第一子阶段,由第二输入电路响应于所述显示触发端的信号,向所述上拉控制端施加由所述第二输入端提供的有效信号;在显示阶段的第二子阶段,由所述控制和输出电路响应于所述上拉控制端的信号将所述下拉控制端的电压确定为无效电压,并且响应于所述上拉控制端的信号而通过所述信号输出端输出所述输出时钟信号端提供的信号;在显示阶段的第三子阶段,由第二复位电路响应于所述第二复位控制端的信号,将所述第一电源端的无效信号提供给所述上拉控制端;在检测阶段的第一子阶段,由第一输入电路响应于所述检测触发端和所述信号输出端的信号,向所述上拉控制端施加由所述第一输入端提供的有效信号;在检测阶段的第二子阶段,由所述控制和输出电路响应于所述上拉控制端的信号将所述下拉控制端的电压确定为无效电压,并且响应于所述上拉控制端的信号而通过所述信号输出端输出所述输出时钟信号端提供的信号;在检测阶段的第三子阶段,由第一复位电路响应于所述第一复位控制端的信号,将所述第一电源端的无效信号提供给所述上拉控制端。
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