WO2020103537A1 - 阵列基板、显示面板及显示装置 - Google Patents
阵列基板、显示面板及显示装置Info
- Publication number
- WO2020103537A1 WO2020103537A1 PCT/CN2019/104969 CN2019104969W WO2020103537A1 WO 2020103537 A1 WO2020103537 A1 WO 2020103537A1 CN 2019104969 W CN2019104969 W CN 2019104969W WO 2020103537 A1 WO2020103537 A1 WO 2020103537A1
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- WIPO (PCT)
- Prior art keywords
- circuit
- sub
- multiplexer
- transistor
- stage
- Prior art date
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/04—Display protection
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
Definitions
- the present disclosure relates to the field of display technology, and in particular, to an array substrate, a display panel, and a display device.
- a test circuit is provided in the non-display area of the array substrate.
- the test of the display panel mainly provides the first data signal to the odd-numbered data lines in the display panel, and provides the second to the even-numbered data lines of the display panel.
- this test circuit can only make the display panel display a simple stripe pattern, resulting in Existing problems for comprehensive testing.
- the array substrate is divided into a display area and a peripheral non-display area, wherein the array substrate includes:
- test circuit the test circuit is located in the non-display area
- the test circuit includes: at least one sub-circuit
- the sub-circuit includes at least one multiplexer; the multiplexer includes an input terminal and multiple output terminals, the multiplexer is configured to control the input terminal under the control of multiple control lines The signal is provided to the corresponding output terminal; in addition to the sub-circuits of the first stage, the input terminals of the multiplexers in each of the sub-circuits and the multi-paths of the sub-circuits of the previous stage The corresponding output terminal in the selector is connected;
- the output of the multiplexer in each of the sub-circuits is connected to the corresponding input in the multiplexer in the sub-circuit of the next stage;
- the input terminal of the multiplexer in the sub-circuit at the first stage is connected to a test terminal that provides a test signal
- the output terminal of the multiplexer in the sub-circuit at the last stage and the display area Is connected to the signal line of each, and the control lines connected to the sub-circuits at all levels are connected to control terminals that provide control signals.
- the number of the multiplexers in the sub-circuit in the next stage is the same as the number of output terminals of the multiplexers in the sub-circuit in the previous stage .
- the test circuit includes: one stage of the sub-circuit;
- the subcircuit includes a multiplexer, the input terminal of the multiplexer in the subcircuit is connected to the test terminal, and the output terminal of the multiplexer in the subcircuit is connected to all The signal lines of the display area are connected.
- the test circuit includes two stages of the sub-circuits
- the sub-circuit at the first stage includes a multiplexer, and the input terminal of the multiplexer in the sub-circuit at the first stage is connected to the test terminal;
- the second stage of the sub-circuit includes a plurality of multiplexers, the input of each of the multiplexers in the second stage of the subcircuit and the multiplexer in the first stage of the subcircuit
- the output terminals of the selector are connected in a one-to-one correspondence, and the output terminal of the multiplexer in the sub-circuit of the second pole is connected to the signal line of the display area.
- the test circuit includes: three levels of the sub-circuits;
- the sub-circuit at the first stage includes a multiplexer, and the input terminal of the multiplexer in the sub-circuit at the first stage is connected to the test terminal;
- the second stage of the sub-circuit includes a plurality of multiplexers, the input of each of the multiplexers in the second stage of the subcircuit and the multiplexer in the first stage of the subcircuit
- the output terminals of the selector are connected one by one;
- the sub-circuit in the third stage includes a plurality of multiplexers, the input terminals of the multiplexers in the sub-circuit in the third stage and the multiplexers in the sub-circuit in the second stage
- the output terminals of the selector are connected in a one-to-one correspondence, and the output terminal of the multiplexer of the sub-circuit of the third stage is connected to the signal line of the display area.
- the array substrate includes multiple test circuits
- Each of the test circuits shares the control line.
- the multiplexer includes: a plurality of first transistors
- each of the first transistors is connected to the corresponding control line
- the first pole of each of the first transistors is connected to the multiplexed input terminal
- the second pole of each of the first transistors They are respectively connected to the output terminals corresponding to the multiplexer.
- the first transistor is a double-gate transistor.
- a first electrostatic discharge circuit is provided between two adjacent control lines;
- the input end of the first electrostatic discharge circuit is connected to one control line, and the output end of the first electrostatic discharge circuit is connected to another adjacent control line.
- the first electrostatic discharge circuit includes: a second transistor and a third transistor;
- the gate of the second transistor, the first electrode of the second transistor, and the second electrode of the third transistor are all connected to one control line;
- the second electrode of the second transistor, the gate of the third transistor, and the first electrode of the third transistor are all connected to another control line.
- the output end of the sub-circuit is provided with a second electrostatic discharge circuit
- the input terminal of the second electrostatic discharge circuit is connected to the output terminal of the multiplexer in the sub-circuit, and the output terminal of the second electrostatic discharge circuit is connected to the discharge line.
- the second electrostatic discharge circuit includes at least one discharge sub-circuit, and each of the electronic discharge circuits is arranged in series or in parallel.
- each of the electronic discharge circuits includes: a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;
- the gate of the fourth transistor and the first electrode of the fourth transistor are both connected to the output of the multiplexer in the sub-circuit, and the second electrode of the fourth transistor is connected to the discharge line Connected
- the gate of the fifth transistor and the first electrode of the fifth transistor are both connected to the output of the multiplexer in the sub-circuit, and the second electrode of the fifth transistor is connected to the discharge line Connected
- the gate of the sixth transistor and the first electrode of the sixth transistor are both connected to the discharge line, and the second electrode of the sixth transistor is connected to the output of the multiplexer in the sub-circuit Connected
- the gate of the seventh transistor and the first pole of the seventh transistor are both connected to the discharge line, the second pole of the seventh transistor and the output of the multiplexer in the sub-circuit Connected.
- an embodiment of the present disclosure also provides a display panel, including any of the above array substrates provided by the embodiments of the present disclosure;
- the output terminal of the multiplexer in the last-stage sub-circuit in each test circuit in the array substrate is connected to the corresponding signal line in the display panel.
- an embodiment of the present disclosure also provides a display device, including the above-mentioned display panel provided by the embodiment of the present disclosure.
- FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure
- FIG. 2 is a schematic structural diagram of a test circuit provided by an embodiment of the present disclosure
- FIG. 3 is a schematic diagram of a specific structure of a test circuit provided by an embodiment of the present disclosure.
- FIG. 4 is a schematic structural diagram of another test circuit provided by an embodiment of the present disclosure.
- FIG. 5 is a schematic diagram of a specific structure of another test circuit provided by an embodiment of the present disclosure.
- FIG. 6 is a schematic structural diagram of another test circuit provided by an embodiment of the present disclosure.
- FIG. 7 is a specific structural schematic diagram of a first electrostatic discharge circuit provided by an embodiment of the present disclosure.
- FIG. 8 is a specific structural schematic diagram of a first electrostatic discharge circuit provided by an embodiment of the present disclosure.
- FIG. 9 is a specific structural schematic diagram of another first electrostatic discharge circuit provided by an embodiment of the present disclosure.
- FIG. 10 is a schematic diagram of a specific structure of another first electrostatic discharge circuit provided by an embodiment of the present disclosure.
- An embodiment of the present disclosure provides an array substrate. As shown in FIGS. 1 and 2, the array substrate is divided into a display area A-A and a peripheral non-display area B-B.
- the above-mentioned array substrate includes:
- Test circuit 10 which is located in the non-display area B-B;
- the test circuit 10 includes: at least one-stage sub-circuit (where FIG. 2 is illustrated by taking the test circuit including two-stage sub-circuit as an example);
- the sub-circuit includes at least one multiplexer DEM; the multiplexer DEM includes an input terminal Q and multiple output terminals O.
- the multiplexer DEM is configured to control the input terminal Q under the control of multiple control lines Con The signal is provided to the corresponding output terminal O;
- the input terminal Q of the multiplexer DEM in each sub-circuit is connected to the corresponding output terminal O in the multiplexer DEM in the previous-stage sub-circuit 11;
- the output of the multiplexer DEM in each sub-circuit is connected to the corresponding input Q in the multiplexer DEM in the next-stage sub-circuit;
- the input terminal Q of the multiplexer DEM in the first-stage sub-circuit 11 is connected to the test terminal p1 that provides a test signal, and the output end of the multiplexer DEM in the last-stage sub-circuit 21 is connected to the signal line da of the display area
- the control lines Con connected to the sub-circuits at all levels are connected to the control terminal p2 that provides the control signal.
- the array substrate provided by the present disclosure includes: at least one stage of sub-circuits, the sub-circuits include at least one multiplexer; the multiplexer includes one input terminal and multiple output terminals, and the multiplexer is configured In order to provide the signal of the input terminal to the corresponding output terminal under the control of multiple control lines; among them, the input terminal of the multiplexer in each sub-circuit and the The corresponding output terminals in the multiplexer are connected; except for the last stage of the subcircuit, the output of the multiplexer in each subcircuit is connected to the corresponding input of the multiplexer in the next stage of the subcircuit; The input of the multiplexer in the first-level sub-circuit is connected to the test terminal that provides the test signal.
- the output of the multiplexer in the last-level sub-circuit is connected to the signal line in the display area.
- the control lines are connected to control terminals that provide control signals.
- the number of multiplexers DEM in the sub-circuit 21 of the next stage is the same as the number of output terminals O of the multiplexers DEM in the sub-circuit 11 of the previous stage . Therefore, the number of signal lines to which the test circuit can be connected is the largest.
- the test circuit includes: a primary sub-circuit
- the subcircuit includes a multiplexer DEM, the input terminal Q of the multiplexer DEM in the subcircuit is connected to the test terminal p1, and the output terminal O of the multiplexer DEM in the subcircuit is connected to the signal line da of the display area .
- FIG. 3 is only schematically illustrated by taking the example that the multiplexer of the sub-circuit has 6 output terminals, where the number of output terminals of the multiplexer is set according to the number of signal lines to be measured It is not limited to the structure shown in FIG. 3, and the number of output terminals of the multiplexer is not specifically limited here.
- the test circuit includes: a two-stage sub-circuit, namely a first-stage sub-circuit 11 and a second-stage sub-circuit 21;
- the first-stage sub-circuit 11 includes a multiplexer DEM, and the input terminal Q of the multiplexer DEM in the first-stage sub-circuit 11 is connected to the test terminal p1;
- the second-stage sub-circuit 21 includes multiple multiplexers DEM, the input Q of each multiplexer DEM in the second-stage sub-circuit 21 and the output of the multiplexer DEM in the first-stage sub-circuit 11 O is connected in a one-to-one correspondence, and the output terminal O of the multiplexer DEM in the second pole circuit 21 is connected to the signal line da of the display area.
- FIG. 4 only shows the structure of one multiplexer in the second-stage subcircuit, but the second-stage subcircuit includes 6 multiplexers. Of course, there are many in the second-stage subcircuit.
- the number of multiplexers is not limited to six, and it needs to be set corresponding to the output of the first-level subcircuit, that is, to ensure that the number of multiplexers in the second-level subcircuit and the multiplexers in the first-level subcircuit The number of outputs is the same.
- the test circuit includes: a three-level sub-circuit, that is, a first-level sub-circuit 11, a second-level sub-circuit 21, and a third-level sub-circuit 31;
- the first-stage sub-circuit 11 includes a multiplexer DEM, and the input terminal Q of the multiplexer DEM in the first-stage sub-circuit 11 is connected to the test terminal p1;
- the second-stage sub-circuit 21 includes a plurality of multiplexers DEM, the input Q of each multiplexer 21 in the second-stage sub-circuit 21 and the output of the multiplexer DEM in the first-stage sub-circuit 11 O one-to-one corresponding connection;
- the third-stage sub-circuit 31 includes a plurality of multiplexers DEM, the input Q of each multiplexer DEM in the third-stage sub-circuit 31 and the output of the multiplexer DEM in the second-stage sub-circuit 21 O is connected in a one-to-one correspondence, and the output terminal O of the multiplexer DEM of the third-stage sub-circuit 31 is connected to the signal line da of the display area.
- the multiplexer in the first-stage subcircuit has 6 output terminals, and each multiplexer in the second-stage subcircuit has 3 output terminals, and the third-stage subcircuit
- the multiplexer has three output terminals as an example for description, but it is not limited to this, and may be other ratios, which are set according to the number of signal lines to be tested.
- each sub-circuit in FIG. 5 shows only one multiplexer, and other multiplexers are not shown one by one.
- test circuit structure shown in FIG. 2 is specifically described, where FIG. 2 is that the multiplexer DEM in the first-stage sub-circuit 11 has 6 selection paths, Each multiplexer DEM in the second-stage sub-circuit 21 has 9 selection paths as an example for description.
- the first-level sub-circuit 11 has 6 selection paths, that is, the first-level sub-circuit 11 has 1 input terminal Q, 6 control lines Con, and 6 output terminals O;
- the second-level sub-circuit 21 has The output terminal O of the sub-circuit 11 has the same number of multiplexers DEM, that is, the second-stage sub-circuit 21 has 6 multiplexers DEM, and each multiplexer DEM has 1 input (first-stage The output of the circuit), 9 control lines and 9 outputs; so that the second stage sub-circuit 21 has 54 output ends, that is, the input of the test signal through one input end of the first-stage sub-circuit 11 can be Provide test signals to 54 signal lines in the display area.
- the display panel has 1080 data lines, and 20 groups of structures as shown in FIG. 1 can be set to control the 1080 data lines in the display panel. If there are more data lines, more groups of the above structures can be set and displayed on the display.
- the panel is bound by regions (wherein, the test circuit binds to each signal line in the display panel through the provided multiple contact terminals pad).
- how many sub-circuits the test circuit has, and the number of output terminals of the multiplexer in each sub-circuit can be set according to the requirements of the specific implementation, and is not limited to the structure in the drawings. There is no specific limitation here.
- the array substrate includes multiple test circuits
- Each test circuit shares a control line.
- a plurality of test circuits in the above embodiments may be provided in the non-display area of the array substrate, where each test circuit is connected
- the control lines can be shared, thereby reducing wiring.
- the multiplexer includes: a plurality of first transistors T1;
- the gates of the first transistors T1 are respectively connected to the corresponding control lines Con, the first poles of the first transistors T1 are connected to the multiplexed input terminal Q, and the second poles of the first transistors T1 are respectively connected to the multiplexed selection
- the corresponding output O of the device is connected.
- each level of sub-circuit in addition to the first-level sub-circuit, the multiplexer DEM in each level of sub-circuit is only a part of each level of sub-circuit, and each level of sub-circuit also includes Multiple multiplexers DEM corresponding to the output of the multiplexer in the sub-circuit of the previous stage (other multiplexers are not specifically shown in the figure).
- each first transistor is controlled by a control line, and a control signal is provided to the gate of the first transistor according to the test pattern to be displayed on the display panel to control the Turn on or off; the first electrode of each first transistor in each level of sub-circuit is connected to the same input terminal, that is, it receives the test signal provided by the same test signal line.
- the timing of the test signal provided by the test signal line is designed to provide different signals to the corresponding signal line, which is convenient for displaying complex test patterns; except for the second pole of the first transistor in the last sub-circuit and the corresponding area in the display area
- the second poles of the first transistors in the sub-circuits at other levels are connected to the corresponding input terminals of the sub-circuits at the next level.
- the first transistor is a double-gate transistor.
- setting the first transistor as a double-gate transistor can reduce the leakage current of the first transistor, reduce energy consumption, and also improve the stability of signal transmission.
- a first electrostatic discharge circuit 3 is provided between two adjacent control lines Con;
- the input terminal of the first electrostatic discharge circuit 3 is connected to one control line Con, and the output terminal of the first electrostatic discharge circuit 3 is connected to another adjacent control line Con.
- the static electricity existing on each control line can be evacuated to prevent the accumulation of static electricity from affecting the signals on each control line.
- Any structure capable of achieving electrostatic transmission is within the protection scope of the present disclosure, and is not specifically limited herein.
- the first electrostatic discharge circuit includes: a second transistor T2 and a third transistor T3;
- the gate of the second transistor T2, the first electrode of the second transistor T2 and the second electrode of the third transistor T3 are all connected to a control line Con;
- the second electrode of the second transistor T2, the gate of the third transistor T3, and the first electrode of the third transistor T3 are all connected to another control line Con.
- the second transistor when static electricity is generated on one control line, the voltage of the gate and the first electrode of the second transistor rises, the second transistor is turned on, and the accumulated static electricity Transfer to another control line to achieve static electricity evacuation; when static electricity accumulates on the other control line, the voltage of the gate and first electrode of the third transistor rises, and the third transistor is turned on to transfer the accumulated static electricity To the adjacent control line, to achieve electrostatic evacuation.
- the output end O of the sub-circuit is provided with a second electrostatic discharge circuit 4;
- the input terminal of the second electrostatic discharge circuit 4 is connected to the output terminal O of the multiplexer in the sub-circuit, and the output terminal of the second electrostatic discharge circuit is connected to the discharge line Com.
- the second static electricity discharge circuit when static electricity is generated at the output end of each sub-circuit, supplies the static electricity at the output end to the discharge line, thereby realizing static electricity discharge.
- the second electrostatic discharge circuit includes at least one electronic discharge circuit, and each electronic discharge circuit is arranged in series or in parallel.
- each electronic discharge circuit includes: a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7;
- the gate of the fourth transistor T4 and the first electrode of the fourth transistor T4 are both connected to the output terminal O1 of the multiplexer in the sub-circuit, and the second electrode of the fourth transistor T4 is connected to the discharge line Com;
- the gate of the fifth transistor T5 and the first electrode of the fifth transistor T5 are both connected to the output terminal O1 of the multiplexer in the sub-circuit, and the second electrode of the fifth transistor is connected to the discharge line Com;
- the gate of the sixth transistor T6 and the first electrode of the sixth transistor T6 are both connected to the discharge line Com, and the second electrode of the sixth transistor T6 is connected to the output terminal O1 of the multiplexer in the sub-circuit;
- the gate of the seventh transistor T7 and the first electrode of the seventh transistor T7 are both connected to the discharge line Com, and the second electrode of the seventh transistor T7 is connected to the output terminal O1 of the multiplexer in the sub-circuit.
- each transistor in the second electrostatic discharge circuit is a polysilicon transistor
- two electronic discharge circuits need to be provided, the input terminals of the two electronic discharge circuits are connected to the output terminal of the sub-circuit, and one electronic discharge circuit Is connected to one discharge line, and the output end of the other electronic discharge circuit is connected to another discharge line.
- the potentials of the two discharge lines are opposite; when each transistor in the second electrostatic discharge circuit is a monocrystalline silicon transistor, only An electronic discharge circuit needs to be provided.
- the input end of the electronic discharge circuit is connected to the output end of the corresponding sub-circuit.
- the output end of the electronic discharge circuit is connected to the discharge line.
- the discharge line is generally connected to a low voltage or ground.
- the structure of the electronic discharge circuit is not limited to the structure shown in FIG. 8, but may also be as shown in FIG. 9 (multiple structures shown in FIG. 8 in series) and FIG. 10 (multiple structures shown in FIG. 8 in parallel)
- the discharge structure of the structure may of course be any other structure capable of realizing the discharge function, which is not specifically limited herein.
- the transistor mentioned in the above embodiments of the present disclosure may be a thin film transistor (TFT, Thin Film Transistor) or a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Semiconductor), which is not limited herein.
- TFT Thin Film Transistor
- MOS Metal Oxide Semiconductor
- the control electrode of each of the above transistors serves as its gate, and depending on the type of transistor and the input signal, the first electrode can be used as the source and the second electrode as the drain; or the first electrode can be used as the drain , The second pole serves as the source, and no specific distinction is made here.
- an embodiment of the present disclosure also provides a display panel including any array substrate provided in the above embodiments;
- the output terminal of the multiplexer in the last sub-circuit of each test circuit in each array substrate is connected to the corresponding signal line in the display panel.
- the implementation mode and principle of the display panel are the same as the implementation mode and principle of the array substrate in the above embodiments. Therefore, the specific implementation of the display panel can be referred to the specific implementation mode of the array substrate in the above embodiments. No longer.
- an embodiment of the present disclosure also provides a display device including the display panel provided by the above embodiment.
- the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
- a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
- a display device reference may be made to the foregoing embodiment of the gate driving circuit, and the repetition is not repeated.
- the array substrate includes: at least one stage of sub-circuits, the sub-circuits include at least one multiplexer; the multiplexer includes an input terminal and multiple outputs End, the multiplexer is configured to provide the signal of the input end to the corresponding output end under the control of multiple control lines; where, in addition to the first-stage subcircuit, the input end of the multiplexer in each subcircuit Connected to the corresponding output of the multiplexer in the sub-circuit of the previous stage; in addition to the final sub-circuit, the output of the multiplexer in each sub-circuit and the multiplexer in the sub-circuit of the next stage
- the corresponding input terminal in the first stage is connected; the input terminal of the multiplexer in the first-stage subcircuit is connected to the test terminal that provides the test signal, and the output terminal of the multiplexer in the last-stage subcircuit is connected to the signal line of the display area
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Abstract
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Claims (15)
- 一种阵列基板,所述阵列基板分为显示区域和周边的非显示区域,其中,所述阵列基板,包括:测试电路,所述测试电路位于所述非显示区域;所述测试电路,包括:至少一级子电路;所述子电路包括至少一个多路选择器;所述多路选择器包括一个输入端和多个输出端,所述多路选择器被配置为在多条控制线的控制下将所述输入端的信号提供给对应的所述输出端;除第一级所述子电路外,各所述子电路中的所述多路选择器的输入端与上一级所述子电路中的所述多路选择器中对应的输出端相连;除最后一级所述子电路外,各所述子电路中所述多路选择器的输出端与下一级所述子电路中的所述多路选择器中对应的输入端相连;第一级所述子电路中的所述多路选择器的输入端与提供测试信号的测试端子相连,最后一级所述子电路中的所述多路选择器的输出端与所述显示区域的信号线相连,各级所述子电路连接的所述控制线均与提供控制信号的控制端子相连。
- 如权利要求1所述的阵列基板,其中,下一级所述子电路中所述多路选择器的个数与上一级所述子电路中的所述多路选择器的输出端的个数相同。
- 如权利要求1所述的阵列基板,其中,所述测试电路包括一级所述子电路;所述子电路包括一个多路选择器,所述子电路中的所述多路选择器的输入端与所述测试端子相连,所述子电路中的所述多路选择器的输出端与所述显示区域的所述信号线相连。
- 如权利要求1所述的阵列基板,其中,所述测试电路包括两级所述子电路;第一级所述子电路包括一个多路选择器,第一级所述子电路中的所述多 路选择器的输入端与所述测试端子相连;第二级所述子电路包括多个所述多路选择器,第二级所述子电路中的各所述多路选择器的输入端与第一级所述子电路中的所述多路选择器的输出端一一对应连接,第二极所述子电路中的所述多路选择器的输出端与所述显示区域的所述信号线相连。
- 如权利要求1所述的阵列基板,其中,所述测试电路包括三级所述子电路;第一级所述子电路包括一个多路选择器,第一级所述子电路中的所述多路选择器的输入端与所述测试端子相连;第二级所述子电路包括多个所述多路选择器,第二级所述子电路中的各所述多路选择器的输入端与第一级所述子电路中的所述多路选择器的输出端一一对应连接;第三级所述子电路包括多个所述多路选择器,第三级所述子电路中的各所述多路选择器的输入端与第二级所述子电路中的所述多路选择器的输出端一一对应连接,第三级所述子电路的所述多路选择器的输出端与所述显示区域的所述信号线相连。
- 如权利要求1-5任一项所述的阵列基板,其中,所述阵列基板包括多个所述测试电路;各所述测试电路共用所述控制线。
- 如权利要求1-5任一项所述的阵列基板,其中,所述多路选择器包括:多个第一晶体管;各所述第一晶体管的栅极分别与对应的所述控制线相连,各所述第一晶体管的第一极与所述多路选择的输入端相连,各所述第一晶体管的第二极分别与所述多路选择器对应的所述输出端相连。
- 如权利要求7所述的阵列基板,其中,所述第一晶体管为双栅型晶体管。
- 如权利要求1-5任一项所述的阵列基板,其中,相邻两条所述控制线 之间设置有第一静电释放电路;所述第一静电释放电路的输入端与一条所述控制线相连,所述第一静电释放电路的输出端与相邻的另一条所述控制线相连。
- 如权利要求9所述的阵列基板,其中,所述第一静电释放电路包括:第二晶体管和第三晶体管;所述第二晶体管的栅极、所述第二晶体管的第一极和所述第三晶体管的第二极均与一条所述控制线相连;所述第二晶体管的第二极、所述第三晶体管的栅极和所述第三晶体管的第一极均与另一条所述控制线相连。
- 如权利要求1-5任一项所述的阵列基板,其中,除最后一级所述子电路外,所述子电路的输出端设置有第二静电释放电路;所述第二静电释放电路的输入端与所述子电路中所述多路选择器的输出端相连,所述第二静电释放电路的输出端与放电线相连。
- 如权利要求11所述的阵列基板,其中,所述第二静电释放电路至少包括一个放电子电路,各所述放电子电路串联设置或并联设置。
- 如权利要求12所述的阵列基板,其中,每个所述放电子电路包括:第四晶体管、第五晶体管、第六晶体管和第七晶体管;所述第四晶体管的栅极和所述第四晶体管的第一极均与所述子电路中所述多路选择器的输出端相连,所述第四晶体管的第二极与所述放电线相连;所述第五晶体管的栅极和所述第五晶体管的第一极均与所述子电路中所述多路选择器的输出端相连,所述第五晶体管的第二极与所述放电线相连;所述第六晶体管的栅极和所述第六晶体管的第一极均与所述放电线相连,所述第六晶体管的第二极与所述子电路中所述多路选择器的输出端相连;所述第七晶体管的栅极和所述第七晶体管的第一极均与所述放电线相连,所述第七晶体管的第二极与所述子电路中所述多路选择器的输出端相连。
- 一种显示面板,其中,包括多个如权利要求1-13任一项所述的阵列基板;所述阵列基板中各测试电路中最后一级子电路中的多路选择器的输出端与所述显示面板内对应的信号线相连。
- 一种显示装置,其中,包括如权利要求14所述的显示面板。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101364022A (zh) * | 2008-09-12 | 2009-02-11 | 昆山龙腾光电有限公司 | 阵列基板及其缺陷检测方法 |
CN106019672A (zh) * | 2016-07-26 | 2016-10-12 | 武汉华星光电技术有限公司 | 一种薄膜晶体管阵列基板的制作方法 |
US9653041B2 (en) * | 2014-07-22 | 2017-05-16 | Japan Display Inc. | Image display device and method of displaying image |
CN107065336A (zh) * | 2017-06-13 | 2017-08-18 | 厦门天马微电子有限公司 | 一种阵列基板、显示面板及显示装置 |
CN206516324U (zh) * | 2016-12-28 | 2017-09-22 | 厦门天马微电子有限公司 | 阵列基板、显示面板及显示装置 |
CN209232376U (zh) * | 2018-11-22 | 2019-08-09 | 京东方科技集团股份有限公司 | 一种阵列基板、显示面板及显示装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI699739B (zh) * | 2014-09-05 | 2020-07-21 | 日商半導體能源研究所股份有限公司 | 半導體裝置、驅動器ic、顯示裝置及電子裝置 |
KR102341411B1 (ko) * | 2017-03-31 | 2021-12-22 | 삼성디스플레이 주식회사 | 터치 센서, 그의 구동 방법 및 표시 장치 |
CN107039467B (zh) * | 2017-05-15 | 2020-03-06 | 厦门天马微电子有限公司 | 一种阵列基板、显示面板及显示装置 |
-
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101364022A (zh) * | 2008-09-12 | 2009-02-11 | 昆山龙腾光电有限公司 | 阵列基板及其缺陷检测方法 |
US9653041B2 (en) * | 2014-07-22 | 2017-05-16 | Japan Display Inc. | Image display device and method of displaying image |
CN106019672A (zh) * | 2016-07-26 | 2016-10-12 | 武汉华星光电技术有限公司 | 一种薄膜晶体管阵列基板的制作方法 |
CN206516324U (zh) * | 2016-12-28 | 2017-09-22 | 厦门天马微电子有限公司 | 阵列基板、显示面板及显示装置 |
CN107065336A (zh) * | 2017-06-13 | 2017-08-18 | 厦门天马微电子有限公司 | 一种阵列基板、显示面板及显示装置 |
CN209232376U (zh) * | 2018-11-22 | 2019-08-09 | 京东方科技集团股份有限公司 | 一种阵列基板、显示面板及显示装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113555401A (zh) * | 2021-07-19 | 2021-10-26 | 京东方科技集团股份有限公司 | 一种显示基板、其检测方法及显示装置 |
CN113555401B (zh) * | 2021-07-19 | 2024-05-24 | 京东方科技集团股份有限公司 | 一种显示基板、其检测方法及显示装置 |
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