WO2020097767A1 - 电路板及超算设备 - Google Patents

电路板及超算设备 Download PDF

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Publication number
WO2020097767A1
WO2020097767A1 PCT/CN2018/115077 CN2018115077W WO2020097767A1 WO 2020097767 A1 WO2020097767 A1 WO 2020097767A1 CN 2018115077 W CN2018115077 W CN 2018115077W WO 2020097767 A1 WO2020097767 A1 WO 2020097767A1
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WIPO (PCT)
Prior art keywords
chip
circuit board
metal substrate
layer
signal
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PCT/CN2018/115077
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English (en)
French (fr)
Inventor
吕政勇
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北京比特大陆科技有限公司
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Priority to PCT/CN2018/115077 priority Critical patent/WO2020097767A1/zh
Publication of WO2020097767A1 publication Critical patent/WO2020097767A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits

Definitions

  • the present disclosure relates to the field of supercomputing equipment, for example, to a circuit board and supercomputing equipment.
  • the circuit board generally includes a substrate and a chip disposed on the substrate.
  • the substrate usually uses a copper-clad laminate.
  • the copper-clad laminate is generally formed by impregnating an electronic glass fiber cloth or other reinforcing material with resin and then pressing it.
  • a plate-like structure also known as copper clad laminate.
  • the copper-clad laminate can be selectively etched, drilled, and copper-plated to form the required circuit on the substrate.
  • the inventors of the present disclosure found that since the chip generates heat during operation, when the heat reaches a certain limit, it will affect the normal operation of the chip, and the heat dissipation of the copper-clad laminate is poor, so that the heat generated by the chip cannot be Distribute in time, reducing the performance and service life of the chip.
  • An embodiment of the present disclosure provides a circuit board, including: a metal substrate, a power layer, a chip, and a signal layer, wherein: the metal substrate is provided with the power layer and the chip; the power layer and the chip Is connected to the power pin of the chip, and the signal layer is connected to the signal pin of the chip.
  • An embodiment of the present disclosure also provides a supercomputing device, including a chassis, and at least one circuit board as described above installed in the chassis.
  • FIG. 1 is a schematic structural diagram of a circuit board according to Embodiment 1 of the present disclosure.
  • FIG. 2 is a schematic structural diagram of another circuit board provided by Embodiment 1 of the present disclosure.
  • FIG. 3 is a schematic structural diagram of a circuit board provided by Embodiment 2 of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a circuit board provided in Embodiment 3 of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a circuit board with heat sinks in Embodiment 4 of the present disclosure
  • FIG. 6 is a schematic structural diagram of another circuit board with heat sinks in Embodiment 4 of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a circuit board with heat sinks in Embodiment 5 of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another circuit board with heat sinks in Embodiment 5 of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a supercomputing device according to Embodiment 6 of the present disclosure.
  • the substrate in the circuit board is usually a plastic substrate or copper clad with poor thermal conductivity, the heat generated by the chip during the work cannot be radiated to the air around the chip in time, making the chip higher Working at a high temperature will reduce the performance of the chip (such as the computing power of the chip) and shorten the service life of the chip.
  • an embodiment of the present disclosure provides a circuit board including a metal substrate, a power layer, a chip, and a signal layer, wherein: the metal substrate is provided with the power layer and the chip; the power layer and the chip The power pin is connected, and the signal layer is connected to the signal pin of the chip.
  • the substrate uses a metal substrate with better thermal conductivity, and the metal substrate has the advantage of good thermal conductivity, and the heat generated during the operation of the chip is distributed to the air around the chip in time, so that the chip can be ideal Working within the temperature range greatly improves the performance of the chip and also extends the service life of the chip.
  • Embodiment 1 of the present disclosure provides a circuit board in which the power supply layer and the chip are located on the same side of the metal substrate.
  • the circuit board 1 includes a metal substrate 10, a power layer 20, a chip 30 and a signal layer 40, wherein: the metal substrate 10 is provided with power layers 20 and 30 chips; the power layer 20 and the chip 30 Is connected to the power pin of the signal, and the signal layer 40 is connected to the signal pin of the chip 30.
  • the metal substrate 10 is located on the bottom layer of the circuit board 1, and a power layer 20 is provided on the top surface of the metal substrate 10.
  • the power layer 20 can generally be a power trace routed on the metal substrate 10.
  • a copper foil circuit is used to provide an operating voltage for the chip 30 mounted on the metal substrate 10.
  • the signal layer 40 may generally be a signal trace for implementing signal interaction, such as a signal link for sending control signals, processing signals or reset signals to the chip, and a signal link for receiving the processing results fed back by the chip Wait, so I won't go into details.
  • the chip 30 is disposed on the top surface of the metal substrate 10, and the chip 30 and the power layer 20 do not overlap each other.
  • the edge of the chip 30 (which can also be other positions, such as the bottom or both sides, etc.) is provided with power pins 32 and signals Pin 31, wherein the power pin 32 of the chip 30 is electrically connected to the corresponding link in the power layer 20, such as soldering, snapping, etc., and the signal pin 31 of the chip 30 is signally connected to the signal layer 40, such as through a signal line Wait.
  • the signal layer 40 is disposed on the bottom surface of the metal substrate 10.
  • the signal layer 40 includes signal traces, which are connected to the signal pins 31 of the chip 30.
  • the number of signal layers 40 can be flexibly set according to actual conditions, which is not limited in this embodiment.
  • the number of signal layers 40 is multiple, two adjacent signal layers are separated by an insulating layer. As shown in FIG. 2, the number of signal layers 40 is two. The two signal layers 40 are separated by an insulating layer 41. The insulating layer 41 is provided with a third via 43 connected to the signal pin 31 of the chip 30. .
  • the number of chips 30 is not limited, that is, one, two, or more than two chips can be provided on the metal substrate 10, depending on the actual working needs of the circuit board and the single chip 30.
  • the performance is selected, for example, in this embodiment, one chip 30 is provided on the metal substrate 10.
  • the connection method between the chip 30 and the metal substrate 10 is not limited in the embodiment of the present disclosure, and the chip 30 and the metal substrate 10 may be bonded with thermally conductive adhesive, or may use mutually matching hooks and buckles
  • the snap connection can also be connected in a plug-in manner.
  • the chip 30 and the metal substrate 10 are bonded by using a thermal conductive adhesive.
  • the circuit board in the embodiment of the present disclosure may generally be set in a supercomputing device to be used for a computing task with a high computational complexity.
  • a plurality of chips 30 can usually be arranged on the circuit board, and the plurality of chips 30 can usually be divided into multiple groups of parallel chips, and each chip 30 in each group of chips is serially connected in series because of the serial chips. The current between them is usually large, so the current on the power supply trace will be large.
  • the power supply trace is connected to the power pin of the chip 30, the heat caused by the large current on the power supply trace can pass through the metal substrate 10 Emitted, it can also improve the heat dissipation capacity of the circuit board, to ensure the high performance of the chip.
  • the substrate carrying the chip 30 uses the metal substrate 10, and the thermal conductivity of the metal substrate 30 is significantly better than that of the traditional plastic substrate or copper clad laminate, therefore, the heat generated by the chip 30 during the work can pass through the metal
  • the substrate 10 is radiated into the air around the chip 30 in time to prevent heat from accumulating on the chip 30, and the heat on the power supply trace can also be dissipated through the metal substrate 10, so that the chip 30 can work at a more ideal temperature, thereby improving The performance and service life of the chip 30.
  • Embodiment 2 of the present disclosure provides a circuit board in which a power layer and a chip are located on different sides of a metal substrate.
  • the circuit board 1 includes a metal substrate 10, a power layer 20, a chip 30 and a signal layer 40, wherein: the metal substrate 10 is provided with power layer 20 and chip 30; the power layer 20 and the chip 30 Is connected to the power pin of the signal, and the signal layer 40 is connected to the signal pin of the chip 30.
  • the power supply layer 20 is provided on the bottom surface of the metal substrate 10, and the power supply layer 20 may generally be a power supply wiring routed on the metal substrate 10, such as a copper foil circuit, etc., for mounting on the metal substrate
  • the chip 30 on 10 provides the operating voltage.
  • the signal layer 40 may generally be a signal trace for implementing signal interaction, such as a signal link for sending control signals, processing signals or reset signals to the chip, and a signal link for receiving the processing results fed back by the chip Wait, so I won't go into details.
  • the chip 30 is disposed on the top surface of the metal substrate 10, that is, the power supply layer 20 and the chip 30 are located on the upper and lower sides of the metal substrate 10, and the edge of the chip 30 (which can also be other locations, such as the bottom or both sides, etc.) is provided with power pins 32 and signal pin 31.
  • the metal substrate 10 is provided with a first via 12, and the power pins 32 of the chip are connected to the power traces in the power layer 20 through the first via 12.
  • the signal pin 31 of the chip 30 is signal-connected to the signal layer 40; in this embodiment, the signal layer 40 is disposed on the bottom surface of the metal substrate 10, the signal layer 40 includes signal traces, and the signal traces are connected to the signal pins 31 of the chip 30 connection.
  • the number of signal layers 40 can be flexibly set according to actual conditions, which is not limited in this embodiment.
  • the number of signal layers 40 is multiple, two adjacent signal layers are separated by an insulating layer.
  • the number of chips 30 is not limited, that is, one, two, or more than two chips can be provided on the metal substrate 10, depending on the actual working needs of the circuit board and the single chip 30.
  • the performance is selected, for example, in this embodiment, one chip 30 is provided on the metal substrate 10.
  • the connection method between the chip 30 and the metal substrate 10 is not limited in the embodiment of the present disclosure, and the chip 30 and the metal substrate 10 may be bonded with thermally conductive adhesive, or may be snap-fitted with each other, It can also be connected in a plug-in manner.
  • the chip 30 and the metal substrate 10 are bonded by using thermal conductive adhesive.
  • the circuit board in the embodiment of the present disclosure may generally be set in a supercomputing device to be used for a computing task with a high computational complexity.
  • a plurality of chips 30 can usually be arranged on the circuit board, and the plurality of chips 30 can usually be divided into a plurality of chips in parallel, and each chip 30 in each group of chips is connected in series in sequence, because the The current between the two is usually large, so the current on the power trace will be very large.
  • the power trace When the power trace is connected to the power pin of the chip 30 through the first via 12 on the metal substrate 10, the current on the power trace is large
  • the heat generated can be dissipated through the metal substrate 10, which can also improve the heat dissipation capacity of the circuit board and ensure the high performance of the chip.
  • the substrate carrying the chip 30 adopts the metal substrate 10, and the thermal conductivity of the metal substrate 30 is significantly better than that of the conventional plastic substrate or copper clad laminate, therefore, the heat generated by the chip 30 during operation can pass through the metal
  • the substrate 10 is radiated into the air around the chip 30 in time to prevent heat from accumulating on the chip 30, and the heat on the power supply trace can also be dissipated through the metal substrate 10, so that the chip 30 can work at a more ideal temperature, thereby improving The performance and service life of the chip 30.
  • the chip 30 and the signal layer 40 may be located on different sides of the metal substrate 10.
  • the signal layer 40 is located on the bottom surface of the metal substrate 10
  • the chip is located on the metal substrate 10
  • the top surface of the signal layer 40 is located on the bottom surface of the metal substrate 10.
  • the metal substrate 10 is provided with a second via 11, and the signal pin 31 of the chip is connected to the signal trace of the signal layer 40 through the second via 11.
  • the chip 30 and the signal layer 40 may also be located on the same side of the metal substrate 10, for example, in the third embodiment, the chip 30 and the signal layer 40 are located on the same side of the metal substrate 10.
  • the circuit board 1 provided in this embodiment includes a metal substrate 10, a power layer 20, a chip 30 and a signal layer 40, wherein the chip 30 is disposed on the top surface of the metal substrate 10, and the signal layer 40 is also disposed on the metal substrate
  • the top surface of 10, that is, the signal layer 40 and the chip 30 are located on the upper side of the metal substrate 10.
  • the edge of the chip (which can also be in other positions, such as the bottom or both sides) is provided with power pins 32 and signal pins 31.
  • the power pins 32 of the chip are connected to the power layer 20 on the top surface of the metal substrate 10, the chip
  • the signal pin 31 is connected to the signal lead in the signal layer 40.
  • the number of signal layers 40 can be flexibly set according to actual conditions, which is not limited in this embodiment.
  • the number of signal layers 40 is multiple, two adjacent signal layers are separated by an insulating layer.
  • the number of chips 30 is not limited, that is, one, two, or more than two chips can be provided on the metal substrate 10, depending on the actual working needs of the circuit board and the single chip 30.
  • the performance is selected, for example, in this embodiment, one chip 30 is provided on the metal substrate 10.
  • the connection method between the chip 30 and the metal substrate 10 is not limited in the embodiment of the present disclosure, and the chip 30 and the metal substrate 10 may be bonded with thermally conductive adhesive, or may be snap-fitted with each other, It can also be connected in a plug-in manner.
  • the chip 30 and the metal substrate 10 are bonded by using thermal conductive adhesive.
  • the circuit board in the embodiment of the present disclosure may generally be set in a supercomputing device to be used for a computing task with a high computational complexity.
  • a plurality of chips 30 can usually be arranged on the circuit board, and the plurality of chips 30 can usually be divided into a plurality of chips in parallel, and each chip 30 in each group of chips is connected in series in sequence, because the The current between the two is usually large, so the current on the power trace will be very large.
  • the power trace When the power trace is connected to the power pin of the chip 30 through the first via 12 on the metal substrate 10, the current on the power trace is large
  • the heat generated can be dissipated through the metal substrate 10, which can also improve the heat dissipation capacity of the circuit board and ensure the high performance of the chip.
  • the substrate carrying the chip 30 uses the metal substrate 10, and the thermal conductivity of the metal substrate 30 is significantly better than that of the traditional plastic substrate or copper clad laminate, therefore, the heat generated by the chip 30 during the work can pass through the metal
  • the substrate 10 is radiated to the air around the chip 30 in time, and the heat on the power supply trace can also be radiated through the metal substrate 10 to prevent the heat from accumulating on the chip 30, so that the chip 30 can work at a more ideal temperature, thereby improving The performance and service life of the chip 30.
  • the signal layer 40 covers the surface of the metal substrate 10 where the chip 30 is located, and the signal layer 40 is provided with an installation to accommodate the chip 30 ⁇ 42.
  • the chip 30 is disposed on the top surface of the metal substrate 10
  • the signal layer 40 covers the top surface of the metal substrate 10 and the chip 30, and the surface of the signal layer 40 in contact with the top surface of the metal substrate 10 is provided with A mounting hole 42 that is recessed upward.
  • the mounting hole 42 is usually formed inside the signal layer 40.
  • the signal layer 40 located around the mounting hole 42 can enclose a space for accommodating the chip 30, that is, the chip 30 is mounted on the top surface of the metal substrate 10.
  • the metal substrate 10 and the signal layer 40 can be used to protect the chip 30 and prevent the chip 30 from receiving physical damage and environmental damage.
  • the power pin 32 and the signal pin 31 of the chip can also be protected, and at the same time, the fixing effect of the power pin 32 and the signal pin 31 can also be improved.
  • a heat sink for dissipating heat from the chip 30 is also provided in the above circuit board, which will be introduced through Embodiment 4 and Embodiment 5 respectively.
  • the power layer 20 is provided on the top surface of the metal substrate 10, and the chip 30 is provided on the top surface of the metal substrate 10. That is, the chip 30 and the power layer 20 are both located in FIG. 5.
  • the signal layer 40 is located on the bottom surface of the metal substrate 10, that is, the chip 30 and the signal layer 40 are located on different sides of the metal substrate 10 in FIG.
  • the chip 30 is disposed on the top surface of the metal substrate 10
  • the power layer 20 is disposed on the bottom surface of the metal substrate 10
  • the signal layer 40 is located on the bottom surface of the metal substrate 10
  • the power layer 20 is located on the metal substrate 10 and the signal Layer 40.
  • the bottom surface of the chip 30 is in contact with the top surface of the metal substrate 10, and a heat sink 50 is provided on the top surface of the chip 30.
  • the heat sink 50 may be made of aluminum or copper. , Steel, silver, aluminum alloy or copper alloy and other materials, the shape of the heat sink 50 can be plate-shaped, sheet-shaped, multi-sheet-shaped or comb-shaped.
  • the heat sink 50 can be mounted on the top surface of the chip 30 by thermal adhesive bonding, screw connection, snap connection, or the like.
  • the heat generated by the chip 30 during operation can be dissipated from the metal substrate 10 into the surrounding air on the one hand, and can be dissipated into the surrounding air through the heat sink 50 on the other hand, thereby further improving the The heat dissipation effect of the chip 30.
  • the mounting positions of the heat sink are as follows:
  • the mounting hole 42 is a blind hole
  • the heat sink 50 is installed on the surface of the metal substrate 10 facing away from the chip 30, and the heat sink 50 and the chip 30 Is on.
  • the bottom surface of the signal layer 40 is provided with a mounting hole 42
  • the bottom of the mounting hole 42 is located in the signal layer 40, that is, the mounting hole 42 does not penetrate the upper and lower surfaces of the signal layer 40, that is, the mounting hole 42 is blind
  • the heat sink 50 is usually provided on the bottom surface of the metal substrate 10, and the heat sink 50 is used to dissipate the bottom surface of the metal substrate 10 directly opposite the chip 30, thereby quickly dissipating the heat generated during the operation of the chip 30 Into the surrounding air.
  • the mounting hole 42 is a through hole
  • the top surface of the chip 30 facing away from the metal substrate 10 is provided with a heat sink 50, and at least part of the heat sink 50 is exposed to the mounting hole 42 outer.
  • the mounting hole 42 penetrates the signal layer 40.
  • the heat sink 50 may be disposed on the top surface of the chip 30, that is, the heat sink 50 is installed in the mounting hole 42.
  • the mounting hole 42 is a through hole, the heat sink is installed in the mounting hole 42 to still radiate the chip 30.
  • at least part of the heat sink 50 is exposed outside the mounting hole 42, ie the heat sink Part or all of 50 is exposed outside the mounting hole 42, which can further improve the heat dissipation effect of the heat sink 50 on the chip 30.
  • the metal substrate has better thermal conductivity.
  • the metal substrate is an aluminum substrate, a tungsten substrate, a molybdenum substrate, a copper substrate, a nickel-iron alloy substrate, or a nickel-cobalt alloy substrate.
  • the signal layer includes a flexible board and signal traces formed on the flexible board.
  • the flexible board may be a polyimide board, an epoxy resin board, a polyethylene terephthalate PET board, or a polytetrafluoroethylene board.
  • Embodiment 6 of the present disclosure provides a supercomputing device.
  • the supercomputing device includes a chassis 2 and at least one circuit board 1 installed in the chassis 2 as described in Embodiments 1 to 5 above.
  • the supercomputing device includes the circuit boards 1 described in the first to fifth embodiments, the supercomputing device has the same advantages as the circuit board 1 described in the first to fifth embodiments, and will not be repeated here.
  • At least one circuit board slot is provided inside the chassis 2, and each circuit board 1 is installed in a corresponding circuit board slot.
  • a mounting board is provided inside the chassis, and only a circuit board slot is provided on the mounting board, or a circuit board slot is provided on the inner side wall of the chassis; the circuit board 1 may be inserted into the circuit board slot, With such a design, the circuit board 1 can be easily removed from the chassis 2 and removed from the chassis 2 to facilitate maintenance and overhaul of the supercomputer equipment.
  • the supercomputing device provided in the embodiment of the present disclosure may generally be a computing device capable of high-speed calculation, such as AI (Artificial Intelligence) computing device, digital voucher processing device, and accounting voucher data processing Devices and the like are not limited as long as the circuit board provided in the present disclosure can be used.
  • AI Artificial Intelligence
  • first, second, etc. may be used in this disclosure to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
  • the first element can be called the second element, and likewise, the second element can be called the first element, as long as all occurrences of the "first element” are consistently renamed and all occurrences of The “second component” can be renamed consistently.
  • the first element and the second element are both elements, but they may not be the same element.
  • the various aspects, implementations, implementations, or features in the described embodiments can be used alone or in any combination.
  • Various aspects in the described embodiments may be implemented by software, hardware, or a combination of software and hardware.
  • the described embodiments may also be embodied by a computer-readable medium that stores computer-readable code including instructions executable by at least one computing device.
  • the computer-readable medium can be associated with any data storage device capable of storing data, which can be read by a computer system.
  • Computer-readable media used for examples may include read-only memory, random access memory, CD-ROM, HDD, DVD, magnetic tape, optical data storage devices, and the like.
  • the computer-readable medium may also be distributed in computer systems connected through a network, so that computer-readable codes can be stored and executed in a distributed manner.

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Abstract

一种电路板（1）及超算设备，涉及超算设备技术领域，用于将芯片（30）工作过程中产生的热量及时散发到芯片（30）外，以提高芯片（30）的性能和使用寿命。该电路板（1）包括金属基板（10）、电源层（20）、芯片（30）以及信号层（40），其中：所述金属基板（10）上设置有所述电源层（20）以及所述芯片（30）；所述电源层（20）与所述芯片（30）的电源引脚（32）连接，所述信号层（40）与所述芯片（30）的信号引脚（31）连接。在该电路板（1）中，承载芯片（30）的基板采用金属基板（10），能够将芯片（30）工作过程中产生的热量及时散发到周围空气中，防止热量在芯片（30）上累积，从而使得芯片（30）可以理想的温度下工作，提高芯片（30）的性能和使用寿命。该超算设备包括机箱，以及安装在所述机箱（2）内的至少一个如上所述的电路板（1）。

Description

电路板及超算设备 技术领域
本公开涉及超算设备领域，例如涉及一种电路板及超算设备。
背景技术
近年来随着人工智能技术的飞速发展，具有低功耗、高算力的电路板成为人工智能领域研究的热点。
电路板一般包括基板和设置在基板上的芯片，其中，基板通常采用覆铜箔层压板，覆铜箔层压板一般是将电子玻纤布或其它增强材料浸以树脂后经过热压形成的一种板状结构，也称为覆铜板。根据电路板的性能要求不同，可对覆铜箔层压板选择性地进行刻蚀、钻孔和镀铜等工序，从而在基板上形成所需的电路。
不过，本公开的发明人发现，由于芯片在工作过程中会产生热量，当热量达到一定限度后会影响芯片的正常工作，而覆铜箔层压板的散热性较差，导致芯片产生的热量不能及时散发，降低了芯片的性能以及使用寿命。
发明内容
本公开实施例提供了一种电路板，包括：金属基板、电源层、芯片以及信号层，其中：所述金属基板上设置有所述电源层以及所述芯片；所述电源层与所述芯片的电源引脚连接，所述信号层与所述芯片的信号引脚连接。
本公开实施例还提供了一种超算设备，包含机箱，以及安装在所述机箱内的至少一个如上述的电路板。
附图说明
一个或多个实施例通过与之对应的附图进行示例性说明，这些示例性说明和附图并不构成对实施例的限定，附图中具有相同参考数字标号的元件示为类似的元件，附图不构成比例限制，并且其中：
图1为本公开实施例一提供的一种电路板的结构示意图；
图2为本公开实施例一提供的另一种电路板的结构示意图；
图3为本公开实施例二提供的电路板的结构示意图；
图4为本公开实施例三提供的电路板的结构示意图；
图5为本公开实施例四中一种具有散热片的电路板的结构示意图；
图6为本公开实施例四中另一种具有散热片的电路板的结构示意图；
图7为本公开实施例五中一种具有散热片的电路板的结构示意图；
图8为本公开实施例五中另一种具有散热片的电路板的结构示意图；
图9为本公开实施例六提供的超算设备的结构示意图。
具体实施方式
为了能够更加详尽地了解本公开实施例的特点与技术内容，下面结合附图对本公开实施例的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本公开实施例。在以下的技术描述中，为方便解释起见，通过多个细节以提供对所披露实施例的充分理解。然而，在没有这些细节的情况下，一个或多个实施例仍然可以实施。在其它情况下，为简化附图，熟知的结构和装置可以简化展示。
在已有的电路板中，由于电路板中的基板通常为导热性较差的塑料基板或覆铜板，导致芯片在工作过程中产生的热量不能及时散发到芯片周围空气中，使得芯片在较高的温度下进行工作，导致芯片的性能(如芯片的计算能力)降低，同时也缩短了芯片的使用寿命。
鉴于上述问题，本公开实施例提供了一种电路板，该电路板包括金属基板、电源层、芯片以及信号层，其中：金属基板上设置有所述电源层以及所述芯片；电源层与芯片的电源引脚连接，信号层与芯片的信号引脚连接。在本公开实施例中，基板采用具有较佳导热性能的金属基板，利用金属基板具有良好的导热性优点，将芯片工作过程中产生的热量及时散发到芯片周围空气中，从而使芯片可以在理想的温度范围内进行工作，大大提高了芯片的性能，同时也延长了芯片的使用寿命。
需要说明的是，在本公开的各附图中，电路板中各层的厚度仅为示意，不表示实际情况，对此不作赘述。
实施例一
本公开实施例一提供了一种电路板，在该电路板中，电源层和芯片位于 金属基板的同一侧。示例性地，请参阅图1，该电路板1包括金属基板10、电源层20、芯片30以及信号层40，其中：金属基板10上设置有电源层20以及30芯片；电源层20与芯片30的电源引脚连接，信号层40与芯片30的信号引脚连接。
具体地，在本实施例中，金属基板10位于该电路板1的底层，在金属基板10的顶面设置有电源层20，电源层20通常可为布设在金属基板10上的电源走线，如铜箔线路等，用于为安装在金属基板10上的芯片30提供工作电压。信号层40通常可为用于实现信号交互的信号走线，如用于向芯片发送控制信号、处理信号或者复位信号等信号的信号链路，以及用于接收芯片反馈的处理结果的信号链路等，对此不作赘述。
芯片30设置在金属基板10的顶面，且芯片30与电源层20之间互不重叠，芯片30的边缘(也可为其它位置，如底部或者两侧等)设置有电源引脚32和信号引脚31，其中，芯片30的电源引脚32与电源层20中的对应链路电连接，如焊接、卡接等，芯片30的信号引脚31与信号层40信号连接，如通过信号线等。在本实施例中，信号层40设置在金属基板10的底面，信号层40包括信号走线，信号走线与芯片30的信号引脚31连接。
可选地，在本实施例中，信号层40的层数可根据实际情况灵活设定，本实施例中对此不做限定。当信号层40的层数为多层时，相邻的两层信号层之间由绝缘层隔开。如图2所示,信号层40的层数为两层，两层信号层40之间由绝缘层41隔离，绝缘层41中设置有与芯片30的信号引脚31连接的第三过孔43。
需要说明的是，在本实施例中芯片30的数量不做限制，即金属基板10上可以设置一个、二个或二个以上数量的芯片，具体根据电路板的实际工作需要以及单个芯片30的性能选定，例如，在本实施例中在金属基板10上设置一个芯片30。此外，芯片30与金属基板10之间的连接方式在在本公开实施例中也不做限制，芯片30与金属基板10之间可以采用导热胶粘接，也可以采用相互配合卡钩和卡扣卡接，还可以采用插接的方式连接，例如在本实施例中芯片30与金属基板10之间采用导热胶粘接。
需要说明的是，本公开实施例中的电路板通常可被设置在超算设备中，以用于计算复杂度很高的计算任务。且，电路板上通常可设置多个芯片30， 且多个芯片30通常可被分为多组并联的芯片，而每一组芯片中的各芯片30都是依次串联的，因为各串联芯片之间的电流通常较大，因而电源走线上的电流就会很大，当电源走线与芯片30的电源引脚连接时，电源走线上大电流所带来的热量就可以通过金属基板10散发出去，进而也能提升电路板的散热能力，保证芯片的高性能。
在上述实施例一中，由于承载芯片30的基板采用金属基板10，而金属基板30的导热性显著优于传统的塑料基板或覆铜板，因此，芯片30在工作过程中产生的热量可以通过金属基板10及时地散发到芯片30周围空气中，防止热量在芯片30上累积，且电源走线上的热量也可通过金属基板10散发出去，使得芯片30可以在较理想的温度下工作，从而提高芯片30的性能和使用寿命。
实施例二
本公开实施例二提供了一种电路板，在该电路板中，电源层和芯片位于金属基板的不同侧。示例性地，请参阅图3，该电路板1包括金属基板10、电源层20、芯片30以及信号层40，其中：金属基板10上设置有电源层20以及30芯片；电源层20与芯片30的电源引脚连接，信号层40与芯片30的信号引脚连接。
具体地，在本实施例中，电源层20设置在金属基板10的底面，电源层20通常可为布设在金属基板10上的电源走线，如铜箔线路等，用于为安装在金属基板10上的芯片30提供工作电压。信号层40通常可为用于实现信号交互的信号走线，如用于向芯片发送控制信号、处理信号或者复位信号等信号的信号链路，以及用于接收芯片反馈的处理结果的信号链路等，对此不作赘述。
芯片30设置在金属基板10的顶面，即电源层20和芯片30位于金属基板10的上下两侧，芯片30的边缘(也可为其它位置，如底部或者两侧等)设置有电源引脚32和信号引脚31。金属基板10中设置有第一过孔12，芯片的电源引脚32通过第一过孔12与电源层20中的电源走线连接。
芯片30的信号引脚31与信号层40信号连接；在本实施例中，信号层40设置在金属基板10的底面，信号层40包括信号走线，信号走线与芯片30的信号引脚31连接。
可选地，在本实施例中，信号层40的层数可根据实际情况灵活设定，本实施例中对此不做限定。当信号层40的层数为多层时，相邻的两层信号层之间由绝缘层隔开。
需要说明的是，在本实施例中芯片30的数量不做限制，即金属基板10上可以设置一个、二个或二个以上数量的芯片，具体根据电路板的实际工作需要以及单个芯片30的性能选定，例如，在本实施例中在金属基板10上设置一个芯片30。此外，芯片30与金属基板10之间的连接方式在在本公开实施例中也不做限制，芯片30与金属基板10之间可以采用导热胶粘接，也可以采用相互配合卡扣卡接，还可以采用插接的方式连接，例如在本实施例中芯片30与金属基板10之间采用导热胶粘接。
需要说明的是，本公开实施例中的电路板通常可被设置在超算设备中，以用于计算复杂度很高的计算任务。且，电路板上通常可设置多个芯片30，且多个芯片30通常可被分为多组并联的芯片，而每一组芯片中的各芯片30都是依次串联的，因为各串联芯片之间的电流通常较大，因而电源走线上的电流就会很大，当电源走线与芯片30的电源引脚通过金属基板10上的第一过孔12连接时，电源走线上大电流所带来的热量就可以通过金属基板10散发出去，进而也能提升电路板的散热能力，保证芯片的高性能。
在上述实施例二中，由于承载芯片30的基板采用金属基板10，而金属基板30的导热性显著优于传统的塑料基板或覆铜板，因此，芯片30在工作过程中产生的热量可以通过金属基板10及时地散发到芯片30周围空气中，防止热量在芯片30上累积，且电源走线上的热量也可通过金属基板10散发出去，使得芯片30可以在较理想的温度下工作，从而提高芯片30的性能和使用寿命。
在本公开实施例提供的电路板中，芯片30和信号层40可以位于金属基板10的不同侧，例如，在上述实施例一中，信号层40位于金属基板10的底面，芯片位于金属基板10的顶面，信号层40位于金属基板10的底面。当芯片30和信号层40位于金属基板10的不同侧时，金属基板10中设置有第二过孔11，芯片的信号引脚31通过第二过孔11与信号层40的信号走线连接。
但并不限于此，芯片30和信号层40也可以位于金属基板10的同侧，例如在实施例三中，芯片30和信号层40位于金属基板10的同侧。
实施例三
请参阅图4，本实施例提供的电路板1包括金属基板10、电源层20、芯片30以及信号层40，其中，芯片30设置在金属基板10的顶面，信号层40也设置在金属基板10的顶面，即信号层40和芯片30位于金属基板10的上侧。芯片的边缘(也可为其它位置，如底部或者两侧等)设置有电源引脚32和信号引脚31，芯片的电源引脚32与位于金属基板10的顶面的电源层20连接，芯片的信号引脚31与信号层40中的信号引线连接。
可选地，在本实施例中，信号层40的层数可根据实际情况灵活设定，本实施例中对此不做限定。当信号层40的层数为多层时，相邻的两层信号层之间由绝缘层隔开。
需要说明的是，在本实施例中芯片30的数量不做限制，即金属基板10上可以设置一个、二个或二个以上数量的芯片，具体根据电路板的实际工作需要以及单个芯片30的性能选定，例如，在本实施例中在金属基板10上设置一个芯片30。此外，芯片30与金属基板10之间的连接方式在在本公开实施例中也不做限制，芯片30与金属基板10之间可以采用导热胶粘接，也可以采用相互配合卡扣卡接，还可以采用插接的方式连接，例如在本实施例中芯片30与金属基板10之间采用导热胶粘接。
需要说明的是，本公开实施例中的电路板通常可被设置在超算设备中，以用于计算复杂度很高的计算任务。且，电路板上通常可设置多个芯片30，且多个芯片30通常可被分为多组并联的芯片，而每一组芯片中的各芯片30都是依次串联的，因为各串联芯片之间的电流通常较大，因而电源走线上的电流就会很大，当电源走线与芯片30的电源引脚通过金属基板10上的第一过孔12连接时，电源走线上大电流所带来的热量就可以通过金属基板10散发出去，进而也能提升电路板的散热能力，保证芯片的高性能。
在上述实施例三中，由于承载芯片30的基板采用金属基板10，而金属基板30的导热性显著优于传统的塑料基板或覆铜板，因此，芯片30在工作过程中产生的热量能够通过金属基板10及时地散发到芯片30周围空气中，且电源走线上的热量也可通过金属基板10散发出去，防止热量在芯片30上累积，使得芯片30可以在较理想的温度下工作，从而提高芯片30的性能和使用寿命。
信号层40和芯片30位于金属基板10的同侧时，在一种较佳的实施例中，信号层40覆盖金属基板10中芯片30所在的面,信号层40内设置有容纳芯片30的安装孔42。示例性地，请继续参阅图4，芯片30设置在金属基板10的顶面，信号层40覆盖金属基板10的顶面和芯片30，信号层40与金属基板10的顶面接触的面设置有向上凹陷的安装孔42，安装孔42通常形成在信号层40内部，位于该安装孔42四周的信号层40可以围成一个容纳芯片30的空间，即芯片30安装在金属基板10的顶面，并位于安装孔42内。如此设计，可以利用金属基板10和信号层40来保护芯片30，防止芯片30收到物理伤害以及环境伤害。此外，也可以保护芯片的电源引脚32和信号引脚31，同时，还能提高对电源引脚32和信号引脚31的固定效果。
为了进一步提高对芯片30的散热效果，在一较佳实施例中，上述电路板中还设置了用于对芯片30进行散热的散热片，下面将通过实施例四和实施例五分别介绍。
实施例四
请参阅图5，在本实施例提供的电路板1中，电源层20设置在金属基板10的顶面，芯片30设置在金属基板10的顶面，即芯片30和电源层20均位于图5中金属基板10的同侧；信号层40位于金属基板10的底面，即芯片30和信号层40位于图4中金属基板10的不同侧。或者，如图6所示，芯片30设置在金属基板10的顶面，电源层20设置在金属基板10的底面，信号层40位于金属基板10的底面，且电源层20位于金属基板10和信号层40之间。
在上述图5和图6所示的电路板1中，芯片30的底面与金属基板10的顶面接触，在芯片30的顶面上设置有一个散热片50，散热片50可以由铝、铜、钢、银、铝合金或铜合金等材料制成，散热片50的形状可以为板状、片状、多片状或者梳子状。散热片50可以过导热胶粘结、或者螺丝拧接、卡扣卡接等方式安装在芯片30的顶面上。具有上述结构的电路板1，芯片30工作时产生的热量，一方面可以由金属基板10散发到周围的空气中，另一方面可以通过散热片50散发到周围的空气中，从而进一步提高了对芯片30的散热效果。
实施例五
在本实施例五中，当芯片30和电源层20位于金属基板10的同侧，芯片30和信号层40位于金属基板10的同侧时，散热片的安装位置如下：
在一种较佳的实施方式中，请参阅图7，在本实施例中，安装孔42为盲孔，散热片50安装在金属基板10背离芯片30的面上，且散热片50与芯片30正对。具体地，信号层40的底面设置有安装孔42，安装孔42的孔底位于信号层40内，即安装孔42未贯穿信号层40的上下两个面，也就是说，安装孔42为盲孔，在此种结构下，散热片50通常设置在金属基板10的底面，利用散热片50对与芯片30正对的金属基板10部分底面进行散热，从而将芯片30工作中产生的热量快速散发到周围空气中。
在另一种较佳的实施方式中，请参阅图8，安装孔42为通孔，芯片30背离金属基板10的顶面设置有散热片50，且散热片50的至少部分暴露在安装孔42外。具体地，在图7所示电路板中，安装孔42贯穿信号层40，在此种结构下，散热片50可以设置在芯片30的顶面，即散热片50安装在位于安装孔42内的芯片30顶面上，由于安装孔42为通孔，因此散热片安装在安装孔42内仍可对芯片30进行散热，进一步地，散热片50的至少部分暴露在安装孔42外，即散热片50一部分或全部暴露在安装孔42外，可以进一步提高散热片50对芯片30的散热效果。
需要补充的是，在上述实施例一至五中，金属基板具有较佳的导热性，可选地，金属基板为铝基板、钨基板、钼基板、铜基板、镍铁合金基板或镍钴合金基板。信号层包括软板和形成在软板上的信号走线，软板可选为聚酰亚胺板、环氧树脂板、聚对苯二甲酸乙二酯PET板或聚四氟乙烯板。
实施例六
本公开实施例六提供了一种超算设备，如图9所示，该超算设备包括机箱2，以及安装在机箱2内的至少一个如上述实施例一至五所述的电路板1。
由于该超算设备包括上述实施例一至五的所述的电路板1，因此该超算设备具有与上述实施例一至五所述的电路板1相同的优势，在此不再赘述。
进一步地，机箱2内部设置有至少一个电路板插槽，每个电路板1安装在对应的一个电路板插槽中。示例性地，在机箱内部设置有安装板，在该安装板上只有电路板插槽，或，在机箱的内侧壁设置有电路板插槽；电 路板1可以插装在电路板插槽中，如此设计，可以方便将电路板1在机箱2内以及从机箱2上拆下，方便对超算设备进行维护与检修。
需要说明的是，本公开实施例中提供的超算设备通常可为能够进行高速计算的计算设备，如用于AI(Artificial Intelligence，人工智能)计算设备、数字凭证处理设备、记账凭证数据处理设备等，只要能够采用本公开中提供的电路板即可，对此不作任何限定。
当用于本公开中时，虽然术语“第一”、“第二”等可能会在本公开中使用以描述各元件，但这些元件不应受到这些术语的限制。这些术语仅用于将一个元件与另一个元件区别开。比如，在不改变描述的含义的情况下，第一元件可以叫做第二元件，并且同样第，第二元件可以叫做第一元件，只要所有出现的“第一元件”一致重命名并且所有出现的“第二元件”一致重命名即可。第一元件和第二元件都是元件，但可以不是相同的元件。
本公开中使用的用词仅用于描述实施例并且不用于限制权利要求。如在实施例以及权利要求的描述中使用的，除非上下文清楚地表明，否则单数形式的“一个”(a)、“一个”(an)和“所述”(the)旨在同样包括复数形式。类似地，如在本公开中所使用的术语“和/或”是指包含一个或一个以上相关联的列出的任何以及所有可能的组合。另外，当用于本公开中时，术语“包括”(comprise)及其变型“包括”(comprises)和/或包括(comprising)等指陈述的特征、整体、步骤、操作、元素，和/或组件的存在，但不排除一个或一个以上其它特征、整体、步骤、操作、元素、组件和/或这些的分组的存在或添加。
所描述的实施例中的各方面、实施方式、实现或特征能够单独使用或以任意组合的方式使用。所描述的实施例中的各方面可由软件、硬件或软硬件的结合实现。所描述的实施例也可以由存储有计算机可读代码的计算机可读介质体现，该计算机可读代码包括可由至少一个计算装置执行的指令。所述计算机可读介质可与任何能够存储数据的数据存储装置相关联，该数据可由计算机***读取。用于举例的计算机可读介质可以包括只读存储器、随机存取存储器、CD-ROM、HDD、DVD、磁带以及光数据存储装置等。所述计算机可读介质还可以分布于通过网络联接的计算机***中，这样计算机可读代码就可以分布式存储并执行。
上述技术描述可参照附图，这些附图形成了本公开的一部分，并且通过描述在附图中示出了依照所描述的实施例的实施方式。虽然这些实施例描述的足够详细以使本领域技术人员能够实现这些实施例，但这些实施例是非限制性的；这样就可以使用其它的实施例，并且在不脱离所描述的实施例的范围的情况下还可以做出变化。比如，流程图中所描述的操作顺序是非限制性的，因此在流程图中阐释并且根据流程图描述的两个或两个以上操作的顺序可以根据若干实施例进行改变。作为另一个例子，在若干实施例中，在流程图中阐释并且根据流程图描述的一个或一个以上操作是可选的，或是可删除的。另外，某些步骤或功能可以添加到所公开的实施例中，或两个以上的步骤顺序被置换。所有这些变化被认为包含在所公开的实施例以及权利要求中。
另外，上述技术描述中使用术语以提供所描述的实施例的透彻理解。然而，并不需要过于详细的细节以实现所描述的实施例。因此，实施例的上述描述是为了阐释和描述而呈现的。上述描述中所呈现的实施例以及根据这些实施例所公开的例子是单独提供的，以添加上下文并有助于理解所描述的实施例。上述说明书不用于做到无遗漏或将所描述的实施例限制到本公开的精确形式。根据上述教导，若干修改、选择适用以及变化是可行的。在某些情况下，没有详细描述为人所熟知的处理步骤以避免不必要地影响所描述的实施例。

Claims (14)

  1. 一种电路板，其特征在于，包括金属基板、电源层、芯片以及信号层，其中：
    所述金属基板上设置有所述电源层以及所述芯片；
    所述电源层与所述芯片的电源引脚连接，所述信号层与所述芯片的信号引脚连接。
  2. 根据权利要求1所述的电路板，其特征在于，所述电源层与所述芯片设置在所述金属基板的同一侧。
  3. 根据权利要求1所述的电路板，其特征在于，所述电源层与所述芯片设置在所述金属基板的不同侧，所述金属基板中设置有连接所述电源层和所述芯片的电源引脚的第一过孔。
  4. 根据权利要求1所述的电路板，其特征在于，所述信号层与所述芯片设置在所述金属基板的同一侧。
  5. 根据权利要求4所述的电路板，其特征在于，所述信号层覆盖所述金属基板中所述芯片所在的面,所述信号层内设置有容纳所述芯片的安装孔。
  6. 根据权利要求5所述的电路板，其特征在于，所述安装孔为通孔，所述芯片背离所述金属基板的顶面设置有散热片，且所述散热片的至少部分暴露在所述安装孔外。
  7. 根据权利要求5所述的电路板，其特征在于，所述安装孔为盲孔，所述散热片安装在所述金属基板背离所述芯片的面上，且所述散热片与所述芯片正对。
  8. 根据权利要求1所述的电路板，其特征在于，所述信号层与所述芯片设置在所述金属基板的不同侧，所述金属基板中设置有连接所述信号层和所述芯片的信号引脚的第二过孔。
  9. 根据权利要求8所述的电路板，其特征在于，所述芯片背离所述金属基板的顶面设置有散热片。
  10. 根据权利要求1所述的电路板，其特征在于，所述金属基板为铝基板、钨基板、钼基板、铜基板、镍铁合金基板或镍钴合金基板。
  11. 根据权利要求1所述的电路板，其特征在于，所述信号层的层数为多层，相邻两层所述信号层之间通过绝缘层隔离。
  12. 根据权利要求11所述的电路板，其特征在于，所述绝缘层为聚酰亚胺层、环氧树脂层、聚对苯二甲酸乙二酯PET层和/或聚四氟乙烯层。
  13. 一种超算设备，其特征在于，包括机箱，以及安装在所述机箱内的至少一个如权利要求1-12任一项所述的电路板。
  14. 根据权利要求13所述的超算设备，其特征在于，所述机箱内部设置有至少一个电路板插槽，每个所述电路板安装在对应的一个所述电路板插槽中。
PCT/CN2018/115077 2018-11-12 2018-11-12 电路板及超算设备 WO2020097767A1 (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6497943B1 (en) * 2000-02-14 2002-12-24 International Business Machines Corporation Surface metal balancing to reduce chip carrier flexing
CN1492498A (zh) * 1995-11-29 2004-04-28 ������������ʽ���� 半导体器件
CN2684375Y (zh) * 2003-08-25 2005-03-09 威盛电子股份有限公司 芯片封装结构
CN102105018A (zh) * 2010-12-31 2011-06-22 深圳市金宏威实业发展有限公司 一种多层电路板
CN103117263A (zh) * 2013-01-31 2013-05-22 建荣集成电路科技(珠海)有限公司 一种集成电路封装
CN207410582U (zh) * 2017-10-27 2018-05-25 成都淞源电子科技有限公司 一种高速数字信号处理电路板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1492498A (zh) * 1995-11-29 2004-04-28 ������������ʽ���� 半导体器件
US6497943B1 (en) * 2000-02-14 2002-12-24 International Business Machines Corporation Surface metal balancing to reduce chip carrier flexing
CN2684375Y (zh) * 2003-08-25 2005-03-09 威盛电子股份有限公司 芯片封装结构
CN102105018A (zh) * 2010-12-31 2011-06-22 深圳市金宏威实业发展有限公司 一种多层电路板
CN103117263A (zh) * 2013-01-31 2013-05-22 建荣集成电路科技(珠海)有限公司 一种集成电路封装
CN207410582U (zh) * 2017-10-27 2018-05-25 成都淞源电子科技有限公司 一种高速数字信号处理电路板

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