WO2020094220A1 - Integrated circuit and standard cell thereof - Google Patents

Integrated circuit and standard cell thereof Download PDF

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Publication number
WO2020094220A1
WO2020094220A1 PCT/EP2018/080402 EP2018080402W WO2020094220A1 WO 2020094220 A1 WO2020094220 A1 WO 2020094220A1 EP 2018080402 W EP2018080402 W EP 2018080402W WO 2020094220 A1 WO2020094220 A1 WO 2020094220A1
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WO
WIPO (PCT)
Prior art keywords
gate
integrated circuit
isolation
diffusion layer
standard cell
Prior art date
Application number
PCT/EP2018/080402
Other languages
French (fr)
Inventor
Stephane Badel
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Priority to EP18799753.1A priority Critical patent/EP3867951A1/en
Priority to PCT/EP2018/080402 priority patent/WO2020094220A1/en
Priority to CN201880099162.1A priority patent/CN112970110B/en
Publication of WO2020094220A1 publication Critical patent/WO2020094220A1/en

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    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
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    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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    • H01L27/118—Masterslice integrated circuits
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    • H01L2027/11875—Wiring region, routing
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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Definitions

  • the present invention relates to the field of integrated circuits, particularly CMOS integrated circuits including multiple transistors and/or multiple standard cells. These integrated circuits include one or more diffusion layers.
  • the present invention is particularly concerned with structuring e.g. transistors in such diffusion layers, particularly in continuous diffusion layers without breaks.
  • the present invention thus presents an integrated circuit including an isolation gate for providing electrical isolation between different regions of at least one such diffusion layer.
  • the isolation gate can provide isolation between different transistors and/or between different standard cells of the integrated circuit.
  • diffusion breaks in diffusion layers which are conventionally required to electrically isolate different transistors of an integrated circuit from another.
  • the diffusion breaks induce variations in the transistor parameters because:
  • the diffusion breaks are typically filled with an oxide. Thus, additional stress is induced by the material mismatch, wherein this stress also varies depending on the position of transistors e.g. whether they are near to or far from a diffusion break. If the diffusion breaks would be removed, i.e. a continuous diffusion layer would be formed, sources of parametric variation could be eliminated. However, in this case another way of achieving electrical isolation between different transistors of an integrated circuit, formed in the diffusion layer, has to be provided. For instance, a transistor could be formed where a diffusion break is removed, and the transistor could be forced into the off-state to achieve the required electrical isolation.
  • FIG. 9 A standard cell of a conventional integrated circuit with diffusion breaks is depicted in FIG. 9.
  • the integrated circuit includes:
  • a transistor is defined at the intersection of an active gate and a diffusion layer.
  • the diffusion layers are interrupted (diffusion break) at the left and right edge of the cells, in order to provide electrical isolation with any other standard cell that may be placed nearby. Additionally, diffusion layers may be interrupted, where electrically necessary, inside the standard cell area.
  • FIG. 10 The same standard cell, however if it would be modified to make the diffusion layers continuous, i.e. with diffusion breaks removed, is illustrated in FIG. 10.
  • the modification extends all diffusion layers in the left and right directions, resulting in continuous diffusion layers.
  • isolation gates would be inserted into the standard cell. These isolation gates are physically no different from regular active gates, but their function is to provide electrical isolation between two diffusion layer regions adjacent on their left and right sides.
  • the isolation gates of FIG. 10 must be connected to the highest or lowest potential, depending on the type (P or N, respectively) of the diffusion layer. This can be achieved by connecting them to one of the power rails (in fact, one rail referred to as“power” is at the highest potential, and one rail referred to as“ground” is at the lowest potential, e.g. ground).
  • FIG. 11 and FIG. 12 Two conventional schemes are shown in FIG. 11 and FIG. 12, respectively.
  • the isolation gates are tied to a power rail by a local interconnect.
  • this requires increasing the cell area, which is detrimental.
  • FIG. 11 a first scheme is illustrated in FIG. 11.
  • the scheme introduces a second local interconnect to connect the isolation gate to an adjacent first local interconnect (on either side (B), or both sides (A)).
  • This scheme is, however, only applicable when at least one adjacent local interconnect, typically one for the source (S), is connected to a power rail. If this is not the case, as it is shown in (C) where two local interconnects for drains (D) are adjacent to the isolation gate and both not connected to a power rail, an additional local interconnect (here for (S)) and gate have to be inserted, as it is shown in (D). This results in an area increase of the integrated circuit, which should be avoided.
  • FIG. 12 A second scheme is illustrated in FIG. 12.
  • the scheme introduces a second local interconnect to connect the isolation gate to a nearby power rail.
  • first and second local interconnects are not electrically isolated from each other, a certain minimum spacing is required between the second local interconnect, which connects the isolation gate to the power rail and any adjacent first local interconnect, which is at a different potential.
  • the present invention aims to improve conventional integrated circuits and the conventional schemes to eliminate diffusion breaks.
  • An objective is thereby to provide a new scheme to electrically isolate regions of a diffusion layer from another, without using a diffusion break and without increasing the cell or circuit area.
  • the scheme should further be applicable in a flexible manner, i.e. there should not be cases where the scheme does not work.
  • a goal of the scheme should be to reduce or eliminate sensitivity to process variations, which impact on the performance or yield.
  • a performance of an integrated circuit according to the scheme of the invention should not be worse, preferably even better, than that of a conventional integrated circuit.
  • no placement constraints should be introduced.
  • the present invention proposes modifying an integrated circuit, particularly a standard cell thereof, to obtain diffusion layers with fewer or even no diffusion breaks.
  • isolation gates are used.
  • the isolation gates are tied to a nearby power rail (“power” or“ground”). This is achieved by means of processing a gate-via, by which the power rail is directly connected to the isolation gate.
  • the processing of the gate- via particularly results a guaranteed minimum spacing to an adjacent local interconnect, and thus an improved reliability of the integrated circuit.
  • a first aspect of the invention provides an integrated circuit, comprising: at least one power rail, at least one diffusion layer, at least one isolation gate provided on the diffusion layer and configured to electrically isolate a first region of the diffusion layer from a second region of the diffusion layer, at least one gate-via vertically connecting the isolation gate to the power rail.
  • the power rail may be at the highest potential (“power”) or lowest potential (“ground”) depending on the type (P or N) of the diffusion layer.
  • the diffusion layer may particularly be a continuous diffusion layer, which extends from one edge of the integrated circuit to the opposite edge, or from one edge of a standard cell of the integrated circuit to its opposite edge.
  • the gate-via may connect a layer of the integrated circuit, in which the power rail is formed, with a layer, in which the isolation gate is formed, particularly in an intersection of isolation gate and power rail when the integrated circuit is viewed from the top.
  • the isolation gate provides electrical isolation, e.g. between transistors or between cells of the integrated circuit, and thus replaces diffusion breaks. Accordingly, the above- mentioned disadvantages of the diffusion breaks can be removed or suppressed.
  • the gate- via makes an additional interconnect, as provided in the conventional schemes (see FIG. 9 or FIG. 10) unnecessary, and allows connecting the isolation gate and power rail without increasing the area of the integrated circuit or cell.
  • the gate-via directly connects the underside of the power rail to the top of the isolation gate.
  • the isolation gate can be tied to the power rail in a simple manned without increasing the area.
  • the width of the gate-via is smaller than, and arranged within, the width of the isolation gate.
  • the integrated circuit further comprises at least one local interconnect vertically connecting the diffusion layer, wherein the gate- via is electrically isolated from the local interconnect.
  • Such a local interconnect connects to a region of the diffusion layer acting as source or drain of a transistor.
  • the shape of the gate-via provides a determined minimum spacing to the local interconnect regardless of the position of the gate-via on top of the isolation gate. Thus, shorts between the isolation gate and the local interconnect can be avoided by means of carefully designing the shape of the gate-via.
  • the isolation gate is capped with a dielectric, and/or the local interconnect is capped with a dielectric, and/or the isolation gate is capped with a different dielectric than the local interconnect.
  • the dielectric(s) supports avoiding shorts between the isolation gate and the local interconnect cause by the gate-via and/or by a via connecting the local interconnect to the power rail.
  • the top of the local interconnect is arranged at a lower level of the integrated circuit than the top of the isolation gate, or the top of the local interconnect is arranged at a higher level of the integrated circuit than the top of the isolation gate.
  • the gate-via comprises a step defining a narrower lower portion and a broader upper portion, the narrower lower bottom portion being connected to the top of the isolation gate and the broader upper portion being connected to the underside of the power rail, and the underside of the broader upper portion is arranged at a higher level of the integrated circuit than the top of the local interconnect.
  • the isolation gate extends perpendicular to the power rail, and the gate-via is arranged in an intersecting area of the isolation gate and the power rail in a top-view of the integrated circuit.
  • the integrated circuit comprises a plurality of standard cells, wherein at least one standard cell includes at least one power rail, at least one diffusion layer, at least one isolation gate, and at least one gate-via vertically connecting the isolation gate to the power rail.
  • At least one isolation gate is arranged and configured to electrically isolate a first region of the diffusion layer in a standard cell from a second region of the diffusion layer in a neighboring standard cell.
  • At least one isolation gate is arranged and configured to electrically isolate a first region of the diffusion layer associated with a transistor in a standard cell from a second region of the diffusion layer associated with a neighboring transistors in the same standard cell.
  • the integrated circuit comprises in at least one standard cell: at least two power rails extending from a first edge to a second opposite edge of the standard cell, at least two diffusion layers extending in a direction from the first edge towards the second edge of the standard cell, wherein one diffusion layer is arranged close to one of the power rails and the other diffusion layer is arranged close to the other one of the power rails, and a plurality of isolation gates, wherein one or more isolation gates of a first set of isolation gates are connected by a gate-via to one of the power rails and one or more isolation gates of a second set of isolation gates are connected by a gate-via to the other one of the power rails.
  • two of the isolation gates are arranged and configured to electrically isolate a first region of a diffusion layer in the standard cell from a second region of the diffusion layer in a first neighboring standard cell adjacent the first edge and from a third region of the diffusion layer in a second neighboring standard cell adjacent the second edge.
  • the integrated circuit comprises at least one active gate defining a transistor, and at least two local interconnects defining respectively a source and a drain of the transistor.
  • the device of the first aspect may be manufactured by making use of a self-aligned gate- via contact process.
  • the gate-via provides a connection directly from the power rail to the isolation gate, without adding an additional second local interconnect, and the resulting gate- via is electrically isolated from any adjacent local interconnect (e.g. for a source or drain diffusion region) thanks to its particular shape and/or other measures described above.
  • any adjacent local interconnect e.g. for a source or drain diffusion region
  • a continuous diffusion layer can be provided, or at least a number of diffusion breaks can be reduced, to improve circuit performance by enhancing the channel stress.
  • a continuous diffusion layer can eliminate any variation or sensitivity caused conventionally by diffusion breaks (e.g. layout-dependent effects (LDE)).
  • LDE layout-dependent effects
  • a standard cell area can be reduced, or at least is not increased, and no placement constraints (such as forbidden drain-drain abutment) are introduced.
  • FIG. 1 shows an integrated circuit according to an embodiment of the invention.
  • FIG. 2 shows an integrated circuit according to an embodiment of the invention.
  • FIG. 3 shows an integrated circuit with multiple standard cells according to an embodiment of the invention.
  • FIG. 4 shows gate-vias in an integrated circuit according to an embodiment of the invention.
  • FIG. 5 shows a gate-vias in an integrated circuit according to an embodiment of the invention.
  • FIG. 6 shows an isolation gate, diffusion layer, and local interconnects in an integrated circuit according to an embodiment of the invention.
  • FIG. 7 shows an isolation gate, diffusion layer, and local interconnects in an integrated circuit according to an embodiment of the invention.
  • FIG. 8 shows an isolation gate, diffusion layer, and local interconnects in an integrated circuit according to an embodiment of the invention.
  • FIG. 9 shows a conventional integrated circuit with diffusion breaks.
  • FIG. 10 shows an exemplary integrated circuit without diffusion breaks.
  • FIG. 11 shows a first conventional scheme for eliminating diffusion breaks.
  • FIG. 12 shows a second conventional scheme for eliminating diffusion breaks.
  • FIG. 1 shows an integrated circuit 100 according to a general embodiment of the invention, wherein the integrated circuit 100 is shown in a top view.
  • the integrated circuit 100 may specifically be a CMOS integrated circuit, in which multiple transistors are defined by diffusion layers, gates and interconnects to source/drain regions of the diffusion layers, respectively.
  • the integrated circuit 100 may comprise multiple standard cells, wherein each standard cell may have the same design, and wherein standard cells may be arranged adjacent one another.
  • the integrated circuit 100 shown in FIG. 1 includes at least one power rail 101 (in the following this power rail 101 may be at the highest potential“power” or lowest potential“ground”), at least one diffusion layer 102, and at least one isolation gate 103 provided on the diffusion layer 102 and configured to electrically isolate a first region l02a of the diffusion layer 102 from a second region l02b of the diffusion layer 102.
  • the isolation gate 103 may be forced into an“off-state” by connecting it to the power rail 101.
  • the diffusion layer 102 under the isolation gate 103 is depleted, thus separating the first diffusion layer region l02a on one side of the isolation gate 103 from the second diffusion layer region l02b on the other side of the isolation gate 103.
  • the isolation gate 103 is connected to the power rail 101 by at least one gate- via 104 of the integrated circuit, which vertically connects the isolation gate 103 and the power rail 101 (wherein the vertical direction is the direction along which multiple layers of the integrated circuit 100 are fabricated/arranged; in FIG. 1 it is the direction into the page).
  • the isolation gate 103 may specifically extend perpendicular to the power rail 101. Further, the gate- via 104 may be arranged in an intersecting area of the isolation gate 103 and the power rail 101 in the top view of the integrated circuit 100.
  • the integrated circuit 101 may notably include a plurality of standard cells, whereby each cell may include elements as are shown in FIG. 1, i.e. at least one diffusion layer 102, at least one isolation gate 103, and at least one gate-via 104 vertically connecting the isolation gate 103 and the power rail 101.
  • FIG. 2 shows an integrated circuit 100 according to an embodiment of the invention in a top view, which builds on the integrated circuit 100 shown in FIG. 1. Same elements in FIG. 1 and FIG. 2 are accordingly labelled with the same reference signs and function likewise.
  • FIG. 2 shows particularly in more detail some relevant features of the proposed integrated circuit 100, and illustrates these features exemplarily in a (simplified) standard cell 200 of the integrated circuit 100.
  • This standard cell 200 comprises: • Two diffusion layers 102 extending continuously between a left and right edge of the standard cell 200.
  • each gate 103 overlapping the cell’s left or right edge, and each gate 103 being connected to one of two power rails 101 (i.e.“power” (P-type) or“ground” (N-type)), specifically by a gate-via 104 each.
  • P-type power rails 101
  • N-type ground rails 101
  • the four isolation gates 103 shown in FIG. 2 are arranged and configured to electrically isolate the diffusion layer 102 within the standard cell 200 from the same diffusion layer 102 extending into neighboring standard cells 200. That is, the diffusion layer 102 may be continuous over more than one standard cell 200 of the integrated circuit 100.
  • FIG. 3 shows an integrated circuit 100 according to an embodiment of the invention in a top view, which builds on the integrated circuit 100 shown in FIG. 2. Same elements in FIG. 2 and FIG. 3 are accordingly labelled with the same reference signs and function likewise.
  • FIG. 3 shows particularly a more complex standard cell 200 of the integrated circuit 100 (which has multiple standard cells 200), wherein the standard cell 200 includes:
  • isolation gates 103 placed where required, particularly placed between transistors in the cell 200 and placed at the edges of the cell 200, i.e. between the cell 200 and a neighboring cell.
  • the isolation gates 103 are each tied to a power rail 101 (“power or“ground”), for instance, by placing a gate via 104 directly under the power rail 101.
  • FIG. 3 also shows that the integrated circuit 100 may include local interconnects 300, which vertically connect to one of the diffusion layers 102. Some local interconnects may be connected by vias 301 to a power rail 101. The gate-vias 104 are electrically isolated from the local interconnect 300. Further, the integrated circuit 100 may comprise at least one active gate 303 for defining a transistor, wherein a source and/or drain of the transistor is defined by at least two local interconnects 300 arranged on opposite sides of the active gate 303 on the diffusion layer 102.
  • isolation gates 103 may be arranged and configured to electrically isolate a first region l02a of the diffusion layer 102 in the cell 200 from a second region l02b of the diffusion layer 102 in a neighboring standard cell 200 or from a third region l02c of the diffusion layer 102 in another neighboring standard cell 200, i.e. to provide electrical isolation between adjacent cells.
  • isolation gates 103 may be arranged and configured to electrically isolate a first diffusion layer region associated with a transistor from a second diffusion layer region associated with a neighboring transistor in the same cell 200.
  • FIG. 4 shows details of gate-vias 104 in an integrated circuit 100 according to an embodiment of the invention, particularly of the integrated circuit 100 shown in FIG. 2.
  • FIG. 4 shows particularly a cross-section across the cut-line indicated in FIG. 2.
  • the gate-vias 104 are formed in/through the power rail 101 and connect to the top of the isolation gate 103. It is, however, also possible to directly connect the gate vias 104 to an underside of the power rail 101 and to the top of the isolation gate 103. Further, it is also possible that a power rail 101 and a gate via 104 are formed integrally.
  • the particular shape of the gate-vias 104 may show a step 201.
  • the step 201 defines a narrower lower portion of a gate-via 104 and a broader upper portion of the gate- 104.
  • the gate-via 104 may be connected with the narrower lower portion, particularly a bottom thereof, to the top of an isolation gate 103.
  • the broader upper portion of the gate-via 104 may go into/through the power rail 101, and may thus connect the isolation gate 103 to the power rail 101.
  • the broader upper portion may also connect to the underside of the power rail 101 (as exemplarily illustrated in FIG. 5).
  • FIG. 5 also shows gate-vias 104 in an integrated circuit 100 according to an embodiment of the invention.
  • FIG. 5 illustrates how the specific gate-via shapes can guarantee a certain minimum spacing to a nearby interconnect 300 (e.g. used for a drain contact) even in the presence of via misalignment or other edge placement error, whereby without the spacing the misalignment would result in unwanted electrical short between the interconnect 300 and the power rail 101, or at least in a reliability concern such as time- dependent dielectric breakdown (TDDB), due to an extremely small spacing.
  • TDDB time- dependent dielectric breakdown
  • the underside of the broader upper portion of the gate-via 104 which is defined by the step 201, may be arranged at a higher level of the integrated circuit 100 than the top of the local interconnect 300 (in the vertical direction).
  • the shape of the gate-via 104 may provide a determined minimum spacing to the local interconnect 300 regardless of the position of the gate-via 104 on top of the isolation gate 103.
  • FIG. 6, 7 and 8 show further ways to avoid shorts in the integrated circuit 100, in particular shorts between the isolation gate 103 and the local interconnect 300 that could be created, because the isolation gate 103 is contacted by the gate-via 104 and/or because the local interconnect 300 is contacted by a via 301.
  • FIG. 6 shows in (A) - (D), respectively, parts of an integrated circuit 100 according to an embodiment of the invention.
  • a diffusion layer 102, an isolation gate 103 and two local interconnects 300, one interconnect 300 on each side of the isolation gate 103, are illustrated.
  • a transistor can be formed.
  • the isolation gate 103 may be capped with a dielectric 600. Depending on the manufacturing process of the integrated circuit 100, this dielectric 600 is able to avoid shorts. In particular, as shown in (C) and (D), when the via 301 is created, the dielectric 600 may be resistant to the manufacturing process of the via 301, e.g. an etching step thereof. Thus, even if the via 301 is misaligned on the local interconnect 300 (shown in (D), whereas the via 301 is aligned in (C)), it does not connect to the isolation gate 103. However, when the gate- via 104 is created, the dielectric 600 is not resistant to the manufacturing process of the gate-via 104, e.g. an etching step thereof. FIG.
  • top of the local interconnect 300 may thus be arranged at a lower level of the integrated circuit 100 than the top of the isolation gate 103. In this way, even if the gate-via 104 is misaligned on the top of the isolation gate 103 (shown in (B), whereas the gate-via 104 is aligned in (A)), it does not connect to the local interconnect 300.
  • FIG. 7 shows in (A) - (D), respectively, parts of an integrated circuit 100 according to an embodiment of the invention.
  • a diffusion layer 102, an isolation gate 103 and two local interconnects 300, one interconnect 300 on each side of the isolation gate 103, are illustrated.
  • a transistor can be formed.
  • the local interconnect 300 may be capped with a first dielectric 700, and the isolation gate may 103 may be capped with a second different dielectric 701.
  • a third dielectric 702 could be provided between the isolation gate 103 and the local interconnect s) 300.
  • the second dielectric 701 and third dielectric 703 may also be a single common dielectric.
  • the dielectrics 700, 701 and 702 are again able to avoid shorts.
  • the dielectric 701 provided on top of the isolation gate 103 may be resistant to the manufacturing process of the via 301, e.g. an etching step thereof.
  • the via 301 is misaligned on the local interconnect 300 (shown in (D), whereas the via 301 is aligned in (C)), it does not connect to the isolation gate 103.
  • the dielectric 700 provided on top of the local interconnect(s) 300 may be resistant to the manufacturing process of the gate-via 104, e.g. an etching step thereof.
  • FIG. 8 shows parts of an integrated circuit 100 according to an embodiment of the invention.
  • a diffusion layer 102, an isolation gate 103 and two local interconnects 300, one interconnect 300 on each side of the isolation gate 103, are illustrated. By means of these parts, a transistor can be formed.
  • FIG. 8 shows particularly that the width of the gate- via 104 may be smaller than the width of the isolation gate 103.
  • the width of the gate- via 104 is preferably arranged within the width of the isolation gate 103. This is a simple way to avoid that the isolation gate 103 and a local interconnect 300 are shorted, even if the gate-via 104 is misaligned. A minimum spacing between the isolation gate 103 and local interconnect(s) 300 may be controlled during the relevant manufacturing step of the integrated circuit 100.
  • a method of manufacturing the integrated circuit 100 may comprise forming a diffusion layer 102, e.g. in or on a substrate, forming and isolation gate 103 on the diffusion layer 102, e.g. in a layer above the diffusion layer 102, forming a power rail 101, e.g. in a layer above the isolation gate 103, and finally connecting the power rail 101 and the isolation gate vertically, e.g. from layer to layer, by a gate-via 104.
  • the gate-via may be formed by etching through the power rail 101 to the isolation gate 103 below, and filling the trench with via material, e.g. a metal.

Abstract

The present invention relates to an integrated circuit, particularly a CMOS integrated circuit, which includes at least one diffusion layer. The diffusion layer may especially be a continuous diffusion layer. The present invention provides accordingly an integrated circuit including: at least one power rail, the at least one diffusion layer, at least one isolation gate provided on the diffusion layer and configured to electrically isolate a first region of the diffusion layer from a second region of the diffusion layer, and at least one gate-via vertically connecting the isolation gate to the power rail.

Description

INTEGRATED CIRCUIT AND STANDARD CELL THEREOF
TECHNICAL FIELD
The present invention relates to the field of integrated circuits, particularly CMOS integrated circuits including multiple transistors and/or multiple standard cells. These integrated circuits include one or more diffusion layers. The present invention is particularly concerned with structuring e.g. transistors in such diffusion layers, particularly in continuous diffusion layers without breaks. The present invention thus presents an integrated circuit including an isolation gate for providing electrical isolation between different regions of at least one such diffusion layer. The isolation gate can provide isolation between different transistors and/or between different standard cells of the integrated circuit.
BACKGROUND
In CMOS integrated circuits, variations in the manufacturing process, which result in parametric variation of transistors, are one of the main reasons for power, performance and yield degradation. These variations tend to increase with technology scaling.
One of the main sources of these variations are diffusion breaks in diffusion layers, which are conventionally required to electrically isolate different transistors of an integrated circuit from another. The diffusion breaks induce variations in the transistor parameters because:
• Stress, which is intentionally built into the channel by e.g. source/drain epitaxy or stress liner, is relaxed. As a consequence, the final stress depends on the size of the diffusion layer and on the position of each transistor in the diffusion layer.
• The diffusion breaks are typically filled with an oxide. Thus, additional stress is induced by the material mismatch, wherein this stress also varies depending on the position of transistors e.g. whether they are near to or far from a diffusion break. If the diffusion breaks would be removed, i.e. a continuous diffusion layer would be formed, sources of parametric variation could be eliminated. However, in this case another way of achieving electrical isolation between different transistors of an integrated circuit, formed in the diffusion layer, has to be provided. For instance, a transistor could be formed where a diffusion break is removed, and the transistor could be forced into the off-state to achieve the required electrical isolation.
Thus, conventional integrated circuit structures were proposed, which have isolation gates connected to power/ground, in order to force the isolation gate into the off-state. However, in these conventional integrated circuits, the electrical isolation by means of isolation gates is achieved at the cost of an increased area of the whole integrated circuit (particularly of each standard cell), or at the cost of placement constraints, which in the end result also in an increased area.
A standard cell of a conventional integrated circuit with diffusion breaks is depicted in FIG. 9. The integrated circuit includes:
• Two horizontal power rails, one at the top and one at the bottom of the standard cell.
• Vertical active gates, which are regularly spaced.
• Two (P- and N-type) diffusion layers arranged in the top and bottom parts of the standard cell, respectively.
• Vertical local interconnects, which act as contacts to parts of the diffusion layer functioning as source/drain.
• Via layers between the gates, local interconnects, and metal layers.
A transistor is defined at the intersection of an active gate and a diffusion layer. The diffusion layers are interrupted (diffusion break) at the left and right edge of the cells, in order to provide electrical isolation with any other standard cell that may be placed nearby. Additionally, diffusion layers may be interrupted, where electrically necessary, inside the standard cell area.
The same standard cell, however if it would be modified to make the diffusion layers continuous, i.e. with diffusion breaks removed, is illustrated in FIG. 10. The modification extends all diffusion layers in the left and right directions, resulting in continuous diffusion layers. In place of the diffusion breaks of FIG. 9, isolation gates would be inserted into the standard cell. These isolation gates are physically no different from regular active gates, but their function is to provide electrical isolation between two diffusion layer regions adjacent on their left and right sides. In order to provide said electrical isolation, the isolation gates of FIG. 10 must be connected to the highest or lowest potential, depending on the type (P or N, respectively) of the diffusion layer. This can be achieved by connecting them to one of the power rails (in fact, one rail referred to as“power” is at the highest potential, and one rail referred to as“ground” is at the lowest potential, e.g. ground).
To make such connection, two conventional schemes are shown in FIG. 11 and FIG. 12, respectively. In each scheme, the isolation gates are tied to a power rail by a local interconnect. However, this requires increasing the cell area, which is detrimental.
In particular, a first scheme is illustrated in FIG. 11. As shown specifically in (A) and (B), the scheme introduces a second local interconnect to connect the isolation gate to an adjacent first local interconnect (on either side (B), or both sides (A)). This scheme is, however, only applicable when at least one adjacent local interconnect, typically one for the source (S), is connected to a power rail. If this is not the case, as it is shown in (C) where two local interconnects for drains (D) are adjacent to the isolation gate and both not connected to a power rail, an additional local interconnect (here for (S)) and gate have to be inserted, as it is shown in (D). This results in an area increase of the integrated circuit, which should be avoided.
A second scheme is illustrated in FIG. 12. The scheme introduces a second local interconnect to connect the isolation gate to a nearby power rail. However, because the first and second local interconnects are not electrically isolated from each other, a certain minimum spacing is required between the second local interconnect, which connects the isolation gate to the power rail and any adjacent first local interconnect, which is at a different potential.
Further, a minimum overlap is required of the second local interconnect, and the isolation gate and power rail, respectively. These requirements usually also require increasing the area of the integrated circuit. SUMMARY
In view of the above-mentioned problems and disadvantages, the present invention aims to improve conventional integrated circuits and the conventional schemes to eliminate diffusion breaks. An objective is thereby to provide a new scheme to electrically isolate regions of a diffusion layer from another, without using a diffusion break and without increasing the cell or circuit area. The scheme should further be applicable in a flexible manner, i.e. there should not be cases where the scheme does not work. A goal of the scheme should be to reduce or eliminate sensitivity to process variations, which impact on the performance or yield. In particular, a performance of an integrated circuit according to the scheme of the invention should not be worse, preferably even better, than that of a conventional integrated circuit. Finally, no placement constraints should be introduced.
The objective is achieved by embodiments according to the invention as provided in the enclosed independent claims. Advantageous implementations of the present invention are further defined in the dependent claims.
In particular the present invention proposes modifying an integrated circuit, particularly a standard cell thereof, to obtain diffusion layers with fewer or even no diffusion breaks. Instead of diffusion breaks, isolation gates are used. The isolation gates are tied to a nearby power rail (“power” or“ground”). This is achieved by means of processing a gate-via, by which the power rail is directly connected to the isolation gate. The processing of the gate- via particularly results a guaranteed minimum spacing to an adjacent local interconnect, and thus an improved reliability of the integrated circuit.
A first aspect of the invention provides an integrated circuit, comprising: at least one power rail, at least one diffusion layer, at least one isolation gate provided on the diffusion layer and configured to electrically isolate a first region of the diffusion layer from a second region of the diffusion layer, at least one gate-via vertically connecting the isolation gate to the power rail.
The power rail may be at the highest potential (“power”) or lowest potential (“ground”) depending on the type (P or N) of the diffusion layer. The diffusion layer may particularly be a continuous diffusion layer, which extends from one edge of the integrated circuit to the opposite edge, or from one edge of a standard cell of the integrated circuit to its opposite edge. The gate-via may connect a layer of the integrated circuit, in which the power rail is formed, with a layer, in which the isolation gate is formed, particularly in an intersection of isolation gate and power rail when the integrated circuit is viewed from the top.
The isolation gate provides electrical isolation, e.g. between transistors or between cells of the integrated circuit, and thus replaces diffusion breaks. Accordingly, the above- mentioned disadvantages of the diffusion breaks can be removed or suppressed. The gate- via makes an additional interconnect, as provided in the conventional schemes (see FIG. 9 or FIG. 10) unnecessary, and allows connecting the isolation gate and power rail without increasing the area of the integrated circuit or cell.
In an implementation form of the first aspect, the gate-via directly connects the underside of the power rail to the top of the isolation gate.
In this way, the isolation gate can be tied to the power rail in a simple manned without increasing the area.
In a further implementation form of the first aspect, the width of the gate-via is smaller than, and arranged within, the width of the isolation gate.
In this way, shorts between the isolation gate and e.g. a local interconnect near the isolation gate, through a misaligned gate-via can be avoided.
In a further implementation form of the first aspect, the integrated circuit further comprises at least one local interconnect vertically connecting the diffusion layer, wherein the gate- via is electrically isolated from the local interconnect.
Such a local interconnect, for instance, connects to a region of the diffusion layer acting as source or drain of a transistor.
In a further implementation form of the first aspect, the shape of the gate-via provides a determined minimum spacing to the local interconnect regardless of the position of the gate-via on top of the isolation gate. Thus, shorts between the isolation gate and the local interconnect can be avoided by means of carefully designing the shape of the gate-via.
In a further implementation form of the first aspect, the isolation gate is capped with a dielectric, and/or the local interconnect is capped with a dielectric, and/or the isolation gate is capped with a different dielectric than the local interconnect.
The dielectric(s) supports avoiding shorts between the isolation gate and the local interconnect cause by the gate-via and/or by a via connecting the local interconnect to the power rail.
In a further implementation form of the first aspect, the top of the local interconnect is arranged at a lower level of the integrated circuit than the top of the isolation gate, or the top of the local interconnect is arranged at a higher level of the integrated circuit than the top of the isolation gate.
In this way, shorts between the isolation gate and the local interconnect can be avoided, even if the gate-via is misaligned on the isolation gate.
In a further implementation form of the first aspect, the gate-via comprises a step defining a narrower lower portion and a broader upper portion, the narrower lower bottom portion being connected to the top of the isolation gate and the broader upper portion being connected to the underside of the power rail, and the underside of the broader upper portion is arranged at a higher level of the integrated circuit than the top of the local interconnect.
In this way, a minimum spacing between gate-via and local interconnect is provided, and shorts between the isolation gate and the local interconnect can be avoided.
In a further implementation form of the first aspect, the isolation gate extends perpendicular to the power rail, and the gate-via is arranged in an intersecting area of the isolation gate and the power rail in a top-view of the integrated circuit.
In a further implementation form of the first aspect, the integrated circuit comprises a plurality of standard cells, wherein at least one standard cell includes at least one power rail, at least one diffusion layer, at least one isolation gate, and at least one gate-via vertically connecting the isolation gate to the power rail.
In a further implementation form of the first aspect, at least one isolation gate is arranged and configured to electrically isolate a first region of the diffusion layer in a standard cell from a second region of the diffusion layer in a neighboring standard cell.
In a further implementation form of the first aspect, at least one isolation gate is arranged and configured to electrically isolate a first region of the diffusion layer associated with a transistor in a standard cell from a second region of the diffusion layer associated with a neighboring transistors in the same standard cell.
In a further implementation form of the first aspect, the integrated circuit comprises in at least one standard cell: at least two power rails extending from a first edge to a second opposite edge of the standard cell, at least two diffusion layers extending in a direction from the first edge towards the second edge of the standard cell, wherein one diffusion layer is arranged close to one of the power rails and the other diffusion layer is arranged close to the other one of the power rails, and a plurality of isolation gates, wherein one or more isolation gates of a first set of isolation gates are connected by a gate-via to one of the power rails and one or more isolation gates of a second set of isolation gates are connected by a gate-via to the other one of the power rails.
In a further implementation form of the first aspect, in at least one standard cell, two of the isolation gates are arranged and configured to electrically isolate a first region of a diffusion layer in the standard cell from a second region of the diffusion layer in a first neighboring standard cell adjacent the first edge and from a third region of the diffusion layer in a second neighboring standard cell adjacent the second edge.
In a further implementation form of the first aspect, the integrated circuit comprises at least one active gate defining a transistor, and at least two local interconnects defining respectively a source and a drain of the transistor.
The device of the first aspect may be manufactured by making use of a self-aligned gate- via contact process. The gate-via provides a connection directly from the power rail to the isolation gate, without adding an additional second local interconnect, and the resulting gate- via is electrically isolated from any adjacent local interconnect (e.g. for a source or drain diffusion region) thanks to its particular shape and/or other measures described above. Thus, the following benefits can be achieved with the integrated circuit:
• A continuous diffusion layer can be provided, or at least a number of diffusion breaks can be reduced, to improve circuit performance by enhancing the channel stress.
• A continuous diffusion layer can eliminate any variation or sensitivity caused conventionally by diffusion breaks (e.g. layout-dependent effects (LDE)).
• A standard cell area can be reduced, or at least is not increased, and no placement constraints (such as forbidden drain-drain abutment) are introduced.
It has to be noted that all devices, elements, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof.
BRIEF DESCRIPTION OF DRAWINGS
The above described aspects and implementation forms of the present invention will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which
FIG. 1 shows an integrated circuit according to an embodiment of the invention.
FIG. 2 shows an integrated circuit according to an embodiment of the invention. FIG. 3 shows an integrated circuit with multiple standard cells according to an embodiment of the invention.
FIG. 4 shows gate-vias in an integrated circuit according to an embodiment of the invention.
FIG. 5 shows a gate-vias in an integrated circuit according to an embodiment of the invention. FIG. 6 shows an isolation gate, diffusion layer, and local interconnects in an integrated circuit according to an embodiment of the invention.
FIG. 7 shows an isolation gate, diffusion layer, and local interconnects in an integrated circuit according to an embodiment of the invention.
FIG. 8 shows an isolation gate, diffusion layer, and local interconnects in an integrated circuit according to an embodiment of the invention.
FIG. 9 shows a conventional integrated circuit with diffusion breaks.
FIG. 10 shows an exemplary integrated circuit without diffusion breaks.
FIG. 11 shows a first conventional scheme for eliminating diffusion breaks. FIG. 12 shows a second conventional scheme for eliminating diffusion breaks.
DETAILED DESCRIPTION OF EMBODIMENTS
FIG. 1 shows an integrated circuit 100 according to a general embodiment of the invention, wherein the integrated circuit 100 is shown in a top view. The integrated circuit 100 may specifically be a CMOS integrated circuit, in which multiple transistors are defined by diffusion layers, gates and interconnects to source/drain regions of the diffusion layers, respectively. Further, the integrated circuit 100 may comprise multiple standard cells, wherein each standard cell may have the same design, and wherein standard cells may be arranged adjacent one another.
In particular, the integrated circuit 100 shown in FIG. 1 includes at least one power rail 101 (in the following this power rail 101 may be at the highest potential“power” or lowest potential“ground”), at least one diffusion layer 102, and at least one isolation gate 103 provided on the diffusion layer 102 and configured to electrically isolate a first region l02a of the diffusion layer 102 from a second region l02b of the diffusion layer 102. To this end, the isolation gate 103 may be forced into an“off-state” by connecting it to the power rail 101. Thereby, the diffusion layer 102 under the isolation gate 103 is depleted, thus separating the first diffusion layer region l02a on one side of the isolation gate 103 from the second diffusion layer region l02b on the other side of the isolation gate 103.
The isolation gate 103 is connected to the power rail 101 by at least one gate- via 104 of the integrated circuit, which vertically connects the isolation gate 103 and the power rail 101 (wherein the vertical direction is the direction along which multiple layers of the integrated circuit 100 are fabricated/arranged; in FIG. 1 it is the direction into the page).
As also shown exemplarily in FIG. 1, the isolation gate 103 may specifically extend perpendicular to the power rail 101. Further, the gate- via 104 may be arranged in an intersecting area of the isolation gate 103 and the power rail 101 in the top view of the integrated circuit 100.
The integrated circuit 101 may notably include a plurality of standard cells, whereby each cell may include elements as are shown in FIG. 1, i.e. at least one diffusion layer 102, at least one isolation gate 103, and at least one gate-via 104 vertically connecting the isolation gate 103 and the power rail 101.
FIG. 2 shows an integrated circuit 100 according to an embodiment of the invention in a top view, which builds on the integrated circuit 100 shown in FIG. 1. Same elements in FIG. 1 and FIG. 2 are accordingly labelled with the same reference signs and function likewise. FIG. 2 shows particularly in more detail some relevant features of the proposed integrated circuit 100, and illustrates these features exemplarily in a (simplified) standard cell 200 of the integrated circuit 100. This standard cell 200 comprises: • Two diffusion layers 102 extending continuously between a left and right edge of the standard cell 200.
• Four isolation gates 103, each gate 103 overlapping the cell’s left or right edge, and each gate 103 being connected to one of two power rails 101 (i.e.“power” (P-type) or“ground” (N-type)), specifically by a gate-via 104 each.
In particular, the four isolation gates 103 shown in FIG. 2 are arranged and configured to electrically isolate the diffusion layer 102 within the standard cell 200 from the same diffusion layer 102 extending into neighboring standard cells 200. That is, the diffusion layer 102 may be continuous over more than one standard cell 200 of the integrated circuit 100.
FIG. 3 shows an integrated circuit 100 according to an embodiment of the invention in a top view, which builds on the integrated circuit 100 shown in FIG. 2. Same elements in FIG. 2 and FIG. 3 are accordingly labelled with the same reference signs and function likewise. FIG. 3 shows particularly a more complex standard cell 200 of the integrated circuit 100 (which has multiple standard cells 200), wherein the standard cell 200 includes:
• Two (N- and P-type) diffusion layers 102 extending horizontally and continuously from one edge of the cell 200 to the opposite edge, i.e. without diffusion breaks within the cell 200.
• A plurality of isolation gates 103 placed where required, particularly placed between transistors in the cell 200 and placed at the edges of the cell 200, i.e. between the cell 200 and a neighboring cell. The isolation gates 103 are each tied to a power rail 101 (“power or“ground”), for instance, by placing a gate via 104 directly under the power rail 101.
According to the cell 200 shown in FIG. 2, diffusion breaks are reduced or eliminated, which helps minimizing LDE and sensitivity to process variations, and the area required for the cell 200 can be reduced in this example from 7 gate pitches to 5 gate pitches, i.e. an area reduction of 28% is achieved. FIG. 3 also shows that the integrated circuit 100 may include local interconnects 300, which vertically connect to one of the diffusion layers 102. Some local interconnects may be connected by vias 301 to a power rail 101. The gate-vias 104 are electrically isolated from the local interconnect 300. Further, the integrated circuit 100 may comprise at least one active gate 303 for defining a transistor, wherein a source and/or drain of the transistor is defined by at least two local interconnects 300 arranged on opposite sides of the active gate 303 on the diffusion layer 102.
Some of the isolation gates 103 (in FIG. 3 the four isolation gates 103 at the cell edge) may be arranged and configured to electrically isolate a first region l02a of the diffusion layer 102 in the cell 200 from a second region l02b of the diffusion layer 102 in a neighboring standard cell 200 or from a third region l02c of the diffusion layer 102 in another neighboring standard cell 200, i.e. to provide electrical isolation between adjacent cells.
Some other isolation gates 103 (in FIG. 3 the two isolation gates 103 shown centrally) may be arranged and configured to electrically isolate a first diffusion layer region associated with a transistor from a second diffusion layer region associated with a neighboring transistor in the same cell 200.
FIG. 4 shows details of gate-vias 104 in an integrated circuit 100 according to an embodiment of the invention, particularly of the integrated circuit 100 shown in FIG. 2. FIG. 4 shows particularly a cross-section across the cut-line indicated in FIG. 2.
In FIG. 4 it can be seen that the gate-vias 104 are formed in/through the power rail 101 and connect to the top of the isolation gate 103. It is, however, also possible to directly connect the gate vias 104 to an underside of the power rail 101 and to the top of the isolation gate 103. Further, it is also possible that a power rail 101 and a gate via 104 are formed integrally.
The particular shape of the gate-vias 104 may show a step 201. The step 201 defines a narrower lower portion of a gate-via 104 and a broader upper portion of the gate- 104. As can be seen, the gate-via 104 may be connected with the narrower lower portion, particularly a bottom thereof, to the top of an isolation gate 103. The broader upper portion of the gate-via 104 may go into/through the power rail 101, and may thus connect the isolation gate 103 to the power rail 101. The broader upper portion may also connect to the underside of the power rail 101 (as exemplarily illustrated in FIG. 5).
FIG. 5 also shows gate-vias 104 in an integrated circuit 100 according to an embodiment of the invention. In particular, FIG. 5 illustrates how the specific gate-via shapes can guarantee a certain minimum spacing to a nearby interconnect 300 (e.g. used for a drain contact) even in the presence of via misalignment or other edge placement error, whereby without the spacing the misalignment would result in unwanted electrical short between the interconnect 300 and the power rail 101, or at least in a reliability concern such as time- dependent dielectric breakdown (TDDB), due to an extremely small spacing.
For instance, as shown in FIG. 5, the underside of the broader upper portion of the gate-via 104, which is defined by the step 201, may be arranged at a higher level of the integrated circuit 100 than the top of the local interconnect 300 (in the vertical direction). In this way, the shape of the gate-via 104 may provide a determined minimum spacing to the local interconnect 300 regardless of the position of the gate-via 104 on top of the isolation gate 103.
FIG. 6, 7 and 8 show further ways to avoid shorts in the integrated circuit 100, in particular shorts between the isolation gate 103 and the local interconnect 300 that could be created, because the isolation gate 103 is contacted by the gate-via 104 and/or because the local interconnect 300 is contacted by a via 301.
FIG. 6 shows in (A) - (D), respectively, parts of an integrated circuit 100 according to an embodiment of the invention. In particular, a diffusion layer 102, an isolation gate 103 and two local interconnects 300, one interconnect 300 on each side of the isolation gate 103, are illustrated. By means of these parts, a transistor can be formed.
The isolation gate 103 may be capped with a dielectric 600. Depending on the manufacturing process of the integrated circuit 100, this dielectric 600 is able to avoid shorts. In particular, as shown in (C) and (D), when the via 301 is created, the dielectric 600 may be resistant to the manufacturing process of the via 301, e.g. an etching step thereof. Thus, even if the via 301 is misaligned on the local interconnect 300 (shown in (D), whereas the via 301 is aligned in (C)), it does not connect to the isolation gate 103. However, when the gate- via 104 is created, the dielectric 600 is not resistant to the manufacturing process of the gate-via 104, e.g. an etching step thereof. FIG. 6 further shows that the top of the local interconnect 300 may thus be arranged at a lower level of the integrated circuit 100 than the top of the isolation gate 103. In this way, even if the gate-via 104 is misaligned on the top of the isolation gate 103 (shown in (B), whereas the gate-via 104 is aligned in (A)), it does not connect to the local interconnect 300.
FIG. 7 shows in (A) - (D), respectively, parts of an integrated circuit 100 according to an embodiment of the invention. In particular, a diffusion layer 102, an isolation gate 103 and two local interconnects 300, one interconnect 300 on each side of the isolation gate 103, are illustrated. By means of these parts, a transistor can be formed.
The local interconnect 300 may be capped with a first dielectric 700, and the isolation gate may 103 may be capped with a second different dielectric 701. Optionally, a third dielectric 702 could be provided between the isolation gate 103 and the local interconnect s) 300. The second dielectric 701 and third dielectric 703 may also be a single common dielectric. Depending on the manufacturing process of the integrated circuit 100, the dielectrics 700, 701 and 702 are again able to avoid shorts.
In particular, as shown in (C) and (D), when the via 301 is created, the dielectric 701 provided on top of the isolation gate 103 may be resistant to the manufacturing process of the via 301, e.g. an etching step thereof. Thus, even if the via 301 is misaligned on the local interconnect 300 (shown in (D), whereas the via 301 is aligned in (C)), it does not connect to the isolation gate 103. Further, as shown in (A) and (B), when the gate-via 104 is created, the dielectric 700 provided on top of the local interconnect(s) 300 may be resistant to the manufacturing process of the gate-via 104, e.g. an etching step thereof. Thus, even if the gate-via 104 is misaligned on the isolation gate 103 (shown in (B), whereas the gate-via 104 is aligned in (A)), it does not connect to the interconnect 300. The optional third dielectric 702 may be resistant to both the manufacturing process of the via 301 and of the gate-via 104, in order to further support avoiding that the isolation gate 103 and local interconnect 300 are shorted, if either gate-via 104 or via 301 is misaligned. FIG. 8 shows parts of an integrated circuit 100 according to an embodiment of the invention. In particular, a diffusion layer 102, an isolation gate 103 and two local interconnects 300, one interconnect 300 on each side of the isolation gate 103, are illustrated. By means of these parts, a transistor can be formed.
FIG. 8 shows particularly that the width of the gate- via 104 may be smaller than the width of the isolation gate 103. In the integrated circuit 100, the width of the gate- via 104 is preferably arranged within the width of the isolation gate 103. This is a simple way to avoid that the isolation gate 103 and a local interconnect 300 are shorted, even if the gate-via 104 is misaligned. A minimum spacing between the isolation gate 103 and local interconnect(s) 300 may be controlled during the relevant manufacturing step of the integrated circuit 100.
A method of manufacturing the integrated circuit 100 according to embodiments of the invention may comprise forming a diffusion layer 102, e.g. in or on a substrate, forming and isolation gate 103 on the diffusion layer 102, e.g. in a layer above the diffusion layer 102, forming a power rail 101, e.g. in a layer above the isolation gate 103, and finally connecting the power rail 101 and the isolation gate vertically, e.g. from layer to layer, by a gate-via 104. The gate-via may be formed by etching through the power rail 101 to the isolation gate 103 below, and filling the trench with via material, e.g. a metal.
The present invention has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed invention, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word“comprising” does not exclude other elements or steps and the indefinite article“a” or“an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

Claims
1. Integrated circuit (100), comprising
at least one power rail (101),
at least one diffusion layer (102),
at least one isolation gate (103) provided on the diffusion layer (102) and configured to electrically isolate a first region (l02a) of the diffusion layer (102) from a second region (l02b) of the diffusion layer (102),
at least one gate-via (104) vertically connecting the isolation gate (103) to the power rail (101).
2. Integrated circuit (100) according to claim 1, wherein
the gate-via (104) directly connects the underside of the power rail (101) to the top of the isolation gate (103).
3. Integrated circuit (100) according to claim 1 or 2, wherein
the width of the gate-via (104) is smaller than, and arranged within, the width of the isolation gate (103).
4. Integrated circuit (100) according to one of the claims 1 to 3, further comprising at least one local interconnect (300) vertically connecting the diffusion layer (102), wherein the gate-via (104) is electrically isolated from the local interconnect (300).
5. Integrated circuit (100) according to claim 4, wherein
the shape of the gate-via (104) provides a determined minimum spacing to the local interconnect (300) regardless of the position of the gate-via (104) on top of the isolation gate (103).
6. Integrated circuit (100) according to claim 4 or 5, wherein
the isolation gate (103) is capped with a dielectric (600, 701), and/or
the local interconnect (300) is capped with a dielectric (700), and/or
the isolation gate (103) is capped with a different dielectric (600, 701) than the local interconnect (300).
7. Integrated circuit (100) according to one of the claims 4 to 6, wherein
the top of the local interconnect (300) is arranged at a lower level of the integrated circuit (100) than the top of the isolation gate (103), or
the top of the local interconnect (300) is arranged at a higher level of the integrated circuit (100) than the top of the isolation gate (103).
8. Integrated circuit (100) according to one of the claims 4 to 7, wherein
the gate- via (104) comprises a step (201) defining a narrower lower portion and a broader upper portion, the narrower lower bottom portion being connected to the top of the isolation gate (103) and the broader upper portion being connected to the underside of the power rail (101), and
the underside of the broader upper portion is arranged at a higher level of the integrated circuit (100) than the top of the local interconnect (300).
9. Integrated circuit (100) according to one of the claims 1 to 8, wherein
the isolation gate (103) extends perpendicular to the power rail (101), and the gate-via (104) is arranged in an intersecting area of the isolation gate (103) and the power rail (101) in a top-view of the integrated circuit (100).
10. Integrated circuit according to one of the claims 1 to 9, comprising
a plurality of standard cells (200), wherein
at least one standard cell (200) includes at least one power rail (101), at least one diffusion layer (102), at least one isolation gate (103), and at least one gate-via (104) vertically connecting the isolation gate (103) to the power rail (101).
11. Integrated circuit (100) according to claim 10, wherein
at least one isolation gate (103) is arranged and configured to electrically isolate a first region (l02a) of the diffusion layer (102) in a standard cell (200) from a second region (l02b) of the diffusion layer (102) in a neighboring standard cell (200).
12. Integrated circuit (100) according to claim 10 or 11, wherein
at least one isolation gate (103) is arranged and configured to electrically isolate a first region (l02a) of the diffusion layer (102) associated with a transistor in a standard cell (200) from a second region (l02b) of the diffusion layer (102) associated with a neighboring transistors in the same standard cell (200).
13. Integrated circuit (100) according to one of the claims 10 to 12, comprising in at least one standard cell (200)
at least two power rails (101) extending from a first edge to a second opposite edge of the standard cell (200),
at least two diffusion layers (102) extending in a direction from the first edge towards the second edge of the standard cell (200), wherein one diffusion layer (102) is arranged close to one of the power rails (101) and the other diffusion layer (102) is arranged close to the other one of the power rails (101), and
a plurality of isolation gates (103), wherein one or more isolation gates (103) of a first set of isolation gates (103) are connected by a gate- via (104) to one of the power rails (101) and one or more isolation gates (103) of a second set of isolation gates (103) are connected by a gate- via (104) to the other one of the power rails (101).
14. Integrated circuit (100) according to claim 13, wherein in at least one standard cell
(200),
two of the isolation gates (103) are arranged and configured to electrically isolate a first region (l02a) of a diffusion layer (102) in the standard cell (200) from a second region (l02b) of the diffusion layer (102) in a first neighboring standard cell (200) adjacent the first edge and from a third region (l02c) of the diffusion layer (102) in a second neighboring standard cell (200) adjacent the second edge.
15. Integrated circuit (100) according to one of the claims 1 to 14, comprising
at least one active gate (303) defining a transistor, and
at least two local interconnects (300) defining respectively a source and a drain of the transistor.
PCT/EP2018/080402 2018-11-07 2018-11-07 Integrated circuit and standard cell thereof WO2020094220A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021254910A1 (en) 2020-06-16 2021-12-23 Saint-Gobain Glass France Composite pane

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040213029A1 (en) * 2003-04-23 2004-10-28 Matsushita Electric Industrial Co., Ltd. Semiconductor memory and semiconductor integrated circuit
US20080283871A1 (en) * 2007-05-15 2008-11-20 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
US20100059825A1 (en) * 2008-09-10 2010-03-11 Gregory Munson Yeric Integrated circuit and a method of making an integrated circuit to provide a gate contact over a diffusion region
US20160336183A1 (en) * 2015-05-14 2016-11-17 Globalfoundries Inc. Methods, apparatus and system for fabricating finfet devices using continuous active area design
US20180012887A1 (en) * 2016-07-06 2018-01-11 Globalfoundries Inc. Method and apparatus for placing a gate contact inside an active region of a semiconductor
US20180102364A1 (en) * 2016-10-06 2018-04-12 Samsung Electronics Co., Ltd. Integrated circuit devices and method of manufacturing the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5531848B2 (en) * 2010-08-06 2014-06-25 富士通セミコンダクター株式会社 Semiconductor device, semiconductor integrated circuit device, SRAM, and method for manufacturing Dt-MOS transistor
US9024418B2 (en) * 2013-03-14 2015-05-05 Qualcomm Incorporated Local interconnect structures for high density
US9824970B1 (en) * 2016-06-27 2017-11-21 Globalfoundries Inc. Methods that use at least a dual damascene process and, optionally, a single damascene process to form interconnects with hybrid metallization and the resulting structures

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040213029A1 (en) * 2003-04-23 2004-10-28 Matsushita Electric Industrial Co., Ltd. Semiconductor memory and semiconductor integrated circuit
US20080283871A1 (en) * 2007-05-15 2008-11-20 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
US20100059825A1 (en) * 2008-09-10 2010-03-11 Gregory Munson Yeric Integrated circuit and a method of making an integrated circuit to provide a gate contact over a diffusion region
US20160336183A1 (en) * 2015-05-14 2016-11-17 Globalfoundries Inc. Methods, apparatus and system for fabricating finfet devices using continuous active area design
US20180012887A1 (en) * 2016-07-06 2018-01-11 Globalfoundries Inc. Method and apparatus for placing a gate contact inside an active region of a semiconductor
US20180102364A1 (en) * 2016-10-06 2018-04-12 Samsung Electronics Co., Ltd. Integrated circuit devices and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021254910A1 (en) 2020-06-16 2021-12-23 Saint-Gobain Glass France Composite pane
DE202021004150U1 (en) 2020-06-16 2022-10-24 Saint-Gobain Glass France compound pane

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